DAGCombiner.cpp revision b77ea550467091e8840d06886dc068f62e9e1c99
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Nate Begeman and is distributed under the 6// University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// FIXME: Missing folds 14// sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into 15// a sequence of multiplies, shifts, and adds. This should be controlled by 16// some kind of hint from the target that int div is expensive. 17// various folds of mulh[s,u] by constants such as -1, powers of 2, etc. 18// 19// FIXME: select C, pow2, pow2 -> something smart 20// FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z) 21// FIXME: Dead stores -> nuke 22// FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!) 23// FIXME: mul (x, const) -> shifts + adds 24// FIXME: undef values 25// FIXME: divide by zero is currently left unfolded. do we want to turn this 26// into an undef? 27// FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false 28// 29//===----------------------------------------------------------------------===// 30 31#define DEBUG_TYPE "dagcombine" 32#include "llvm/CodeGen/SelectionDAG.h" 33#include "llvm/Analysis/AliasAnalysis.h" 34#include "llvm/Target/TargetData.h" 35#include "llvm/Target/TargetLowering.h" 36#include "llvm/Target/TargetMachine.h" 37#include "llvm/Target/TargetOptions.h" 38#include "llvm/ADT/SmallPtrSet.h" 39#include "llvm/ADT/Statistic.h" 40#include "llvm/Support/Compiler.h" 41#include "llvm/Support/CommandLine.h" 42#include "llvm/Support/Debug.h" 43#include "llvm/Support/MathExtras.h" 44#include <algorithm> 45using namespace llvm; 46 47STATISTIC(NodesCombined , "Number of dag nodes combined"); 48STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 49STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 50 51namespace { 52#ifndef NDEBUG 53 static cl::opt<bool> 54 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 55 cl::desc("Pop up a window to show dags before the first " 56 "dag combine pass")); 57 static cl::opt<bool> 58 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 59 cl::desc("Pop up a window to show dags before the second " 60 "dag combine pass")); 61#else 62 static const bool ViewDAGCombine1 = false; 63 static const bool ViewDAGCombine2 = false; 64#endif 65 66 static cl::opt<bool> 67 CombinerAA("combiner-alias-analysis", cl::Hidden, 68 cl::desc("Turn on alias analysis during testing")); 69 70 static cl::opt<bool> 71 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 72 cl::desc("Include global information in alias analysis")); 73 74//------------------------------ DAGCombiner ---------------------------------// 75 76 class VISIBILITY_HIDDEN DAGCombiner { 77 SelectionDAG &DAG; 78 TargetLowering &TLI; 79 bool AfterLegalize; 80 81 // Worklist of all of the nodes that need to be simplified. 82 std::vector<SDNode*> WorkList; 83 84 // AA - Used for DAG load/store alias analysis. 85 AliasAnalysis &AA; 86 87 /// AddUsersToWorkList - When an instruction is simplified, add all users of 88 /// the instruction to the work lists because they might get more simplified 89 /// now. 90 /// 91 void AddUsersToWorkList(SDNode *N) { 92 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 93 UI != UE; ++UI) 94 AddToWorkList(*UI); 95 } 96 97 /// removeFromWorkList - remove all instances of N from the worklist. 98 /// 99 void removeFromWorkList(SDNode *N) { 100 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 101 WorkList.end()); 102 } 103 104 /// visit - call the node-specific routine that knows how to fold each 105 /// particular type of node. 106 SDOperand visit(SDNode *N); 107 108 public: 109 /// AddToWorkList - Add to the work list making sure it's instance is at the 110 /// the back (next to be processed.) 111 void AddToWorkList(SDNode *N) { 112 removeFromWorkList(N); 113 WorkList.push_back(N); 114 } 115 116 SDOperand CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo, 117 bool AddTo = true) { 118 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 119 ++NodesCombined; 120 DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG)); 121 DOUT << "\nWith: "; DEBUG(To[0].Val->dump(&DAG)); 122 DOUT << " and " << NumTo-1 << " other values\n"; 123 std::vector<SDNode*> NowDead; 124 DAG.ReplaceAllUsesWith(N, To, &NowDead); 125 126 if (AddTo) { 127 // Push the new nodes and any users onto the worklist 128 for (unsigned i = 0, e = NumTo; i != e; ++i) { 129 AddToWorkList(To[i].Val); 130 AddUsersToWorkList(To[i].Val); 131 } 132 } 133 134 // Nodes can be reintroduced into the worklist. Make sure we do not 135 // process a node that has been replaced. 136 removeFromWorkList(N); 137 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 138 removeFromWorkList(NowDead[i]); 139 140 // Finally, since the node is now dead, remove it from the graph. 141 DAG.DeleteNode(N); 142 return SDOperand(N, 0); 143 } 144 145 SDOperand CombineTo(SDNode *N, SDOperand Res, bool AddTo = true) { 146 return CombineTo(N, &Res, 1, AddTo); 147 } 148 149 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1, 150 bool AddTo = true) { 151 SDOperand To[] = { Res0, Res1 }; 152 return CombineTo(N, To, 2, AddTo); 153 } 154 private: 155 156 /// SimplifyDemandedBits - Check the specified integer node value to see if 157 /// it can be simplified or if things it uses can be simplified by bit 158 /// propagation. If so, return true. 159 bool SimplifyDemandedBits(SDOperand Op, uint64_t Demanded = ~0ULL) { 160 TargetLowering::TargetLoweringOpt TLO(DAG); 161 uint64_t KnownZero, KnownOne; 162 Demanded &= MVT::getIntVTBitMask(Op.getValueType()); 163 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 164 return false; 165 166 // Revisit the node. 167 AddToWorkList(Op.Val); 168 169 // Replace the old value with the new one. 170 ++NodesCombined; 171 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.Val->dump(&DAG)); 172 DOUT << "\nWith: "; DEBUG(TLO.New.Val->dump(&DAG)); 173 DOUT << '\n'; 174 175 std::vector<SDNode*> NowDead; 176 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, NowDead); 177 178 // Push the new node and any (possibly new) users onto the worklist. 179 AddToWorkList(TLO.New.Val); 180 AddUsersToWorkList(TLO.New.Val); 181 182 // Nodes can end up on the worklist more than once. Make sure we do 183 // not process a node that has been replaced. 184 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 185 removeFromWorkList(NowDead[i]); 186 187 // Finally, if the node is now dead, remove it from the graph. The node 188 // may not be dead if the replacement process recursively simplified to 189 // something else needing this node. 190 if (TLO.Old.Val->use_empty()) { 191 removeFromWorkList(TLO.Old.Val); 192 193 // If the operands of this node are only used by the node, they will now 194 // be dead. Make sure to visit them first to delete dead nodes early. 195 for (unsigned i = 0, e = TLO.Old.Val->getNumOperands(); i != e; ++i) 196 if (TLO.Old.Val->getOperand(i).Val->hasOneUse()) 197 AddToWorkList(TLO.Old.Val->getOperand(i).Val); 198 199 DAG.DeleteNode(TLO.Old.Val); 200 } 201 return true; 202 } 203 204 bool CombineToPreIndexedLoadStore(SDNode *N); 205 bool CombineToPostIndexedLoadStore(SDNode *N); 206 207 208 /// combine - call the node-specific routine that knows how to fold each 209 /// particular type of node. If that doesn't do anything, try the 210 /// target-specific DAG combines. 211 SDOperand combine(SDNode *N); 212 213 // Visitation implementation - Implement dag node combining for different 214 // node types. The semantics are as follows: 215 // Return Value: 216 // SDOperand.Val == 0 - No change was made 217 // SDOperand.Val == N - N was replaced, is dead, and is already handled. 218 // otherwise - N should be replaced by the returned Operand. 219 // 220 SDOperand visitTokenFactor(SDNode *N); 221 SDOperand visitADD(SDNode *N); 222 SDOperand visitSUB(SDNode *N); 223 SDOperand visitADDC(SDNode *N); 224 SDOperand visitADDE(SDNode *N); 225 SDOperand visitMUL(SDNode *N); 226 SDOperand visitSDIV(SDNode *N); 227 SDOperand visitUDIV(SDNode *N); 228 SDOperand visitSREM(SDNode *N); 229 SDOperand visitUREM(SDNode *N); 230 SDOperand visitMULHU(SDNode *N); 231 SDOperand visitMULHS(SDNode *N); 232 SDOperand visitSMUL_LOHI(SDNode *N); 233 SDOperand visitUMUL_LOHI(SDNode *N); 234 SDOperand visitSDIVREM(SDNode *N); 235 SDOperand visitUDIVREM(SDNode *N); 236 SDOperand visitAND(SDNode *N); 237 SDOperand visitOR(SDNode *N); 238 SDOperand visitXOR(SDNode *N); 239 SDOperand SimplifyVBinOp(SDNode *N); 240 SDOperand visitSHL(SDNode *N); 241 SDOperand visitSRA(SDNode *N); 242 SDOperand visitSRL(SDNode *N); 243 SDOperand visitCTLZ(SDNode *N); 244 SDOperand visitCTTZ(SDNode *N); 245 SDOperand visitCTPOP(SDNode *N); 246 SDOperand visitSELECT(SDNode *N); 247 SDOperand visitSELECT_CC(SDNode *N); 248 SDOperand visitSETCC(SDNode *N); 249 SDOperand visitSIGN_EXTEND(SDNode *N); 250 SDOperand visitZERO_EXTEND(SDNode *N); 251 SDOperand visitANY_EXTEND(SDNode *N); 252 SDOperand visitSIGN_EXTEND_INREG(SDNode *N); 253 SDOperand visitTRUNCATE(SDNode *N); 254 SDOperand visitBIT_CONVERT(SDNode *N); 255 SDOperand visitFADD(SDNode *N); 256 SDOperand visitFSUB(SDNode *N); 257 SDOperand visitFMUL(SDNode *N); 258 SDOperand visitFDIV(SDNode *N); 259 SDOperand visitFREM(SDNode *N); 260 SDOperand visitFCOPYSIGN(SDNode *N); 261 SDOperand visitSINT_TO_FP(SDNode *N); 262 SDOperand visitUINT_TO_FP(SDNode *N); 263 SDOperand visitFP_TO_SINT(SDNode *N); 264 SDOperand visitFP_TO_UINT(SDNode *N); 265 SDOperand visitFP_ROUND(SDNode *N); 266 SDOperand visitFP_ROUND_INREG(SDNode *N); 267 SDOperand visitFP_EXTEND(SDNode *N); 268 SDOperand visitFNEG(SDNode *N); 269 SDOperand visitFABS(SDNode *N); 270 SDOperand visitBRCOND(SDNode *N); 271 SDOperand visitBR_CC(SDNode *N); 272 SDOperand visitLOAD(SDNode *N); 273 SDOperand visitSTORE(SDNode *N); 274 SDOperand visitINSERT_VECTOR_ELT(SDNode *N); 275 SDOperand visitEXTRACT_VECTOR_ELT(SDNode *N); 276 SDOperand visitBUILD_VECTOR(SDNode *N); 277 SDOperand visitCONCAT_VECTORS(SDNode *N); 278 SDOperand visitVECTOR_SHUFFLE(SDNode *N); 279 280 SDOperand XformToShuffleWithZero(SDNode *N); 281 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS); 282 283 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS); 284 SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N); 285 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2); 286 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2, 287 SDOperand N3, ISD::CondCode CC, 288 bool NotExtCompare = false); 289 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, 290 ISD::CondCode Cond, bool foldBooleans = true); 291 bool SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, unsigned HiOp); 292 SDOperand ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT::ValueType); 293 SDOperand BuildSDIV(SDNode *N); 294 SDOperand BuildUDIV(SDNode *N); 295 SDNode *MatchRotate(SDOperand LHS, SDOperand RHS); 296 SDOperand ReduceLoadWidth(SDNode *N); 297 298 SDOperand GetDemandedBits(SDOperand V, uint64_t Mask); 299 300 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 301 /// looking for aliasing nodes and adding them to the Aliases vector. 302 void GatherAllAliases(SDNode *N, SDOperand OriginalChain, 303 SmallVector<SDOperand, 8> &Aliases); 304 305 /// isAlias - Return true if there is any possibility that the two addresses 306 /// overlap. 307 bool isAlias(SDOperand Ptr1, int64_t Size1, 308 const Value *SrcValue1, int SrcValueOffset1, 309 SDOperand Ptr2, int64_t Size2, 310 const Value *SrcValue2, int SrcValueOffset2); 311 312 /// FindAliasInfo - Extracts the relevant alias information from the memory 313 /// node. Returns true if the operand was a load. 314 bool FindAliasInfo(SDNode *N, 315 SDOperand &Ptr, int64_t &Size, 316 const Value *&SrcValue, int &SrcValueOffset); 317 318 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 319 /// looking for a better chain (aliasing node.) 320 SDOperand FindBetterChain(SDNode *N, SDOperand Chain); 321 322public: 323 DAGCombiner(SelectionDAG &D, AliasAnalysis &A) 324 : DAG(D), 325 TLI(D.getTargetLoweringInfo()), 326 AfterLegalize(false), 327 AA(A) {} 328 329 /// Run - runs the dag combiner on all nodes in the work list 330 void Run(bool RunningAfterLegalize); 331 }; 332} 333 334//===----------------------------------------------------------------------===// 335// TargetLowering::DAGCombinerInfo implementation 336//===----------------------------------------------------------------------===// 337 338void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 339 ((DAGCombiner*)DC)->AddToWorkList(N); 340} 341 342SDOperand TargetLowering::DAGCombinerInfo:: 343CombineTo(SDNode *N, const std::vector<SDOperand> &To) { 344 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size()); 345} 346 347SDOperand TargetLowering::DAGCombinerInfo:: 348CombineTo(SDNode *N, SDOperand Res) { 349 return ((DAGCombiner*)DC)->CombineTo(N, Res); 350} 351 352 353SDOperand TargetLowering::DAGCombinerInfo:: 354CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) { 355 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1); 356} 357 358 359//===----------------------------------------------------------------------===// 360// Helper Functions 361//===----------------------------------------------------------------------===// 362 363/// isNegatibleForFree - Return 1 if we can compute the negated form of the 364/// specified expression for the same cost as the expression itself, or 2 if we 365/// can compute the negated form more cheaply than the expression itself. 366static char isNegatibleForFree(SDOperand Op, unsigned Depth = 0) { 367 // fneg is removable even if it has multiple uses. 368 if (Op.getOpcode() == ISD::FNEG) return 2; 369 370 // Don't allow anything with multiple uses. 371 if (!Op.hasOneUse()) return 0; 372 373 // Don't recurse exponentially. 374 if (Depth > 6) return 0; 375 376 switch (Op.getOpcode()) { 377 default: return false; 378 case ISD::ConstantFP: 379 return 1; 380 case ISD::FADD: 381 // FIXME: determine better conditions for this xform. 382 if (!UnsafeFPMath) return 0; 383 384 // -(A+B) -> -A - B 385 if (char V = isNegatibleForFree(Op.getOperand(0), Depth+1)) 386 return V; 387 // -(A+B) -> -B - A 388 return isNegatibleForFree(Op.getOperand(1), Depth+1); 389 case ISD::FSUB: 390 // We can't turn -(A-B) into B-A when we honor signed zeros. 391 if (!UnsafeFPMath) return 0; 392 393 // -(A-B) -> B-A 394 return 1; 395 396 case ISD::FMUL: 397 case ISD::FDIV: 398 if (HonorSignDependentRoundingFPMath()) return 0; 399 400 // -(X*Y) -> (-X * Y) or (X*-Y) 401 if (char V = isNegatibleForFree(Op.getOperand(0), Depth+1)) 402 return V; 403 404 return isNegatibleForFree(Op.getOperand(1), Depth+1); 405 406 case ISD::FP_EXTEND: 407 case ISD::FP_ROUND: 408 case ISD::FSIN: 409 return isNegatibleForFree(Op.getOperand(0), Depth+1); 410 } 411} 412 413/// GetNegatedExpression - If isNegatibleForFree returns true, this function 414/// returns the newly negated expression. 415static SDOperand GetNegatedExpression(SDOperand Op, SelectionDAG &DAG, 416 unsigned Depth = 0) { 417 // fneg is removable even if it has multiple uses. 418 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 419 420 // Don't allow anything with multiple uses. 421 assert(Op.hasOneUse() && "Unknown reuse!"); 422 423 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 424 switch (Op.getOpcode()) { 425 default: assert(0 && "Unknown code"); 426 case ISD::ConstantFP: { 427 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 428 V.changeSign(); 429 return DAG.getConstantFP(V, Op.getValueType()); 430 } 431 case ISD::FADD: 432 // FIXME: determine better conditions for this xform. 433 assert(UnsafeFPMath); 434 435 // -(A+B) -> -A - B 436 if (isNegatibleForFree(Op.getOperand(0), Depth+1)) 437 return DAG.getNode(ISD::FSUB, Op.getValueType(), 438 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1), 439 Op.getOperand(1)); 440 // -(A+B) -> -B - A 441 return DAG.getNode(ISD::FSUB, Op.getValueType(), 442 GetNegatedExpression(Op.getOperand(1), DAG, Depth+1), 443 Op.getOperand(0)); 444 case ISD::FSUB: 445 // We can't turn -(A-B) into B-A when we honor signed zeros. 446 assert(UnsafeFPMath); 447 448 // -(0-B) -> B 449 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 450 if (N0CFP->getValueAPF().isZero()) 451 return Op.getOperand(1); 452 453 // -(A-B) -> B-A 454 return DAG.getNode(ISD::FSUB, Op.getValueType(), Op.getOperand(1), 455 Op.getOperand(0)); 456 457 case ISD::FMUL: 458 case ISD::FDIV: 459 assert(!HonorSignDependentRoundingFPMath()); 460 461 // -(X*Y) -> -X * Y 462 if (isNegatibleForFree(Op.getOperand(0), Depth+1)) 463 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 464 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1), 465 Op.getOperand(1)); 466 467 // -(X*Y) -> X * -Y 468 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 469 Op.getOperand(0), 470 GetNegatedExpression(Op.getOperand(1), DAG, Depth+1)); 471 472 case ISD::FP_EXTEND: 473 case ISD::FP_ROUND: 474 case ISD::FSIN: 475 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 476 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1)); 477 } 478} 479 480 481// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 482// that selects between the values 1 and 0, making it equivalent to a setcc. 483// Also, set the incoming LHS, RHS, and CC references to the appropriate 484// nodes based on the type of node we are checking. This simplifies life a 485// bit for the callers. 486static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS, 487 SDOperand &CC) { 488 if (N.getOpcode() == ISD::SETCC) { 489 LHS = N.getOperand(0); 490 RHS = N.getOperand(1); 491 CC = N.getOperand(2); 492 return true; 493 } 494 if (N.getOpcode() == ISD::SELECT_CC && 495 N.getOperand(2).getOpcode() == ISD::Constant && 496 N.getOperand(3).getOpcode() == ISD::Constant && 497 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 && 498 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 499 LHS = N.getOperand(0); 500 RHS = N.getOperand(1); 501 CC = N.getOperand(4); 502 return true; 503 } 504 return false; 505} 506 507// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 508// one use. If this is true, it allows the users to invert the operation for 509// free when it is profitable to do so. 510static bool isOneUseSetCC(SDOperand N) { 511 SDOperand N0, N1, N2; 512 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse()) 513 return true; 514 return false; 515} 516 517SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){ 518 MVT::ValueType VT = N0.getValueType(); 519 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 520 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 521 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 522 if (isa<ConstantSDNode>(N1)) { 523 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1); 524 AddToWorkList(OpNode.Val); 525 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0)); 526 } else if (N0.hasOneUse()) { 527 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1); 528 AddToWorkList(OpNode.Val); 529 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1)); 530 } 531 } 532 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 533 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 534 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 535 if (isa<ConstantSDNode>(N0)) { 536 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0); 537 AddToWorkList(OpNode.Val); 538 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0)); 539 } else if (N1.hasOneUse()) { 540 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0); 541 AddToWorkList(OpNode.Val); 542 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1)); 543 } 544 } 545 return SDOperand(); 546} 547 548//===----------------------------------------------------------------------===// 549// Main DAG Combiner implementation 550//===----------------------------------------------------------------------===// 551 552void DAGCombiner::Run(bool RunningAfterLegalize) { 553 // set the instance variable, so that the various visit routines may use it. 554 AfterLegalize = RunningAfterLegalize; 555 556 // Add all the dag nodes to the worklist. 557 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 558 E = DAG.allnodes_end(); I != E; ++I) 559 WorkList.push_back(I); 560 561 // Create a dummy node (which is not added to allnodes), that adds a reference 562 // to the root node, preventing it from being deleted, and tracking any 563 // changes of the root. 564 HandleSDNode Dummy(DAG.getRoot()); 565 566 // The root of the dag may dangle to deleted nodes until the dag combiner is 567 // done. Set it to null to avoid confusion. 568 DAG.setRoot(SDOperand()); 569 570 // while the worklist isn't empty, inspect the node on the end of it and 571 // try and combine it. 572 while (!WorkList.empty()) { 573 SDNode *N = WorkList.back(); 574 WorkList.pop_back(); 575 576 // If N has no uses, it is dead. Make sure to revisit all N's operands once 577 // N is deleted from the DAG, since they too may now be dead or may have a 578 // reduced number of uses, allowing other xforms. 579 if (N->use_empty() && N != &Dummy) { 580 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 581 AddToWorkList(N->getOperand(i).Val); 582 583 DAG.DeleteNode(N); 584 continue; 585 } 586 587 SDOperand RV = combine(N); 588 589 if (RV.Val) { 590 ++NodesCombined; 591 // If we get back the same node we passed in, rather than a new node or 592 // zero, we know that the node must have defined multiple values and 593 // CombineTo was used. Since CombineTo takes care of the worklist 594 // mechanics for us, we have no work to do in this case. 595 if (RV.Val != N) { 596 assert(N->getOpcode() != ISD::DELETED_NODE && 597 RV.Val->getOpcode() != ISD::DELETED_NODE && 598 "Node was deleted but visit returned new node!"); 599 600 DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG)); 601 DOUT << "\nWith: "; DEBUG(RV.Val->dump(&DAG)); 602 DOUT << '\n'; 603 std::vector<SDNode*> NowDead; 604 if (N->getNumValues() == RV.Val->getNumValues()) 605 DAG.ReplaceAllUsesWith(N, RV.Val, &NowDead); 606 else { 607 assert(N->getValueType(0) == RV.getValueType() && "Type mismatch"); 608 SDOperand OpV = RV; 609 DAG.ReplaceAllUsesWith(N, &OpV, &NowDead); 610 } 611 612 // Push the new node and any users onto the worklist 613 AddToWorkList(RV.Val); 614 AddUsersToWorkList(RV.Val); 615 616 // Nodes can be reintroduced into the worklist. Make sure we do not 617 // process a node that has been replaced. 618 removeFromWorkList(N); 619 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 620 removeFromWorkList(NowDead[i]); 621 622 // Finally, since the node is now dead, remove it from the graph. 623 DAG.DeleteNode(N); 624 } 625 } 626 } 627 628 // If the root changed (e.g. it was a dead load, update the root). 629 DAG.setRoot(Dummy.getValue()); 630} 631 632SDOperand DAGCombiner::visit(SDNode *N) { 633 switch(N->getOpcode()) { 634 default: break; 635 case ISD::TokenFactor: return visitTokenFactor(N); 636 case ISD::ADD: return visitADD(N); 637 case ISD::SUB: return visitSUB(N); 638 case ISD::ADDC: return visitADDC(N); 639 case ISD::ADDE: return visitADDE(N); 640 case ISD::MUL: return visitMUL(N); 641 case ISD::SDIV: return visitSDIV(N); 642 case ISD::UDIV: return visitUDIV(N); 643 case ISD::SREM: return visitSREM(N); 644 case ISD::UREM: return visitUREM(N); 645 case ISD::MULHU: return visitMULHU(N); 646 case ISD::MULHS: return visitMULHS(N); 647 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 648 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 649 case ISD::SDIVREM: return visitSDIVREM(N); 650 case ISD::UDIVREM: return visitUDIVREM(N); 651 case ISD::AND: return visitAND(N); 652 case ISD::OR: return visitOR(N); 653 case ISD::XOR: return visitXOR(N); 654 case ISD::SHL: return visitSHL(N); 655 case ISD::SRA: return visitSRA(N); 656 case ISD::SRL: return visitSRL(N); 657 case ISD::CTLZ: return visitCTLZ(N); 658 case ISD::CTTZ: return visitCTTZ(N); 659 case ISD::CTPOP: return visitCTPOP(N); 660 case ISD::SELECT: return visitSELECT(N); 661 case ISD::SELECT_CC: return visitSELECT_CC(N); 662 case ISD::SETCC: return visitSETCC(N); 663 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 664 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 665 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 666 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 667 case ISD::TRUNCATE: return visitTRUNCATE(N); 668 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 669 case ISD::FADD: return visitFADD(N); 670 case ISD::FSUB: return visitFSUB(N); 671 case ISD::FMUL: return visitFMUL(N); 672 case ISD::FDIV: return visitFDIV(N); 673 case ISD::FREM: return visitFREM(N); 674 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 675 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 676 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 677 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 678 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 679 case ISD::FP_ROUND: return visitFP_ROUND(N); 680 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 681 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 682 case ISD::FNEG: return visitFNEG(N); 683 case ISD::FABS: return visitFABS(N); 684 case ISD::BRCOND: return visitBRCOND(N); 685 case ISD::BR_CC: return visitBR_CC(N); 686 case ISD::LOAD: return visitLOAD(N); 687 case ISD::STORE: return visitSTORE(N); 688 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 689 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 690 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 691 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 692 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 693 } 694 return SDOperand(); 695} 696 697SDOperand DAGCombiner::combine(SDNode *N) { 698 699 SDOperand RV = visit(N); 700 701 // If nothing happened, try a target-specific DAG combine. 702 if (RV.Val == 0) { 703 assert(N->getOpcode() != ISD::DELETED_NODE && 704 "Node was deleted but visit returned NULL!"); 705 706 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 707 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 708 709 // Expose the DAG combiner to the target combiner impls. 710 TargetLowering::DAGCombinerInfo 711 DagCombineInfo(DAG, !AfterLegalize, false, this); 712 713 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 714 } 715 } 716 717 return RV; 718} 719 720/// getInputChainForNode - Given a node, return its input chain if it has one, 721/// otherwise return a null sd operand. 722static SDOperand getInputChainForNode(SDNode *N) { 723 if (unsigned NumOps = N->getNumOperands()) { 724 if (N->getOperand(0).getValueType() == MVT::Other) 725 return N->getOperand(0); 726 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 727 return N->getOperand(NumOps-1); 728 for (unsigned i = 1; i < NumOps-1; ++i) 729 if (N->getOperand(i).getValueType() == MVT::Other) 730 return N->getOperand(i); 731 } 732 return SDOperand(0, 0); 733} 734 735SDOperand DAGCombiner::visitTokenFactor(SDNode *N) { 736 // If N has two operands, where one has an input chain equal to the other, 737 // the 'other' chain is redundant. 738 if (N->getNumOperands() == 2) { 739 if (getInputChainForNode(N->getOperand(0).Val) == N->getOperand(1)) 740 return N->getOperand(0); 741 if (getInputChainForNode(N->getOperand(1).Val) == N->getOperand(0)) 742 return N->getOperand(1); 743 } 744 745 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 746 SmallVector<SDOperand, 8> Ops; // Ops for replacing token factor. 747 SmallPtrSet<SDNode*, 16> SeenOps; 748 bool Changed = false; // If we should replace this token factor. 749 750 // Start out with this token factor. 751 TFs.push_back(N); 752 753 // Iterate through token factors. The TFs grows when new token factors are 754 // encountered. 755 for (unsigned i = 0; i < TFs.size(); ++i) { 756 SDNode *TF = TFs[i]; 757 758 // Check each of the operands. 759 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 760 SDOperand Op = TF->getOperand(i); 761 762 switch (Op.getOpcode()) { 763 case ISD::EntryToken: 764 // Entry tokens don't need to be added to the list. They are 765 // rededundant. 766 Changed = true; 767 break; 768 769 case ISD::TokenFactor: 770 if ((CombinerAA || Op.hasOneUse()) && 771 std::find(TFs.begin(), TFs.end(), Op.Val) == TFs.end()) { 772 // Queue up for processing. 773 TFs.push_back(Op.Val); 774 // Clean up in case the token factor is removed. 775 AddToWorkList(Op.Val); 776 Changed = true; 777 break; 778 } 779 // Fall thru 780 781 default: 782 // Only add if it isn't already in the list. 783 if (SeenOps.insert(Op.Val)) 784 Ops.push_back(Op); 785 else 786 Changed = true; 787 break; 788 } 789 } 790 } 791 792 SDOperand Result; 793 794 // If we've change things around then replace token factor. 795 if (Changed) { 796 if (Ops.size() == 0) { 797 // The entry token is the only possible outcome. 798 Result = DAG.getEntryNode(); 799 } else { 800 // New and improved token factor. 801 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size()); 802 } 803 804 // Don't add users to work list. 805 return CombineTo(N, Result, false); 806 } 807 808 return Result; 809} 810 811static 812SDOperand combineShlAddConstant(SDOperand N0, SDOperand N1, SelectionDAG &DAG) { 813 MVT::ValueType VT = N0.getValueType(); 814 SDOperand N00 = N0.getOperand(0); 815 SDOperand N01 = N0.getOperand(1); 816 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 817 if (N01C && N00.getOpcode() == ISD::ADD && N00.Val->hasOneUse() && 818 isa<ConstantSDNode>(N00.getOperand(1))) { 819 N0 = DAG.getNode(ISD::ADD, VT, 820 DAG.getNode(ISD::SHL, VT, N00.getOperand(0), N01), 821 DAG.getNode(ISD::SHL, VT, N00.getOperand(1), N01)); 822 return DAG.getNode(ISD::ADD, VT, N0, N1); 823 } 824 return SDOperand(); 825} 826 827static 828SDOperand combineSelectAndUse(SDNode *N, SDOperand Slct, SDOperand OtherOp, 829 SelectionDAG &DAG) { 830 MVT::ValueType VT = N->getValueType(0); 831 unsigned Opc = N->getOpcode(); 832 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC; 833 SDOperand LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1); 834 SDOperand RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2); 835 ISD::CondCode CC = ISD::SETCC_INVALID; 836 if (isSlctCC) 837 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get(); 838 else { 839 SDOperand CCOp = Slct.getOperand(0); 840 if (CCOp.getOpcode() == ISD::SETCC) 841 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get(); 842 } 843 844 bool DoXform = false; 845 bool InvCC = false; 846 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) && 847 "Bad input!"); 848 if (LHS.getOpcode() == ISD::Constant && 849 cast<ConstantSDNode>(LHS)->isNullValue()) 850 DoXform = true; 851 else if (CC != ISD::SETCC_INVALID && 852 RHS.getOpcode() == ISD::Constant && 853 cast<ConstantSDNode>(RHS)->isNullValue()) { 854 std::swap(LHS, RHS); 855 bool isInt = MVT::isInteger(isSlctCC ? Slct.getOperand(0).getValueType() 856 : Slct.getOperand(0).getOperand(0).getValueType()); 857 CC = ISD::getSetCCInverse(CC, isInt); 858 DoXform = true; 859 InvCC = true; 860 } 861 862 if (DoXform) { 863 SDOperand Result = DAG.getNode(Opc, VT, OtherOp, RHS); 864 if (isSlctCC) 865 return DAG.getSelectCC(OtherOp, Result, 866 Slct.getOperand(0), Slct.getOperand(1), CC); 867 SDOperand CCOp = Slct.getOperand(0); 868 if (InvCC) 869 CCOp = DAG.getSetCC(CCOp.getValueType(), CCOp.getOperand(0), 870 CCOp.getOperand(1), CC); 871 return DAG.getNode(ISD::SELECT, VT, CCOp, OtherOp, Result); 872 } 873 return SDOperand(); 874} 875 876SDOperand DAGCombiner::visitADD(SDNode *N) { 877 SDOperand N0 = N->getOperand(0); 878 SDOperand N1 = N->getOperand(1); 879 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 880 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 881 MVT::ValueType VT = N0.getValueType(); 882 883 // fold vector ops 884 if (MVT::isVector(VT)) { 885 SDOperand FoldedVOp = SimplifyVBinOp(N); 886 if (FoldedVOp.Val) return FoldedVOp; 887 } 888 889 // fold (add x, undef) -> undef 890 if (N0.getOpcode() == ISD::UNDEF) 891 return N0; 892 if (N1.getOpcode() == ISD::UNDEF) 893 return N1; 894 // fold (add c1, c2) -> c1+c2 895 if (N0C && N1C) 896 return DAG.getNode(ISD::ADD, VT, N0, N1); 897 // canonicalize constant to RHS 898 if (N0C && !N1C) 899 return DAG.getNode(ISD::ADD, VT, N1, N0); 900 // fold (add x, 0) -> x 901 if (N1C && N1C->isNullValue()) 902 return N0; 903 // fold ((c1-A)+c2) -> (c1+c2)-A 904 if (N1C && N0.getOpcode() == ISD::SUB) 905 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 906 return DAG.getNode(ISD::SUB, VT, 907 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT), 908 N0.getOperand(1)); 909 // reassociate add 910 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1); 911 if (RADD.Val != 0) 912 return RADD; 913 // fold ((0-A) + B) -> B-A 914 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 915 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 916 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1)); 917 // fold (A + (0-B)) -> A-B 918 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 919 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 920 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1)); 921 // fold (A+(B-A)) -> B 922 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 923 return N1.getOperand(0); 924 925 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0))) 926 return SDOperand(N, 0); 927 928 // fold (a+b) -> (a|b) iff a and b share no bits. 929 if (MVT::isInteger(VT) && !MVT::isVector(VT)) { 930 uint64_t LHSZero, LHSOne; 931 uint64_t RHSZero, RHSOne; 932 uint64_t Mask = MVT::getIntVTBitMask(VT); 933 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 934 if (LHSZero) { 935 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 936 937 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 938 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 939 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 940 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 941 return DAG.getNode(ISD::OR, VT, N0, N1); 942 } 943 } 944 945 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 946 if (N0.getOpcode() == ISD::SHL && N0.Val->hasOneUse()) { 947 SDOperand Result = combineShlAddConstant(N0, N1, DAG); 948 if (Result.Val) return Result; 949 } 950 if (N1.getOpcode() == ISD::SHL && N1.Val->hasOneUse()) { 951 SDOperand Result = combineShlAddConstant(N1, N0, DAG); 952 if (Result.Val) return Result; 953 } 954 955 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c)) 956 if (N0.getOpcode() == ISD::SELECT && N0.Val->hasOneUse()) { 957 SDOperand Result = combineSelectAndUse(N, N0, N1, DAG); 958 if (Result.Val) return Result; 959 } 960 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) { 961 SDOperand Result = combineSelectAndUse(N, N1, N0, DAG); 962 if (Result.Val) return Result; 963 } 964 965 return SDOperand(); 966} 967 968SDOperand DAGCombiner::visitADDC(SDNode *N) { 969 SDOperand N0 = N->getOperand(0); 970 SDOperand N1 = N->getOperand(1); 971 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 972 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 973 MVT::ValueType VT = N0.getValueType(); 974 975 // If the flag result is dead, turn this into an ADD. 976 if (N->hasNUsesOfValue(0, 1)) 977 return CombineTo(N, DAG.getNode(ISD::ADD, VT, N1, N0), 978 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 979 980 // canonicalize constant to RHS. 981 if (N0C && !N1C) { 982 SDOperand Ops[] = { N1, N0 }; 983 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2); 984 } 985 986 // fold (addc x, 0) -> x + no carry out 987 if (N1C && N1C->isNullValue()) 988 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 989 990 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 991 uint64_t LHSZero, LHSOne; 992 uint64_t RHSZero, RHSOne; 993 uint64_t Mask = MVT::getIntVTBitMask(VT); 994 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 995 if (LHSZero) { 996 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 997 998 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 999 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1000 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1001 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1002 return CombineTo(N, DAG.getNode(ISD::OR, VT, N0, N1), 1003 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 1004 } 1005 1006 return SDOperand(); 1007} 1008 1009SDOperand DAGCombiner::visitADDE(SDNode *N) { 1010 SDOperand N0 = N->getOperand(0); 1011 SDOperand N1 = N->getOperand(1); 1012 SDOperand CarryIn = N->getOperand(2); 1013 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1014 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1015 //MVT::ValueType VT = N0.getValueType(); 1016 1017 // canonicalize constant to RHS 1018 if (N0C && !N1C) { 1019 SDOperand Ops[] = { N1, N0, CarryIn }; 1020 return DAG.getNode(ISD::ADDE, N->getVTList(), Ops, 3); 1021 } 1022 1023 // fold (adde x, y, false) -> (addc x, y) 1024 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) { 1025 SDOperand Ops[] = { N1, N0 }; 1026 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2); 1027 } 1028 1029 return SDOperand(); 1030} 1031 1032 1033 1034SDOperand DAGCombiner::visitSUB(SDNode *N) { 1035 SDOperand N0 = N->getOperand(0); 1036 SDOperand N1 = N->getOperand(1); 1037 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1038 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1039 MVT::ValueType VT = N0.getValueType(); 1040 1041 // fold vector ops 1042 if (MVT::isVector(VT)) { 1043 SDOperand FoldedVOp = SimplifyVBinOp(N); 1044 if (FoldedVOp.Val) return FoldedVOp; 1045 } 1046 1047 // fold (sub x, x) -> 0 1048 if (N0 == N1) 1049 return DAG.getConstant(0, N->getValueType(0)); 1050 // fold (sub c1, c2) -> c1-c2 1051 if (N0C && N1C) 1052 return DAG.getNode(ISD::SUB, VT, N0, N1); 1053 // fold (sub x, c) -> (add x, -c) 1054 if (N1C) 1055 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT)); 1056 // fold (A+B)-A -> B 1057 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1058 return N0.getOperand(1); 1059 // fold (A+B)-B -> A 1060 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1061 return N0.getOperand(0); 1062 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c)) 1063 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) { 1064 SDOperand Result = combineSelectAndUse(N, N1, N0, DAG); 1065 if (Result.Val) return Result; 1066 } 1067 // If either operand of a sub is undef, the result is undef 1068 if (N0.getOpcode() == ISD::UNDEF) 1069 return N0; 1070 if (N1.getOpcode() == ISD::UNDEF) 1071 return N1; 1072 1073 return SDOperand(); 1074} 1075 1076SDOperand DAGCombiner::visitMUL(SDNode *N) { 1077 SDOperand N0 = N->getOperand(0); 1078 SDOperand N1 = N->getOperand(1); 1079 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1080 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1081 MVT::ValueType VT = N0.getValueType(); 1082 1083 // fold vector ops 1084 if (MVT::isVector(VT)) { 1085 SDOperand FoldedVOp = SimplifyVBinOp(N); 1086 if (FoldedVOp.Val) return FoldedVOp; 1087 } 1088 1089 // fold (mul x, undef) -> 0 1090 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1091 return DAG.getConstant(0, VT); 1092 // fold (mul c1, c2) -> c1*c2 1093 if (N0C && N1C) 1094 return DAG.getNode(ISD::MUL, VT, N0, N1); 1095 // canonicalize constant to RHS 1096 if (N0C && !N1C) 1097 return DAG.getNode(ISD::MUL, VT, N1, N0); 1098 // fold (mul x, 0) -> 0 1099 if (N1C && N1C->isNullValue()) 1100 return N1; 1101 // fold (mul x, -1) -> 0-x 1102 if (N1C && N1C->isAllOnesValue()) 1103 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 1104 // fold (mul x, (1 << c)) -> x << c 1105 if (N1C && isPowerOf2_64(N1C->getValue())) 1106 return DAG.getNode(ISD::SHL, VT, N0, 1107 DAG.getConstant(Log2_64(N1C->getValue()), 1108 TLI.getShiftAmountTy())); 1109 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1110 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) { 1111 // FIXME: If the input is something that is easily negated (e.g. a 1112 // single-use add), we should put the negate there. 1113 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), 1114 DAG.getNode(ISD::SHL, VT, N0, 1115 DAG.getConstant(Log2_64(-N1C->getSignExtended()), 1116 TLI.getShiftAmountTy()))); 1117 } 1118 1119 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1120 if (N1C && N0.getOpcode() == ISD::SHL && 1121 isa<ConstantSDNode>(N0.getOperand(1))) { 1122 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1)); 1123 AddToWorkList(C3.Val); 1124 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3); 1125 } 1126 1127 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1128 // use. 1129 { 1130 SDOperand Sh(0,0), Y(0,0); 1131 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1132 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1133 N0.Val->hasOneUse()) { 1134 Sh = N0; Y = N1; 1135 } else if (N1.getOpcode() == ISD::SHL && 1136 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) { 1137 Sh = N1; Y = N0; 1138 } 1139 if (Sh.Val) { 1140 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y); 1141 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1)); 1142 } 1143 } 1144 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1145 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() && 1146 isa<ConstantSDNode>(N0.getOperand(1))) { 1147 return DAG.getNode(ISD::ADD, VT, 1148 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1), 1149 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1)); 1150 } 1151 1152 // reassociate mul 1153 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1); 1154 if (RMUL.Val != 0) 1155 return RMUL; 1156 1157 return SDOperand(); 1158} 1159 1160SDOperand DAGCombiner::visitSDIV(SDNode *N) { 1161 SDOperand N0 = N->getOperand(0); 1162 SDOperand N1 = N->getOperand(1); 1163 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1164 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1165 MVT::ValueType VT = N->getValueType(0); 1166 1167 // fold vector ops 1168 if (MVT::isVector(VT)) { 1169 SDOperand FoldedVOp = SimplifyVBinOp(N); 1170 if (FoldedVOp.Val) return FoldedVOp; 1171 } 1172 1173 // fold (sdiv c1, c2) -> c1/c2 1174 if (N0C && N1C && !N1C->isNullValue()) 1175 return DAG.getNode(ISD::SDIV, VT, N0, N1); 1176 // fold (sdiv X, 1) -> X 1177 if (N1C && N1C->getSignExtended() == 1LL) 1178 return N0; 1179 // fold (sdiv X, -1) -> 0-X 1180 if (N1C && N1C->isAllOnesValue()) 1181 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 1182 // If we know the sign bits of both operands are zero, strength reduce to a 1183 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1184 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 1185 if (DAG.MaskedValueIsZero(N1, SignBit) && 1186 DAG.MaskedValueIsZero(N0, SignBit)) 1187 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1); 1188 // fold (sdiv X, pow2) -> simple ops after legalize 1189 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() && 1190 (isPowerOf2_64(N1C->getSignExtended()) || 1191 isPowerOf2_64(-N1C->getSignExtended()))) { 1192 // If dividing by powers of two is cheap, then don't perform the following 1193 // fold. 1194 if (TLI.isPow2DivCheap()) 1195 return SDOperand(); 1196 int64_t pow2 = N1C->getSignExtended(); 1197 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1198 unsigned lg2 = Log2_64(abs2); 1199 // Splat the sign bit into the register 1200 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0, 1201 DAG.getConstant(MVT::getSizeInBits(VT)-1, 1202 TLI.getShiftAmountTy())); 1203 AddToWorkList(SGN.Val); 1204 // Add (N0 < 0) ? abs2 - 1 : 0; 1205 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN, 1206 DAG.getConstant(MVT::getSizeInBits(VT)-lg2, 1207 TLI.getShiftAmountTy())); 1208 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL); 1209 AddToWorkList(SRL.Val); 1210 AddToWorkList(ADD.Val); // Divide by pow2 1211 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD, 1212 DAG.getConstant(lg2, TLI.getShiftAmountTy())); 1213 // If we're dividing by a positive value, we're done. Otherwise, we must 1214 // negate the result. 1215 if (pow2 > 0) 1216 return SRA; 1217 AddToWorkList(SRA.Val); 1218 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA); 1219 } 1220 // if integer divide is expensive and we satisfy the requirements, emit an 1221 // alternate sequence. 1222 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) && 1223 !TLI.isIntDivCheap()) { 1224 SDOperand Op = BuildSDIV(N); 1225 if (Op.Val) return Op; 1226 } 1227 1228 // undef / X -> 0 1229 if (N0.getOpcode() == ISD::UNDEF) 1230 return DAG.getConstant(0, VT); 1231 // X / undef -> undef 1232 if (N1.getOpcode() == ISD::UNDEF) 1233 return N1; 1234 1235 return SDOperand(); 1236} 1237 1238SDOperand DAGCombiner::visitUDIV(SDNode *N) { 1239 SDOperand N0 = N->getOperand(0); 1240 SDOperand N1 = N->getOperand(1); 1241 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1242 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1243 MVT::ValueType VT = N->getValueType(0); 1244 1245 // fold vector ops 1246 if (MVT::isVector(VT)) { 1247 SDOperand FoldedVOp = SimplifyVBinOp(N); 1248 if (FoldedVOp.Val) return FoldedVOp; 1249 } 1250 1251 // fold (udiv c1, c2) -> c1/c2 1252 if (N0C && N1C && !N1C->isNullValue()) 1253 return DAG.getNode(ISD::UDIV, VT, N0, N1); 1254 // fold (udiv x, (1 << c)) -> x >>u c 1255 if (N1C && isPowerOf2_64(N1C->getValue())) 1256 return DAG.getNode(ISD::SRL, VT, N0, 1257 DAG.getConstant(Log2_64(N1C->getValue()), 1258 TLI.getShiftAmountTy())); 1259 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1260 if (N1.getOpcode() == ISD::SHL) { 1261 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1262 if (isPowerOf2_64(SHC->getValue())) { 1263 MVT::ValueType ADDVT = N1.getOperand(1).getValueType(); 1264 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1), 1265 DAG.getConstant(Log2_64(SHC->getValue()), 1266 ADDVT)); 1267 AddToWorkList(Add.Val); 1268 return DAG.getNode(ISD::SRL, VT, N0, Add); 1269 } 1270 } 1271 } 1272 // fold (udiv x, c) -> alternate 1273 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) { 1274 SDOperand Op = BuildUDIV(N); 1275 if (Op.Val) return Op; 1276 } 1277 1278 // undef / X -> 0 1279 if (N0.getOpcode() == ISD::UNDEF) 1280 return DAG.getConstant(0, VT); 1281 // X / undef -> undef 1282 if (N1.getOpcode() == ISD::UNDEF) 1283 return N1; 1284 1285 return SDOperand(); 1286} 1287 1288SDOperand DAGCombiner::visitSREM(SDNode *N) { 1289 SDOperand N0 = N->getOperand(0); 1290 SDOperand N1 = N->getOperand(1); 1291 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1292 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1293 MVT::ValueType VT = N->getValueType(0); 1294 1295 // fold (srem c1, c2) -> c1%c2 1296 if (N0C && N1C && !N1C->isNullValue()) 1297 return DAG.getNode(ISD::SREM, VT, N0, N1); 1298 // If we know the sign bits of both operands are zero, strength reduce to a 1299 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1300 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 1301 if (DAG.MaskedValueIsZero(N1, SignBit) && 1302 DAG.MaskedValueIsZero(N0, SignBit)) 1303 return DAG.getNode(ISD::UREM, VT, N0, N1); 1304 1305 // Unconditionally lower X%C -> X-X/C*C. This allows the X/C logic to hack on 1306 // the remainder operation. 1307 if (N1C && !N1C->isNullValue()) { 1308 SDOperand Div = DAG.getNode(ISD::SDIV, VT, N0, N1); 1309 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Div, N1); 1310 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1311 AddToWorkList(Div.Val); 1312 AddToWorkList(Mul.Val); 1313 return Sub; 1314 } 1315 1316 // undef % X -> 0 1317 if (N0.getOpcode() == ISD::UNDEF) 1318 return DAG.getConstant(0, VT); 1319 // X % undef -> undef 1320 if (N1.getOpcode() == ISD::UNDEF) 1321 return N1; 1322 1323 return SDOperand(); 1324} 1325 1326SDOperand DAGCombiner::visitUREM(SDNode *N) { 1327 SDOperand N0 = N->getOperand(0); 1328 SDOperand N1 = N->getOperand(1); 1329 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1330 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1331 MVT::ValueType VT = N->getValueType(0); 1332 1333 // fold (urem c1, c2) -> c1%c2 1334 if (N0C && N1C && !N1C->isNullValue()) 1335 return DAG.getNode(ISD::UREM, VT, N0, N1); 1336 // fold (urem x, pow2) -> (and x, pow2-1) 1337 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue())) 1338 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT)); 1339 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1340 if (N1.getOpcode() == ISD::SHL) { 1341 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1342 if (isPowerOf2_64(SHC->getValue())) { 1343 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT)); 1344 AddToWorkList(Add.Val); 1345 return DAG.getNode(ISD::AND, VT, N0, Add); 1346 } 1347 } 1348 } 1349 1350 // Unconditionally lower X%C -> X-X/C*C. This allows the X/C logic to hack on 1351 // the remainder operation. 1352 if (N1C && !N1C->isNullValue()) { 1353 SDOperand Div = DAG.getNode(ISD::UDIV, VT, N0, N1); 1354 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Div, N1); 1355 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1356 AddToWorkList(Div.Val); 1357 AddToWorkList(Mul.Val); 1358 return Sub; 1359 } 1360 1361 // undef % X -> 0 1362 if (N0.getOpcode() == ISD::UNDEF) 1363 return DAG.getConstant(0, VT); 1364 // X % undef -> undef 1365 if (N1.getOpcode() == ISD::UNDEF) 1366 return N1; 1367 1368 return SDOperand(); 1369} 1370 1371SDOperand DAGCombiner::visitMULHS(SDNode *N) { 1372 SDOperand N0 = N->getOperand(0); 1373 SDOperand N1 = N->getOperand(1); 1374 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1375 MVT::ValueType VT = N->getValueType(0); 1376 1377 // fold (mulhs x, 0) -> 0 1378 if (N1C && N1C->isNullValue()) 1379 return N1; 1380 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1381 if (N1C && N1C->getValue() == 1) 1382 return DAG.getNode(ISD::SRA, N0.getValueType(), N0, 1383 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1, 1384 TLI.getShiftAmountTy())); 1385 // fold (mulhs x, undef) -> 0 1386 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1387 return DAG.getConstant(0, VT); 1388 1389 return SDOperand(); 1390} 1391 1392SDOperand DAGCombiner::visitMULHU(SDNode *N) { 1393 SDOperand N0 = N->getOperand(0); 1394 SDOperand N1 = N->getOperand(1); 1395 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1396 MVT::ValueType VT = N->getValueType(0); 1397 1398 // fold (mulhu x, 0) -> 0 1399 if (N1C && N1C->isNullValue()) 1400 return N1; 1401 // fold (mulhu x, 1) -> 0 1402 if (N1C && N1C->getValue() == 1) 1403 return DAG.getConstant(0, N0.getValueType()); 1404 // fold (mulhu x, undef) -> 0 1405 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1406 return DAG.getConstant(0, VT); 1407 1408 return SDOperand(); 1409} 1410 1411/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 1412/// compute two values. LoOp and HiOp give the opcodes for the two computations 1413/// that are being performed. Return true if a simplification was made. 1414/// 1415bool DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, 1416 unsigned LoOp, unsigned HiOp) { 1417 std::vector<SDNode*> NowDead; 1418 1419 // If the high half is not needed, just compute the low half. 1420 if (!N->hasAnyUseOfValue(1) && 1421 (!AfterLegalize || 1422 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 1423 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), 1424 DAG.getNode(LoOp, N->getValueType(0), 1425 N->op_begin(), 1426 N->getNumOperands()), 1427 NowDead); 1428 return true; 1429 } 1430 1431 // If the low half is not needed, just compute the high half. 1432 if (!N->hasAnyUseOfValue(0) && 1433 (!AfterLegalize || 1434 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 1435 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), 1436 DAG.getNode(HiOp, N->getValueType(1), 1437 N->op_begin(), 1438 N->getNumOperands()), 1439 NowDead); 1440 return true; 1441 } 1442 1443 // If the two computed results can be siplified separately, separate them. 1444 SDOperand Lo = DAG.getNode(LoOp, N->getValueType(0), 1445 N->op_begin(), N->getNumOperands()); 1446 SDOperand Hi = DAG.getNode(HiOp, N->getValueType(1), 1447 N->op_begin(), N->getNumOperands()); 1448 unsigned LoExists = !Lo.use_empty(); 1449 unsigned HiExists = !Hi.use_empty(); 1450 SDOperand LoOpt = Lo; 1451 SDOperand HiOpt = Hi; 1452 if (!LoExists || !HiExists) { 1453 SDOperand Pair = DAG.getNode(ISD::BUILD_PAIR, MVT::Other, Lo, Hi); 1454 assert(Pair.use_empty() && "Pair with type MVT::Other already exists!"); 1455 LoOpt = combine(Lo.Val); 1456 HiOpt = combine(Hi.Val); 1457 if (!LoOpt.Val) 1458 LoOpt = Pair.getOperand(0); 1459 if (!HiOpt.Val) 1460 HiOpt = Pair.getOperand(1); 1461 DAG.DeleteNode(Pair.Val); 1462 } 1463 if ((LoExists || LoOpt != Lo) && 1464 (HiExists || HiOpt != Hi) && 1465 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()) && 1466 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())) { 1467 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), LoOpt, NowDead); 1468 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), HiOpt, NowDead); 1469 return true; 1470 } 1471 1472 return false; 1473} 1474 1475SDOperand DAGCombiner::visitSMUL_LOHI(SDNode *N) { 1476 1477 if (SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS)) 1478 return SDOperand(); 1479 1480 return SDOperand(); 1481} 1482 1483SDOperand DAGCombiner::visitUMUL_LOHI(SDNode *N) { 1484 1485 if (SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU)) 1486 return SDOperand(); 1487 1488 return SDOperand(); 1489} 1490 1491SDOperand DAGCombiner::visitSDIVREM(SDNode *N) { 1492 1493 if (SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM)) 1494 return SDOperand(); 1495 1496 return SDOperand(); 1497} 1498 1499SDOperand DAGCombiner::visitUDIVREM(SDNode *N) { 1500 1501 if (SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM)) 1502 return SDOperand(); 1503 1504 return SDOperand(); 1505} 1506 1507/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 1508/// two operands of the same opcode, try to simplify it. 1509SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 1510 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1); 1511 MVT::ValueType VT = N0.getValueType(); 1512 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 1513 1514 // For each of OP in AND/OR/XOR: 1515 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 1516 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 1517 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 1518 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) 1519 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND|| 1520 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) && 1521 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1522 SDOperand ORNode = DAG.getNode(N->getOpcode(), 1523 N0.getOperand(0).getValueType(), 1524 N0.getOperand(0), N1.getOperand(0)); 1525 AddToWorkList(ORNode.Val); 1526 return DAG.getNode(N0.getOpcode(), VT, ORNode); 1527 } 1528 1529 // For each of OP in SHL/SRL/SRA/AND... 1530 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 1531 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 1532 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 1533 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 1534 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 1535 N0.getOperand(1) == N1.getOperand(1)) { 1536 SDOperand ORNode = DAG.getNode(N->getOpcode(), 1537 N0.getOperand(0).getValueType(), 1538 N0.getOperand(0), N1.getOperand(0)); 1539 AddToWorkList(ORNode.Val); 1540 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1)); 1541 } 1542 1543 return SDOperand(); 1544} 1545 1546SDOperand DAGCombiner::visitAND(SDNode *N) { 1547 SDOperand N0 = N->getOperand(0); 1548 SDOperand N1 = N->getOperand(1); 1549 SDOperand LL, LR, RL, RR, CC0, CC1; 1550 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1551 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1552 MVT::ValueType VT = N1.getValueType(); 1553 1554 // fold vector ops 1555 if (MVT::isVector(VT)) { 1556 SDOperand FoldedVOp = SimplifyVBinOp(N); 1557 if (FoldedVOp.Val) return FoldedVOp; 1558 } 1559 1560 // fold (and x, undef) -> 0 1561 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1562 return DAG.getConstant(0, VT); 1563 // fold (and c1, c2) -> c1&c2 1564 if (N0C && N1C) 1565 return DAG.getNode(ISD::AND, VT, N0, N1); 1566 // canonicalize constant to RHS 1567 if (N0C && !N1C) 1568 return DAG.getNode(ISD::AND, VT, N1, N0); 1569 // fold (and x, -1) -> x 1570 if (N1C && N1C->isAllOnesValue()) 1571 return N0; 1572 // if (and x, c) is known to be zero, return 0 1573 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) 1574 return DAG.getConstant(0, VT); 1575 // reassociate and 1576 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1); 1577 if (RAND.Val != 0) 1578 return RAND; 1579 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 1580 if (N1C && N0.getOpcode() == ISD::OR) 1581 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1582 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue()) 1583 return N1; 1584 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 1585 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1586 unsigned InMask = MVT::getIntVTBitMask(N0.getOperand(0).getValueType()); 1587 if (DAG.MaskedValueIsZero(N0.getOperand(0), 1588 ~N1C->getValue() & InMask)) { 1589 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(), 1590 N0.getOperand(0)); 1591 1592 // Replace uses of the AND with uses of the Zero extend node. 1593 CombineTo(N, Zext); 1594 1595 // We actually want to replace all uses of the any_extend with the 1596 // zero_extend, to avoid duplicating things. This will later cause this 1597 // AND to be folded. 1598 CombineTo(N0.Val, Zext); 1599 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1600 } 1601 } 1602 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 1603 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1604 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1605 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1606 1607 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1608 MVT::isInteger(LL.getValueType())) { 1609 // fold (X == 0) & (Y == 0) -> (X|Y == 0) 1610 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) { 1611 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1612 AddToWorkList(ORNode.Val); 1613 return DAG.getSetCC(VT, ORNode, LR, Op1); 1614 } 1615 // fold (X == -1) & (Y == -1) -> (X&Y == -1) 1616 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 1617 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1618 AddToWorkList(ANDNode.Val); 1619 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1620 } 1621 // fold (X > -1) & (Y > -1) -> (X|Y > -1) 1622 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1623 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1624 AddToWorkList(ORNode.Val); 1625 return DAG.getSetCC(VT, ORNode, LR, Op1); 1626 } 1627 } 1628 // canonicalize equivalent to ll == rl 1629 if (LL == RR && LR == RL) { 1630 Op1 = ISD::getSetCCSwappedOperands(Op1); 1631 std::swap(RL, RR); 1632 } 1633 if (LL == RL && LR == RR) { 1634 bool isInteger = MVT::isInteger(LL.getValueType()); 1635 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1636 if (Result != ISD::SETCC_INVALID) 1637 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1638 } 1639 } 1640 1641 // Simplify: and (op x...), (op y...) -> (op (and x, y)) 1642 if (N0.getOpcode() == N1.getOpcode()) { 1643 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1644 if (Tmp.Val) return Tmp; 1645 } 1646 1647 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1648 // fold (and (sra)) -> (and (srl)) when possible. 1649 if (!MVT::isVector(VT) && 1650 SimplifyDemandedBits(SDOperand(N, 0))) 1651 return SDOperand(N, 0); 1652 // fold (zext_inreg (extload x)) -> (zextload x) 1653 if (ISD::isEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val)) { 1654 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1655 MVT::ValueType EVT = LN0->getLoadedVT(); 1656 // If we zero all the possible extended bits, then we can turn this into 1657 // a zextload if we are running before legalize or the operation is legal. 1658 if (DAG.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && 1659 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1660 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1661 LN0->getBasePtr(), LN0->getSrcValue(), 1662 LN0->getSrcValueOffset(), EVT, 1663 LN0->isVolatile(), 1664 LN0->getAlignment()); 1665 AddToWorkList(N); 1666 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1667 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1668 } 1669 } 1670 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1671 if (ISD::isSEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 1672 N0.hasOneUse()) { 1673 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1674 MVT::ValueType EVT = LN0->getLoadedVT(); 1675 // If we zero all the possible extended bits, then we can turn this into 1676 // a zextload if we are running before legalize or the operation is legal. 1677 if (DAG.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && 1678 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1679 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1680 LN0->getBasePtr(), LN0->getSrcValue(), 1681 LN0->getSrcValueOffset(), EVT, 1682 LN0->isVolatile(), 1683 LN0->getAlignment()); 1684 AddToWorkList(N); 1685 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1686 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1687 } 1688 } 1689 1690 // fold (and (load x), 255) -> (zextload x, i8) 1691 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1692 if (N1C && N0.getOpcode() == ISD::LOAD) { 1693 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1694 if (LN0->getExtensionType() != ISD::SEXTLOAD && 1695 LN0->getAddressingMode() == ISD::UNINDEXED && 1696 N0.hasOneUse()) { 1697 MVT::ValueType EVT, LoadedVT; 1698 if (N1C->getValue() == 255) 1699 EVT = MVT::i8; 1700 else if (N1C->getValue() == 65535) 1701 EVT = MVT::i16; 1702 else if (N1C->getValue() == ~0U) 1703 EVT = MVT::i32; 1704 else 1705 EVT = MVT::Other; 1706 1707 LoadedVT = LN0->getLoadedVT(); 1708 if (EVT != MVT::Other && LoadedVT > EVT && 1709 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1710 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 1711 // For big endian targets, we need to add an offset to the pointer to 1712 // load the correct bytes. For little endian systems, we merely need to 1713 // read fewer bytes from the same pointer. 1714 unsigned PtrOff = 1715 (MVT::getSizeInBits(LoadedVT) - MVT::getSizeInBits(EVT)) / 8; 1716 SDOperand NewPtr = LN0->getBasePtr(); 1717 if (!TLI.isLittleEndian()) 1718 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, 1719 DAG.getConstant(PtrOff, PtrType)); 1720 AddToWorkList(NewPtr.Val); 1721 SDOperand Load = 1722 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr, 1723 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT, 1724 LN0->isVolatile(), LN0->getAlignment()); 1725 AddToWorkList(N); 1726 CombineTo(N0.Val, Load, Load.getValue(1)); 1727 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1728 } 1729 } 1730 } 1731 1732 return SDOperand(); 1733} 1734 1735SDOperand DAGCombiner::visitOR(SDNode *N) { 1736 SDOperand N0 = N->getOperand(0); 1737 SDOperand N1 = N->getOperand(1); 1738 SDOperand LL, LR, RL, RR, CC0, CC1; 1739 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1740 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1741 MVT::ValueType VT = N1.getValueType(); 1742 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1743 1744 // fold vector ops 1745 if (MVT::isVector(VT)) { 1746 SDOperand FoldedVOp = SimplifyVBinOp(N); 1747 if (FoldedVOp.Val) return FoldedVOp; 1748 } 1749 1750 // fold (or x, undef) -> -1 1751 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1752 return DAG.getConstant(~0ULL, VT); 1753 // fold (or c1, c2) -> c1|c2 1754 if (N0C && N1C) 1755 return DAG.getNode(ISD::OR, VT, N0, N1); 1756 // canonicalize constant to RHS 1757 if (N0C && !N1C) 1758 return DAG.getNode(ISD::OR, VT, N1, N0); 1759 // fold (or x, 0) -> x 1760 if (N1C && N1C->isNullValue()) 1761 return N0; 1762 // fold (or x, -1) -> -1 1763 if (N1C && N1C->isAllOnesValue()) 1764 return N1; 1765 // fold (or x, c) -> c iff (x & ~c) == 0 1766 if (N1C && 1767 DAG.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)))) 1768 return N1; 1769 // reassociate or 1770 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1); 1771 if (ROR.Val != 0) 1772 return ROR; 1773 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 1774 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() && 1775 isa<ConstantSDNode>(N0.getOperand(1))) { 1776 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 1777 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0), 1778 N1), 1779 DAG.getConstant(N1C->getValue() | C1->getValue(), VT)); 1780 } 1781 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 1782 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1783 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1784 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1785 1786 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1787 MVT::isInteger(LL.getValueType())) { 1788 // fold (X != 0) | (Y != 0) -> (X|Y != 0) 1789 // fold (X < 0) | (Y < 0) -> (X|Y < 0) 1790 if (cast<ConstantSDNode>(LR)->getValue() == 0 && 1791 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 1792 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1793 AddToWorkList(ORNode.Val); 1794 return DAG.getSetCC(VT, ORNode, LR, Op1); 1795 } 1796 // fold (X != -1) | (Y != -1) -> (X&Y != -1) 1797 // fold (X > -1) | (Y > -1) -> (X&Y > -1) 1798 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 1799 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 1800 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1801 AddToWorkList(ANDNode.Val); 1802 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1803 } 1804 } 1805 // canonicalize equivalent to ll == rl 1806 if (LL == RR && LR == RL) { 1807 Op1 = ISD::getSetCCSwappedOperands(Op1); 1808 std::swap(RL, RR); 1809 } 1810 if (LL == RL && LR == RR) { 1811 bool isInteger = MVT::isInteger(LL.getValueType()); 1812 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 1813 if (Result != ISD::SETCC_INVALID) 1814 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1815 } 1816 } 1817 1818 // Simplify: or (op x...), (op y...) -> (op (or x, y)) 1819 if (N0.getOpcode() == N1.getOpcode()) { 1820 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1821 if (Tmp.Val) return Tmp; 1822 } 1823 1824 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible. 1825 if (N0.getOpcode() == ISD::AND && 1826 N1.getOpcode() == ISD::AND && 1827 N0.getOperand(1).getOpcode() == ISD::Constant && 1828 N1.getOperand(1).getOpcode() == ISD::Constant && 1829 // Don't increase # computations. 1830 (N0.Val->hasOneUse() || N1.Val->hasOneUse())) { 1831 // We can only do this xform if we know that bits from X that are set in C2 1832 // but not in C1 are already zero. Likewise for Y. 1833 uint64_t LHSMask = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1834 uint64_t RHSMask = cast<ConstantSDNode>(N1.getOperand(1))->getValue(); 1835 1836 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 1837 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 1838 SDOperand X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0)); 1839 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT)); 1840 } 1841 } 1842 1843 1844 // See if this is some rotate idiom. 1845 if (SDNode *Rot = MatchRotate(N0, N1)) 1846 return SDOperand(Rot, 0); 1847 1848 return SDOperand(); 1849} 1850 1851 1852/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 1853static bool MatchRotateHalf(SDOperand Op, SDOperand &Shift, SDOperand &Mask) { 1854 if (Op.getOpcode() == ISD::AND) { 1855 if (isa<ConstantSDNode>(Op.getOperand(1))) { 1856 Mask = Op.getOperand(1); 1857 Op = Op.getOperand(0); 1858 } else { 1859 return false; 1860 } 1861 } 1862 1863 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 1864 Shift = Op; 1865 return true; 1866 } 1867 return false; 1868} 1869 1870 1871// MatchRotate - Handle an 'or' of two operands. If this is one of the many 1872// idioms for rotate, and if the target supports rotation instructions, generate 1873// a rot[lr]. 1874SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) { 1875 // Must be a legal type. Expanded an promoted things won't work with rotates. 1876 MVT::ValueType VT = LHS.getValueType(); 1877 if (!TLI.isTypeLegal(VT)) return 0; 1878 1879 // The target must have at least one rotate flavor. 1880 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT); 1881 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT); 1882 if (!HasROTL && !HasROTR) return 0; 1883 1884 // Match "(X shl/srl V1) & V2" where V2 may not be present. 1885 SDOperand LHSShift; // The shift. 1886 SDOperand LHSMask; // AND value if any. 1887 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 1888 return 0; // Not part of a rotate. 1889 1890 SDOperand RHSShift; // The shift. 1891 SDOperand RHSMask; // AND value if any. 1892 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 1893 return 0; // Not part of a rotate. 1894 1895 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 1896 return 0; // Not shifting the same value. 1897 1898 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 1899 return 0; // Shifts must disagree. 1900 1901 // Canonicalize shl to left side in a shl/srl pair. 1902 if (RHSShift.getOpcode() == ISD::SHL) { 1903 std::swap(LHS, RHS); 1904 std::swap(LHSShift, RHSShift); 1905 std::swap(LHSMask , RHSMask ); 1906 } 1907 1908 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1909 SDOperand LHSShiftArg = LHSShift.getOperand(0); 1910 SDOperand LHSShiftAmt = LHSShift.getOperand(1); 1911 SDOperand RHSShiftAmt = RHSShift.getOperand(1); 1912 1913 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 1914 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 1915 if (LHSShiftAmt.getOpcode() == ISD::Constant && 1916 RHSShiftAmt.getOpcode() == ISD::Constant) { 1917 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getValue(); 1918 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getValue(); 1919 if ((LShVal + RShVal) != OpSizeInBits) 1920 return 0; 1921 1922 SDOperand Rot; 1923 if (HasROTL) 1924 Rot = DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt); 1925 else 1926 Rot = DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt); 1927 1928 // If there is an AND of either shifted operand, apply it to the result. 1929 if (LHSMask.Val || RHSMask.Val) { 1930 uint64_t Mask = MVT::getIntVTBitMask(VT); 1931 1932 if (LHSMask.Val) { 1933 uint64_t RHSBits = (1ULL << LShVal)-1; 1934 Mask &= cast<ConstantSDNode>(LHSMask)->getValue() | RHSBits; 1935 } 1936 if (RHSMask.Val) { 1937 uint64_t LHSBits = ~((1ULL << (OpSizeInBits-RShVal))-1); 1938 Mask &= cast<ConstantSDNode>(RHSMask)->getValue() | LHSBits; 1939 } 1940 1941 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT)); 1942 } 1943 1944 return Rot.Val; 1945 } 1946 1947 // If there is a mask here, and we have a variable shift, we can't be sure 1948 // that we're masking out the right stuff. 1949 if (LHSMask.Val || RHSMask.Val) 1950 return 0; 1951 1952 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 1953 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 1954 if (RHSShiftAmt.getOpcode() == ISD::SUB && 1955 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 1956 if (ConstantSDNode *SUBC = 1957 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 1958 if (SUBC->getValue() == OpSizeInBits) 1959 if (HasROTL) 1960 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 1961 else 1962 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 1963 } 1964 } 1965 1966 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 1967 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 1968 if (LHSShiftAmt.getOpcode() == ISD::SUB && 1969 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 1970 if (ConstantSDNode *SUBC = 1971 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 1972 if (SUBC->getValue() == OpSizeInBits) 1973 if (HasROTL) 1974 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 1975 else 1976 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 1977 } 1978 } 1979 1980 // Look for sign/zext/any-extended cases: 1981 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 1982 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 1983 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND) && 1984 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 1985 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 1986 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND)) { 1987 SDOperand LExtOp0 = LHSShiftAmt.getOperand(0); 1988 SDOperand RExtOp0 = RHSShiftAmt.getOperand(0); 1989 if (RExtOp0.getOpcode() == ISD::SUB && 1990 RExtOp0.getOperand(1) == LExtOp0) { 1991 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 1992 // (rotr x, y) 1993 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 1994 // (rotl x, (sub 32, y)) 1995 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 1996 if (SUBC->getValue() == OpSizeInBits) { 1997 if (HasROTL) 1998 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 1999 else 2000 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 2001 } 2002 } 2003 } else if (LExtOp0.getOpcode() == ISD::SUB && 2004 RExtOp0 == LExtOp0.getOperand(1)) { 2005 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -> 2006 // (rotl x, y) 2007 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -> 2008 // (rotr x, (sub 32, y)) 2009 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 2010 if (SUBC->getValue() == OpSizeInBits) { 2011 if (HasROTL) 2012 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, RHSShiftAmt).Val; 2013 else 2014 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 2015 } 2016 } 2017 } 2018 } 2019 2020 return 0; 2021} 2022 2023 2024SDOperand DAGCombiner::visitXOR(SDNode *N) { 2025 SDOperand N0 = N->getOperand(0); 2026 SDOperand N1 = N->getOperand(1); 2027 SDOperand LHS, RHS, CC; 2028 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2029 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2030 MVT::ValueType VT = N0.getValueType(); 2031 2032 // fold vector ops 2033 if (MVT::isVector(VT)) { 2034 SDOperand FoldedVOp = SimplifyVBinOp(N); 2035 if (FoldedVOp.Val) return FoldedVOp; 2036 } 2037 2038 // fold (xor x, undef) -> undef 2039 if (N0.getOpcode() == ISD::UNDEF) 2040 return N0; 2041 if (N1.getOpcode() == ISD::UNDEF) 2042 return N1; 2043 // fold (xor c1, c2) -> c1^c2 2044 if (N0C && N1C) 2045 return DAG.getNode(ISD::XOR, VT, N0, N1); 2046 // canonicalize constant to RHS 2047 if (N0C && !N1C) 2048 return DAG.getNode(ISD::XOR, VT, N1, N0); 2049 // fold (xor x, 0) -> x 2050 if (N1C && N1C->isNullValue()) 2051 return N0; 2052 // reassociate xor 2053 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1); 2054 if (RXOR.Val != 0) 2055 return RXOR; 2056 // fold !(x cc y) -> (x !cc y) 2057 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 2058 bool isInt = MVT::isInteger(LHS.getValueType()); 2059 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 2060 isInt); 2061 if (N0.getOpcode() == ISD::SETCC) 2062 return DAG.getSetCC(VT, LHS, RHS, NotCC); 2063 if (N0.getOpcode() == ISD::SELECT_CC) 2064 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC); 2065 assert(0 && "Unhandled SetCC Equivalent!"); 2066 abort(); 2067 } 2068 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 2069 if (N1C && N1C->getValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 2070 N0.Val->hasOneUse() && isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 2071 SDOperand V = N0.getOperand(0); 2072 V = DAG.getNode(ISD::XOR, V.getValueType(), V, 2073 DAG.getConstant(1, V.getValueType())); 2074 AddToWorkList(V.Val); 2075 return DAG.getNode(ISD::ZERO_EXTEND, VT, V); 2076 } 2077 2078 // fold !(x or y) -> (!x and !y) iff x or y are setcc 2079 if (N1C && N1C->getValue() == 1 && VT == MVT::i1 && 2080 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2081 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2082 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 2083 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2084 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 2085 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 2086 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 2087 return DAG.getNode(NewOpcode, VT, LHS, RHS); 2088 } 2089 } 2090 // fold !(x or y) -> (!x and !y) iff x or y are constants 2091 if (N1C && N1C->isAllOnesValue() && 2092 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2093 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2094 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 2095 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2096 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 2097 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 2098 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 2099 return DAG.getNode(NewOpcode, VT, LHS, RHS); 2100 } 2101 } 2102 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2) 2103 if (N1C && N0.getOpcode() == ISD::XOR) { 2104 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 2105 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2106 if (N00C) 2107 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1), 2108 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT)); 2109 if (N01C) 2110 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0), 2111 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT)); 2112 } 2113 // fold (xor x, x) -> 0 2114 if (N0 == N1) { 2115 if (!MVT::isVector(VT)) { 2116 return DAG.getConstant(0, VT); 2117 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 2118 // Produce a vector of zeros. 2119 SDOperand El = DAG.getConstant(0, MVT::getVectorElementType(VT)); 2120 std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El); 2121 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 2122 } 2123 } 2124 2125 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 2126 if (N0.getOpcode() == N1.getOpcode()) { 2127 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2128 if (Tmp.Val) return Tmp; 2129 } 2130 2131 // Simplify the expression using non-local knowledge. 2132 if (!MVT::isVector(VT) && 2133 SimplifyDemandedBits(SDOperand(N, 0))) 2134 return SDOperand(N, 0); 2135 2136 return SDOperand(); 2137} 2138 2139SDOperand DAGCombiner::visitSHL(SDNode *N) { 2140 SDOperand N0 = N->getOperand(0); 2141 SDOperand N1 = N->getOperand(1); 2142 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2143 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2144 MVT::ValueType VT = N0.getValueType(); 2145 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 2146 2147 // fold (shl c1, c2) -> c1<<c2 2148 if (N0C && N1C) 2149 return DAG.getNode(ISD::SHL, VT, N0, N1); 2150 // fold (shl 0, x) -> 0 2151 if (N0C && N0C->isNullValue()) 2152 return N0; 2153 // fold (shl x, c >= size(x)) -> undef 2154 if (N1C && N1C->getValue() >= OpSizeInBits) 2155 return DAG.getNode(ISD::UNDEF, VT); 2156 // fold (shl x, 0) -> x 2157 if (N1C && N1C->isNullValue()) 2158 return N0; 2159 // if (shl x, c) is known to be zero, return 0 2160 if (DAG.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) 2161 return DAG.getConstant(0, VT); 2162 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 2163 return SDOperand(N, 0); 2164 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2) 2165 if (N1C && N0.getOpcode() == ISD::SHL && 2166 N0.getOperand(1).getOpcode() == ISD::Constant) { 2167 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2168 uint64_t c2 = N1C->getValue(); 2169 if (c1 + c2 > OpSizeInBits) 2170 return DAG.getConstant(0, VT); 2171 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0), 2172 DAG.getConstant(c1 + c2, N1.getValueType())); 2173 } 2174 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or 2175 // (srl (and x, -1 << c1), c1-c2) 2176 if (N1C && N0.getOpcode() == ISD::SRL && 2177 N0.getOperand(1).getOpcode() == ISD::Constant) { 2178 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2179 uint64_t c2 = N1C->getValue(); 2180 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0), 2181 DAG.getConstant(~0ULL << c1, VT)); 2182 if (c2 > c1) 2183 return DAG.getNode(ISD::SHL, VT, Mask, 2184 DAG.getConstant(c2-c1, N1.getValueType())); 2185 else 2186 return DAG.getNode(ISD::SRL, VT, Mask, 2187 DAG.getConstant(c1-c2, N1.getValueType())); 2188 } 2189 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1) 2190 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 2191 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 2192 DAG.getConstant(~0ULL << N1C->getValue(), VT)); 2193 return SDOperand(); 2194} 2195 2196SDOperand DAGCombiner::visitSRA(SDNode *N) { 2197 SDOperand N0 = N->getOperand(0); 2198 SDOperand N1 = N->getOperand(1); 2199 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2200 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2201 MVT::ValueType VT = N0.getValueType(); 2202 2203 // fold (sra c1, c2) -> c1>>c2 2204 if (N0C && N1C) 2205 return DAG.getNode(ISD::SRA, VT, N0, N1); 2206 // fold (sra 0, x) -> 0 2207 if (N0C && N0C->isNullValue()) 2208 return N0; 2209 // fold (sra -1, x) -> -1 2210 if (N0C && N0C->isAllOnesValue()) 2211 return N0; 2212 // fold (sra x, c >= size(x)) -> undef 2213 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT)) 2214 return DAG.getNode(ISD::UNDEF, VT); 2215 // fold (sra x, 0) -> x 2216 if (N1C && N1C->isNullValue()) 2217 return N0; 2218 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 2219 // sext_inreg. 2220 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 2221 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue(); 2222 MVT::ValueType EVT; 2223 switch (LowBits) { 2224 default: EVT = MVT::Other; break; 2225 case 1: EVT = MVT::i1; break; 2226 case 8: EVT = MVT::i8; break; 2227 case 16: EVT = MVT::i16; break; 2228 case 32: EVT = MVT::i32; break; 2229 } 2230 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT)) 2231 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), 2232 DAG.getValueType(EVT)); 2233 } 2234 2235 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2) 2236 if (N1C && N0.getOpcode() == ISD::SRA) { 2237 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2238 unsigned Sum = N1C->getValue() + C1->getValue(); 2239 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1; 2240 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), 2241 DAG.getConstant(Sum, N1C->getValueType(0))); 2242 } 2243 } 2244 2245 // Simplify, based on bits shifted out of the LHS. 2246 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 2247 return SDOperand(N, 0); 2248 2249 2250 // If the sign bit is known to be zero, switch this to a SRL. 2251 if (DAG.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT))) 2252 return DAG.getNode(ISD::SRL, VT, N0, N1); 2253 return SDOperand(); 2254} 2255 2256SDOperand DAGCombiner::visitSRL(SDNode *N) { 2257 SDOperand N0 = N->getOperand(0); 2258 SDOperand N1 = N->getOperand(1); 2259 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2260 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2261 MVT::ValueType VT = N0.getValueType(); 2262 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 2263 2264 // fold (srl c1, c2) -> c1 >>u c2 2265 if (N0C && N1C) 2266 return DAG.getNode(ISD::SRL, VT, N0, N1); 2267 // fold (srl 0, x) -> 0 2268 if (N0C && N0C->isNullValue()) 2269 return N0; 2270 // fold (srl x, c >= size(x)) -> undef 2271 if (N1C && N1C->getValue() >= OpSizeInBits) 2272 return DAG.getNode(ISD::UNDEF, VT); 2273 // fold (srl x, 0) -> x 2274 if (N1C && N1C->isNullValue()) 2275 return N0; 2276 // if (srl x, c) is known to be zero, return 0 2277 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits))) 2278 return DAG.getConstant(0, VT); 2279 2280 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2) 2281 if (N1C && N0.getOpcode() == ISD::SRL && 2282 N0.getOperand(1).getOpcode() == ISD::Constant) { 2283 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2284 uint64_t c2 = N1C->getValue(); 2285 if (c1 + c2 > OpSizeInBits) 2286 return DAG.getConstant(0, VT); 2287 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 2288 DAG.getConstant(c1 + c2, N1.getValueType())); 2289 } 2290 2291 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 2292 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2293 // Shifting in all undef bits? 2294 MVT::ValueType SmallVT = N0.getOperand(0).getValueType(); 2295 if (N1C->getValue() >= MVT::getSizeInBits(SmallVT)) 2296 return DAG.getNode(ISD::UNDEF, VT); 2297 2298 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1); 2299 AddToWorkList(SmallShift.Val); 2300 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift); 2301 } 2302 2303 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 2304 // bit, which is unmodified by sra. 2305 if (N1C && N1C->getValue()+1 == MVT::getSizeInBits(VT)) { 2306 if (N0.getOpcode() == ISD::SRA) 2307 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1); 2308 } 2309 2310 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 2311 if (N1C && N0.getOpcode() == ISD::CTLZ && 2312 N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) { 2313 uint64_t KnownZero, KnownOne, Mask = MVT::getIntVTBitMask(VT); 2314 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 2315 2316 // If any of the input bits are KnownOne, then the input couldn't be all 2317 // zeros, thus the result of the srl will always be zero. 2318 if (KnownOne) return DAG.getConstant(0, VT); 2319 2320 // If all of the bits input the to ctlz node are known to be zero, then 2321 // the result of the ctlz is "32" and the result of the shift is one. 2322 uint64_t UnknownBits = ~KnownZero & Mask; 2323 if (UnknownBits == 0) return DAG.getConstant(1, VT); 2324 2325 // Otherwise, check to see if there is exactly one bit input to the ctlz. 2326 if ((UnknownBits & (UnknownBits-1)) == 0) { 2327 // Okay, we know that only that the single bit specified by UnknownBits 2328 // could be set on input to the CTLZ node. If this bit is set, the SRL 2329 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 2330 // to an SRL,XOR pair, which is likely to simplify more. 2331 unsigned ShAmt = CountTrailingZeros_64(UnknownBits); 2332 SDOperand Op = N0.getOperand(0); 2333 if (ShAmt) { 2334 Op = DAG.getNode(ISD::SRL, VT, Op, 2335 DAG.getConstant(ShAmt, TLI.getShiftAmountTy())); 2336 AddToWorkList(Op.Val); 2337 } 2338 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT)); 2339 } 2340 } 2341 2342 // fold operands of srl based on knowledge that the low bits are not 2343 // demanded. 2344 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 2345 return SDOperand(N, 0); 2346 2347 return SDOperand(); 2348} 2349 2350SDOperand DAGCombiner::visitCTLZ(SDNode *N) { 2351 SDOperand N0 = N->getOperand(0); 2352 MVT::ValueType VT = N->getValueType(0); 2353 2354 // fold (ctlz c1) -> c2 2355 if (isa<ConstantSDNode>(N0)) 2356 return DAG.getNode(ISD::CTLZ, VT, N0); 2357 return SDOperand(); 2358} 2359 2360SDOperand DAGCombiner::visitCTTZ(SDNode *N) { 2361 SDOperand N0 = N->getOperand(0); 2362 MVT::ValueType VT = N->getValueType(0); 2363 2364 // fold (cttz c1) -> c2 2365 if (isa<ConstantSDNode>(N0)) 2366 return DAG.getNode(ISD::CTTZ, VT, N0); 2367 return SDOperand(); 2368} 2369 2370SDOperand DAGCombiner::visitCTPOP(SDNode *N) { 2371 SDOperand N0 = N->getOperand(0); 2372 MVT::ValueType VT = N->getValueType(0); 2373 2374 // fold (ctpop c1) -> c2 2375 if (isa<ConstantSDNode>(N0)) 2376 return DAG.getNode(ISD::CTPOP, VT, N0); 2377 return SDOperand(); 2378} 2379 2380SDOperand DAGCombiner::visitSELECT(SDNode *N) { 2381 SDOperand N0 = N->getOperand(0); 2382 SDOperand N1 = N->getOperand(1); 2383 SDOperand N2 = N->getOperand(2); 2384 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2385 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2386 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 2387 MVT::ValueType VT = N->getValueType(0); 2388 MVT::ValueType VT0 = N0.getValueType(); 2389 2390 // fold select C, X, X -> X 2391 if (N1 == N2) 2392 return N1; 2393 // fold select true, X, Y -> X 2394 if (N0C && !N0C->isNullValue()) 2395 return N1; 2396 // fold select false, X, Y -> Y 2397 if (N0C && N0C->isNullValue()) 2398 return N2; 2399 // fold select C, 1, X -> C | X 2400 if (MVT::i1 == VT && N1C && N1C->getValue() == 1) 2401 return DAG.getNode(ISD::OR, VT, N0, N2); 2402 // fold select C, 0, 1 -> ~C 2403 if (MVT::isInteger(VT) && MVT::isInteger(VT0) && 2404 N1C && N2C && N1C->isNullValue() && N2C->getValue() == 1) { 2405 SDOperand XORNode = DAG.getNode(ISD::XOR, VT0, N0, DAG.getConstant(1, VT0)); 2406 if (VT == VT0) 2407 return XORNode; 2408 AddToWorkList(XORNode.Val); 2409 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(VT0)) 2410 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode); 2411 return DAG.getNode(ISD::TRUNCATE, VT, XORNode); 2412 } 2413 // fold select C, 0, X -> ~C & X 2414 if (VT == VT0 && N1C && N1C->isNullValue()) { 2415 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 2416 AddToWorkList(XORNode.Val); 2417 return DAG.getNode(ISD::AND, VT, XORNode, N2); 2418 } 2419 // fold select C, X, 1 -> ~C | X 2420 if (VT == VT0 && N2C && N2C->getValue() == 1) { 2421 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 2422 AddToWorkList(XORNode.Val); 2423 return DAG.getNode(ISD::OR, VT, XORNode, N1); 2424 } 2425 // fold select C, X, 0 -> C & X 2426 // FIXME: this should check for C type == X type, not i1? 2427 if (MVT::i1 == VT && N2C && N2C->isNullValue()) 2428 return DAG.getNode(ISD::AND, VT, N0, N1); 2429 // fold X ? X : Y --> X ? 1 : Y --> X | Y 2430 if (MVT::i1 == VT && N0 == N1) 2431 return DAG.getNode(ISD::OR, VT, N0, N2); 2432 // fold X ? Y : X --> X ? Y : 0 --> X & Y 2433 if (MVT::i1 == VT && N0 == N2) 2434 return DAG.getNode(ISD::AND, VT, N0, N1); 2435 2436 // If we can fold this based on the true/false value, do so. 2437 if (SimplifySelectOps(N, N1, N2)) 2438 return SDOperand(N, 0); // Don't revisit N. 2439 2440 // fold selects based on a setcc into other things, such as min/max/abs 2441 if (N0.getOpcode() == ISD::SETCC) 2442 // FIXME: 2443 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 2444 // having to say they don't support SELECT_CC on every type the DAG knows 2445 // about, since there is no way to mark an opcode illegal at all value types 2446 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other)) 2447 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1), 2448 N1, N2, N0.getOperand(2)); 2449 else 2450 return SimplifySelect(N0, N1, N2); 2451 return SDOperand(); 2452} 2453 2454SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) { 2455 SDOperand N0 = N->getOperand(0); 2456 SDOperand N1 = N->getOperand(1); 2457 SDOperand N2 = N->getOperand(2); 2458 SDOperand N3 = N->getOperand(3); 2459 SDOperand N4 = N->getOperand(4); 2460 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 2461 2462 // fold select_cc lhs, rhs, x, x, cc -> x 2463 if (N2 == N3) 2464 return N2; 2465 2466 // Determine if the condition we're dealing with is constant 2467 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 2468 if (SCC.Val) AddToWorkList(SCC.Val); 2469 2470 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) { 2471 if (SCCC->getValue()) 2472 return N2; // cond always true -> true val 2473 else 2474 return N3; // cond always false -> false val 2475 } 2476 2477 // Fold to a simpler select_cc 2478 if (SCC.Val && SCC.getOpcode() == ISD::SETCC) 2479 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(), 2480 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 2481 SCC.getOperand(2)); 2482 2483 // If we can fold this based on the true/false value, do so. 2484 if (SimplifySelectOps(N, N2, N3)) 2485 return SDOperand(N, 0); // Don't revisit N. 2486 2487 // fold select_cc into other things, such as min/max/abs 2488 return SimplifySelectCC(N0, N1, N2, N3, CC); 2489} 2490 2491SDOperand DAGCombiner::visitSETCC(SDNode *N) { 2492 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 2493 cast<CondCodeSDNode>(N->getOperand(2))->get()); 2494} 2495 2496SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 2497 SDOperand N0 = N->getOperand(0); 2498 MVT::ValueType VT = N->getValueType(0); 2499 2500 // fold (sext c1) -> c1 2501 if (isa<ConstantSDNode>(N0)) 2502 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0); 2503 2504 // fold (sext (sext x)) -> (sext x) 2505 // fold (sext (aext x)) -> (sext x) 2506 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2507 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0)); 2508 2509 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 2510 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 2511 if (N0.getOpcode() == ISD::TRUNCATE) { 2512 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2513 if (NarrowLoad.Val) { 2514 if (NarrowLoad.Val != N0.Val) 2515 CombineTo(N0.Val, NarrowLoad); 2516 return DAG.getNode(ISD::SIGN_EXTEND, VT, NarrowLoad); 2517 } 2518 } 2519 2520 // See if the value being truncated is already sign extended. If so, just 2521 // eliminate the trunc/sext pair. 2522 if (N0.getOpcode() == ISD::TRUNCATE) { 2523 SDOperand Op = N0.getOperand(0); 2524 unsigned OpBits = MVT::getSizeInBits(Op.getValueType()); 2525 unsigned MidBits = MVT::getSizeInBits(N0.getValueType()); 2526 unsigned DestBits = MVT::getSizeInBits(VT); 2527 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 2528 2529 if (OpBits == DestBits) { 2530 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 2531 // bits, it is already ready. 2532 if (NumSignBits > DestBits-MidBits) 2533 return Op; 2534 } else if (OpBits < DestBits) { 2535 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 2536 // bits, just sext from i32. 2537 if (NumSignBits > OpBits-MidBits) 2538 return DAG.getNode(ISD::SIGN_EXTEND, VT, Op); 2539 } else { 2540 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 2541 // bits, just truncate to i32. 2542 if (NumSignBits > OpBits-MidBits) 2543 return DAG.getNode(ISD::TRUNCATE, VT, Op); 2544 } 2545 2546 // fold (sext (truncate x)) -> (sextinreg x). 2547 if (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 2548 N0.getValueType())) { 2549 if (Op.getValueType() < VT) 2550 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2551 else if (Op.getValueType() > VT) 2552 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2553 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op, 2554 DAG.getValueType(N0.getValueType())); 2555 } 2556 } 2557 2558 // fold (sext (load x)) -> (sext (truncate (sextload x))) 2559 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2560 (!AfterLegalize||TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType()))){ 2561 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2562 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2563 LN0->getBasePtr(), LN0->getSrcValue(), 2564 LN0->getSrcValueOffset(), 2565 N0.getValueType(), 2566 LN0->isVolatile(), 2567 LN0->getAlignment()); 2568 CombineTo(N, ExtLoad); 2569 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2570 ExtLoad.getValue(1)); 2571 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2572 } 2573 2574 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 2575 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 2576 if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && 2577 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) { 2578 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2579 MVT::ValueType EVT = LN0->getLoadedVT(); 2580 if (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) { 2581 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2582 LN0->getBasePtr(), LN0->getSrcValue(), 2583 LN0->getSrcValueOffset(), EVT, 2584 LN0->isVolatile(), 2585 LN0->getAlignment()); 2586 CombineTo(N, ExtLoad); 2587 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2588 ExtLoad.getValue(1)); 2589 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2590 } 2591 } 2592 2593 // sext(setcc x,y,cc) -> select_cc x, y, -1, 0, cc 2594 if (N0.getOpcode() == ISD::SETCC) { 2595 SDOperand SCC = 2596 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 2597 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT), 2598 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 2599 if (SCC.Val) return SCC; 2600 } 2601 2602 return SDOperand(); 2603} 2604 2605SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) { 2606 SDOperand N0 = N->getOperand(0); 2607 MVT::ValueType VT = N->getValueType(0); 2608 2609 // fold (zext c1) -> c1 2610 if (isa<ConstantSDNode>(N0)) 2611 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 2612 // fold (zext (zext x)) -> (zext x) 2613 // fold (zext (aext x)) -> (zext x) 2614 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2615 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0)); 2616 2617 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 2618 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 2619 if (N0.getOpcode() == ISD::TRUNCATE) { 2620 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2621 if (NarrowLoad.Val) { 2622 if (NarrowLoad.Val != N0.Val) 2623 CombineTo(N0.Val, NarrowLoad); 2624 return DAG.getNode(ISD::ZERO_EXTEND, VT, NarrowLoad); 2625 } 2626 } 2627 2628 // fold (zext (truncate x)) -> (and x, mask) 2629 if (N0.getOpcode() == ISD::TRUNCATE && 2630 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) { 2631 SDOperand Op = N0.getOperand(0); 2632 if (Op.getValueType() < VT) { 2633 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2634 } else if (Op.getValueType() > VT) { 2635 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2636 } 2637 return DAG.getZeroExtendInReg(Op, N0.getValueType()); 2638 } 2639 2640 // fold (zext (and (trunc x), cst)) -> (and x, cst). 2641 if (N0.getOpcode() == ISD::AND && 2642 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 2643 N0.getOperand(1).getOpcode() == ISD::Constant) { 2644 SDOperand X = N0.getOperand(0).getOperand(0); 2645 if (X.getValueType() < VT) { 2646 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 2647 } else if (X.getValueType() > VT) { 2648 X = DAG.getNode(ISD::TRUNCATE, VT, X); 2649 } 2650 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2651 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 2652 } 2653 2654 // fold (zext (load x)) -> (zext (truncate (zextload x))) 2655 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2656 (!AfterLegalize||TLI.isLoadXLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 2657 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2658 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 2659 LN0->getBasePtr(), LN0->getSrcValue(), 2660 LN0->getSrcValueOffset(), 2661 N0.getValueType(), 2662 LN0->isVolatile(), 2663 LN0->getAlignment()); 2664 CombineTo(N, ExtLoad); 2665 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2666 ExtLoad.getValue(1)); 2667 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2668 } 2669 2670 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 2671 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 2672 if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && 2673 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) { 2674 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2675 MVT::ValueType EVT = LN0->getLoadedVT(); 2676 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 2677 LN0->getBasePtr(), LN0->getSrcValue(), 2678 LN0->getSrcValueOffset(), EVT, 2679 LN0->isVolatile(), 2680 LN0->getAlignment()); 2681 CombineTo(N, ExtLoad); 2682 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2683 ExtLoad.getValue(1)); 2684 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2685 } 2686 2687 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 2688 if (N0.getOpcode() == ISD::SETCC) { 2689 SDOperand SCC = 2690 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 2691 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 2692 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 2693 if (SCC.Val) return SCC; 2694 } 2695 2696 return SDOperand(); 2697} 2698 2699SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) { 2700 SDOperand N0 = N->getOperand(0); 2701 MVT::ValueType VT = N->getValueType(0); 2702 2703 // fold (aext c1) -> c1 2704 if (isa<ConstantSDNode>(N0)) 2705 return DAG.getNode(ISD::ANY_EXTEND, VT, N0); 2706 // fold (aext (aext x)) -> (aext x) 2707 // fold (aext (zext x)) -> (zext x) 2708 // fold (aext (sext x)) -> (sext x) 2709 if (N0.getOpcode() == ISD::ANY_EXTEND || 2710 N0.getOpcode() == ISD::ZERO_EXTEND || 2711 N0.getOpcode() == ISD::SIGN_EXTEND) 2712 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 2713 2714 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 2715 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 2716 if (N0.getOpcode() == ISD::TRUNCATE) { 2717 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2718 if (NarrowLoad.Val) { 2719 if (NarrowLoad.Val != N0.Val) 2720 CombineTo(N0.Val, NarrowLoad); 2721 return DAG.getNode(ISD::ANY_EXTEND, VT, NarrowLoad); 2722 } 2723 } 2724 2725 // fold (aext (truncate x)) 2726 if (N0.getOpcode() == ISD::TRUNCATE) { 2727 SDOperand TruncOp = N0.getOperand(0); 2728 if (TruncOp.getValueType() == VT) 2729 return TruncOp; // x iff x size == zext size. 2730 if (TruncOp.getValueType() > VT) 2731 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp); 2732 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp); 2733 } 2734 2735 // fold (aext (and (trunc x), cst)) -> (and x, cst). 2736 if (N0.getOpcode() == ISD::AND && 2737 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 2738 N0.getOperand(1).getOpcode() == ISD::Constant) { 2739 SDOperand X = N0.getOperand(0).getOperand(0); 2740 if (X.getValueType() < VT) { 2741 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 2742 } else if (X.getValueType() > VT) { 2743 X = DAG.getNode(ISD::TRUNCATE, VT, X); 2744 } 2745 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2746 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 2747 } 2748 2749 // fold (aext (load x)) -> (aext (truncate (extload x))) 2750 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2751 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) { 2752 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2753 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 2754 LN0->getBasePtr(), LN0->getSrcValue(), 2755 LN0->getSrcValueOffset(), 2756 N0.getValueType(), 2757 LN0->isVolatile(), 2758 LN0->getAlignment()); 2759 CombineTo(N, ExtLoad); 2760 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2761 ExtLoad.getValue(1)); 2762 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2763 } 2764 2765 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 2766 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 2767 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 2768 if (N0.getOpcode() == ISD::LOAD && 2769 !ISD::isNON_EXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 2770 N0.hasOneUse()) { 2771 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2772 MVT::ValueType EVT = LN0->getLoadedVT(); 2773 SDOperand ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT, 2774 LN0->getChain(), LN0->getBasePtr(), 2775 LN0->getSrcValue(), 2776 LN0->getSrcValueOffset(), EVT, 2777 LN0->isVolatile(), 2778 LN0->getAlignment()); 2779 CombineTo(N, ExtLoad); 2780 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2781 ExtLoad.getValue(1)); 2782 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2783 } 2784 2785 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 2786 if (N0.getOpcode() == ISD::SETCC) { 2787 SDOperand SCC = 2788 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 2789 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 2790 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 2791 if (SCC.Val) 2792 return SCC; 2793 } 2794 2795 return SDOperand(); 2796} 2797 2798/// GetDemandedBits - See if the specified operand can be simplified with the 2799/// knowledge that only the bits specified by Mask are used. If so, return the 2800/// simpler operand, otherwise return a null SDOperand. 2801SDOperand DAGCombiner::GetDemandedBits(SDOperand V, uint64_t Mask) { 2802 switch (V.getOpcode()) { 2803 default: break; 2804 case ISD::OR: 2805 case ISD::XOR: 2806 // If the LHS or RHS don't contribute bits to the or, drop them. 2807 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 2808 return V.getOperand(1); 2809 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 2810 return V.getOperand(0); 2811 break; 2812 case ISD::SRL: 2813 // Only look at single-use SRLs. 2814 if (!V.Val->hasOneUse()) 2815 break; 2816 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 2817 // See if we can recursively simplify the LHS. 2818 unsigned Amt = RHSC->getValue(); 2819 Mask = (Mask << Amt) & MVT::getIntVTBitMask(V.getValueType()); 2820 SDOperand SimplifyLHS = GetDemandedBits(V.getOperand(0), Mask); 2821 if (SimplifyLHS.Val) { 2822 return DAG.getNode(ISD::SRL, V.getValueType(), 2823 SimplifyLHS, V.getOperand(1)); 2824 } 2825 } 2826 } 2827 return SDOperand(); 2828} 2829 2830/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 2831/// bits and then truncated to a narrower type and where N is a multiple 2832/// of number of bits of the narrower type, transform it to a narrower load 2833/// from address + N / num of bits of new type. If the result is to be 2834/// extended, also fold the extension to form a extending load. 2835SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) { 2836 unsigned Opc = N->getOpcode(); 2837 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 2838 SDOperand N0 = N->getOperand(0); 2839 MVT::ValueType VT = N->getValueType(0); 2840 MVT::ValueType EVT = N->getValueType(0); 2841 2842 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then 2843 // extended to VT. 2844 if (Opc == ISD::SIGN_EXTEND_INREG) { 2845 ExtType = ISD::SEXTLOAD; 2846 EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 2847 if (AfterLegalize && !TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) 2848 return SDOperand(); 2849 } 2850 2851 unsigned EVTBits = MVT::getSizeInBits(EVT); 2852 unsigned ShAmt = 0; 2853 bool CombineSRL = false; 2854 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 2855 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2856 ShAmt = N01->getValue(); 2857 // Is the shift amount a multiple of size of VT? 2858 if ((ShAmt & (EVTBits-1)) == 0) { 2859 N0 = N0.getOperand(0); 2860 if (MVT::getSizeInBits(N0.getValueType()) <= EVTBits) 2861 return SDOperand(); 2862 CombineSRL = true; 2863 } 2864 } 2865 } 2866 2867 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2868 // Do not allow folding to i1 here. i1 is implicitly stored in memory in 2869 // zero extended form: by shrinking the load, we lose track of the fact 2870 // that it is already zero extended. 2871 // FIXME: This should be reevaluated. 2872 VT != MVT::i1) { 2873 assert(MVT::getSizeInBits(N0.getValueType()) > EVTBits && 2874 "Cannot truncate to larger type!"); 2875 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2876 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 2877 // For big endian targets, we need to adjust the offset to the pointer to 2878 // load the correct bytes. 2879 if (!TLI.isLittleEndian()) 2880 ShAmt = MVT::getSizeInBits(N0.getValueType()) - ShAmt - EVTBits; 2881 uint64_t PtrOff = ShAmt / 8; 2882 SDOperand NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(), 2883 DAG.getConstant(PtrOff, PtrType)); 2884 AddToWorkList(NewPtr.Val); 2885 SDOperand Load = (ExtType == ISD::NON_EXTLOAD) 2886 ? DAG.getLoad(VT, LN0->getChain(), NewPtr, 2887 LN0->getSrcValue(), LN0->getSrcValueOffset(), 2888 LN0->isVolatile(), LN0->getAlignment()) 2889 : DAG.getExtLoad(ExtType, VT, LN0->getChain(), NewPtr, 2890 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT, 2891 LN0->isVolatile(), LN0->getAlignment()); 2892 AddToWorkList(N); 2893 if (CombineSRL) { 2894 std::vector<SDNode*> NowDead; 2895 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), NowDead); 2896 CombineTo(N->getOperand(0).Val, Load); 2897 } else 2898 CombineTo(N0.Val, Load, Load.getValue(1)); 2899 if (ShAmt) { 2900 if (Opc == ISD::SIGN_EXTEND_INREG) 2901 return DAG.getNode(Opc, VT, Load, N->getOperand(1)); 2902 else 2903 return DAG.getNode(Opc, VT, Load); 2904 } 2905 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2906 } 2907 2908 return SDOperand(); 2909} 2910 2911 2912SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 2913 SDOperand N0 = N->getOperand(0); 2914 SDOperand N1 = N->getOperand(1); 2915 MVT::ValueType VT = N->getValueType(0); 2916 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT(); 2917 unsigned EVTBits = MVT::getSizeInBits(EVT); 2918 2919 // fold (sext_in_reg c1) -> c1 2920 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 2921 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1); 2922 2923 // If the input is already sign extended, just drop the extension. 2924 if (DAG.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1) 2925 return N0; 2926 2927 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 2928 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 2929 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) { 2930 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); 2931 } 2932 2933 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 2934 if (DAG.MaskedValueIsZero(N0, 1ULL << (EVTBits-1))) 2935 return DAG.getZeroExtendInReg(N0, EVT); 2936 2937 // fold operands of sext_in_reg based on knowledge that the top bits are not 2938 // demanded. 2939 if (SimplifyDemandedBits(SDOperand(N, 0))) 2940 return SDOperand(N, 0); 2941 2942 // fold (sext_in_reg (load x)) -> (smaller sextload x) 2943 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 2944 SDOperand NarrowLoad = ReduceLoadWidth(N); 2945 if (NarrowLoad.Val) 2946 return NarrowLoad; 2947 2948 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24 2949 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible. 2950 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 2951 if (N0.getOpcode() == ISD::SRL) { 2952 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 2953 if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) { 2954 // We can turn this into an SRA iff the input to the SRL is already sign 2955 // extended enough. 2956 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 2957 if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits) 2958 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1)); 2959 } 2960 } 2961 2962 // fold (sext_inreg (extload x)) -> (sextload x) 2963 if (ISD::isEXTLoad(N0.Val) && 2964 ISD::isUNINDEXEDLoad(N0.Val) && 2965 EVT == cast<LoadSDNode>(N0)->getLoadedVT() && 2966 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) { 2967 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2968 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2969 LN0->getBasePtr(), LN0->getSrcValue(), 2970 LN0->getSrcValueOffset(), EVT, 2971 LN0->isVolatile(), 2972 LN0->getAlignment()); 2973 CombineTo(N, ExtLoad); 2974 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 2975 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2976 } 2977 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 2978 if (ISD::isZEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 2979 N0.hasOneUse() && 2980 EVT == cast<LoadSDNode>(N0)->getLoadedVT() && 2981 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) { 2982 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2983 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2984 LN0->getBasePtr(), LN0->getSrcValue(), 2985 LN0->getSrcValueOffset(), EVT, 2986 LN0->isVolatile(), 2987 LN0->getAlignment()); 2988 CombineTo(N, ExtLoad); 2989 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 2990 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2991 } 2992 return SDOperand(); 2993} 2994 2995SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) { 2996 SDOperand N0 = N->getOperand(0); 2997 MVT::ValueType VT = N->getValueType(0); 2998 2999 // noop truncate 3000 if (N0.getValueType() == N->getValueType(0)) 3001 return N0; 3002 // fold (truncate c1) -> c1 3003 if (isa<ConstantSDNode>(N0)) 3004 return DAG.getNode(ISD::TRUNCATE, VT, N0); 3005 // fold (truncate (truncate x)) -> (truncate x) 3006 if (N0.getOpcode() == ISD::TRUNCATE) 3007 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 3008 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 3009 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| 3010 N0.getOpcode() == ISD::ANY_EXTEND) { 3011 if (N0.getOperand(0).getValueType() < VT) 3012 // if the source is smaller than the dest, we still need an extend 3013 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 3014 else if (N0.getOperand(0).getValueType() > VT) 3015 // if the source is larger than the dest, than we just need the truncate 3016 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 3017 else 3018 // if the source and dest are the same type, we can drop both the extend 3019 // and the truncate 3020 return N0.getOperand(0); 3021 } 3022 3023 // See if we can simplify the input to this truncate through knowledge that 3024 // only the low bits are being used. For example "trunc (or (shl x, 8), y)" 3025 // -> trunc y 3026 SDOperand Shorter = GetDemandedBits(N0, MVT::getIntVTBitMask(VT)); 3027 if (Shorter.Val) 3028 return DAG.getNode(ISD::TRUNCATE, VT, Shorter); 3029 3030 // fold (truncate (load x)) -> (smaller load x) 3031 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 3032 return ReduceLoadWidth(N); 3033} 3034 3035SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) { 3036 SDOperand N0 = N->getOperand(0); 3037 MVT::ValueType VT = N->getValueType(0); 3038 3039 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 3040 // Only do this before legalize, since afterward the target may be depending 3041 // on the bitconvert. 3042 // First check to see if this is all constant. 3043 if (!AfterLegalize && 3044 N0.getOpcode() == ISD::BUILD_VECTOR && N0.Val->hasOneUse() && 3045 MVT::isVector(VT)) { 3046 bool isSimple = true; 3047 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 3048 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 3049 N0.getOperand(i).getOpcode() != ISD::Constant && 3050 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 3051 isSimple = false; 3052 break; 3053 } 3054 3055 MVT::ValueType DestEltVT = MVT::getVectorElementType(N->getValueType(0)); 3056 assert(!MVT::isVector(DestEltVT) && 3057 "Element type of vector ValueType must not be vector!"); 3058 if (isSimple) { 3059 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.Val, DestEltVT); 3060 } 3061 } 3062 3063 // If the input is a constant, let getNode() fold it. 3064 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 3065 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0); 3066 if (Res.Val != N) return Res; 3067 } 3068 3069 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2) 3070 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3071 3072 // fold (conv (load x)) -> (load (conv*)x) 3073 // If the resultant load doesn't need a higher alignment than the original! 3074 if (ISD::isNormalLoad(N0.Val) && N0.hasOneUse() && 3075 TLI.isOperationLegal(ISD::LOAD, VT)) { 3076 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3077 unsigned Align = TLI.getTargetMachine().getTargetData()-> 3078 getABITypeAlignment(MVT::getTypeForValueType(VT)); 3079 unsigned OrigAlign = LN0->getAlignment(); 3080 if (Align <= OrigAlign) { 3081 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(), 3082 LN0->getSrcValue(), LN0->getSrcValueOffset(), 3083 LN0->isVolatile(), Align); 3084 AddToWorkList(N); 3085 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load), 3086 Load.getValue(1)); 3087 return Load; 3088 } 3089 } 3090 3091 return SDOperand(); 3092} 3093 3094/// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector 3095/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 3096/// destination element value type. 3097SDOperand DAGCombiner:: 3098ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) { 3099 MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType(); 3100 3101 // If this is already the right type, we're done. 3102 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0); 3103 3104 unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT); 3105 unsigned DstBitSize = MVT::getSizeInBits(DstEltVT); 3106 3107 // If this is a conversion of N elements of one type to N elements of another 3108 // type, convert each element. This handles FP<->INT cases. 3109 if (SrcBitSize == DstBitSize) { 3110 SmallVector<SDOperand, 8> Ops; 3111 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3112 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i))); 3113 AddToWorkList(Ops.back().Val); 3114 } 3115 MVT::ValueType VT = 3116 MVT::getVectorType(DstEltVT, 3117 MVT::getVectorNumElements(BV->getValueType(0))); 3118 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3119 } 3120 3121 // Otherwise, we're growing or shrinking the elements. To avoid having to 3122 // handle annoying details of growing/shrinking FP values, we convert them to 3123 // int first. 3124 if (MVT::isFloatingPoint(SrcEltVT)) { 3125 // Convert the input float vector to a int vector where the elements are the 3126 // same sizes. 3127 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 3128 MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 3129 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).Val; 3130 SrcEltVT = IntVT; 3131 } 3132 3133 // Now we know the input is an integer vector. If the output is a FP type, 3134 // convert to integer first, then to FP of the right size. 3135 if (MVT::isFloatingPoint(DstEltVT)) { 3136 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 3137 MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 3138 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).Val; 3139 3140 // Next, convert to FP elements of the same size. 3141 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT); 3142 } 3143 3144 // Okay, we know the src/dst types are both integers of differing types. 3145 // Handling growing first. 3146 assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT)); 3147 if (SrcBitSize < DstBitSize) { 3148 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 3149 3150 SmallVector<SDOperand, 8> Ops; 3151 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 3152 i += NumInputsPerOutput) { 3153 bool isLE = TLI.isLittleEndian(); 3154 uint64_t NewBits = 0; 3155 bool EltIsUndef = true; 3156 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 3157 // Shift the previously computed bits over. 3158 NewBits <<= SrcBitSize; 3159 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 3160 if (Op.getOpcode() == ISD::UNDEF) continue; 3161 EltIsUndef = false; 3162 3163 NewBits |= cast<ConstantSDNode>(Op)->getValue(); 3164 } 3165 3166 if (EltIsUndef) 3167 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 3168 else 3169 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 3170 } 3171 3172 MVT::ValueType VT = MVT::getVectorType(DstEltVT, 3173 Ops.size()); 3174 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3175 } 3176 3177 // Finally, this must be the case where we are shrinking elements: each input 3178 // turns into multiple outputs. 3179 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 3180 SmallVector<SDOperand, 8> Ops; 3181 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3182 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 3183 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 3184 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 3185 continue; 3186 } 3187 uint64_t OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getValue(); 3188 3189 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 3190 unsigned ThisVal = OpVal & ((1ULL << DstBitSize)-1); 3191 OpVal >>= DstBitSize; 3192 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 3193 } 3194 3195 // For big endian targets, swap the order of the pieces of each element. 3196 if (!TLI.isLittleEndian()) 3197 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 3198 } 3199 MVT::ValueType VT = MVT::getVectorType(DstEltVT, Ops.size()); 3200 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3201} 3202 3203 3204 3205SDOperand DAGCombiner::visitFADD(SDNode *N) { 3206 SDOperand N0 = N->getOperand(0); 3207 SDOperand N1 = N->getOperand(1); 3208 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3209 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3210 MVT::ValueType VT = N->getValueType(0); 3211 3212 // fold vector ops 3213 if (MVT::isVector(VT)) { 3214 SDOperand FoldedVOp = SimplifyVBinOp(N); 3215 if (FoldedVOp.Val) return FoldedVOp; 3216 } 3217 3218 // fold (fadd c1, c2) -> c1+c2 3219 if (N0CFP && N1CFP) 3220 return DAG.getNode(ISD::FADD, VT, N0, N1); 3221 // canonicalize constant to RHS 3222 if (N0CFP && !N1CFP) 3223 return DAG.getNode(ISD::FADD, VT, N1, N0); 3224 // fold (A + (-B)) -> A-B 3225 if (isNegatibleForFree(N1) == 2) 3226 return DAG.getNode(ISD::FSUB, VT, N0, GetNegatedExpression(N1, DAG)); 3227 // fold ((-A) + B) -> B-A 3228 if (isNegatibleForFree(N0) == 2) 3229 return DAG.getNode(ISD::FSUB, VT, N1, GetNegatedExpression(N0, DAG)); 3230 3231 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 3232 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 3233 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3234 return DAG.getNode(ISD::FADD, VT, N0.getOperand(0), 3235 DAG.getNode(ISD::FADD, VT, N0.getOperand(1), N1)); 3236 3237 return SDOperand(); 3238} 3239 3240SDOperand DAGCombiner::visitFSUB(SDNode *N) { 3241 SDOperand N0 = N->getOperand(0); 3242 SDOperand N1 = N->getOperand(1); 3243 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3244 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3245 MVT::ValueType VT = N->getValueType(0); 3246 3247 // fold vector ops 3248 if (MVT::isVector(VT)) { 3249 SDOperand FoldedVOp = SimplifyVBinOp(N); 3250 if (FoldedVOp.Val) return FoldedVOp; 3251 } 3252 3253 // fold (fsub c1, c2) -> c1-c2 3254 if (N0CFP && N1CFP) 3255 return DAG.getNode(ISD::FSUB, VT, N0, N1); 3256 // fold (0-B) -> -B 3257 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { 3258 if (isNegatibleForFree(N1)) 3259 return GetNegatedExpression(N1, DAG); 3260 return DAG.getNode(ISD::FNEG, VT, N1); 3261 } 3262 // fold (A-(-B)) -> A+B 3263 if (isNegatibleForFree(N1)) 3264 return DAG.getNode(ISD::FADD, VT, N0, GetNegatedExpression(N1, DAG)); 3265 3266 return SDOperand(); 3267} 3268 3269SDOperand DAGCombiner::visitFMUL(SDNode *N) { 3270 SDOperand N0 = N->getOperand(0); 3271 SDOperand N1 = N->getOperand(1); 3272 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3273 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3274 MVT::ValueType VT = N->getValueType(0); 3275 3276 // fold vector ops 3277 if (MVT::isVector(VT)) { 3278 SDOperand FoldedVOp = SimplifyVBinOp(N); 3279 if (FoldedVOp.Val) return FoldedVOp; 3280 } 3281 3282 // fold (fmul c1, c2) -> c1*c2 3283 if (N0CFP && N1CFP) 3284 return DAG.getNode(ISD::FMUL, VT, N0, N1); 3285 // canonicalize constant to RHS 3286 if (N0CFP && !N1CFP) 3287 return DAG.getNode(ISD::FMUL, VT, N1, N0); 3288 // fold (fmul X, 2.0) -> (fadd X, X) 3289 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 3290 return DAG.getNode(ISD::FADD, VT, N0, N0); 3291 // fold (fmul X, -1.0) -> (fneg X) 3292 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 3293 return DAG.getNode(ISD::FNEG, VT, N0); 3294 3295 // -X * -Y -> X*Y 3296 if (char LHSNeg = isNegatibleForFree(N0)) { 3297 if (char RHSNeg = isNegatibleForFree(N1)) { 3298 // Both can be negated for free, check to see if at least one is cheaper 3299 // negated. 3300 if (LHSNeg == 2 || RHSNeg == 2) 3301 return DAG.getNode(ISD::FMUL, VT, GetNegatedExpression(N0, DAG), 3302 GetNegatedExpression(N1, DAG)); 3303 } 3304 } 3305 3306 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 3307 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 3308 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3309 return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0), 3310 DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1)); 3311 3312 return SDOperand(); 3313} 3314 3315SDOperand DAGCombiner::visitFDIV(SDNode *N) { 3316 SDOperand N0 = N->getOperand(0); 3317 SDOperand N1 = N->getOperand(1); 3318 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3319 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3320 MVT::ValueType VT = N->getValueType(0); 3321 3322 // fold vector ops 3323 if (MVT::isVector(VT)) { 3324 SDOperand FoldedVOp = SimplifyVBinOp(N); 3325 if (FoldedVOp.Val) return FoldedVOp; 3326 } 3327 3328 // fold (fdiv c1, c2) -> c1/c2 3329 if (N0CFP && N1CFP) 3330 return DAG.getNode(ISD::FDIV, VT, N0, N1); 3331 3332 3333 // -X / -Y -> X*Y 3334 if (char LHSNeg = isNegatibleForFree(N0)) { 3335 if (char RHSNeg = isNegatibleForFree(N1)) { 3336 // Both can be negated for free, check to see if at least one is cheaper 3337 // negated. 3338 if (LHSNeg == 2 || RHSNeg == 2) 3339 return DAG.getNode(ISD::FDIV, VT, GetNegatedExpression(N0, DAG), 3340 GetNegatedExpression(N1, DAG)); 3341 } 3342 } 3343 3344 return SDOperand(); 3345} 3346 3347SDOperand DAGCombiner::visitFREM(SDNode *N) { 3348 SDOperand N0 = N->getOperand(0); 3349 SDOperand N1 = N->getOperand(1); 3350 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3351 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3352 MVT::ValueType VT = N->getValueType(0); 3353 3354 // fold (frem c1, c2) -> fmod(c1,c2) 3355 if (N0CFP && N1CFP) 3356 return DAG.getNode(ISD::FREM, VT, N0, N1); 3357 3358 return SDOperand(); 3359} 3360 3361SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) { 3362 SDOperand N0 = N->getOperand(0); 3363 SDOperand N1 = N->getOperand(1); 3364 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3365 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3366 MVT::ValueType VT = N->getValueType(0); 3367 3368 if (N0CFP && N1CFP) // Constant fold 3369 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1); 3370 3371 if (N1CFP) { 3372 const APFloat& V = N1CFP->getValueAPF(); 3373 // copysign(x, c1) -> fabs(x) iff ispos(c1) 3374 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 3375 if (!V.isNegative()) 3376 return DAG.getNode(ISD::FABS, VT, N0); 3377 else 3378 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0)); 3379 } 3380 3381 // copysign(fabs(x), y) -> copysign(x, y) 3382 // copysign(fneg(x), y) -> copysign(x, y) 3383 // copysign(copysign(x,z), y) -> copysign(x, y) 3384 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 3385 N0.getOpcode() == ISD::FCOPYSIGN) 3386 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1); 3387 3388 // copysign(x, abs(y)) -> abs(x) 3389 if (N1.getOpcode() == ISD::FABS) 3390 return DAG.getNode(ISD::FABS, VT, N0); 3391 3392 // copysign(x, copysign(y,z)) -> copysign(x, z) 3393 if (N1.getOpcode() == ISD::FCOPYSIGN) 3394 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1)); 3395 3396 // copysign(x, fp_extend(y)) -> copysign(x, y) 3397 // copysign(x, fp_round(y)) -> copysign(x, y) 3398 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 3399 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0)); 3400 3401 return SDOperand(); 3402} 3403 3404 3405 3406SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) { 3407 SDOperand N0 = N->getOperand(0); 3408 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3409 MVT::ValueType VT = N->getValueType(0); 3410 3411 // fold (sint_to_fp c1) -> c1fp 3412 if (N0C) 3413 return DAG.getNode(ISD::SINT_TO_FP, VT, N0); 3414 return SDOperand(); 3415} 3416 3417SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) { 3418 SDOperand N0 = N->getOperand(0); 3419 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3420 MVT::ValueType VT = N->getValueType(0); 3421 3422 // fold (uint_to_fp c1) -> c1fp 3423 if (N0C) 3424 return DAG.getNode(ISD::UINT_TO_FP, VT, N0); 3425 return SDOperand(); 3426} 3427 3428SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) { 3429 SDOperand N0 = N->getOperand(0); 3430 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3431 MVT::ValueType VT = N->getValueType(0); 3432 3433 // fold (fp_to_sint c1fp) -> c1 3434 if (N0CFP) 3435 return DAG.getNode(ISD::FP_TO_SINT, VT, N0); 3436 return SDOperand(); 3437} 3438 3439SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) { 3440 SDOperand N0 = N->getOperand(0); 3441 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3442 MVT::ValueType VT = N->getValueType(0); 3443 3444 // fold (fp_to_uint c1fp) -> c1 3445 if (N0CFP) 3446 return DAG.getNode(ISD::FP_TO_UINT, VT, N0); 3447 return SDOperand(); 3448} 3449 3450SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) { 3451 SDOperand N0 = N->getOperand(0); 3452 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3453 MVT::ValueType VT = N->getValueType(0); 3454 3455 // fold (fp_round c1fp) -> c1fp 3456 if (N0CFP) 3457 return DAG.getNode(ISD::FP_ROUND, VT, N0); 3458 3459 // fold (fp_round (fp_extend x)) -> x 3460 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 3461 return N0.getOperand(0); 3462 3463 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 3464 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) { 3465 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0)); 3466 AddToWorkList(Tmp.Val); 3467 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1)); 3468 } 3469 3470 return SDOperand(); 3471} 3472 3473SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 3474 SDOperand N0 = N->getOperand(0); 3475 MVT::ValueType VT = N->getValueType(0); 3476 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3477 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3478 3479 // fold (fp_round_inreg c1fp) -> c1fp 3480 if (N0CFP) { 3481 SDOperand Round = DAG.getConstantFP(N0CFP->getValueAPF(), EVT); 3482 return DAG.getNode(ISD::FP_EXTEND, VT, Round); 3483 } 3484 return SDOperand(); 3485} 3486 3487SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) { 3488 SDOperand N0 = N->getOperand(0); 3489 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3490 MVT::ValueType VT = N->getValueType(0); 3491 3492 // fold (fp_extend c1fp) -> c1fp 3493 if (N0CFP) 3494 return DAG.getNode(ISD::FP_EXTEND, VT, N0); 3495 3496 // fold (fpext (load x)) -> (fpext (fpround (extload x))) 3497 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 3498 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) { 3499 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3500 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 3501 LN0->getBasePtr(), LN0->getSrcValue(), 3502 LN0->getSrcValueOffset(), 3503 N0.getValueType(), 3504 LN0->isVolatile(), 3505 LN0->getAlignment()); 3506 CombineTo(N, ExtLoad); 3507 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad), 3508 ExtLoad.getValue(1)); 3509 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3510 } 3511 3512 3513 return SDOperand(); 3514} 3515 3516SDOperand DAGCombiner::visitFNEG(SDNode *N) { 3517 SDOperand N0 = N->getOperand(0); 3518 3519 if (isNegatibleForFree(N0)) 3520 return GetNegatedExpression(N0, DAG); 3521 3522 return SDOperand(); 3523} 3524 3525SDOperand DAGCombiner::visitFABS(SDNode *N) { 3526 SDOperand N0 = N->getOperand(0); 3527 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3528 MVT::ValueType VT = N->getValueType(0); 3529 3530 // fold (fabs c1) -> fabs(c1) 3531 if (N0CFP) 3532 return DAG.getNode(ISD::FABS, VT, N0); 3533 // fold (fabs (fabs x)) -> (fabs x) 3534 if (N0.getOpcode() == ISD::FABS) 3535 return N->getOperand(0); 3536 // fold (fabs (fneg x)) -> (fabs x) 3537 // fold (fabs (fcopysign x, y)) -> (fabs x) 3538 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 3539 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0)); 3540 3541 return SDOperand(); 3542} 3543 3544SDOperand DAGCombiner::visitBRCOND(SDNode *N) { 3545 SDOperand Chain = N->getOperand(0); 3546 SDOperand N1 = N->getOperand(1); 3547 SDOperand N2 = N->getOperand(2); 3548 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3549 3550 // never taken branch, fold to chain 3551 if (N1C && N1C->isNullValue()) 3552 return Chain; 3553 // unconditional branch 3554 if (N1C && N1C->getValue() == 1) 3555 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 3556 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 3557 // on the target. 3558 if (N1.getOpcode() == ISD::SETCC && 3559 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) { 3560 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2), 3561 N1.getOperand(0), N1.getOperand(1), N2); 3562 } 3563 return SDOperand(); 3564} 3565 3566// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 3567// 3568SDOperand DAGCombiner::visitBR_CC(SDNode *N) { 3569 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 3570 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 3571 3572 // Use SimplifySetCC to simplify SETCC's. 3573 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false); 3574 if (Simp.Val) AddToWorkList(Simp.Val); 3575 3576 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val); 3577 3578 // fold br_cc true, dest -> br dest (unconditional branch) 3579 if (SCCC && SCCC->getValue()) 3580 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0), 3581 N->getOperand(4)); 3582 // fold br_cc false, dest -> unconditional fall through 3583 if (SCCC && SCCC->isNullValue()) 3584 return N->getOperand(0); 3585 3586 // fold to a simpler setcc 3587 if (Simp.Val && Simp.getOpcode() == ISD::SETCC) 3588 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0), 3589 Simp.getOperand(2), Simp.getOperand(0), 3590 Simp.getOperand(1), N->getOperand(4)); 3591 return SDOperand(); 3592} 3593 3594 3595/// CombineToPreIndexedLoadStore - Try turning a load / store and a 3596/// pre-indexed load / store when the base pointer is a add or subtract 3597/// and it has other uses besides the load / store. After the 3598/// transformation, the new indexed load / store has effectively folded 3599/// the add / subtract in and all of its other uses are redirected to the 3600/// new load / store. 3601bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 3602 if (!AfterLegalize) 3603 return false; 3604 3605 bool isLoad = true; 3606 SDOperand Ptr; 3607 MVT::ValueType VT; 3608 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 3609 if (LD->getAddressingMode() != ISD::UNINDEXED) 3610 return false; 3611 VT = LD->getLoadedVT(); 3612 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 3613 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 3614 return false; 3615 Ptr = LD->getBasePtr(); 3616 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 3617 if (ST->getAddressingMode() != ISD::UNINDEXED) 3618 return false; 3619 VT = ST->getStoredVT(); 3620 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 3621 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 3622 return false; 3623 Ptr = ST->getBasePtr(); 3624 isLoad = false; 3625 } else 3626 return false; 3627 3628 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 3629 // out. There is no reason to make this a preinc/predec. 3630 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 3631 Ptr.Val->hasOneUse()) 3632 return false; 3633 3634 // Ask the target to do addressing mode selection. 3635 SDOperand BasePtr; 3636 SDOperand Offset; 3637 ISD::MemIndexedMode AM = ISD::UNINDEXED; 3638 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 3639 return false; 3640 // Don't create a indexed load / store with zero offset. 3641 if (isa<ConstantSDNode>(Offset) && 3642 cast<ConstantSDNode>(Offset)->getValue() == 0) 3643 return false; 3644 3645 // Try turning it into a pre-indexed load / store except when: 3646 // 1) The new base ptr is a frame index. 3647 // 2) If N is a store and the new base ptr is either the same as or is a 3648 // predecessor of the value being stored. 3649 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 3650 // that would create a cycle. 3651 // 4) All uses are load / store ops that use it as old base ptr. 3652 3653 // Check #1. Preinc'ing a frame index would require copying the stack pointer 3654 // (plus the implicit offset) to a register to preinc anyway. 3655 if (isa<FrameIndexSDNode>(BasePtr)) 3656 return false; 3657 3658 // Check #2. 3659 if (!isLoad) { 3660 SDOperand Val = cast<StoreSDNode>(N)->getValue(); 3661 if (Val == BasePtr || BasePtr.Val->isPredecessor(Val.Val)) 3662 return false; 3663 } 3664 3665 // Now check for #3 and #4. 3666 bool RealUse = false; 3667 for (SDNode::use_iterator I = Ptr.Val->use_begin(), 3668 E = Ptr.Val->use_end(); I != E; ++I) { 3669 SDNode *Use = *I; 3670 if (Use == N) 3671 continue; 3672 if (Use->isPredecessor(N)) 3673 return false; 3674 3675 if (!((Use->getOpcode() == ISD::LOAD && 3676 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 3677 (Use->getOpcode() == ISD::STORE) && 3678 cast<StoreSDNode>(Use)->getBasePtr() == Ptr)) 3679 RealUse = true; 3680 } 3681 if (!RealUse) 3682 return false; 3683 3684 SDOperand Result; 3685 if (isLoad) 3686 Result = DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM); 3687 else 3688 Result = DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM); 3689 ++PreIndexedNodes; 3690 ++NodesCombined; 3691 DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG)); 3692 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG)); 3693 DOUT << '\n'; 3694 std::vector<SDNode*> NowDead; 3695 if (isLoad) { 3696 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0), 3697 NowDead); 3698 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2), 3699 NowDead); 3700 } else { 3701 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1), 3702 NowDead); 3703 } 3704 3705 // Nodes can end up on the worklist more than once. Make sure we do 3706 // not process a node that has been replaced. 3707 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 3708 removeFromWorkList(NowDead[i]); 3709 // Finally, since the node is now dead, remove it from the graph. 3710 DAG.DeleteNode(N); 3711 3712 // Replace the uses of Ptr with uses of the updated base value. 3713 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 3714 NowDead); 3715 removeFromWorkList(Ptr.Val); 3716 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 3717 removeFromWorkList(NowDead[i]); 3718 DAG.DeleteNode(Ptr.Val); 3719 3720 return true; 3721} 3722 3723/// CombineToPostIndexedLoadStore - Try combine a load / store with a 3724/// add / sub of the base pointer node into a post-indexed load / store. 3725/// The transformation folded the add / subtract into the new indexed 3726/// load / store effectively and all of its uses are redirected to the 3727/// new load / store. 3728bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 3729 if (!AfterLegalize) 3730 return false; 3731 3732 bool isLoad = true; 3733 SDOperand Ptr; 3734 MVT::ValueType VT; 3735 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 3736 if (LD->getAddressingMode() != ISD::UNINDEXED) 3737 return false; 3738 VT = LD->getLoadedVT(); 3739 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 3740 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 3741 return false; 3742 Ptr = LD->getBasePtr(); 3743 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 3744 if (ST->getAddressingMode() != ISD::UNINDEXED) 3745 return false; 3746 VT = ST->getStoredVT(); 3747 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 3748 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 3749 return false; 3750 Ptr = ST->getBasePtr(); 3751 isLoad = false; 3752 } else 3753 return false; 3754 3755 if (Ptr.Val->hasOneUse()) 3756 return false; 3757 3758 for (SDNode::use_iterator I = Ptr.Val->use_begin(), 3759 E = Ptr.Val->use_end(); I != E; ++I) { 3760 SDNode *Op = *I; 3761 if (Op == N || 3762 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 3763 continue; 3764 3765 SDOperand BasePtr; 3766 SDOperand Offset; 3767 ISD::MemIndexedMode AM = ISD::UNINDEXED; 3768 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 3769 if (Ptr == Offset) 3770 std::swap(BasePtr, Offset); 3771 if (Ptr != BasePtr) 3772 continue; 3773 // Don't create a indexed load / store with zero offset. 3774 if (isa<ConstantSDNode>(Offset) && 3775 cast<ConstantSDNode>(Offset)->getValue() == 0) 3776 continue; 3777 3778 // Try turning it into a post-indexed load / store except when 3779 // 1) All uses are load / store ops that use it as base ptr. 3780 // 2) Op must be independent of N, i.e. Op is neither a predecessor 3781 // nor a successor of N. Otherwise, if Op is folded that would 3782 // create a cycle. 3783 3784 // Check for #1. 3785 bool TryNext = false; 3786 for (SDNode::use_iterator II = BasePtr.Val->use_begin(), 3787 EE = BasePtr.Val->use_end(); II != EE; ++II) { 3788 SDNode *Use = *II; 3789 if (Use == Ptr.Val) 3790 continue; 3791 3792 // If all the uses are load / store addresses, then don't do the 3793 // transformation. 3794 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 3795 bool RealUse = false; 3796 for (SDNode::use_iterator III = Use->use_begin(), 3797 EEE = Use->use_end(); III != EEE; ++III) { 3798 SDNode *UseUse = *III; 3799 if (!((UseUse->getOpcode() == ISD::LOAD && 3800 cast<LoadSDNode>(UseUse)->getBasePtr().Val == Use) || 3801 (UseUse->getOpcode() == ISD::STORE) && 3802 cast<StoreSDNode>(UseUse)->getBasePtr().Val == Use)) 3803 RealUse = true; 3804 } 3805 3806 if (!RealUse) { 3807 TryNext = true; 3808 break; 3809 } 3810 } 3811 } 3812 if (TryNext) 3813 continue; 3814 3815 // Check for #2 3816 if (!Op->isPredecessor(N) && !N->isPredecessor(Op)) { 3817 SDOperand Result = isLoad 3818 ? DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM) 3819 : DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM); 3820 ++PostIndexedNodes; 3821 ++NodesCombined; 3822 DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG)); 3823 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG)); 3824 DOUT << '\n'; 3825 std::vector<SDNode*> NowDead; 3826 if (isLoad) { 3827 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0), 3828 NowDead); 3829 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2), 3830 NowDead); 3831 } else { 3832 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1), 3833 NowDead); 3834 } 3835 3836 // Nodes can end up on the worklist more than once. Make sure we do 3837 // not process a node that has been replaced. 3838 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 3839 removeFromWorkList(NowDead[i]); 3840 // Finally, since the node is now dead, remove it from the graph. 3841 DAG.DeleteNode(N); 3842 3843 // Replace the uses of Use with uses of the updated base value. 3844 DAG.ReplaceAllUsesOfValueWith(SDOperand(Op, 0), 3845 Result.getValue(isLoad ? 1 : 0), 3846 NowDead); 3847 removeFromWorkList(Op); 3848 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 3849 removeFromWorkList(NowDead[i]); 3850 DAG.DeleteNode(Op); 3851 3852 return true; 3853 } 3854 } 3855 } 3856 return false; 3857} 3858 3859 3860SDOperand DAGCombiner::visitLOAD(SDNode *N) { 3861 LoadSDNode *LD = cast<LoadSDNode>(N); 3862 SDOperand Chain = LD->getChain(); 3863 SDOperand Ptr = LD->getBasePtr(); 3864 3865 // If load is not volatile and there are no uses of the loaded value (and 3866 // the updated indexed value in case of indexed loads), change uses of the 3867 // chain value into uses of the chain input (i.e. delete the dead load). 3868 if (!LD->isVolatile()) { 3869 if (N->getValueType(1) == MVT::Other) { 3870 // Unindexed loads. 3871 if (N->hasNUsesOfValue(0, 0)) 3872 return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain); 3873 } else { 3874 // Indexed loads. 3875 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 3876 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 3877 SDOperand Undef0 = DAG.getNode(ISD::UNDEF, N->getValueType(0)); 3878 SDOperand Undef1 = DAG.getNode(ISD::UNDEF, N->getValueType(1)); 3879 SDOperand To[] = { Undef0, Undef1, Chain }; 3880 return CombineTo(N, To, 3); 3881 } 3882 } 3883 } 3884 3885 // If this load is directly stored, replace the load value with the stored 3886 // value. 3887 // TODO: Handle store large -> read small portion. 3888 // TODO: Handle TRUNCSTORE/LOADEXT 3889 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 3890 if (ISD::isNON_TRUNCStore(Chain.Val)) { 3891 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 3892 if (PrevST->getBasePtr() == Ptr && 3893 PrevST->getValue().getValueType() == N->getValueType(0)) 3894 return CombineTo(N, Chain.getOperand(1), Chain); 3895 } 3896 } 3897 3898 if (CombinerAA) { 3899 // Walk up chain skipping non-aliasing memory nodes. 3900 SDOperand BetterChain = FindBetterChain(N, Chain); 3901 3902 // If there is a better chain. 3903 if (Chain != BetterChain) { 3904 SDOperand ReplLoad; 3905 3906 // Replace the chain to void dependency. 3907 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 3908 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr, 3909 LD->getSrcValue(), LD->getSrcValueOffset(), 3910 LD->isVolatile(), LD->getAlignment()); 3911 } else { 3912 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), 3913 LD->getValueType(0), 3914 BetterChain, Ptr, LD->getSrcValue(), 3915 LD->getSrcValueOffset(), 3916 LD->getLoadedVT(), 3917 LD->isVolatile(), 3918 LD->getAlignment()); 3919 } 3920 3921 // Create token factor to keep old chain connected. 3922 SDOperand Token = DAG.getNode(ISD::TokenFactor, MVT::Other, 3923 Chain, ReplLoad.getValue(1)); 3924 3925 // Replace uses with load result and token factor. Don't add users 3926 // to work list. 3927 return CombineTo(N, ReplLoad.getValue(0), Token, false); 3928 } 3929 } 3930 3931 // Try transforming N to an indexed load. 3932 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 3933 return SDOperand(N, 0); 3934 3935 return SDOperand(); 3936} 3937 3938SDOperand DAGCombiner::visitSTORE(SDNode *N) { 3939 StoreSDNode *ST = cast<StoreSDNode>(N); 3940 SDOperand Chain = ST->getChain(); 3941 SDOperand Value = ST->getValue(); 3942 SDOperand Ptr = ST->getBasePtr(); 3943 3944 // If this is a store of a bit convert, store the input value if the 3945 // resultant store does not need a higher alignment than the original. 3946 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() && 3947 ST->getAddressingMode() == ISD::UNINDEXED) { 3948 unsigned Align = ST->getAlignment(); 3949 MVT::ValueType SVT = Value.getOperand(0).getValueType(); 3950 unsigned OrigAlign = TLI.getTargetMachine().getTargetData()-> 3951 getABITypeAlignment(MVT::getTypeForValueType(SVT)); 3952 if (Align <= OrigAlign && TLI.isOperationLegal(ISD::STORE, SVT)) 3953 return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), 3954 ST->getSrcValueOffset(), ST->isVolatile(), Align); 3955 } 3956 3957 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 3958 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 3959 if (Value.getOpcode() != ISD::TargetConstantFP) { 3960 SDOperand Tmp; 3961 switch (CFP->getValueType(0)) { 3962 default: assert(0 && "Unknown FP type"); 3963 case MVT::f80: // We don't do this for these yet. 3964 case MVT::f128: 3965 case MVT::ppcf128: 3966 break; 3967 case MVT::f32: 3968 if (!AfterLegalize || TLI.isTypeLegal(MVT::i32)) { 3969 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 3970 convertToAPInt().getZExtValue(), MVT::i32); 3971 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 3972 ST->getSrcValueOffset(), ST->isVolatile(), 3973 ST->getAlignment()); 3974 } 3975 break; 3976 case MVT::f64: 3977 if (!AfterLegalize || TLI.isTypeLegal(MVT::i64)) { 3978 Tmp = DAG.getConstant(CFP->getValueAPF().convertToAPInt(). 3979 getZExtValue(), MVT::i64); 3980 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 3981 ST->getSrcValueOffset(), ST->isVolatile(), 3982 ST->getAlignment()); 3983 } else if (TLI.isTypeLegal(MVT::i32)) { 3984 // Many FP stores are not make apparent until after legalize, e.g. for 3985 // argument passing. Since this is so common, custom legalize the 3986 // 64-bit integer store into two 32-bit stores. 3987 uint64_t Val = CFP->getValueAPF().convertToAPInt().getZExtValue(); 3988 SDOperand Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 3989 SDOperand Hi = DAG.getConstant(Val >> 32, MVT::i32); 3990 if (!TLI.isLittleEndian()) std::swap(Lo, Hi); 3991 3992 int SVOffset = ST->getSrcValueOffset(); 3993 unsigned Alignment = ST->getAlignment(); 3994 bool isVolatile = ST->isVolatile(); 3995 3996 SDOperand St0 = DAG.getStore(Chain, Lo, Ptr, ST->getSrcValue(), 3997 ST->getSrcValueOffset(), 3998 isVolatile, ST->getAlignment()); 3999 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 4000 DAG.getConstant(4, Ptr.getValueType())); 4001 SVOffset += 4; 4002 if (Alignment > 4) 4003 Alignment = 4; 4004 SDOperand St1 = DAG.getStore(Chain, Hi, Ptr, ST->getSrcValue(), 4005 SVOffset, isVolatile, Alignment); 4006 return DAG.getNode(ISD::TokenFactor, MVT::Other, St0, St1); 4007 } 4008 break; 4009 } 4010 } 4011 } 4012 4013 if (CombinerAA) { 4014 // Walk up chain skipping non-aliasing memory nodes. 4015 SDOperand BetterChain = FindBetterChain(N, Chain); 4016 4017 // If there is a better chain. 4018 if (Chain != BetterChain) { 4019 // Replace the chain to avoid dependency. 4020 SDOperand ReplStore; 4021 if (ST->isTruncatingStore()) { 4022 ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr, 4023 ST->getSrcValue(), ST->getSrcValueOffset(), ST->getStoredVT(), 4024 ST->isVolatile(), ST->getAlignment()); 4025 } else { 4026 ReplStore = DAG.getStore(BetterChain, Value, Ptr, 4027 ST->getSrcValue(), ST->getSrcValueOffset(), 4028 ST->isVolatile(), ST->getAlignment()); 4029 } 4030 4031 // Create token to keep both nodes around. 4032 SDOperand Token = 4033 DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore); 4034 4035 // Don't add users to work list. 4036 return CombineTo(N, Token, false); 4037 } 4038 } 4039 4040 // Try transforming N to an indexed store. 4041 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4042 return SDOperand(N, 0); 4043 4044 // FIXME: is there such a think as a truncating indexed store? 4045 if (ST->isTruncatingStore() && ST->getAddressingMode() == ISD::UNINDEXED && 4046 MVT::isInteger(Value.getValueType())) { 4047 // See if we can simplify the input to this truncstore with knowledge that 4048 // only the low bits are being used. For example: 4049 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 4050 SDOperand Shorter = 4051 GetDemandedBits(Value, MVT::getIntVTBitMask(ST->getStoredVT())); 4052 AddToWorkList(Value.Val); 4053 if (Shorter.Val) 4054 return DAG.getTruncStore(Chain, Shorter, Ptr, ST->getSrcValue(), 4055 ST->getSrcValueOffset(), ST->getStoredVT(), 4056 ST->isVolatile(), ST->getAlignment()); 4057 4058 // Otherwise, see if we can simplify the operation with 4059 // SimplifyDemandedBits, which only works if the value has a single use. 4060 if (SimplifyDemandedBits(Value, MVT::getIntVTBitMask(ST->getStoredVT()))) 4061 return SDOperand(N, 0); 4062 } 4063 4064 return SDOperand(); 4065} 4066 4067SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 4068 SDOperand InVec = N->getOperand(0); 4069 SDOperand InVal = N->getOperand(1); 4070 SDOperand EltNo = N->getOperand(2); 4071 4072 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 4073 // vector with the inserted element. 4074 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 4075 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 4076 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end()); 4077 if (Elt < Ops.size()) 4078 Ops[Elt] = InVal; 4079 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(), 4080 &Ops[0], Ops.size()); 4081 } 4082 4083 return SDOperand(); 4084} 4085 4086SDOperand DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 4087 SDOperand InVec = N->getOperand(0); 4088 SDOperand EltNo = N->getOperand(1); 4089 4090 // (vextract (v4f32 s2v (f32 load $addr)), 0) -> (f32 load $addr) 4091 // (vextract (v4i32 bc (v4f32 s2v (f32 load $addr))), 0) -> (i32 load $addr) 4092 if (isa<ConstantSDNode>(EltNo)) { 4093 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 4094 bool NewLoad = false; 4095 if (Elt == 0) { 4096 MVT::ValueType VT = InVec.getValueType(); 4097 MVT::ValueType EVT = MVT::getVectorElementType(VT); 4098 MVT::ValueType LVT = EVT; 4099 unsigned NumElts = MVT::getVectorNumElements(VT); 4100 if (InVec.getOpcode() == ISD::BIT_CONVERT) { 4101 MVT::ValueType BCVT = InVec.getOperand(0).getValueType(); 4102 if (NumElts != MVT::getVectorNumElements(BCVT)) 4103 return SDOperand(); 4104 InVec = InVec.getOperand(0); 4105 EVT = MVT::getVectorElementType(BCVT); 4106 NewLoad = true; 4107 } 4108 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 4109 InVec.getOperand(0).getValueType() == EVT && 4110 ISD::isNormalLoad(InVec.getOperand(0).Val) && 4111 InVec.getOperand(0).hasOneUse()) { 4112 LoadSDNode *LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 4113 unsigned Align = LN0->getAlignment(); 4114 if (NewLoad) { 4115 // Check the resultant load doesn't need a higher alignment than the 4116 // original load. 4117 unsigned NewAlign = TLI.getTargetMachine().getTargetData()-> 4118 getABITypeAlignment(MVT::getTypeForValueType(LVT)); 4119 if (!TLI.isOperationLegal(ISD::LOAD, LVT) || NewAlign > Align) 4120 return SDOperand(); 4121 Align = NewAlign; 4122 } 4123 4124 return DAG.getLoad(LVT, LN0->getChain(), LN0->getBasePtr(), 4125 LN0->getSrcValue(), LN0->getSrcValueOffset(), 4126 LN0->isVolatile(), Align); 4127 } 4128 } 4129 } 4130 return SDOperand(); 4131} 4132 4133 4134SDOperand DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 4135 unsigned NumInScalars = N->getNumOperands(); 4136 MVT::ValueType VT = N->getValueType(0); 4137 unsigned NumElts = MVT::getVectorNumElements(VT); 4138 MVT::ValueType EltType = MVT::getVectorElementType(VT); 4139 4140 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 4141 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 4142 // at most two distinct vectors, turn this into a shuffle node. 4143 SDOperand VecIn1, VecIn2; 4144 for (unsigned i = 0; i != NumInScalars; ++i) { 4145 // Ignore undef inputs. 4146 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 4147 4148 // If this input is something other than a EXTRACT_VECTOR_ELT with a 4149 // constant index, bail out. 4150 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 4151 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 4152 VecIn1 = VecIn2 = SDOperand(0, 0); 4153 break; 4154 } 4155 4156 // If the input vector type disagrees with the result of the build_vector, 4157 // we can't make a shuffle. 4158 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0); 4159 if (ExtractedFromVec.getValueType() != VT) { 4160 VecIn1 = VecIn2 = SDOperand(0, 0); 4161 break; 4162 } 4163 4164 // Otherwise, remember this. We allow up to two distinct input vectors. 4165 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 4166 continue; 4167 4168 if (VecIn1.Val == 0) { 4169 VecIn1 = ExtractedFromVec; 4170 } else if (VecIn2.Val == 0) { 4171 VecIn2 = ExtractedFromVec; 4172 } else { 4173 // Too many inputs. 4174 VecIn1 = VecIn2 = SDOperand(0, 0); 4175 break; 4176 } 4177 } 4178 4179 // If everything is good, we can make a shuffle operation. 4180 if (VecIn1.Val) { 4181 SmallVector<SDOperand, 8> BuildVecIndices; 4182 for (unsigned i = 0; i != NumInScalars; ++i) { 4183 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 4184 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, TLI.getPointerTy())); 4185 continue; 4186 } 4187 4188 SDOperand Extract = N->getOperand(i); 4189 4190 // If extracting from the first vector, just use the index directly. 4191 if (Extract.getOperand(0) == VecIn1) { 4192 BuildVecIndices.push_back(Extract.getOperand(1)); 4193 continue; 4194 } 4195 4196 // Otherwise, use InIdx + VecSize 4197 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue(); 4198 BuildVecIndices.push_back(DAG.getConstant(Idx+NumInScalars, 4199 TLI.getPointerTy())); 4200 } 4201 4202 // Add count and size info. 4203 MVT::ValueType BuildVecVT = 4204 MVT::getVectorType(TLI.getPointerTy(), NumElts); 4205 4206 // Return the new VECTOR_SHUFFLE node. 4207 SDOperand Ops[5]; 4208 Ops[0] = VecIn1; 4209 if (VecIn2.Val) { 4210 Ops[1] = VecIn2; 4211 } else { 4212 // Use an undef build_vector as input for the second operand. 4213 std::vector<SDOperand> UnOps(NumInScalars, 4214 DAG.getNode(ISD::UNDEF, 4215 EltType)); 4216 Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, VT, 4217 &UnOps[0], UnOps.size()); 4218 AddToWorkList(Ops[1].Val); 4219 } 4220 Ops[2] = DAG.getNode(ISD::BUILD_VECTOR, BuildVecVT, 4221 &BuildVecIndices[0], BuildVecIndices.size()); 4222 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Ops, 3); 4223 } 4224 4225 return SDOperand(); 4226} 4227 4228SDOperand DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 4229 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 4230 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 4231 // inputs come from at most two distinct vectors, turn this into a shuffle 4232 // node. 4233 4234 // If we only have one input vector, we don't need to do any concatenation. 4235 if (N->getNumOperands() == 1) { 4236 return N->getOperand(0); 4237 } 4238 4239 return SDOperand(); 4240} 4241 4242SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 4243 SDOperand ShufMask = N->getOperand(2); 4244 unsigned NumElts = ShufMask.getNumOperands(); 4245 4246 // If the shuffle mask is an identity operation on the LHS, return the LHS. 4247 bool isIdentity = true; 4248 for (unsigned i = 0; i != NumElts; ++i) { 4249 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 4250 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) { 4251 isIdentity = false; 4252 break; 4253 } 4254 } 4255 if (isIdentity) return N->getOperand(0); 4256 4257 // If the shuffle mask is an identity operation on the RHS, return the RHS. 4258 isIdentity = true; 4259 for (unsigned i = 0; i != NumElts; ++i) { 4260 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 4261 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) { 4262 isIdentity = false; 4263 break; 4264 } 4265 } 4266 if (isIdentity) return N->getOperand(1); 4267 4268 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not 4269 // needed at all. 4270 bool isUnary = true; 4271 bool isSplat = true; 4272 int VecNum = -1; 4273 unsigned BaseIdx = 0; 4274 for (unsigned i = 0; i != NumElts; ++i) 4275 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) { 4276 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue(); 4277 int V = (Idx < NumElts) ? 0 : 1; 4278 if (VecNum == -1) { 4279 VecNum = V; 4280 BaseIdx = Idx; 4281 } else { 4282 if (BaseIdx != Idx) 4283 isSplat = false; 4284 if (VecNum != V) { 4285 isUnary = false; 4286 break; 4287 } 4288 } 4289 } 4290 4291 SDOperand N0 = N->getOperand(0); 4292 SDOperand N1 = N->getOperand(1); 4293 // Normalize unary shuffle so the RHS is undef. 4294 if (isUnary && VecNum == 1) 4295 std::swap(N0, N1); 4296 4297 // If it is a splat, check if the argument vector is a build_vector with 4298 // all scalar elements the same. 4299 if (isSplat) { 4300 SDNode *V = N0.Val; 4301 4302 // If this is a bit convert that changes the element type of the vector but 4303 // not the number of vector elements, look through it. Be careful not to 4304 // look though conversions that change things like v4f32 to v2f64. 4305 if (V->getOpcode() == ISD::BIT_CONVERT) { 4306 SDOperand ConvInput = V->getOperand(0); 4307 if (MVT::getVectorNumElements(ConvInput.getValueType()) == NumElts) 4308 V = ConvInput.Val; 4309 } 4310 4311 if (V->getOpcode() == ISD::BUILD_VECTOR) { 4312 unsigned NumElems = V->getNumOperands(); 4313 if (NumElems > BaseIdx) { 4314 SDOperand Base; 4315 bool AllSame = true; 4316 for (unsigned i = 0; i != NumElems; ++i) { 4317 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 4318 Base = V->getOperand(i); 4319 break; 4320 } 4321 } 4322 // Splat of <u, u, u, u>, return <u, u, u, u> 4323 if (!Base.Val) 4324 return N0; 4325 for (unsigned i = 0; i != NumElems; ++i) { 4326 if (V->getOperand(i) != Base) { 4327 AllSame = false; 4328 break; 4329 } 4330 } 4331 // Splat of <x, x, x, x>, return <x, x, x, x> 4332 if (AllSame) 4333 return N0; 4334 } 4335 } 4336 } 4337 4338 // If it is a unary or the LHS and the RHS are the same node, turn the RHS 4339 // into an undef. 4340 if (isUnary || N0 == N1) { 4341 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the 4342 // first operand. 4343 SmallVector<SDOperand, 8> MappedOps; 4344 for (unsigned i = 0; i != NumElts; ++i) { 4345 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || 4346 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) { 4347 MappedOps.push_back(ShufMask.getOperand(i)); 4348 } else { 4349 unsigned NewIdx = 4350 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts; 4351 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32)); 4352 } 4353 } 4354 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(), 4355 &MappedOps[0], MappedOps.size()); 4356 AddToWorkList(ShufMask.Val); 4357 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0), 4358 N0, 4359 DAG.getNode(ISD::UNDEF, N->getValueType(0)), 4360 ShufMask); 4361 } 4362 4363 return SDOperand(); 4364} 4365 4366/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 4367/// an AND to a vector_shuffle with the destination vector and a zero vector. 4368/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 4369/// vector_shuffle V, Zero, <0, 4, 2, 4> 4370SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) { 4371 SDOperand LHS = N->getOperand(0); 4372 SDOperand RHS = N->getOperand(1); 4373 if (N->getOpcode() == ISD::AND) { 4374 if (RHS.getOpcode() == ISD::BIT_CONVERT) 4375 RHS = RHS.getOperand(0); 4376 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 4377 std::vector<SDOperand> IdxOps; 4378 unsigned NumOps = RHS.getNumOperands(); 4379 unsigned NumElts = NumOps; 4380 MVT::ValueType EVT = MVT::getVectorElementType(RHS.getValueType()); 4381 for (unsigned i = 0; i != NumElts; ++i) { 4382 SDOperand Elt = RHS.getOperand(i); 4383 if (!isa<ConstantSDNode>(Elt)) 4384 return SDOperand(); 4385 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 4386 IdxOps.push_back(DAG.getConstant(i, EVT)); 4387 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 4388 IdxOps.push_back(DAG.getConstant(NumElts, EVT)); 4389 else 4390 return SDOperand(); 4391 } 4392 4393 // Let's see if the target supports this vector_shuffle. 4394 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG)) 4395 return SDOperand(); 4396 4397 // Return the new VECTOR_SHUFFLE node. 4398 MVT::ValueType VT = MVT::getVectorType(EVT, NumElts); 4399 std::vector<SDOperand> Ops; 4400 LHS = DAG.getNode(ISD::BIT_CONVERT, VT, LHS); 4401 Ops.push_back(LHS); 4402 AddToWorkList(LHS.Val); 4403 std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT)); 4404 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT, 4405 &ZeroOps[0], ZeroOps.size())); 4406 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT, 4407 &IdxOps[0], IdxOps.size())); 4408 SDOperand Result = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, 4409 &Ops[0], Ops.size()); 4410 if (VT != LHS.getValueType()) { 4411 Result = DAG.getNode(ISD::BIT_CONVERT, LHS.getValueType(), Result); 4412 } 4413 return Result; 4414 } 4415 } 4416 return SDOperand(); 4417} 4418 4419/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 4420SDOperand DAGCombiner::SimplifyVBinOp(SDNode *N) { 4421 // After legalize, the target may be depending on adds and other 4422 // binary ops to provide legal ways to construct constants or other 4423 // things. Simplifying them may result in a loss of legality. 4424 if (AfterLegalize) return SDOperand(); 4425 4426 MVT::ValueType VT = N->getValueType(0); 4427 assert(MVT::isVector(VT) && "SimplifyVBinOp only works on vectors!"); 4428 4429 MVT::ValueType EltType = MVT::getVectorElementType(VT); 4430 SDOperand LHS = N->getOperand(0); 4431 SDOperand RHS = N->getOperand(1); 4432 SDOperand Shuffle = XformToShuffleWithZero(N); 4433 if (Shuffle.Val) return Shuffle; 4434 4435 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 4436 // this operation. 4437 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 4438 RHS.getOpcode() == ISD::BUILD_VECTOR) { 4439 SmallVector<SDOperand, 8> Ops; 4440 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 4441 SDOperand LHSOp = LHS.getOperand(i); 4442 SDOperand RHSOp = RHS.getOperand(i); 4443 // If these two elements can't be folded, bail out. 4444 if ((LHSOp.getOpcode() != ISD::UNDEF && 4445 LHSOp.getOpcode() != ISD::Constant && 4446 LHSOp.getOpcode() != ISD::ConstantFP) || 4447 (RHSOp.getOpcode() != ISD::UNDEF && 4448 RHSOp.getOpcode() != ISD::Constant && 4449 RHSOp.getOpcode() != ISD::ConstantFP)) 4450 break; 4451 // Can't fold divide by zero. 4452 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 4453 N->getOpcode() == ISD::FDIV) { 4454 if ((RHSOp.getOpcode() == ISD::Constant && 4455 cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) || 4456 (RHSOp.getOpcode() == ISD::ConstantFP && 4457 cast<ConstantFPSDNode>(RHSOp.Val)->getValueAPF().isZero())) 4458 break; 4459 } 4460 Ops.push_back(DAG.getNode(N->getOpcode(), EltType, LHSOp, RHSOp)); 4461 AddToWorkList(Ops.back().Val); 4462 assert((Ops.back().getOpcode() == ISD::UNDEF || 4463 Ops.back().getOpcode() == ISD::Constant || 4464 Ops.back().getOpcode() == ISD::ConstantFP) && 4465 "Scalar binop didn't fold!"); 4466 } 4467 4468 if (Ops.size() == LHS.getNumOperands()) { 4469 MVT::ValueType VT = LHS.getValueType(); 4470 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 4471 } 4472 } 4473 4474 return SDOperand(); 4475} 4476 4477SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){ 4478 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 4479 4480 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2, 4481 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4482 // If we got a simplified select_cc node back from SimplifySelectCC, then 4483 // break it down into a new SETCC node, and a new SELECT node, and then return 4484 // the SELECT node, since we were called with a SELECT node. 4485 if (SCC.Val) { 4486 // Check to see if we got a select_cc back (to turn into setcc/select). 4487 // Otherwise, just return whatever node we got back, like fabs. 4488 if (SCC.getOpcode() == ISD::SELECT_CC) { 4489 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(), 4490 SCC.getOperand(0), SCC.getOperand(1), 4491 SCC.getOperand(4)); 4492 AddToWorkList(SETCC.Val); 4493 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2), 4494 SCC.getOperand(3), SETCC); 4495 } 4496 return SCC; 4497 } 4498 return SDOperand(); 4499} 4500 4501/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 4502/// are the two values being selected between, see if we can simplify the 4503/// select. Callers of this should assume that TheSelect is deleted if this 4504/// returns true. As such, they should return the appropriate thing (e.g. the 4505/// node) back to the top-level of the DAG combiner loop to avoid it being 4506/// looked at. 4507/// 4508bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS, 4509 SDOperand RHS) { 4510 4511 // If this is a select from two identical things, try to pull the operation 4512 // through the select. 4513 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 4514 // If this is a load and the token chain is identical, replace the select 4515 // of two loads with a load through a select of the address to load from. 4516 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 4517 // constants have been dropped into the constant pool. 4518 if (LHS.getOpcode() == ISD::LOAD && 4519 // Token chains must be identical. 4520 LHS.getOperand(0) == RHS.getOperand(0)) { 4521 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 4522 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 4523 4524 // If this is an EXTLOAD, the VT's must match. 4525 if (LLD->getLoadedVT() == RLD->getLoadedVT()) { 4526 // FIXME: this conflates two src values, discarding one. This is not 4527 // the right thing to do, but nothing uses srcvalues now. When they do, 4528 // turn SrcValue into a list of locations. 4529 SDOperand Addr; 4530 if (TheSelect->getOpcode() == ISD::SELECT) { 4531 // Check that the condition doesn't reach either load. If so, folding 4532 // this will induce a cycle into the DAG. 4533 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) && 4534 !RLD->isPredecessor(TheSelect->getOperand(0).Val)) { 4535 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(), 4536 TheSelect->getOperand(0), LLD->getBasePtr(), 4537 RLD->getBasePtr()); 4538 } 4539 } else { 4540 // Check that the condition doesn't reach either load. If so, folding 4541 // this will induce a cycle into the DAG. 4542 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) && 4543 !RLD->isPredecessor(TheSelect->getOperand(0).Val) && 4544 !LLD->isPredecessor(TheSelect->getOperand(1).Val) && 4545 !RLD->isPredecessor(TheSelect->getOperand(1).Val)) { 4546 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(), 4547 TheSelect->getOperand(0), 4548 TheSelect->getOperand(1), 4549 LLD->getBasePtr(), RLD->getBasePtr(), 4550 TheSelect->getOperand(4)); 4551 } 4552 } 4553 4554 if (Addr.Val) { 4555 SDOperand Load; 4556 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) 4557 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(), 4558 Addr,LLD->getSrcValue(), 4559 LLD->getSrcValueOffset(), 4560 LLD->isVolatile(), 4561 LLD->getAlignment()); 4562 else { 4563 Load = DAG.getExtLoad(LLD->getExtensionType(), 4564 TheSelect->getValueType(0), 4565 LLD->getChain(), Addr, LLD->getSrcValue(), 4566 LLD->getSrcValueOffset(), 4567 LLD->getLoadedVT(), 4568 LLD->isVolatile(), 4569 LLD->getAlignment()); 4570 } 4571 // Users of the select now use the result of the load. 4572 CombineTo(TheSelect, Load); 4573 4574 // Users of the old loads now use the new load's chain. We know the 4575 // old-load value is dead now. 4576 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1)); 4577 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1)); 4578 return true; 4579 } 4580 } 4581 } 4582 } 4583 4584 return false; 4585} 4586 4587SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1, 4588 SDOperand N2, SDOperand N3, 4589 ISD::CondCode CC, bool NotExtCompare) { 4590 4591 MVT::ValueType VT = N2.getValueType(); 4592 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 4593 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 4594 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 4595 4596 // Determine if the condition we're dealing with is constant 4597 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 4598 if (SCC.Val) AddToWorkList(SCC.Val); 4599 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 4600 4601 // fold select_cc true, x, y -> x 4602 if (SCCC && SCCC->getValue()) 4603 return N2; 4604 // fold select_cc false, x, y -> y 4605 if (SCCC && SCCC->getValue() == 0) 4606 return N3; 4607 4608 // Check to see if we can simplify the select into an fabs node 4609 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 4610 // Allow either -0.0 or 0.0 4611 if (CFP->getValueAPF().isZero()) { 4612 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 4613 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 4614 N0 == N2 && N3.getOpcode() == ISD::FNEG && 4615 N2 == N3.getOperand(0)) 4616 return DAG.getNode(ISD::FABS, VT, N0); 4617 4618 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 4619 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 4620 N0 == N3 && N2.getOpcode() == ISD::FNEG && 4621 N2.getOperand(0) == N3) 4622 return DAG.getNode(ISD::FABS, VT, N3); 4623 } 4624 } 4625 4626 // Check to see if we can perform the "gzip trick", transforming 4627 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 4628 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 4629 MVT::isInteger(N0.getValueType()) && 4630 MVT::isInteger(N2.getValueType()) && 4631 (N1C->isNullValue() || // (a < 0) ? b : 0 4632 (N1C->getValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 4633 MVT::ValueType XType = N0.getValueType(); 4634 MVT::ValueType AType = N2.getValueType(); 4635 if (XType >= AType) { 4636 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 4637 // single-bit constant. 4638 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) { 4639 unsigned ShCtV = Log2_64(N2C->getValue()); 4640 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1; 4641 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy()); 4642 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt); 4643 AddToWorkList(Shift.Val); 4644 if (XType > AType) { 4645 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 4646 AddToWorkList(Shift.Val); 4647 } 4648 return DAG.getNode(ISD::AND, AType, Shift, N2); 4649 } 4650 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 4651 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4652 TLI.getShiftAmountTy())); 4653 AddToWorkList(Shift.Val); 4654 if (XType > AType) { 4655 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 4656 AddToWorkList(Shift.Val); 4657 } 4658 return DAG.getNode(ISD::AND, AType, Shift, N2); 4659 } 4660 } 4661 4662 // fold select C, 16, 0 -> shl C, 4 4663 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) && 4664 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) { 4665 4666 // If the caller doesn't want us to simplify this into a zext of a compare, 4667 // don't do it. 4668 if (NotExtCompare && N2C->getValue() == 1) 4669 return SDOperand(); 4670 4671 // Get a SetCC of the condition 4672 // FIXME: Should probably make sure that setcc is legal if we ever have a 4673 // target where it isn't. 4674 SDOperand Temp, SCC; 4675 // cast from setcc result type to select result type 4676 if (AfterLegalize) { 4677 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 4678 if (N2.getValueType() < SCC.getValueType()) 4679 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType()); 4680 else 4681 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 4682 } else { 4683 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC); 4684 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 4685 } 4686 AddToWorkList(SCC.Val); 4687 AddToWorkList(Temp.Val); 4688 4689 if (N2C->getValue() == 1) 4690 return Temp; 4691 // shl setcc result by log2 n2c 4692 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp, 4693 DAG.getConstant(Log2_64(N2C->getValue()), 4694 TLI.getShiftAmountTy())); 4695 } 4696 4697 // Check to see if this is the equivalent of setcc 4698 // FIXME: Turn all of these into setcc if setcc if setcc is legal 4699 // otherwise, go ahead with the folds. 4700 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) { 4701 MVT::ValueType XType = N0.getValueType(); 4702 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) { 4703 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 4704 if (Res.getValueType() != VT) 4705 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res); 4706 return Res; 4707 } 4708 4709 // seteq X, 0 -> srl (ctlz X, log2(size(X))) 4710 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 4711 TLI.isOperationLegal(ISD::CTLZ, XType)) { 4712 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0); 4713 return DAG.getNode(ISD::SRL, XType, Ctlz, 4714 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)), 4715 TLI.getShiftAmountTy())); 4716 } 4717 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) 4718 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 4719 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType), 4720 N0); 4721 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0, 4722 DAG.getConstant(~0ULL, XType)); 4723 return DAG.getNode(ISD::SRL, XType, 4724 DAG.getNode(ISD::AND, XType, NegN0, NotN0), 4725 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4726 TLI.getShiftAmountTy())); 4727 } 4728 // setgt X, -1 -> xor (srl (X, size(X)-1), 1) 4729 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 4730 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0, 4731 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4732 TLI.getShiftAmountTy())); 4733 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType)); 4734 } 4735 } 4736 4737 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 4738 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 4739 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 4740 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) && 4741 N2.getOperand(0) == N1 && MVT::isInteger(N0.getValueType())) { 4742 MVT::ValueType XType = N0.getValueType(); 4743 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 4744 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4745 TLI.getShiftAmountTy())); 4746 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 4747 AddToWorkList(Shift.Val); 4748 AddToWorkList(Add.Val); 4749 return DAG.getNode(ISD::XOR, XType, Add, Shift); 4750 } 4751 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X -> 4752 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 4753 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT && 4754 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) { 4755 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 4756 MVT::ValueType XType = N0.getValueType(); 4757 if (SubC->isNullValue() && MVT::isInteger(XType)) { 4758 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 4759 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4760 TLI.getShiftAmountTy())); 4761 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 4762 AddToWorkList(Shift.Val); 4763 AddToWorkList(Add.Val); 4764 return DAG.getNode(ISD::XOR, XType, Add, Shift); 4765 } 4766 } 4767 } 4768 4769 return SDOperand(); 4770} 4771 4772/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 4773SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0, 4774 SDOperand N1, ISD::CondCode Cond, 4775 bool foldBooleans) { 4776 TargetLowering::DAGCombinerInfo 4777 DagCombineInfo(DAG, !AfterLegalize, false, this); 4778 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo); 4779} 4780 4781/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 4782/// return a DAG expression to select that will generate the same value by 4783/// multiplying by a magic number. See: 4784/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 4785SDOperand DAGCombiner::BuildSDIV(SDNode *N) { 4786 std::vector<SDNode*> Built; 4787 SDOperand S = TLI.BuildSDIV(N, DAG, &Built); 4788 4789 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 4790 ii != ee; ++ii) 4791 AddToWorkList(*ii); 4792 return S; 4793} 4794 4795/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 4796/// return a DAG expression to select that will generate the same value by 4797/// multiplying by a magic number. See: 4798/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 4799SDOperand DAGCombiner::BuildUDIV(SDNode *N) { 4800 std::vector<SDNode*> Built; 4801 SDOperand S = TLI.BuildUDIV(N, DAG, &Built); 4802 4803 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 4804 ii != ee; ++ii) 4805 AddToWorkList(*ii); 4806 return S; 4807} 4808 4809/// FindBaseOffset - Return true if base is known not to alias with anything 4810/// but itself. Provides base object and offset as results. 4811static bool FindBaseOffset(SDOperand Ptr, SDOperand &Base, int64_t &Offset) { 4812 // Assume it is a primitive operation. 4813 Base = Ptr; Offset = 0; 4814 4815 // If it's an adding a simple constant then integrate the offset. 4816 if (Base.getOpcode() == ISD::ADD) { 4817 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 4818 Base = Base.getOperand(0); 4819 Offset += C->getValue(); 4820 } 4821 } 4822 4823 // If it's any of the following then it can't alias with anything but itself. 4824 return isa<FrameIndexSDNode>(Base) || 4825 isa<ConstantPoolSDNode>(Base) || 4826 isa<GlobalAddressSDNode>(Base); 4827} 4828 4829/// isAlias - Return true if there is any possibility that the two addresses 4830/// overlap. 4831bool DAGCombiner::isAlias(SDOperand Ptr1, int64_t Size1, 4832 const Value *SrcValue1, int SrcValueOffset1, 4833 SDOperand Ptr2, int64_t Size2, 4834 const Value *SrcValue2, int SrcValueOffset2) 4835{ 4836 // If they are the same then they must be aliases. 4837 if (Ptr1 == Ptr2) return true; 4838 4839 // Gather base node and offset information. 4840 SDOperand Base1, Base2; 4841 int64_t Offset1, Offset2; 4842 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1); 4843 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2); 4844 4845 // If they have a same base address then... 4846 if (Base1 == Base2) { 4847 // Check to see if the addresses overlap. 4848 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 4849 } 4850 4851 // If we know both bases then they can't alias. 4852 if (KnownBase1 && KnownBase2) return false; 4853 4854 if (CombinerGlobalAA) { 4855 // Use alias analysis information. 4856 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 4857 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 4858 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 4859 AliasAnalysis::AliasResult AAResult = 4860 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2); 4861 if (AAResult == AliasAnalysis::NoAlias) 4862 return false; 4863 } 4864 4865 // Otherwise we have to assume they alias. 4866 return true; 4867} 4868 4869/// FindAliasInfo - Extracts the relevant alias information from the memory 4870/// node. Returns true if the operand was a load. 4871bool DAGCombiner::FindAliasInfo(SDNode *N, 4872 SDOperand &Ptr, int64_t &Size, 4873 const Value *&SrcValue, int &SrcValueOffset) { 4874 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4875 Ptr = LD->getBasePtr(); 4876 Size = MVT::getSizeInBits(LD->getLoadedVT()) >> 3; 4877 SrcValue = LD->getSrcValue(); 4878 SrcValueOffset = LD->getSrcValueOffset(); 4879 return true; 4880 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4881 Ptr = ST->getBasePtr(); 4882 Size = MVT::getSizeInBits(ST->getStoredVT()) >> 3; 4883 SrcValue = ST->getSrcValue(); 4884 SrcValueOffset = ST->getSrcValueOffset(); 4885 } else { 4886 assert(0 && "FindAliasInfo expected a memory operand"); 4887 } 4888 4889 return false; 4890} 4891 4892/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 4893/// looking for aliasing nodes and adding them to the Aliases vector. 4894void DAGCombiner::GatherAllAliases(SDNode *N, SDOperand OriginalChain, 4895 SmallVector<SDOperand, 8> &Aliases) { 4896 SmallVector<SDOperand, 8> Chains; // List of chains to visit. 4897 std::set<SDNode *> Visited; // Visited node set. 4898 4899 // Get alias information for node. 4900 SDOperand Ptr; 4901 int64_t Size; 4902 const Value *SrcValue; 4903 int SrcValueOffset; 4904 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset); 4905 4906 // Starting off. 4907 Chains.push_back(OriginalChain); 4908 4909 // Look at each chain and determine if it is an alias. If so, add it to the 4910 // aliases list. If not, then continue up the chain looking for the next 4911 // candidate. 4912 while (!Chains.empty()) { 4913 SDOperand Chain = Chains.back(); 4914 Chains.pop_back(); 4915 4916 // Don't bother if we've been before. 4917 if (Visited.find(Chain.Val) != Visited.end()) continue; 4918 Visited.insert(Chain.Val); 4919 4920 switch (Chain.getOpcode()) { 4921 case ISD::EntryToken: 4922 // Entry token is ideal chain operand, but handled in FindBetterChain. 4923 break; 4924 4925 case ISD::LOAD: 4926 case ISD::STORE: { 4927 // Get alias information for Chain. 4928 SDOperand OpPtr; 4929 int64_t OpSize; 4930 const Value *OpSrcValue; 4931 int OpSrcValueOffset; 4932 bool IsOpLoad = FindAliasInfo(Chain.Val, OpPtr, OpSize, 4933 OpSrcValue, OpSrcValueOffset); 4934 4935 // If chain is alias then stop here. 4936 if (!(IsLoad && IsOpLoad) && 4937 isAlias(Ptr, Size, SrcValue, SrcValueOffset, 4938 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) { 4939 Aliases.push_back(Chain); 4940 } else { 4941 // Look further up the chain. 4942 Chains.push_back(Chain.getOperand(0)); 4943 // Clean up old chain. 4944 AddToWorkList(Chain.Val); 4945 } 4946 break; 4947 } 4948 4949 case ISD::TokenFactor: 4950 // We have to check each of the operands of the token factor, so we queue 4951 // then up. Adding the operands to the queue (stack) in reverse order 4952 // maintains the original order and increases the likelihood that getNode 4953 // will find a matching token factor (CSE.) 4954 for (unsigned n = Chain.getNumOperands(); n;) 4955 Chains.push_back(Chain.getOperand(--n)); 4956 // Eliminate the token factor if we can. 4957 AddToWorkList(Chain.Val); 4958 break; 4959 4960 default: 4961 // For all other instructions we will just have to take what we can get. 4962 Aliases.push_back(Chain); 4963 break; 4964 } 4965 } 4966} 4967 4968/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 4969/// for a better chain (aliasing node.) 4970SDOperand DAGCombiner::FindBetterChain(SDNode *N, SDOperand OldChain) { 4971 SmallVector<SDOperand, 8> Aliases; // Ops for replacing token factor. 4972 4973 // Accumulate all the aliases to this node. 4974 GatherAllAliases(N, OldChain, Aliases); 4975 4976 if (Aliases.size() == 0) { 4977 // If no operands then chain to entry token. 4978 return DAG.getEntryNode(); 4979 } else if (Aliases.size() == 1) { 4980 // If a single operand then chain to it. We don't need to revisit it. 4981 return Aliases[0]; 4982 } 4983 4984 // Construct a custom tailored token factor. 4985 SDOperand NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 4986 &Aliases[0], Aliases.size()); 4987 4988 // Make sure the old chain gets cleaned up. 4989 if (NewChain != OldChain) AddToWorkList(OldChain.Val); 4990 4991 return NewChain; 4992} 4993 4994// SelectionDAG::Combine - This is the entry point for the file. 4995// 4996void SelectionDAG::Combine(bool RunningAfterLegalize, AliasAnalysis &AA) { 4997 if (!RunningAfterLegalize && ViewDAGCombine1) 4998 viewGraph(); 4999 if (RunningAfterLegalize && ViewDAGCombine2) 5000 viewGraph(); 5001 /// run - This is the main entry point to this class. 5002 /// 5003 DAGCombiner(*this, AA).Run(RunningAfterLegalize); 5004} 5005