DAGCombiner.cpp revision bab9239d0572d35a08423782eb964e532c3c6524
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Nate Begeman and is distributed under the 6// University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// FIXME: Missing folds 14// sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into 15// a sequence of multiplies, shifts, and adds. This should be controlled by 16// some kind of hint from the target that int div is expensive. 17// various folds of mulh[s,u] by constants such as -1, powers of 2, etc. 18// 19// FIXME: Should add a corresponding version of fold AND with 20// ZERO_EXTEND/SIGN_EXTEND by converting them to an ANY_EXTEND node which 21// we don't have yet. 22// 23// FIXME: select C, pow2, pow2 -> something smart 24// FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z) 25// FIXME: Dead stores -> nuke 26// FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!) 27// FIXME: mul (x, const) -> shifts + adds 28// FIXME: undef values 29// FIXME: make truncate see through SIGN_EXTEND and AND 30// FIXME: (sra (sra x, c1), c2) -> (sra x, c1+c2) 31// FIXME: verify that getNode can't return extends with an operand whose type 32// is >= to that of the extend. 33// FIXME: divide by zero is currently left unfolded. do we want to turn this 34// into an undef? 35// FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false 36// 37//===----------------------------------------------------------------------===// 38 39#define DEBUG_TYPE "dagcombine" 40#include "llvm/ADT/Statistic.h" 41#include "llvm/CodeGen/SelectionDAG.h" 42#include "llvm/Support/Debug.h" 43#include "llvm/Support/MathExtras.h" 44#include "llvm/Target/TargetLowering.h" 45#include <algorithm> 46#include <cmath> 47#include <iostream> 48using namespace llvm; 49 50namespace { 51 Statistic<> NodesCombined ("dagcombiner", "Number of dag nodes combined"); 52 53 class DAGCombiner { 54 SelectionDAG &DAG; 55 TargetLowering &TLI; 56 bool AfterLegalize; 57 58 // Worklist of all of the nodes that need to be simplified. 59 std::vector<SDNode*> WorkList; 60 61 /// AddUsersToWorkList - When an instruction is simplified, add all users of 62 /// the instruction to the work lists because they might get more simplified 63 /// now. 64 /// 65 void AddUsersToWorkList(SDNode *N) { 66 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 67 UI != UE; ++UI) 68 WorkList.push_back(*UI); 69 } 70 71 /// removeFromWorkList - remove all instances of N from the worklist. 72 void removeFromWorkList(SDNode *N) { 73 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 74 WorkList.end()); 75 } 76 77 SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To) { 78 ++NodesCombined; 79 DEBUG(std::cerr << "\nReplacing "; N->dump(); 80 std::cerr << "\nWith: "; To[0].Val->dump(); 81 std::cerr << " and " << To.size()-1 << " other values\n"); 82 std::vector<SDNode*> NowDead; 83 DAG.ReplaceAllUsesWith(N, To, &NowDead); 84 85 // Push the new nodes and any users onto the worklist 86 for (unsigned i = 0, e = To.size(); i != e; ++i) { 87 WorkList.push_back(To[i].Val); 88 AddUsersToWorkList(To[i].Val); 89 } 90 91 // Nodes can end up on the worklist more than once. Make sure we do 92 // not process a node that has been replaced. 93 removeFromWorkList(N); 94 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 95 removeFromWorkList(NowDead[i]); 96 97 // Finally, since the node is now dead, remove it from the graph. 98 DAG.DeleteNode(N); 99 return SDOperand(N, 0); 100 } 101 102 SDOperand CombineTo(SDNode *N, SDOperand Res) { 103 std::vector<SDOperand> To; 104 To.push_back(Res); 105 return CombineTo(N, To); 106 } 107 108 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) { 109 std::vector<SDOperand> To; 110 To.push_back(Res0); 111 To.push_back(Res1); 112 return CombineTo(N, To); 113 } 114 115 /// visit - call the node-specific routine that knows how to fold each 116 /// particular type of node. 117 SDOperand visit(SDNode *N); 118 119 // Visitation implementation - Implement dag node combining for different 120 // node types. The semantics are as follows: 121 // Return Value: 122 // SDOperand.Val == 0 - No change was made 123 // SDOperand.Val == N - N was replaced, is dead, and is already handled. 124 // otherwise - N should be replaced by the returned Operand. 125 // 126 SDOperand visitTokenFactor(SDNode *N); 127 SDOperand visitADD(SDNode *N); 128 SDOperand visitSUB(SDNode *N); 129 SDOperand visitMUL(SDNode *N); 130 SDOperand visitSDIV(SDNode *N); 131 SDOperand visitUDIV(SDNode *N); 132 SDOperand visitSREM(SDNode *N); 133 SDOperand visitUREM(SDNode *N); 134 SDOperand visitMULHU(SDNode *N); 135 SDOperand visitMULHS(SDNode *N); 136 SDOperand visitAND(SDNode *N); 137 SDOperand visitOR(SDNode *N); 138 SDOperand visitXOR(SDNode *N); 139 SDOperand visitSHL(SDNode *N); 140 SDOperand visitSRA(SDNode *N); 141 SDOperand visitSRL(SDNode *N); 142 SDOperand visitCTLZ(SDNode *N); 143 SDOperand visitCTTZ(SDNode *N); 144 SDOperand visitCTPOP(SDNode *N); 145 SDOperand visitSELECT(SDNode *N); 146 SDOperand visitSELECT_CC(SDNode *N); 147 SDOperand visitSETCC(SDNode *N); 148 SDOperand visitADD_PARTS(SDNode *N); 149 SDOperand visitSUB_PARTS(SDNode *N); 150 SDOperand visitSIGN_EXTEND(SDNode *N); 151 SDOperand visitZERO_EXTEND(SDNode *N); 152 SDOperand visitSIGN_EXTEND_INREG(SDNode *N); 153 SDOperand visitTRUNCATE(SDNode *N); 154 SDOperand visitBIT_CONVERT(SDNode *N); 155 156 SDOperand visitFADD(SDNode *N); 157 SDOperand visitFSUB(SDNode *N); 158 SDOperand visitFMUL(SDNode *N); 159 SDOperand visitFDIV(SDNode *N); 160 SDOperand visitFREM(SDNode *N); 161 SDOperand visitSINT_TO_FP(SDNode *N); 162 SDOperand visitUINT_TO_FP(SDNode *N); 163 SDOperand visitFP_TO_SINT(SDNode *N); 164 SDOperand visitFP_TO_UINT(SDNode *N); 165 SDOperand visitFP_ROUND(SDNode *N); 166 SDOperand visitFP_ROUND_INREG(SDNode *N); 167 SDOperand visitFP_EXTEND(SDNode *N); 168 SDOperand visitFNEG(SDNode *N); 169 SDOperand visitFABS(SDNode *N); 170 SDOperand visitBRCOND(SDNode *N); 171 SDOperand visitBRCONDTWOWAY(SDNode *N); 172 SDOperand visitBR_CC(SDNode *N); 173 SDOperand visitBRTWOWAY_CC(SDNode *N); 174 175 SDOperand visitLOAD(SDNode *N); 176 SDOperand visitSTORE(SDNode *N); 177 178 SDOperand visitLOCATION(SDNode *N); 179 SDOperand visitDEBUGLOC(SDNode *N); 180 181 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS); 182 183 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS); 184 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2); 185 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2, 186 SDOperand N3, ISD::CondCode CC); 187 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, 188 ISD::CondCode Cond, bool foldBooleans = true); 189 190 SDOperand BuildSDIV(SDNode *N); 191 SDOperand BuildUDIV(SDNode *N); 192public: 193 DAGCombiner(SelectionDAG &D) 194 : DAG(D), TLI(D.getTargetLoweringInfo()), AfterLegalize(false) {} 195 196 /// Run - runs the dag combiner on all nodes in the work list 197 void Run(bool RunningAfterLegalize); 198 }; 199} 200 201struct ms { 202 int64_t m; // magic number 203 int64_t s; // shift amount 204}; 205 206struct mu { 207 uint64_t m; // magic number 208 int64_t a; // add indicator 209 int64_t s; // shift amount 210}; 211 212/// magic - calculate the magic numbers required to codegen an integer sdiv as 213/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1, 214/// or -1. 215static ms magic32(int32_t d) { 216 int32_t p; 217 uint32_t ad, anc, delta, q1, r1, q2, r2, t; 218 const uint32_t two31 = 0x80000000U; 219 struct ms mag; 220 221 ad = abs(d); 222 t = two31 + ((uint32_t)d >> 31); 223 anc = t - 1 - t%ad; // absolute value of nc 224 p = 31; // initialize p 225 q1 = two31/anc; // initialize q1 = 2p/abs(nc) 226 r1 = two31 - q1*anc; // initialize r1 = rem(2p,abs(nc)) 227 q2 = two31/ad; // initialize q2 = 2p/abs(d) 228 r2 = two31 - q2*ad; // initialize r2 = rem(2p,abs(d)) 229 do { 230 p = p + 1; 231 q1 = 2*q1; // update q1 = 2p/abs(nc) 232 r1 = 2*r1; // update r1 = rem(2p/abs(nc)) 233 if (r1 >= anc) { // must be unsigned comparison 234 q1 = q1 + 1; 235 r1 = r1 - anc; 236 } 237 q2 = 2*q2; // update q2 = 2p/abs(d) 238 r2 = 2*r2; // update r2 = rem(2p/abs(d)) 239 if (r2 >= ad) { // must be unsigned comparison 240 q2 = q2 + 1; 241 r2 = r2 - ad; 242 } 243 delta = ad - r2; 244 } while (q1 < delta || (q1 == delta && r1 == 0)); 245 246 mag.m = (int32_t)(q2 + 1); // make sure to sign extend 247 if (d < 0) mag.m = -mag.m; // resulting magic number 248 mag.s = p - 32; // resulting shift 249 return mag; 250} 251 252/// magicu - calculate the magic numbers required to codegen an integer udiv as 253/// a sequence of multiply, add and shifts. Requires that the divisor not be 0. 254static mu magicu32(uint32_t d) { 255 int32_t p; 256 uint32_t nc, delta, q1, r1, q2, r2; 257 struct mu magu; 258 magu.a = 0; // initialize "add" indicator 259 nc = - 1 - (-d)%d; 260 p = 31; // initialize p 261 q1 = 0x80000000/nc; // initialize q1 = 2p/nc 262 r1 = 0x80000000 - q1*nc; // initialize r1 = rem(2p,nc) 263 q2 = 0x7FFFFFFF/d; // initialize q2 = (2p-1)/d 264 r2 = 0x7FFFFFFF - q2*d; // initialize r2 = rem((2p-1),d) 265 do { 266 p = p + 1; 267 if (r1 >= nc - r1 ) { 268 q1 = 2*q1 + 1; // update q1 269 r1 = 2*r1 - nc; // update r1 270 } 271 else { 272 q1 = 2*q1; // update q1 273 r1 = 2*r1; // update r1 274 } 275 if (r2 + 1 >= d - r2) { 276 if (q2 >= 0x7FFFFFFF) magu.a = 1; 277 q2 = 2*q2 + 1; // update q2 278 r2 = 2*r2 + 1 - d; // update r2 279 } 280 else { 281 if (q2 >= 0x80000000) magu.a = 1; 282 q2 = 2*q2; // update q2 283 r2 = 2*r2 + 1; // update r2 284 } 285 delta = d - 1 - r2; 286 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0))); 287 magu.m = q2 + 1; // resulting magic number 288 magu.s = p - 32; // resulting shift 289 return magu; 290} 291 292/// magic - calculate the magic numbers required to codegen an integer sdiv as 293/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1, 294/// or -1. 295static ms magic64(int64_t d) { 296 int64_t p; 297 uint64_t ad, anc, delta, q1, r1, q2, r2, t; 298 const uint64_t two63 = 9223372036854775808ULL; // 2^63 299 struct ms mag; 300 301 ad = d >= 0 ? d : -d; 302 t = two63 + ((uint64_t)d >> 63); 303 anc = t - 1 - t%ad; // absolute value of nc 304 p = 63; // initialize p 305 q1 = two63/anc; // initialize q1 = 2p/abs(nc) 306 r1 = two63 - q1*anc; // initialize r1 = rem(2p,abs(nc)) 307 q2 = two63/ad; // initialize q2 = 2p/abs(d) 308 r2 = two63 - q2*ad; // initialize r2 = rem(2p,abs(d)) 309 do { 310 p = p + 1; 311 q1 = 2*q1; // update q1 = 2p/abs(nc) 312 r1 = 2*r1; // update r1 = rem(2p/abs(nc)) 313 if (r1 >= anc) { // must be unsigned comparison 314 q1 = q1 + 1; 315 r1 = r1 - anc; 316 } 317 q2 = 2*q2; // update q2 = 2p/abs(d) 318 r2 = 2*r2; // update r2 = rem(2p/abs(d)) 319 if (r2 >= ad) { // must be unsigned comparison 320 q2 = q2 + 1; 321 r2 = r2 - ad; 322 } 323 delta = ad - r2; 324 } while (q1 < delta || (q1 == delta && r1 == 0)); 325 326 mag.m = q2 + 1; 327 if (d < 0) mag.m = -mag.m; // resulting magic number 328 mag.s = p - 64; // resulting shift 329 return mag; 330} 331 332/// magicu - calculate the magic numbers required to codegen an integer udiv as 333/// a sequence of multiply, add and shifts. Requires that the divisor not be 0. 334static mu magicu64(uint64_t d) 335{ 336 int64_t p; 337 uint64_t nc, delta, q1, r1, q2, r2; 338 struct mu magu; 339 magu.a = 0; // initialize "add" indicator 340 nc = - 1 - (-d)%d; 341 p = 63; // initialize p 342 q1 = 0x8000000000000000ull/nc; // initialize q1 = 2p/nc 343 r1 = 0x8000000000000000ull - q1*nc; // initialize r1 = rem(2p,nc) 344 q2 = 0x7FFFFFFFFFFFFFFFull/d; // initialize q2 = (2p-1)/d 345 r2 = 0x7FFFFFFFFFFFFFFFull - q2*d; // initialize r2 = rem((2p-1),d) 346 do { 347 p = p + 1; 348 if (r1 >= nc - r1 ) { 349 q1 = 2*q1 + 1; // update q1 350 r1 = 2*r1 - nc; // update r1 351 } 352 else { 353 q1 = 2*q1; // update q1 354 r1 = 2*r1; // update r1 355 } 356 if (r2 + 1 >= d - r2) { 357 if (q2 >= 0x7FFFFFFFFFFFFFFFull) magu.a = 1; 358 q2 = 2*q2 + 1; // update q2 359 r2 = 2*r2 + 1 - d; // update r2 360 } 361 else { 362 if (q2 >= 0x8000000000000000ull) magu.a = 1; 363 q2 = 2*q2; // update q2 364 r2 = 2*r2 + 1; // update r2 365 } 366 delta = d - 1 - r2; 367 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0))); 368 magu.m = q2 + 1; // resulting magic number 369 magu.s = p - 64; // resulting shift 370 return magu; 371} 372 373// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 374// that selects between the values 1 and 0, making it equivalent to a setcc. 375// Also, set the incoming LHS, RHS, and CC references to the appropriate 376// nodes based on the type of node we are checking. This simplifies life a 377// bit for the callers. 378static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS, 379 SDOperand &CC) { 380 if (N.getOpcode() == ISD::SETCC) { 381 LHS = N.getOperand(0); 382 RHS = N.getOperand(1); 383 CC = N.getOperand(2); 384 return true; 385 } 386 if (N.getOpcode() == ISD::SELECT_CC && 387 N.getOperand(2).getOpcode() == ISD::Constant && 388 N.getOperand(3).getOpcode() == ISD::Constant && 389 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 && 390 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 391 LHS = N.getOperand(0); 392 RHS = N.getOperand(1); 393 CC = N.getOperand(4); 394 return true; 395 } 396 return false; 397} 398 399// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 400// one use. If this is true, it allows the users to invert the operation for 401// free when it is profitable to do so. 402static bool isOneUseSetCC(SDOperand N) { 403 SDOperand N0, N1, N2; 404 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse()) 405 return true; 406 return false; 407} 408 409// FIXME: This should probably go in the ISD class rather than being duplicated 410// in several files. 411static bool isCommutativeBinOp(unsigned Opcode) { 412 switch (Opcode) { 413 case ISD::ADD: 414 case ISD::MUL: 415 case ISD::AND: 416 case ISD::OR: 417 case ISD::XOR: return true; 418 default: return false; // FIXME: Need commutative info for user ops! 419 } 420} 421 422SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){ 423 MVT::ValueType VT = N0.getValueType(); 424 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 425 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 426 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 427 if (isa<ConstantSDNode>(N1)) { 428 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1); 429 WorkList.push_back(OpNode.Val); 430 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0)); 431 } else if (N0.hasOneUse()) { 432 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1); 433 WorkList.push_back(OpNode.Val); 434 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1)); 435 } 436 } 437 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 438 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 439 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 440 if (isa<ConstantSDNode>(N0)) { 441 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0); 442 WorkList.push_back(OpNode.Val); 443 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0)); 444 } else if (N1.hasOneUse()) { 445 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0); 446 WorkList.push_back(OpNode.Val); 447 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1)); 448 } 449 } 450 return SDOperand(); 451} 452 453void DAGCombiner::Run(bool RunningAfterLegalize) { 454 // set the instance variable, so that the various visit routines may use it. 455 AfterLegalize = RunningAfterLegalize; 456 457 // Add all the dag nodes to the worklist. 458 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 459 E = DAG.allnodes_end(); I != E; ++I) 460 WorkList.push_back(I); 461 462 // Create a dummy node (which is not added to allnodes), that adds a reference 463 // to the root node, preventing it from being deleted, and tracking any 464 // changes of the root. 465 HandleSDNode Dummy(DAG.getRoot()); 466 467 // while the worklist isn't empty, inspect the node on the end of it and 468 // try and combine it. 469 while (!WorkList.empty()) { 470 SDNode *N = WorkList.back(); 471 WorkList.pop_back(); 472 473 // If N has no uses, it is dead. Make sure to revisit all N's operands once 474 // N is deleted from the DAG, since they too may now be dead or may have a 475 // reduced number of uses, allowing other xforms. 476 if (N->use_empty() && N != &Dummy) { 477 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 478 WorkList.push_back(N->getOperand(i).Val); 479 480 removeFromWorkList(N); 481 DAG.DeleteNode(N); 482 continue; 483 } 484 485 SDOperand RV = visit(N); 486 if (RV.Val) { 487 ++NodesCombined; 488 // If we get back the same node we passed in, rather than a new node or 489 // zero, we know that the node must have defined multiple values and 490 // CombineTo was used. Since CombineTo takes care of the worklist 491 // mechanics for us, we have no work to do in this case. 492 if (RV.Val != N) { 493 DEBUG(std::cerr << "\nReplacing "; N->dump(); 494 std::cerr << "\nWith: "; RV.Val->dump(); 495 std::cerr << '\n'); 496 std::vector<SDNode*> NowDead; 497 DAG.ReplaceAllUsesWith(N, std::vector<SDOperand>(1, RV), &NowDead); 498 499 // Push the new node and any users onto the worklist 500 WorkList.push_back(RV.Val); 501 AddUsersToWorkList(RV.Val); 502 503 // Nodes can end up on the worklist more than once. Make sure we do 504 // not process a node that has been replaced. 505 removeFromWorkList(N); 506 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 507 removeFromWorkList(NowDead[i]); 508 509 // Finally, since the node is now dead, remove it from the graph. 510 DAG.DeleteNode(N); 511 } 512 } 513 } 514 515 // If the root changed (e.g. it was a dead load, update the root). 516 DAG.setRoot(Dummy.getValue()); 517} 518 519SDOperand DAGCombiner::visit(SDNode *N) { 520 switch(N->getOpcode()) { 521 default: break; 522 case ISD::TokenFactor: return visitTokenFactor(N); 523 case ISD::ADD: return visitADD(N); 524 case ISD::SUB: return visitSUB(N); 525 case ISD::MUL: return visitMUL(N); 526 case ISD::SDIV: return visitSDIV(N); 527 case ISD::UDIV: return visitUDIV(N); 528 case ISD::SREM: return visitSREM(N); 529 case ISD::UREM: return visitUREM(N); 530 case ISD::MULHU: return visitMULHU(N); 531 case ISD::MULHS: return visitMULHS(N); 532 case ISD::AND: return visitAND(N); 533 case ISD::OR: return visitOR(N); 534 case ISD::XOR: return visitXOR(N); 535 case ISD::SHL: return visitSHL(N); 536 case ISD::SRA: return visitSRA(N); 537 case ISD::SRL: return visitSRL(N); 538 case ISD::CTLZ: return visitCTLZ(N); 539 case ISD::CTTZ: return visitCTTZ(N); 540 case ISD::CTPOP: return visitCTPOP(N); 541 case ISD::SELECT: return visitSELECT(N); 542 case ISD::SELECT_CC: return visitSELECT_CC(N); 543 case ISD::SETCC: return visitSETCC(N); 544 case ISD::ADD_PARTS: return visitADD_PARTS(N); 545 case ISD::SUB_PARTS: return visitSUB_PARTS(N); 546 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 547 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 548 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 549 case ISD::TRUNCATE: return visitTRUNCATE(N); 550 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 551 case ISD::FADD: return visitFADD(N); 552 case ISD::FSUB: return visitFSUB(N); 553 case ISD::FMUL: return visitFMUL(N); 554 case ISD::FDIV: return visitFDIV(N); 555 case ISD::FREM: return visitFREM(N); 556 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 557 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 558 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 559 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 560 case ISD::FP_ROUND: return visitFP_ROUND(N); 561 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 562 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 563 case ISD::FNEG: return visitFNEG(N); 564 case ISD::FABS: return visitFABS(N); 565 case ISD::BRCOND: return visitBRCOND(N); 566 case ISD::BRCONDTWOWAY: return visitBRCONDTWOWAY(N); 567 case ISD::BR_CC: return visitBR_CC(N); 568 case ISD::BRTWOWAY_CC: return visitBRTWOWAY_CC(N); 569 case ISD::LOAD: return visitLOAD(N); 570 case ISD::STORE: return visitSTORE(N); 571 case ISD::LOCATION: return visitLOCATION(N); 572 case ISD::DEBUG_LOC: return visitDEBUGLOC(N); 573 } 574 return SDOperand(); 575} 576 577SDOperand DAGCombiner::visitTokenFactor(SDNode *N) { 578 std::vector<SDOperand> Ops; 579 bool Changed = false; 580 581 // If the token factor has two operands and one is the entry token, replace 582 // the token factor with the other operand. 583 if (N->getNumOperands() == 2) { 584 if (N->getOperand(0).getOpcode() == ISD::EntryToken) 585 return N->getOperand(1); 586 if (N->getOperand(1).getOpcode() == ISD::EntryToken) 587 return N->getOperand(0); 588 } 589 590 // fold (tokenfactor (tokenfactor)) -> tokenfactor 591 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 592 SDOperand Op = N->getOperand(i); 593 if (Op.getOpcode() == ISD::TokenFactor && Op.hasOneUse()) { 594 Changed = true; 595 for (unsigned j = 0, e = Op.getNumOperands(); j != e; ++j) 596 Ops.push_back(Op.getOperand(j)); 597 } else { 598 Ops.push_back(Op); 599 } 600 } 601 if (Changed) 602 return DAG.getNode(ISD::TokenFactor, MVT::Other, Ops); 603 return SDOperand(); 604} 605 606SDOperand DAGCombiner::visitADD(SDNode *N) { 607 SDOperand N0 = N->getOperand(0); 608 SDOperand N1 = N->getOperand(1); 609 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 610 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 611 MVT::ValueType VT = N0.getValueType(); 612 613 // fold (add c1, c2) -> c1+c2 614 if (N0C && N1C) 615 return DAG.getNode(ISD::ADD, VT, N0, N1); 616 // canonicalize constant to RHS 617 if (N0C && !N1C) 618 return DAG.getNode(ISD::ADD, VT, N1, N0); 619 // fold (add x, 0) -> x 620 if (N1C && N1C->isNullValue()) 621 return N0; 622 // fold ((c1-A)+c2) -> (c1+c2)-A 623 if (N1C && N0.getOpcode() == ISD::SUB) 624 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 625 return DAG.getNode(ISD::SUB, VT, 626 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT), 627 N0.getOperand(1)); 628 // reassociate add 629 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1); 630 if (RADD.Val != 0) 631 return RADD; 632 // fold ((0-A) + B) -> B-A 633 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 634 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 635 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1)); 636 // fold (A + (0-B)) -> A-B 637 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 638 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 639 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1)); 640 // fold (A+(B-A)) -> B 641 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 642 return N1.getOperand(0); 643 return SDOperand(); 644} 645 646SDOperand DAGCombiner::visitSUB(SDNode *N) { 647 SDOperand N0 = N->getOperand(0); 648 SDOperand N1 = N->getOperand(1); 649 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 650 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 651 MVT::ValueType VT = N0.getValueType(); 652 653 // fold (sub x, x) -> 0 654 if (N0 == N1) 655 return DAG.getConstant(0, N->getValueType(0)); 656 // fold (sub c1, c2) -> c1-c2 657 if (N0C && N1C) 658 return DAG.getNode(ISD::SUB, VT, N0, N1); 659 // fold (sub x, c) -> (add x, -c) 660 if (N1C) 661 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT)); 662 // fold (A+B)-A -> B 663 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 664 return N0.getOperand(1); 665 // fold (A+B)-B -> A 666 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 667 return N0.getOperand(0); 668 return SDOperand(); 669} 670 671SDOperand DAGCombiner::visitMUL(SDNode *N) { 672 SDOperand N0 = N->getOperand(0); 673 SDOperand N1 = N->getOperand(1); 674 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 675 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 676 MVT::ValueType VT = N0.getValueType(); 677 678 // fold (mul c1, c2) -> c1*c2 679 if (N0C && N1C) 680 return DAG.getNode(ISD::MUL, VT, N0, N1); 681 // canonicalize constant to RHS 682 if (N0C && !N1C) 683 return DAG.getNode(ISD::MUL, VT, N1, N0); 684 // fold (mul x, 0) -> 0 685 if (N1C && N1C->isNullValue()) 686 return N1; 687 // fold (mul x, -1) -> 0-x 688 if (N1C && N1C->isAllOnesValue()) 689 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 690 // fold (mul x, (1 << c)) -> x << c 691 if (N1C && isPowerOf2_64(N1C->getValue())) 692 return DAG.getNode(ISD::SHL, VT, N0, 693 DAG.getConstant(Log2_64(N1C->getValue()), 694 TLI.getShiftAmountTy())); 695 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 696 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) { 697 // FIXME: If the input is something that is easily negated (e.g. a 698 // single-use add), we should put the negate there. 699 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), 700 DAG.getNode(ISD::SHL, VT, N0, 701 DAG.getConstant(Log2_64(-N1C->getSignExtended()), 702 TLI.getShiftAmountTy()))); 703 } 704 // reassociate mul 705 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1); 706 if (RMUL.Val != 0) 707 return RMUL; 708 return SDOperand(); 709} 710 711SDOperand DAGCombiner::visitSDIV(SDNode *N) { 712 SDOperand N0 = N->getOperand(0); 713 SDOperand N1 = N->getOperand(1); 714 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 715 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 716 MVT::ValueType VT = N->getValueType(0); 717 718 // fold (sdiv c1, c2) -> c1/c2 719 if (N0C && N1C && !N1C->isNullValue()) 720 return DAG.getNode(ISD::SDIV, VT, N0, N1); 721 // fold (sdiv X, 1) -> X 722 if (N1C && N1C->getSignExtended() == 1LL) 723 return N0; 724 // fold (sdiv X, -1) -> 0-X 725 if (N1C && N1C->isAllOnesValue()) 726 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 727 // If we know the sign bits of both operands are zero, strength reduce to a 728 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 729 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 730 if (TLI.MaskedValueIsZero(N1, SignBit) && 731 TLI.MaskedValueIsZero(N0, SignBit)) 732 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1); 733 // fold (sdiv X, pow2) -> (add (sra X, log(pow2)), (srl X, sizeof(X)-1)) 734 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() && 735 (isPowerOf2_64(N1C->getSignExtended()) || 736 isPowerOf2_64(-N1C->getSignExtended()))) { 737 // If dividing by powers of two is cheap, then don't perform the following 738 // fold. 739 if (TLI.isPow2DivCheap()) 740 return SDOperand(); 741 int64_t pow2 = N1C->getSignExtended(); 742 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 743 SDOperand SRL = DAG.getNode(ISD::SRL, VT, N0, 744 DAG.getConstant(MVT::getSizeInBits(VT)-1, 745 TLI.getShiftAmountTy())); 746 WorkList.push_back(SRL.Val); 747 SDOperand SGN = DAG.getNode(ISD::ADD, VT, N0, SRL); 748 WorkList.push_back(SGN.Val); 749 SDOperand SRA = DAG.getNode(ISD::SRA, VT, SGN, 750 DAG.getConstant(Log2_64(abs2), 751 TLI.getShiftAmountTy())); 752 // If we're dividing by a positive value, we're done. Otherwise, we must 753 // negate the result. 754 if (pow2 > 0) 755 return SRA; 756 WorkList.push_back(SRA.Val); 757 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA); 758 } 759 // if integer divide is expensive and we satisfy the requirements, emit an 760 // alternate sequence. 761 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) && 762 !TLI.isIntDivCheap()) { 763 SDOperand Op = BuildSDIV(N); 764 if (Op.Val) return Op; 765 } 766 return SDOperand(); 767} 768 769SDOperand DAGCombiner::visitUDIV(SDNode *N) { 770 SDOperand N0 = N->getOperand(0); 771 SDOperand N1 = N->getOperand(1); 772 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 773 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 774 MVT::ValueType VT = N->getValueType(0); 775 776 // fold (udiv c1, c2) -> c1/c2 777 if (N0C && N1C && !N1C->isNullValue()) 778 return DAG.getNode(ISD::UDIV, VT, N0, N1); 779 // fold (udiv x, (1 << c)) -> x >>u c 780 if (N1C && isPowerOf2_64(N1C->getValue())) 781 return DAG.getNode(ISD::SRL, VT, N0, 782 DAG.getConstant(Log2_64(N1C->getValue()), 783 TLI.getShiftAmountTy())); 784 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 785 if (N1.getOpcode() == ISD::SHL) { 786 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 787 if (isPowerOf2_64(SHC->getValue())) { 788 MVT::ValueType ADDVT = N1.getOperand(1).getValueType(); 789 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1), 790 DAG.getConstant(Log2_64(SHC->getValue()), 791 ADDVT)); 792 WorkList.push_back(Add.Val); 793 return DAG.getNode(ISD::SRL, VT, N0, Add); 794 } 795 } 796 } 797 // fold (udiv x, c) -> alternate 798 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) { 799 SDOperand Op = BuildUDIV(N); 800 if (Op.Val) return Op; 801 } 802 return SDOperand(); 803} 804 805SDOperand DAGCombiner::visitSREM(SDNode *N) { 806 SDOperand N0 = N->getOperand(0); 807 SDOperand N1 = N->getOperand(1); 808 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 809 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 810 MVT::ValueType VT = N->getValueType(0); 811 812 // fold (srem c1, c2) -> c1%c2 813 if (N0C && N1C && !N1C->isNullValue()) 814 return DAG.getNode(ISD::SREM, VT, N0, N1); 815 // If we know the sign bits of both operands are zero, strength reduce to a 816 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 817 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 818 if (TLI.MaskedValueIsZero(N1, SignBit) && 819 TLI.MaskedValueIsZero(N0, SignBit)) 820 return DAG.getNode(ISD::UREM, VT, N0, N1); 821 return SDOperand(); 822} 823 824SDOperand DAGCombiner::visitUREM(SDNode *N) { 825 SDOperand N0 = N->getOperand(0); 826 SDOperand N1 = N->getOperand(1); 827 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 828 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 829 MVT::ValueType VT = N->getValueType(0); 830 831 // fold (urem c1, c2) -> c1%c2 832 if (N0C && N1C && !N1C->isNullValue()) 833 return DAG.getNode(ISD::UREM, VT, N0, N1); 834 // fold (urem x, pow2) -> (and x, pow2-1) 835 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue())) 836 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT)); 837 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 838 if (N1.getOpcode() == ISD::SHL) { 839 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 840 if (isPowerOf2_64(SHC->getValue())) { 841 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT)); 842 WorkList.push_back(Add.Val); 843 return DAG.getNode(ISD::AND, VT, N0, Add); 844 } 845 } 846 } 847 return SDOperand(); 848} 849 850SDOperand DAGCombiner::visitMULHS(SDNode *N) { 851 SDOperand N0 = N->getOperand(0); 852 SDOperand N1 = N->getOperand(1); 853 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 854 855 // fold (mulhs x, 0) -> 0 856 if (N1C && N1C->isNullValue()) 857 return N1; 858 // fold (mulhs x, 1) -> (sra x, size(x)-1) 859 if (N1C && N1C->getValue() == 1) 860 return DAG.getNode(ISD::SRA, N0.getValueType(), N0, 861 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1, 862 TLI.getShiftAmountTy())); 863 return SDOperand(); 864} 865 866SDOperand DAGCombiner::visitMULHU(SDNode *N) { 867 SDOperand N0 = N->getOperand(0); 868 SDOperand N1 = N->getOperand(1); 869 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 870 871 // fold (mulhu x, 0) -> 0 872 if (N1C && N1C->isNullValue()) 873 return N1; 874 // fold (mulhu x, 1) -> 0 875 if (N1C && N1C->getValue() == 1) 876 return DAG.getConstant(0, N0.getValueType()); 877 return SDOperand(); 878} 879 880SDOperand DAGCombiner::visitAND(SDNode *N) { 881 SDOperand N0 = N->getOperand(0); 882 SDOperand N1 = N->getOperand(1); 883 SDOperand LL, LR, RL, RR, CC0, CC1, Old, New; 884 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 885 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 886 MVT::ValueType VT = N1.getValueType(); 887 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 888 889 // fold (and c1, c2) -> c1&c2 890 if (N0C && N1C) 891 return DAG.getNode(ISD::AND, VT, N0, N1); 892 // canonicalize constant to RHS 893 if (N0C && !N1C) 894 return DAG.getNode(ISD::AND, VT, N1, N0); 895 // fold (and x, -1) -> x 896 if (N1C && N1C->isAllOnesValue()) 897 return N0; 898 // if (and x, c) is known to be zero, return 0 899 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits))) 900 return DAG.getConstant(0, VT); 901 // fold (and x, c) -> x iff (x & ~c) == 0 902 if (N1C && 903 TLI.MaskedValueIsZero(N0, ~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)))) 904 return N0; 905 // reassociate and 906 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1); 907 if (RAND.Val != 0) 908 return RAND; 909 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 910 if (N1C && N0.getOpcode() == ISD::OR) 911 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 912 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue()) 913 return N1; 914 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 915 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 916 unsigned InBits = MVT::getSizeInBits(N0.getOperand(0).getValueType()); 917 if (TLI.MaskedValueIsZero(N0.getOperand(0), 918 ~N1C->getValue() & ((1ULL << InBits)-1))) { 919 // We actually want to replace all uses of the any_extend with the 920 // zero_extend, to avoid duplicating things. This will later cause this 921 // AND to be folded. 922 CombineTo(N0.Val, DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(), 923 N0.getOperand(0))); 924 return SDOperand(); 925 } 926 } 927 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 928 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 929 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 930 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 931 932 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 933 MVT::isInteger(LL.getValueType())) { 934 // fold (X == 0) & (Y == 0) -> (X|Y == 0) 935 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) { 936 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 937 WorkList.push_back(ORNode.Val); 938 return DAG.getSetCC(VT, ORNode, LR, Op1); 939 } 940 // fold (X == -1) & (Y == -1) -> (X&Y == -1) 941 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 942 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 943 WorkList.push_back(ANDNode.Val); 944 return DAG.getSetCC(VT, ANDNode, LR, Op1); 945 } 946 // fold (X > -1) & (Y > -1) -> (X|Y > -1) 947 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 948 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 949 WorkList.push_back(ORNode.Val); 950 return DAG.getSetCC(VT, ORNode, LR, Op1); 951 } 952 } 953 // canonicalize equivalent to ll == rl 954 if (LL == RR && LR == RL) { 955 Op1 = ISD::getSetCCSwappedOperands(Op1); 956 std::swap(RL, RR); 957 } 958 if (LL == RL && LR == RR) { 959 bool isInteger = MVT::isInteger(LL.getValueType()); 960 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 961 if (Result != ISD::SETCC_INVALID) 962 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 963 } 964 } 965 // fold (and (zext x), (zext y)) -> (zext (and x, y)) 966 if (N0.getOpcode() == ISD::ZERO_EXTEND && 967 N1.getOpcode() == ISD::ZERO_EXTEND && 968 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 969 SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(), 970 N0.getOperand(0), N1.getOperand(0)); 971 WorkList.push_back(ANDNode.Val); 972 return DAG.getNode(ISD::ZERO_EXTEND, VT, ANDNode); 973 } 974 // fold (and (shl/srl/sra x), (shl/srl/sra y)) -> (shl/srl/sra (and x, y)) 975 if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) || 976 (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL) || 977 (N0.getOpcode() == ISD::SRA && N1.getOpcode() == ISD::SRA)) && 978 N0.getOperand(1) == N1.getOperand(1)) { 979 SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(), 980 N0.getOperand(0), N1.getOperand(0)); 981 WorkList.push_back(ANDNode.Val); 982 return DAG.getNode(N0.getOpcode(), VT, ANDNode, N0.getOperand(1)); 983 } 984 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 985 // fold (and (sra)) -> (and (srl)) when possible. 986 if (TLI.DemandedBitsAreZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits), Old, 987 New, DAG)) { 988 WorkList.push_back(N); 989 CombineTo(Old.Val, New); 990 return SDOperand(); 991 } 992 // FIXME: DemandedBitsAreZero cannot currently handle AND with non-constant 993 // RHS and propagate known cleared bits to LHS. For this reason, we must keep 994 // this fold, for now, for the following testcase: 995 // 996 //int %test2(uint %mode.0.i.0) { 997 // %tmp.79 = cast uint %mode.0.i.0 to int 998 // %tmp.80 = shr int %tmp.79, ubyte 15 999 // %tmp.81 = shr uint %mode.0.i.0, ubyte 16 1000 // %tmp.82 = cast uint %tmp.81 to int 1001 // %tmp.83 = and int %tmp.80, %tmp.82 1002 // ret int %tmp.83 1003 //} 1004 // fold (and (sra)) -> (and (srl)) when possible. 1005 if (N0.getOpcode() == ISD::SRA && N0.Val->hasOneUse()) { 1006 if (ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1007 // If the RHS of the AND has zeros where the sign bits of the SRA will 1008 // land, turn the SRA into an SRL. 1009 if (TLI.MaskedValueIsZero(N1, (~0ULL << (OpSizeInBits-N01C->getValue())) & 1010 (~0ULL>>(64-OpSizeInBits)))) { 1011 WorkList.push_back(N); 1012 CombineTo(N0.Val, DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 1013 N0.getOperand(1))); 1014 return SDOperand(); 1015 } 1016 } 1017 } 1018 // fold (zext_inreg (extload x)) -> (zextload x) 1019 if (N0.getOpcode() == ISD::EXTLOAD) { 1020 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT(); 1021 // If we zero all the possible extended bits, then we can turn this into 1022 // a zextload if we are running before legalize or the operation is legal. 1023 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && 1024 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) { 1025 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), 1026 N0.getOperand(1), N0.getOperand(2), 1027 EVT); 1028 WorkList.push_back(N); 1029 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1030 return SDOperand(); 1031 } 1032 } 1033 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1034 if (N0.getOpcode() == ISD::SEXTLOAD && N0.hasOneUse()) { 1035 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT(); 1036 // If we zero all the possible extended bits, then we can turn this into 1037 // a zextload if we are running before legalize or the operation is legal. 1038 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && 1039 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) { 1040 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), 1041 N0.getOperand(1), N0.getOperand(2), 1042 EVT); 1043 WorkList.push_back(N); 1044 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1045 return SDOperand(); 1046 } 1047 } 1048 return SDOperand(); 1049} 1050 1051SDOperand DAGCombiner::visitOR(SDNode *N) { 1052 SDOperand N0 = N->getOperand(0); 1053 SDOperand N1 = N->getOperand(1); 1054 SDOperand LL, LR, RL, RR, CC0, CC1; 1055 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1056 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1057 MVT::ValueType VT = N1.getValueType(); 1058 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1059 1060 // fold (or c1, c2) -> c1|c2 1061 if (N0C && N1C) 1062 return DAG.getNode(ISD::OR, VT, N0, N1); 1063 // canonicalize constant to RHS 1064 if (N0C && !N1C) 1065 return DAG.getNode(ISD::OR, VT, N1, N0); 1066 // fold (or x, 0) -> x 1067 if (N1C && N1C->isNullValue()) 1068 return N0; 1069 // fold (or x, -1) -> -1 1070 if (N1C && N1C->isAllOnesValue()) 1071 return N1; 1072 // fold (or x, c) -> c iff (x & ~c) == 0 1073 if (N1C && 1074 TLI.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)))) 1075 return N1; 1076 // reassociate or 1077 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1); 1078 if (ROR.Val != 0) 1079 return ROR; 1080 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 1081 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() && 1082 isa<ConstantSDNode>(N0.getOperand(1))) { 1083 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 1084 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0), 1085 N1), 1086 DAG.getConstant(N1C->getValue() | C1->getValue(), VT)); 1087 } 1088 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 1089 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1090 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1091 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1092 1093 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1094 MVT::isInteger(LL.getValueType())) { 1095 // fold (X != 0) | (Y != 0) -> (X|Y != 0) 1096 // fold (X < 0) | (Y < 0) -> (X|Y < 0) 1097 if (cast<ConstantSDNode>(LR)->getValue() == 0 && 1098 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 1099 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1100 WorkList.push_back(ORNode.Val); 1101 return DAG.getSetCC(VT, ORNode, LR, Op1); 1102 } 1103 // fold (X != -1) | (Y != -1) -> (X&Y != -1) 1104 // fold (X > -1) | (Y > -1) -> (X&Y > -1) 1105 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 1106 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 1107 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1108 WorkList.push_back(ANDNode.Val); 1109 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1110 } 1111 } 1112 // canonicalize equivalent to ll == rl 1113 if (LL == RR && LR == RL) { 1114 Op1 = ISD::getSetCCSwappedOperands(Op1); 1115 std::swap(RL, RR); 1116 } 1117 if (LL == RL && LR == RR) { 1118 bool isInteger = MVT::isInteger(LL.getValueType()); 1119 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 1120 if (Result != ISD::SETCC_INVALID) 1121 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1122 } 1123 } 1124 // fold (or (zext x), (zext y)) -> (zext (or x, y)) 1125 if (N0.getOpcode() == ISD::ZERO_EXTEND && 1126 N1.getOpcode() == ISD::ZERO_EXTEND && 1127 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1128 SDOperand ORNode = DAG.getNode(ISD::OR, N0.getOperand(0).getValueType(), 1129 N0.getOperand(0), N1.getOperand(0)); 1130 WorkList.push_back(ORNode.Val); 1131 return DAG.getNode(ISD::ZERO_EXTEND, VT, ORNode); 1132 } 1133 // fold (or (shl/srl/sra x), (shl/srl/sra y)) -> (shl/srl/sra (or x, y)) 1134 if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) || 1135 (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL) || 1136 (N0.getOpcode() == ISD::SRA && N1.getOpcode() == ISD::SRA)) && 1137 N0.getOperand(1) == N1.getOperand(1)) { 1138 SDOperand ORNode = DAG.getNode(ISD::OR, N0.getOperand(0).getValueType(), 1139 N0.getOperand(0), N1.getOperand(0)); 1140 WorkList.push_back(ORNode.Val); 1141 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1)); 1142 } 1143 // canonicalize shl to left side in a shl/srl pair, to match rotate 1144 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 1145 std::swap(N0, N1); 1146 // check for rotl, rotr 1147 if (N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SRL && 1148 N0.getOperand(0) == N1.getOperand(0) && 1149 TLI.isOperationLegal(ISD::ROTL, VT) && TLI.isTypeLegal(VT)) { 1150 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 1151 if (N0.getOperand(1).getOpcode() == ISD::Constant && 1152 N1.getOperand(1).getOpcode() == ISD::Constant) { 1153 uint64_t c1val = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1154 uint64_t c2val = cast<ConstantSDNode>(N1.getOperand(1))->getValue(); 1155 if ((c1val + c2val) == OpSizeInBits) 1156 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), N0.getOperand(1)); 1157 } 1158 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 1159 if (N1.getOperand(1).getOpcode() == ISD::SUB && 1160 N0.getOperand(1) == N1.getOperand(1).getOperand(1)) 1161 if (ConstantSDNode *SUBC = 1162 dyn_cast<ConstantSDNode>(N1.getOperand(1).getOperand(0))) 1163 if (SUBC->getValue() == OpSizeInBits) 1164 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), N0.getOperand(1)); 1165 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 1166 if (N0.getOperand(1).getOpcode() == ISD::SUB && 1167 N1.getOperand(1) == N0.getOperand(1).getOperand(1)) 1168 if (ConstantSDNode *SUBC = 1169 dyn_cast<ConstantSDNode>(N0.getOperand(1).getOperand(0))) 1170 if (SUBC->getValue() == OpSizeInBits) { 1171 if (TLI.isOperationLegal(ISD::ROTR, VT) && TLI.isTypeLegal(VT)) 1172 return DAG.getNode(ISD::ROTR, VT, N0.getOperand(0), 1173 N1.getOperand(1)); 1174 else 1175 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), 1176 N0.getOperand(1)); 1177 } 1178 } 1179 return SDOperand(); 1180} 1181 1182SDOperand DAGCombiner::visitXOR(SDNode *N) { 1183 SDOperand N0 = N->getOperand(0); 1184 SDOperand N1 = N->getOperand(1); 1185 SDOperand LHS, RHS, CC; 1186 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1187 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1188 MVT::ValueType VT = N0.getValueType(); 1189 1190 // fold (xor c1, c2) -> c1^c2 1191 if (N0C && N1C) 1192 return DAG.getNode(ISD::XOR, VT, N0, N1); 1193 // canonicalize constant to RHS 1194 if (N0C && !N1C) 1195 return DAG.getNode(ISD::XOR, VT, N1, N0); 1196 // fold (xor x, 0) -> x 1197 if (N1C && N1C->isNullValue()) 1198 return N0; 1199 // reassociate xor 1200 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1); 1201 if (RXOR.Val != 0) 1202 return RXOR; 1203 // fold !(x cc y) -> (x !cc y) 1204 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 1205 bool isInt = MVT::isInteger(LHS.getValueType()); 1206 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 1207 isInt); 1208 if (N0.getOpcode() == ISD::SETCC) 1209 return DAG.getSetCC(VT, LHS, RHS, NotCC); 1210 if (N0.getOpcode() == ISD::SELECT_CC) 1211 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC); 1212 assert(0 && "Unhandled SetCC Equivalent!"); 1213 abort(); 1214 } 1215 // fold !(x or y) -> (!x and !y) iff x or y are setcc 1216 if (N1C && N1C->getValue() == 1 && 1217 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 1218 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 1219 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 1220 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 1221 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 1222 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 1223 WorkList.push_back(LHS.Val); WorkList.push_back(RHS.Val); 1224 return DAG.getNode(NewOpcode, VT, LHS, RHS); 1225 } 1226 } 1227 // fold !(x or y) -> (!x and !y) iff x or y are constants 1228 if (N1C && N1C->isAllOnesValue() && 1229 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 1230 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 1231 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 1232 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 1233 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 1234 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 1235 WorkList.push_back(LHS.Val); WorkList.push_back(RHS.Val); 1236 return DAG.getNode(NewOpcode, VT, LHS, RHS); 1237 } 1238 } 1239 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2) 1240 if (N1C && N0.getOpcode() == ISD::XOR) { 1241 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 1242 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 1243 if (N00C) 1244 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1), 1245 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT)); 1246 if (N01C) 1247 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0), 1248 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT)); 1249 } 1250 // fold (xor x, x) -> 0 1251 if (N0 == N1) 1252 return DAG.getConstant(0, VT); 1253 // fold (xor (zext x), (zext y)) -> (zext (xor x, y)) 1254 if (N0.getOpcode() == ISD::ZERO_EXTEND && 1255 N1.getOpcode() == ISD::ZERO_EXTEND && 1256 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1257 SDOperand XORNode = DAG.getNode(ISD::XOR, N0.getOperand(0).getValueType(), 1258 N0.getOperand(0), N1.getOperand(0)); 1259 WorkList.push_back(XORNode.Val); 1260 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode); 1261 } 1262 // fold (xor (shl/srl/sra x), (shl/srl/sra y)) -> (shl/srl/sra (xor x, y)) 1263 if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) || 1264 (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL) || 1265 (N0.getOpcode() == ISD::SRA && N1.getOpcode() == ISD::SRA)) && 1266 N0.getOperand(1) == N1.getOperand(1)) { 1267 SDOperand XORNode = DAG.getNode(ISD::XOR, N0.getOperand(0).getValueType(), 1268 N0.getOperand(0), N1.getOperand(0)); 1269 WorkList.push_back(XORNode.Val); 1270 return DAG.getNode(N0.getOpcode(), VT, XORNode, N0.getOperand(1)); 1271 } 1272 return SDOperand(); 1273} 1274 1275SDOperand DAGCombiner::visitSHL(SDNode *N) { 1276 SDOperand N0 = N->getOperand(0); 1277 SDOperand N1 = N->getOperand(1); 1278 SDOperand Old = SDOperand(); 1279 SDOperand New = SDOperand(); 1280 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1281 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1282 MVT::ValueType VT = N0.getValueType(); 1283 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1284 1285 // fold (shl c1, c2) -> c1<<c2 1286 if (N0C && N1C) 1287 return DAG.getNode(ISD::SHL, VT, N0, N1); 1288 // fold (shl 0, x) -> 0 1289 if (N0C && N0C->isNullValue()) 1290 return N0; 1291 // fold (shl c1, (add x, c2)) -> (shl c1 << c2, x) 1292 if (N0C && N1.getOpcode() == ISD::ADD && 1293 N1.getOperand(1).getOpcode() == ISD::Constant) { 1294 SDOperand LHS = DAG.getNode(ISD::SHL, VT, N0, N1.getOperand(1)); 1295 return DAG.getNode(ISD::SHL, VT, LHS, N1.getOperand(0)); 1296 } 1297 // fold (shl x, c >= size(x)) -> undef 1298 if (N1C && N1C->getValue() >= OpSizeInBits) 1299 return DAG.getNode(ISD::UNDEF, VT); 1300 // fold (shl x, 0) -> x 1301 if (N1C && N1C->isNullValue()) 1302 return N0; 1303 // if (shl x, c) is known to be zero, return 0 1304 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits))) 1305 return DAG.getConstant(0, VT); 1306 if (N1C && TLI.DemandedBitsAreZero(SDOperand(N,0), ~0ULL >> (64-OpSizeInBits), 1307 Old, New, DAG)) { 1308 WorkList.push_back(N); 1309 CombineTo(Old.Val, New); 1310 return SDOperand(); 1311 } 1312 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2) 1313 if (N1C && N0.getOpcode() == ISD::SHL && 1314 N0.getOperand(1).getOpcode() == ISD::Constant) { 1315 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1316 uint64_t c2 = N1C->getValue(); 1317 if (c1 + c2 > OpSizeInBits) 1318 return DAG.getConstant(0, VT); 1319 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0), 1320 DAG.getConstant(c1 + c2, N1.getValueType())); 1321 } 1322 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or 1323 // (srl (and x, -1 << c1), c1-c2) 1324 if (N1C && N0.getOpcode() == ISD::SRL && 1325 N0.getOperand(1).getOpcode() == ISD::Constant) { 1326 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1327 uint64_t c2 = N1C->getValue(); 1328 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0), 1329 DAG.getConstant(~0ULL << c1, VT)); 1330 if (c2 > c1) 1331 return DAG.getNode(ISD::SHL, VT, Mask, 1332 DAG.getConstant(c2-c1, N1.getValueType())); 1333 else 1334 return DAG.getNode(ISD::SRL, VT, Mask, 1335 DAG.getConstant(c1-c2, N1.getValueType())); 1336 } 1337 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1) 1338 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 1339 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 1340 DAG.getConstant(~0ULL << N1C->getValue(), VT)); 1341 return SDOperand(); 1342} 1343 1344SDOperand DAGCombiner::visitSRA(SDNode *N) { 1345 SDOperand N0 = N->getOperand(0); 1346 SDOperand N1 = N->getOperand(1); 1347 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1348 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1349 MVT::ValueType VT = N0.getValueType(); 1350 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1351 1352 // fold (sra c1, c2) -> c1>>c2 1353 if (N0C && N1C) 1354 return DAG.getNode(ISD::SRA, VT, N0, N1); 1355 // fold (sra 0, x) -> 0 1356 if (N0C && N0C->isNullValue()) 1357 return N0; 1358 // fold (sra -1, x) -> -1 1359 if (N0C && N0C->isAllOnesValue()) 1360 return N0; 1361 // fold (sra x, c >= size(x)) -> undef 1362 if (N1C && N1C->getValue() >= OpSizeInBits) 1363 return DAG.getNode(ISD::UNDEF, VT); 1364 // fold (sra x, 0) -> x 1365 if (N1C && N1C->isNullValue()) 1366 return N0; 1367 // If the sign bit is known to be zero, switch this to a SRL. 1368 if (TLI.MaskedValueIsZero(N0, (1ULL << (OpSizeInBits-1)))) 1369 return DAG.getNode(ISD::SRL, VT, N0, N1); 1370 return SDOperand(); 1371} 1372 1373SDOperand DAGCombiner::visitSRL(SDNode *N) { 1374 SDOperand N0 = N->getOperand(0); 1375 SDOperand N1 = N->getOperand(1); 1376 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1377 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1378 MVT::ValueType VT = N0.getValueType(); 1379 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1380 1381 // fold (srl c1, c2) -> c1 >>u c2 1382 if (N0C && N1C) 1383 return DAG.getNode(ISD::SRL, VT, N0, N1); 1384 // fold (srl 0, x) -> 0 1385 if (N0C && N0C->isNullValue()) 1386 return N0; 1387 // fold (srl x, c >= size(x)) -> undef 1388 if (N1C && N1C->getValue() >= OpSizeInBits) 1389 return DAG.getNode(ISD::UNDEF, VT); 1390 // fold (srl x, 0) -> x 1391 if (N1C && N1C->isNullValue()) 1392 return N0; 1393 // if (srl x, c) is known to be zero, return 0 1394 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits))) 1395 return DAG.getConstant(0, VT); 1396 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2) 1397 if (N1C && N0.getOpcode() == ISD::SRL && 1398 N0.getOperand(1).getOpcode() == ISD::Constant) { 1399 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1400 uint64_t c2 = N1C->getValue(); 1401 if (c1 + c2 > OpSizeInBits) 1402 return DAG.getConstant(0, VT); 1403 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 1404 DAG.getConstant(c1 + c2, N1.getValueType())); 1405 } 1406 return SDOperand(); 1407} 1408 1409SDOperand DAGCombiner::visitCTLZ(SDNode *N) { 1410 SDOperand N0 = N->getOperand(0); 1411 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1412 MVT::ValueType VT = N->getValueType(0); 1413 1414 // fold (ctlz c1) -> c2 1415 if (N0C) 1416 return DAG.getNode(ISD::CTLZ, VT, N0); 1417 return SDOperand(); 1418} 1419 1420SDOperand DAGCombiner::visitCTTZ(SDNode *N) { 1421 SDOperand N0 = N->getOperand(0); 1422 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1423 MVT::ValueType VT = N->getValueType(0); 1424 1425 // fold (cttz c1) -> c2 1426 if (N0C) 1427 return DAG.getNode(ISD::CTTZ, VT, N0); 1428 return SDOperand(); 1429} 1430 1431SDOperand DAGCombiner::visitCTPOP(SDNode *N) { 1432 SDOperand N0 = N->getOperand(0); 1433 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1434 MVT::ValueType VT = N->getValueType(0); 1435 1436 // fold (ctpop c1) -> c2 1437 if (N0C) 1438 return DAG.getNode(ISD::CTPOP, VT, N0); 1439 return SDOperand(); 1440} 1441 1442SDOperand DAGCombiner::visitSELECT(SDNode *N) { 1443 SDOperand N0 = N->getOperand(0); 1444 SDOperand N1 = N->getOperand(1); 1445 SDOperand N2 = N->getOperand(2); 1446 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1447 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1448 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 1449 MVT::ValueType VT = N->getValueType(0); 1450 1451 // fold select C, X, X -> X 1452 if (N1 == N2) 1453 return N1; 1454 // fold select true, X, Y -> X 1455 if (N0C && !N0C->isNullValue()) 1456 return N1; 1457 // fold select false, X, Y -> Y 1458 if (N0C && N0C->isNullValue()) 1459 return N2; 1460 // fold select C, 1, X -> C | X 1461 if (MVT::i1 == VT && N1C && N1C->getValue() == 1) 1462 return DAG.getNode(ISD::OR, VT, N0, N2); 1463 // fold select C, 0, X -> ~C & X 1464 // FIXME: this should check for C type == X type, not i1? 1465 if (MVT::i1 == VT && N1C && N1C->isNullValue()) { 1466 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 1467 WorkList.push_back(XORNode.Val); 1468 return DAG.getNode(ISD::AND, VT, XORNode, N2); 1469 } 1470 // fold select C, X, 1 -> ~C | X 1471 if (MVT::i1 == VT && N2C && N2C->getValue() == 1) { 1472 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 1473 WorkList.push_back(XORNode.Val); 1474 return DAG.getNode(ISD::OR, VT, XORNode, N1); 1475 } 1476 // fold select C, X, 0 -> C & X 1477 // FIXME: this should check for C type == X type, not i1? 1478 if (MVT::i1 == VT && N2C && N2C->isNullValue()) 1479 return DAG.getNode(ISD::AND, VT, N0, N1); 1480 // fold X ? X : Y --> X ? 1 : Y --> X | Y 1481 if (MVT::i1 == VT && N0 == N1) 1482 return DAG.getNode(ISD::OR, VT, N0, N2); 1483 // fold X ? Y : X --> X ? Y : 0 --> X & Y 1484 if (MVT::i1 == VT && N0 == N2) 1485 return DAG.getNode(ISD::AND, VT, N0, N1); 1486 // If we can fold this based on the true/false value, do so. 1487 if (SimplifySelectOps(N, N1, N2)) 1488 return SDOperand(); 1489 // fold selects based on a setcc into other things, such as min/max/abs 1490 if (N0.getOpcode() == ISD::SETCC) 1491 // FIXME: 1492 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 1493 // having to say they don't support SELECT_CC on every type the DAG knows 1494 // about, since there is no way to mark an opcode illegal at all value types 1495 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other)) 1496 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1), 1497 N1, N2, N0.getOperand(2)); 1498 else 1499 return SimplifySelect(N0, N1, N2); 1500 return SDOperand(); 1501} 1502 1503SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) { 1504 SDOperand N0 = N->getOperand(0); 1505 SDOperand N1 = N->getOperand(1); 1506 SDOperand N2 = N->getOperand(2); 1507 SDOperand N3 = N->getOperand(3); 1508 SDOperand N4 = N->getOperand(4); 1509 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1510 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1511 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 1512 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 1513 1514 // Determine if the condition we're dealing with is constant 1515 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 1516 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 1517 1518 // fold select_cc lhs, rhs, x, x, cc -> x 1519 if (N2 == N3) 1520 return N2; 1521 1522 // If we can fold this based on the true/false value, do so. 1523 if (SimplifySelectOps(N, N2, N3)) 1524 return SDOperand(); 1525 1526 // fold select_cc into other things, such as min/max/abs 1527 return SimplifySelectCC(N0, N1, N2, N3, CC); 1528} 1529 1530SDOperand DAGCombiner::visitSETCC(SDNode *N) { 1531 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 1532 cast<CondCodeSDNode>(N->getOperand(2))->get()); 1533} 1534 1535SDOperand DAGCombiner::visitADD_PARTS(SDNode *N) { 1536 SDOperand LHSLo = N->getOperand(0); 1537 SDOperand RHSLo = N->getOperand(2); 1538 MVT::ValueType VT = LHSLo.getValueType(); 1539 1540 // fold (a_Hi, 0) + (b_Hi, b_Lo) -> (b_Hi + a_Hi, b_Lo) 1541 if (TLI.MaskedValueIsZero(LHSLo, (1ULL << MVT::getSizeInBits(VT))-1)) { 1542 SDOperand Hi = DAG.getNode(ISD::ADD, VT, N->getOperand(1), 1543 N->getOperand(3)); 1544 WorkList.push_back(Hi.Val); 1545 CombineTo(N, RHSLo, Hi); 1546 return SDOperand(); 1547 } 1548 // fold (a_Hi, a_Lo) + (b_Hi, 0) -> (a_Hi + b_Hi, a_Lo) 1549 if (TLI.MaskedValueIsZero(RHSLo, (1ULL << MVT::getSizeInBits(VT))-1)) { 1550 SDOperand Hi = DAG.getNode(ISD::ADD, VT, N->getOperand(1), 1551 N->getOperand(3)); 1552 WorkList.push_back(Hi.Val); 1553 CombineTo(N, LHSLo, Hi); 1554 return SDOperand(); 1555 } 1556 return SDOperand(); 1557} 1558 1559SDOperand DAGCombiner::visitSUB_PARTS(SDNode *N) { 1560 SDOperand LHSLo = N->getOperand(0); 1561 SDOperand RHSLo = N->getOperand(2); 1562 MVT::ValueType VT = LHSLo.getValueType(); 1563 1564 // fold (a_Hi, a_Lo) - (b_Hi, 0) -> (a_Hi - b_Hi, a_Lo) 1565 if (TLI.MaskedValueIsZero(RHSLo, (1ULL << MVT::getSizeInBits(VT))-1)) { 1566 SDOperand Hi = DAG.getNode(ISD::SUB, VT, N->getOperand(1), 1567 N->getOperand(3)); 1568 WorkList.push_back(Hi.Val); 1569 CombineTo(N, LHSLo, Hi); 1570 return SDOperand(); 1571 } 1572 return SDOperand(); 1573} 1574 1575SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 1576 SDOperand N0 = N->getOperand(0); 1577 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1578 MVT::ValueType VT = N->getValueType(0); 1579 1580 // fold (sext c1) -> c1 1581 if (N0C) 1582 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0); 1583 // fold (sext (sext x)) -> (sext x) 1584 if (N0.getOpcode() == ISD::SIGN_EXTEND) 1585 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0)); 1586 // fold (sext (truncate x)) -> (sextinreg x) iff x size == sext size. 1587 if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT&& 1588 (!AfterLegalize || 1589 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, N0.getValueType()))) 1590 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), 1591 DAG.getValueType(N0.getValueType())); 1592 // fold (sext (load x)) -> (sext (truncate (sextload x))) 1593 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() && 1594 (!AfterLegalize||TLI.isOperationLegal(ISD::SEXTLOAD, N0.getValueType()))){ 1595 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), 1596 N0.getOperand(1), N0.getOperand(2), 1597 N0.getValueType()); 1598 CombineTo(N, ExtLoad); 1599 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 1600 ExtLoad.getValue(1)); 1601 return SDOperand(); 1602 } 1603 1604 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 1605 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 1606 if ((N0.getOpcode() == ISD::SEXTLOAD || N0.getOpcode() == ISD::EXTLOAD) && 1607 N0.hasOneUse()) { 1608 SDOperand ExtLoad = DAG.getNode(ISD::SEXTLOAD, VT, N0.getOperand(0), 1609 N0.getOperand(1), N0.getOperand(2), 1610 N0.getOperand(3)); 1611 CombineTo(N, ExtLoad); 1612 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 1613 ExtLoad.getValue(1)); 1614 return SDOperand(); 1615 } 1616 1617 return SDOperand(); 1618} 1619 1620SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) { 1621 SDOperand N0 = N->getOperand(0); 1622 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1623 MVT::ValueType VT = N->getValueType(0); 1624 1625 // fold (zext c1) -> c1 1626 if (N0C) 1627 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 1628 // fold (zext (zext x)) -> (zext x) 1629 if (N0.getOpcode() == ISD::ZERO_EXTEND) 1630 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0)); 1631 // fold (zext (truncate x)) -> (zextinreg x) iff x size == zext size. 1632 if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT&& 1633 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, N0.getValueType()))) 1634 return DAG.getZeroExtendInReg(N0.getOperand(0), N0.getValueType()); 1635 // fold (zext (load x)) -> (zext (truncate (zextload x))) 1636 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() && 1637 (!AfterLegalize||TLI.isOperationLegal(ISD::ZEXTLOAD, N0.getValueType()))){ 1638 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), 1639 N0.getOperand(1), N0.getOperand(2), 1640 N0.getValueType()); 1641 CombineTo(N, ExtLoad); 1642 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 1643 ExtLoad.getValue(1)); 1644 return SDOperand(); 1645 } 1646 1647 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 1648 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 1649 if ((N0.getOpcode() == ISD::ZEXTLOAD || N0.getOpcode() == ISD::EXTLOAD) && 1650 N0.hasOneUse()) { 1651 SDOperand ExtLoad = DAG.getNode(ISD::ZEXTLOAD, VT, N0.getOperand(0), 1652 N0.getOperand(1), N0.getOperand(2), 1653 N0.getOperand(3)); 1654 CombineTo(N, ExtLoad); 1655 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 1656 ExtLoad.getValue(1)); 1657 return SDOperand(); 1658 } 1659 return SDOperand(); 1660} 1661 1662SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 1663 SDOperand N0 = N->getOperand(0); 1664 SDOperand N1 = N->getOperand(1); 1665 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1666 MVT::ValueType VT = N->getValueType(0); 1667 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT(); 1668 unsigned EVTBits = MVT::getSizeInBits(EVT); 1669 1670 // fold (sext_in_reg c1) -> c1 1671 if (N0C) { 1672 SDOperand Truncate = DAG.getConstant(N0C->getValue(), EVT); 1673 return DAG.getNode(ISD::SIGN_EXTEND, VT, Truncate); 1674 } 1675 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt1 1676 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1677 cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) { 1678 return N0; 1679 } 1680 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 1681 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1682 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) { 1683 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); 1684 } 1685 // fold (sext_in_reg (assert_sext x)) -> (assert_sext x) 1686 if (N0.getOpcode() == ISD::AssertSext && 1687 cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) { 1688 return N0; 1689 } 1690 // fold (sext_in_reg (sextload x)) -> (sextload x) 1691 if (N0.getOpcode() == ISD::SEXTLOAD && 1692 cast<VTSDNode>(N0.getOperand(3))->getVT() <= EVT) { 1693 return N0; 1694 } 1695 // fold (sext_in_reg (setcc x)) -> setcc x iff (setcc x) == 0 or -1 1696 if (N0.getOpcode() == ISD::SETCC && 1697 TLI.getSetCCResultContents() == 1698 TargetLowering::ZeroOrNegativeOneSetCCResult) 1699 return N0; 1700 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero 1701 if (TLI.MaskedValueIsZero(N0, 1ULL << (EVTBits-1))) 1702 return DAG.getZeroExtendInReg(N0, EVT); 1703 // fold (sext_in_reg (srl x)) -> sra x 1704 if (N0.getOpcode() == ISD::SRL && 1705 N0.getOperand(1).getOpcode() == ISD::Constant && 1706 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == EVTBits) { 1707 return DAG.getNode(ISD::SRA, N0.getValueType(), N0.getOperand(0), 1708 N0.getOperand(1)); 1709 } 1710 // fold (sext_inreg (extload x)) -> (sextload x) 1711 if (N0.getOpcode() == ISD::EXTLOAD && 1712 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() && 1713 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) { 1714 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), 1715 N0.getOperand(1), N0.getOperand(2), 1716 EVT); 1717 CombineTo(N, ExtLoad); 1718 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1719 return SDOperand(); 1720 } 1721 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 1722 if (N0.getOpcode() == ISD::ZEXTLOAD && N0.hasOneUse() && 1723 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() && 1724 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) { 1725 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), 1726 N0.getOperand(1), N0.getOperand(2), 1727 EVT); 1728 CombineTo(N, ExtLoad); 1729 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1730 return SDOperand(); 1731 } 1732 return SDOperand(); 1733} 1734 1735SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) { 1736 SDOperand N0 = N->getOperand(0); 1737 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1738 MVT::ValueType VT = N->getValueType(0); 1739 1740 // noop truncate 1741 if (N0.getValueType() == N->getValueType(0)) 1742 return N0; 1743 // fold (truncate c1) -> c1 1744 if (N0C) 1745 return DAG.getNode(ISD::TRUNCATE, VT, N0); 1746 // fold (truncate (truncate x)) -> (truncate x) 1747 if (N0.getOpcode() == ISD::TRUNCATE) 1748 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 1749 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 1750 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND){ 1751 if (N0.getValueType() < VT) 1752 // if the source is smaller than the dest, we still need an extend 1753 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 1754 else if (N0.getValueType() > VT) 1755 // if the source is larger than the dest, than we just need the truncate 1756 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 1757 else 1758 // if the source and dest are the same type, we can drop both the extend 1759 // and the truncate 1760 return N0.getOperand(0); 1761 } 1762 // fold (truncate (load x)) -> (smaller load x) 1763 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) { 1764 assert(MVT::getSizeInBits(N0.getValueType()) > MVT::getSizeInBits(VT) && 1765 "Cannot truncate to larger type!"); 1766 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 1767 // For big endian targets, we need to add an offset to the pointer to load 1768 // the correct bytes. For little endian systems, we merely need to read 1769 // fewer bytes from the same pointer. 1770 uint64_t PtrOff = 1771 (MVT::getSizeInBits(N0.getValueType()) - MVT::getSizeInBits(VT)) / 8; 1772 SDOperand NewPtr = TLI.isLittleEndian() ? N0.getOperand(1) : 1773 DAG.getNode(ISD::ADD, PtrType, N0.getOperand(1), 1774 DAG.getConstant(PtrOff, PtrType)); 1775 WorkList.push_back(NewPtr.Val); 1776 SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), NewPtr,N0.getOperand(2)); 1777 WorkList.push_back(N); 1778 CombineTo(N0.Val, Load, Load.getValue(1)); 1779 return SDOperand(); 1780 } 1781 return SDOperand(); 1782} 1783 1784SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) { 1785 SDOperand N0 = N->getOperand(0); 1786 MVT::ValueType VT = N->getValueType(0); 1787 1788 // If the input is a constant, let getNode() fold it. 1789 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 1790 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0); 1791 if (Res.Val != N) return Res; 1792 } 1793 1794 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2) 1795 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 1796 1797 // fold (conv (load x)) -> (load (conv*)x) 1798 // FIXME: These xforms need to know that the resultant load doesn't need a 1799 // higher alignment than the original! 1800 if (0 && N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) { 1801 SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), N0.getOperand(1), 1802 N0.getOperand(2)); 1803 WorkList.push_back(N); 1804 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load), 1805 Load.getValue(1)); 1806 return Load; 1807 } 1808 1809 return SDOperand(); 1810} 1811 1812SDOperand DAGCombiner::visitFADD(SDNode *N) { 1813 SDOperand N0 = N->getOperand(0); 1814 SDOperand N1 = N->getOperand(1); 1815 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1816 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 1817 MVT::ValueType VT = N->getValueType(0); 1818 1819 // fold (fadd c1, c2) -> c1+c2 1820 if (N0CFP && N1CFP) 1821 return DAG.getNode(ISD::FADD, VT, N0, N1); 1822 // canonicalize constant to RHS 1823 if (N0CFP && !N1CFP) 1824 return DAG.getNode(ISD::FADD, VT, N1, N0); 1825 // fold (A + (-B)) -> A-B 1826 if (N1.getOpcode() == ISD::FNEG) 1827 return DAG.getNode(ISD::FSUB, VT, N0, N1.getOperand(0)); 1828 // fold ((-A) + B) -> B-A 1829 if (N0.getOpcode() == ISD::FNEG) 1830 return DAG.getNode(ISD::FSUB, VT, N1, N0.getOperand(0)); 1831 return SDOperand(); 1832} 1833 1834SDOperand DAGCombiner::visitFSUB(SDNode *N) { 1835 SDOperand N0 = N->getOperand(0); 1836 SDOperand N1 = N->getOperand(1); 1837 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1838 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 1839 MVT::ValueType VT = N->getValueType(0); 1840 1841 // fold (fsub c1, c2) -> c1-c2 1842 if (N0CFP && N1CFP) 1843 return DAG.getNode(ISD::FSUB, VT, N0, N1); 1844 // fold (A-(-B)) -> A+B 1845 if (N1.getOpcode() == ISD::FNEG) 1846 return DAG.getNode(ISD::FADD, VT, N0, N1.getOperand(0)); 1847 return SDOperand(); 1848} 1849 1850SDOperand DAGCombiner::visitFMUL(SDNode *N) { 1851 SDOperand N0 = N->getOperand(0); 1852 SDOperand N1 = N->getOperand(1); 1853 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1854 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 1855 MVT::ValueType VT = N->getValueType(0); 1856 1857 // fold (fmul c1, c2) -> c1*c2 1858 if (N0CFP && N1CFP) 1859 return DAG.getNode(ISD::FMUL, VT, N0, N1); 1860 // canonicalize constant to RHS 1861 if (N0CFP && !N1CFP) 1862 return DAG.getNode(ISD::FMUL, VT, N1, N0); 1863 // fold (fmul X, 2.0) -> (fadd X, X) 1864 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 1865 return DAG.getNode(ISD::FADD, VT, N0, N0); 1866 return SDOperand(); 1867} 1868 1869SDOperand DAGCombiner::visitFDIV(SDNode *N) { 1870 SDOperand N0 = N->getOperand(0); 1871 SDOperand N1 = N->getOperand(1); 1872 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1873 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 1874 MVT::ValueType VT = N->getValueType(0); 1875 1876 // fold (fdiv c1, c2) -> c1/c2 1877 if (N0CFP && N1CFP) 1878 return DAG.getNode(ISD::FDIV, VT, N0, N1); 1879 return SDOperand(); 1880} 1881 1882SDOperand DAGCombiner::visitFREM(SDNode *N) { 1883 SDOperand N0 = N->getOperand(0); 1884 SDOperand N1 = N->getOperand(1); 1885 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1886 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 1887 MVT::ValueType VT = N->getValueType(0); 1888 1889 // fold (frem c1, c2) -> fmod(c1,c2) 1890 if (N0CFP && N1CFP) 1891 return DAG.getNode(ISD::FREM, VT, N0, N1); 1892 return SDOperand(); 1893} 1894 1895 1896SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) { 1897 SDOperand N0 = N->getOperand(0); 1898 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1899 MVT::ValueType VT = N->getValueType(0); 1900 1901 // fold (sint_to_fp c1) -> c1fp 1902 if (N0C) 1903 return DAG.getNode(ISD::SINT_TO_FP, VT, N0); 1904 return SDOperand(); 1905} 1906 1907SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) { 1908 SDOperand N0 = N->getOperand(0); 1909 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1910 MVT::ValueType VT = N->getValueType(0); 1911 1912 // fold (uint_to_fp c1) -> c1fp 1913 if (N0C) 1914 return DAG.getNode(ISD::UINT_TO_FP, VT, N0); 1915 return SDOperand(); 1916} 1917 1918SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) { 1919 SDOperand N0 = N->getOperand(0); 1920 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1921 MVT::ValueType VT = N->getValueType(0); 1922 1923 // fold (fp_to_sint c1fp) -> c1 1924 if (N0CFP) 1925 return DAG.getNode(ISD::FP_TO_SINT, VT, N0); 1926 return SDOperand(); 1927} 1928 1929SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) { 1930 SDOperand N0 = N->getOperand(0); 1931 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1932 MVT::ValueType VT = N->getValueType(0); 1933 1934 // fold (fp_to_uint c1fp) -> c1 1935 if (N0CFP) 1936 return DAG.getNode(ISD::FP_TO_UINT, VT, N0); 1937 return SDOperand(); 1938} 1939 1940SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) { 1941 SDOperand N0 = N->getOperand(0); 1942 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1943 MVT::ValueType VT = N->getValueType(0); 1944 1945 // fold (fp_round c1fp) -> c1fp 1946 if (N0CFP) 1947 return DAG.getNode(ISD::FP_ROUND, VT, N0); 1948 return SDOperand(); 1949} 1950 1951SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 1952 SDOperand N0 = N->getOperand(0); 1953 MVT::ValueType VT = N->getValueType(0); 1954 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 1955 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1956 1957 // fold (fp_round_inreg c1fp) -> c1fp 1958 if (N0CFP) { 1959 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT); 1960 return DAG.getNode(ISD::FP_EXTEND, VT, Round); 1961 } 1962 return SDOperand(); 1963} 1964 1965SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) { 1966 SDOperand N0 = N->getOperand(0); 1967 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1968 MVT::ValueType VT = N->getValueType(0); 1969 1970 // fold (fp_extend c1fp) -> c1fp 1971 if (N0CFP) 1972 return DAG.getNode(ISD::FP_EXTEND, VT, N0); 1973 return SDOperand(); 1974} 1975 1976SDOperand DAGCombiner::visitFNEG(SDNode *N) { 1977 SDOperand N0 = N->getOperand(0); 1978 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1979 MVT::ValueType VT = N->getValueType(0); 1980 1981 // fold (fneg c1) -> -c1 1982 if (N0CFP) 1983 return DAG.getNode(ISD::FNEG, VT, N0); 1984 // fold (fneg (sub x, y)) -> (sub y, x) 1985 if (N->getOperand(0).getOpcode() == ISD::SUB) 1986 return DAG.getNode(ISD::SUB, VT, N->getOperand(1), N->getOperand(0)); 1987 // fold (fneg (fneg x)) -> x 1988 if (N->getOperand(0).getOpcode() == ISD::FNEG) 1989 return N->getOperand(0).getOperand(0); 1990 return SDOperand(); 1991} 1992 1993SDOperand DAGCombiner::visitFABS(SDNode *N) { 1994 SDOperand N0 = N->getOperand(0); 1995 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1996 MVT::ValueType VT = N->getValueType(0); 1997 1998 // fold (fabs c1) -> fabs(c1) 1999 if (N0CFP) 2000 return DAG.getNode(ISD::FABS, VT, N0); 2001 // fold (fabs (fabs x)) -> (fabs x) 2002 if (N->getOperand(0).getOpcode() == ISD::FABS) 2003 return N->getOperand(0); 2004 // fold (fabs (fneg x)) -> (fabs x) 2005 if (N->getOperand(0).getOpcode() == ISD::FNEG) 2006 return DAG.getNode(ISD::FABS, VT, N->getOperand(0).getOperand(0)); 2007 return SDOperand(); 2008} 2009 2010SDOperand DAGCombiner::visitBRCOND(SDNode *N) { 2011 SDOperand Chain = N->getOperand(0); 2012 SDOperand N1 = N->getOperand(1); 2013 SDOperand N2 = N->getOperand(2); 2014 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2015 2016 // never taken branch, fold to chain 2017 if (N1C && N1C->isNullValue()) 2018 return Chain; 2019 // unconditional branch 2020 if (N1C && N1C->getValue() == 1) 2021 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 2022 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 2023 // on the target. 2024 if (N1.getOpcode() == ISD::SETCC && 2025 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) { 2026 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2), 2027 N1.getOperand(0), N1.getOperand(1), N2); 2028 } 2029 return SDOperand(); 2030} 2031 2032SDOperand DAGCombiner::visitBRCONDTWOWAY(SDNode *N) { 2033 SDOperand Chain = N->getOperand(0); 2034 SDOperand N1 = N->getOperand(1); 2035 SDOperand N2 = N->getOperand(2); 2036 SDOperand N3 = N->getOperand(3); 2037 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2038 2039 // unconditional branch to true mbb 2040 if (N1C && N1C->getValue() == 1) 2041 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 2042 // unconditional branch to false mbb 2043 if (N1C && N1C->isNullValue()) 2044 return DAG.getNode(ISD::BR, MVT::Other, Chain, N3); 2045 // fold a brcondtwoway with a setcc condition into a BRTWOWAY_CC node if 2046 // BRTWOWAY_CC is legal on the target. 2047 if (N1.getOpcode() == ISD::SETCC && 2048 TLI.isOperationLegal(ISD::BRTWOWAY_CC, MVT::Other)) { 2049 std::vector<SDOperand> Ops; 2050 Ops.push_back(Chain); 2051 Ops.push_back(N1.getOperand(2)); 2052 Ops.push_back(N1.getOperand(0)); 2053 Ops.push_back(N1.getOperand(1)); 2054 Ops.push_back(N2); 2055 Ops.push_back(N3); 2056 return DAG.getNode(ISD::BRTWOWAY_CC, MVT::Other, Ops); 2057 } 2058 return SDOperand(); 2059} 2060 2061// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 2062// 2063SDOperand DAGCombiner::visitBR_CC(SDNode *N) { 2064 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 2065 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 2066 2067 // Use SimplifySetCC to simplify SETCC's. 2068 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false); 2069 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val); 2070 2071 // fold br_cc true, dest -> br dest (unconditional branch) 2072 if (SCCC && SCCC->getValue()) 2073 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0), 2074 N->getOperand(4)); 2075 // fold br_cc false, dest -> unconditional fall through 2076 if (SCCC && SCCC->isNullValue()) 2077 return N->getOperand(0); 2078 // fold to a simpler setcc 2079 if (Simp.Val && Simp.getOpcode() == ISD::SETCC) 2080 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0), 2081 Simp.getOperand(2), Simp.getOperand(0), 2082 Simp.getOperand(1), N->getOperand(4)); 2083 return SDOperand(); 2084} 2085 2086SDOperand DAGCombiner::visitBRTWOWAY_CC(SDNode *N) { 2087 SDOperand Chain = N->getOperand(0); 2088 SDOperand CCN = N->getOperand(1); 2089 SDOperand LHS = N->getOperand(2); 2090 SDOperand RHS = N->getOperand(3); 2091 SDOperand N4 = N->getOperand(4); 2092 SDOperand N5 = N->getOperand(5); 2093 2094 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), LHS, RHS, 2095 cast<CondCodeSDNode>(CCN)->get(), false); 2096 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 2097 2098 // fold select_cc lhs, rhs, x, x, cc -> x 2099 if (N4 == N5) 2100 return DAG.getNode(ISD::BR, MVT::Other, Chain, N4); 2101 // fold select_cc true, x, y -> x 2102 if (SCCC && SCCC->getValue()) 2103 return DAG.getNode(ISD::BR, MVT::Other, Chain, N4); 2104 // fold select_cc false, x, y -> y 2105 if (SCCC && SCCC->isNullValue()) 2106 return DAG.getNode(ISD::BR, MVT::Other, Chain, N5); 2107 // fold to a simpler setcc 2108 if (SCC.Val && SCC.getOpcode() == ISD::SETCC) { 2109 std::vector<SDOperand> Ops; 2110 Ops.push_back(Chain); 2111 Ops.push_back(SCC.getOperand(2)); 2112 Ops.push_back(SCC.getOperand(0)); 2113 Ops.push_back(SCC.getOperand(1)); 2114 Ops.push_back(N4); 2115 Ops.push_back(N5); 2116 return DAG.getNode(ISD::BRTWOWAY_CC, MVT::Other, Ops); 2117 } 2118 return SDOperand(); 2119} 2120 2121SDOperand DAGCombiner::visitLOAD(SDNode *N) { 2122 SDOperand Chain = N->getOperand(0); 2123 SDOperand Ptr = N->getOperand(1); 2124 SDOperand SrcValue = N->getOperand(2); 2125 2126 // If this load is directly stored, replace the load value with the stored 2127 // value. 2128 // TODO: Handle store large -> read small portion. 2129 // TODO: Handle TRUNCSTORE/EXTLOAD 2130 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr && 2131 Chain.getOperand(1).getValueType() == N->getValueType(0)) 2132 return CombineTo(N, Chain.getOperand(1), Chain); 2133 2134 return SDOperand(); 2135} 2136 2137SDOperand DAGCombiner::visitSTORE(SDNode *N) { 2138 SDOperand Chain = N->getOperand(0); 2139 SDOperand Value = N->getOperand(1); 2140 SDOperand Ptr = N->getOperand(2); 2141 SDOperand SrcValue = N->getOperand(3); 2142 2143 // If this is a store that kills a previous store, remove the previous store. 2144 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr && 2145 Chain.Val->hasOneUse() /* Avoid introducing DAG cycles */ && 2146 // Make sure that these stores are the same value type: 2147 // FIXME: we really care that the second store is >= size of the first. 2148 Value.getValueType() == Chain.getOperand(1).getValueType()) { 2149 // Create a new store of Value that replaces both stores. 2150 SDNode *PrevStore = Chain.Val; 2151 if (PrevStore->getOperand(1) == Value) // Same value multiply stored. 2152 return Chain; 2153 SDOperand NewStore = DAG.getNode(ISD::STORE, MVT::Other, 2154 PrevStore->getOperand(0), Value, Ptr, 2155 SrcValue); 2156 CombineTo(N, NewStore); // Nuke this store. 2157 CombineTo(PrevStore, NewStore); // Nuke the previous store. 2158 return SDOperand(N, 0); 2159 } 2160 2161 // If this is a store of a bit convert, store the input value. 2162 // FIXME: This needs to know that the resultant store does not need a 2163 // higher alignment than the original. 2164 if (0 && Value.getOpcode() == ISD::BIT_CONVERT) 2165 return DAG.getNode(ISD::STORE, MVT::Other, Chain, Value.getOperand(0), 2166 Ptr, SrcValue); 2167 2168 return SDOperand(); 2169} 2170 2171SDOperand DAGCombiner::visitLOCATION(SDNode *N) { 2172 SDOperand Chain = N->getOperand(0); 2173 2174 // Remove redundant locations (last one holds) 2175 if (Chain.getOpcode() == ISD::LOCATION && Chain.hasOneUse()) { 2176 return DAG.getNode(ISD::LOCATION, MVT::Other, Chain.getOperand(0), 2177 N->getOperand(1), 2178 N->getOperand(2), 2179 N->getOperand(3), 2180 N->getOperand(4)); 2181 } 2182 2183 return SDOperand(); 2184} 2185 2186SDOperand DAGCombiner::visitDEBUGLOC(SDNode *N) { 2187 SDOperand Chain = N->getOperand(0); 2188 2189 // Remove redundant debug locations (last one holds) 2190 if (Chain.getOpcode() == ISD::DEBUG_LOC && Chain.hasOneUse()) { 2191 return DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Chain.getOperand(0), 2192 N->getOperand(1), 2193 N->getOperand(2), 2194 N->getOperand(3)); 2195 } 2196 2197 return SDOperand(); 2198} 2199 2200SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){ 2201 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 2202 2203 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2, 2204 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 2205 // If we got a simplified select_cc node back from SimplifySelectCC, then 2206 // break it down into a new SETCC node, and a new SELECT node, and then return 2207 // the SELECT node, since we were called with a SELECT node. 2208 if (SCC.Val) { 2209 // Check to see if we got a select_cc back (to turn into setcc/select). 2210 // Otherwise, just return whatever node we got back, like fabs. 2211 if (SCC.getOpcode() == ISD::SELECT_CC) { 2212 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(), 2213 SCC.getOperand(0), SCC.getOperand(1), 2214 SCC.getOperand(4)); 2215 WorkList.push_back(SETCC.Val); 2216 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2), 2217 SCC.getOperand(3), SETCC); 2218 } 2219 return SCC; 2220 } 2221 return SDOperand(); 2222} 2223 2224/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 2225/// are the two values being selected between, see if we can simplify the 2226/// select. 2227/// 2228bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS, 2229 SDOperand RHS) { 2230 2231 // If this is a select from two identical things, try to pull the operation 2232 // through the select. 2233 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 2234#if 0 2235 std::cerr << "SELECT: ["; LHS.Val->dump(); 2236 std::cerr << "] ["; RHS.Val->dump(); 2237 std::cerr << "]\n"; 2238#endif 2239 2240 // If this is a load and the token chain is identical, replace the select 2241 // of two loads with a load through a select of the address to load from. 2242 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 2243 // constants have been dropped into the constant pool. 2244 if ((LHS.getOpcode() == ISD::LOAD || 2245 LHS.getOpcode() == ISD::EXTLOAD || 2246 LHS.getOpcode() == ISD::ZEXTLOAD || 2247 LHS.getOpcode() == ISD::SEXTLOAD) && 2248 // Token chains must be identical. 2249 LHS.getOperand(0) == RHS.getOperand(0) && 2250 // If this is an EXTLOAD, the VT's must match. 2251 (LHS.getOpcode() == ISD::LOAD || 2252 LHS.getOperand(3) == RHS.getOperand(3))) { 2253 // FIXME: this conflates two src values, discarding one. This is not 2254 // the right thing to do, but nothing uses srcvalues now. When they do, 2255 // turn SrcValue into a list of locations. 2256 SDOperand Addr; 2257 if (TheSelect->getOpcode() == ISD::SELECT) 2258 Addr = DAG.getNode(ISD::SELECT, LHS.getOperand(1).getValueType(), 2259 TheSelect->getOperand(0), LHS.getOperand(1), 2260 RHS.getOperand(1)); 2261 else 2262 Addr = DAG.getNode(ISD::SELECT_CC, LHS.getOperand(1).getValueType(), 2263 TheSelect->getOperand(0), 2264 TheSelect->getOperand(1), 2265 LHS.getOperand(1), RHS.getOperand(1), 2266 TheSelect->getOperand(4)); 2267 2268 SDOperand Load; 2269 if (LHS.getOpcode() == ISD::LOAD) 2270 Load = DAG.getLoad(TheSelect->getValueType(0), LHS.getOperand(0), 2271 Addr, LHS.getOperand(2)); 2272 else 2273 Load = DAG.getExtLoad(LHS.getOpcode(), TheSelect->getValueType(0), 2274 LHS.getOperand(0), Addr, LHS.getOperand(2), 2275 cast<VTSDNode>(LHS.getOperand(3))->getVT()); 2276 // Users of the select now use the result of the load. 2277 CombineTo(TheSelect, Load); 2278 2279 // Users of the old loads now use the new load's chain. We know the 2280 // old-load value is dead now. 2281 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1)); 2282 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1)); 2283 return true; 2284 } 2285 } 2286 2287 return false; 2288} 2289 2290SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1, 2291 SDOperand N2, SDOperand N3, 2292 ISD::CondCode CC) { 2293 2294 MVT::ValueType VT = N2.getValueType(); 2295 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 2296 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 2297 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 2298 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 2299 2300 // Determine if the condition we're dealing with is constant 2301 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 2302 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 2303 2304 // fold select_cc true, x, y -> x 2305 if (SCCC && SCCC->getValue()) 2306 return N2; 2307 // fold select_cc false, x, y -> y 2308 if (SCCC && SCCC->getValue() == 0) 2309 return N3; 2310 2311 // Check to see if we can simplify the select into an fabs node 2312 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 2313 // Allow either -0.0 or 0.0 2314 if (CFP->getValue() == 0.0) { 2315 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 2316 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 2317 N0 == N2 && N3.getOpcode() == ISD::FNEG && 2318 N2 == N3.getOperand(0)) 2319 return DAG.getNode(ISD::FABS, VT, N0); 2320 2321 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 2322 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 2323 N0 == N3 && N2.getOpcode() == ISD::FNEG && 2324 N2.getOperand(0) == N3) 2325 return DAG.getNode(ISD::FABS, VT, N3); 2326 } 2327 } 2328 2329 // Check to see if we can perform the "gzip trick", transforming 2330 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 2331 if (N1C && N1C->isNullValue() && N3C && N3C->isNullValue() && 2332 MVT::isInteger(N0.getValueType()) && 2333 MVT::isInteger(N2.getValueType()) && CC == ISD::SETLT) { 2334 MVT::ValueType XType = N0.getValueType(); 2335 MVT::ValueType AType = N2.getValueType(); 2336 if (XType >= AType) { 2337 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 2338 // single-bit constant. 2339 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) { 2340 unsigned ShCtV = Log2_64(N2C->getValue()); 2341 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1; 2342 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy()); 2343 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt); 2344 WorkList.push_back(Shift.Val); 2345 if (XType > AType) { 2346 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 2347 WorkList.push_back(Shift.Val); 2348 } 2349 return DAG.getNode(ISD::AND, AType, Shift, N2); 2350 } 2351 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 2352 DAG.getConstant(MVT::getSizeInBits(XType)-1, 2353 TLI.getShiftAmountTy())); 2354 WorkList.push_back(Shift.Val); 2355 if (XType > AType) { 2356 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 2357 WorkList.push_back(Shift.Val); 2358 } 2359 return DAG.getNode(ISD::AND, AType, Shift, N2); 2360 } 2361 } 2362 2363 // fold select C, 16, 0 -> shl C, 4 2364 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) && 2365 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) { 2366 // Get a SetCC of the condition 2367 // FIXME: Should probably make sure that setcc is legal if we ever have a 2368 // target where it isn't. 2369 SDOperand Temp, SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 2370 WorkList.push_back(SCC.Val); 2371 // cast from setcc result type to select result type 2372 if (AfterLegalize) 2373 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType()); 2374 else 2375 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 2376 WorkList.push_back(Temp.Val); 2377 // shl setcc result by log2 n2c 2378 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp, 2379 DAG.getConstant(Log2_64(N2C->getValue()), 2380 TLI.getShiftAmountTy())); 2381 } 2382 2383 // Check to see if this is the equivalent of setcc 2384 // FIXME: Turn all of these into setcc if setcc if setcc is legal 2385 // otherwise, go ahead with the folds. 2386 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) { 2387 MVT::ValueType XType = N0.getValueType(); 2388 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) { 2389 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 2390 if (Res.getValueType() != VT) 2391 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res); 2392 return Res; 2393 } 2394 2395 // seteq X, 0 -> srl (ctlz X, log2(size(X))) 2396 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 2397 TLI.isOperationLegal(ISD::CTLZ, XType)) { 2398 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0); 2399 return DAG.getNode(ISD::SRL, XType, Ctlz, 2400 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)), 2401 TLI.getShiftAmountTy())); 2402 } 2403 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) 2404 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 2405 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType), 2406 N0); 2407 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0, 2408 DAG.getConstant(~0ULL, XType)); 2409 return DAG.getNode(ISD::SRL, XType, 2410 DAG.getNode(ISD::AND, XType, NegN0, NotN0), 2411 DAG.getConstant(MVT::getSizeInBits(XType)-1, 2412 TLI.getShiftAmountTy())); 2413 } 2414 // setgt X, -1 -> xor (srl (X, size(X)-1), 1) 2415 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 2416 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0, 2417 DAG.getConstant(MVT::getSizeInBits(XType)-1, 2418 TLI.getShiftAmountTy())); 2419 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType)); 2420 } 2421 } 2422 2423 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 2424 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 2425 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 2426 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) { 2427 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0))) { 2428 MVT::ValueType XType = N0.getValueType(); 2429 if (SubC->isNullValue() && MVT::isInteger(XType)) { 2430 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 2431 DAG.getConstant(MVT::getSizeInBits(XType)-1, 2432 TLI.getShiftAmountTy())); 2433 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 2434 WorkList.push_back(Shift.Val); 2435 WorkList.push_back(Add.Val); 2436 return DAG.getNode(ISD::XOR, XType, Add, Shift); 2437 } 2438 } 2439 } 2440 2441 return SDOperand(); 2442} 2443 2444SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0, 2445 SDOperand N1, ISD::CondCode Cond, 2446 bool foldBooleans) { 2447 // These setcc operations always fold. 2448 switch (Cond) { 2449 default: break; 2450 case ISD::SETFALSE: 2451 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 2452 case ISD::SETTRUE: 2453 case ISD::SETTRUE2: return DAG.getConstant(1, VT); 2454 } 2455 2456 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) { 2457 uint64_t C1 = N1C->getValue(); 2458 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val)) { 2459 uint64_t C0 = N0C->getValue(); 2460 2461 // Sign extend the operands if required 2462 if (ISD::isSignedIntSetCC(Cond)) { 2463 C0 = N0C->getSignExtended(); 2464 C1 = N1C->getSignExtended(); 2465 } 2466 2467 switch (Cond) { 2468 default: assert(0 && "Unknown integer setcc!"); 2469 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT); 2470 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT); 2471 case ISD::SETULT: return DAG.getConstant(C0 < C1, VT); 2472 case ISD::SETUGT: return DAG.getConstant(C0 > C1, VT); 2473 case ISD::SETULE: return DAG.getConstant(C0 <= C1, VT); 2474 case ISD::SETUGE: return DAG.getConstant(C0 >= C1, VT); 2475 case ISD::SETLT: return DAG.getConstant((int64_t)C0 < (int64_t)C1, VT); 2476 case ISD::SETGT: return DAG.getConstant((int64_t)C0 > (int64_t)C1, VT); 2477 case ISD::SETLE: return DAG.getConstant((int64_t)C0 <= (int64_t)C1, VT); 2478 case ISD::SETGE: return DAG.getConstant((int64_t)C0 >= (int64_t)C1, VT); 2479 } 2480 } else { 2481 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 2482 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 2483 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType()); 2484 2485 // If the comparison constant has bits in the upper part, the 2486 // zero-extended value could never match. 2487 if (C1 & (~0ULL << InSize)) { 2488 unsigned VSize = MVT::getSizeInBits(N0.getValueType()); 2489 switch (Cond) { 2490 case ISD::SETUGT: 2491 case ISD::SETUGE: 2492 case ISD::SETEQ: return DAG.getConstant(0, VT); 2493 case ISD::SETULT: 2494 case ISD::SETULE: 2495 case ISD::SETNE: return DAG.getConstant(1, VT); 2496 case ISD::SETGT: 2497 case ISD::SETGE: 2498 // True if the sign bit of C1 is set. 2499 return DAG.getConstant((C1 & (1ULL << VSize)) != 0, VT); 2500 case ISD::SETLT: 2501 case ISD::SETLE: 2502 // True if the sign bit of C1 isn't set. 2503 return DAG.getConstant((C1 & (1ULL << VSize)) == 0, VT); 2504 default: 2505 break; 2506 } 2507 } 2508 2509 // Otherwise, we can perform the comparison with the low bits. 2510 switch (Cond) { 2511 case ISD::SETEQ: 2512 case ISD::SETNE: 2513 case ISD::SETUGT: 2514 case ISD::SETUGE: 2515 case ISD::SETULT: 2516 case ISD::SETULE: 2517 return DAG.getSetCC(VT, N0.getOperand(0), 2518 DAG.getConstant(C1, N0.getOperand(0).getValueType()), 2519 Cond); 2520 default: 2521 break; // todo, be more careful with signed comparisons 2522 } 2523 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 2524 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 2525 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 2526 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy); 2527 MVT::ValueType ExtDstTy = N0.getValueType(); 2528 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy); 2529 2530 // If the extended part has any inconsistent bits, it cannot ever 2531 // compare equal. In other words, they have to be all ones or all 2532 // zeros. 2533 uint64_t ExtBits = 2534 (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1)); 2535 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits) 2536 return DAG.getConstant(Cond == ISD::SETNE, VT); 2537 2538 SDOperand ZextOp; 2539 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType(); 2540 if (Op0Ty == ExtSrcTy) { 2541 ZextOp = N0.getOperand(0); 2542 } else { 2543 int64_t Imm = ~0ULL >> (64-ExtSrcTyBits); 2544 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0), 2545 DAG.getConstant(Imm, Op0Ty)); 2546 } 2547 WorkList.push_back(ZextOp.Val); 2548 // Otherwise, make this a use of a zext. 2549 return DAG.getSetCC(VT, ZextOp, 2550 DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)), 2551 ExtDstTy), 2552 Cond); 2553 } 2554 2555 uint64_t MinVal, MaxVal; 2556 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0)); 2557 if (ISD::isSignedIntSetCC(Cond)) { 2558 MinVal = 1ULL << (OperandBitSize-1); 2559 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined. 2560 MaxVal = ~0ULL >> (65-OperandBitSize); 2561 else 2562 MaxVal = 0; 2563 } else { 2564 MinVal = 0; 2565 MaxVal = ~0ULL >> (64-OperandBitSize); 2566 } 2567 2568 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 2569 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 2570 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 2571 --C1; // X >= C0 --> X > (C0-1) 2572 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()), 2573 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 2574 } 2575 2576 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 2577 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 2578 ++C1; // X <= C0 --> X < (C0+1) 2579 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()), 2580 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 2581 } 2582 2583 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 2584 return DAG.getConstant(0, VT); // X < MIN --> false 2585 2586 // Canonicalize setgt X, Min --> setne X, Min 2587 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 2588 return DAG.getSetCC(VT, N0, N1, ISD::SETNE); 2589 // Canonicalize setlt X, Max --> setne X, Max 2590 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) 2591 return DAG.getSetCC(VT, N0, N1, ISD::SETNE); 2592 2593 // If we have setult X, 1, turn it into seteq X, 0 2594 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 2595 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()), 2596 ISD::SETEQ); 2597 // If we have setugt X, Max-1, turn it into seteq X, Max 2598 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 2599 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()), 2600 ISD::SETEQ); 2601 2602 // If we have "setcc X, C0", check to see if we can shrink the immediate 2603 // by changing cc. 2604 2605 // SETUGT X, SINTMAX -> SETLT X, 0 2606 if (Cond == ISD::SETUGT && OperandBitSize != 1 && 2607 C1 == (~0ULL >> (65-OperandBitSize))) 2608 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()), 2609 ISD::SETLT); 2610 2611 // FIXME: Implement the rest of these. 2612 2613 // Fold bit comparisons when we can. 2614 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2615 VT == N0.getValueType() && N0.getOpcode() == ISD::AND) 2616 if (ConstantSDNode *AndRHS = 2617 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2618 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 2619 // Perform the xform if the AND RHS is a single bit. 2620 if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) { 2621 return DAG.getNode(ISD::SRL, VT, N0, 2622 DAG.getConstant(Log2_64(AndRHS->getValue()), 2623 TLI.getShiftAmountTy())); 2624 } 2625 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) { 2626 // (X & 8) == 8 --> (X & 8) >> 3 2627 // Perform the xform if C1 is a single bit. 2628 if ((C1 & (C1-1)) == 0) { 2629 return DAG.getNode(ISD::SRL, VT, N0, 2630 DAG.getConstant(Log2_64(C1),TLI.getShiftAmountTy())); 2631 } 2632 } 2633 } 2634 } 2635 } else if (isa<ConstantSDNode>(N0.Val)) { 2636 // Ensure that the constant occurs on the RHS. 2637 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 2638 } 2639 2640 if (ConstantFPSDNode *N0C = dyn_cast<ConstantFPSDNode>(N0.Val)) 2641 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) { 2642 double C0 = N0C->getValue(), C1 = N1C->getValue(); 2643 2644 switch (Cond) { 2645 default: break; // FIXME: Implement the rest of these! 2646 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT); 2647 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT); 2648 case ISD::SETLT: return DAG.getConstant(C0 < C1, VT); 2649 case ISD::SETGT: return DAG.getConstant(C0 > C1, VT); 2650 case ISD::SETLE: return DAG.getConstant(C0 <= C1, VT); 2651 case ISD::SETGE: return DAG.getConstant(C0 >= C1, VT); 2652 } 2653 } else { 2654 // Ensure that the constant occurs on the RHS. 2655 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 2656 } 2657 2658 if (N0 == N1) { 2659 // We can always fold X == Y for integer setcc's. 2660 if (MVT::isInteger(N0.getValueType())) 2661 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2662 unsigned UOF = ISD::getUnorderedFlavor(Cond); 2663 if (UOF == 2) // FP operators that are undefined on NaNs. 2664 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2665 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 2666 return DAG.getConstant(UOF, VT); 2667 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 2668 // if it is not already. 2669 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; 2670 if (NewCond != Cond) 2671 return DAG.getSetCC(VT, N0, N1, NewCond); 2672 } 2673 2674 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2675 MVT::isInteger(N0.getValueType())) { 2676 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 2677 N0.getOpcode() == ISD::XOR) { 2678 // Simplify (X+Y) == (X+Z) --> Y == Z 2679 if (N0.getOpcode() == N1.getOpcode()) { 2680 if (N0.getOperand(0) == N1.getOperand(0)) 2681 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond); 2682 if (N0.getOperand(1) == N1.getOperand(1)) 2683 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond); 2684 if (isCommutativeBinOp(N0.getOpcode())) { 2685 // If X op Y == Y op X, try other combinations. 2686 if (N0.getOperand(0) == N1.getOperand(1)) 2687 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond); 2688 if (N0.getOperand(1) == N1.getOperand(0)) 2689 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond); 2690 } 2691 } 2692 2693 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 2694 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2695 // Turn (X+C1) == C2 --> X == C2-C1 2696 if (N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse()) { 2697 return DAG.getSetCC(VT, N0.getOperand(0), 2698 DAG.getConstant(RHSC->getValue()-LHSR->getValue(), 2699 N0.getValueType()), Cond); 2700 } 2701 2702 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. 2703 if (N0.getOpcode() == ISD::XOR) 2704 // If we know that all of the inverted bits are zero, don't bother 2705 // performing the inversion. 2706 if (TLI.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getValue())) 2707 return DAG.getSetCC(VT, N0.getOperand(0), 2708 DAG.getConstant(LHSR->getValue()^RHSC->getValue(), 2709 N0.getValueType()), Cond); 2710 } 2711 2712 // Turn (C1-X) == C2 --> X == C1-C2 2713 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { 2714 if (N0.getOpcode() == ISD::SUB && N0.Val->hasOneUse()) { 2715 return DAG.getSetCC(VT, N0.getOperand(1), 2716 DAG.getConstant(SUBC->getValue()-RHSC->getValue(), 2717 N0.getValueType()), Cond); 2718 } 2719 } 2720 } 2721 2722 // Simplify (X+Z) == X --> Z == 0 2723 if (N0.getOperand(0) == N1) 2724 return DAG.getSetCC(VT, N0.getOperand(1), 2725 DAG.getConstant(0, N0.getValueType()), Cond); 2726 if (N0.getOperand(1) == N1) { 2727 if (isCommutativeBinOp(N0.getOpcode())) 2728 return DAG.getSetCC(VT, N0.getOperand(0), 2729 DAG.getConstant(0, N0.getValueType()), Cond); 2730 else { 2731 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 2732 // (Z-X) == X --> Z == X<<1 2733 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), 2734 N1, 2735 DAG.getConstant(1,TLI.getShiftAmountTy())); 2736 WorkList.push_back(SH.Val); 2737 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond); 2738 } 2739 } 2740 } 2741 2742 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 2743 N1.getOpcode() == ISD::XOR) { 2744 // Simplify X == (X+Z) --> Z == 0 2745 if (N1.getOperand(0) == N0) { 2746 return DAG.getSetCC(VT, N1.getOperand(1), 2747 DAG.getConstant(0, N1.getValueType()), Cond); 2748 } else if (N1.getOperand(1) == N0) { 2749 if (isCommutativeBinOp(N1.getOpcode())) { 2750 return DAG.getSetCC(VT, N1.getOperand(0), 2751 DAG.getConstant(0, N1.getValueType()), Cond); 2752 } else { 2753 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 2754 // X == (Z-X) --> X<<1 == Z 2755 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0, 2756 DAG.getConstant(1,TLI.getShiftAmountTy())); 2757 WorkList.push_back(SH.Val); 2758 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond); 2759 } 2760 } 2761 } 2762 } 2763 2764 // Fold away ALL boolean setcc's. 2765 SDOperand Temp; 2766 if (N0.getValueType() == MVT::i1 && foldBooleans) { 2767 switch (Cond) { 2768 default: assert(0 && "Unknown integer setcc!"); 2769 case ISD::SETEQ: // X == Y -> (X^Y)^1 2770 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 2771 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1)); 2772 WorkList.push_back(Temp.Val); 2773 break; 2774 case ISD::SETNE: // X != Y --> (X^Y) 2775 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 2776 break; 2777 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y 2778 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y 2779 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 2780 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp); 2781 WorkList.push_back(Temp.Val); 2782 break; 2783 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X 2784 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X 2785 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 2786 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp); 2787 WorkList.push_back(Temp.Val); 2788 break; 2789 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y 2790 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y 2791 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 2792 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp); 2793 WorkList.push_back(Temp.Val); 2794 break; 2795 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X 2796 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X 2797 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 2798 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp); 2799 break; 2800 } 2801 if (VT != MVT::i1) { 2802 WorkList.push_back(N0.Val); 2803 // FIXME: If running after legalize, we probably can't do this. 2804 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 2805 } 2806 return N0; 2807 } 2808 2809 // Could not fold it. 2810 return SDOperand(); 2811} 2812 2813/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 2814/// return a DAG expression to select that will generate the same value by 2815/// multiplying by a magic number. See: 2816/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2817SDOperand DAGCombiner::BuildSDIV(SDNode *N) { 2818 MVT::ValueType VT = N->getValueType(0); 2819 2820 // Check to see if we can do this. 2821 if (!TLI.isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64)) 2822 return SDOperand(); // BuildSDIV only operates on i32 or i64 2823 if (!TLI.isOperationLegal(ISD::MULHS, VT)) 2824 return SDOperand(); // Make sure the target supports MULHS. 2825 2826 int64_t d = cast<ConstantSDNode>(N->getOperand(1))->getSignExtended(); 2827 ms magics = (VT == MVT::i32) ? magic32(d) : magic64(d); 2828 2829 // Multiply the numerator (operand 0) by the magic value 2830 SDOperand Q = DAG.getNode(ISD::MULHS, VT, N->getOperand(0), 2831 DAG.getConstant(magics.m, VT)); 2832 // If d > 0 and m < 0, add the numerator 2833 if (d > 0 && magics.m < 0) { 2834 Q = DAG.getNode(ISD::ADD, VT, Q, N->getOperand(0)); 2835 WorkList.push_back(Q.Val); 2836 } 2837 // If d < 0 and m > 0, subtract the numerator. 2838 if (d < 0 && magics.m > 0) { 2839 Q = DAG.getNode(ISD::SUB, VT, Q, N->getOperand(0)); 2840 WorkList.push_back(Q.Val); 2841 } 2842 // Shift right algebraic if shift value is nonzero 2843 if (magics.s > 0) { 2844 Q = DAG.getNode(ISD::SRA, VT, Q, 2845 DAG.getConstant(magics.s, TLI.getShiftAmountTy())); 2846 WorkList.push_back(Q.Val); 2847 } 2848 // Extract the sign bit and add it to the quotient 2849 SDOperand T = 2850 DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(MVT::getSizeInBits(VT)-1, 2851 TLI.getShiftAmountTy())); 2852 WorkList.push_back(T.Val); 2853 return DAG.getNode(ISD::ADD, VT, Q, T); 2854} 2855 2856/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 2857/// return a DAG expression to select that will generate the same value by 2858/// multiplying by a magic number. See: 2859/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2860SDOperand DAGCombiner::BuildUDIV(SDNode *N) { 2861 MVT::ValueType VT = N->getValueType(0); 2862 2863 // Check to see if we can do this. 2864 if (!TLI.isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64)) 2865 return SDOperand(); // BuildUDIV only operates on i32 or i64 2866 if (!TLI.isOperationLegal(ISD::MULHU, VT)) 2867 return SDOperand(); // Make sure the target supports MULHU. 2868 2869 uint64_t d = cast<ConstantSDNode>(N->getOperand(1))->getValue(); 2870 mu magics = (VT == MVT::i32) ? magicu32(d) : magicu64(d); 2871 2872 // Multiply the numerator (operand 0) by the magic value 2873 SDOperand Q = DAG.getNode(ISD::MULHU, VT, N->getOperand(0), 2874 DAG.getConstant(magics.m, VT)); 2875 WorkList.push_back(Q.Val); 2876 2877 if (magics.a == 0) { 2878 return DAG.getNode(ISD::SRL, VT, Q, 2879 DAG.getConstant(magics.s, TLI.getShiftAmountTy())); 2880 } else { 2881 SDOperand NPQ = DAG.getNode(ISD::SUB, VT, N->getOperand(0), Q); 2882 WorkList.push_back(NPQ.Val); 2883 NPQ = DAG.getNode(ISD::SRL, VT, NPQ, 2884 DAG.getConstant(1, TLI.getShiftAmountTy())); 2885 WorkList.push_back(NPQ.Val); 2886 NPQ = DAG.getNode(ISD::ADD, VT, NPQ, Q); 2887 WorkList.push_back(NPQ.Val); 2888 return DAG.getNode(ISD::SRL, VT, NPQ, 2889 DAG.getConstant(magics.s-1, TLI.getShiftAmountTy())); 2890 } 2891} 2892 2893// SelectionDAG::Combine - This is the entry point for the file. 2894// 2895void SelectionDAG::Combine(bool RunningAfterLegalize) { 2896 /// run - This is the main entry point to this class. 2897 /// 2898 DAGCombiner(*this).Run(RunningAfterLegalize); 2899} 2900