DAGCombiner.cpp revision c6a454e8d57acd47e9769516b36ce0810e9dc4f4
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Nate Begeman and is distributed under the 6// University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// FIXME: Missing folds 14// sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into 15// a sequence of multiplies, shifts, and adds. This should be controlled by 16// some kind of hint from the target that int div is expensive. 17// various folds of mulh[s,u] by constants such as -1, powers of 2, etc. 18// 19// FIXME: Should add a corresponding version of fold AND with 20// ZERO_EXTEND/SIGN_EXTEND by converting them to an ANY_EXTEND node which 21// we don't have yet. 22// 23// FIXME: select C, pow2, pow2 -> something smart 24// FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z) 25// FIXME: Dead stores -> nuke 26// FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!) 27// FIXME: mul (x, const) -> shifts + adds 28// FIXME: undef values 29// FIXME: make truncate see through SIGN_EXTEND and AND 30// FIXME: (sra (sra x, c1), c2) -> (sra x, c1+c2) 31// FIXME: verify that getNode can't return extends with an operand whose type 32// is >= to that of the extend. 33// FIXME: divide by zero is currently left unfolded. do we want to turn this 34// into an undef? 35// FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false 36// FIXME: reassociate (X+C)+Y into (X+Y)+C if the inner expression has one use 37// 38//===----------------------------------------------------------------------===// 39 40#define DEBUG_TYPE "dagcombine" 41#include "llvm/ADT/Statistic.h" 42#include "llvm/CodeGen/SelectionDAG.h" 43#include "llvm/Support/Debug.h" 44#include "llvm/Support/MathExtras.h" 45#include "llvm/Target/TargetLowering.h" 46#include <algorithm> 47#include <cmath> 48using namespace llvm; 49 50namespace { 51 Statistic<> NodesCombined ("dagcombiner", "Number of dag nodes combined"); 52 53 class DAGCombiner { 54 SelectionDAG &DAG; 55 TargetLowering &TLI; 56 bool AfterLegalize; 57 58 // Worklist of all of the nodes that need to be simplified. 59 std::vector<SDNode*> WorkList; 60 61 /// AddUsersToWorkList - When an instruction is simplified, add all users of 62 /// the instruction to the work lists because they might get more simplified 63 /// now. 64 /// 65 void AddUsersToWorkList(SDNode *N) { 66 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 67 UI != UE; ++UI) 68 WorkList.push_back(*UI); 69 } 70 71 /// removeFromWorkList - remove all instances of N from the worklist. 72 void removeFromWorkList(SDNode *N) { 73 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 74 WorkList.end()); 75 } 76 77 SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To) { 78 ++NodesCombined; 79 DEBUG(std::cerr << "\nReplacing "; N->dump(); 80 std::cerr << "\nWith: "; To[0].Val->dump(); 81 std::cerr << " and " << To.size()-1 << " other values\n"); 82 std::vector<SDNode*> NowDead; 83 DAG.ReplaceAllUsesWith(N, To, &NowDead); 84 85 // Push the new nodes and any users onto the worklist 86 for (unsigned i = 0, e = To.size(); i != e; ++i) { 87 WorkList.push_back(To[i].Val); 88 AddUsersToWorkList(To[i].Val); 89 } 90 91 // Nodes can end up on the worklist more than once. Make sure we do 92 // not process a node that has been replaced. 93 removeFromWorkList(N); 94 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 95 removeFromWorkList(NowDead[i]); 96 97 // Finally, since the node is now dead, remove it from the graph. 98 DAG.DeleteNode(N); 99 return SDOperand(N, 0); 100 } 101 102 SDOperand CombineTo(SDNode *N, SDOperand Res) { 103 std::vector<SDOperand> To; 104 To.push_back(Res); 105 return CombineTo(N, To); 106 } 107 108 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) { 109 std::vector<SDOperand> To; 110 To.push_back(Res0); 111 To.push_back(Res1); 112 return CombineTo(N, To); 113 } 114 115 /// visit - call the node-specific routine that knows how to fold each 116 /// particular type of node. 117 SDOperand visit(SDNode *N); 118 119 // Visitation implementation - Implement dag node combining for different 120 // node types. The semantics are as follows: 121 // Return Value: 122 // SDOperand.Val == 0 - No change was made 123 // SDOperand.Val == N - N was replaced, is dead, and is already handled. 124 // otherwise - N should be replaced by the returned Operand. 125 // 126 SDOperand visitTokenFactor(SDNode *N); 127 SDOperand visitADD(SDNode *N); 128 SDOperand visitSUB(SDNode *N); 129 SDOperand visitMUL(SDNode *N); 130 SDOperand visitSDIV(SDNode *N); 131 SDOperand visitUDIV(SDNode *N); 132 SDOperand visitSREM(SDNode *N); 133 SDOperand visitUREM(SDNode *N); 134 SDOperand visitMULHU(SDNode *N); 135 SDOperand visitMULHS(SDNode *N); 136 SDOperand visitAND(SDNode *N); 137 SDOperand visitOR(SDNode *N); 138 SDOperand visitXOR(SDNode *N); 139 SDOperand visitSHL(SDNode *N); 140 SDOperand visitSRA(SDNode *N); 141 SDOperand visitSRL(SDNode *N); 142 SDOperand visitCTLZ(SDNode *N); 143 SDOperand visitCTTZ(SDNode *N); 144 SDOperand visitCTPOP(SDNode *N); 145 SDOperand visitSELECT(SDNode *N); 146 SDOperand visitSELECT_CC(SDNode *N); 147 SDOperand visitSETCC(SDNode *N); 148 SDOperand visitADD_PARTS(SDNode *N); 149 SDOperand visitSUB_PARTS(SDNode *N); 150 SDOperand visitSIGN_EXTEND(SDNode *N); 151 SDOperand visitZERO_EXTEND(SDNode *N); 152 SDOperand visitSIGN_EXTEND_INREG(SDNode *N); 153 SDOperand visitTRUNCATE(SDNode *N); 154 155 SDOperand visitFADD(SDNode *N); 156 SDOperand visitFSUB(SDNode *N); 157 SDOperand visitFMUL(SDNode *N); 158 SDOperand visitFDIV(SDNode *N); 159 SDOperand visitFREM(SDNode *N); 160 SDOperand visitSINT_TO_FP(SDNode *N); 161 SDOperand visitUINT_TO_FP(SDNode *N); 162 SDOperand visitFP_TO_SINT(SDNode *N); 163 SDOperand visitFP_TO_UINT(SDNode *N); 164 SDOperand visitFP_ROUND(SDNode *N); 165 SDOperand visitFP_ROUND_INREG(SDNode *N); 166 SDOperand visitFP_EXTEND(SDNode *N); 167 SDOperand visitFNEG(SDNode *N); 168 SDOperand visitFABS(SDNode *N); 169 SDOperand visitBRCOND(SDNode *N); 170 SDOperand visitBRCONDTWOWAY(SDNode *N); 171 SDOperand visitBR_CC(SDNode *N); 172 SDOperand visitBRTWOWAY_CC(SDNode *N); 173 174 SDOperand visitLOAD(SDNode *N); 175 SDOperand visitSTORE(SDNode *N); 176 177 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS); 178 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2); 179 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2, 180 SDOperand N3, ISD::CondCode CC); 181 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, 182 ISD::CondCode Cond, bool foldBooleans = true); 183 184 SDOperand BuildSDIV(SDNode *N); 185 SDOperand BuildUDIV(SDNode *N); 186public: 187 DAGCombiner(SelectionDAG &D) 188 : DAG(D), TLI(D.getTargetLoweringInfo()), AfterLegalize(false) {} 189 190 /// Run - runs the dag combiner on all nodes in the work list 191 void Run(bool RunningAfterLegalize); 192 }; 193} 194 195struct ms { 196 int64_t m; // magic number 197 int64_t s; // shift amount 198}; 199 200struct mu { 201 uint64_t m; // magic number 202 int64_t a; // add indicator 203 int64_t s; // shift amount 204}; 205 206/// magic - calculate the magic numbers required to codegen an integer sdiv as 207/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1, 208/// or -1. 209static ms magic32(int32_t d) { 210 int32_t p; 211 uint32_t ad, anc, delta, q1, r1, q2, r2, t; 212 const uint32_t two31 = 0x80000000U; 213 struct ms mag; 214 215 ad = abs(d); 216 t = two31 + ((uint32_t)d >> 31); 217 anc = t - 1 - t%ad; // absolute value of nc 218 p = 31; // initialize p 219 q1 = two31/anc; // initialize q1 = 2p/abs(nc) 220 r1 = two31 - q1*anc; // initialize r1 = rem(2p,abs(nc)) 221 q2 = two31/ad; // initialize q2 = 2p/abs(d) 222 r2 = two31 - q2*ad; // initialize r2 = rem(2p,abs(d)) 223 do { 224 p = p + 1; 225 q1 = 2*q1; // update q1 = 2p/abs(nc) 226 r1 = 2*r1; // update r1 = rem(2p/abs(nc)) 227 if (r1 >= anc) { // must be unsigned comparison 228 q1 = q1 + 1; 229 r1 = r1 - anc; 230 } 231 q2 = 2*q2; // update q2 = 2p/abs(d) 232 r2 = 2*r2; // update r2 = rem(2p/abs(d)) 233 if (r2 >= ad) { // must be unsigned comparison 234 q2 = q2 + 1; 235 r2 = r2 - ad; 236 } 237 delta = ad - r2; 238 } while (q1 < delta || (q1 == delta && r1 == 0)); 239 240 mag.m = (int32_t)(q2 + 1); // make sure to sign extend 241 if (d < 0) mag.m = -mag.m; // resulting magic number 242 mag.s = p - 32; // resulting shift 243 return mag; 244} 245 246/// magicu - calculate the magic numbers required to codegen an integer udiv as 247/// a sequence of multiply, add and shifts. Requires that the divisor not be 0. 248static mu magicu32(uint32_t d) { 249 int32_t p; 250 uint32_t nc, delta, q1, r1, q2, r2; 251 struct mu magu; 252 magu.a = 0; // initialize "add" indicator 253 nc = - 1 - (-d)%d; 254 p = 31; // initialize p 255 q1 = 0x80000000/nc; // initialize q1 = 2p/nc 256 r1 = 0x80000000 - q1*nc; // initialize r1 = rem(2p,nc) 257 q2 = 0x7FFFFFFF/d; // initialize q2 = (2p-1)/d 258 r2 = 0x7FFFFFFF - q2*d; // initialize r2 = rem((2p-1),d) 259 do { 260 p = p + 1; 261 if (r1 >= nc - r1 ) { 262 q1 = 2*q1 + 1; // update q1 263 r1 = 2*r1 - nc; // update r1 264 } 265 else { 266 q1 = 2*q1; // update q1 267 r1 = 2*r1; // update r1 268 } 269 if (r2 + 1 >= d - r2) { 270 if (q2 >= 0x7FFFFFFF) magu.a = 1; 271 q2 = 2*q2 + 1; // update q2 272 r2 = 2*r2 + 1 - d; // update r2 273 } 274 else { 275 if (q2 >= 0x80000000) magu.a = 1; 276 q2 = 2*q2; // update q2 277 r2 = 2*r2 + 1; // update r2 278 } 279 delta = d - 1 - r2; 280 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0))); 281 magu.m = q2 + 1; // resulting magic number 282 magu.s = p - 32; // resulting shift 283 return magu; 284} 285 286/// magic - calculate the magic numbers required to codegen an integer sdiv as 287/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1, 288/// or -1. 289static ms magic64(int64_t d) { 290 int64_t p; 291 uint64_t ad, anc, delta, q1, r1, q2, r2, t; 292 const uint64_t two63 = 9223372036854775808ULL; // 2^63 293 struct ms mag; 294 295 ad = d >= 0 ? d : -d; 296 t = two63 + ((uint64_t)d >> 63); 297 anc = t - 1 - t%ad; // absolute value of nc 298 p = 63; // initialize p 299 q1 = two63/anc; // initialize q1 = 2p/abs(nc) 300 r1 = two63 - q1*anc; // initialize r1 = rem(2p,abs(nc)) 301 q2 = two63/ad; // initialize q2 = 2p/abs(d) 302 r2 = two63 - q2*ad; // initialize r2 = rem(2p,abs(d)) 303 do { 304 p = p + 1; 305 q1 = 2*q1; // update q1 = 2p/abs(nc) 306 r1 = 2*r1; // update r1 = rem(2p/abs(nc)) 307 if (r1 >= anc) { // must be unsigned comparison 308 q1 = q1 + 1; 309 r1 = r1 - anc; 310 } 311 q2 = 2*q2; // update q2 = 2p/abs(d) 312 r2 = 2*r2; // update r2 = rem(2p/abs(d)) 313 if (r2 >= ad) { // must be unsigned comparison 314 q2 = q2 + 1; 315 r2 = r2 - ad; 316 } 317 delta = ad - r2; 318 } while (q1 < delta || (q1 == delta && r1 == 0)); 319 320 mag.m = q2 + 1; 321 if (d < 0) mag.m = -mag.m; // resulting magic number 322 mag.s = p - 64; // resulting shift 323 return mag; 324} 325 326/// magicu - calculate the magic numbers required to codegen an integer udiv as 327/// a sequence of multiply, add and shifts. Requires that the divisor not be 0. 328static mu magicu64(uint64_t d) 329{ 330 int64_t p; 331 uint64_t nc, delta, q1, r1, q2, r2; 332 struct mu magu; 333 magu.a = 0; // initialize "add" indicator 334 nc = - 1 - (-d)%d; 335 p = 63; // initialize p 336 q1 = 0x8000000000000000ull/nc; // initialize q1 = 2p/nc 337 r1 = 0x8000000000000000ull - q1*nc; // initialize r1 = rem(2p,nc) 338 q2 = 0x7FFFFFFFFFFFFFFFull/d; // initialize q2 = (2p-1)/d 339 r2 = 0x7FFFFFFFFFFFFFFFull - q2*d; // initialize r2 = rem((2p-1),d) 340 do { 341 p = p + 1; 342 if (r1 >= nc - r1 ) { 343 q1 = 2*q1 + 1; // update q1 344 r1 = 2*r1 - nc; // update r1 345 } 346 else { 347 q1 = 2*q1; // update q1 348 r1 = 2*r1; // update r1 349 } 350 if (r2 + 1 >= d - r2) { 351 if (q2 >= 0x7FFFFFFFFFFFFFFFull) magu.a = 1; 352 q2 = 2*q2 + 1; // update q2 353 r2 = 2*r2 + 1 - d; // update r2 354 } 355 else { 356 if (q2 >= 0x8000000000000000ull) magu.a = 1; 357 q2 = 2*q2; // update q2 358 r2 = 2*r2 + 1; // update r2 359 } 360 delta = d - 1 - r2; 361 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0))); 362 magu.m = q2 + 1; // resulting magic number 363 magu.s = p - 64; // resulting shift 364 return magu; 365} 366 367/// MaskedValueIsZero - Return true if 'Op & Mask' is known to be zero. We use 368/// this predicate to simplify operations downstream. Op and Mask are known to 369/// be the same type. 370static bool MaskedValueIsZero(const SDOperand &Op, uint64_t Mask, 371 const TargetLowering &TLI) { 372 unsigned SrcBits; 373 if (Mask == 0) return true; 374 375 // If we know the result of a setcc has the top bits zero, use this info. 376 switch (Op.getOpcode()) { 377 case ISD::Constant: 378 return (cast<ConstantSDNode>(Op)->getValue() & Mask) == 0; 379 case ISD::SETCC: 380 return ((Mask & 1) == 0) && 381 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult; 382 case ISD::ZEXTLOAD: 383 SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(3))->getVT()); 384 return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits. 385 case ISD::ZERO_EXTEND: 386 SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType()); 387 return MaskedValueIsZero(Op.getOperand(0),Mask & ((1ULL << SrcBits)-1),TLI); 388 case ISD::AssertZext: 389 SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT()); 390 return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits. 391 case ISD::AND: 392 // If either of the operands has zero bits, the result will too. 393 if (MaskedValueIsZero(Op.getOperand(1), Mask, TLI) || 394 MaskedValueIsZero(Op.getOperand(0), Mask, TLI)) 395 return true; 396 // (X & C1) & C2 == 0 iff C1 & C2 == 0. 397 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1))) 398 return MaskedValueIsZero(Op.getOperand(0),AndRHS->getValue() & Mask, TLI); 399 return false; 400 case ISD::OR: 401 case ISD::XOR: 402 return MaskedValueIsZero(Op.getOperand(0), Mask, TLI) && 403 MaskedValueIsZero(Op.getOperand(1), Mask, TLI); 404 case ISD::SELECT: 405 return MaskedValueIsZero(Op.getOperand(1), Mask, TLI) && 406 MaskedValueIsZero(Op.getOperand(2), Mask, TLI); 407 case ISD::SELECT_CC: 408 return MaskedValueIsZero(Op.getOperand(2), Mask, TLI) && 409 MaskedValueIsZero(Op.getOperand(3), Mask, TLI); 410 case ISD::SRL: 411 // (ushr X, C1) & C2 == 0 iff X & (C2 << C1) == 0 412 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 413 uint64_t NewVal = Mask << ShAmt->getValue(); 414 SrcBits = MVT::getSizeInBits(Op.getValueType()); 415 if (SrcBits != 64) NewVal &= (1ULL << SrcBits)-1; 416 return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI); 417 } 418 return false; 419 case ISD::SHL: 420 // (ushl X, C1) & C2 == 0 iff X & (C2 >> C1) == 0 421 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 422 uint64_t NewVal = Mask >> ShAmt->getValue(); 423 return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI); 424 } 425 return false; 426 case ISD::ADD: 427 // (add X, Y) & C == 0 iff (X&C)|(Y&C) == 0 and all bits are low bits. 428 if ((Mask&(Mask+1)) == 0) { // All low bits 429 if (MaskedValueIsZero(Op.getOperand(0), Mask, TLI) && 430 MaskedValueIsZero(Op.getOperand(1), Mask, TLI)) 431 return true; 432 } 433 break; 434 case ISD::SUB: 435 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) { 436 // We know that the top bits of C-X are clear if X contains less bits 437 // than C (i.e. no wrap-around can happen). For example, 20-X is 438 // positive if we can prove that X is >= 0 and < 16. 439 unsigned Bits = MVT::getSizeInBits(CLHS->getValueType(0)); 440 if ((CLHS->getValue() & (1 << (Bits-1))) == 0) { // sign bit clear 441 unsigned NLZ = CountLeadingZeros_64(CLHS->getValue()+1); 442 uint64_t MaskV = (1ULL << (63-NLZ))-1; 443 if (MaskedValueIsZero(Op.getOperand(1), ~MaskV, TLI)) { 444 // High bits are clear this value is known to be >= C. 445 unsigned NLZ2 = CountLeadingZeros_64(CLHS->getValue()); 446 if ((Mask & ((1ULL << (64-NLZ2))-1)) == 0) 447 return true; 448 } 449 } 450 } 451 break; 452 case ISD::CTTZ: 453 case ISD::CTLZ: 454 case ISD::CTPOP: 455 // Bit counting instructions can not set the high bits of the result 456 // register. The max number of bits sets depends on the input. 457 return (Mask & (MVT::getSizeInBits(Op.getValueType())*2-1)) == 0; 458 default: break; 459 } 460 return false; 461} 462 463// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 464// that selects between the values 1 and 0, making it equivalent to a setcc. 465// Also, set the incoming LHS, RHS, and CC references to the appropriate 466// nodes based on the type of node we are checking. This simplifies life a 467// bit for the callers. 468static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS, 469 SDOperand &CC) { 470 if (N.getOpcode() == ISD::SETCC) { 471 LHS = N.getOperand(0); 472 RHS = N.getOperand(1); 473 CC = N.getOperand(2); 474 return true; 475 } 476 if (N.getOpcode() == ISD::SELECT_CC && 477 N.getOperand(2).getOpcode() == ISD::Constant && 478 N.getOperand(3).getOpcode() == ISD::Constant && 479 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 && 480 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 481 LHS = N.getOperand(0); 482 RHS = N.getOperand(1); 483 CC = N.getOperand(4); 484 return true; 485 } 486 return false; 487} 488 489// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 490// one use. If this is true, it allows the users to invert the operation for 491// free when it is profitable to do so. 492static bool isOneUseSetCC(SDOperand N) { 493 SDOperand N0, N1, N2; 494 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse()) 495 return true; 496 return false; 497} 498 499// FIXME: This should probably go in the ISD class rather than being duplicated 500// in several files. 501static bool isCommutativeBinOp(unsigned Opcode) { 502 switch (Opcode) { 503 case ISD::ADD: 504 case ISD::MUL: 505 case ISD::AND: 506 case ISD::OR: 507 case ISD::XOR: return true; 508 default: return false; // FIXME: Need commutative info for user ops! 509 } 510} 511 512void DAGCombiner::Run(bool RunningAfterLegalize) { 513 // set the instance variable, so that the various visit routines may use it. 514 AfterLegalize = RunningAfterLegalize; 515 516 // Add all the dag nodes to the worklist. 517 WorkList.insert(WorkList.end(), DAG.allnodes_begin(), DAG.allnodes_end()); 518 519 // Create a dummy node (which is not added to allnodes), that adds a reference 520 // to the root node, preventing it from being deleted, and tracking any 521 // changes of the root. 522 HandleSDNode Dummy(DAG.getRoot()); 523 524 // while the worklist isn't empty, inspect the node on the end of it and 525 // try and combine it. 526 while (!WorkList.empty()) { 527 SDNode *N = WorkList.back(); 528 WorkList.pop_back(); 529 530 // If N has no uses, it is dead. Make sure to revisit all N's operands once 531 // N is deleted from the DAG, since they too may now be dead or may have a 532 // reduced number of uses, allowing other xforms. 533 if (N->use_empty() && N != &Dummy) { 534 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 535 WorkList.push_back(N->getOperand(i).Val); 536 537 removeFromWorkList(N); 538 DAG.DeleteNode(N); 539 continue; 540 } 541 542 SDOperand RV = visit(N); 543 if (RV.Val) { 544 ++NodesCombined; 545 // If we get back the same node we passed in, rather than a new node or 546 // zero, we know that the node must have defined multiple values and 547 // CombineTo was used. Since CombineTo takes care of the worklist 548 // mechanics for us, we have no work to do in this case. 549 if (RV.Val != N) { 550 DEBUG(std::cerr << "\nReplacing "; N->dump(); 551 std::cerr << "\nWith: "; RV.Val->dump(); 552 std::cerr << '\n'); 553 std::vector<SDNode*> NowDead; 554 DAG.ReplaceAllUsesWith(N, std::vector<SDOperand>(1, RV), &NowDead); 555 556 // Push the new node and any users onto the worklist 557 WorkList.push_back(RV.Val); 558 AddUsersToWorkList(RV.Val); 559 560 // Nodes can end up on the worklist more than once. Make sure we do 561 // not process a node that has been replaced. 562 removeFromWorkList(N); 563 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 564 removeFromWorkList(NowDead[i]); 565 566 // Finally, since the node is now dead, remove it from the graph. 567 DAG.DeleteNode(N); 568 } 569 } 570 } 571 572 // If the root changed (e.g. it was a dead load, update the root). 573 DAG.setRoot(Dummy.getValue()); 574} 575 576SDOperand DAGCombiner::visit(SDNode *N) { 577 switch(N->getOpcode()) { 578 default: break; 579 case ISD::TokenFactor: return visitTokenFactor(N); 580 case ISD::ADD: return visitADD(N); 581 case ISD::SUB: return visitSUB(N); 582 case ISD::MUL: return visitMUL(N); 583 case ISD::SDIV: return visitSDIV(N); 584 case ISD::UDIV: return visitUDIV(N); 585 case ISD::SREM: return visitSREM(N); 586 case ISD::UREM: return visitUREM(N); 587 case ISD::MULHU: return visitMULHU(N); 588 case ISD::MULHS: return visitMULHS(N); 589 case ISD::AND: return visitAND(N); 590 case ISD::OR: return visitOR(N); 591 case ISD::XOR: return visitXOR(N); 592 case ISD::SHL: return visitSHL(N); 593 case ISD::SRA: return visitSRA(N); 594 case ISD::SRL: return visitSRL(N); 595 case ISD::CTLZ: return visitCTLZ(N); 596 case ISD::CTTZ: return visitCTTZ(N); 597 case ISD::CTPOP: return visitCTPOP(N); 598 case ISD::SELECT: return visitSELECT(N); 599 case ISD::SELECT_CC: return visitSELECT_CC(N); 600 case ISD::SETCC: return visitSETCC(N); 601 case ISD::ADD_PARTS: return visitADD_PARTS(N); 602 case ISD::SUB_PARTS: return visitSUB_PARTS(N); 603 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 604 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 605 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 606 case ISD::TRUNCATE: return visitTRUNCATE(N); 607 case ISD::FADD: return visitFADD(N); 608 case ISD::FSUB: return visitFSUB(N); 609 case ISD::FMUL: return visitFMUL(N); 610 case ISD::FDIV: return visitFDIV(N); 611 case ISD::FREM: return visitFREM(N); 612 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 613 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 614 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 615 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 616 case ISD::FP_ROUND: return visitFP_ROUND(N); 617 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 618 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 619 case ISD::FNEG: return visitFNEG(N); 620 case ISD::FABS: return visitFABS(N); 621 case ISD::BRCOND: return visitBRCOND(N); 622 case ISD::BRCONDTWOWAY: return visitBRCONDTWOWAY(N); 623 case ISD::BR_CC: return visitBR_CC(N); 624 case ISD::BRTWOWAY_CC: return visitBRTWOWAY_CC(N); 625 case ISD::LOAD: return visitLOAD(N); 626 case ISD::STORE: return visitSTORE(N); 627 } 628 return SDOperand(); 629} 630 631SDOperand DAGCombiner::visitTokenFactor(SDNode *N) { 632 std::vector<SDOperand> Ops; 633 bool Changed = false; 634 635 // If the token factor has two operands and one is the entry token, replace 636 // the token factor with the other operand. 637 if (N->getNumOperands() == 2) { 638 if (N->getOperand(0).getOpcode() == ISD::EntryToken) 639 return N->getOperand(1); 640 if (N->getOperand(1).getOpcode() == ISD::EntryToken) 641 return N->getOperand(0); 642 } 643 644 // fold (tokenfactor (tokenfactor)) -> tokenfactor 645 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 646 SDOperand Op = N->getOperand(i); 647 if (Op.getOpcode() == ISD::TokenFactor && Op.hasOneUse()) { 648 Changed = true; 649 for (unsigned j = 0, e = Op.getNumOperands(); j != e; ++j) 650 Ops.push_back(Op.getOperand(j)); 651 } else { 652 Ops.push_back(Op); 653 } 654 } 655 if (Changed) 656 return DAG.getNode(ISD::TokenFactor, MVT::Other, Ops); 657 return SDOperand(); 658} 659 660SDOperand DAGCombiner::visitADD(SDNode *N) { 661 SDOperand N0 = N->getOperand(0); 662 SDOperand N1 = N->getOperand(1); 663 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 664 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 665 MVT::ValueType VT = N0.getValueType(); 666 667 // fold (add c1, c2) -> c1+c2 668 if (N0C && N1C) 669 return DAG.getConstant(N0C->getValue() + N1C->getValue(), VT); 670 // canonicalize constant to RHS 671 if (N0C && !N1C) 672 return DAG.getNode(ISD::ADD, VT, N1, N0); 673 // fold (add x, 0) -> x 674 if (N1C && N1C->isNullValue()) 675 return N0; 676 // fold (add (add x, c1), c2) -> (add x, c1+c2) 677 if (N1C && N0.getOpcode() == ISD::ADD) { 678 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 679 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 680 if (N00C) 681 return DAG.getNode(ISD::ADD, VT, N0.getOperand(1), 682 DAG.getConstant(N1C->getValue()+N00C->getValue(), VT)); 683 if (N01C) 684 return DAG.getNode(ISD::ADD, VT, N0.getOperand(0), 685 DAG.getConstant(N1C->getValue()+N01C->getValue(), VT)); 686 } 687 // fold ((0-A) + B) -> B-A 688 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 689 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 690 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1)); 691 // fold (A + (0-B)) -> A-B 692 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 693 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 694 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1)); 695 // fold (A+(B-A)) -> B 696 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 697 return N1.getOperand(0); 698 return SDOperand(); 699} 700 701SDOperand DAGCombiner::visitSUB(SDNode *N) { 702 SDOperand N0 = N->getOperand(0); 703 SDOperand N1 = N->getOperand(1); 704 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 705 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 706 707 // fold (sub x, x) -> 0 708 if (N0 == N1) 709 return DAG.getConstant(0, N->getValueType(0)); 710 711 // fold (sub c1, c2) -> c1-c2 712 if (N0C && N1C) 713 return DAG.getConstant(N0C->getValue() - N1C->getValue(), 714 N->getValueType(0)); 715 // fold (sub x, c) -> (add x, -c) 716 if (N1C) 717 return DAG.getNode(ISD::ADD, N0.getValueType(), N0, 718 DAG.getConstant(-N1C->getValue(), N0.getValueType())); 719 720 // fold (A+B)-A -> B 721 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 722 return N0.getOperand(1); 723 // fold (A+B)-B -> A 724 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 725 return N0.getOperand(0); 726 return SDOperand(); 727} 728 729SDOperand DAGCombiner::visitMUL(SDNode *N) { 730 SDOperand N0 = N->getOperand(0); 731 SDOperand N1 = N->getOperand(1); 732 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 733 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 734 MVT::ValueType VT = N0.getValueType(); 735 736 // fold (mul c1, c2) -> c1*c2 737 if (N0C && N1C) 738 return DAG.getConstant(N0C->getValue() * N1C->getValue(), 739 N->getValueType(0)); 740 // canonicalize constant to RHS 741 if (N0C && !N1C) 742 return DAG.getNode(ISD::MUL, VT, N1, N0); 743 // fold (mul x, 0) -> 0 744 if (N1C && N1C->isNullValue()) 745 return N1; 746 // fold (mul x, -1) -> 0-x 747 if (N1C && N1C->isAllOnesValue()) 748 return DAG.getNode(ISD::SUB, N->getValueType(0), 749 DAG.getConstant(0, N->getValueType(0)), N0); 750 // fold (mul x, (1 << c)) -> x << c 751 if (N1C && isPowerOf2_64(N1C->getValue())) 752 return DAG.getNode(ISD::SHL, N->getValueType(0), N0, 753 DAG.getConstant(Log2_64(N1C->getValue()), 754 TLI.getShiftAmountTy())); 755 // fold (mul (mul x, c1), c2) -> (mul x, c1*c2) 756 if (N1C && N0.getOpcode() == ISD::MUL) { 757 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 758 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 759 if (N00C) 760 return DAG.getNode(ISD::MUL, VT, N0.getOperand(1), 761 DAG.getConstant(N1C->getValue()*N00C->getValue(), VT)); 762 if (N01C) 763 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), 764 DAG.getConstant(N1C->getValue()*N01C->getValue(), VT)); 765 } 766 return SDOperand(); 767} 768 769SDOperand DAGCombiner::visitSDIV(SDNode *N) { 770 SDOperand N0 = N->getOperand(0); 771 SDOperand N1 = N->getOperand(1); 772 MVT::ValueType VT = N->getValueType(0); 773 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 774 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 775 776 // fold (sdiv c1, c2) -> c1/c2 777 if (N0C && N1C && !N1C->isNullValue()) 778 return DAG.getConstant(N0C->getSignExtended() / N1C->getSignExtended(), 779 N->getValueType(0)); 780 // If we know the sign bits of both operands are zero, strength reduce to a 781 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 782 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 783 if (MaskedValueIsZero(N1, SignBit, TLI) && 784 MaskedValueIsZero(N0, SignBit, TLI)) 785 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1); 786 // if integer divide is expensive and we satisfy the requirements, emit an 787 // alternate sequence. 788 // FIXME: This currently opts out powers of two, since targets can often be 789 // more clever in those cases. In an idea world, we would have some way to 790 // detect that too. 791 if (N1C && !isPowerOf2_64(N1C->getSignExtended()) && 792 (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) && 793 TLI.isOperationLegal(ISD::MULHS, VT) && TLI.isTypeLegal(VT) && 794 TLI.isIntDivExpensive()) { 795 return BuildSDIV(N); 796 } 797 return SDOperand(); 798} 799 800SDOperand DAGCombiner::visitUDIV(SDNode *N) { 801 SDOperand N0 = N->getOperand(0); 802 SDOperand N1 = N->getOperand(1); 803 MVT::ValueType VT = N->getValueType(0); 804 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 805 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 806 807 // fold (udiv c1, c2) -> c1/c2 808 if (N0C && N1C && !N1C->isNullValue()) 809 return DAG.getConstant(N0C->getValue() / N1C->getValue(), 810 N->getValueType(0)); 811 // fold (udiv x, (1 << c)) -> x >>u c 812 if (N1C && isPowerOf2_64(N1C->getValue())) 813 return DAG.getNode(ISD::SRL, N->getValueType(0), N0, 814 DAG.getConstant(Log2_64(N1C->getValue()), 815 TLI.getShiftAmountTy())); 816 // fold (udiv x, c) -> alternate 817 if (N1C && N1C->getValue() && TLI.isOperationLegal(ISD::MULHU, VT) && 818 TLI.isTypeLegal(VT) && TLI.isIntDivExpensive()) 819 return BuildUDIV(N); 820 return SDOperand(); 821} 822 823SDOperand DAGCombiner::visitSREM(SDNode *N) { 824 SDOperand N0 = N->getOperand(0); 825 SDOperand N1 = N->getOperand(1); 826 MVT::ValueType VT = N->getValueType(0); 827 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 828 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 829 830 // fold (srem c1, c2) -> c1%c2 831 if (N0C && N1C && !N1C->isNullValue()) 832 return DAG.getConstant(N0C->getSignExtended() % N1C->getSignExtended(), 833 N->getValueType(0)); 834 // If we know the sign bits of both operands are zero, strength reduce to a 835 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 836 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 837 if (MaskedValueIsZero(N1, SignBit, TLI) && 838 MaskedValueIsZero(N0, SignBit, TLI)) 839 return DAG.getNode(ISD::UREM, N1.getValueType(), N0, N1); 840 return SDOperand(); 841} 842 843SDOperand DAGCombiner::visitUREM(SDNode *N) { 844 SDOperand N0 = N->getOperand(0); 845 SDOperand N1 = N->getOperand(1); 846 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 847 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 848 849 // fold (urem c1, c2) -> c1%c2 850 if (N0C && N1C && !N1C->isNullValue()) 851 return DAG.getConstant(N0C->getValue() % N1C->getValue(), 852 N->getValueType(0)); 853 // fold (urem x, pow2) -> (and x, pow2-1) 854 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue())) 855 return DAG.getNode(ISD::AND, N0.getValueType(), N0, 856 DAG.getConstant(N1C->getValue()-1, N1.getValueType())); 857 return SDOperand(); 858} 859 860SDOperand DAGCombiner::visitMULHS(SDNode *N) { 861 SDOperand N0 = N->getOperand(0); 862 SDOperand N1 = N->getOperand(1); 863 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 864 865 // fold (mulhs x, 0) -> 0 866 if (N1C && N1C->isNullValue()) 867 return N1; 868 // fold (mulhs x, 1) -> (sra x, size(x)-1) 869 if (N1C && N1C->getValue() == 1) 870 return DAG.getNode(ISD::SRA, N0.getValueType(), N0, 871 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1, 872 TLI.getShiftAmountTy())); 873 return SDOperand(); 874} 875 876SDOperand DAGCombiner::visitMULHU(SDNode *N) { 877 SDOperand N0 = N->getOperand(0); 878 SDOperand N1 = N->getOperand(1); 879 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 880 881 // fold (mulhu x, 0) -> 0 882 if (N1C && N1C->isNullValue()) 883 return N1; 884 // fold (mulhu x, 1) -> 0 885 if (N1C && N1C->getValue() == 1) 886 return DAG.getConstant(0, N0.getValueType()); 887 return SDOperand(); 888} 889 890SDOperand DAGCombiner::visitAND(SDNode *N) { 891 SDOperand N0 = N->getOperand(0); 892 SDOperand N1 = N->getOperand(1); 893 SDOperand LL, LR, RL, RR, CC0, CC1; 894 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 895 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 896 MVT::ValueType VT = N1.getValueType(); 897 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 898 899 // fold (and c1, c2) -> c1&c2 900 if (N0C && N1C) 901 return DAG.getConstant(N0C->getValue() & N1C->getValue(), VT); 902 // canonicalize constant to RHS 903 if (N0C && !N1C) 904 return DAG.getNode(ISD::AND, VT, N1, N0); 905 // fold (and x, -1) -> x 906 if (N1C && N1C->isAllOnesValue()) 907 return N0; 908 // if (and x, c) is known to be zero, return 0 909 if (N1C && MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits),TLI)) 910 return DAG.getConstant(0, VT); 911 // fold (and x, c) -> x iff (x & ~c) == 0 912 if (N1C && MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)), 913 TLI)) 914 return N0; 915 // fold (and (and x, c1), c2) -> (and x, c1^c2) 916 if (N1C && N0.getOpcode() == ISD::AND) { 917 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 918 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 919 if (N00C) 920 return DAG.getNode(ISD::AND, VT, N0.getOperand(1), 921 DAG.getConstant(N1C->getValue()&N00C->getValue(), VT)); 922 if (N01C) 923 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 924 DAG.getConstant(N1C->getValue()&N01C->getValue(), VT)); 925 } 926 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 927 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) { 928 unsigned ExtendBits = 929 MVT::getSizeInBits(cast<VTSDNode>(N0.getOperand(1))->getVT()); 930 if ((N1C->getValue() & (~0ULL << ExtendBits)) == 0) 931 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), N1); 932 } 933 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 934 if (N0.getOpcode() == ISD::OR && N1C) 935 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 936 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue()) 937 return N1; 938 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 939 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 940 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 941 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 942 943 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 944 MVT::isInteger(LL.getValueType())) { 945 // fold (X == 0) & (Y == 0) -> (X|Y == 0) 946 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) { 947 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 948 WorkList.push_back(ORNode.Val); 949 return DAG.getSetCC(VT, ORNode, LR, Op1); 950 } 951 // fold (X == -1) & (Y == -1) -> (X&Y == -1) 952 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 953 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 954 WorkList.push_back(ANDNode.Val); 955 return DAG.getSetCC(VT, ANDNode, LR, Op1); 956 } 957 // fold (X > -1) & (Y > -1) -> (X|Y > -1) 958 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 959 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 960 WorkList.push_back(ORNode.Val); 961 return DAG.getSetCC(VT, ORNode, LR, Op1); 962 } 963 } 964 // canonicalize equivalent to ll == rl 965 if (LL == RR && LR == RL) { 966 Op1 = ISD::getSetCCSwappedOperands(Op1); 967 std::swap(RL, RR); 968 } 969 if (LL == RL && LR == RR) { 970 bool isInteger = MVT::isInteger(LL.getValueType()); 971 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 972 if (Result != ISD::SETCC_INVALID) 973 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 974 } 975 } 976 // fold (and (zext x), (zext y)) -> (zext (and x, y)) 977 if (N0.getOpcode() == ISD::ZERO_EXTEND && 978 N1.getOpcode() == ISD::ZERO_EXTEND && 979 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 980 SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(), 981 N0.getOperand(0), N1.getOperand(0)); 982 WorkList.push_back(ANDNode.Val); 983 return DAG.getNode(ISD::ZERO_EXTEND, VT, ANDNode); 984 } 985 // fold (and (shl/srl x), (shl/srl y)) -> (shl/srl (and x, y)) 986 if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) || 987 (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL)) && 988 N0.getOperand(1) == N1.getOperand(1)) { 989 SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(), 990 N0.getOperand(0), N1.getOperand(0)); 991 WorkList.push_back(ANDNode.Val); 992 return DAG.getNode(N0.getOpcode(), VT, ANDNode, N0.getOperand(1)); 993 } 994 // fold (and (sra)) -> (and (srl)) when possible. 995 if (N0.getOpcode() == ISD::SRA && N0.Val->hasOneUse()) 996 if (ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 997 // If the RHS of the AND has zeros where the sign bits of the SRA will 998 // land, turn the SRA into an SRL. 999 if (MaskedValueIsZero(N1, (~0ULL << (OpSizeInBits-N01C->getValue())) & 1000 (~0ULL>>(64-OpSizeInBits)), TLI)) { 1001 WorkList.push_back(N); 1002 CombineTo(N0.Val, DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 1003 N0.getOperand(1))); 1004 return SDOperand(); 1005 } 1006 } 1007 1008 // fold (zext_inreg (extload x)) -> (zextload x) 1009 if (N0.getOpcode() == ISD::EXTLOAD) { 1010 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT(); 1011 // If we zero all the possible extended bits, then we can turn this into 1012 // a zextload if we are running before legalize or the operation is legal. 1013 if (MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT), TLI) && 1014 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) { 1015 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), 1016 N0.getOperand(1), N0.getOperand(2), 1017 EVT); 1018 WorkList.push_back(N); 1019 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1020 return SDOperand(); 1021 } 1022 } 1023 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1024 if (N0.getOpcode() == ISD::SEXTLOAD && N0.hasOneUse()) { 1025 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT(); 1026 // If we zero all the possible extended bits, then we can turn this into 1027 // a zextload if we are running before legalize or the operation is legal. 1028 if (MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT), TLI) && 1029 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) { 1030 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), 1031 N0.getOperand(1), N0.getOperand(2), 1032 EVT); 1033 WorkList.push_back(N); 1034 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1035 return SDOperand(); 1036 } 1037 } 1038 return SDOperand(); 1039} 1040 1041SDOperand DAGCombiner::visitOR(SDNode *N) { 1042 SDOperand N0 = N->getOperand(0); 1043 SDOperand N1 = N->getOperand(1); 1044 SDOperand LL, LR, RL, RR, CC0, CC1; 1045 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1046 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1047 MVT::ValueType VT = N1.getValueType(); 1048 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1049 1050 // fold (or c1, c2) -> c1|c2 1051 if (N0C && N1C) 1052 return DAG.getConstant(N0C->getValue() | N1C->getValue(), 1053 N->getValueType(0)); 1054 // canonicalize constant to RHS 1055 if (N0C && !N1C) 1056 return DAG.getNode(ISD::OR, VT, N1, N0); 1057 // fold (or x, 0) -> x 1058 if (N1C && N1C->isNullValue()) 1059 return N0; 1060 // fold (or x, -1) -> -1 1061 if (N1C && N1C->isAllOnesValue()) 1062 return N1; 1063 // fold (or x, c) -> c iff (x & ~c) == 0 1064 if (N1C && MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)), 1065 TLI)) 1066 return N1; 1067 // fold (or (or x, c1), c2) -> (or x, c1|c2) 1068 if (N1C && N0.getOpcode() == ISD::OR) { 1069 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 1070 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 1071 if (N00C) 1072 return DAG.getNode(ISD::OR, VT, N0.getOperand(1), 1073 DAG.getConstant(N1C->getValue()|N00C->getValue(), VT)); 1074 if (N01C) 1075 return DAG.getNode(ISD::OR, VT, N0.getOperand(0), 1076 DAG.getConstant(N1C->getValue()|N01C->getValue(), VT)); 1077 } 1078 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 1079 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1080 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1081 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1082 1083 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1084 MVT::isInteger(LL.getValueType())) { 1085 // fold (X != 0) | (Y != 0) -> (X|Y != 0) 1086 // fold (X < 0) | (Y < 0) -> (X|Y < 0) 1087 if (cast<ConstantSDNode>(LR)->getValue() == 0 && 1088 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 1089 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1090 WorkList.push_back(ORNode.Val); 1091 return DAG.getSetCC(VT, ORNode, LR, Op1); 1092 } 1093 // fold (X != -1) | (Y != -1) -> (X&Y != -1) 1094 // fold (X > -1) | (Y > -1) -> (X&Y > -1) 1095 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 1096 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 1097 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1098 WorkList.push_back(ANDNode.Val); 1099 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1100 } 1101 } 1102 // canonicalize equivalent to ll == rl 1103 if (LL == RR && LR == RL) { 1104 Op1 = ISD::getSetCCSwappedOperands(Op1); 1105 std::swap(RL, RR); 1106 } 1107 if (LL == RL && LR == RR) { 1108 bool isInteger = MVT::isInteger(LL.getValueType()); 1109 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 1110 if (Result != ISD::SETCC_INVALID) 1111 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1112 } 1113 } 1114 // fold (or (zext x), (zext y)) -> (zext (or x, y)) 1115 if (N0.getOpcode() == ISD::ZERO_EXTEND && 1116 N1.getOpcode() == ISD::ZERO_EXTEND && 1117 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1118 SDOperand ORNode = DAG.getNode(ISD::OR, N0.getOperand(0).getValueType(), 1119 N0.getOperand(0), N1.getOperand(0)); 1120 WorkList.push_back(ORNode.Val); 1121 return DAG.getNode(ISD::ZERO_EXTEND, VT, ORNode); 1122 } 1123 return SDOperand(); 1124} 1125 1126SDOperand DAGCombiner::visitXOR(SDNode *N) { 1127 SDOperand N0 = N->getOperand(0); 1128 SDOperand N1 = N->getOperand(1); 1129 SDOperand LHS, RHS, CC; 1130 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1131 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1132 MVT::ValueType VT = N0.getValueType(); 1133 1134 // fold (xor c1, c2) -> c1^c2 1135 if (N0C && N1C) 1136 return DAG.getConstant(N0C->getValue() ^ N1C->getValue(), VT); 1137 // canonicalize constant to RHS 1138 if (N0C && !N1C) 1139 return DAG.getNode(ISD::XOR, VT, N1, N0); 1140 // fold (xor x, 0) -> x 1141 if (N1C && N1C->isNullValue()) 1142 return N0; 1143 // fold !(x cc y) -> (x !cc y) 1144 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 1145 bool isInt = MVT::isInteger(LHS.getValueType()); 1146 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 1147 isInt); 1148 if (N0.getOpcode() == ISD::SETCC) 1149 return DAG.getSetCC(VT, LHS, RHS, NotCC); 1150 if (N0.getOpcode() == ISD::SELECT_CC) 1151 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC); 1152 assert(0 && "Unhandled SetCC Equivalent!"); 1153 abort(); 1154 } 1155 // fold !(x or y) -> (!x and !y) iff x or y are setcc 1156 if (N1C && N1C->getValue() == 1 && 1157 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 1158 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 1159 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 1160 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 1161 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 1162 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 1163 WorkList.push_back(LHS.Val); WorkList.push_back(RHS.Val); 1164 return DAG.getNode(NewOpcode, VT, LHS, RHS); 1165 } 1166 } 1167 // fold !(x or y) -> (!x and !y) iff x or y are constants 1168 if (N1C && N1C->isAllOnesValue() && 1169 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 1170 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 1171 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 1172 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 1173 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 1174 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 1175 WorkList.push_back(LHS.Val); WorkList.push_back(RHS.Val); 1176 return DAG.getNode(NewOpcode, VT, LHS, RHS); 1177 } 1178 } 1179 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2) 1180 if (N1C && N0.getOpcode() == ISD::XOR) { 1181 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 1182 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 1183 if (N00C) 1184 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1), 1185 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT)); 1186 if (N01C) 1187 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0), 1188 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT)); 1189 } 1190 // fold (xor x, x) -> 0 1191 if (N0 == N1) 1192 return DAG.getConstant(0, VT); 1193 // fold (xor (zext x), (zext y)) -> (zext (xor x, y)) 1194 if (N0.getOpcode() == ISD::ZERO_EXTEND && 1195 N1.getOpcode() == ISD::ZERO_EXTEND && 1196 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1197 SDOperand XORNode = DAG.getNode(ISD::XOR, N0.getOperand(0).getValueType(), 1198 N0.getOperand(0), N1.getOperand(0)); 1199 WorkList.push_back(XORNode.Val); 1200 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode); 1201 } 1202 return SDOperand(); 1203} 1204 1205SDOperand DAGCombiner::visitSHL(SDNode *N) { 1206 SDOperand N0 = N->getOperand(0); 1207 SDOperand N1 = N->getOperand(1); 1208 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1209 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1210 MVT::ValueType VT = N0.getValueType(); 1211 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1212 1213 // fold (shl c1, c2) -> c1<<c2 1214 if (N0C && N1C) 1215 return DAG.getConstant(N0C->getValue() << N1C->getValue(), VT); 1216 // fold (shl 0, x) -> 0 1217 if (N0C && N0C->isNullValue()) 1218 return N0; 1219 // fold (shl x, c >= size(x)) -> undef 1220 if (N1C && N1C->getValue() >= OpSizeInBits) 1221 return DAG.getNode(ISD::UNDEF, VT); 1222 // fold (shl x, 0) -> x 1223 if (N1C && N1C->isNullValue()) 1224 return N0; 1225 // if (shl x, c) is known to be zero, return 0 1226 if (N1C && MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits),TLI)) 1227 return DAG.getConstant(0, VT); 1228 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2) 1229 if (N1C && N0.getOpcode() == ISD::SHL && 1230 N0.getOperand(1).getOpcode() == ISD::Constant) { 1231 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1232 uint64_t c2 = N1C->getValue(); 1233 if (c1 + c2 > OpSizeInBits) 1234 return DAG.getConstant(0, VT); 1235 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0), 1236 DAG.getConstant(c1 + c2, N1.getValueType())); 1237 } 1238 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or 1239 // (srl (and x, -1 << c1), c1-c2) 1240 if (N1C && N0.getOpcode() == ISD::SRL && 1241 N0.getOperand(1).getOpcode() == ISD::Constant) { 1242 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1243 uint64_t c2 = N1C->getValue(); 1244 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0), 1245 DAG.getConstant(~0ULL << c1, VT)); 1246 if (c2 > c1) 1247 return DAG.getNode(ISD::SHL, VT, Mask, 1248 DAG.getConstant(c2-c1, N1.getValueType())); 1249 else 1250 return DAG.getNode(ISD::SRL, VT, Mask, 1251 DAG.getConstant(c1-c2, N1.getValueType())); 1252 } 1253 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1) 1254 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 1255 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 1256 DAG.getConstant(~0ULL << N1C->getValue(), VT)); 1257 return SDOperand(); 1258} 1259 1260SDOperand DAGCombiner::visitSRA(SDNode *N) { 1261 SDOperand N0 = N->getOperand(0); 1262 SDOperand N1 = N->getOperand(1); 1263 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1264 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1265 MVT::ValueType VT = N0.getValueType(); 1266 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1267 1268 // fold (sra c1, c2) -> c1>>c2 1269 if (N0C && N1C) 1270 return DAG.getConstant(N0C->getSignExtended() >> N1C->getValue(), VT); 1271 // fold (sra 0, x) -> 0 1272 if (N0C && N0C->isNullValue()) 1273 return N0; 1274 // fold (sra -1, x) -> -1 1275 if (N0C && N0C->isAllOnesValue()) 1276 return N0; 1277 // fold (sra x, c >= size(x)) -> undef 1278 if (N1C && N1C->getValue() >= OpSizeInBits) 1279 return DAG.getNode(ISD::UNDEF, VT); 1280 // fold (sra x, 0) -> x 1281 if (N1C && N1C->isNullValue()) 1282 return N0; 1283 // If the sign bit is known to be zero, switch this to a SRL. 1284 if (MaskedValueIsZero(N0, (1ULL << (OpSizeInBits-1)), TLI)) 1285 return DAG.getNode(ISD::SRL, VT, N0, N1); 1286 return SDOperand(); 1287} 1288 1289SDOperand DAGCombiner::visitSRL(SDNode *N) { 1290 SDOperand N0 = N->getOperand(0); 1291 SDOperand N1 = N->getOperand(1); 1292 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1293 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1294 MVT::ValueType VT = N0.getValueType(); 1295 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1296 1297 // fold (srl c1, c2) -> c1 >>u c2 1298 if (N0C && N1C) 1299 return DAG.getConstant(N0C->getValue() >> N1C->getValue(), VT); 1300 // fold (srl 0, x) -> 0 1301 if (N0C && N0C->isNullValue()) 1302 return N0; 1303 // fold (srl x, c >= size(x)) -> undef 1304 if (N1C && N1C->getValue() >= OpSizeInBits) 1305 return DAG.getNode(ISD::UNDEF, VT); 1306 // fold (srl x, 0) -> x 1307 if (N1C && N1C->isNullValue()) 1308 return N0; 1309 // if (srl x, c) is known to be zero, return 0 1310 if (N1C && MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits),TLI)) 1311 return DAG.getConstant(0, VT); 1312 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2) 1313 if (N1C && N0.getOpcode() == ISD::SRL && 1314 N0.getOperand(1).getOpcode() == ISD::Constant) { 1315 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1316 uint64_t c2 = N1C->getValue(); 1317 if (c1 + c2 > OpSizeInBits) 1318 return DAG.getConstant(0, VT); 1319 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 1320 DAG.getConstant(c1 + c2, N1.getValueType())); 1321 } 1322 return SDOperand(); 1323} 1324 1325SDOperand DAGCombiner::visitCTLZ(SDNode *N) { 1326 SDOperand N0 = N->getOperand(0); 1327 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1328 1329 // fold (ctlz c1) -> c2 1330 if (N0C) 1331 return DAG.getConstant(CountLeadingZeros_64(N0C->getValue()), 1332 N0.getValueType()); 1333 return SDOperand(); 1334} 1335 1336SDOperand DAGCombiner::visitCTTZ(SDNode *N) { 1337 SDOperand N0 = N->getOperand(0); 1338 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1339 1340 // fold (cttz c1) -> c2 1341 if (N0C) 1342 return DAG.getConstant(CountTrailingZeros_64(N0C->getValue()), 1343 N0.getValueType()); 1344 return SDOperand(); 1345} 1346 1347SDOperand DAGCombiner::visitCTPOP(SDNode *N) { 1348 SDOperand N0 = N->getOperand(0); 1349 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1350 1351 // fold (ctpop c1) -> c2 1352 if (N0C) 1353 return DAG.getConstant(CountPopulation_64(N0C->getValue()), 1354 N0.getValueType()); 1355 return SDOperand(); 1356} 1357 1358SDOperand DAGCombiner::visitSELECT(SDNode *N) { 1359 SDOperand N0 = N->getOperand(0); 1360 SDOperand N1 = N->getOperand(1); 1361 SDOperand N2 = N->getOperand(2); 1362 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1363 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1364 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 1365 MVT::ValueType VT = N->getValueType(0); 1366 1367 // fold select C, X, X -> X 1368 if (N1 == N2) 1369 return N1; 1370 // fold select true, X, Y -> X 1371 if (N0C && !N0C->isNullValue()) 1372 return N1; 1373 // fold select false, X, Y -> Y 1374 if (N0C && N0C->isNullValue()) 1375 return N2; 1376 // fold select C, 1, X -> C | X 1377 if (MVT::i1 == VT && N1C && N1C->getValue() == 1) 1378 return DAG.getNode(ISD::OR, VT, N0, N2); 1379 // fold select C, 0, X -> ~C & X 1380 // FIXME: this should check for C type == X type, not i1? 1381 if (MVT::i1 == VT && N1C && N1C->isNullValue()) { 1382 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 1383 WorkList.push_back(XORNode.Val); 1384 return DAG.getNode(ISD::AND, VT, XORNode, N2); 1385 } 1386 // fold select C, X, 1 -> ~C | X 1387 if (MVT::i1 == VT && N2C && N2C->getValue() == 1) { 1388 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 1389 WorkList.push_back(XORNode.Val); 1390 return DAG.getNode(ISD::OR, VT, XORNode, N1); 1391 } 1392 // fold select C, X, 0 -> C & X 1393 // FIXME: this should check for C type == X type, not i1? 1394 if (MVT::i1 == VT && N2C && N2C->isNullValue()) 1395 return DAG.getNode(ISD::AND, VT, N0, N1); 1396 // fold X ? X : Y --> X ? 1 : Y --> X | Y 1397 if (MVT::i1 == VT && N0 == N1) 1398 return DAG.getNode(ISD::OR, VT, N0, N2); 1399 // fold X ? Y : X --> X ? Y : 0 --> X & Y 1400 if (MVT::i1 == VT && N0 == N2) 1401 return DAG.getNode(ISD::AND, VT, N0, N1); 1402 1403 // If we can fold this based on the true/false value, do so. 1404 if (SimplifySelectOps(N, N1, N2)) 1405 return SDOperand(); 1406 1407 // fold selects based on a setcc into other things, such as min/max/abs 1408 if (N0.getOpcode() == ISD::SETCC) 1409 return SimplifySelect(N0, N1, N2); 1410 return SDOperand(); 1411} 1412 1413SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) { 1414 SDOperand N0 = N->getOperand(0); 1415 SDOperand N1 = N->getOperand(1); 1416 SDOperand N2 = N->getOperand(2); 1417 SDOperand N3 = N->getOperand(3); 1418 SDOperand N4 = N->getOperand(4); 1419 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1420 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1421 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 1422 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 1423 1424 // Determine if the condition we're dealing with is constant 1425 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 1426 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 1427 1428 // fold select_cc lhs, rhs, x, x, cc -> x 1429 if (N2 == N3) 1430 return N2; 1431 1432 // If we can fold this based on the true/false value, do so. 1433 if (SimplifySelectOps(N, N2, N3)) 1434 return SDOperand(); 1435 1436 // fold select_cc into other things, such as min/max/abs 1437 return SimplifySelectCC(N0, N1, N2, N3, CC); 1438} 1439 1440SDOperand DAGCombiner::visitSETCC(SDNode *N) { 1441 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 1442 cast<CondCodeSDNode>(N->getOperand(2))->get()); 1443} 1444 1445SDOperand DAGCombiner::visitADD_PARTS(SDNode *N) { 1446 SDOperand LHSLo = N->getOperand(0); 1447 SDOperand RHSLo = N->getOperand(2); 1448 MVT::ValueType VT = LHSLo.getValueType(); 1449 1450 // fold (a_Hi, 0) + (b_Hi, b_Lo) -> (b_Hi + a_Hi, b_Lo) 1451 if (MaskedValueIsZero(LHSLo, (1ULL << MVT::getSizeInBits(VT))-1, TLI)) { 1452 SDOperand Hi = DAG.getNode(ISD::ADD, VT, N->getOperand(1), 1453 N->getOperand(3)); 1454 WorkList.push_back(Hi.Val); 1455 CombineTo(N, RHSLo, Hi); 1456 return SDOperand(); 1457 } 1458 // fold (a_Hi, a_Lo) + (b_Hi, 0) -> (a_Hi + b_Hi, a_Lo) 1459 if (MaskedValueIsZero(RHSLo, (1ULL << MVT::getSizeInBits(VT))-1, TLI)) { 1460 SDOperand Hi = DAG.getNode(ISD::ADD, VT, N->getOperand(1), 1461 N->getOperand(3)); 1462 WorkList.push_back(Hi.Val); 1463 CombineTo(N, LHSLo, Hi); 1464 return SDOperand(); 1465 } 1466 return SDOperand(); 1467} 1468 1469SDOperand DAGCombiner::visitSUB_PARTS(SDNode *N) { 1470 SDOperand LHSLo = N->getOperand(0); 1471 SDOperand RHSLo = N->getOperand(2); 1472 MVT::ValueType VT = LHSLo.getValueType(); 1473 1474 // fold (a_Hi, a_Lo) - (b_Hi, 0) -> (a_Hi - b_Hi, a_Lo) 1475 if (MaskedValueIsZero(RHSLo, (1ULL << MVT::getSizeInBits(VT))-1, TLI)) { 1476 SDOperand Hi = DAG.getNode(ISD::SUB, VT, N->getOperand(1), 1477 N->getOperand(3)); 1478 WorkList.push_back(Hi.Val); 1479 CombineTo(N, LHSLo, Hi); 1480 return SDOperand(); 1481 } 1482 return SDOperand(); 1483} 1484 1485SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 1486 SDOperand N0 = N->getOperand(0); 1487 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1488 MVT::ValueType VT = N->getValueType(0); 1489 1490 // fold (sext c1) -> c1 1491 if (N0C) 1492 return DAG.getConstant(N0C->getSignExtended(), VT); 1493 // fold (sext (sext x)) -> (sext x) 1494 if (N0.getOpcode() == ISD::SIGN_EXTEND) 1495 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0)); 1496 // fold (sext (sextload x)) -> (sextload x) 1497 if (N0.getOpcode() == ISD::SEXTLOAD && VT == N0.getValueType()) 1498 return N0; 1499 // fold (sext (load x)) -> (sextload x) 1500 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) { 1501 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), 1502 N0.getOperand(1), N0.getOperand(2), 1503 N0.getValueType()); 1504 WorkList.push_back(N); 1505 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 1506 ExtLoad.getValue(1)); 1507 return SDOperand(); 1508 } 1509 return SDOperand(); 1510} 1511 1512SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) { 1513 SDOperand N0 = N->getOperand(0); 1514 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1515 MVT::ValueType VT = N->getValueType(0); 1516 1517 // fold (zext c1) -> c1 1518 if (N0C) 1519 return DAG.getConstant(N0C->getValue(), VT); 1520 // fold (zext (zext x)) -> (zext x) 1521 if (N0.getOpcode() == ISD::ZERO_EXTEND) 1522 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0)); 1523 return SDOperand(); 1524} 1525 1526SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 1527 SDOperand N0 = N->getOperand(0); 1528 SDOperand N1 = N->getOperand(1); 1529 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1530 MVT::ValueType VT = N->getValueType(0); 1531 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT(); 1532 unsigned EVTBits = MVT::getSizeInBits(EVT); 1533 1534 // fold (sext_in_reg c1) -> c1 1535 if (N0C) { 1536 SDOperand Truncate = DAG.getConstant(N0C->getValue(), EVT); 1537 return DAG.getNode(ISD::SIGN_EXTEND, VT, Truncate); 1538 } 1539 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt1 1540 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1541 cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) { 1542 return N0; 1543 } 1544 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 1545 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1546 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) { 1547 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); 1548 } 1549 // fold (sext_in_reg (assert_sext x)) -> (assert_sext x) 1550 if (N0.getOpcode() == ISD::AssertSext && 1551 cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) { 1552 return N0; 1553 } 1554 // fold (sext_in_reg (sextload x)) -> (sextload x) 1555 if (N0.getOpcode() == ISD::SEXTLOAD && 1556 cast<VTSDNode>(N0.getOperand(3))->getVT() <= EVT) { 1557 return N0; 1558 } 1559 // fold (sext_in_reg (setcc x)) -> setcc x iff (setcc x) == 0 or -1 1560 if (N0.getOpcode() == ISD::SETCC && 1561 TLI.getSetCCResultContents() == 1562 TargetLowering::ZeroOrNegativeOneSetCCResult) 1563 return N0; 1564 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero 1565 if (MaskedValueIsZero(N0, 1ULL << (EVTBits-1), TLI)) 1566 return DAG.getNode(ISD::AND, N0.getValueType(), N0, 1567 DAG.getConstant(~0ULL >> (64-EVTBits), VT)); 1568 // fold (sext_in_reg (srl x)) -> sra x 1569 if (N0.getOpcode() == ISD::SRL && 1570 N0.getOperand(1).getOpcode() == ISD::Constant && 1571 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == EVTBits) { 1572 return DAG.getNode(ISD::SRA, N0.getValueType(), N0.getOperand(0), 1573 N0.getOperand(1)); 1574 } 1575 // fold (sext_inreg (extload x)) -> (sextload x) 1576 if (N0.getOpcode() == ISD::EXTLOAD && 1577 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() && 1578 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) { 1579 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), 1580 N0.getOperand(1), N0.getOperand(2), 1581 EVT); 1582 WorkList.push_back(N); 1583 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1584 return SDOperand(); 1585 } 1586 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 1587 if (N0.getOpcode() == ISD::ZEXTLOAD && N0.hasOneUse() && 1588 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() && 1589 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) { 1590 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), 1591 N0.getOperand(1), N0.getOperand(2), 1592 EVT); 1593 WorkList.push_back(N); 1594 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1595 return SDOperand(); 1596 } 1597 return SDOperand(); 1598} 1599 1600SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) { 1601 SDOperand N0 = N->getOperand(0); 1602 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1603 MVT::ValueType VT = N->getValueType(0); 1604 1605 // noop truncate 1606 if (N0.getValueType() == N->getValueType(0)) 1607 return N0; 1608 // fold (truncate c1) -> c1 1609 if (N0C) 1610 return DAG.getConstant(N0C->getValue(), VT); 1611 // fold (truncate (truncate x)) -> (truncate x) 1612 if (N0.getOpcode() == ISD::TRUNCATE) 1613 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 1614 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 1615 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND){ 1616 if (N0.getValueType() < VT) 1617 // if the source is smaller than the dest, we still need an extend 1618 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 1619 else if (N0.getValueType() > VT) 1620 // if the source is larger than the dest, than we just need the truncate 1621 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 1622 else 1623 // if the source and dest are the same type, we can drop both the extend 1624 // and the truncate 1625 return N0.getOperand(0); 1626 } 1627 // fold (truncate (load x)) -> (smaller load x) 1628 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) { 1629 assert(MVT::getSizeInBits(N0.getValueType()) > MVT::getSizeInBits(VT) && 1630 "Cannot truncate to larger type!"); 1631 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 1632 // For big endian targets, we need to add an offset to the pointer to load 1633 // the correct bytes. For little endian systems, we merely need to read 1634 // fewer bytes from the same pointer. 1635 uint64_t PtrOff = 1636 (MVT::getSizeInBits(N0.getValueType()) - MVT::getSizeInBits(VT)) / 8; 1637 SDOperand NewPtr = TLI.isLittleEndian() ? N0.getOperand(1) : 1638 DAG.getNode(ISD::ADD, PtrType, N0.getOperand(1), 1639 DAG.getConstant(PtrOff, PtrType)); 1640 WorkList.push_back(NewPtr.Val); 1641 SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), NewPtr,N0.getOperand(2)); 1642 WorkList.push_back(N); 1643 CombineTo(N0.Val, Load, Load.getValue(1)); 1644 return SDOperand(); 1645 } 1646 return SDOperand(); 1647} 1648 1649SDOperand DAGCombiner::visitFADD(SDNode *N) { 1650 SDOperand N0 = N->getOperand(0); 1651 SDOperand N1 = N->getOperand(1); 1652 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1653 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 1654 MVT::ValueType VT = N->getValueType(0); 1655 1656 // fold (fadd c1, c2) -> c1+c2 1657 if (N0CFP && N1CFP) 1658 return DAG.getConstantFP(N0CFP->getValue() + N1CFP->getValue(), VT); 1659 // canonicalize constant to RHS 1660 if (N0CFP && !N1CFP) 1661 return DAG.getNode(ISD::FADD, VT, N1, N0); 1662 // fold (A + (-B)) -> A-B 1663 if (N1.getOpcode() == ISD::FNEG) 1664 return DAG.getNode(ISD::FSUB, VT, N0, N1.getOperand(0)); 1665 // fold ((-A) + B) -> B-A 1666 if (N0.getOpcode() == ISD::FNEG) 1667 return DAG.getNode(ISD::FSUB, VT, N1, N0.getOperand(0)); 1668 return SDOperand(); 1669} 1670 1671SDOperand DAGCombiner::visitFSUB(SDNode *N) { 1672 SDOperand N0 = N->getOperand(0); 1673 SDOperand N1 = N->getOperand(1); 1674 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1675 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 1676 MVT::ValueType VT = N->getValueType(0); 1677 1678 // fold (fsub c1, c2) -> c1-c2 1679 if (N0CFP && N1CFP) 1680 return DAG.getConstantFP(N0CFP->getValue() - N1CFP->getValue(), VT); 1681 // fold (A-(-B)) -> A+B 1682 if (N1.getOpcode() == ISD::FNEG) 1683 return DAG.getNode(ISD::FADD, N0.getValueType(), N0, N1.getOperand(0)); 1684 return SDOperand(); 1685} 1686 1687SDOperand DAGCombiner::visitFMUL(SDNode *N) { 1688 SDOperand N0 = N->getOperand(0); 1689 SDOperand N1 = N->getOperand(1); 1690 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1691 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 1692 MVT::ValueType VT = N->getValueType(0); 1693 1694 // fold (fmul c1, c2) -> c1*c2 1695 if (N0CFP && N1CFP) 1696 return DAG.getConstantFP(N0CFP->getValue() * N1CFP->getValue(), VT); 1697 // canonicalize constant to RHS 1698 if (N0CFP && !N1CFP) 1699 return DAG.getNode(ISD::FMUL, VT, N1, N0); 1700 // fold (fmul X, 2.0) -> (fadd X, X) 1701 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 1702 return DAG.getNode(ISD::FADD, VT, N0, N0); 1703 return SDOperand(); 1704} 1705 1706SDOperand DAGCombiner::visitFDIV(SDNode *N) { 1707 SDOperand N0 = N->getOperand(0); 1708 SDOperand N1 = N->getOperand(1); 1709 MVT::ValueType VT = N->getValueType(0); 1710 1711 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0)) 1712 if (ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1)) { 1713 // fold floating point (fdiv c1, c2) 1714 return DAG.getConstantFP(N0CFP->getValue() / N1CFP->getValue(), VT); 1715 } 1716 return SDOperand(); 1717} 1718 1719SDOperand DAGCombiner::visitFREM(SDNode *N) { 1720 SDOperand N0 = N->getOperand(0); 1721 SDOperand N1 = N->getOperand(1); 1722 MVT::ValueType VT = N->getValueType(0); 1723 1724 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0)) 1725 if (ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1)) { 1726 // fold floating point (frem c1, c2) -> fmod(c1, c2) 1727 return DAG.getConstantFP(fmod(N0CFP->getValue(),N1CFP->getValue()), VT); 1728 } 1729 return SDOperand(); 1730} 1731 1732 1733SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) { 1734 SDOperand N0 = N->getOperand(0); 1735 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1736 1737 // fold (sint_to_fp c1) -> c1fp 1738 if (N0C) 1739 return DAG.getConstantFP(N0C->getSignExtended(), N->getValueType(0)); 1740 return SDOperand(); 1741} 1742 1743SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) { 1744 SDOperand N0 = N->getOperand(0); 1745 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1746 1747 // fold (uint_to_fp c1) -> c1fp 1748 if (N0C) 1749 return DAG.getConstantFP(N0C->getValue(), N->getValueType(0)); 1750 return SDOperand(); 1751} 1752 1753SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) { 1754 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)); 1755 1756 // fold (fp_to_sint c1fp) -> c1 1757 if (N0CFP) 1758 return DAG.getConstant((int64_t)N0CFP->getValue(), N->getValueType(0)); 1759 return SDOperand(); 1760} 1761 1762SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) { 1763 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)); 1764 1765 // fold (fp_to_uint c1fp) -> c1 1766 if (N0CFP) 1767 return DAG.getConstant((uint64_t)N0CFP->getValue(), N->getValueType(0)); 1768 return SDOperand(); 1769} 1770 1771SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) { 1772 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)); 1773 1774 // fold (fp_round c1fp) -> c1fp 1775 if (N0CFP) 1776 return DAG.getConstantFP(N0CFP->getValue(), N->getValueType(0)); 1777 return SDOperand(); 1778} 1779 1780SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 1781 SDOperand N0 = N->getOperand(0); 1782 MVT::ValueType VT = N->getValueType(0); 1783 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 1784 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1785 1786 // fold (fp_round_inreg c1fp) -> c1fp 1787 if (N0CFP) { 1788 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT); 1789 return DAG.getNode(ISD::FP_EXTEND, VT, Round); 1790 } 1791 return SDOperand(); 1792} 1793 1794SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) { 1795 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)); 1796 1797 // fold (fp_extend c1fp) -> c1fp 1798 if (N0CFP) 1799 return DAG.getConstantFP(N0CFP->getValue(), N->getValueType(0)); 1800 return SDOperand(); 1801} 1802 1803SDOperand DAGCombiner::visitFNEG(SDNode *N) { 1804 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)); 1805 // fold (neg c1) -> -c1 1806 if (N0CFP) 1807 return DAG.getConstantFP(-N0CFP->getValue(), N->getValueType(0)); 1808 // fold (neg (sub x, y)) -> (sub y, x) 1809 if (N->getOperand(0).getOpcode() == ISD::SUB) 1810 return DAG.getNode(ISD::SUB, N->getValueType(0), N->getOperand(1), 1811 N->getOperand(0)); 1812 // fold (neg (neg x)) -> x 1813 if (N->getOperand(0).getOpcode() == ISD::FNEG) 1814 return N->getOperand(0).getOperand(0); 1815 return SDOperand(); 1816} 1817 1818SDOperand DAGCombiner::visitFABS(SDNode *N) { 1819 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)); 1820 // fold (fabs c1) -> fabs(c1) 1821 if (N0CFP) 1822 return DAG.getConstantFP(fabs(N0CFP->getValue()), N->getValueType(0)); 1823 // fold (fabs (fabs x)) -> (fabs x) 1824 if (N->getOperand(0).getOpcode() == ISD::FABS) 1825 return N->getOperand(0); 1826 // fold (fabs (fneg x)) -> (fabs x) 1827 if (N->getOperand(0).getOpcode() == ISD::FNEG) 1828 return DAG.getNode(ISD::FABS, N->getValueType(0), 1829 N->getOperand(0).getOperand(0)); 1830 return SDOperand(); 1831} 1832 1833SDOperand DAGCombiner::visitBRCOND(SDNode *N) { 1834 SDOperand Chain = N->getOperand(0); 1835 SDOperand N1 = N->getOperand(1); 1836 SDOperand N2 = N->getOperand(2); 1837 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1838 1839 // never taken branch, fold to chain 1840 if (N1C && N1C->isNullValue()) 1841 return Chain; 1842 // unconditional branch 1843 if (N1C && N1C->getValue() == 1) 1844 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 1845 return SDOperand(); 1846} 1847 1848SDOperand DAGCombiner::visitBRCONDTWOWAY(SDNode *N) { 1849 SDOperand Chain = N->getOperand(0); 1850 SDOperand N1 = N->getOperand(1); 1851 SDOperand N2 = N->getOperand(2); 1852 SDOperand N3 = N->getOperand(3); 1853 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1854 1855 // unconditional branch to true mbb 1856 if (N1C && N1C->getValue() == 1) 1857 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 1858 // unconditional branch to false mbb 1859 if (N1C && N1C->isNullValue()) 1860 return DAG.getNode(ISD::BR, MVT::Other, Chain, N3); 1861 return SDOperand(); 1862} 1863 1864// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 1865// 1866SDOperand DAGCombiner::visitBR_CC(SDNode *N) { 1867 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 1868 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 1869 1870 // Use SimplifySetCC to simplify SETCC's. 1871 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false); 1872 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val); 1873 1874 // fold br_cc true, dest -> br dest (unconditional branch) 1875 if (SCCC && SCCC->getValue()) 1876 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0), 1877 N->getOperand(4)); 1878 // fold br_cc false, dest -> unconditional fall through 1879 if (SCCC && SCCC->isNullValue()) 1880 return N->getOperand(0); 1881 // fold to a simpler setcc 1882 if (Simp.Val && Simp.getOpcode() == ISD::SETCC) 1883 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0), 1884 Simp.getOperand(2), Simp.getOperand(0), 1885 Simp.getOperand(1), N->getOperand(4)); 1886 return SDOperand(); 1887} 1888 1889SDOperand DAGCombiner::visitBRTWOWAY_CC(SDNode *N) { 1890 SDOperand Chain = N->getOperand(0); 1891 SDOperand CCN = N->getOperand(1); 1892 SDOperand LHS = N->getOperand(2); 1893 SDOperand RHS = N->getOperand(3); 1894 SDOperand N4 = N->getOperand(4); 1895 SDOperand N5 = N->getOperand(5); 1896 1897 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), LHS, RHS, 1898 cast<CondCodeSDNode>(CCN)->get(), false); 1899 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 1900 1901 // fold select_cc lhs, rhs, x, x, cc -> x 1902 if (N4 == N5) 1903 return DAG.getNode(ISD::BR, MVT::Other, Chain, N4); 1904 // fold select_cc true, x, y -> x 1905 if (SCCC && SCCC->getValue()) 1906 return DAG.getNode(ISD::BR, MVT::Other, Chain, N4); 1907 // fold select_cc false, x, y -> y 1908 if (SCCC && SCCC->isNullValue()) 1909 return DAG.getNode(ISD::BR, MVT::Other, Chain, N5); 1910 // fold to a simpler setcc 1911 if (SCC.Val && SCC.getOpcode() == ISD::SETCC) 1912 return DAG.getBR2Way_CC(Chain, SCC.getOperand(2), SCC.getOperand(0), 1913 SCC.getOperand(1), N4, N5); 1914 return SDOperand(); 1915} 1916 1917SDOperand DAGCombiner::visitLOAD(SDNode *N) { 1918 SDOperand Chain = N->getOperand(0); 1919 SDOperand Ptr = N->getOperand(1); 1920 SDOperand SrcValue = N->getOperand(2); 1921 1922 // If this load is directly stored, replace the load value with the stored 1923 // value. 1924 // TODO: Handle store large -> read small portion. 1925 // TODO: Handle TRUNCSTORE/EXTLOAD 1926 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr && 1927 Chain.getOperand(1).getValueType() == N->getValueType(0)) 1928 return CombineTo(N, Chain.getOperand(1), Chain); 1929 1930 return SDOperand(); 1931} 1932 1933SDOperand DAGCombiner::visitSTORE(SDNode *N) { 1934 SDOperand Chain = N->getOperand(0); 1935 SDOperand Value = N->getOperand(1); 1936 SDOperand Ptr = N->getOperand(2); 1937 SDOperand SrcValue = N->getOperand(3); 1938 1939 // If this is a store that kills a previous store, remove the previous store. 1940 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr && 1941 Chain.Val->hasOneUse() /* Avoid introducing DAG cycles */) { 1942 // Create a new store of Value that replaces both stores. 1943 SDNode *PrevStore = Chain.Val; 1944 if (PrevStore->getOperand(1) == Value) // Same value multiply stored. 1945 return Chain; 1946 SDOperand NewStore = DAG.getNode(ISD::STORE, MVT::Other, 1947 PrevStore->getOperand(0), Value, Ptr, 1948 SrcValue); 1949 CombineTo(N, NewStore); // Nuke this store. 1950 CombineTo(PrevStore, NewStore); // Nuke the previous store. 1951 return SDOperand(N, 0); 1952 } 1953 1954 return SDOperand(); 1955} 1956 1957SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){ 1958 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 1959 1960 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2, 1961 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 1962 // If we got a simplified select_cc node back from SimplifySelectCC, then 1963 // break it down into a new SETCC node, and a new SELECT node, and then return 1964 // the SELECT node, since we were called with a SELECT node. 1965 if (SCC.Val) { 1966 // Check to see if we got a select_cc back (to turn into setcc/select). 1967 // Otherwise, just return whatever node we got back, like fabs. 1968 if (SCC.getOpcode() == ISD::SELECT_CC) { 1969 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(), 1970 SCC.getOperand(0), SCC.getOperand(1), 1971 SCC.getOperand(4)); 1972 WorkList.push_back(SETCC.Val); 1973 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2), 1974 SCC.getOperand(3), SETCC); 1975 } 1976 return SCC; 1977 } 1978 return SDOperand(); 1979} 1980 1981/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 1982/// are the two values being selected between, see if we can simplify the 1983/// select. 1984/// 1985bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS, 1986 SDOperand RHS) { 1987 1988 // If this is a select from two identical things, try to pull the operation 1989 // through the select. 1990 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 1991#if 0 1992 std::cerr << "SELECT: ["; LHS.Val->dump(); 1993 std::cerr << "] ["; RHS.Val->dump(); 1994 std::cerr << "]\n"; 1995#endif 1996 1997 // If this is a load and the token chain is identical, replace the select 1998 // of two loads with a load through a select of the address to load from. 1999 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 2000 // constants have been dropped into the constant pool. 2001 if ((LHS.getOpcode() == ISD::LOAD || 2002 LHS.getOpcode() == ISD::EXTLOAD || 2003 LHS.getOpcode() == ISD::ZEXTLOAD || 2004 LHS.getOpcode() == ISD::SEXTLOAD) && 2005 // Token chains must be identical. 2006 LHS.getOperand(0) == RHS.getOperand(0) && 2007 // If this is an EXTLOAD, the VT's must match. 2008 (LHS.getOpcode() == ISD::LOAD || 2009 LHS.getOperand(3) == RHS.getOperand(3))) { 2010 // FIXME: this conflates two src values, discarding one. This is not 2011 // the right thing to do, but nothing uses srcvalues now. When they do, 2012 // turn SrcValue into a list of locations. 2013 SDOperand Addr; 2014 if (TheSelect->getOpcode() == ISD::SELECT) 2015 Addr = DAG.getNode(ISD::SELECT, LHS.getOperand(1).getValueType(), 2016 TheSelect->getOperand(0), LHS.getOperand(1), 2017 RHS.getOperand(1)); 2018 else 2019 Addr = DAG.getNode(ISD::SELECT_CC, LHS.getOperand(1).getValueType(), 2020 TheSelect->getOperand(0), 2021 TheSelect->getOperand(1), 2022 LHS.getOperand(1), RHS.getOperand(1), 2023 TheSelect->getOperand(4)); 2024 2025 SDOperand Load; 2026 if (LHS.getOpcode() == ISD::LOAD) 2027 Load = DAG.getLoad(TheSelect->getValueType(0), LHS.getOperand(0), 2028 Addr, LHS.getOperand(2)); 2029 else 2030 Load = DAG.getExtLoad(LHS.getOpcode(), TheSelect->getValueType(0), 2031 LHS.getOperand(0), Addr, LHS.getOperand(2), 2032 cast<VTSDNode>(LHS.getOperand(3))->getVT()); 2033 // Users of the select now use the result of the load. 2034 CombineTo(TheSelect, Load); 2035 2036 // Users of the old loads now use the new load's chain. We know the 2037 // old-load value is dead now. 2038 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1)); 2039 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1)); 2040 return true; 2041 } 2042 } 2043 2044 return false; 2045} 2046 2047SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1, 2048 SDOperand N2, SDOperand N3, 2049 ISD::CondCode CC) { 2050 2051 MVT::ValueType VT = N2.getValueType(); 2052 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 2053 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 2054 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 2055 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 2056 2057 // Determine if the condition we're dealing with is constant 2058 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 2059 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 2060 2061 // fold select_cc true, x, y -> x 2062 if (SCCC && SCCC->getValue()) 2063 return N2; 2064 // fold select_cc false, x, y -> y 2065 if (SCCC && SCCC->getValue() == 0) 2066 return N3; 2067 2068 // Check to see if we can simplify the select into an fabs node 2069 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 2070 // Allow either -0.0 or 0.0 2071 if (CFP->getValue() == 0.0) { 2072 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 2073 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 2074 N0 == N2 && N3.getOpcode() == ISD::FNEG && 2075 N2 == N3.getOperand(0)) 2076 return DAG.getNode(ISD::FABS, VT, N0); 2077 2078 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 2079 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 2080 N0 == N3 && N2.getOpcode() == ISD::FNEG && 2081 N2.getOperand(0) == N3) 2082 return DAG.getNode(ISD::FABS, VT, N3); 2083 } 2084 } 2085 2086 // Check to see if we can perform the "gzip trick", transforming 2087 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 2088 if (N1C && N1C->isNullValue() && N3C && N3C->isNullValue() && 2089 MVT::isInteger(N0.getValueType()) && 2090 MVT::isInteger(N2.getValueType()) && CC == ISD::SETLT) { 2091 MVT::ValueType XType = N0.getValueType(); 2092 MVT::ValueType AType = N2.getValueType(); 2093 if (XType >= AType) { 2094 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 2095 // single-bit constant. 2096 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) { 2097 unsigned ShCtV = Log2_64(N2C->getValue()); 2098 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1; 2099 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy()); 2100 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt); 2101 WorkList.push_back(Shift.Val); 2102 if (XType > AType) { 2103 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 2104 WorkList.push_back(Shift.Val); 2105 } 2106 return DAG.getNode(ISD::AND, AType, Shift, N2); 2107 } 2108 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 2109 DAG.getConstant(MVT::getSizeInBits(XType)-1, 2110 TLI.getShiftAmountTy())); 2111 WorkList.push_back(Shift.Val); 2112 if (XType > AType) { 2113 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 2114 WorkList.push_back(Shift.Val); 2115 } 2116 return DAG.getNode(ISD::AND, AType, Shift, N2); 2117 } 2118 } 2119 2120 // fold select C, 16, 0 -> shl C, 4 2121 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) && 2122 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) { 2123 // Get a SetCC of the condition 2124 // FIXME: Should probably make sure that setcc is legal if we ever have a 2125 // target where it isn't. 2126 SDOperand Temp, SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 2127 WorkList.push_back(SCC.Val); 2128 // cast from setcc result type to select result type 2129 if (AfterLegalize) 2130 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType()); 2131 else 2132 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 2133 WorkList.push_back(Temp.Val); 2134 // shl setcc result by log2 n2c 2135 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp, 2136 DAG.getConstant(Log2_64(N2C->getValue()), 2137 TLI.getShiftAmountTy())); 2138 } 2139 2140 // Check to see if this is the equivalent of setcc 2141 // FIXME: Turn all of these into setcc if setcc if setcc is legal 2142 // otherwise, go ahead with the folds. 2143 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) { 2144 MVT::ValueType XType = N0.getValueType(); 2145 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) { 2146 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 2147 if (Res.getValueType() != VT) 2148 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res); 2149 return Res; 2150 } 2151 2152 // seteq X, 0 -> srl (ctlz X, log2(size(X))) 2153 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 2154 TLI.isOperationLegal(ISD::CTLZ, XType)) { 2155 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0); 2156 return DAG.getNode(ISD::SRL, XType, Ctlz, 2157 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)), 2158 TLI.getShiftAmountTy())); 2159 } 2160 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) 2161 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 2162 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType), 2163 N0); 2164 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0, 2165 DAG.getConstant(~0ULL, XType)); 2166 return DAG.getNode(ISD::SRL, XType, 2167 DAG.getNode(ISD::AND, XType, NegN0, NotN0), 2168 DAG.getConstant(MVT::getSizeInBits(XType)-1, 2169 TLI.getShiftAmountTy())); 2170 } 2171 // setgt X, -1 -> xor (srl (X, size(X)-1), 1) 2172 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 2173 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0, 2174 DAG.getConstant(MVT::getSizeInBits(XType)-1, 2175 TLI.getShiftAmountTy())); 2176 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType)); 2177 } 2178 } 2179 2180 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 2181 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 2182 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 2183 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) { 2184 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0))) { 2185 MVT::ValueType XType = N0.getValueType(); 2186 if (SubC->isNullValue() && MVT::isInteger(XType)) { 2187 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 2188 DAG.getConstant(MVT::getSizeInBits(XType)-1, 2189 TLI.getShiftAmountTy())); 2190 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 2191 WorkList.push_back(Shift.Val); 2192 WorkList.push_back(Add.Val); 2193 return DAG.getNode(ISD::XOR, XType, Add, Shift); 2194 } 2195 } 2196 } 2197 2198 return SDOperand(); 2199} 2200 2201SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0, 2202 SDOperand N1, ISD::CondCode Cond, 2203 bool foldBooleans) { 2204 // These setcc operations always fold. 2205 switch (Cond) { 2206 default: break; 2207 case ISD::SETFALSE: 2208 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 2209 case ISD::SETTRUE: 2210 case ISD::SETTRUE2: return DAG.getConstant(1, VT); 2211 } 2212 2213 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) { 2214 uint64_t C1 = N1C->getValue(); 2215 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val)) { 2216 uint64_t C0 = N0C->getValue(); 2217 2218 // Sign extend the operands if required 2219 if (ISD::isSignedIntSetCC(Cond)) { 2220 C0 = N0C->getSignExtended(); 2221 C1 = N1C->getSignExtended(); 2222 } 2223 2224 switch (Cond) { 2225 default: assert(0 && "Unknown integer setcc!"); 2226 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT); 2227 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT); 2228 case ISD::SETULT: return DAG.getConstant(C0 < C1, VT); 2229 case ISD::SETUGT: return DAG.getConstant(C0 > C1, VT); 2230 case ISD::SETULE: return DAG.getConstant(C0 <= C1, VT); 2231 case ISD::SETUGE: return DAG.getConstant(C0 >= C1, VT); 2232 case ISD::SETLT: return DAG.getConstant((int64_t)C0 < (int64_t)C1, VT); 2233 case ISD::SETGT: return DAG.getConstant((int64_t)C0 > (int64_t)C1, VT); 2234 case ISD::SETLE: return DAG.getConstant((int64_t)C0 <= (int64_t)C1, VT); 2235 case ISD::SETGE: return DAG.getConstant((int64_t)C0 >= (int64_t)C1, VT); 2236 } 2237 } else { 2238 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 2239 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 2240 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType()); 2241 2242 // If the comparison constant has bits in the upper part, the 2243 // zero-extended value could never match. 2244 if (C1 & (~0ULL << InSize)) { 2245 unsigned VSize = MVT::getSizeInBits(N0.getValueType()); 2246 switch (Cond) { 2247 case ISD::SETUGT: 2248 case ISD::SETUGE: 2249 case ISD::SETEQ: return DAG.getConstant(0, VT); 2250 case ISD::SETULT: 2251 case ISD::SETULE: 2252 case ISD::SETNE: return DAG.getConstant(1, VT); 2253 case ISD::SETGT: 2254 case ISD::SETGE: 2255 // True if the sign bit of C1 is set. 2256 return DAG.getConstant((C1 & (1ULL << VSize)) != 0, VT); 2257 case ISD::SETLT: 2258 case ISD::SETLE: 2259 // True if the sign bit of C1 isn't set. 2260 return DAG.getConstant((C1 & (1ULL << VSize)) == 0, VT); 2261 default: 2262 break; 2263 } 2264 } 2265 2266 // Otherwise, we can perform the comparison with the low bits. 2267 switch (Cond) { 2268 case ISD::SETEQ: 2269 case ISD::SETNE: 2270 case ISD::SETUGT: 2271 case ISD::SETUGE: 2272 case ISD::SETULT: 2273 case ISD::SETULE: 2274 return DAG.getSetCC(VT, N0.getOperand(0), 2275 DAG.getConstant(C1, N0.getOperand(0).getValueType()), 2276 Cond); 2277 default: 2278 break; // todo, be more careful with signed comparisons 2279 } 2280 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 2281 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 2282 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 2283 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy); 2284 MVT::ValueType ExtDstTy = N0.getValueType(); 2285 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy); 2286 2287 // If the extended part has any inconsistent bits, it cannot ever 2288 // compare equal. In other words, they have to be all ones or all 2289 // zeros. 2290 uint64_t ExtBits = 2291 (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1)); 2292 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits) 2293 return DAG.getConstant(Cond == ISD::SETNE, VT); 2294 2295 SDOperand ZextOp; 2296 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType(); 2297 if (Op0Ty == ExtSrcTy) { 2298 ZextOp = N0.getOperand(0); 2299 } else { 2300 int64_t Imm = ~0ULL >> (64-ExtSrcTyBits); 2301 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0), 2302 DAG.getConstant(Imm, Op0Ty)); 2303 } 2304 WorkList.push_back(ZextOp.Val); 2305 // Otherwise, make this a use of a zext. 2306 return DAG.getSetCC(VT, ZextOp, 2307 DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)), 2308 ExtDstTy), 2309 Cond); 2310 } 2311 2312 uint64_t MinVal, MaxVal; 2313 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0)); 2314 if (ISD::isSignedIntSetCC(Cond)) { 2315 MinVal = 1ULL << (OperandBitSize-1); 2316 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined. 2317 MaxVal = ~0ULL >> (65-OperandBitSize); 2318 else 2319 MaxVal = 0; 2320 } else { 2321 MinVal = 0; 2322 MaxVal = ~0ULL >> (64-OperandBitSize); 2323 } 2324 2325 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 2326 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 2327 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 2328 --C1; // X >= C0 --> X > (C0-1) 2329 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()), 2330 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 2331 } 2332 2333 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 2334 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 2335 ++C1; // X <= C0 --> X < (C0+1) 2336 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()), 2337 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 2338 } 2339 2340 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 2341 return DAG.getConstant(0, VT); // X < MIN --> false 2342 2343 // Canonicalize setgt X, Min --> setne X, Min 2344 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 2345 return DAG.getSetCC(VT, N0, N1, ISD::SETNE); 2346 2347 // If we have setult X, 1, turn it into seteq X, 0 2348 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 2349 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()), 2350 ISD::SETEQ); 2351 // If we have setugt X, Max-1, turn it into seteq X, Max 2352 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 2353 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()), 2354 ISD::SETEQ); 2355 2356 // If we have "setcc X, C0", check to see if we can shrink the immediate 2357 // by changing cc. 2358 2359 // SETUGT X, SINTMAX -> SETLT X, 0 2360 if (Cond == ISD::SETUGT && OperandBitSize != 1 && 2361 C1 == (~0ULL >> (65-OperandBitSize))) 2362 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()), 2363 ISD::SETLT); 2364 2365 // FIXME: Implement the rest of these. 2366 2367 // Fold bit comparisons when we can. 2368 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2369 VT == N0.getValueType() && N0.getOpcode() == ISD::AND) 2370 if (ConstantSDNode *AndRHS = 2371 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2372 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 2373 // Perform the xform if the AND RHS is a single bit. 2374 if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) { 2375 return DAG.getNode(ISD::SRL, VT, N0, 2376 DAG.getConstant(Log2_64(AndRHS->getValue()), 2377 TLI.getShiftAmountTy())); 2378 } 2379 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) { 2380 // (X & 8) == 8 --> (X & 8) >> 3 2381 // Perform the xform if C1 is a single bit. 2382 if ((C1 & (C1-1)) == 0) { 2383 return DAG.getNode(ISD::SRL, VT, N0, 2384 DAG.getConstant(Log2_64(C1),TLI.getShiftAmountTy())); 2385 } 2386 } 2387 } 2388 } 2389 } else if (isa<ConstantSDNode>(N0.Val)) { 2390 // Ensure that the constant occurs on the RHS. 2391 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 2392 } 2393 2394 if (ConstantFPSDNode *N0C = dyn_cast<ConstantFPSDNode>(N0.Val)) 2395 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) { 2396 double C0 = N0C->getValue(), C1 = N1C->getValue(); 2397 2398 switch (Cond) { 2399 default: break; // FIXME: Implement the rest of these! 2400 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT); 2401 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT); 2402 case ISD::SETLT: return DAG.getConstant(C0 < C1, VT); 2403 case ISD::SETGT: return DAG.getConstant(C0 > C1, VT); 2404 case ISD::SETLE: return DAG.getConstant(C0 <= C1, VT); 2405 case ISD::SETGE: return DAG.getConstant(C0 >= C1, VT); 2406 } 2407 } else { 2408 // Ensure that the constant occurs on the RHS. 2409 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 2410 } 2411 2412 if (N0 == N1) { 2413 // We can always fold X == Y for integer setcc's. 2414 if (MVT::isInteger(N0.getValueType())) 2415 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2416 unsigned UOF = ISD::getUnorderedFlavor(Cond); 2417 if (UOF == 2) // FP operators that are undefined on NaNs. 2418 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2419 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 2420 return DAG.getConstant(UOF, VT); 2421 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 2422 // if it is not already. 2423 ISD::CondCode NewCond = UOF == 0 ? ISD::SETUO : ISD::SETO; 2424 if (NewCond != Cond) 2425 return DAG.getSetCC(VT, N0, N1, NewCond); 2426 } 2427 2428 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2429 MVT::isInteger(N0.getValueType())) { 2430 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 2431 N0.getOpcode() == ISD::XOR) { 2432 // Simplify (X+Y) == (X+Z) --> Y == Z 2433 if (N0.getOpcode() == N1.getOpcode()) { 2434 if (N0.getOperand(0) == N1.getOperand(0)) 2435 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond); 2436 if (N0.getOperand(1) == N1.getOperand(1)) 2437 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond); 2438 if (isCommutativeBinOp(N0.getOpcode())) { 2439 // If X op Y == Y op X, try other combinations. 2440 if (N0.getOperand(0) == N1.getOperand(1)) 2441 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond); 2442 if (N0.getOperand(1) == N1.getOperand(0)) 2443 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond); 2444 } 2445 } 2446 2447 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. Common for condcodes. 2448 if (N0.getOpcode() == ISD::XOR) 2449 if (ConstantSDNode *XORC = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 2450 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 2451 // If we know that all of the inverted bits are zero, don't bother 2452 // performing the inversion. 2453 if (MaskedValueIsZero(N0.getOperand(0), ~XORC->getValue(), TLI)) 2454 return DAG.getSetCC(VT, N0.getOperand(0), 2455 DAG.getConstant(XORC->getValue()^RHSC->getValue(), 2456 N0.getValueType()), Cond); 2457 } 2458 2459 // Simplify (X+Z) == X --> Z == 0 2460 if (N0.getOperand(0) == N1) 2461 return DAG.getSetCC(VT, N0.getOperand(1), 2462 DAG.getConstant(0, N0.getValueType()), Cond); 2463 if (N0.getOperand(1) == N1) { 2464 if (isCommutativeBinOp(N0.getOpcode())) 2465 return DAG.getSetCC(VT, N0.getOperand(0), 2466 DAG.getConstant(0, N0.getValueType()), Cond); 2467 else { 2468 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 2469 // (Z-X) == X --> Z == X<<1 2470 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), 2471 N1, 2472 DAG.getConstant(1,TLI.getShiftAmountTy())); 2473 WorkList.push_back(SH.Val); 2474 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond); 2475 } 2476 } 2477 } 2478 2479 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 2480 N1.getOpcode() == ISD::XOR) { 2481 // Simplify X == (X+Z) --> Z == 0 2482 if (N1.getOperand(0) == N0) { 2483 return DAG.getSetCC(VT, N1.getOperand(1), 2484 DAG.getConstant(0, N1.getValueType()), Cond); 2485 } else if (N1.getOperand(1) == N0) { 2486 if (isCommutativeBinOp(N1.getOpcode())) { 2487 return DAG.getSetCC(VT, N1.getOperand(0), 2488 DAG.getConstant(0, N1.getValueType()), Cond); 2489 } else { 2490 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 2491 // X == (Z-X) --> X<<1 == Z 2492 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0, 2493 DAG.getConstant(1,TLI.getShiftAmountTy())); 2494 WorkList.push_back(SH.Val); 2495 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond); 2496 } 2497 } 2498 } 2499 } 2500 2501 // Fold away ALL boolean setcc's. 2502 SDOperand Temp; 2503 if (N0.getValueType() == MVT::i1 && foldBooleans) { 2504 switch (Cond) { 2505 default: assert(0 && "Unknown integer setcc!"); 2506 case ISD::SETEQ: // X == Y -> (X^Y)^1 2507 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 2508 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1)); 2509 WorkList.push_back(Temp.Val); 2510 break; 2511 case ISD::SETNE: // X != Y --> (X^Y) 2512 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 2513 break; 2514 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y 2515 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y 2516 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 2517 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp); 2518 WorkList.push_back(Temp.Val); 2519 break; 2520 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X 2521 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X 2522 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 2523 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp); 2524 WorkList.push_back(Temp.Val); 2525 break; 2526 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y 2527 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y 2528 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 2529 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp); 2530 WorkList.push_back(Temp.Val); 2531 break; 2532 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X 2533 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X 2534 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 2535 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp); 2536 break; 2537 } 2538 if (VT != MVT::i1) { 2539 WorkList.push_back(N0.Val); 2540 // FIXME: If running after legalize, we probably can't do this. 2541 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 2542 } 2543 return N0; 2544 } 2545 2546 // Could not fold it. 2547 return SDOperand(); 2548} 2549 2550/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 2551/// return a DAG expression to select that will generate the same value by 2552/// multiplying by a magic number. See: 2553/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2554SDOperand DAGCombiner::BuildSDIV(SDNode *N) { 2555 MVT::ValueType VT = N->getValueType(0); 2556 assert((VT == MVT::i32 || VT == MVT::i64) && 2557 "BuildSDIV only operates on i32 or i64!"); 2558 2559 int64_t d = cast<ConstantSDNode>(N->getOperand(1))->getSignExtended(); 2560 ms magics = (VT == MVT::i32) ? magic32(d) : magic64(d); 2561 2562 // Multiply the numerator (operand 0) by the magic value 2563 SDOperand Q = DAG.getNode(ISD::MULHS, VT, N->getOperand(0), 2564 DAG.getConstant(magics.m, VT)); 2565 // If d > 0 and m < 0, add the numerator 2566 if (d > 0 && magics.m < 0) { 2567 Q = DAG.getNode(ISD::ADD, VT, Q, N->getOperand(0)); 2568 WorkList.push_back(Q.Val); 2569 } 2570 // If d < 0 and m > 0, subtract the numerator. 2571 if (d < 0 && magics.m > 0) { 2572 Q = DAG.getNode(ISD::SUB, VT, Q, N->getOperand(0)); 2573 WorkList.push_back(Q.Val); 2574 } 2575 // Shift right algebraic if shift value is nonzero 2576 if (magics.s > 0) { 2577 Q = DAG.getNode(ISD::SRA, VT, Q, 2578 DAG.getConstant(magics.s, TLI.getShiftAmountTy())); 2579 WorkList.push_back(Q.Val); 2580 } 2581 // Extract the sign bit and add it to the quotient 2582 SDOperand T = 2583 DAG.getNode(ISD::SRL, MVT::i32, Q, 2584 DAG.getConstant(MVT::getSizeInBits(VT)-1, 2585 TLI.getShiftAmountTy())); 2586 WorkList.push_back(T.Val); 2587 return DAG.getNode(ISD::ADD, VT, Q, T); 2588} 2589 2590/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 2591/// return a DAG expression to select that will generate the same value by 2592/// multiplying by a magic number. See: 2593/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2594SDOperand DAGCombiner::BuildUDIV(SDNode *N) { 2595 MVT::ValueType VT = N->getValueType(0); 2596 assert((VT == MVT::i32 || VT == MVT::i64) && 2597 "BuildUDIV only operates on i32 or i64!"); 2598 2599 uint64_t d = cast<ConstantSDNode>(N->getOperand(1))->getValue(); 2600 mu magics = (VT == MVT::i32) ? magicu32(d) : magicu64(d); 2601 2602 // Multiply the numerator (operand 0) by the magic value 2603 SDOperand Q = DAG.getNode(ISD::MULHU, VT, N->getOperand(0), 2604 DAG.getConstant(magics.m, VT)); 2605 WorkList.push_back(Q.Val); 2606 2607 if (magics.a == 0) { 2608 return DAG.getNode(ISD::SRL, VT, Q, 2609 DAG.getConstant(magics.s, TLI.getShiftAmountTy())); 2610 } else { 2611 SDOperand NPQ = DAG.getNode(ISD::SUB, VT, N->getOperand(0), Q); 2612 WorkList.push_back(NPQ.Val); 2613 NPQ = DAG.getNode(ISD::SRL, VT, NPQ, 2614 DAG.getConstant(1, TLI.getShiftAmountTy())); 2615 WorkList.push_back(NPQ.Val); 2616 NPQ = DAG.getNode(ISD::ADD, VT, NPQ, Q); 2617 WorkList.push_back(NPQ.Val); 2618 return DAG.getNode(ISD::SRL, VT, NPQ, 2619 DAG.getConstant(magics.s-1, TLI.getShiftAmountTy())); 2620 } 2621} 2622 2623// SelectionDAG::Combine - This is the entry point for the file. 2624// 2625void SelectionDAG::Combine(bool RunningAfterLegalize) { 2626 /// run - This is the main entry point to this class. 2627 /// 2628 DAGCombiner(*this).Run(RunningAfterLegalize); 2629} 2630