DAGCombiner.cpp revision ca0e80fc6b927e48363387a8f721883141f8b2b3
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "dagcombine" 16#include "llvm/CodeGen/SelectionDAG.h" 17#include "llvm/CodeGen/MachineFunction.h" 18#include "llvm/CodeGen/MachineFrameInfo.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Target/TargetData.h" 21#include "llvm/Target/TargetFrameInfo.h" 22#include "llvm/Target/TargetLowering.h" 23#include "llvm/Target/TargetMachine.h" 24#include "llvm/Target/TargetOptions.h" 25#include "llvm/ADT/SmallPtrSet.h" 26#include "llvm/ADT/Statistic.h" 27#include "llvm/Support/Compiler.h" 28#include "llvm/Support/CommandLine.h" 29#include "llvm/Support/Debug.h" 30#include "llvm/Support/MathExtras.h" 31#include <algorithm> 32using namespace llvm; 33 34STATISTIC(NodesCombined , "Number of dag nodes combined"); 35STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 36STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 37 38namespace { 39#ifndef NDEBUG 40 static cl::opt<bool> 41 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 42 cl::desc("Pop up a window to show dags before the first " 43 "dag combine pass")); 44 static cl::opt<bool> 45 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 46 cl::desc("Pop up a window to show dags before the second " 47 "dag combine pass")); 48#else 49 static const bool ViewDAGCombine1 = false; 50 static const bool ViewDAGCombine2 = false; 51#endif 52 53 static cl::opt<bool> 54 CombinerAA("combiner-alias-analysis", cl::Hidden, 55 cl::desc("Turn on alias analysis during testing")); 56 57 static cl::opt<bool> 58 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 59 cl::desc("Include global information in alias analysis")); 60 61//------------------------------ DAGCombiner ---------------------------------// 62 63 class VISIBILITY_HIDDEN DAGCombiner { 64 SelectionDAG &DAG; 65 TargetLowering &TLI; 66 bool AfterLegalize; 67 68 // Worklist of all of the nodes that need to be simplified. 69 std::vector<SDNode*> WorkList; 70 71 // AA - Used for DAG load/store alias analysis. 72 AliasAnalysis &AA; 73 74 /// AddUsersToWorkList - When an instruction is simplified, add all users of 75 /// the instruction to the work lists because they might get more simplified 76 /// now. 77 /// 78 void AddUsersToWorkList(SDNode *N) { 79 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 80 UI != UE; ++UI) 81 AddToWorkList(*UI); 82 } 83 84 /// visit - call the node-specific routine that knows how to fold each 85 /// particular type of node. 86 SDOperand visit(SDNode *N); 87 88 public: 89 /// AddToWorkList - Add to the work list making sure it's instance is at the 90 /// the back (next to be processed.) 91 void AddToWorkList(SDNode *N) { 92 removeFromWorkList(N); 93 WorkList.push_back(N); 94 } 95 96 /// removeFromWorkList - remove all instances of N from the worklist. 97 /// 98 void removeFromWorkList(SDNode *N) { 99 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 100 WorkList.end()); 101 } 102 103 SDOperand CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo, 104 bool AddTo = true); 105 106 SDOperand CombineTo(SDNode *N, SDOperand Res, bool AddTo = true) { 107 return CombineTo(N, &Res, 1, AddTo); 108 } 109 110 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1, 111 bool AddTo = true) { 112 SDOperand To[] = { Res0, Res1 }; 113 return CombineTo(N, To, 2, AddTo); 114 } 115 116 private: 117 118 /// SimplifyDemandedBits - Check the specified integer node value to see if 119 /// it can be simplified or if things it uses can be simplified by bit 120 /// propagation. If so, return true. 121 bool SimplifyDemandedBits(SDOperand Op) { 122 APInt Demanded = APInt::getAllOnesValue(Op.getValueSizeInBits()); 123 return SimplifyDemandedBits(Op, Demanded); 124 } 125 126 bool SimplifyDemandedBits(SDOperand Op, const APInt &Demanded); 127 128 bool CombineToPreIndexedLoadStore(SDNode *N); 129 bool CombineToPostIndexedLoadStore(SDNode *N); 130 131 132 /// combine - call the node-specific routine that knows how to fold each 133 /// particular type of node. If that doesn't do anything, try the 134 /// target-specific DAG combines. 135 SDOperand combine(SDNode *N); 136 137 // Visitation implementation - Implement dag node combining for different 138 // node types. The semantics are as follows: 139 // Return Value: 140 // SDOperand.Val == 0 - No change was made 141 // SDOperand.Val == N - N was replaced, is dead, and is already handled. 142 // otherwise - N should be replaced by the returned Operand. 143 // 144 SDOperand visitTokenFactor(SDNode *N); 145 SDOperand visitMERGE_VALUES(SDNode *N); 146 SDOperand visitADD(SDNode *N); 147 SDOperand visitSUB(SDNode *N); 148 SDOperand visitADDC(SDNode *N); 149 SDOperand visitADDE(SDNode *N); 150 SDOperand visitMUL(SDNode *N); 151 SDOperand visitSDIV(SDNode *N); 152 SDOperand visitUDIV(SDNode *N); 153 SDOperand visitSREM(SDNode *N); 154 SDOperand visitUREM(SDNode *N); 155 SDOperand visitMULHU(SDNode *N); 156 SDOperand visitMULHS(SDNode *N); 157 SDOperand visitSMUL_LOHI(SDNode *N); 158 SDOperand visitUMUL_LOHI(SDNode *N); 159 SDOperand visitSDIVREM(SDNode *N); 160 SDOperand visitUDIVREM(SDNode *N); 161 SDOperand visitAND(SDNode *N); 162 SDOperand visitOR(SDNode *N); 163 SDOperand visitXOR(SDNode *N); 164 SDOperand SimplifyVBinOp(SDNode *N); 165 SDOperand visitSHL(SDNode *N); 166 SDOperand visitSRA(SDNode *N); 167 SDOperand visitSRL(SDNode *N); 168 SDOperand visitCTLZ(SDNode *N); 169 SDOperand visitCTTZ(SDNode *N); 170 SDOperand visitCTPOP(SDNode *N); 171 SDOperand visitSELECT(SDNode *N); 172 SDOperand visitSELECT_CC(SDNode *N); 173 SDOperand visitSETCC(SDNode *N); 174 SDOperand visitSIGN_EXTEND(SDNode *N); 175 SDOperand visitZERO_EXTEND(SDNode *N); 176 SDOperand visitANY_EXTEND(SDNode *N); 177 SDOperand visitSIGN_EXTEND_INREG(SDNode *N); 178 SDOperand visitTRUNCATE(SDNode *N); 179 SDOperand visitBIT_CONVERT(SDNode *N); 180 SDOperand visitFADD(SDNode *N); 181 SDOperand visitFSUB(SDNode *N); 182 SDOperand visitFMUL(SDNode *N); 183 SDOperand visitFDIV(SDNode *N); 184 SDOperand visitFREM(SDNode *N); 185 SDOperand visitFCOPYSIGN(SDNode *N); 186 SDOperand visitSINT_TO_FP(SDNode *N); 187 SDOperand visitUINT_TO_FP(SDNode *N); 188 SDOperand visitFP_TO_SINT(SDNode *N); 189 SDOperand visitFP_TO_UINT(SDNode *N); 190 SDOperand visitFP_ROUND(SDNode *N); 191 SDOperand visitFP_ROUND_INREG(SDNode *N); 192 SDOperand visitFP_EXTEND(SDNode *N); 193 SDOperand visitFNEG(SDNode *N); 194 SDOperand visitFABS(SDNode *N); 195 SDOperand visitBRCOND(SDNode *N); 196 SDOperand visitBR_CC(SDNode *N); 197 SDOperand visitLOAD(SDNode *N); 198 SDOperand visitSTORE(SDNode *N); 199 SDOperand visitINSERT_VECTOR_ELT(SDNode *N); 200 SDOperand visitEXTRACT_VECTOR_ELT(SDNode *N); 201 SDOperand visitBUILD_VECTOR(SDNode *N); 202 SDOperand visitCONCAT_VECTORS(SDNode *N); 203 SDOperand visitVECTOR_SHUFFLE(SDNode *N); 204 205 SDOperand XformToShuffleWithZero(SDNode *N); 206 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS); 207 208 SDOperand visitShiftByConstant(SDNode *N, unsigned Amt); 209 210 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS); 211 SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N); 212 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2); 213 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2, 214 SDOperand N3, ISD::CondCode CC, 215 bool NotExtCompare = false); 216 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, 217 ISD::CondCode Cond, bool foldBooleans = true); 218 SDOperand SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 219 unsigned HiOp); 220 SDOperand ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT::ValueType); 221 SDOperand BuildSDIV(SDNode *N); 222 SDOperand BuildUDIV(SDNode *N); 223 SDNode *MatchRotate(SDOperand LHS, SDOperand RHS); 224 SDOperand ReduceLoadWidth(SDNode *N); 225 226 SDOperand GetDemandedBits(SDOperand V, const APInt &Mask); 227 228 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 229 /// looking for aliasing nodes and adding them to the Aliases vector. 230 void GatherAllAliases(SDNode *N, SDOperand OriginalChain, 231 SmallVector<SDOperand, 8> &Aliases); 232 233 /// isAlias - Return true if there is any possibility that the two addresses 234 /// overlap. 235 bool isAlias(SDOperand Ptr1, int64_t Size1, 236 const Value *SrcValue1, int SrcValueOffset1, 237 SDOperand Ptr2, int64_t Size2, 238 const Value *SrcValue2, int SrcValueOffset2); 239 240 /// FindAliasInfo - Extracts the relevant alias information from the memory 241 /// node. Returns true if the operand was a load. 242 bool FindAliasInfo(SDNode *N, 243 SDOperand &Ptr, int64_t &Size, 244 const Value *&SrcValue, int &SrcValueOffset); 245 246 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 247 /// looking for a better chain (aliasing node.) 248 SDOperand FindBetterChain(SDNode *N, SDOperand Chain); 249 250public: 251 DAGCombiner(SelectionDAG &D, AliasAnalysis &A) 252 : DAG(D), 253 TLI(D.getTargetLoweringInfo()), 254 AfterLegalize(false), 255 AA(A) {} 256 257 /// Run - runs the dag combiner on all nodes in the work list 258 void Run(bool RunningAfterLegalize); 259 }; 260} 261 262 263namespace { 264/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 265/// nodes from the worklist. 266class VISIBILITY_HIDDEN WorkListRemover : 267 public SelectionDAG::DAGUpdateListener { 268 DAGCombiner &DC; 269public: 270 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {} 271 272 virtual void NodeDeleted(SDNode *N) { 273 DC.removeFromWorkList(N); 274 } 275 276 virtual void NodeUpdated(SDNode *N) { 277 // Ignore updates. 278 } 279}; 280} 281 282//===----------------------------------------------------------------------===// 283// TargetLowering::DAGCombinerInfo implementation 284//===----------------------------------------------------------------------===// 285 286void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 287 ((DAGCombiner*)DC)->AddToWorkList(N); 288} 289 290SDOperand TargetLowering::DAGCombinerInfo:: 291CombineTo(SDNode *N, const std::vector<SDOperand> &To) { 292 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size()); 293} 294 295SDOperand TargetLowering::DAGCombinerInfo:: 296CombineTo(SDNode *N, SDOperand Res) { 297 return ((DAGCombiner*)DC)->CombineTo(N, Res); 298} 299 300 301SDOperand TargetLowering::DAGCombinerInfo:: 302CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) { 303 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1); 304} 305 306 307//===----------------------------------------------------------------------===// 308// Helper Functions 309//===----------------------------------------------------------------------===// 310 311/// isNegatibleForFree - Return 1 if we can compute the negated form of the 312/// specified expression for the same cost as the expression itself, or 2 if we 313/// can compute the negated form more cheaply than the expression itself. 314static char isNegatibleForFree(SDOperand Op, bool AfterLegalize, 315 unsigned Depth = 0) { 316 // No compile time optimizations on this type. 317 if (Op.getValueType() == MVT::ppcf128) 318 return 0; 319 320 // fneg is removable even if it has multiple uses. 321 if (Op.getOpcode() == ISD::FNEG) return 2; 322 323 // Don't allow anything with multiple uses. 324 if (!Op.hasOneUse()) return 0; 325 326 // Don't recurse exponentially. 327 if (Depth > 6) return 0; 328 329 switch (Op.getOpcode()) { 330 default: return false; 331 case ISD::ConstantFP: 332 // Don't invert constant FP values after legalize. The negated constant 333 // isn't necessarily legal. 334 return AfterLegalize ? 0 : 1; 335 case ISD::FADD: 336 // FIXME: determine better conditions for this xform. 337 if (!UnsafeFPMath) return 0; 338 339 // -(A+B) -> -A - B 340 if (char V = isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1)) 341 return V; 342 // -(A+B) -> -B - A 343 return isNegatibleForFree(Op.getOperand(1), AfterLegalize, Depth+1); 344 case ISD::FSUB: 345 // We can't turn -(A-B) into B-A when we honor signed zeros. 346 if (!UnsafeFPMath) return 0; 347 348 // -(A-B) -> B-A 349 return 1; 350 351 case ISD::FMUL: 352 case ISD::FDIV: 353 if (HonorSignDependentRoundingFPMath()) return 0; 354 355 // -(X*Y) -> (-X * Y) or (X*-Y) 356 if (char V = isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1)) 357 return V; 358 359 return isNegatibleForFree(Op.getOperand(1), AfterLegalize, Depth+1); 360 361 case ISD::FP_EXTEND: 362 case ISD::FP_ROUND: 363 case ISD::FSIN: 364 return isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1); 365 } 366} 367 368/// GetNegatedExpression - If isNegatibleForFree returns true, this function 369/// returns the newly negated expression. 370static SDOperand GetNegatedExpression(SDOperand Op, SelectionDAG &DAG, 371 bool AfterLegalize, unsigned Depth = 0) { 372 // fneg is removable even if it has multiple uses. 373 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 374 375 // Don't allow anything with multiple uses. 376 assert(Op.hasOneUse() && "Unknown reuse!"); 377 378 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 379 switch (Op.getOpcode()) { 380 default: assert(0 && "Unknown code"); 381 case ISD::ConstantFP: { 382 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 383 V.changeSign(); 384 return DAG.getConstantFP(V, Op.getValueType()); 385 } 386 case ISD::FADD: 387 // FIXME: determine better conditions for this xform. 388 assert(UnsafeFPMath); 389 390 // -(A+B) -> -A - B 391 if (isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1)) 392 return DAG.getNode(ISD::FSUB, Op.getValueType(), 393 GetNegatedExpression(Op.getOperand(0), DAG, 394 AfterLegalize, Depth+1), 395 Op.getOperand(1)); 396 // -(A+B) -> -B - A 397 return DAG.getNode(ISD::FSUB, Op.getValueType(), 398 GetNegatedExpression(Op.getOperand(1), DAG, 399 AfterLegalize, Depth+1), 400 Op.getOperand(0)); 401 case ISD::FSUB: 402 // We can't turn -(A-B) into B-A when we honor signed zeros. 403 assert(UnsafeFPMath); 404 405 // -(0-B) -> B 406 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 407 if (N0CFP->getValueAPF().isZero()) 408 return Op.getOperand(1); 409 410 // -(A-B) -> B-A 411 return DAG.getNode(ISD::FSUB, Op.getValueType(), Op.getOperand(1), 412 Op.getOperand(0)); 413 414 case ISD::FMUL: 415 case ISD::FDIV: 416 assert(!HonorSignDependentRoundingFPMath()); 417 418 // -(X*Y) -> -X * Y 419 if (isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1)) 420 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 421 GetNegatedExpression(Op.getOperand(0), DAG, 422 AfterLegalize, Depth+1), 423 Op.getOperand(1)); 424 425 // -(X*Y) -> X * -Y 426 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 427 Op.getOperand(0), 428 GetNegatedExpression(Op.getOperand(1), DAG, 429 AfterLegalize, Depth+1)); 430 431 case ISD::FP_EXTEND: 432 case ISD::FSIN: 433 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 434 GetNegatedExpression(Op.getOperand(0), DAG, 435 AfterLegalize, Depth+1)); 436 case ISD::FP_ROUND: 437 return DAG.getNode(ISD::FP_ROUND, Op.getValueType(), 438 GetNegatedExpression(Op.getOperand(0), DAG, 439 AfterLegalize, Depth+1), 440 Op.getOperand(1)); 441 } 442} 443 444 445// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 446// that selects between the values 1 and 0, making it equivalent to a setcc. 447// Also, set the incoming LHS, RHS, and CC references to the appropriate 448// nodes based on the type of node we are checking. This simplifies life a 449// bit for the callers. 450static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS, 451 SDOperand &CC) { 452 if (N.getOpcode() == ISD::SETCC) { 453 LHS = N.getOperand(0); 454 RHS = N.getOperand(1); 455 CC = N.getOperand(2); 456 return true; 457 } 458 if (N.getOpcode() == ISD::SELECT_CC && 459 N.getOperand(2).getOpcode() == ISD::Constant && 460 N.getOperand(3).getOpcode() == ISD::Constant && 461 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 462 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 463 LHS = N.getOperand(0); 464 RHS = N.getOperand(1); 465 CC = N.getOperand(4); 466 return true; 467 } 468 return false; 469} 470 471// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 472// one use. If this is true, it allows the users to invert the operation for 473// free when it is profitable to do so. 474static bool isOneUseSetCC(SDOperand N) { 475 SDOperand N0, N1, N2; 476 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse()) 477 return true; 478 return false; 479} 480 481SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){ 482 MVT::ValueType VT = N0.getValueType(); 483 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 484 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 485 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 486 if (isa<ConstantSDNode>(N1)) { 487 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1); 488 AddToWorkList(OpNode.Val); 489 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0)); 490 } else if (N0.hasOneUse()) { 491 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1); 492 AddToWorkList(OpNode.Val); 493 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1)); 494 } 495 } 496 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 497 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 498 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 499 if (isa<ConstantSDNode>(N0)) { 500 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0); 501 AddToWorkList(OpNode.Val); 502 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0)); 503 } else if (N1.hasOneUse()) { 504 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0); 505 AddToWorkList(OpNode.Val); 506 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1)); 507 } 508 } 509 return SDOperand(); 510} 511 512SDOperand DAGCombiner::CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo, 513 bool AddTo) { 514 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 515 ++NodesCombined; 516 DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG)); 517 DOUT << "\nWith: "; DEBUG(To[0].Val->dump(&DAG)); 518 DOUT << " and " << NumTo-1 << " other values\n"; 519 WorkListRemover DeadNodes(*this); 520 DAG.ReplaceAllUsesWith(N, To, &DeadNodes); 521 522 if (AddTo) { 523 // Push the new nodes and any users onto the worklist 524 for (unsigned i = 0, e = NumTo; i != e; ++i) { 525 AddToWorkList(To[i].Val); 526 AddUsersToWorkList(To[i].Val); 527 } 528 } 529 530 // Nodes can be reintroduced into the worklist. Make sure we do not 531 // process a node that has been replaced. 532 removeFromWorkList(N); 533 534 // Finally, since the node is now dead, remove it from the graph. 535 DAG.DeleteNode(N); 536 return SDOperand(N, 0); 537} 538 539/// SimplifyDemandedBits - Check the specified integer node value to see if 540/// it can be simplified or if things it uses can be simplified by bit 541/// propagation. If so, return true. 542bool DAGCombiner::SimplifyDemandedBits(SDOperand Op, const APInt &Demanded) { 543 TargetLowering::TargetLoweringOpt TLO(DAG, AfterLegalize); 544 APInt KnownZero, KnownOne; 545 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 546 return false; 547 548 // Revisit the node. 549 AddToWorkList(Op.Val); 550 551 // Replace the old value with the new one. 552 ++NodesCombined; 553 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.Val->dump(&DAG)); 554 DOUT << "\nWith: "; DEBUG(TLO.New.Val->dump(&DAG)); 555 DOUT << '\n'; 556 557 // Replace all uses. If any nodes become isomorphic to other nodes and 558 // are deleted, make sure to remove them from our worklist. 559 WorkListRemover DeadNodes(*this); 560 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 561 562 // Push the new node and any (possibly new) users onto the worklist. 563 AddToWorkList(TLO.New.Val); 564 AddUsersToWorkList(TLO.New.Val); 565 566 // Finally, if the node is now dead, remove it from the graph. The node 567 // may not be dead if the replacement process recursively simplified to 568 // something else needing this node. 569 if (TLO.Old.Val->use_empty()) { 570 removeFromWorkList(TLO.Old.Val); 571 572 // If the operands of this node are only used by the node, they will now 573 // be dead. Make sure to visit them first to delete dead nodes early. 574 for (unsigned i = 0, e = TLO.Old.Val->getNumOperands(); i != e; ++i) 575 if (TLO.Old.Val->getOperand(i).Val->hasOneUse()) 576 AddToWorkList(TLO.Old.Val->getOperand(i).Val); 577 578 DAG.DeleteNode(TLO.Old.Val); 579 } 580 return true; 581} 582 583//===----------------------------------------------------------------------===// 584// Main DAG Combiner implementation 585//===----------------------------------------------------------------------===// 586 587void DAGCombiner::Run(bool RunningAfterLegalize) { 588 // set the instance variable, so that the various visit routines may use it. 589 AfterLegalize = RunningAfterLegalize; 590 591 // Add all the dag nodes to the worklist. 592 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 593 E = DAG.allnodes_end(); I != E; ++I) 594 WorkList.push_back(I); 595 596 // Create a dummy node (which is not added to allnodes), that adds a reference 597 // to the root node, preventing it from being deleted, and tracking any 598 // changes of the root. 599 HandleSDNode Dummy(DAG.getRoot()); 600 601 // The root of the dag may dangle to deleted nodes until the dag combiner is 602 // done. Set it to null to avoid confusion. 603 DAG.setRoot(SDOperand()); 604 605 // while the worklist isn't empty, inspect the node on the end of it and 606 // try and combine it. 607 while (!WorkList.empty()) { 608 SDNode *N = WorkList.back(); 609 WorkList.pop_back(); 610 611 // If N has no uses, it is dead. Make sure to revisit all N's operands once 612 // N is deleted from the DAG, since they too may now be dead or may have a 613 // reduced number of uses, allowing other xforms. 614 if (N->use_empty() && N != &Dummy) { 615 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 616 AddToWorkList(N->getOperand(i).Val); 617 618 DAG.DeleteNode(N); 619 continue; 620 } 621 622 SDOperand RV = combine(N); 623 624 if (RV.Val == 0) 625 continue; 626 627 ++NodesCombined; 628 629 // If we get back the same node we passed in, rather than a new node or 630 // zero, we know that the node must have defined multiple values and 631 // CombineTo was used. Since CombineTo takes care of the worklist 632 // mechanics for us, we have no work to do in this case. 633 if (RV.Val == N) 634 continue; 635 636 assert(N->getOpcode() != ISD::DELETED_NODE && 637 RV.Val->getOpcode() != ISD::DELETED_NODE && 638 "Node was deleted but visit returned new node!"); 639 640 DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG)); 641 DOUT << "\nWith: "; DEBUG(RV.Val->dump(&DAG)); 642 DOUT << '\n'; 643 WorkListRemover DeadNodes(*this); 644 if (N->getNumValues() == RV.Val->getNumValues()) 645 DAG.ReplaceAllUsesWith(N, RV.Val, &DeadNodes); 646 else { 647 assert(N->getValueType(0) == RV.getValueType() && 648 N->getNumValues() == 1 && "Type mismatch"); 649 SDOperand OpV = RV; 650 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes); 651 } 652 653 // Push the new node and any users onto the worklist 654 AddToWorkList(RV.Val); 655 AddUsersToWorkList(RV.Val); 656 657 // Add any uses of the old node to the worklist in case this node is the 658 // last one that uses them. They may become dead after this node is 659 // deleted. 660 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 661 AddToWorkList(N->getOperand(i).Val); 662 663 // Nodes can be reintroduced into the worklist. Make sure we do not 664 // process a node that has been replaced. 665 removeFromWorkList(N); 666 667 // Finally, since the node is now dead, remove it from the graph. 668 DAG.DeleteNode(N); 669 } 670 671 // If the root changed (e.g. it was a dead load, update the root). 672 DAG.setRoot(Dummy.getValue()); 673} 674 675SDOperand DAGCombiner::visit(SDNode *N) { 676 switch(N->getOpcode()) { 677 default: break; 678 case ISD::TokenFactor: return visitTokenFactor(N); 679 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 680 case ISD::ADD: return visitADD(N); 681 case ISD::SUB: return visitSUB(N); 682 case ISD::ADDC: return visitADDC(N); 683 case ISD::ADDE: return visitADDE(N); 684 case ISD::MUL: return visitMUL(N); 685 case ISD::SDIV: return visitSDIV(N); 686 case ISD::UDIV: return visitUDIV(N); 687 case ISD::SREM: return visitSREM(N); 688 case ISD::UREM: return visitUREM(N); 689 case ISD::MULHU: return visitMULHU(N); 690 case ISD::MULHS: return visitMULHS(N); 691 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 692 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 693 case ISD::SDIVREM: return visitSDIVREM(N); 694 case ISD::UDIVREM: return visitUDIVREM(N); 695 case ISD::AND: return visitAND(N); 696 case ISD::OR: return visitOR(N); 697 case ISD::XOR: return visitXOR(N); 698 case ISD::SHL: return visitSHL(N); 699 case ISD::SRA: return visitSRA(N); 700 case ISD::SRL: return visitSRL(N); 701 case ISD::CTLZ: return visitCTLZ(N); 702 case ISD::CTTZ: return visitCTTZ(N); 703 case ISD::CTPOP: return visitCTPOP(N); 704 case ISD::SELECT: return visitSELECT(N); 705 case ISD::SELECT_CC: return visitSELECT_CC(N); 706 case ISD::SETCC: return visitSETCC(N); 707 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 708 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 709 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 710 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 711 case ISD::TRUNCATE: return visitTRUNCATE(N); 712 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 713 case ISD::FADD: return visitFADD(N); 714 case ISD::FSUB: return visitFSUB(N); 715 case ISD::FMUL: return visitFMUL(N); 716 case ISD::FDIV: return visitFDIV(N); 717 case ISD::FREM: return visitFREM(N); 718 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 719 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 720 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 721 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 722 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 723 case ISD::FP_ROUND: return visitFP_ROUND(N); 724 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 725 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 726 case ISD::FNEG: return visitFNEG(N); 727 case ISD::FABS: return visitFABS(N); 728 case ISD::BRCOND: return visitBRCOND(N); 729 case ISD::BR_CC: return visitBR_CC(N); 730 case ISD::LOAD: return visitLOAD(N); 731 case ISD::STORE: return visitSTORE(N); 732 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 733 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 734 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 735 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 736 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 737 } 738 return SDOperand(); 739} 740 741SDOperand DAGCombiner::combine(SDNode *N) { 742 743 SDOperand RV = visit(N); 744 745 // If nothing happened, try a target-specific DAG combine. 746 if (RV.Val == 0) { 747 assert(N->getOpcode() != ISD::DELETED_NODE && 748 "Node was deleted but visit returned NULL!"); 749 750 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 751 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 752 753 // Expose the DAG combiner to the target combiner impls. 754 TargetLowering::DAGCombinerInfo 755 DagCombineInfo(DAG, !AfterLegalize, false, this); 756 757 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 758 } 759 } 760 761 return RV; 762} 763 764/// getInputChainForNode - Given a node, return its input chain if it has one, 765/// otherwise return a null sd operand. 766static SDOperand getInputChainForNode(SDNode *N) { 767 if (unsigned NumOps = N->getNumOperands()) { 768 if (N->getOperand(0).getValueType() == MVT::Other) 769 return N->getOperand(0); 770 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 771 return N->getOperand(NumOps-1); 772 for (unsigned i = 1; i < NumOps-1; ++i) 773 if (N->getOperand(i).getValueType() == MVT::Other) 774 return N->getOperand(i); 775 } 776 return SDOperand(0, 0); 777} 778 779SDOperand DAGCombiner::visitTokenFactor(SDNode *N) { 780 // If N has two operands, where one has an input chain equal to the other, 781 // the 'other' chain is redundant. 782 if (N->getNumOperands() == 2) { 783 if (getInputChainForNode(N->getOperand(0).Val) == N->getOperand(1)) 784 return N->getOperand(0); 785 if (getInputChainForNode(N->getOperand(1).Val) == N->getOperand(0)) 786 return N->getOperand(1); 787 } 788 789 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 790 SmallVector<SDOperand, 8> Ops; // Ops for replacing token factor. 791 SmallPtrSet<SDNode*, 16> SeenOps; 792 bool Changed = false; // If we should replace this token factor. 793 794 // Start out with this token factor. 795 TFs.push_back(N); 796 797 // Iterate through token factors. The TFs grows when new token factors are 798 // encountered. 799 for (unsigned i = 0; i < TFs.size(); ++i) { 800 SDNode *TF = TFs[i]; 801 802 // Check each of the operands. 803 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 804 SDOperand Op = TF->getOperand(i); 805 806 switch (Op.getOpcode()) { 807 case ISD::EntryToken: 808 // Entry tokens don't need to be added to the list. They are 809 // rededundant. 810 Changed = true; 811 break; 812 813 case ISD::TokenFactor: 814 if ((CombinerAA || Op.hasOneUse()) && 815 std::find(TFs.begin(), TFs.end(), Op.Val) == TFs.end()) { 816 // Queue up for processing. 817 TFs.push_back(Op.Val); 818 // Clean up in case the token factor is removed. 819 AddToWorkList(Op.Val); 820 Changed = true; 821 break; 822 } 823 // Fall thru 824 825 default: 826 // Only add if it isn't already in the list. 827 if (SeenOps.insert(Op.Val)) 828 Ops.push_back(Op); 829 else 830 Changed = true; 831 break; 832 } 833 } 834 } 835 836 SDOperand Result; 837 838 // If we've change things around then replace token factor. 839 if (Changed) { 840 if (Ops.empty()) { 841 // The entry token is the only possible outcome. 842 Result = DAG.getEntryNode(); 843 } else { 844 // New and improved token factor. 845 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size()); 846 } 847 848 // Don't add users to work list. 849 return CombineTo(N, Result, false); 850 } 851 852 return Result; 853} 854 855/// MERGE_VALUES can always be eliminated. 856SDOperand DAGCombiner::visitMERGE_VALUES(SDNode *N) { 857 WorkListRemover DeadNodes(*this); 858 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 859 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, i), N->getOperand(i), 860 &DeadNodes); 861 removeFromWorkList(N); 862 DAG.DeleteNode(N); 863 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 864} 865 866 867static 868SDOperand combineShlAddConstant(SDOperand N0, SDOperand N1, SelectionDAG &DAG) { 869 MVT::ValueType VT = N0.getValueType(); 870 SDOperand N00 = N0.getOperand(0); 871 SDOperand N01 = N0.getOperand(1); 872 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 873 if (N01C && N00.getOpcode() == ISD::ADD && N00.Val->hasOneUse() && 874 isa<ConstantSDNode>(N00.getOperand(1))) { 875 N0 = DAG.getNode(ISD::ADD, VT, 876 DAG.getNode(ISD::SHL, VT, N00.getOperand(0), N01), 877 DAG.getNode(ISD::SHL, VT, N00.getOperand(1), N01)); 878 return DAG.getNode(ISD::ADD, VT, N0, N1); 879 } 880 return SDOperand(); 881} 882 883static 884SDOperand combineSelectAndUse(SDNode *N, SDOperand Slct, SDOperand OtherOp, 885 SelectionDAG &DAG) { 886 MVT::ValueType VT = N->getValueType(0); 887 unsigned Opc = N->getOpcode(); 888 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC; 889 SDOperand LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1); 890 SDOperand RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2); 891 ISD::CondCode CC = ISD::SETCC_INVALID; 892 if (isSlctCC) 893 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get(); 894 else { 895 SDOperand CCOp = Slct.getOperand(0); 896 if (CCOp.getOpcode() == ISD::SETCC) 897 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get(); 898 } 899 900 bool DoXform = false; 901 bool InvCC = false; 902 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) && 903 "Bad input!"); 904 if (LHS.getOpcode() == ISD::Constant && 905 cast<ConstantSDNode>(LHS)->isNullValue()) 906 DoXform = true; 907 else if (CC != ISD::SETCC_INVALID && 908 RHS.getOpcode() == ISD::Constant && 909 cast<ConstantSDNode>(RHS)->isNullValue()) { 910 std::swap(LHS, RHS); 911 SDOperand Op0 = Slct.getOperand(0); 912 bool isInt = MVT::isInteger(isSlctCC ? Op0.getValueType() 913 : Op0.getOperand(0).getValueType()); 914 CC = ISD::getSetCCInverse(CC, isInt); 915 DoXform = true; 916 InvCC = true; 917 } 918 919 if (DoXform) { 920 SDOperand Result = DAG.getNode(Opc, VT, OtherOp, RHS); 921 if (isSlctCC) 922 return DAG.getSelectCC(OtherOp, Result, 923 Slct.getOperand(0), Slct.getOperand(1), CC); 924 SDOperand CCOp = Slct.getOperand(0); 925 if (InvCC) 926 CCOp = DAG.getSetCC(CCOp.getValueType(), CCOp.getOperand(0), 927 CCOp.getOperand(1), CC); 928 return DAG.getNode(ISD::SELECT, VT, CCOp, OtherOp, Result); 929 } 930 return SDOperand(); 931} 932 933SDOperand DAGCombiner::visitADD(SDNode *N) { 934 SDOperand N0 = N->getOperand(0); 935 SDOperand N1 = N->getOperand(1); 936 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 937 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 938 MVT::ValueType VT = N0.getValueType(); 939 940 // fold vector ops 941 if (MVT::isVector(VT)) { 942 SDOperand FoldedVOp = SimplifyVBinOp(N); 943 if (FoldedVOp.Val) return FoldedVOp; 944 } 945 946 // fold (add x, undef) -> undef 947 if (N0.getOpcode() == ISD::UNDEF) 948 return N0; 949 if (N1.getOpcode() == ISD::UNDEF) 950 return N1; 951 // fold (add c1, c2) -> c1+c2 952 if (N0C && N1C) 953 return DAG.getConstant(N0C->getAPIntValue() + N1C->getAPIntValue(), VT); 954 // canonicalize constant to RHS 955 if (N0C && !N1C) 956 return DAG.getNode(ISD::ADD, VT, N1, N0); 957 // fold (add x, 0) -> x 958 if (N1C && N1C->isNullValue()) 959 return N0; 960 // fold ((c1-A)+c2) -> (c1+c2)-A 961 if (N1C && N0.getOpcode() == ISD::SUB) 962 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 963 return DAG.getNode(ISD::SUB, VT, 964 DAG.getConstant(N1C->getAPIntValue()+ 965 N0C->getAPIntValue(), VT), 966 N0.getOperand(1)); 967 // reassociate add 968 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1); 969 if (RADD.Val != 0) 970 return RADD; 971 // fold ((0-A) + B) -> B-A 972 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 973 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 974 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1)); 975 // fold (A + (0-B)) -> A-B 976 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 977 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 978 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1)); 979 // fold (A+(B-A)) -> B 980 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 981 return N1.getOperand(0); 982 983 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0))) 984 return SDOperand(N, 0); 985 986 // fold (a+b) -> (a|b) iff a and b share no bits. 987 if (MVT::isInteger(VT) && !MVT::isVector(VT)) { 988 APInt LHSZero, LHSOne; 989 APInt RHSZero, RHSOne; 990 APInt Mask = APInt::getAllOnesValue(MVT::getSizeInBits(VT)); 991 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 992 if (LHSZero.getBoolValue()) { 993 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 994 995 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 996 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 997 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 998 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 999 return DAG.getNode(ISD::OR, VT, N0, N1); 1000 } 1001 } 1002 1003 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1004 if (N0.getOpcode() == ISD::SHL && N0.Val->hasOneUse()) { 1005 SDOperand Result = combineShlAddConstant(N0, N1, DAG); 1006 if (Result.Val) return Result; 1007 } 1008 if (N1.getOpcode() == ISD::SHL && N1.Val->hasOneUse()) { 1009 SDOperand Result = combineShlAddConstant(N1, N0, DAG); 1010 if (Result.Val) return Result; 1011 } 1012 1013 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c)) 1014 if (N0.getOpcode() == ISD::SELECT && N0.Val->hasOneUse()) { 1015 SDOperand Result = combineSelectAndUse(N, N0, N1, DAG); 1016 if (Result.Val) return Result; 1017 } 1018 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) { 1019 SDOperand Result = combineSelectAndUse(N, N1, N0, DAG); 1020 if (Result.Val) return Result; 1021 } 1022 1023 return SDOperand(); 1024} 1025 1026SDOperand DAGCombiner::visitADDC(SDNode *N) { 1027 SDOperand N0 = N->getOperand(0); 1028 SDOperand N1 = N->getOperand(1); 1029 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1030 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1031 MVT::ValueType VT = N0.getValueType(); 1032 1033 // If the flag result is dead, turn this into an ADD. 1034 if (N->hasNUsesOfValue(0, 1)) 1035 return CombineTo(N, DAG.getNode(ISD::ADD, VT, N1, N0), 1036 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 1037 1038 // canonicalize constant to RHS. 1039 if (N0C && !N1C) { 1040 SDOperand Ops[] = { N1, N0 }; 1041 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2); 1042 } 1043 1044 // fold (addc x, 0) -> x + no carry out 1045 if (N1C && N1C->isNullValue()) 1046 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 1047 1048 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1049 APInt LHSZero, LHSOne; 1050 APInt RHSZero, RHSOne; 1051 APInt Mask = APInt::getAllOnesValue(MVT::getSizeInBits(VT)); 1052 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1053 if (LHSZero.getBoolValue()) { 1054 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1055 1056 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1057 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1058 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1059 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1060 return CombineTo(N, DAG.getNode(ISD::OR, VT, N0, N1), 1061 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 1062 } 1063 1064 return SDOperand(); 1065} 1066 1067SDOperand DAGCombiner::visitADDE(SDNode *N) { 1068 SDOperand N0 = N->getOperand(0); 1069 SDOperand N1 = N->getOperand(1); 1070 SDOperand CarryIn = N->getOperand(2); 1071 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1072 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1073 //MVT::ValueType VT = N0.getValueType(); 1074 1075 // canonicalize constant to RHS 1076 if (N0C && !N1C) { 1077 SDOperand Ops[] = { N1, N0, CarryIn }; 1078 return DAG.getNode(ISD::ADDE, N->getVTList(), Ops, 3); 1079 } 1080 1081 // fold (adde x, y, false) -> (addc x, y) 1082 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) { 1083 SDOperand Ops[] = { N1, N0 }; 1084 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2); 1085 } 1086 1087 return SDOperand(); 1088} 1089 1090 1091 1092SDOperand DAGCombiner::visitSUB(SDNode *N) { 1093 SDOperand N0 = N->getOperand(0); 1094 SDOperand N1 = N->getOperand(1); 1095 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1096 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1097 MVT::ValueType VT = N0.getValueType(); 1098 1099 // fold vector ops 1100 if (MVT::isVector(VT)) { 1101 SDOperand FoldedVOp = SimplifyVBinOp(N); 1102 if (FoldedVOp.Val) return FoldedVOp; 1103 } 1104 1105 // fold (sub x, x) -> 0 1106 if (N0 == N1) 1107 return DAG.getConstant(0, N->getValueType(0)); 1108 // fold (sub c1, c2) -> c1-c2 1109 if (N0C && N1C) 1110 return DAG.getNode(ISD::SUB, VT, N0, N1); 1111 // fold (sub x, c) -> (add x, -c) 1112 if (N1C) 1113 return DAG.getNode(ISD::ADD, VT, N0, 1114 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1115 // fold (A+B)-A -> B 1116 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1117 return N0.getOperand(1); 1118 // fold (A+B)-B -> A 1119 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1120 return N0.getOperand(0); 1121 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c)) 1122 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) { 1123 SDOperand Result = combineSelectAndUse(N, N1, N0, DAG); 1124 if (Result.Val) return Result; 1125 } 1126 // If either operand of a sub is undef, the result is undef 1127 if (N0.getOpcode() == ISD::UNDEF) 1128 return N0; 1129 if (N1.getOpcode() == ISD::UNDEF) 1130 return N1; 1131 1132 return SDOperand(); 1133} 1134 1135SDOperand DAGCombiner::visitMUL(SDNode *N) { 1136 SDOperand N0 = N->getOperand(0); 1137 SDOperand N1 = N->getOperand(1); 1138 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1139 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1140 MVT::ValueType VT = N0.getValueType(); 1141 1142 // fold vector ops 1143 if (MVT::isVector(VT)) { 1144 SDOperand FoldedVOp = SimplifyVBinOp(N); 1145 if (FoldedVOp.Val) return FoldedVOp; 1146 } 1147 1148 // fold (mul x, undef) -> 0 1149 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1150 return DAG.getConstant(0, VT); 1151 // fold (mul c1, c2) -> c1*c2 1152 if (N0C && N1C) 1153 return DAG.getNode(ISD::MUL, VT, N0, N1); 1154 // canonicalize constant to RHS 1155 if (N0C && !N1C) 1156 return DAG.getNode(ISD::MUL, VT, N1, N0); 1157 // fold (mul x, 0) -> 0 1158 if (N1C && N1C->isNullValue()) 1159 return N1; 1160 // fold (mul x, -1) -> 0-x 1161 if (N1C && N1C->isAllOnesValue()) 1162 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 1163 // fold (mul x, (1 << c)) -> x << c 1164 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1165 return DAG.getNode(ISD::SHL, VT, N0, 1166 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1167 TLI.getShiftAmountTy())); 1168 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1169 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) { 1170 // FIXME: If the input is something that is easily negated (e.g. a 1171 // single-use add), we should put the negate there. 1172 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), 1173 DAG.getNode(ISD::SHL, VT, N0, 1174 DAG.getConstant(Log2_64(-N1C->getSignExtended()), 1175 TLI.getShiftAmountTy()))); 1176 } 1177 1178 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1179 if (N1C && N0.getOpcode() == ISD::SHL && 1180 isa<ConstantSDNode>(N0.getOperand(1))) { 1181 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1)); 1182 AddToWorkList(C3.Val); 1183 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3); 1184 } 1185 1186 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1187 // use. 1188 { 1189 SDOperand Sh(0,0), Y(0,0); 1190 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1191 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1192 N0.Val->hasOneUse()) { 1193 Sh = N0; Y = N1; 1194 } else if (N1.getOpcode() == ISD::SHL && 1195 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) { 1196 Sh = N1; Y = N0; 1197 } 1198 if (Sh.Val) { 1199 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y); 1200 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1)); 1201 } 1202 } 1203 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1204 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() && 1205 isa<ConstantSDNode>(N0.getOperand(1))) { 1206 return DAG.getNode(ISD::ADD, VT, 1207 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1), 1208 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1)); 1209 } 1210 1211 // reassociate mul 1212 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1); 1213 if (RMUL.Val != 0) 1214 return RMUL; 1215 1216 return SDOperand(); 1217} 1218 1219SDOperand DAGCombiner::visitSDIV(SDNode *N) { 1220 SDOperand N0 = N->getOperand(0); 1221 SDOperand N1 = N->getOperand(1); 1222 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1223 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1224 MVT::ValueType VT = N->getValueType(0); 1225 1226 // fold vector ops 1227 if (MVT::isVector(VT)) { 1228 SDOperand FoldedVOp = SimplifyVBinOp(N); 1229 if (FoldedVOp.Val) return FoldedVOp; 1230 } 1231 1232 // fold (sdiv c1, c2) -> c1/c2 1233 if (N0C && N1C && !N1C->isNullValue()) 1234 return DAG.getNode(ISD::SDIV, VT, N0, N1); 1235 // fold (sdiv X, 1) -> X 1236 if (N1C && N1C->getSignExtended() == 1LL) 1237 return N0; 1238 // fold (sdiv X, -1) -> 0-X 1239 if (N1C && N1C->isAllOnesValue()) 1240 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 1241 // If we know the sign bits of both operands are zero, strength reduce to a 1242 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1243 if (!MVT::isVector(VT)) { 1244 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1245 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1); 1246 } 1247 // fold (sdiv X, pow2) -> simple ops after legalize 1248 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() && 1249 (isPowerOf2_64(N1C->getSignExtended()) || 1250 isPowerOf2_64(-N1C->getSignExtended()))) { 1251 // If dividing by powers of two is cheap, then don't perform the following 1252 // fold. 1253 if (TLI.isPow2DivCheap()) 1254 return SDOperand(); 1255 int64_t pow2 = N1C->getSignExtended(); 1256 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1257 unsigned lg2 = Log2_64(abs2); 1258 // Splat the sign bit into the register 1259 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0, 1260 DAG.getConstant(MVT::getSizeInBits(VT)-1, 1261 TLI.getShiftAmountTy())); 1262 AddToWorkList(SGN.Val); 1263 // Add (N0 < 0) ? abs2 - 1 : 0; 1264 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN, 1265 DAG.getConstant(MVT::getSizeInBits(VT)-lg2, 1266 TLI.getShiftAmountTy())); 1267 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL); 1268 AddToWorkList(SRL.Val); 1269 AddToWorkList(ADD.Val); // Divide by pow2 1270 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD, 1271 DAG.getConstant(lg2, TLI.getShiftAmountTy())); 1272 // If we're dividing by a positive value, we're done. Otherwise, we must 1273 // negate the result. 1274 if (pow2 > 0) 1275 return SRA; 1276 AddToWorkList(SRA.Val); 1277 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA); 1278 } 1279 // if integer divide is expensive and we satisfy the requirements, emit an 1280 // alternate sequence. 1281 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) && 1282 !TLI.isIntDivCheap()) { 1283 SDOperand Op = BuildSDIV(N); 1284 if (Op.Val) return Op; 1285 } 1286 1287 // undef / X -> 0 1288 if (N0.getOpcode() == ISD::UNDEF) 1289 return DAG.getConstant(0, VT); 1290 // X / undef -> undef 1291 if (N1.getOpcode() == ISD::UNDEF) 1292 return N1; 1293 1294 return SDOperand(); 1295} 1296 1297SDOperand DAGCombiner::visitUDIV(SDNode *N) { 1298 SDOperand N0 = N->getOperand(0); 1299 SDOperand N1 = N->getOperand(1); 1300 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1301 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1302 MVT::ValueType VT = N->getValueType(0); 1303 1304 // fold vector ops 1305 if (MVT::isVector(VT)) { 1306 SDOperand FoldedVOp = SimplifyVBinOp(N); 1307 if (FoldedVOp.Val) return FoldedVOp; 1308 } 1309 1310 // fold (udiv c1, c2) -> c1/c2 1311 if (N0C && N1C && !N1C->isNullValue()) 1312 return DAG.getNode(ISD::UDIV, VT, N0, N1); 1313 // fold (udiv x, (1 << c)) -> x >>u c 1314 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1315 return DAG.getNode(ISD::SRL, VT, N0, 1316 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1317 TLI.getShiftAmountTy())); 1318 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1319 if (N1.getOpcode() == ISD::SHL) { 1320 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1321 if (SHC->getAPIntValue().isPowerOf2()) { 1322 MVT::ValueType ADDVT = N1.getOperand(1).getValueType(); 1323 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1), 1324 DAG.getConstant(SHC->getAPIntValue() 1325 .logBase2(), 1326 ADDVT)); 1327 AddToWorkList(Add.Val); 1328 return DAG.getNode(ISD::SRL, VT, N0, Add); 1329 } 1330 } 1331 } 1332 // fold (udiv x, c) -> alternate 1333 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1334 SDOperand Op = BuildUDIV(N); 1335 if (Op.Val) return Op; 1336 } 1337 1338 // undef / X -> 0 1339 if (N0.getOpcode() == ISD::UNDEF) 1340 return DAG.getConstant(0, VT); 1341 // X / undef -> undef 1342 if (N1.getOpcode() == ISD::UNDEF) 1343 return N1; 1344 1345 return SDOperand(); 1346} 1347 1348SDOperand DAGCombiner::visitSREM(SDNode *N) { 1349 SDOperand N0 = N->getOperand(0); 1350 SDOperand N1 = N->getOperand(1); 1351 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1352 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1353 MVT::ValueType VT = N->getValueType(0); 1354 1355 // fold (srem c1, c2) -> c1%c2 1356 if (N0C && N1C && !N1C->isNullValue()) 1357 return DAG.getNode(ISD::SREM, VT, N0, N1); 1358 // If we know the sign bits of both operands are zero, strength reduce to a 1359 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1360 if (!MVT::isVector(VT)) { 1361 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1362 return DAG.getNode(ISD::UREM, VT, N0, N1); 1363 } 1364 1365 // If X/C can be simplified by the division-by-constant logic, lower 1366 // X%C to the equivalent of X-X/C*C. 1367 if (N1C && !N1C->isNullValue()) { 1368 SDOperand Div = DAG.getNode(ISD::SDIV, VT, N0, N1); 1369 AddToWorkList(Div.Val); 1370 SDOperand OptimizedDiv = combine(Div.Val); 1371 if (OptimizedDiv.Val && OptimizedDiv.Val != Div.Val) { 1372 SDOperand Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1); 1373 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1374 AddToWorkList(Mul.Val); 1375 return Sub; 1376 } 1377 } 1378 1379 // undef % X -> 0 1380 if (N0.getOpcode() == ISD::UNDEF) 1381 return DAG.getConstant(0, VT); 1382 // X % undef -> undef 1383 if (N1.getOpcode() == ISD::UNDEF) 1384 return N1; 1385 1386 return SDOperand(); 1387} 1388 1389SDOperand DAGCombiner::visitUREM(SDNode *N) { 1390 SDOperand N0 = N->getOperand(0); 1391 SDOperand N1 = N->getOperand(1); 1392 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1393 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1394 MVT::ValueType VT = N->getValueType(0); 1395 1396 // fold (urem c1, c2) -> c1%c2 1397 if (N0C && N1C && !N1C->isNullValue()) 1398 return DAG.getNode(ISD::UREM, VT, N0, N1); 1399 // fold (urem x, pow2) -> (and x, pow2-1) 1400 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 1401 return DAG.getNode(ISD::AND, VT, N0, 1402 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 1403 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1404 if (N1.getOpcode() == ISD::SHL) { 1405 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1406 if (SHC->getAPIntValue().isPowerOf2()) { 1407 SDOperand Add = 1408 DAG.getNode(ISD::ADD, VT, N1, 1409 DAG.getConstant(APInt::getAllOnesValue(MVT::getSizeInBits(VT)), 1410 VT)); 1411 AddToWorkList(Add.Val); 1412 return DAG.getNode(ISD::AND, VT, N0, Add); 1413 } 1414 } 1415 } 1416 1417 // If X/C can be simplified by the division-by-constant logic, lower 1418 // X%C to the equivalent of X-X/C*C. 1419 if (N1C && !N1C->isNullValue()) { 1420 SDOperand Div = DAG.getNode(ISD::UDIV, VT, N0, N1); 1421 SDOperand OptimizedDiv = combine(Div.Val); 1422 if (OptimizedDiv.Val && OptimizedDiv.Val != Div.Val) { 1423 SDOperand Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1); 1424 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1425 AddToWorkList(Mul.Val); 1426 return Sub; 1427 } 1428 } 1429 1430 // undef % X -> 0 1431 if (N0.getOpcode() == ISD::UNDEF) 1432 return DAG.getConstant(0, VT); 1433 // X % undef -> undef 1434 if (N1.getOpcode() == ISD::UNDEF) 1435 return N1; 1436 1437 return SDOperand(); 1438} 1439 1440SDOperand DAGCombiner::visitMULHS(SDNode *N) { 1441 SDOperand N0 = N->getOperand(0); 1442 SDOperand N1 = N->getOperand(1); 1443 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1444 MVT::ValueType VT = N->getValueType(0); 1445 1446 // fold (mulhs x, 0) -> 0 1447 if (N1C && N1C->isNullValue()) 1448 return N1; 1449 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1450 if (N1C && N1C->getAPIntValue() == 1) 1451 return DAG.getNode(ISD::SRA, N0.getValueType(), N0, 1452 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1, 1453 TLI.getShiftAmountTy())); 1454 // fold (mulhs x, undef) -> 0 1455 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1456 return DAG.getConstant(0, VT); 1457 1458 return SDOperand(); 1459} 1460 1461SDOperand DAGCombiner::visitMULHU(SDNode *N) { 1462 SDOperand N0 = N->getOperand(0); 1463 SDOperand N1 = N->getOperand(1); 1464 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1465 MVT::ValueType VT = N->getValueType(0); 1466 1467 // fold (mulhu x, 0) -> 0 1468 if (N1C && N1C->isNullValue()) 1469 return N1; 1470 // fold (mulhu x, 1) -> 0 1471 if (N1C && N1C->getAPIntValue() == 1) 1472 return DAG.getConstant(0, N0.getValueType()); 1473 // fold (mulhu x, undef) -> 0 1474 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1475 return DAG.getConstant(0, VT); 1476 1477 return SDOperand(); 1478} 1479 1480/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 1481/// compute two values. LoOp and HiOp give the opcodes for the two computations 1482/// that are being performed. Return true if a simplification was made. 1483/// 1484SDOperand DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 1485 unsigned HiOp) { 1486 // If the high half is not needed, just compute the low half. 1487 bool HiExists = N->hasAnyUseOfValue(1); 1488 if (!HiExists && 1489 (!AfterLegalize || 1490 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 1491 SDOperand Res = DAG.getNode(LoOp, N->getValueType(0), N->op_begin(), 1492 N->getNumOperands()); 1493 return CombineTo(N, Res, Res); 1494 } 1495 1496 // If the low half is not needed, just compute the high half. 1497 bool LoExists = N->hasAnyUseOfValue(0); 1498 if (!LoExists && 1499 (!AfterLegalize || 1500 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 1501 SDOperand Res = DAG.getNode(HiOp, N->getValueType(1), N->op_begin(), 1502 N->getNumOperands()); 1503 return CombineTo(N, Res, Res); 1504 } 1505 1506 // If both halves are used, return as it is. 1507 if (LoExists && HiExists) 1508 return SDOperand(); 1509 1510 // If the two computed results can be simplified separately, separate them. 1511 if (LoExists) { 1512 SDOperand Lo = DAG.getNode(LoOp, N->getValueType(0), 1513 N->op_begin(), N->getNumOperands()); 1514 AddToWorkList(Lo.Val); 1515 SDOperand LoOpt = combine(Lo.Val); 1516 if (LoOpt.Val && LoOpt.Val != Lo.Val && 1517 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())) 1518 return CombineTo(N, LoOpt, LoOpt); 1519 } 1520 1521 if (HiExists) { 1522 SDOperand Hi = DAG.getNode(HiOp, N->getValueType(1), 1523 N->op_begin(), N->getNumOperands()); 1524 AddToWorkList(Hi.Val); 1525 SDOperand HiOpt = combine(Hi.Val); 1526 if (HiOpt.Val && HiOpt != Hi && 1527 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())) 1528 return CombineTo(N, HiOpt, HiOpt); 1529 } 1530 return SDOperand(); 1531} 1532 1533SDOperand DAGCombiner::visitSMUL_LOHI(SDNode *N) { 1534 SDOperand Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 1535 if (Res.Val) return Res; 1536 1537 return SDOperand(); 1538} 1539 1540SDOperand DAGCombiner::visitUMUL_LOHI(SDNode *N) { 1541 SDOperand Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 1542 if (Res.Val) return Res; 1543 1544 return SDOperand(); 1545} 1546 1547SDOperand DAGCombiner::visitSDIVREM(SDNode *N) { 1548 SDOperand Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 1549 if (Res.Val) return Res; 1550 1551 return SDOperand(); 1552} 1553 1554SDOperand DAGCombiner::visitUDIVREM(SDNode *N) { 1555 SDOperand Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 1556 if (Res.Val) return Res; 1557 1558 return SDOperand(); 1559} 1560 1561/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 1562/// two operands of the same opcode, try to simplify it. 1563SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 1564 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1); 1565 MVT::ValueType VT = N0.getValueType(); 1566 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 1567 1568 // For each of OP in AND/OR/XOR: 1569 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 1570 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 1571 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 1572 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) 1573 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND|| 1574 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) && 1575 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1576 SDOperand ORNode = DAG.getNode(N->getOpcode(), 1577 N0.getOperand(0).getValueType(), 1578 N0.getOperand(0), N1.getOperand(0)); 1579 AddToWorkList(ORNode.Val); 1580 return DAG.getNode(N0.getOpcode(), VT, ORNode); 1581 } 1582 1583 // For each of OP in SHL/SRL/SRA/AND... 1584 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 1585 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 1586 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 1587 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 1588 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 1589 N0.getOperand(1) == N1.getOperand(1)) { 1590 SDOperand ORNode = DAG.getNode(N->getOpcode(), 1591 N0.getOperand(0).getValueType(), 1592 N0.getOperand(0), N1.getOperand(0)); 1593 AddToWorkList(ORNode.Val); 1594 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1)); 1595 } 1596 1597 return SDOperand(); 1598} 1599 1600SDOperand DAGCombiner::visitAND(SDNode *N) { 1601 SDOperand N0 = N->getOperand(0); 1602 SDOperand N1 = N->getOperand(1); 1603 SDOperand LL, LR, RL, RR, CC0, CC1; 1604 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1605 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1606 MVT::ValueType VT = N1.getValueType(); 1607 unsigned BitWidth = MVT::getSizeInBits(VT); 1608 1609 // fold vector ops 1610 if (MVT::isVector(VT)) { 1611 SDOperand FoldedVOp = SimplifyVBinOp(N); 1612 if (FoldedVOp.Val) return FoldedVOp; 1613 } 1614 1615 // fold (and x, undef) -> 0 1616 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1617 return DAG.getConstant(0, VT); 1618 // fold (and c1, c2) -> c1&c2 1619 if (N0C && N1C) 1620 return DAG.getNode(ISD::AND, VT, N0, N1); 1621 // canonicalize constant to RHS 1622 if (N0C && !N1C) 1623 return DAG.getNode(ISD::AND, VT, N1, N0); 1624 // fold (and x, -1) -> x 1625 if (N1C && N1C->isAllOnesValue()) 1626 return N0; 1627 // if (and x, c) is known to be zero, return 0 1628 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), 1629 APInt::getAllOnesValue(BitWidth))) 1630 return DAG.getConstant(0, VT); 1631 // reassociate and 1632 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1); 1633 if (RAND.Val != 0) 1634 return RAND; 1635 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 1636 if (N1C && N0.getOpcode() == ISD::OR) 1637 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1638 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 1639 return N1; 1640 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 1641 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1642 SDOperand N0Op0 = N0.getOperand(0); 1643 APInt Mask = ~N1C->getAPIntValue(); 1644 Mask.trunc(N0Op0.getValueSizeInBits()); 1645 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 1646 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(), 1647 N0Op0); 1648 1649 // Replace uses of the AND with uses of the Zero extend node. 1650 CombineTo(N, Zext); 1651 1652 // We actually want to replace all uses of the any_extend with the 1653 // zero_extend, to avoid duplicating things. This will later cause this 1654 // AND to be folded. 1655 CombineTo(N0.Val, Zext); 1656 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1657 } 1658 } 1659 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 1660 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1661 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1662 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1663 1664 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1665 MVT::isInteger(LL.getValueType())) { 1666 // fold (X == 0) & (Y == 0) -> (X|Y == 0) 1667 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 1668 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1669 AddToWorkList(ORNode.Val); 1670 return DAG.getSetCC(VT, ORNode, LR, Op1); 1671 } 1672 // fold (X == -1) & (Y == -1) -> (X&Y == -1) 1673 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 1674 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1675 AddToWorkList(ANDNode.Val); 1676 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1677 } 1678 // fold (X > -1) & (Y > -1) -> (X|Y > -1) 1679 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1680 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1681 AddToWorkList(ORNode.Val); 1682 return DAG.getSetCC(VT, ORNode, LR, Op1); 1683 } 1684 } 1685 // canonicalize equivalent to ll == rl 1686 if (LL == RR && LR == RL) { 1687 Op1 = ISD::getSetCCSwappedOperands(Op1); 1688 std::swap(RL, RR); 1689 } 1690 if (LL == RL && LR == RR) { 1691 bool isInteger = MVT::isInteger(LL.getValueType()); 1692 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1693 if (Result != ISD::SETCC_INVALID) 1694 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1695 } 1696 } 1697 1698 // Simplify: and (op x...), (op y...) -> (op (and x, y)) 1699 if (N0.getOpcode() == N1.getOpcode()) { 1700 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1701 if (Tmp.Val) return Tmp; 1702 } 1703 1704 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1705 // fold (and (sra)) -> (and (srl)) when possible. 1706 if (!MVT::isVector(VT) && 1707 SimplifyDemandedBits(SDOperand(N, 0))) 1708 return SDOperand(N, 0); 1709 // fold (zext_inreg (extload x)) -> (zextload x) 1710 if (ISD::isEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val)) { 1711 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1712 MVT::ValueType EVT = LN0->getMemoryVT(); 1713 // If we zero all the possible extended bits, then we can turn this into 1714 // a zextload if we are running before legalize or the operation is legal. 1715 unsigned BitWidth = N1.getValueSizeInBits(); 1716 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1717 BitWidth - MVT::getSizeInBits(EVT))) && 1718 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1719 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1720 LN0->getBasePtr(), LN0->getSrcValue(), 1721 LN0->getSrcValueOffset(), EVT, 1722 LN0->isVolatile(), 1723 LN0->getAlignment()); 1724 AddToWorkList(N); 1725 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1726 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1727 } 1728 } 1729 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1730 if (ISD::isSEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 1731 N0.hasOneUse()) { 1732 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1733 MVT::ValueType EVT = LN0->getMemoryVT(); 1734 // If we zero all the possible extended bits, then we can turn this into 1735 // a zextload if we are running before legalize or the operation is legal. 1736 unsigned BitWidth = N1.getValueSizeInBits(); 1737 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1738 BitWidth - MVT::getSizeInBits(EVT))) && 1739 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1740 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1741 LN0->getBasePtr(), LN0->getSrcValue(), 1742 LN0->getSrcValueOffset(), EVT, 1743 LN0->isVolatile(), 1744 LN0->getAlignment()); 1745 AddToWorkList(N); 1746 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1747 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1748 } 1749 } 1750 1751 // fold (and (load x), 255) -> (zextload x, i8) 1752 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1753 if (N1C && N0.getOpcode() == ISD::LOAD) { 1754 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1755 if (LN0->getExtensionType() != ISD::SEXTLOAD && 1756 LN0->isUnindexed() && N0.hasOneUse()) { 1757 MVT::ValueType EVT, LoadedVT; 1758 if (N1C->getAPIntValue() == 255) 1759 EVT = MVT::i8; 1760 else if (N1C->getAPIntValue() == 65535) 1761 EVT = MVT::i16; 1762 else if (N1C->getAPIntValue() == ~0U) 1763 EVT = MVT::i32; 1764 else 1765 EVT = MVT::Other; 1766 1767 LoadedVT = LN0->getMemoryVT(); 1768 if (EVT != MVT::Other && LoadedVT > EVT && 1769 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1770 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 1771 // For big endian targets, we need to add an offset to the pointer to 1772 // load the correct bytes. For little endian systems, we merely need to 1773 // read fewer bytes from the same pointer. 1774 unsigned LVTStoreBytes = MVT::getStoreSizeInBits(LoadedVT)/8; 1775 unsigned EVTStoreBytes = MVT::getStoreSizeInBits(EVT)/8; 1776 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 1777 unsigned Alignment = LN0->getAlignment(); 1778 SDOperand NewPtr = LN0->getBasePtr(); 1779 if (TLI.isBigEndian()) { 1780 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, 1781 DAG.getConstant(PtrOff, PtrType)); 1782 Alignment = MinAlign(Alignment, PtrOff); 1783 } 1784 AddToWorkList(NewPtr.Val); 1785 SDOperand Load = 1786 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr, 1787 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT, 1788 LN0->isVolatile(), Alignment); 1789 AddToWorkList(N); 1790 CombineTo(N0.Val, Load, Load.getValue(1)); 1791 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1792 } 1793 } 1794 } 1795 1796 return SDOperand(); 1797} 1798 1799SDOperand DAGCombiner::visitOR(SDNode *N) { 1800 SDOperand N0 = N->getOperand(0); 1801 SDOperand N1 = N->getOperand(1); 1802 SDOperand LL, LR, RL, RR, CC0, CC1; 1803 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1804 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1805 MVT::ValueType VT = N1.getValueType(); 1806 1807 // fold vector ops 1808 if (MVT::isVector(VT)) { 1809 SDOperand FoldedVOp = SimplifyVBinOp(N); 1810 if (FoldedVOp.Val) return FoldedVOp; 1811 } 1812 1813 // fold (or x, undef) -> -1 1814 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1815 return DAG.getConstant(~0ULL, VT); 1816 // fold (or c1, c2) -> c1|c2 1817 if (N0C && N1C) 1818 return DAG.getNode(ISD::OR, VT, N0, N1); 1819 // canonicalize constant to RHS 1820 if (N0C && !N1C) 1821 return DAG.getNode(ISD::OR, VT, N1, N0); 1822 // fold (or x, 0) -> x 1823 if (N1C && N1C->isNullValue()) 1824 return N0; 1825 // fold (or x, -1) -> -1 1826 if (N1C && N1C->isAllOnesValue()) 1827 return N1; 1828 // fold (or x, c) -> c iff (x & ~c) == 0 1829 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 1830 return N1; 1831 // reassociate or 1832 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1); 1833 if (ROR.Val != 0) 1834 return ROR; 1835 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 1836 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() && 1837 isa<ConstantSDNode>(N0.getOperand(1))) { 1838 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 1839 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0), 1840 N1), 1841 DAG.getConstant(N1C->getAPIntValue() | 1842 C1->getAPIntValue(), VT)); 1843 } 1844 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 1845 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1846 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1847 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1848 1849 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1850 MVT::isInteger(LL.getValueType())) { 1851 // fold (X != 0) | (Y != 0) -> (X|Y != 0) 1852 // fold (X < 0) | (Y < 0) -> (X|Y < 0) 1853 if (cast<ConstantSDNode>(LR)->isNullValue() && 1854 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 1855 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1856 AddToWorkList(ORNode.Val); 1857 return DAG.getSetCC(VT, ORNode, LR, Op1); 1858 } 1859 // fold (X != -1) | (Y != -1) -> (X&Y != -1) 1860 // fold (X > -1) | (Y > -1) -> (X&Y > -1) 1861 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 1862 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 1863 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1864 AddToWorkList(ANDNode.Val); 1865 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1866 } 1867 } 1868 // canonicalize equivalent to ll == rl 1869 if (LL == RR && LR == RL) { 1870 Op1 = ISD::getSetCCSwappedOperands(Op1); 1871 std::swap(RL, RR); 1872 } 1873 if (LL == RL && LR == RR) { 1874 bool isInteger = MVT::isInteger(LL.getValueType()); 1875 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 1876 if (Result != ISD::SETCC_INVALID) 1877 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1878 } 1879 } 1880 1881 // Simplify: or (op x...), (op y...) -> (op (or x, y)) 1882 if (N0.getOpcode() == N1.getOpcode()) { 1883 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1884 if (Tmp.Val) return Tmp; 1885 } 1886 1887 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible. 1888 if (N0.getOpcode() == ISD::AND && 1889 N1.getOpcode() == ISD::AND && 1890 N0.getOperand(1).getOpcode() == ISD::Constant && 1891 N1.getOperand(1).getOpcode() == ISD::Constant && 1892 // Don't increase # computations. 1893 (N0.Val->hasOneUse() || N1.Val->hasOneUse())) { 1894 // We can only do this xform if we know that bits from X that are set in C2 1895 // but not in C1 are already zero. Likewise for Y. 1896 const APInt &LHSMask = 1897 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 1898 const APInt &RHSMask = 1899 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 1900 1901 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 1902 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 1903 SDOperand X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0)); 1904 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT)); 1905 } 1906 } 1907 1908 1909 // See if this is some rotate idiom. 1910 if (SDNode *Rot = MatchRotate(N0, N1)) 1911 return SDOperand(Rot, 0); 1912 1913 return SDOperand(); 1914} 1915 1916 1917/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 1918static bool MatchRotateHalf(SDOperand Op, SDOperand &Shift, SDOperand &Mask) { 1919 if (Op.getOpcode() == ISD::AND) { 1920 if (isa<ConstantSDNode>(Op.getOperand(1))) { 1921 Mask = Op.getOperand(1); 1922 Op = Op.getOperand(0); 1923 } else { 1924 return false; 1925 } 1926 } 1927 1928 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 1929 Shift = Op; 1930 return true; 1931 } 1932 return false; 1933} 1934 1935 1936// MatchRotate - Handle an 'or' of two operands. If this is one of the many 1937// idioms for rotate, and if the target supports rotation instructions, generate 1938// a rot[lr]. 1939SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) { 1940 // Must be a legal type. Expanded an promoted things won't work with rotates. 1941 MVT::ValueType VT = LHS.getValueType(); 1942 if (!TLI.isTypeLegal(VT)) return 0; 1943 1944 // The target must have at least one rotate flavor. 1945 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT); 1946 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT); 1947 if (!HasROTL && !HasROTR) return 0; 1948 1949 // Match "(X shl/srl V1) & V2" where V2 may not be present. 1950 SDOperand LHSShift; // The shift. 1951 SDOperand LHSMask; // AND value if any. 1952 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 1953 return 0; // Not part of a rotate. 1954 1955 SDOperand RHSShift; // The shift. 1956 SDOperand RHSMask; // AND value if any. 1957 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 1958 return 0; // Not part of a rotate. 1959 1960 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 1961 return 0; // Not shifting the same value. 1962 1963 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 1964 return 0; // Shifts must disagree. 1965 1966 // Canonicalize shl to left side in a shl/srl pair. 1967 if (RHSShift.getOpcode() == ISD::SHL) { 1968 std::swap(LHS, RHS); 1969 std::swap(LHSShift, RHSShift); 1970 std::swap(LHSMask , RHSMask ); 1971 } 1972 1973 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1974 SDOperand LHSShiftArg = LHSShift.getOperand(0); 1975 SDOperand LHSShiftAmt = LHSShift.getOperand(1); 1976 SDOperand RHSShiftAmt = RHSShift.getOperand(1); 1977 1978 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 1979 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 1980 if (LHSShiftAmt.getOpcode() == ISD::Constant && 1981 RHSShiftAmt.getOpcode() == ISD::Constant) { 1982 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getValue(); 1983 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getValue(); 1984 if ((LShVal + RShVal) != OpSizeInBits) 1985 return 0; 1986 1987 SDOperand Rot; 1988 if (HasROTL) 1989 Rot = DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt); 1990 else 1991 Rot = DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt); 1992 1993 // If there is an AND of either shifted operand, apply it to the result. 1994 if (LHSMask.Val || RHSMask.Val) { 1995 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 1996 1997 if (LHSMask.Val) { 1998 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 1999 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 2000 } 2001 if (RHSMask.Val) { 2002 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 2003 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 2004 } 2005 2006 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT)); 2007 } 2008 2009 return Rot.Val; 2010 } 2011 2012 // If there is a mask here, and we have a variable shift, we can't be sure 2013 // that we're masking out the right stuff. 2014 if (LHSMask.Val || RHSMask.Val) 2015 return 0; 2016 2017 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 2018 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 2019 if (RHSShiftAmt.getOpcode() == ISD::SUB && 2020 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 2021 if (ConstantSDNode *SUBC = 2022 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 2023 if (SUBC->getAPIntValue() == OpSizeInBits) { 2024 if (HasROTL) 2025 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 2026 else 2027 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 2028 } 2029 } 2030 } 2031 2032 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 2033 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 2034 if (LHSShiftAmt.getOpcode() == ISD::SUB && 2035 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 2036 if (ConstantSDNode *SUBC = 2037 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 2038 if (SUBC->getAPIntValue() == OpSizeInBits) { 2039 if (HasROTL) 2040 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 2041 else 2042 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 2043 } 2044 } 2045 } 2046 2047 // Look for sign/zext/any-extended cases: 2048 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2049 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2050 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND) && 2051 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2052 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2053 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND)) { 2054 SDOperand LExtOp0 = LHSShiftAmt.getOperand(0); 2055 SDOperand RExtOp0 = RHSShiftAmt.getOperand(0); 2056 if (RExtOp0.getOpcode() == ISD::SUB && 2057 RExtOp0.getOperand(1) == LExtOp0) { 2058 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2059 // (rotr x, y) 2060 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2061 // (rotl x, (sub 32, y)) 2062 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 2063 if (SUBC->getAPIntValue() == OpSizeInBits) { 2064 if (HasROTL) 2065 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 2066 else 2067 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 2068 } 2069 } 2070 } else if (LExtOp0.getOpcode() == ISD::SUB && 2071 RExtOp0 == LExtOp0.getOperand(1)) { 2072 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -> 2073 // (rotl x, y) 2074 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -> 2075 // (rotr x, (sub 32, y)) 2076 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 2077 if (SUBC->getAPIntValue() == OpSizeInBits) { 2078 if (HasROTL) 2079 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, RHSShiftAmt).Val; 2080 else 2081 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 2082 } 2083 } 2084 } 2085 } 2086 2087 return 0; 2088} 2089 2090 2091SDOperand DAGCombiner::visitXOR(SDNode *N) { 2092 SDOperand N0 = N->getOperand(0); 2093 SDOperand N1 = N->getOperand(1); 2094 SDOperand LHS, RHS, CC; 2095 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2096 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2097 MVT::ValueType VT = N0.getValueType(); 2098 2099 // fold vector ops 2100 if (MVT::isVector(VT)) { 2101 SDOperand FoldedVOp = SimplifyVBinOp(N); 2102 if (FoldedVOp.Val) return FoldedVOp; 2103 } 2104 2105 // fold (xor x, undef) -> undef 2106 if (N0.getOpcode() == ISD::UNDEF) 2107 return N0; 2108 if (N1.getOpcode() == ISD::UNDEF) 2109 return N1; 2110 // fold (xor c1, c2) -> c1^c2 2111 if (N0C && N1C) 2112 return DAG.getNode(ISD::XOR, VT, N0, N1); 2113 // canonicalize constant to RHS 2114 if (N0C && !N1C) 2115 return DAG.getNode(ISD::XOR, VT, N1, N0); 2116 // fold (xor x, 0) -> x 2117 if (N1C && N1C->isNullValue()) 2118 return N0; 2119 // reassociate xor 2120 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1); 2121 if (RXOR.Val != 0) 2122 return RXOR; 2123 // fold !(x cc y) -> (x !cc y) 2124 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 2125 bool isInt = MVT::isInteger(LHS.getValueType()); 2126 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 2127 isInt); 2128 if (N0.getOpcode() == ISD::SETCC) 2129 return DAG.getSetCC(VT, LHS, RHS, NotCC); 2130 if (N0.getOpcode() == ISD::SELECT_CC) 2131 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC); 2132 assert(0 && "Unhandled SetCC Equivalent!"); 2133 abort(); 2134 } 2135 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 2136 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 2137 N0.Val->hasOneUse() && isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 2138 SDOperand V = N0.getOperand(0); 2139 V = DAG.getNode(ISD::XOR, V.getValueType(), V, 2140 DAG.getConstant(1, V.getValueType())); 2141 AddToWorkList(V.Val); 2142 return DAG.getNode(ISD::ZERO_EXTEND, VT, V); 2143 } 2144 2145 // fold !(x or y) -> (!x and !y) iff x or y are setcc 2146 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 2147 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2148 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2149 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 2150 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2151 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 2152 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 2153 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 2154 return DAG.getNode(NewOpcode, VT, LHS, RHS); 2155 } 2156 } 2157 // fold !(x or y) -> (!x and !y) iff x or y are constants 2158 if (N1C && N1C->isAllOnesValue() && 2159 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2160 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2161 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 2162 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2163 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 2164 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 2165 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 2166 return DAG.getNode(NewOpcode, VT, LHS, RHS); 2167 } 2168 } 2169 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2) 2170 if (N1C && N0.getOpcode() == ISD::XOR) { 2171 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 2172 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2173 if (N00C) 2174 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1), 2175 DAG.getConstant(N1C->getAPIntValue()^ 2176 N00C->getAPIntValue(), VT)); 2177 if (N01C) 2178 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0), 2179 DAG.getConstant(N1C->getAPIntValue()^ 2180 N01C->getAPIntValue(), VT)); 2181 } 2182 // fold (xor x, x) -> 0 2183 if (N0 == N1) { 2184 if (!MVT::isVector(VT)) { 2185 return DAG.getConstant(0, VT); 2186 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 2187 // Produce a vector of zeros. 2188 SDOperand El = DAG.getConstant(0, MVT::getVectorElementType(VT)); 2189 std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El); 2190 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 2191 } 2192 } 2193 2194 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 2195 if (N0.getOpcode() == N1.getOpcode()) { 2196 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2197 if (Tmp.Val) return Tmp; 2198 } 2199 2200 // Simplify the expression using non-local knowledge. 2201 if (!MVT::isVector(VT) && 2202 SimplifyDemandedBits(SDOperand(N, 0))) 2203 return SDOperand(N, 0); 2204 2205 return SDOperand(); 2206} 2207 2208/// visitShiftByConstant - Handle transforms common to the three shifts, when 2209/// the shift amount is a constant. 2210SDOperand DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 2211 SDNode *LHS = N->getOperand(0).Val; 2212 if (!LHS->hasOneUse()) return SDOperand(); 2213 2214 // We want to pull some binops through shifts, so that we have (and (shift)) 2215 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 2216 // thing happens with address calculations, so it's important to canonicalize 2217 // it. 2218 bool HighBitSet = false; // Can we transform this if the high bit is set? 2219 2220 switch (LHS->getOpcode()) { 2221 default: return SDOperand(); 2222 case ISD::OR: 2223 case ISD::XOR: 2224 HighBitSet = false; // We can only transform sra if the high bit is clear. 2225 break; 2226 case ISD::AND: 2227 HighBitSet = true; // We can only transform sra if the high bit is set. 2228 break; 2229 case ISD::ADD: 2230 if (N->getOpcode() != ISD::SHL) 2231 return SDOperand(); // only shl(add) not sr[al](add). 2232 HighBitSet = false; // We can only transform sra if the high bit is clear. 2233 break; 2234 } 2235 2236 // We require the RHS of the binop to be a constant as well. 2237 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 2238 if (!BinOpCst) return SDOperand(); 2239 2240 2241 // FIXME: disable this for unless the input to the binop is a shift by a 2242 // constant. If it is not a shift, it pessimizes some common cases like: 2243 // 2244 //void foo(int *X, int i) { X[i & 1235] = 1; } 2245 //int bar(int *X, int i) { return X[i & 255]; } 2246 SDNode *BinOpLHSVal = LHS->getOperand(0).Val; 2247 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 2248 BinOpLHSVal->getOpcode() != ISD::SRA && 2249 BinOpLHSVal->getOpcode() != ISD::SRL) || 2250 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 2251 return SDOperand(); 2252 2253 MVT::ValueType VT = N->getValueType(0); 2254 2255 // If this is a signed shift right, and the high bit is modified 2256 // by the logical operation, do not perform the transformation. 2257 // The highBitSet boolean indicates the value of the high bit of 2258 // the constant which would cause it to be modified for this 2259 // operation. 2260 if (N->getOpcode() == ISD::SRA) { 2261 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 2262 if (BinOpRHSSignSet != HighBitSet) 2263 return SDOperand(); 2264 } 2265 2266 // Fold the constants, shifting the binop RHS by the shift amount. 2267 SDOperand NewRHS = DAG.getNode(N->getOpcode(), N->getValueType(0), 2268 LHS->getOperand(1), N->getOperand(1)); 2269 2270 // Create the new shift. 2271 SDOperand NewShift = DAG.getNode(N->getOpcode(), VT, LHS->getOperand(0), 2272 N->getOperand(1)); 2273 2274 // Create the new binop. 2275 return DAG.getNode(LHS->getOpcode(), VT, NewShift, NewRHS); 2276} 2277 2278 2279SDOperand DAGCombiner::visitSHL(SDNode *N) { 2280 SDOperand N0 = N->getOperand(0); 2281 SDOperand N1 = N->getOperand(1); 2282 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2283 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2284 MVT::ValueType VT = N0.getValueType(); 2285 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 2286 2287 // fold (shl c1, c2) -> c1<<c2 2288 if (N0C && N1C) 2289 return DAG.getNode(ISD::SHL, VT, N0, N1); 2290 // fold (shl 0, x) -> 0 2291 if (N0C && N0C->isNullValue()) 2292 return N0; 2293 // fold (shl x, c >= size(x)) -> undef 2294 if (N1C && N1C->getValue() >= OpSizeInBits) 2295 return DAG.getNode(ISD::UNDEF, VT); 2296 // fold (shl x, 0) -> x 2297 if (N1C && N1C->isNullValue()) 2298 return N0; 2299 // if (shl x, c) is known to be zero, return 0 2300 if (DAG.MaskedValueIsZero(SDOperand(N, 0), 2301 APInt::getAllOnesValue(MVT::getSizeInBits(VT)))) 2302 return DAG.getConstant(0, VT); 2303 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 2304 return SDOperand(N, 0); 2305 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2) 2306 if (N1C && N0.getOpcode() == ISD::SHL && 2307 N0.getOperand(1).getOpcode() == ISD::Constant) { 2308 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2309 uint64_t c2 = N1C->getValue(); 2310 if (c1 + c2 > OpSizeInBits) 2311 return DAG.getConstant(0, VT); 2312 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0), 2313 DAG.getConstant(c1 + c2, N1.getValueType())); 2314 } 2315 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or 2316 // (srl (and x, -1 << c1), c1-c2) 2317 if (N1C && N0.getOpcode() == ISD::SRL && 2318 N0.getOperand(1).getOpcode() == ISD::Constant) { 2319 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2320 uint64_t c2 = N1C->getValue(); 2321 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0), 2322 DAG.getConstant(~0ULL << c1, VT)); 2323 if (c2 > c1) 2324 return DAG.getNode(ISD::SHL, VT, Mask, 2325 DAG.getConstant(c2-c1, N1.getValueType())); 2326 else 2327 return DAG.getNode(ISD::SRL, VT, Mask, 2328 DAG.getConstant(c1-c2, N1.getValueType())); 2329 } 2330 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1) 2331 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 2332 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 2333 DAG.getConstant(~0ULL << N1C->getValue(), VT)); 2334 2335 return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDOperand(); 2336} 2337 2338SDOperand DAGCombiner::visitSRA(SDNode *N) { 2339 SDOperand N0 = N->getOperand(0); 2340 SDOperand N1 = N->getOperand(1); 2341 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2342 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2343 MVT::ValueType VT = N0.getValueType(); 2344 2345 // fold (sra c1, c2) -> c1>>c2 2346 if (N0C && N1C) 2347 return DAG.getNode(ISD::SRA, VT, N0, N1); 2348 // fold (sra 0, x) -> 0 2349 if (N0C && N0C->isNullValue()) 2350 return N0; 2351 // fold (sra -1, x) -> -1 2352 if (N0C && N0C->isAllOnesValue()) 2353 return N0; 2354 // fold (sra x, c >= size(x)) -> undef 2355 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT)) 2356 return DAG.getNode(ISD::UNDEF, VT); 2357 // fold (sra x, 0) -> x 2358 if (N1C && N1C->isNullValue()) 2359 return N0; 2360 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 2361 // sext_inreg. 2362 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 2363 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue(); 2364 MVT::ValueType EVT; 2365 switch (LowBits) { 2366 default: EVT = MVT::Other; break; 2367 case 1: EVT = MVT::i1; break; 2368 case 8: EVT = MVT::i8; break; 2369 case 16: EVT = MVT::i16; break; 2370 case 32: EVT = MVT::i32; break; 2371 } 2372 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT)) 2373 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), 2374 DAG.getValueType(EVT)); 2375 } 2376 2377 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2) 2378 if (N1C && N0.getOpcode() == ISD::SRA) { 2379 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2380 unsigned Sum = N1C->getValue() + C1->getValue(); 2381 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1; 2382 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), 2383 DAG.getConstant(Sum, N1C->getValueType(0))); 2384 } 2385 } 2386 2387 // fold sra (shl X, m), result_size - n 2388 // -> (sign_extend (trunc (shl X, result_size - n - m))) for 2389 // result_size - n != m. If truncate is free for the target sext(shl) is 2390 // likely to result in better code. 2391 if (N0.getOpcode() == ISD::SHL) { 2392 // Get the two constanst of the shifts, CN0 = m, CN = n. 2393 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2394 if (N01C && N1C) { 2395 // Determine if the truncate type's bitsize would correspond to 2396 // an integer type for this target. 2397 unsigned VTValSize = MVT::getSizeInBits(VT); 2398 MVT::ValueType TruncVT = MVT::getIntegerType(VTValSize - N1C->getValue()); 2399 unsigned ShiftAmt = N1C->getValue() - N01C->getValue(); 2400 2401 // If the shift wouldn't be a noop, the truncated type is an actual type, 2402 // and the truncate is free, then proceed with the transform. 2403 if (ShiftAmt != 0 && 2404 TLI.isTypeLegal(TruncVT) && 2405 TLI.isTruncateFree(VT, TruncVT)) { 2406 SDOperand Amt = DAG.getConstant(ShiftAmt, TLI.getShiftAmountTy()); 2407 SDOperand Shift = DAG.getNode(ISD::SRL, VT, N0.getOperand(0), Amt); 2408 SDOperand Trunc = DAG.getNode(ISD::TRUNCATE, TruncVT, Shift); 2409 return DAG.getNode(ISD::SIGN_EXTEND, N->getValueType(0), Trunc); 2410 } 2411 } 2412 } 2413 2414 // Simplify, based on bits shifted out of the LHS. 2415 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 2416 return SDOperand(N, 0); 2417 2418 2419 // If the sign bit is known to be zero, switch this to a SRL. 2420 if (DAG.SignBitIsZero(N0)) 2421 return DAG.getNode(ISD::SRL, VT, N0, N1); 2422 2423 return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDOperand(); 2424} 2425 2426SDOperand DAGCombiner::visitSRL(SDNode *N) { 2427 SDOperand N0 = N->getOperand(0); 2428 SDOperand N1 = N->getOperand(1); 2429 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2430 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2431 MVT::ValueType VT = N0.getValueType(); 2432 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 2433 2434 // fold (srl c1, c2) -> c1 >>u c2 2435 if (N0C && N1C) 2436 return DAG.getNode(ISD::SRL, VT, N0, N1); 2437 // fold (srl 0, x) -> 0 2438 if (N0C && N0C->isNullValue()) 2439 return N0; 2440 // fold (srl x, c >= size(x)) -> undef 2441 if (N1C && N1C->getValue() >= OpSizeInBits) 2442 return DAG.getNode(ISD::UNDEF, VT); 2443 // fold (srl x, 0) -> x 2444 if (N1C && N1C->isNullValue()) 2445 return N0; 2446 // if (srl x, c) is known to be zero, return 0 2447 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), 2448 APInt::getAllOnesValue(OpSizeInBits))) 2449 return DAG.getConstant(0, VT); 2450 2451 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2) 2452 if (N1C && N0.getOpcode() == ISD::SRL && 2453 N0.getOperand(1).getOpcode() == ISD::Constant) { 2454 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2455 uint64_t c2 = N1C->getValue(); 2456 if (c1 + c2 > OpSizeInBits) 2457 return DAG.getConstant(0, VT); 2458 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 2459 DAG.getConstant(c1 + c2, N1.getValueType())); 2460 } 2461 2462 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 2463 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2464 // Shifting in all undef bits? 2465 MVT::ValueType SmallVT = N0.getOperand(0).getValueType(); 2466 if (N1C->getValue() >= MVT::getSizeInBits(SmallVT)) 2467 return DAG.getNode(ISD::UNDEF, VT); 2468 2469 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1); 2470 AddToWorkList(SmallShift.Val); 2471 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift); 2472 } 2473 2474 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 2475 // bit, which is unmodified by sra. 2476 if (N1C && N1C->getValue()+1 == MVT::getSizeInBits(VT)) { 2477 if (N0.getOpcode() == ISD::SRA) 2478 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1); 2479 } 2480 2481 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 2482 if (N1C && N0.getOpcode() == ISD::CTLZ && 2483 N1C->getAPIntValue() == Log2_32(MVT::getSizeInBits(VT))) { 2484 APInt KnownZero, KnownOne; 2485 APInt Mask = APInt::getAllOnesValue(MVT::getSizeInBits(VT)); 2486 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 2487 2488 // If any of the input bits are KnownOne, then the input couldn't be all 2489 // zeros, thus the result of the srl will always be zero. 2490 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 2491 2492 // If all of the bits input the to ctlz node are known to be zero, then 2493 // the result of the ctlz is "32" and the result of the shift is one. 2494 APInt UnknownBits = ~KnownZero & Mask; 2495 if (UnknownBits == 0) return DAG.getConstant(1, VT); 2496 2497 // Otherwise, check to see if there is exactly one bit input to the ctlz. 2498 if ((UnknownBits & (UnknownBits-1)) == 0) { 2499 // Okay, we know that only that the single bit specified by UnknownBits 2500 // could be set on input to the CTLZ node. If this bit is set, the SRL 2501 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 2502 // to an SRL,XOR pair, which is likely to simplify more. 2503 unsigned ShAmt = UnknownBits.countTrailingZeros(); 2504 SDOperand Op = N0.getOperand(0); 2505 if (ShAmt) { 2506 Op = DAG.getNode(ISD::SRL, VT, Op, 2507 DAG.getConstant(ShAmt, TLI.getShiftAmountTy())); 2508 AddToWorkList(Op.Val); 2509 } 2510 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT)); 2511 } 2512 } 2513 2514 // fold operands of srl based on knowledge that the low bits are not 2515 // demanded. 2516 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 2517 return SDOperand(N, 0); 2518 2519 return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDOperand(); 2520} 2521 2522SDOperand DAGCombiner::visitCTLZ(SDNode *N) { 2523 SDOperand N0 = N->getOperand(0); 2524 MVT::ValueType VT = N->getValueType(0); 2525 2526 // fold (ctlz c1) -> c2 2527 if (isa<ConstantSDNode>(N0)) 2528 return DAG.getNode(ISD::CTLZ, VT, N0); 2529 return SDOperand(); 2530} 2531 2532SDOperand DAGCombiner::visitCTTZ(SDNode *N) { 2533 SDOperand N0 = N->getOperand(0); 2534 MVT::ValueType VT = N->getValueType(0); 2535 2536 // fold (cttz c1) -> c2 2537 if (isa<ConstantSDNode>(N0)) 2538 return DAG.getNode(ISD::CTTZ, VT, N0); 2539 return SDOperand(); 2540} 2541 2542SDOperand DAGCombiner::visitCTPOP(SDNode *N) { 2543 SDOperand N0 = N->getOperand(0); 2544 MVT::ValueType VT = N->getValueType(0); 2545 2546 // fold (ctpop c1) -> c2 2547 if (isa<ConstantSDNode>(N0)) 2548 return DAG.getNode(ISD::CTPOP, VT, N0); 2549 return SDOperand(); 2550} 2551 2552SDOperand DAGCombiner::visitSELECT(SDNode *N) { 2553 SDOperand N0 = N->getOperand(0); 2554 SDOperand N1 = N->getOperand(1); 2555 SDOperand N2 = N->getOperand(2); 2556 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2557 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2558 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 2559 MVT::ValueType VT = N->getValueType(0); 2560 MVT::ValueType VT0 = N0.getValueType(); 2561 2562 // fold select C, X, X -> X 2563 if (N1 == N2) 2564 return N1; 2565 // fold select true, X, Y -> X 2566 if (N0C && !N0C->isNullValue()) 2567 return N1; 2568 // fold select false, X, Y -> Y 2569 if (N0C && N0C->isNullValue()) 2570 return N2; 2571 // fold select C, 1, X -> C | X 2572 if (MVT::i1 == VT && N1C && N1C->getAPIntValue() == 1) 2573 return DAG.getNode(ISD::OR, VT, N0, N2); 2574 // fold select C, 0, 1 -> ~C 2575 if (MVT::isInteger(VT) && MVT::isInteger(VT0) && 2576 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 2577 SDOperand XORNode = DAG.getNode(ISD::XOR, VT0, N0, DAG.getConstant(1, VT0)); 2578 if (VT == VT0) 2579 return XORNode; 2580 AddToWorkList(XORNode.Val); 2581 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(VT0)) 2582 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode); 2583 return DAG.getNode(ISD::TRUNCATE, VT, XORNode); 2584 } 2585 // fold select C, 0, X -> ~C & X 2586 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 2587 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 2588 AddToWorkList(XORNode.Val); 2589 return DAG.getNode(ISD::AND, VT, XORNode, N2); 2590 } 2591 // fold select C, X, 1 -> ~C | X 2592 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 2593 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 2594 AddToWorkList(XORNode.Val); 2595 return DAG.getNode(ISD::OR, VT, XORNode, N1); 2596 } 2597 // fold select C, X, 0 -> C & X 2598 // FIXME: this should check for C type == X type, not i1? 2599 if (MVT::i1 == VT && N2C && N2C->isNullValue()) 2600 return DAG.getNode(ISD::AND, VT, N0, N1); 2601 // fold X ? X : Y --> X ? 1 : Y --> X | Y 2602 if (MVT::i1 == VT && N0 == N1) 2603 return DAG.getNode(ISD::OR, VT, N0, N2); 2604 // fold X ? Y : X --> X ? Y : 0 --> X & Y 2605 if (MVT::i1 == VT && N0 == N2) 2606 return DAG.getNode(ISD::AND, VT, N0, N1); 2607 2608 // If we can fold this based on the true/false value, do so. 2609 if (SimplifySelectOps(N, N1, N2)) 2610 return SDOperand(N, 0); // Don't revisit N. 2611 2612 // fold selects based on a setcc into other things, such as min/max/abs 2613 if (N0.getOpcode() == ISD::SETCC) { 2614 // FIXME: 2615 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 2616 // having to say they don't support SELECT_CC on every type the DAG knows 2617 // about, since there is no way to mark an opcode illegal at all value types 2618 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other)) 2619 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1), 2620 N1, N2, N0.getOperand(2)); 2621 else 2622 return SimplifySelect(N0, N1, N2); 2623 } 2624 return SDOperand(); 2625} 2626 2627SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) { 2628 SDOperand N0 = N->getOperand(0); 2629 SDOperand N1 = N->getOperand(1); 2630 SDOperand N2 = N->getOperand(2); 2631 SDOperand N3 = N->getOperand(3); 2632 SDOperand N4 = N->getOperand(4); 2633 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 2634 2635 // fold select_cc lhs, rhs, x, x, cc -> x 2636 if (N2 == N3) 2637 return N2; 2638 2639 // Determine if the condition we're dealing with is constant 2640 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultType(N0), N0, N1, CC, false); 2641 if (SCC.Val) AddToWorkList(SCC.Val); 2642 2643 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) { 2644 if (!SCCC->isNullValue()) 2645 return N2; // cond always true -> true val 2646 else 2647 return N3; // cond always false -> false val 2648 } 2649 2650 // Fold to a simpler select_cc 2651 if (SCC.Val && SCC.getOpcode() == ISD::SETCC) 2652 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(), 2653 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 2654 SCC.getOperand(2)); 2655 2656 // If we can fold this based on the true/false value, do so. 2657 if (SimplifySelectOps(N, N2, N3)) 2658 return SDOperand(N, 0); // Don't revisit N. 2659 2660 // fold select_cc into other things, such as min/max/abs 2661 return SimplifySelectCC(N0, N1, N2, N3, CC); 2662} 2663 2664SDOperand DAGCombiner::visitSETCC(SDNode *N) { 2665 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 2666 cast<CondCodeSDNode>(N->getOperand(2))->get()); 2667} 2668 2669// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 2670// "fold ({s|z}ext (load x)) -> ({s|z}ext (truncate ({s|z}extload x)))" 2671// transformation. Returns true if extension are possible and the above 2672// mentioned transformation is profitable. 2673static bool ExtendUsesToFormExtLoad(SDNode *N, SDOperand N0, 2674 unsigned ExtOpc, 2675 SmallVector<SDNode*, 4> &ExtendNodes, 2676 TargetLowering &TLI) { 2677 bool HasCopyToRegUses = false; 2678 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 2679 for (SDNode::use_iterator UI = N0.Val->use_begin(), UE = N0.Val->use_end(); 2680 UI != UE; ++UI) { 2681 SDNode *User = *UI; 2682 if (User == N) 2683 continue; 2684 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 2685 if (User->getOpcode() == ISD::SETCC) { 2686 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 2687 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 2688 // Sign bits will be lost after a zext. 2689 return false; 2690 bool Add = false; 2691 for (unsigned i = 0; i != 2; ++i) { 2692 SDOperand UseOp = User->getOperand(i); 2693 if (UseOp == N0) 2694 continue; 2695 if (!isa<ConstantSDNode>(UseOp)) 2696 return false; 2697 Add = true; 2698 } 2699 if (Add) 2700 ExtendNodes.push_back(User); 2701 } else { 2702 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2703 SDOperand UseOp = User->getOperand(i); 2704 if (UseOp == N0) { 2705 // If truncate from extended type to original load type is free 2706 // on this target, then it's ok to extend a CopyToReg. 2707 if (isTruncFree && User->getOpcode() == ISD::CopyToReg) 2708 HasCopyToRegUses = true; 2709 else 2710 return false; 2711 } 2712 } 2713 } 2714 } 2715 2716 if (HasCopyToRegUses) { 2717 bool BothLiveOut = false; 2718 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 2719 UI != UE; ++UI) { 2720 SDNode *User = *UI; 2721 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2722 SDOperand UseOp = User->getOperand(i); 2723 if (UseOp.Val == N && UseOp.ResNo == 0) { 2724 BothLiveOut = true; 2725 break; 2726 } 2727 } 2728 } 2729 if (BothLiveOut) 2730 // Both unextended and extended values are live out. There had better be 2731 // good a reason for the transformation. 2732 return ExtendNodes.size(); 2733 } 2734 return true; 2735} 2736 2737SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 2738 SDOperand N0 = N->getOperand(0); 2739 MVT::ValueType VT = N->getValueType(0); 2740 2741 // fold (sext c1) -> c1 2742 if (isa<ConstantSDNode>(N0)) 2743 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0); 2744 2745 // fold (sext (sext x)) -> (sext x) 2746 // fold (sext (aext x)) -> (sext x) 2747 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2748 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0)); 2749 2750 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 2751 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 2752 if (N0.getOpcode() == ISD::TRUNCATE) { 2753 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2754 if (NarrowLoad.Val) { 2755 if (NarrowLoad.Val != N0.Val) 2756 CombineTo(N0.Val, NarrowLoad); 2757 return DAG.getNode(ISD::SIGN_EXTEND, VT, NarrowLoad); 2758 } 2759 } 2760 2761 // See if the value being truncated is already sign extended. If so, just 2762 // eliminate the trunc/sext pair. 2763 if (N0.getOpcode() == ISD::TRUNCATE) { 2764 SDOperand Op = N0.getOperand(0); 2765 unsigned OpBits = MVT::getSizeInBits(Op.getValueType()); 2766 unsigned MidBits = MVT::getSizeInBits(N0.getValueType()); 2767 unsigned DestBits = MVT::getSizeInBits(VT); 2768 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 2769 2770 if (OpBits == DestBits) { 2771 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 2772 // bits, it is already ready. 2773 if (NumSignBits > DestBits-MidBits) 2774 return Op; 2775 } else if (OpBits < DestBits) { 2776 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 2777 // bits, just sext from i32. 2778 if (NumSignBits > OpBits-MidBits) 2779 return DAG.getNode(ISD::SIGN_EXTEND, VT, Op); 2780 } else { 2781 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 2782 // bits, just truncate to i32. 2783 if (NumSignBits > OpBits-MidBits) 2784 return DAG.getNode(ISD::TRUNCATE, VT, Op); 2785 } 2786 2787 // fold (sext (truncate x)) -> (sextinreg x). 2788 if (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 2789 N0.getValueType())) { 2790 if (Op.getValueType() < VT) 2791 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2792 else if (Op.getValueType() > VT) 2793 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2794 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op, 2795 DAG.getValueType(N0.getValueType())); 2796 } 2797 } 2798 2799 // fold (sext (load x)) -> (sext (truncate (sextload x))) 2800 if (ISD::isNON_EXTLoad(N0.Val) && 2801 (!AfterLegalize||TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType()))){ 2802 bool DoXform = true; 2803 SmallVector<SDNode*, 4> SetCCs; 2804 if (!N0.hasOneUse()) 2805 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 2806 if (DoXform) { 2807 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2808 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2809 LN0->getBasePtr(), LN0->getSrcValue(), 2810 LN0->getSrcValueOffset(), 2811 N0.getValueType(), 2812 LN0->isVolatile(), 2813 LN0->getAlignment()); 2814 CombineTo(N, ExtLoad); 2815 SDOperand Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad); 2816 CombineTo(N0.Val, Trunc, ExtLoad.getValue(1)); 2817 // Extend SetCC uses if necessary. 2818 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 2819 SDNode *SetCC = SetCCs[i]; 2820 SmallVector<SDOperand, 4> Ops; 2821 for (unsigned j = 0; j != 2; ++j) { 2822 SDOperand SOp = SetCC->getOperand(j); 2823 if (SOp == Trunc) 2824 Ops.push_back(ExtLoad); 2825 else 2826 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, VT, SOp)); 2827 } 2828 Ops.push_back(SetCC->getOperand(2)); 2829 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0), 2830 &Ops[0], Ops.size())); 2831 } 2832 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2833 } 2834 } 2835 2836 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 2837 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 2838 if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && 2839 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) { 2840 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2841 MVT::ValueType EVT = LN0->getMemoryVT(); 2842 if (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) { 2843 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2844 LN0->getBasePtr(), LN0->getSrcValue(), 2845 LN0->getSrcValueOffset(), EVT, 2846 LN0->isVolatile(), 2847 LN0->getAlignment()); 2848 CombineTo(N, ExtLoad); 2849 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2850 ExtLoad.getValue(1)); 2851 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2852 } 2853 } 2854 2855 // sext(setcc x,y,cc) -> select_cc x, y, -1, 0, cc 2856 if (N0.getOpcode() == ISD::SETCC) { 2857 SDOperand SCC = 2858 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 2859 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT), 2860 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 2861 if (SCC.Val) return SCC; 2862 } 2863 2864 return SDOperand(); 2865} 2866 2867SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) { 2868 SDOperand N0 = N->getOperand(0); 2869 MVT::ValueType VT = N->getValueType(0); 2870 2871 // fold (zext c1) -> c1 2872 if (isa<ConstantSDNode>(N0)) 2873 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 2874 // fold (zext (zext x)) -> (zext x) 2875 // fold (zext (aext x)) -> (zext x) 2876 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2877 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0)); 2878 2879 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 2880 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 2881 if (N0.getOpcode() == ISD::TRUNCATE) { 2882 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2883 if (NarrowLoad.Val) { 2884 if (NarrowLoad.Val != N0.Val) 2885 CombineTo(N0.Val, NarrowLoad); 2886 return DAG.getNode(ISD::ZERO_EXTEND, VT, NarrowLoad); 2887 } 2888 } 2889 2890 // fold (zext (truncate x)) -> (and x, mask) 2891 if (N0.getOpcode() == ISD::TRUNCATE && 2892 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) { 2893 SDOperand Op = N0.getOperand(0); 2894 if (Op.getValueType() < VT) { 2895 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2896 } else if (Op.getValueType() > VT) { 2897 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2898 } 2899 return DAG.getZeroExtendInReg(Op, N0.getValueType()); 2900 } 2901 2902 // fold (zext (and (trunc x), cst)) -> (and x, cst). 2903 if (N0.getOpcode() == ISD::AND && 2904 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 2905 N0.getOperand(1).getOpcode() == ISD::Constant) { 2906 SDOperand X = N0.getOperand(0).getOperand(0); 2907 if (X.getValueType() < VT) { 2908 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 2909 } else if (X.getValueType() > VT) { 2910 X = DAG.getNode(ISD::TRUNCATE, VT, X); 2911 } 2912 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 2913 Mask.zext(MVT::getSizeInBits(VT)); 2914 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 2915 } 2916 2917 // fold (zext (load x)) -> (zext (truncate (zextload x))) 2918 if (ISD::isNON_EXTLoad(N0.Val) && 2919 (!AfterLegalize||TLI.isLoadXLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 2920 bool DoXform = true; 2921 SmallVector<SDNode*, 4> SetCCs; 2922 if (!N0.hasOneUse()) 2923 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 2924 if (DoXform) { 2925 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2926 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 2927 LN0->getBasePtr(), LN0->getSrcValue(), 2928 LN0->getSrcValueOffset(), 2929 N0.getValueType(), 2930 LN0->isVolatile(), 2931 LN0->getAlignment()); 2932 CombineTo(N, ExtLoad); 2933 SDOperand Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad); 2934 CombineTo(N0.Val, Trunc, ExtLoad.getValue(1)); 2935 // Extend SetCC uses if necessary. 2936 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 2937 SDNode *SetCC = SetCCs[i]; 2938 SmallVector<SDOperand, 4> Ops; 2939 for (unsigned j = 0; j != 2; ++j) { 2940 SDOperand SOp = SetCC->getOperand(j); 2941 if (SOp == Trunc) 2942 Ops.push_back(ExtLoad); 2943 else 2944 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, VT, SOp)); 2945 } 2946 Ops.push_back(SetCC->getOperand(2)); 2947 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0), 2948 &Ops[0], Ops.size())); 2949 } 2950 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2951 } 2952 } 2953 2954 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 2955 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 2956 if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && 2957 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) { 2958 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2959 MVT::ValueType EVT = LN0->getMemoryVT(); 2960 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 2961 LN0->getBasePtr(), LN0->getSrcValue(), 2962 LN0->getSrcValueOffset(), EVT, 2963 LN0->isVolatile(), 2964 LN0->getAlignment()); 2965 CombineTo(N, ExtLoad); 2966 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2967 ExtLoad.getValue(1)); 2968 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2969 } 2970 2971 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 2972 if (N0.getOpcode() == ISD::SETCC) { 2973 SDOperand SCC = 2974 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 2975 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 2976 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 2977 if (SCC.Val) return SCC; 2978 } 2979 2980 return SDOperand(); 2981} 2982 2983SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) { 2984 SDOperand N0 = N->getOperand(0); 2985 MVT::ValueType VT = N->getValueType(0); 2986 2987 // fold (aext c1) -> c1 2988 if (isa<ConstantSDNode>(N0)) 2989 return DAG.getNode(ISD::ANY_EXTEND, VT, N0); 2990 // fold (aext (aext x)) -> (aext x) 2991 // fold (aext (zext x)) -> (zext x) 2992 // fold (aext (sext x)) -> (sext x) 2993 if (N0.getOpcode() == ISD::ANY_EXTEND || 2994 N0.getOpcode() == ISD::ZERO_EXTEND || 2995 N0.getOpcode() == ISD::SIGN_EXTEND) 2996 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 2997 2998 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 2999 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 3000 if (N0.getOpcode() == ISD::TRUNCATE) { 3001 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 3002 if (NarrowLoad.Val) { 3003 if (NarrowLoad.Val != N0.Val) 3004 CombineTo(N0.Val, NarrowLoad); 3005 return DAG.getNode(ISD::ANY_EXTEND, VT, NarrowLoad); 3006 } 3007 } 3008 3009 // fold (aext (truncate x)) 3010 if (N0.getOpcode() == ISD::TRUNCATE) { 3011 SDOperand TruncOp = N0.getOperand(0); 3012 if (TruncOp.getValueType() == VT) 3013 return TruncOp; // x iff x size == zext size. 3014 if (TruncOp.getValueType() > VT) 3015 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp); 3016 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp); 3017 } 3018 3019 // fold (aext (and (trunc x), cst)) -> (and x, cst). 3020 if (N0.getOpcode() == ISD::AND && 3021 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3022 N0.getOperand(1).getOpcode() == ISD::Constant) { 3023 SDOperand X = N0.getOperand(0).getOperand(0); 3024 if (X.getValueType() < VT) { 3025 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 3026 } else if (X.getValueType() > VT) { 3027 X = DAG.getNode(ISD::TRUNCATE, VT, X); 3028 } 3029 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3030 Mask.zext(MVT::getSizeInBits(VT)); 3031 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 3032 } 3033 3034 // fold (aext (load x)) -> (aext (truncate (extload x))) 3035 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 3036 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) { 3037 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3038 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 3039 LN0->getBasePtr(), LN0->getSrcValue(), 3040 LN0->getSrcValueOffset(), 3041 N0.getValueType(), 3042 LN0->isVolatile(), 3043 LN0->getAlignment()); 3044 CombineTo(N, ExtLoad); 3045 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 3046 ExtLoad.getValue(1)); 3047 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3048 } 3049 3050 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 3051 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 3052 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 3053 if (N0.getOpcode() == ISD::LOAD && 3054 !ISD::isNON_EXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 3055 N0.hasOneUse()) { 3056 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3057 MVT::ValueType EVT = LN0->getMemoryVT(); 3058 SDOperand ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT, 3059 LN0->getChain(), LN0->getBasePtr(), 3060 LN0->getSrcValue(), 3061 LN0->getSrcValueOffset(), EVT, 3062 LN0->isVolatile(), 3063 LN0->getAlignment()); 3064 CombineTo(N, ExtLoad); 3065 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 3066 ExtLoad.getValue(1)); 3067 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3068 } 3069 3070 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3071 if (N0.getOpcode() == ISD::SETCC) { 3072 SDOperand SCC = 3073 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 3074 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3075 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3076 if (SCC.Val) 3077 return SCC; 3078 } 3079 3080 return SDOperand(); 3081} 3082 3083/// GetDemandedBits - See if the specified operand can be simplified with the 3084/// knowledge that only the bits specified by Mask are used. If so, return the 3085/// simpler operand, otherwise return a null SDOperand. 3086SDOperand DAGCombiner::GetDemandedBits(SDOperand V, const APInt &Mask) { 3087 switch (V.getOpcode()) { 3088 default: break; 3089 case ISD::OR: 3090 case ISD::XOR: 3091 // If the LHS or RHS don't contribute bits to the or, drop them. 3092 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 3093 return V.getOperand(1); 3094 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 3095 return V.getOperand(0); 3096 break; 3097 case ISD::SRL: 3098 // Only look at single-use SRLs. 3099 if (!V.Val->hasOneUse()) 3100 break; 3101 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 3102 // See if we can recursively simplify the LHS. 3103 unsigned Amt = RHSC->getValue(); 3104 APInt NewMask = Mask << Amt; 3105 SDOperand SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 3106 if (SimplifyLHS.Val) { 3107 return DAG.getNode(ISD::SRL, V.getValueType(), 3108 SimplifyLHS, V.getOperand(1)); 3109 } 3110 } 3111 } 3112 return SDOperand(); 3113} 3114 3115/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 3116/// bits and then truncated to a narrower type and where N is a multiple 3117/// of number of bits of the narrower type, transform it to a narrower load 3118/// from address + N / num of bits of new type. If the result is to be 3119/// extended, also fold the extension to form a extending load. 3120SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) { 3121 unsigned Opc = N->getOpcode(); 3122 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 3123 SDOperand N0 = N->getOperand(0); 3124 MVT::ValueType VT = N->getValueType(0); 3125 MVT::ValueType EVT = N->getValueType(0); 3126 3127 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then 3128 // extended to VT. 3129 if (Opc == ISD::SIGN_EXTEND_INREG) { 3130 ExtType = ISD::SEXTLOAD; 3131 EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3132 if (AfterLegalize && !TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) 3133 return SDOperand(); 3134 } 3135 3136 unsigned EVTBits = MVT::getSizeInBits(EVT); 3137 unsigned ShAmt = 0; 3138 bool CombineSRL = false; 3139 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 3140 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3141 ShAmt = N01->getValue(); 3142 // Is the shift amount a multiple of size of VT? 3143 if ((ShAmt & (EVTBits-1)) == 0) { 3144 N0 = N0.getOperand(0); 3145 if (MVT::getSizeInBits(N0.getValueType()) <= EVTBits) 3146 return SDOperand(); 3147 CombineSRL = true; 3148 } 3149 } 3150 } 3151 3152 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 3153 // Do not allow folding to i1 here. i1 is implicitly stored in memory in 3154 // zero extended form: by shrinking the load, we lose track of the fact 3155 // that it is already zero extended. 3156 // FIXME: This should be reevaluated. 3157 VT != MVT::i1) { 3158 assert(MVT::getSizeInBits(N0.getValueType()) > EVTBits && 3159 "Cannot truncate to larger type!"); 3160 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3161 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 3162 // For big endian targets, we need to adjust the offset to the pointer to 3163 // load the correct bytes. 3164 if (TLI.isBigEndian()) { 3165 unsigned LVTStoreBits = MVT::getStoreSizeInBits(N0.getValueType()); 3166 unsigned EVTStoreBits = MVT::getStoreSizeInBits(EVT); 3167 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 3168 } 3169 uint64_t PtrOff = ShAmt / 8; 3170 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 3171 SDOperand NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(), 3172 DAG.getConstant(PtrOff, PtrType)); 3173 AddToWorkList(NewPtr.Val); 3174 SDOperand Load = (ExtType == ISD::NON_EXTLOAD) 3175 ? DAG.getLoad(VT, LN0->getChain(), NewPtr, 3176 LN0->getSrcValue(), LN0->getSrcValueOffset(), 3177 LN0->isVolatile(), NewAlign) 3178 : DAG.getExtLoad(ExtType, VT, LN0->getChain(), NewPtr, 3179 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT, 3180 LN0->isVolatile(), NewAlign); 3181 AddToWorkList(N); 3182 if (CombineSRL) { 3183 WorkListRemover DeadNodes(*this); 3184 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), 3185 &DeadNodes); 3186 CombineTo(N->getOperand(0).Val, Load); 3187 } else 3188 CombineTo(N0.Val, Load, Load.getValue(1)); 3189 if (ShAmt) { 3190 if (Opc == ISD::SIGN_EXTEND_INREG) 3191 return DAG.getNode(Opc, VT, Load, N->getOperand(1)); 3192 else 3193 return DAG.getNode(Opc, VT, Load); 3194 } 3195 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3196 } 3197 3198 return SDOperand(); 3199} 3200 3201 3202SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 3203 SDOperand N0 = N->getOperand(0); 3204 SDOperand N1 = N->getOperand(1); 3205 MVT::ValueType VT = N->getValueType(0); 3206 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT(); 3207 unsigned VTBits = MVT::getSizeInBits(VT); 3208 unsigned EVTBits = MVT::getSizeInBits(EVT); 3209 3210 // fold (sext_in_reg c1) -> c1 3211 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 3212 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1); 3213 3214 // If the input is already sign extended, just drop the extension. 3215 if (DAG.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1) 3216 return N0; 3217 3218 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 3219 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 3220 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) { 3221 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); 3222 } 3223 3224 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 3225 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 3226 return DAG.getZeroExtendInReg(N0, EVT); 3227 3228 // fold operands of sext_in_reg based on knowledge that the top bits are not 3229 // demanded. 3230 if (SimplifyDemandedBits(SDOperand(N, 0))) 3231 return SDOperand(N, 0); 3232 3233 // fold (sext_in_reg (load x)) -> (smaller sextload x) 3234 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 3235 SDOperand NarrowLoad = ReduceLoadWidth(N); 3236 if (NarrowLoad.Val) 3237 return NarrowLoad; 3238 3239 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24 3240 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible. 3241 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 3242 if (N0.getOpcode() == ISD::SRL) { 3243 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 3244 if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) { 3245 // We can turn this into an SRA iff the input to the SRL is already sign 3246 // extended enough. 3247 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 3248 if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits) 3249 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1)); 3250 } 3251 } 3252 3253 // fold (sext_inreg (extload x)) -> (sextload x) 3254 if (ISD::isEXTLoad(N0.Val) && 3255 ISD::isUNINDEXEDLoad(N0.Val) && 3256 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3257 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) { 3258 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3259 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 3260 LN0->getBasePtr(), LN0->getSrcValue(), 3261 LN0->getSrcValueOffset(), EVT, 3262 LN0->isVolatile(), 3263 LN0->getAlignment()); 3264 CombineTo(N, ExtLoad); 3265 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 3266 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3267 } 3268 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 3269 if (ISD::isZEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 3270 N0.hasOneUse() && 3271 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3272 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) { 3273 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3274 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 3275 LN0->getBasePtr(), LN0->getSrcValue(), 3276 LN0->getSrcValueOffset(), EVT, 3277 LN0->isVolatile(), 3278 LN0->getAlignment()); 3279 CombineTo(N, ExtLoad); 3280 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 3281 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3282 } 3283 return SDOperand(); 3284} 3285 3286SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) { 3287 SDOperand N0 = N->getOperand(0); 3288 MVT::ValueType VT = N->getValueType(0); 3289 3290 // noop truncate 3291 if (N0.getValueType() == N->getValueType(0)) 3292 return N0; 3293 // fold (truncate c1) -> c1 3294 if (isa<ConstantSDNode>(N0)) 3295 return DAG.getNode(ISD::TRUNCATE, VT, N0); 3296 // fold (truncate (truncate x)) -> (truncate x) 3297 if (N0.getOpcode() == ISD::TRUNCATE) 3298 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 3299 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 3300 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| 3301 N0.getOpcode() == ISD::ANY_EXTEND) { 3302 if (N0.getOperand(0).getValueType() < VT) 3303 // if the source is smaller than the dest, we still need an extend 3304 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 3305 else if (N0.getOperand(0).getValueType() > VT) 3306 // if the source is larger than the dest, than we just need the truncate 3307 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 3308 else 3309 // if the source and dest are the same type, we can drop both the extend 3310 // and the truncate 3311 return N0.getOperand(0); 3312 } 3313 3314 // See if we can simplify the input to this truncate through knowledge that 3315 // only the low bits are being used. For example "trunc (or (shl x, 8), y)" 3316 // -> trunc y 3317 SDOperand Shorter = 3318 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 3319 MVT::getSizeInBits(VT))); 3320 if (Shorter.Val) 3321 return DAG.getNode(ISD::TRUNCATE, VT, Shorter); 3322 3323 // fold (truncate (load x)) -> (smaller load x) 3324 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 3325 return ReduceLoadWidth(N); 3326} 3327 3328SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) { 3329 SDOperand N0 = N->getOperand(0); 3330 MVT::ValueType VT = N->getValueType(0); 3331 3332 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 3333 // Only do this before legalize, since afterward the target may be depending 3334 // on the bitconvert. 3335 // First check to see if this is all constant. 3336 if (!AfterLegalize && 3337 N0.getOpcode() == ISD::BUILD_VECTOR && N0.Val->hasOneUse() && 3338 MVT::isVector(VT)) { 3339 bool isSimple = true; 3340 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 3341 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 3342 N0.getOperand(i).getOpcode() != ISD::Constant && 3343 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 3344 isSimple = false; 3345 break; 3346 } 3347 3348 MVT::ValueType DestEltVT = MVT::getVectorElementType(N->getValueType(0)); 3349 assert(!MVT::isVector(DestEltVT) && 3350 "Element type of vector ValueType must not be vector!"); 3351 if (isSimple) { 3352 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.Val, DestEltVT); 3353 } 3354 } 3355 3356 // If the input is a constant, let getNode() fold it. 3357 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 3358 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0); 3359 if (Res.Val != N) return Res; 3360 } 3361 3362 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2) 3363 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3364 3365 // fold (conv (load x)) -> (load (conv*)x) 3366 // If the resultant load doesn't need a higher alignment than the original! 3367 if (ISD::isNormalLoad(N0.Val) && N0.hasOneUse() && 3368 TLI.isOperationLegal(ISD::LOAD, VT)) { 3369 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3370 unsigned Align = TLI.getTargetMachine().getTargetData()-> 3371 getABITypeAlignment(MVT::getTypeForValueType(VT)); 3372 unsigned OrigAlign = LN0->getAlignment(); 3373 if (Align <= OrigAlign) { 3374 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(), 3375 LN0->getSrcValue(), LN0->getSrcValueOffset(), 3376 LN0->isVolatile(), Align); 3377 AddToWorkList(N); 3378 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load), 3379 Load.getValue(1)); 3380 return Load; 3381 } 3382 } 3383 3384 // Fold bitconvert(fneg(x)) -> xor(bitconvert(x), signbit) 3385 // Fold bitconvert(fabs(x)) -> and(bitconvert(x), ~signbit) 3386 // This often reduces constant pool loads. 3387 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && 3388 N0.Val->hasOneUse() && MVT::isInteger(VT) && !MVT::isVector(VT)) { 3389 SDOperand NewConv = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3390 AddToWorkList(NewConv.Val); 3391 3392 APInt SignBit = APInt::getSignBit(MVT::getSizeInBits(VT)); 3393 if (N0.getOpcode() == ISD::FNEG) 3394 return DAG.getNode(ISD::XOR, VT, NewConv, DAG.getConstant(SignBit, VT)); 3395 assert(N0.getOpcode() == ISD::FABS); 3396 return DAG.getNode(ISD::AND, VT, NewConv, DAG.getConstant(~SignBit, VT)); 3397 } 3398 3399 // Fold bitconvert(fcopysign(cst, x)) -> bitconvert(x)&sign | cst&~sign' 3400 // Note that we don't handle copysign(x,cst) because this can always be folded 3401 // to an fneg or fabs. 3402 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse() && 3403 isa<ConstantFPSDNode>(N0.getOperand(0)) && 3404 MVT::isInteger(VT) && !MVT::isVector(VT)) { 3405 unsigned OrigXWidth = MVT::getSizeInBits(N0.getOperand(1).getValueType()); 3406 SDOperand X = DAG.getNode(ISD::BIT_CONVERT, MVT::getIntegerType(OrigXWidth), 3407 N0.getOperand(1)); 3408 AddToWorkList(X.Val); 3409 3410 // If X has a different width than the result/lhs, sext it or truncate it. 3411 unsigned VTWidth = MVT::getSizeInBits(VT); 3412 if (OrigXWidth < VTWidth) { 3413 X = DAG.getNode(ISD::SIGN_EXTEND, VT, X); 3414 AddToWorkList(X.Val); 3415 } else if (OrigXWidth > VTWidth) { 3416 // To get the sign bit in the right place, we have to shift it right 3417 // before truncating. 3418 X = DAG.getNode(ISD::SRL, X.getValueType(), X, 3419 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 3420 AddToWorkList(X.Val); 3421 X = DAG.getNode(ISD::TRUNCATE, VT, X); 3422 AddToWorkList(X.Val); 3423 } 3424 3425 APInt SignBit = APInt::getSignBit(MVT::getSizeInBits(VT)); 3426 X = DAG.getNode(ISD::AND, VT, X, DAG.getConstant(SignBit, VT)); 3427 AddToWorkList(X.Val); 3428 3429 SDOperand Cst = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3430 Cst = DAG.getNode(ISD::AND, VT, Cst, DAG.getConstant(~SignBit, VT)); 3431 AddToWorkList(Cst.Val); 3432 3433 return DAG.getNode(ISD::OR, VT, X, Cst); 3434 } 3435 3436 return SDOperand(); 3437} 3438 3439/// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector 3440/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 3441/// destination element value type. 3442SDOperand DAGCombiner:: 3443ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) { 3444 MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType(); 3445 3446 // If this is already the right type, we're done. 3447 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0); 3448 3449 unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT); 3450 unsigned DstBitSize = MVT::getSizeInBits(DstEltVT); 3451 3452 // If this is a conversion of N elements of one type to N elements of another 3453 // type, convert each element. This handles FP<->INT cases. 3454 if (SrcBitSize == DstBitSize) { 3455 SmallVector<SDOperand, 8> Ops; 3456 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3457 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i))); 3458 AddToWorkList(Ops.back().Val); 3459 } 3460 MVT::ValueType VT = 3461 MVT::getVectorType(DstEltVT, 3462 MVT::getVectorNumElements(BV->getValueType(0))); 3463 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3464 } 3465 3466 // Otherwise, we're growing or shrinking the elements. To avoid having to 3467 // handle annoying details of growing/shrinking FP values, we convert them to 3468 // int first. 3469 if (MVT::isFloatingPoint(SrcEltVT)) { 3470 // Convert the input float vector to a int vector where the elements are the 3471 // same sizes. 3472 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 3473 MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 3474 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).Val; 3475 SrcEltVT = IntVT; 3476 } 3477 3478 // Now we know the input is an integer vector. If the output is a FP type, 3479 // convert to integer first, then to FP of the right size. 3480 if (MVT::isFloatingPoint(DstEltVT)) { 3481 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 3482 MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 3483 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).Val; 3484 3485 // Next, convert to FP elements of the same size. 3486 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT); 3487 } 3488 3489 // Okay, we know the src/dst types are both integers of differing types. 3490 // Handling growing first. 3491 assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT)); 3492 if (SrcBitSize < DstBitSize) { 3493 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 3494 3495 SmallVector<SDOperand, 8> Ops; 3496 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 3497 i += NumInputsPerOutput) { 3498 bool isLE = TLI.isLittleEndian(); 3499 APInt NewBits = APInt(DstBitSize, 0); 3500 bool EltIsUndef = true; 3501 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 3502 // Shift the previously computed bits over. 3503 NewBits <<= SrcBitSize; 3504 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 3505 if (Op.getOpcode() == ISD::UNDEF) continue; 3506 EltIsUndef = false; 3507 3508 NewBits |= 3509 APInt(cast<ConstantSDNode>(Op)->getAPIntValue()).zext(DstBitSize); 3510 } 3511 3512 if (EltIsUndef) 3513 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 3514 else 3515 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 3516 } 3517 3518 MVT::ValueType VT = MVT::getVectorType(DstEltVT, Ops.size()); 3519 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3520 } 3521 3522 // Finally, this must be the case where we are shrinking elements: each input 3523 // turns into multiple outputs. 3524 bool isS2V = ISD::isScalarToVector(BV); 3525 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 3526 MVT::ValueType VT = MVT::getVectorType(DstEltVT, 3527 NumOutputsPerInput * BV->getNumOperands()); 3528 SmallVector<SDOperand, 8> Ops; 3529 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3530 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 3531 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 3532 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 3533 continue; 3534 } 3535 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getAPIntValue(); 3536 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 3537 APInt ThisVal = APInt(OpVal).trunc(DstBitSize); 3538 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 3539 if (isS2V && i == 0 && j == 0 && APInt(ThisVal).zext(SrcBitSize) == OpVal) 3540 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 3541 return DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Ops[0]); 3542 OpVal = OpVal.lshr(DstBitSize); 3543 } 3544 3545 // For big endian targets, swap the order of the pieces of each element. 3546 if (TLI.isBigEndian()) 3547 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 3548 } 3549 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3550} 3551 3552 3553 3554SDOperand DAGCombiner::visitFADD(SDNode *N) { 3555 SDOperand N0 = N->getOperand(0); 3556 SDOperand N1 = N->getOperand(1); 3557 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3558 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3559 MVT::ValueType VT = N->getValueType(0); 3560 3561 // fold vector ops 3562 if (MVT::isVector(VT)) { 3563 SDOperand FoldedVOp = SimplifyVBinOp(N); 3564 if (FoldedVOp.Val) return FoldedVOp; 3565 } 3566 3567 // fold (fadd c1, c2) -> c1+c2 3568 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3569 return DAG.getNode(ISD::FADD, VT, N0, N1); 3570 // canonicalize constant to RHS 3571 if (N0CFP && !N1CFP) 3572 return DAG.getNode(ISD::FADD, VT, N1, N0); 3573 // fold (A + (-B)) -> A-B 3574 if (isNegatibleForFree(N1, AfterLegalize) == 2) 3575 return DAG.getNode(ISD::FSUB, VT, N0, 3576 GetNegatedExpression(N1, DAG, AfterLegalize)); 3577 // fold ((-A) + B) -> B-A 3578 if (isNegatibleForFree(N0, AfterLegalize) == 2) 3579 return DAG.getNode(ISD::FSUB, VT, N1, 3580 GetNegatedExpression(N0, DAG, AfterLegalize)); 3581 3582 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 3583 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 3584 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3585 return DAG.getNode(ISD::FADD, VT, N0.getOperand(0), 3586 DAG.getNode(ISD::FADD, VT, N0.getOperand(1), N1)); 3587 3588 return SDOperand(); 3589} 3590 3591SDOperand DAGCombiner::visitFSUB(SDNode *N) { 3592 SDOperand N0 = N->getOperand(0); 3593 SDOperand N1 = N->getOperand(1); 3594 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3595 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3596 MVT::ValueType VT = N->getValueType(0); 3597 3598 // fold vector ops 3599 if (MVT::isVector(VT)) { 3600 SDOperand FoldedVOp = SimplifyVBinOp(N); 3601 if (FoldedVOp.Val) return FoldedVOp; 3602 } 3603 3604 // fold (fsub c1, c2) -> c1-c2 3605 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3606 return DAG.getNode(ISD::FSUB, VT, N0, N1); 3607 // fold (0-B) -> -B 3608 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { 3609 if (isNegatibleForFree(N1, AfterLegalize)) 3610 return GetNegatedExpression(N1, DAG, AfterLegalize); 3611 return DAG.getNode(ISD::FNEG, VT, N1); 3612 } 3613 // fold (A-(-B)) -> A+B 3614 if (isNegatibleForFree(N1, AfterLegalize)) 3615 return DAG.getNode(ISD::FADD, VT, N0, 3616 GetNegatedExpression(N1, DAG, AfterLegalize)); 3617 3618 return SDOperand(); 3619} 3620 3621SDOperand DAGCombiner::visitFMUL(SDNode *N) { 3622 SDOperand N0 = N->getOperand(0); 3623 SDOperand N1 = N->getOperand(1); 3624 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3625 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3626 MVT::ValueType VT = N->getValueType(0); 3627 3628 // fold vector ops 3629 if (MVT::isVector(VT)) { 3630 SDOperand FoldedVOp = SimplifyVBinOp(N); 3631 if (FoldedVOp.Val) return FoldedVOp; 3632 } 3633 3634 // fold (fmul c1, c2) -> c1*c2 3635 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3636 return DAG.getNode(ISD::FMUL, VT, N0, N1); 3637 // canonicalize constant to RHS 3638 if (N0CFP && !N1CFP) 3639 return DAG.getNode(ISD::FMUL, VT, N1, N0); 3640 // fold (fmul X, 2.0) -> (fadd X, X) 3641 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 3642 return DAG.getNode(ISD::FADD, VT, N0, N0); 3643 // fold (fmul X, -1.0) -> (fneg X) 3644 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 3645 return DAG.getNode(ISD::FNEG, VT, N0); 3646 3647 // -X * -Y -> X*Y 3648 if (char LHSNeg = isNegatibleForFree(N0, AfterLegalize)) { 3649 if (char RHSNeg = isNegatibleForFree(N1, AfterLegalize)) { 3650 // Both can be negated for free, check to see if at least one is cheaper 3651 // negated. 3652 if (LHSNeg == 2 || RHSNeg == 2) 3653 return DAG.getNode(ISD::FMUL, VT, 3654 GetNegatedExpression(N0, DAG, AfterLegalize), 3655 GetNegatedExpression(N1, DAG, AfterLegalize)); 3656 } 3657 } 3658 3659 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 3660 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 3661 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3662 return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0), 3663 DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1)); 3664 3665 return SDOperand(); 3666} 3667 3668SDOperand DAGCombiner::visitFDIV(SDNode *N) { 3669 SDOperand N0 = N->getOperand(0); 3670 SDOperand N1 = N->getOperand(1); 3671 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3672 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3673 MVT::ValueType VT = N->getValueType(0); 3674 3675 // fold vector ops 3676 if (MVT::isVector(VT)) { 3677 SDOperand FoldedVOp = SimplifyVBinOp(N); 3678 if (FoldedVOp.Val) return FoldedVOp; 3679 } 3680 3681 // fold (fdiv c1, c2) -> c1/c2 3682 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3683 return DAG.getNode(ISD::FDIV, VT, N0, N1); 3684 3685 3686 // -X / -Y -> X*Y 3687 if (char LHSNeg = isNegatibleForFree(N0, AfterLegalize)) { 3688 if (char RHSNeg = isNegatibleForFree(N1, AfterLegalize)) { 3689 // Both can be negated for free, check to see if at least one is cheaper 3690 // negated. 3691 if (LHSNeg == 2 || RHSNeg == 2) 3692 return DAG.getNode(ISD::FDIV, VT, 3693 GetNegatedExpression(N0, DAG, AfterLegalize), 3694 GetNegatedExpression(N1, DAG, AfterLegalize)); 3695 } 3696 } 3697 3698 return SDOperand(); 3699} 3700 3701SDOperand DAGCombiner::visitFREM(SDNode *N) { 3702 SDOperand N0 = N->getOperand(0); 3703 SDOperand N1 = N->getOperand(1); 3704 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3705 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3706 MVT::ValueType VT = N->getValueType(0); 3707 3708 // fold (frem c1, c2) -> fmod(c1,c2) 3709 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3710 return DAG.getNode(ISD::FREM, VT, N0, N1); 3711 3712 return SDOperand(); 3713} 3714 3715SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) { 3716 SDOperand N0 = N->getOperand(0); 3717 SDOperand N1 = N->getOperand(1); 3718 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3719 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3720 MVT::ValueType VT = N->getValueType(0); 3721 3722 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 3723 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1); 3724 3725 if (N1CFP) { 3726 const APFloat& V = N1CFP->getValueAPF(); 3727 // copysign(x, c1) -> fabs(x) iff ispos(c1) 3728 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 3729 if (!V.isNegative()) 3730 return DAG.getNode(ISD::FABS, VT, N0); 3731 else 3732 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0)); 3733 } 3734 3735 // copysign(fabs(x), y) -> copysign(x, y) 3736 // copysign(fneg(x), y) -> copysign(x, y) 3737 // copysign(copysign(x,z), y) -> copysign(x, y) 3738 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 3739 N0.getOpcode() == ISD::FCOPYSIGN) 3740 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1); 3741 3742 // copysign(x, abs(y)) -> abs(x) 3743 if (N1.getOpcode() == ISD::FABS) 3744 return DAG.getNode(ISD::FABS, VT, N0); 3745 3746 // copysign(x, copysign(y,z)) -> copysign(x, z) 3747 if (N1.getOpcode() == ISD::FCOPYSIGN) 3748 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1)); 3749 3750 // copysign(x, fp_extend(y)) -> copysign(x, y) 3751 // copysign(x, fp_round(y)) -> copysign(x, y) 3752 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 3753 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0)); 3754 3755 return SDOperand(); 3756} 3757 3758 3759 3760SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) { 3761 SDOperand N0 = N->getOperand(0); 3762 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3763 MVT::ValueType VT = N->getValueType(0); 3764 3765 // fold (sint_to_fp c1) -> c1fp 3766 if (N0C && N0.getValueType() != MVT::ppcf128) 3767 return DAG.getNode(ISD::SINT_TO_FP, VT, N0); 3768 return SDOperand(); 3769} 3770 3771SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) { 3772 SDOperand N0 = N->getOperand(0); 3773 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3774 MVT::ValueType VT = N->getValueType(0); 3775 3776 // fold (uint_to_fp c1) -> c1fp 3777 if (N0C && N0.getValueType() != MVT::ppcf128) 3778 return DAG.getNode(ISD::UINT_TO_FP, VT, N0); 3779 return SDOperand(); 3780} 3781 3782SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) { 3783 SDOperand N0 = N->getOperand(0); 3784 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3785 MVT::ValueType VT = N->getValueType(0); 3786 3787 // fold (fp_to_sint c1fp) -> c1 3788 if (N0CFP) 3789 return DAG.getNode(ISD::FP_TO_SINT, VT, N0); 3790 return SDOperand(); 3791} 3792 3793SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) { 3794 SDOperand N0 = N->getOperand(0); 3795 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3796 MVT::ValueType VT = N->getValueType(0); 3797 3798 // fold (fp_to_uint c1fp) -> c1 3799 if (N0CFP && VT != MVT::ppcf128) 3800 return DAG.getNode(ISD::FP_TO_UINT, VT, N0); 3801 return SDOperand(); 3802} 3803 3804SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) { 3805 SDOperand N0 = N->getOperand(0); 3806 SDOperand N1 = N->getOperand(1); 3807 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3808 MVT::ValueType VT = N->getValueType(0); 3809 3810 // fold (fp_round c1fp) -> c1fp 3811 if (N0CFP && N0.getValueType() != MVT::ppcf128) 3812 return DAG.getNode(ISD::FP_ROUND, VT, N0, N1); 3813 3814 // fold (fp_round (fp_extend x)) -> x 3815 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 3816 return N0.getOperand(0); 3817 3818 // fold (fp_round (fp_round x)) -> (fp_round x) 3819 if (N0.getOpcode() == ISD::FP_ROUND) { 3820 // This is a value preserving truncation if both round's are. 3821 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 3822 N0.Val->getConstantOperandVal(1) == 1; 3823 return DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0), 3824 DAG.getIntPtrConstant(IsTrunc)); 3825 } 3826 3827 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 3828 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) { 3829 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0), N1); 3830 AddToWorkList(Tmp.Val); 3831 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1)); 3832 } 3833 3834 return SDOperand(); 3835} 3836 3837SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 3838 SDOperand N0 = N->getOperand(0); 3839 MVT::ValueType VT = N->getValueType(0); 3840 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3841 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3842 3843 // fold (fp_round_inreg c1fp) -> c1fp 3844 if (N0CFP) { 3845 SDOperand Round = DAG.getConstantFP(N0CFP->getValueAPF(), EVT); 3846 return DAG.getNode(ISD::FP_EXTEND, VT, Round); 3847 } 3848 return SDOperand(); 3849} 3850 3851SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) { 3852 SDOperand N0 = N->getOperand(0); 3853 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3854 MVT::ValueType VT = N->getValueType(0); 3855 3856 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 3857 if (N->hasOneUse() && (*N->use_begin())->getOpcode() == ISD::FP_ROUND) 3858 return SDOperand(); 3859 3860 // fold (fp_extend c1fp) -> c1fp 3861 if (N0CFP && VT != MVT::ppcf128) 3862 return DAG.getNode(ISD::FP_EXTEND, VT, N0); 3863 3864 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 3865 // value of X. 3866 if (N0.getOpcode() == ISD::FP_ROUND && N0.Val->getConstantOperandVal(1) == 1){ 3867 SDOperand In = N0.getOperand(0); 3868 if (In.getValueType() == VT) return In; 3869 if (VT < In.getValueType()) 3870 return DAG.getNode(ISD::FP_ROUND, VT, In, N0.getOperand(1)); 3871 return DAG.getNode(ISD::FP_EXTEND, VT, In); 3872 } 3873 3874 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 3875 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 3876 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) { 3877 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3878 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 3879 LN0->getBasePtr(), LN0->getSrcValue(), 3880 LN0->getSrcValueOffset(), 3881 N0.getValueType(), 3882 LN0->isVolatile(), 3883 LN0->getAlignment()); 3884 CombineTo(N, ExtLoad); 3885 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad, 3886 DAG.getIntPtrConstant(1)), 3887 ExtLoad.getValue(1)); 3888 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3889 } 3890 3891 3892 return SDOperand(); 3893} 3894 3895SDOperand DAGCombiner::visitFNEG(SDNode *N) { 3896 SDOperand N0 = N->getOperand(0); 3897 3898 if (isNegatibleForFree(N0, AfterLegalize)) 3899 return GetNegatedExpression(N0, DAG, AfterLegalize); 3900 3901 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 3902 // constant pool values. 3903 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.Val->hasOneUse() && 3904 MVT::isInteger(N0.getOperand(0).getValueType()) && 3905 !MVT::isVector(N0.getOperand(0).getValueType())) { 3906 SDOperand Int = N0.getOperand(0); 3907 MVT::ValueType IntVT = Int.getValueType(); 3908 if (MVT::isInteger(IntVT) && !MVT::isVector(IntVT)) { 3909 Int = DAG.getNode(ISD::XOR, IntVT, Int, 3910 DAG.getConstant(MVT::getIntVTSignBit(IntVT), IntVT)); 3911 AddToWorkList(Int.Val); 3912 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int); 3913 } 3914 } 3915 3916 return SDOperand(); 3917} 3918 3919SDOperand DAGCombiner::visitFABS(SDNode *N) { 3920 SDOperand N0 = N->getOperand(0); 3921 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3922 MVT::ValueType VT = N->getValueType(0); 3923 3924 // fold (fabs c1) -> fabs(c1) 3925 if (N0CFP && VT != MVT::ppcf128) 3926 return DAG.getNode(ISD::FABS, VT, N0); 3927 // fold (fabs (fabs x)) -> (fabs x) 3928 if (N0.getOpcode() == ISD::FABS) 3929 return N->getOperand(0); 3930 // fold (fabs (fneg x)) -> (fabs x) 3931 // fold (fabs (fcopysign x, y)) -> (fabs x) 3932 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 3933 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0)); 3934 3935 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 3936 // constant pool values. 3937 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.Val->hasOneUse() && 3938 MVT::isInteger(N0.getOperand(0).getValueType()) && 3939 !MVT::isVector(N0.getOperand(0).getValueType())) { 3940 SDOperand Int = N0.getOperand(0); 3941 MVT::ValueType IntVT = Int.getValueType(); 3942 if (MVT::isInteger(IntVT) && !MVT::isVector(IntVT)) { 3943 Int = DAG.getNode(ISD::AND, IntVT, Int, 3944 DAG.getConstant(~MVT::getIntVTSignBit(IntVT), IntVT)); 3945 AddToWorkList(Int.Val); 3946 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int); 3947 } 3948 } 3949 3950 return SDOperand(); 3951} 3952 3953SDOperand DAGCombiner::visitBRCOND(SDNode *N) { 3954 SDOperand Chain = N->getOperand(0); 3955 SDOperand N1 = N->getOperand(1); 3956 SDOperand N2 = N->getOperand(2); 3957 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3958 3959 // never taken branch, fold to chain 3960 if (N1C && N1C->isNullValue()) 3961 return Chain; 3962 // unconditional branch 3963 if (N1C && N1C->getAPIntValue() == 1) 3964 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 3965 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 3966 // on the target. 3967 if (N1.getOpcode() == ISD::SETCC && 3968 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) { 3969 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2), 3970 N1.getOperand(0), N1.getOperand(1), N2); 3971 } 3972 return SDOperand(); 3973} 3974 3975// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 3976// 3977SDOperand DAGCombiner::visitBR_CC(SDNode *N) { 3978 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 3979 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 3980 3981 // Use SimplifySetCC to simplify SETCC's. 3982 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false); 3983 if (Simp.Val) AddToWorkList(Simp.Val); 3984 3985 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val); 3986 3987 // fold br_cc true, dest -> br dest (unconditional branch) 3988 if (SCCC && !SCCC->isNullValue()) 3989 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0), 3990 N->getOperand(4)); 3991 // fold br_cc false, dest -> unconditional fall through 3992 if (SCCC && SCCC->isNullValue()) 3993 return N->getOperand(0); 3994 3995 // fold to a simpler setcc 3996 if (Simp.Val && Simp.getOpcode() == ISD::SETCC) 3997 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0), 3998 Simp.getOperand(2), Simp.getOperand(0), 3999 Simp.getOperand(1), N->getOperand(4)); 4000 return SDOperand(); 4001} 4002 4003 4004/// CombineToPreIndexedLoadStore - Try turning a load / store and a 4005/// pre-indexed load / store when the base pointer is a add or subtract 4006/// and it has other uses besides the load / store. After the 4007/// transformation, the new indexed load / store has effectively folded 4008/// the add / subtract in and all of its other uses are redirected to the 4009/// new load / store. 4010bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 4011 if (!AfterLegalize) 4012 return false; 4013 4014 bool isLoad = true; 4015 SDOperand Ptr; 4016 MVT::ValueType VT; 4017 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4018 if (LD->isIndexed()) 4019 return false; 4020 VT = LD->getMemoryVT(); 4021 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 4022 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 4023 return false; 4024 Ptr = LD->getBasePtr(); 4025 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4026 if (ST->isIndexed()) 4027 return false; 4028 VT = ST->getMemoryVT(); 4029 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 4030 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 4031 return false; 4032 Ptr = ST->getBasePtr(); 4033 isLoad = false; 4034 } else 4035 return false; 4036 4037 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 4038 // out. There is no reason to make this a preinc/predec. 4039 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 4040 Ptr.Val->hasOneUse()) 4041 return false; 4042 4043 // Ask the target to do addressing mode selection. 4044 SDOperand BasePtr; 4045 SDOperand Offset; 4046 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4047 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 4048 return false; 4049 // Don't create a indexed load / store with zero offset. 4050 if (isa<ConstantSDNode>(Offset) && 4051 cast<ConstantSDNode>(Offset)->isNullValue()) 4052 return false; 4053 4054 // Try turning it into a pre-indexed load / store except when: 4055 // 1) The new base ptr is a frame index. 4056 // 2) If N is a store and the new base ptr is either the same as or is a 4057 // predecessor of the value being stored. 4058 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 4059 // that would create a cycle. 4060 // 4) All uses are load / store ops that use it as old base ptr. 4061 4062 // Check #1. Preinc'ing a frame index would require copying the stack pointer 4063 // (plus the implicit offset) to a register to preinc anyway. 4064 if (isa<FrameIndexSDNode>(BasePtr)) 4065 return false; 4066 4067 // Check #2. 4068 if (!isLoad) { 4069 SDOperand Val = cast<StoreSDNode>(N)->getValue(); 4070 if (Val == BasePtr || BasePtr.Val->isPredecessorOf(Val.Val)) 4071 return false; 4072 } 4073 4074 // Now check for #3 and #4. 4075 bool RealUse = false; 4076 for (SDNode::use_iterator I = Ptr.Val->use_begin(), 4077 E = Ptr.Val->use_end(); I != E; ++I) { 4078 SDNode *Use = *I; 4079 if (Use == N) 4080 continue; 4081 if (Use->isPredecessorOf(N)) 4082 return false; 4083 4084 if (!((Use->getOpcode() == ISD::LOAD && 4085 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 4086 (Use->getOpcode() == ISD::STORE && 4087 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))) 4088 RealUse = true; 4089 } 4090 if (!RealUse) 4091 return false; 4092 4093 SDOperand Result; 4094 if (isLoad) 4095 Result = DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM); 4096 else 4097 Result = DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM); 4098 ++PreIndexedNodes; 4099 ++NodesCombined; 4100 DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG)); 4101 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG)); 4102 DOUT << '\n'; 4103 WorkListRemover DeadNodes(*this); 4104 if (isLoad) { 4105 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0), 4106 &DeadNodes); 4107 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2), 4108 &DeadNodes); 4109 } else { 4110 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1), 4111 &DeadNodes); 4112 } 4113 4114 // Finally, since the node is now dead, remove it from the graph. 4115 DAG.DeleteNode(N); 4116 4117 // Replace the uses of Ptr with uses of the updated base value. 4118 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 4119 &DeadNodes); 4120 removeFromWorkList(Ptr.Val); 4121 DAG.DeleteNode(Ptr.Val); 4122 4123 return true; 4124} 4125 4126/// CombineToPostIndexedLoadStore - Try combine a load / store with a 4127/// add / sub of the base pointer node into a post-indexed load / store. 4128/// The transformation folded the add / subtract into the new indexed 4129/// load / store effectively and all of its uses are redirected to the 4130/// new load / store. 4131bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 4132 if (!AfterLegalize) 4133 return false; 4134 4135 bool isLoad = true; 4136 SDOperand Ptr; 4137 MVT::ValueType VT; 4138 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4139 if (LD->isIndexed()) 4140 return false; 4141 VT = LD->getMemoryVT(); 4142 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 4143 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 4144 return false; 4145 Ptr = LD->getBasePtr(); 4146 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4147 if (ST->isIndexed()) 4148 return false; 4149 VT = ST->getMemoryVT(); 4150 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 4151 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 4152 return false; 4153 Ptr = ST->getBasePtr(); 4154 isLoad = false; 4155 } else 4156 return false; 4157 4158 if (Ptr.Val->hasOneUse()) 4159 return false; 4160 4161 for (SDNode::use_iterator I = Ptr.Val->use_begin(), 4162 E = Ptr.Val->use_end(); I != E; ++I) { 4163 SDNode *Op = *I; 4164 if (Op == N || 4165 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 4166 continue; 4167 4168 SDOperand BasePtr; 4169 SDOperand Offset; 4170 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4171 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 4172 if (Ptr == Offset) 4173 std::swap(BasePtr, Offset); 4174 if (Ptr != BasePtr) 4175 continue; 4176 // Don't create a indexed load / store with zero offset. 4177 if (isa<ConstantSDNode>(Offset) && 4178 cast<ConstantSDNode>(Offset)->isNullValue()) 4179 continue; 4180 4181 // Try turning it into a post-indexed load / store except when 4182 // 1) All uses are load / store ops that use it as base ptr. 4183 // 2) Op must be independent of N, i.e. Op is neither a predecessor 4184 // nor a successor of N. Otherwise, if Op is folded that would 4185 // create a cycle. 4186 4187 // Check for #1. 4188 bool TryNext = false; 4189 for (SDNode::use_iterator II = BasePtr.Val->use_begin(), 4190 EE = BasePtr.Val->use_end(); II != EE; ++II) { 4191 SDNode *Use = *II; 4192 if (Use == Ptr.Val) 4193 continue; 4194 4195 // If all the uses are load / store addresses, then don't do the 4196 // transformation. 4197 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 4198 bool RealUse = false; 4199 for (SDNode::use_iterator III = Use->use_begin(), 4200 EEE = Use->use_end(); III != EEE; ++III) { 4201 SDNode *UseUse = *III; 4202 if (!((UseUse->getOpcode() == ISD::LOAD && 4203 cast<LoadSDNode>(UseUse)->getBasePtr().Val == Use) || 4204 (UseUse->getOpcode() == ISD::STORE && 4205 cast<StoreSDNode>(UseUse)->getBasePtr().Val == Use))) 4206 RealUse = true; 4207 } 4208 4209 if (!RealUse) { 4210 TryNext = true; 4211 break; 4212 } 4213 } 4214 } 4215 if (TryNext) 4216 continue; 4217 4218 // Check for #2 4219 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 4220 SDOperand Result = isLoad 4221 ? DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM) 4222 : DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM); 4223 ++PostIndexedNodes; 4224 ++NodesCombined; 4225 DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG)); 4226 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG)); 4227 DOUT << '\n'; 4228 WorkListRemover DeadNodes(*this); 4229 if (isLoad) { 4230 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0), 4231 &DeadNodes); 4232 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2), 4233 &DeadNodes); 4234 } else { 4235 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1), 4236 &DeadNodes); 4237 } 4238 4239 // Finally, since the node is now dead, remove it from the graph. 4240 DAG.DeleteNode(N); 4241 4242 // Replace the uses of Use with uses of the updated base value. 4243 DAG.ReplaceAllUsesOfValueWith(SDOperand(Op, 0), 4244 Result.getValue(isLoad ? 1 : 0), 4245 &DeadNodes); 4246 removeFromWorkList(Op); 4247 DAG.DeleteNode(Op); 4248 return true; 4249 } 4250 } 4251 } 4252 return false; 4253} 4254 4255/// InferAlignment - If we can infer some alignment information from this 4256/// pointer, return it. 4257static unsigned InferAlignment(SDOperand Ptr, SelectionDAG &DAG) { 4258 // If this is a direct reference to a stack slot, use information about the 4259 // stack slot's alignment. 4260 int FrameIdx = 1 << 31; 4261 int64_t FrameOffset = 0; 4262 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Ptr)) { 4263 FrameIdx = FI->getIndex(); 4264 } else if (Ptr.getOpcode() == ISD::ADD && 4265 isa<ConstantSDNode>(Ptr.getOperand(1)) && 4266 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 4267 FrameIdx = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 4268 FrameOffset = Ptr.getConstantOperandVal(1); 4269 } 4270 4271 if (FrameIdx != (1 << 31)) { 4272 // FIXME: Handle FI+CST. 4273 const MachineFrameInfo &MFI = *DAG.getMachineFunction().getFrameInfo(); 4274 if (MFI.isFixedObjectIndex(FrameIdx)) { 4275 int64_t ObjectOffset = MFI.getObjectOffset(FrameIdx); 4276 4277 // The alignment of the frame index can be determined from its offset from 4278 // the incoming frame position. If the frame object is at offset 32 and 4279 // the stack is guaranteed to be 16-byte aligned, then we know that the 4280 // object is 16-byte aligned. 4281 unsigned StackAlign = DAG.getTarget().getFrameInfo()->getStackAlignment(); 4282 unsigned Align = MinAlign(ObjectOffset, StackAlign); 4283 4284 // Finally, the frame object itself may have a known alignment. Factor 4285 // the alignment + offset into a new alignment. For example, if we know 4286 // the FI is 8 byte aligned, but the pointer is 4 off, we really have a 4287 // 4-byte alignment of the resultant pointer. Likewise align 4 + 4-byte 4288 // offset = 4-byte alignment, align 4 + 1-byte offset = align 1, etc. 4289 unsigned FIInfoAlign = MinAlign(MFI.getObjectAlignment(FrameIdx), 4290 FrameOffset); 4291 return std::max(Align, FIInfoAlign); 4292 } 4293 } 4294 4295 return 0; 4296} 4297 4298SDOperand DAGCombiner::visitLOAD(SDNode *N) { 4299 LoadSDNode *LD = cast<LoadSDNode>(N); 4300 SDOperand Chain = LD->getChain(); 4301 SDOperand Ptr = LD->getBasePtr(); 4302 4303 // Try to infer better alignment information than the load already has. 4304 if (LD->isUnindexed()) { 4305 if (unsigned Align = InferAlignment(Ptr, DAG)) { 4306 if (Align > LD->getAlignment()) 4307 return DAG.getExtLoad(LD->getExtensionType(), LD->getValueType(0), 4308 Chain, Ptr, LD->getSrcValue(), 4309 LD->getSrcValueOffset(), LD->getMemoryVT(), 4310 LD->isVolatile(), Align); 4311 } 4312 } 4313 4314 4315 // If load is not volatile and there are no uses of the loaded value (and 4316 // the updated indexed value in case of indexed loads), change uses of the 4317 // chain value into uses of the chain input (i.e. delete the dead load). 4318 if (!LD->isVolatile()) { 4319 if (N->getValueType(1) == MVT::Other) { 4320 // Unindexed loads. 4321 if (N->hasNUsesOfValue(0, 0)) { 4322 // It's not safe to use the two value CombineTo variant here. e.g. 4323 // v1, chain2 = load chain1, loc 4324 // v2, chain3 = load chain2, loc 4325 // v3 = add v2, c 4326 // Now we replace use of chain2 with chain1. This makes the second load 4327 // isomorphic to the one we are deleting, and thus makes this load live. 4328 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4329 DOUT << "\nWith chain: "; DEBUG(Chain.Val->dump(&DAG)); 4330 DOUT << "\n"; 4331 WorkListRemover DeadNodes(*this); 4332 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Chain, &DeadNodes); 4333 if (N->use_empty()) { 4334 removeFromWorkList(N); 4335 DAG.DeleteNode(N); 4336 } 4337 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 4338 } 4339 } else { 4340 // Indexed loads. 4341 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 4342 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 4343 SDOperand Undef = DAG.getNode(ISD::UNDEF, N->getValueType(0)); 4344 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4345 DOUT << "\nWith: "; DEBUG(Undef.Val->dump(&DAG)); 4346 DOUT << " and 2 other values\n"; 4347 WorkListRemover DeadNodes(*this); 4348 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Undef, &DeadNodes); 4349 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), 4350 DAG.getNode(ISD::UNDEF, N->getValueType(1)), 4351 &DeadNodes); 4352 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 2), Chain, &DeadNodes); 4353 removeFromWorkList(N); 4354 DAG.DeleteNode(N); 4355 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 4356 } 4357 } 4358 } 4359 4360 // If this load is directly stored, replace the load value with the stored 4361 // value. 4362 // TODO: Handle store large -> read small portion. 4363 // TODO: Handle TRUNCSTORE/LOADEXT 4364 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 4365 if (ISD::isNON_TRUNCStore(Chain.Val)) { 4366 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 4367 if (PrevST->getBasePtr() == Ptr && 4368 PrevST->getValue().getValueType() == N->getValueType(0)) 4369 return CombineTo(N, Chain.getOperand(1), Chain); 4370 } 4371 } 4372 4373 if (CombinerAA) { 4374 // Walk up chain skipping non-aliasing memory nodes. 4375 SDOperand BetterChain = FindBetterChain(N, Chain); 4376 4377 // If there is a better chain. 4378 if (Chain != BetterChain) { 4379 SDOperand ReplLoad; 4380 4381 // Replace the chain to void dependency. 4382 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 4383 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr, 4384 LD->getSrcValue(), LD->getSrcValueOffset(), 4385 LD->isVolatile(), LD->getAlignment()); 4386 } else { 4387 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), 4388 LD->getValueType(0), 4389 BetterChain, Ptr, LD->getSrcValue(), 4390 LD->getSrcValueOffset(), 4391 LD->getMemoryVT(), 4392 LD->isVolatile(), 4393 LD->getAlignment()); 4394 } 4395 4396 // Create token factor to keep old chain connected. 4397 SDOperand Token = DAG.getNode(ISD::TokenFactor, MVT::Other, 4398 Chain, ReplLoad.getValue(1)); 4399 4400 // Replace uses with load result and token factor. Don't add users 4401 // to work list. 4402 return CombineTo(N, ReplLoad.getValue(0), Token, false); 4403 } 4404 } 4405 4406 // Try transforming N to an indexed load. 4407 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4408 return SDOperand(N, 0); 4409 4410 return SDOperand(); 4411} 4412 4413 4414SDOperand DAGCombiner::visitSTORE(SDNode *N) { 4415 StoreSDNode *ST = cast<StoreSDNode>(N); 4416 SDOperand Chain = ST->getChain(); 4417 SDOperand Value = ST->getValue(); 4418 SDOperand Ptr = ST->getBasePtr(); 4419 4420 // Try to infer better alignment information than the store already has. 4421 if (ST->isUnindexed()) { 4422 if (unsigned Align = InferAlignment(Ptr, DAG)) { 4423 if (Align > ST->getAlignment()) 4424 return DAG.getTruncStore(Chain, Value, Ptr, ST->getSrcValue(), 4425 ST->getSrcValueOffset(), ST->getMemoryVT(), 4426 ST->isVolatile(), Align); 4427 } 4428 } 4429 4430 // If this is a store of a bit convert, store the input value if the 4431 // resultant store does not need a higher alignment than the original. 4432 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() && 4433 ST->isUnindexed()) { 4434 unsigned Align = ST->getAlignment(); 4435 MVT::ValueType SVT = Value.getOperand(0).getValueType(); 4436 unsigned OrigAlign = TLI.getTargetMachine().getTargetData()-> 4437 getABITypeAlignment(MVT::getTypeForValueType(SVT)); 4438 if (Align <= OrigAlign && TLI.isOperationLegal(ISD::STORE, SVT)) 4439 return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), 4440 ST->getSrcValueOffset(), ST->isVolatile(), Align); 4441 } 4442 4443 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 4444 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 4445 if (Value.getOpcode() != ISD::TargetConstantFP) { 4446 SDOperand Tmp; 4447 switch (CFP->getValueType(0)) { 4448 default: assert(0 && "Unknown FP type"); 4449 case MVT::f80: // We don't do this for these yet. 4450 case MVT::f128: 4451 case MVT::ppcf128: 4452 break; 4453 case MVT::f32: 4454 if (!AfterLegalize || TLI.isTypeLegal(MVT::i32)) { 4455 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 4456 convertToAPInt().getZExtValue(), MVT::i32); 4457 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 4458 ST->getSrcValueOffset(), ST->isVolatile(), 4459 ST->getAlignment()); 4460 } 4461 break; 4462 case MVT::f64: 4463 if (!AfterLegalize || TLI.isTypeLegal(MVT::i64)) { 4464 Tmp = DAG.getConstant(CFP->getValueAPF().convertToAPInt(). 4465 getZExtValue(), MVT::i64); 4466 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 4467 ST->getSrcValueOffset(), ST->isVolatile(), 4468 ST->getAlignment()); 4469 } else if (TLI.isTypeLegal(MVT::i32)) { 4470 // Many FP stores are not made apparent until after legalize, e.g. for 4471 // argument passing. Since this is so common, custom legalize the 4472 // 64-bit integer store into two 32-bit stores. 4473 uint64_t Val = CFP->getValueAPF().convertToAPInt().getZExtValue(); 4474 SDOperand Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 4475 SDOperand Hi = DAG.getConstant(Val >> 32, MVT::i32); 4476 if (TLI.isBigEndian()) std::swap(Lo, Hi); 4477 4478 int SVOffset = ST->getSrcValueOffset(); 4479 unsigned Alignment = ST->getAlignment(); 4480 bool isVolatile = ST->isVolatile(); 4481 4482 SDOperand St0 = DAG.getStore(Chain, Lo, Ptr, ST->getSrcValue(), 4483 ST->getSrcValueOffset(), 4484 isVolatile, ST->getAlignment()); 4485 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 4486 DAG.getConstant(4, Ptr.getValueType())); 4487 SVOffset += 4; 4488 Alignment = MinAlign(Alignment, 4U); 4489 SDOperand St1 = DAG.getStore(Chain, Hi, Ptr, ST->getSrcValue(), 4490 SVOffset, isVolatile, Alignment); 4491 return DAG.getNode(ISD::TokenFactor, MVT::Other, St0, St1); 4492 } 4493 break; 4494 } 4495 } 4496 } 4497 4498 if (CombinerAA) { 4499 // Walk up chain skipping non-aliasing memory nodes. 4500 SDOperand BetterChain = FindBetterChain(N, Chain); 4501 4502 // If there is a better chain. 4503 if (Chain != BetterChain) { 4504 // Replace the chain to avoid dependency. 4505 SDOperand ReplStore; 4506 if (ST->isTruncatingStore()) { 4507 ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr, 4508 ST->getSrcValue(),ST->getSrcValueOffset(), 4509 ST->getMemoryVT(), 4510 ST->isVolatile(), ST->getAlignment()); 4511 } else { 4512 ReplStore = DAG.getStore(BetterChain, Value, Ptr, 4513 ST->getSrcValue(), ST->getSrcValueOffset(), 4514 ST->isVolatile(), ST->getAlignment()); 4515 } 4516 4517 // Create token to keep both nodes around. 4518 SDOperand Token = 4519 DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore); 4520 4521 // Don't add users to work list. 4522 return CombineTo(N, Token, false); 4523 } 4524 } 4525 4526 // Try transforming N to an indexed store. 4527 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4528 return SDOperand(N, 0); 4529 4530 // FIXME: is there such a thing as a truncating indexed store? 4531 if (ST->isTruncatingStore() && ST->isUnindexed() && 4532 MVT::isInteger(Value.getValueType())) { 4533 // See if we can simplify the input to this truncstore with knowledge that 4534 // only the low bits are being used. For example: 4535 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 4536 SDOperand Shorter = 4537 GetDemandedBits(Value, 4538 APInt::getLowBitsSet(Value.getValueSizeInBits(), 4539 MVT::getSizeInBits(ST->getMemoryVT()))); 4540 AddToWorkList(Value.Val); 4541 if (Shorter.Val) 4542 return DAG.getTruncStore(Chain, Shorter, Ptr, ST->getSrcValue(), 4543 ST->getSrcValueOffset(), ST->getMemoryVT(), 4544 ST->isVolatile(), ST->getAlignment()); 4545 4546 // Otherwise, see if we can simplify the operation with 4547 // SimplifyDemandedBits, which only works if the value has a single use. 4548 if (SimplifyDemandedBits(Value, 4549 APInt::getLowBitsSet( 4550 Value.getValueSizeInBits(), 4551 MVT::getSizeInBits(ST->getMemoryVT())))) 4552 return SDOperand(N, 0); 4553 } 4554 4555 // If this is a load followed by a store to the same location, then the store 4556 // is dead/noop. 4557 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 4558 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 4559 ST->isUnindexed() && !ST->isVolatile() && 4560 // There can't be any side effects between the load and store, such as 4561 // a call or store. 4562 Chain.reachesChainWithoutSideEffects(SDOperand(Ld, 1))) { 4563 // The store is dead, remove it. 4564 return Chain; 4565 } 4566 } 4567 4568 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 4569 // truncating store. We can do this even if this is already a truncstore. 4570 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 4571 && TLI.isTypeLegal(Value.getOperand(0).getValueType()) && 4572 Value.Val->hasOneUse() && ST->isUnindexed() && 4573 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 4574 ST->getMemoryVT())) { 4575 return DAG.getTruncStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), 4576 ST->getSrcValueOffset(), ST->getMemoryVT(), 4577 ST->isVolatile(), ST->getAlignment()); 4578 } 4579 4580 return SDOperand(); 4581} 4582 4583SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 4584 SDOperand InVec = N->getOperand(0); 4585 SDOperand InVal = N->getOperand(1); 4586 SDOperand EltNo = N->getOperand(2); 4587 4588 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 4589 // vector with the inserted element. 4590 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 4591 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 4592 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end()); 4593 if (Elt < Ops.size()) 4594 Ops[Elt] = InVal; 4595 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(), 4596 &Ops[0], Ops.size()); 4597 } 4598 4599 return SDOperand(); 4600} 4601 4602SDOperand DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 4603 SDOperand InVec = N->getOperand(0); 4604 SDOperand EltNo = N->getOperand(1); 4605 4606 // (vextract (v4f32 s2v (f32 load $addr)), 0) -> (f32 load $addr) 4607 // (vextract (v4i32 bc (v4f32 s2v (f32 load $addr))), 0) -> (i32 load $addr) 4608 if (isa<ConstantSDNode>(EltNo)) { 4609 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 4610 bool NewLoad = false; 4611 if (Elt == 0) { 4612 MVT::ValueType VT = InVec.getValueType(); 4613 MVT::ValueType EVT = MVT::getVectorElementType(VT); 4614 MVT::ValueType LVT = EVT; 4615 unsigned NumElts = MVT::getVectorNumElements(VT); 4616 if (InVec.getOpcode() == ISD::BIT_CONVERT) { 4617 MVT::ValueType BCVT = InVec.getOperand(0).getValueType(); 4618 if (!MVT::isVector(BCVT) || 4619 NumElts != MVT::getVectorNumElements(BCVT)) 4620 return SDOperand(); 4621 InVec = InVec.getOperand(0); 4622 EVT = MVT::getVectorElementType(BCVT); 4623 NewLoad = true; 4624 } 4625 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 4626 InVec.getOperand(0).getValueType() == EVT && 4627 ISD::isNormalLoad(InVec.getOperand(0).Val) && 4628 InVec.getOperand(0).hasOneUse()) { 4629 LoadSDNode *LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 4630 unsigned Align = LN0->getAlignment(); 4631 if (NewLoad) { 4632 // Check the resultant load doesn't need a higher alignment than the 4633 // original load. 4634 unsigned NewAlign = TLI.getTargetMachine().getTargetData()-> 4635 getABITypeAlignment(MVT::getTypeForValueType(LVT)); 4636 if (!TLI.isOperationLegal(ISD::LOAD, LVT) || NewAlign > Align) 4637 return SDOperand(); 4638 Align = NewAlign; 4639 } 4640 4641 return DAG.getLoad(LVT, LN0->getChain(), LN0->getBasePtr(), 4642 LN0->getSrcValue(), LN0->getSrcValueOffset(), 4643 LN0->isVolatile(), Align); 4644 } 4645 } 4646 } 4647 return SDOperand(); 4648} 4649 4650 4651SDOperand DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 4652 unsigned NumInScalars = N->getNumOperands(); 4653 MVT::ValueType VT = N->getValueType(0); 4654 unsigned NumElts = MVT::getVectorNumElements(VT); 4655 MVT::ValueType EltType = MVT::getVectorElementType(VT); 4656 4657 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 4658 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 4659 // at most two distinct vectors, turn this into a shuffle node. 4660 SDOperand VecIn1, VecIn2; 4661 for (unsigned i = 0; i != NumInScalars; ++i) { 4662 // Ignore undef inputs. 4663 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 4664 4665 // If this input is something other than a EXTRACT_VECTOR_ELT with a 4666 // constant index, bail out. 4667 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 4668 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 4669 VecIn1 = VecIn2 = SDOperand(0, 0); 4670 break; 4671 } 4672 4673 // If the input vector type disagrees with the result of the build_vector, 4674 // we can't make a shuffle. 4675 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0); 4676 if (ExtractedFromVec.getValueType() != VT) { 4677 VecIn1 = VecIn2 = SDOperand(0, 0); 4678 break; 4679 } 4680 4681 // Otherwise, remember this. We allow up to two distinct input vectors. 4682 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 4683 continue; 4684 4685 if (VecIn1.Val == 0) { 4686 VecIn1 = ExtractedFromVec; 4687 } else if (VecIn2.Val == 0) { 4688 VecIn2 = ExtractedFromVec; 4689 } else { 4690 // Too many inputs. 4691 VecIn1 = VecIn2 = SDOperand(0, 0); 4692 break; 4693 } 4694 } 4695 4696 // If everything is good, we can make a shuffle operation. 4697 if (VecIn1.Val) { 4698 SmallVector<SDOperand, 8> BuildVecIndices; 4699 for (unsigned i = 0; i != NumInScalars; ++i) { 4700 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 4701 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, TLI.getPointerTy())); 4702 continue; 4703 } 4704 4705 SDOperand Extract = N->getOperand(i); 4706 4707 // If extracting from the first vector, just use the index directly. 4708 if (Extract.getOperand(0) == VecIn1) { 4709 BuildVecIndices.push_back(Extract.getOperand(1)); 4710 continue; 4711 } 4712 4713 // Otherwise, use InIdx + VecSize 4714 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue(); 4715 BuildVecIndices.push_back(DAG.getIntPtrConstant(Idx+NumInScalars)); 4716 } 4717 4718 // Add count and size info. 4719 MVT::ValueType BuildVecVT = MVT::getVectorType(TLI.getPointerTy(), NumElts); 4720 4721 // Return the new VECTOR_SHUFFLE node. 4722 SDOperand Ops[5]; 4723 Ops[0] = VecIn1; 4724 if (VecIn2.Val) { 4725 Ops[1] = VecIn2; 4726 } else { 4727 // Use an undef build_vector as input for the second operand. 4728 std::vector<SDOperand> UnOps(NumInScalars, 4729 DAG.getNode(ISD::UNDEF, 4730 EltType)); 4731 Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, VT, 4732 &UnOps[0], UnOps.size()); 4733 AddToWorkList(Ops[1].Val); 4734 } 4735 Ops[2] = DAG.getNode(ISD::BUILD_VECTOR, BuildVecVT, 4736 &BuildVecIndices[0], BuildVecIndices.size()); 4737 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Ops, 3); 4738 } 4739 4740 return SDOperand(); 4741} 4742 4743SDOperand DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 4744 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 4745 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 4746 // inputs come from at most two distinct vectors, turn this into a shuffle 4747 // node. 4748 4749 // If we only have one input vector, we don't need to do any concatenation. 4750 if (N->getNumOperands() == 1) { 4751 return N->getOperand(0); 4752 } 4753 4754 return SDOperand(); 4755} 4756 4757SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 4758 SDOperand ShufMask = N->getOperand(2); 4759 unsigned NumElts = ShufMask.getNumOperands(); 4760 4761 // If the shuffle mask is an identity operation on the LHS, return the LHS. 4762 bool isIdentity = true; 4763 for (unsigned i = 0; i != NumElts; ++i) { 4764 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 4765 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) { 4766 isIdentity = false; 4767 break; 4768 } 4769 } 4770 if (isIdentity) return N->getOperand(0); 4771 4772 // If the shuffle mask is an identity operation on the RHS, return the RHS. 4773 isIdentity = true; 4774 for (unsigned i = 0; i != NumElts; ++i) { 4775 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 4776 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) { 4777 isIdentity = false; 4778 break; 4779 } 4780 } 4781 if (isIdentity) return N->getOperand(1); 4782 4783 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not 4784 // needed at all. 4785 bool isUnary = true; 4786 bool isSplat = true; 4787 int VecNum = -1; 4788 unsigned BaseIdx = 0; 4789 for (unsigned i = 0; i != NumElts; ++i) 4790 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) { 4791 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue(); 4792 int V = (Idx < NumElts) ? 0 : 1; 4793 if (VecNum == -1) { 4794 VecNum = V; 4795 BaseIdx = Idx; 4796 } else { 4797 if (BaseIdx != Idx) 4798 isSplat = false; 4799 if (VecNum != V) { 4800 isUnary = false; 4801 break; 4802 } 4803 } 4804 } 4805 4806 SDOperand N0 = N->getOperand(0); 4807 SDOperand N1 = N->getOperand(1); 4808 // Normalize unary shuffle so the RHS is undef. 4809 if (isUnary && VecNum == 1) 4810 std::swap(N0, N1); 4811 4812 // If it is a splat, check if the argument vector is a build_vector with 4813 // all scalar elements the same. 4814 if (isSplat) { 4815 SDNode *V = N0.Val; 4816 4817 // If this is a bit convert that changes the element type of the vector but 4818 // not the number of vector elements, look through it. Be careful not to 4819 // look though conversions that change things like v4f32 to v2f64. 4820 if (V->getOpcode() == ISD::BIT_CONVERT) { 4821 SDOperand ConvInput = V->getOperand(0); 4822 if (MVT::getVectorNumElements(ConvInput.getValueType()) == NumElts) 4823 V = ConvInput.Val; 4824 } 4825 4826 if (V->getOpcode() == ISD::BUILD_VECTOR) { 4827 unsigned NumElems = V->getNumOperands(); 4828 if (NumElems > BaseIdx) { 4829 SDOperand Base; 4830 bool AllSame = true; 4831 for (unsigned i = 0; i != NumElems; ++i) { 4832 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 4833 Base = V->getOperand(i); 4834 break; 4835 } 4836 } 4837 // Splat of <u, u, u, u>, return <u, u, u, u> 4838 if (!Base.Val) 4839 return N0; 4840 for (unsigned i = 0; i != NumElems; ++i) { 4841 if (V->getOperand(i) != Base) { 4842 AllSame = false; 4843 break; 4844 } 4845 } 4846 // Splat of <x, x, x, x>, return <x, x, x, x> 4847 if (AllSame) 4848 return N0; 4849 } 4850 } 4851 } 4852 4853 // If it is a unary or the LHS and the RHS are the same node, turn the RHS 4854 // into an undef. 4855 if (isUnary || N0 == N1) { 4856 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the 4857 // first operand. 4858 SmallVector<SDOperand, 8> MappedOps; 4859 for (unsigned i = 0; i != NumElts; ++i) { 4860 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || 4861 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) { 4862 MappedOps.push_back(ShufMask.getOperand(i)); 4863 } else { 4864 unsigned NewIdx = 4865 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts; 4866 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32)); 4867 } 4868 } 4869 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(), 4870 &MappedOps[0], MappedOps.size()); 4871 AddToWorkList(ShufMask.Val); 4872 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0), 4873 N0, 4874 DAG.getNode(ISD::UNDEF, N->getValueType(0)), 4875 ShufMask); 4876 } 4877 4878 return SDOperand(); 4879} 4880 4881/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 4882/// an AND to a vector_shuffle with the destination vector and a zero vector. 4883/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 4884/// vector_shuffle V, Zero, <0, 4, 2, 4> 4885SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) { 4886 SDOperand LHS = N->getOperand(0); 4887 SDOperand RHS = N->getOperand(1); 4888 if (N->getOpcode() == ISD::AND) { 4889 if (RHS.getOpcode() == ISD::BIT_CONVERT) 4890 RHS = RHS.getOperand(0); 4891 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 4892 std::vector<SDOperand> IdxOps; 4893 unsigned NumOps = RHS.getNumOperands(); 4894 unsigned NumElts = NumOps; 4895 MVT::ValueType EVT = MVT::getVectorElementType(RHS.getValueType()); 4896 for (unsigned i = 0; i != NumElts; ++i) { 4897 SDOperand Elt = RHS.getOperand(i); 4898 if (!isa<ConstantSDNode>(Elt)) 4899 return SDOperand(); 4900 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 4901 IdxOps.push_back(DAG.getConstant(i, EVT)); 4902 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 4903 IdxOps.push_back(DAG.getConstant(NumElts, EVT)); 4904 else 4905 return SDOperand(); 4906 } 4907 4908 // Let's see if the target supports this vector_shuffle. 4909 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG)) 4910 return SDOperand(); 4911 4912 // Return the new VECTOR_SHUFFLE node. 4913 MVT::ValueType VT = MVT::getVectorType(EVT, NumElts); 4914 std::vector<SDOperand> Ops; 4915 LHS = DAG.getNode(ISD::BIT_CONVERT, VT, LHS); 4916 Ops.push_back(LHS); 4917 AddToWorkList(LHS.Val); 4918 std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT)); 4919 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT, 4920 &ZeroOps[0], ZeroOps.size())); 4921 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT, 4922 &IdxOps[0], IdxOps.size())); 4923 SDOperand Result = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, 4924 &Ops[0], Ops.size()); 4925 if (VT != LHS.getValueType()) { 4926 Result = DAG.getNode(ISD::BIT_CONVERT, LHS.getValueType(), Result); 4927 } 4928 return Result; 4929 } 4930 } 4931 return SDOperand(); 4932} 4933 4934/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 4935SDOperand DAGCombiner::SimplifyVBinOp(SDNode *N) { 4936 // After legalize, the target may be depending on adds and other 4937 // binary ops to provide legal ways to construct constants or other 4938 // things. Simplifying them may result in a loss of legality. 4939 if (AfterLegalize) return SDOperand(); 4940 4941 MVT::ValueType VT = N->getValueType(0); 4942 assert(MVT::isVector(VT) && "SimplifyVBinOp only works on vectors!"); 4943 4944 MVT::ValueType EltType = MVT::getVectorElementType(VT); 4945 SDOperand LHS = N->getOperand(0); 4946 SDOperand RHS = N->getOperand(1); 4947 SDOperand Shuffle = XformToShuffleWithZero(N); 4948 if (Shuffle.Val) return Shuffle; 4949 4950 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 4951 // this operation. 4952 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 4953 RHS.getOpcode() == ISD::BUILD_VECTOR) { 4954 SmallVector<SDOperand, 8> Ops; 4955 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 4956 SDOperand LHSOp = LHS.getOperand(i); 4957 SDOperand RHSOp = RHS.getOperand(i); 4958 // If these two elements can't be folded, bail out. 4959 if ((LHSOp.getOpcode() != ISD::UNDEF && 4960 LHSOp.getOpcode() != ISD::Constant && 4961 LHSOp.getOpcode() != ISD::ConstantFP) || 4962 (RHSOp.getOpcode() != ISD::UNDEF && 4963 RHSOp.getOpcode() != ISD::Constant && 4964 RHSOp.getOpcode() != ISD::ConstantFP)) 4965 break; 4966 // Can't fold divide by zero. 4967 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 4968 N->getOpcode() == ISD::FDIV) { 4969 if ((RHSOp.getOpcode() == ISD::Constant && 4970 cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) || 4971 (RHSOp.getOpcode() == ISD::ConstantFP && 4972 cast<ConstantFPSDNode>(RHSOp.Val)->getValueAPF().isZero())) 4973 break; 4974 } 4975 Ops.push_back(DAG.getNode(N->getOpcode(), EltType, LHSOp, RHSOp)); 4976 AddToWorkList(Ops.back().Val); 4977 assert((Ops.back().getOpcode() == ISD::UNDEF || 4978 Ops.back().getOpcode() == ISD::Constant || 4979 Ops.back().getOpcode() == ISD::ConstantFP) && 4980 "Scalar binop didn't fold!"); 4981 } 4982 4983 if (Ops.size() == LHS.getNumOperands()) { 4984 MVT::ValueType VT = LHS.getValueType(); 4985 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 4986 } 4987 } 4988 4989 return SDOperand(); 4990} 4991 4992SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){ 4993 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 4994 4995 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2, 4996 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4997 // If we got a simplified select_cc node back from SimplifySelectCC, then 4998 // break it down into a new SETCC node, and a new SELECT node, and then return 4999 // the SELECT node, since we were called with a SELECT node. 5000 if (SCC.Val) { 5001 // Check to see if we got a select_cc back (to turn into setcc/select). 5002 // Otherwise, just return whatever node we got back, like fabs. 5003 if (SCC.getOpcode() == ISD::SELECT_CC) { 5004 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(), 5005 SCC.getOperand(0), SCC.getOperand(1), 5006 SCC.getOperand(4)); 5007 AddToWorkList(SETCC.Val); 5008 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2), 5009 SCC.getOperand(3), SETCC); 5010 } 5011 return SCC; 5012 } 5013 return SDOperand(); 5014} 5015 5016/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 5017/// are the two values being selected between, see if we can simplify the 5018/// select. Callers of this should assume that TheSelect is deleted if this 5019/// returns true. As such, they should return the appropriate thing (e.g. the 5020/// node) back to the top-level of the DAG combiner loop to avoid it being 5021/// looked at. 5022/// 5023bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS, 5024 SDOperand RHS) { 5025 5026 // If this is a select from two identical things, try to pull the operation 5027 // through the select. 5028 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 5029 // If this is a load and the token chain is identical, replace the select 5030 // of two loads with a load through a select of the address to load from. 5031 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 5032 // constants have been dropped into the constant pool. 5033 if (LHS.getOpcode() == ISD::LOAD && 5034 // Token chains must be identical. 5035 LHS.getOperand(0) == RHS.getOperand(0)) { 5036 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 5037 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 5038 5039 // If this is an EXTLOAD, the VT's must match. 5040 if (LLD->getMemoryVT() == RLD->getMemoryVT()) { 5041 // FIXME: this conflates two src values, discarding one. This is not 5042 // the right thing to do, but nothing uses srcvalues now. When they do, 5043 // turn SrcValue into a list of locations. 5044 SDOperand Addr; 5045 if (TheSelect->getOpcode() == ISD::SELECT) { 5046 // Check that the condition doesn't reach either load. If so, folding 5047 // this will induce a cycle into the DAG. 5048 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).Val) && 5049 !RLD->isPredecessorOf(TheSelect->getOperand(0).Val)) { 5050 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(), 5051 TheSelect->getOperand(0), LLD->getBasePtr(), 5052 RLD->getBasePtr()); 5053 } 5054 } else { 5055 // Check that the condition doesn't reach either load. If so, folding 5056 // this will induce a cycle into the DAG. 5057 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).Val) && 5058 !RLD->isPredecessorOf(TheSelect->getOperand(0).Val) && 5059 !LLD->isPredecessorOf(TheSelect->getOperand(1).Val) && 5060 !RLD->isPredecessorOf(TheSelect->getOperand(1).Val)) { 5061 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(), 5062 TheSelect->getOperand(0), 5063 TheSelect->getOperand(1), 5064 LLD->getBasePtr(), RLD->getBasePtr(), 5065 TheSelect->getOperand(4)); 5066 } 5067 } 5068 5069 if (Addr.Val) { 5070 SDOperand Load; 5071 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) 5072 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(), 5073 Addr,LLD->getSrcValue(), 5074 LLD->getSrcValueOffset(), 5075 LLD->isVolatile(), 5076 LLD->getAlignment()); 5077 else { 5078 Load = DAG.getExtLoad(LLD->getExtensionType(), 5079 TheSelect->getValueType(0), 5080 LLD->getChain(), Addr, LLD->getSrcValue(), 5081 LLD->getSrcValueOffset(), 5082 LLD->getMemoryVT(), 5083 LLD->isVolatile(), 5084 LLD->getAlignment()); 5085 } 5086 // Users of the select now use the result of the load. 5087 CombineTo(TheSelect, Load); 5088 5089 // Users of the old loads now use the new load's chain. We know the 5090 // old-load value is dead now. 5091 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1)); 5092 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1)); 5093 return true; 5094 } 5095 } 5096 } 5097 } 5098 5099 return false; 5100} 5101 5102SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1, 5103 SDOperand N2, SDOperand N3, 5104 ISD::CondCode CC, bool NotExtCompare) { 5105 5106 MVT::ValueType VT = N2.getValueType(); 5107 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 5108 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 5109 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 5110 5111 // Determine if the condition we're dealing with is constant 5112 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultType(N0), N0, N1, CC, false); 5113 if (SCC.Val) AddToWorkList(SCC.Val); 5114 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 5115 5116 // fold select_cc true, x, y -> x 5117 if (SCCC && !SCCC->isNullValue()) 5118 return N2; 5119 // fold select_cc false, x, y -> y 5120 if (SCCC && SCCC->isNullValue()) 5121 return N3; 5122 5123 // Check to see if we can simplify the select into an fabs node 5124 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 5125 // Allow either -0.0 or 0.0 5126 if (CFP->getValueAPF().isZero()) { 5127 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 5128 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 5129 N0 == N2 && N3.getOpcode() == ISD::FNEG && 5130 N2 == N3.getOperand(0)) 5131 return DAG.getNode(ISD::FABS, VT, N0); 5132 5133 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 5134 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 5135 N0 == N3 && N2.getOpcode() == ISD::FNEG && 5136 N2.getOperand(0) == N3) 5137 return DAG.getNode(ISD::FABS, VT, N3); 5138 } 5139 } 5140 5141 // Check to see if we can perform the "gzip trick", transforming 5142 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 5143 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 5144 MVT::isInteger(N0.getValueType()) && 5145 MVT::isInteger(N2.getValueType()) && 5146 (N1C->isNullValue() || // (a < 0) ? b : 0 5147 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 5148 MVT::ValueType XType = N0.getValueType(); 5149 MVT::ValueType AType = N2.getValueType(); 5150 if (XType >= AType) { 5151 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 5152 // single-bit constant. 5153 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 5154 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 5155 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1; 5156 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy()); 5157 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt); 5158 AddToWorkList(Shift.Val); 5159 if (XType > AType) { 5160 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 5161 AddToWorkList(Shift.Val); 5162 } 5163 return DAG.getNode(ISD::AND, AType, Shift, N2); 5164 } 5165 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 5166 DAG.getConstant(MVT::getSizeInBits(XType)-1, 5167 TLI.getShiftAmountTy())); 5168 AddToWorkList(Shift.Val); 5169 if (XType > AType) { 5170 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 5171 AddToWorkList(Shift.Val); 5172 } 5173 return DAG.getNode(ISD::AND, AType, Shift, N2); 5174 } 5175 } 5176 5177 // fold select C, 16, 0 -> shl C, 4 5178 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 5179 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) { 5180 5181 // If the caller doesn't want us to simplify this into a zext of a compare, 5182 // don't do it. 5183 if (NotExtCompare && N2C->getAPIntValue() == 1) 5184 return SDOperand(); 5185 5186 // Get a SetCC of the condition 5187 // FIXME: Should probably make sure that setcc is legal if we ever have a 5188 // target where it isn't. 5189 SDOperand Temp, SCC; 5190 // cast from setcc result type to select result type 5191 if (AfterLegalize) { 5192 SCC = DAG.getSetCC(TLI.getSetCCResultType(N0), N0, N1, CC); 5193 if (N2.getValueType() < SCC.getValueType()) 5194 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType()); 5195 else 5196 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 5197 } else { 5198 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC); 5199 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 5200 } 5201 AddToWorkList(SCC.Val); 5202 AddToWorkList(Temp.Val); 5203 5204 if (N2C->getAPIntValue() == 1) 5205 return Temp; 5206 // shl setcc result by log2 n2c 5207 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp, 5208 DAG.getConstant(N2C->getAPIntValue().logBase2(), 5209 TLI.getShiftAmountTy())); 5210 } 5211 5212 // Check to see if this is the equivalent of setcc 5213 // FIXME: Turn all of these into setcc if setcc if setcc is legal 5214 // otherwise, go ahead with the folds. 5215 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 5216 MVT::ValueType XType = N0.getValueType(); 5217 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(N0))) { 5218 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultType(N0), N0, N1, CC); 5219 if (Res.getValueType() != VT) 5220 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res); 5221 return Res; 5222 } 5223 5224 // seteq X, 0 -> srl (ctlz X, log2(size(X))) 5225 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 5226 TLI.isOperationLegal(ISD::CTLZ, XType)) { 5227 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0); 5228 return DAG.getNode(ISD::SRL, XType, Ctlz, 5229 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)), 5230 TLI.getShiftAmountTy())); 5231 } 5232 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) 5233 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 5234 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType), 5235 N0); 5236 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0, 5237 DAG.getConstant(~0ULL, XType)); 5238 return DAG.getNode(ISD::SRL, XType, 5239 DAG.getNode(ISD::AND, XType, NegN0, NotN0), 5240 DAG.getConstant(MVT::getSizeInBits(XType)-1, 5241 TLI.getShiftAmountTy())); 5242 } 5243 // setgt X, -1 -> xor (srl (X, size(X)-1), 1) 5244 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 5245 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0, 5246 DAG.getConstant(MVT::getSizeInBits(XType)-1, 5247 TLI.getShiftAmountTy())); 5248 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType)); 5249 } 5250 } 5251 5252 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 5253 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5254 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 5255 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) && 5256 N2.getOperand(0) == N1 && MVT::isInteger(N0.getValueType())) { 5257 MVT::ValueType XType = N0.getValueType(); 5258 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 5259 DAG.getConstant(MVT::getSizeInBits(XType)-1, 5260 TLI.getShiftAmountTy())); 5261 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 5262 AddToWorkList(Shift.Val); 5263 AddToWorkList(Add.Val); 5264 return DAG.getNode(ISD::XOR, XType, Add, Shift); 5265 } 5266 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X -> 5267 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5268 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT && 5269 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) { 5270 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 5271 MVT::ValueType XType = N0.getValueType(); 5272 if (SubC->isNullValue() && MVT::isInteger(XType)) { 5273 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 5274 DAG.getConstant(MVT::getSizeInBits(XType)-1, 5275 TLI.getShiftAmountTy())); 5276 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 5277 AddToWorkList(Shift.Val); 5278 AddToWorkList(Add.Val); 5279 return DAG.getNode(ISD::XOR, XType, Add, Shift); 5280 } 5281 } 5282 } 5283 5284 return SDOperand(); 5285} 5286 5287/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 5288SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0, 5289 SDOperand N1, ISD::CondCode Cond, 5290 bool foldBooleans) { 5291 TargetLowering::DAGCombinerInfo 5292 DagCombineInfo(DAG, !AfterLegalize, false, this); 5293 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo); 5294} 5295 5296/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 5297/// return a DAG expression to select that will generate the same value by 5298/// multiplying by a magic number. See: 5299/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 5300SDOperand DAGCombiner::BuildSDIV(SDNode *N) { 5301 std::vector<SDNode*> Built; 5302 SDOperand S = TLI.BuildSDIV(N, DAG, &Built); 5303 5304 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 5305 ii != ee; ++ii) 5306 AddToWorkList(*ii); 5307 return S; 5308} 5309 5310/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 5311/// return a DAG expression to select that will generate the same value by 5312/// multiplying by a magic number. See: 5313/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 5314SDOperand DAGCombiner::BuildUDIV(SDNode *N) { 5315 std::vector<SDNode*> Built; 5316 SDOperand S = TLI.BuildUDIV(N, DAG, &Built); 5317 5318 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 5319 ii != ee; ++ii) 5320 AddToWorkList(*ii); 5321 return S; 5322} 5323 5324/// FindBaseOffset - Return true if base is known not to alias with anything 5325/// but itself. Provides base object and offset as results. 5326static bool FindBaseOffset(SDOperand Ptr, SDOperand &Base, int64_t &Offset) { 5327 // Assume it is a primitive operation. 5328 Base = Ptr; Offset = 0; 5329 5330 // If it's an adding a simple constant then integrate the offset. 5331 if (Base.getOpcode() == ISD::ADD) { 5332 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 5333 Base = Base.getOperand(0); 5334 Offset += C->getValue(); 5335 } 5336 } 5337 5338 // If it's any of the following then it can't alias with anything but itself. 5339 return isa<FrameIndexSDNode>(Base) || 5340 isa<ConstantPoolSDNode>(Base) || 5341 isa<GlobalAddressSDNode>(Base); 5342} 5343 5344/// isAlias - Return true if there is any possibility that the two addresses 5345/// overlap. 5346bool DAGCombiner::isAlias(SDOperand Ptr1, int64_t Size1, 5347 const Value *SrcValue1, int SrcValueOffset1, 5348 SDOperand Ptr2, int64_t Size2, 5349 const Value *SrcValue2, int SrcValueOffset2) 5350{ 5351 // If they are the same then they must be aliases. 5352 if (Ptr1 == Ptr2) return true; 5353 5354 // Gather base node and offset information. 5355 SDOperand Base1, Base2; 5356 int64_t Offset1, Offset2; 5357 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1); 5358 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2); 5359 5360 // If they have a same base address then... 5361 if (Base1 == Base2) { 5362 // Check to see if the addresses overlap. 5363 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 5364 } 5365 5366 // If we know both bases then they can't alias. 5367 if (KnownBase1 && KnownBase2) return false; 5368 5369 if (CombinerGlobalAA) { 5370 // Use alias analysis information. 5371 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 5372 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 5373 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 5374 AliasAnalysis::AliasResult AAResult = 5375 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2); 5376 if (AAResult == AliasAnalysis::NoAlias) 5377 return false; 5378 } 5379 5380 // Otherwise we have to assume they alias. 5381 return true; 5382} 5383 5384/// FindAliasInfo - Extracts the relevant alias information from the memory 5385/// node. Returns true if the operand was a load. 5386bool DAGCombiner::FindAliasInfo(SDNode *N, 5387 SDOperand &Ptr, int64_t &Size, 5388 const Value *&SrcValue, int &SrcValueOffset) { 5389 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 5390 Ptr = LD->getBasePtr(); 5391 Size = MVT::getSizeInBits(LD->getMemoryVT()) >> 3; 5392 SrcValue = LD->getSrcValue(); 5393 SrcValueOffset = LD->getSrcValueOffset(); 5394 return true; 5395 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 5396 Ptr = ST->getBasePtr(); 5397 Size = MVT::getSizeInBits(ST->getMemoryVT()) >> 3; 5398 SrcValue = ST->getSrcValue(); 5399 SrcValueOffset = ST->getSrcValueOffset(); 5400 } else { 5401 assert(0 && "FindAliasInfo expected a memory operand"); 5402 } 5403 5404 return false; 5405} 5406 5407/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 5408/// looking for aliasing nodes and adding them to the Aliases vector. 5409void DAGCombiner::GatherAllAliases(SDNode *N, SDOperand OriginalChain, 5410 SmallVector<SDOperand, 8> &Aliases) { 5411 SmallVector<SDOperand, 8> Chains; // List of chains to visit. 5412 std::set<SDNode *> Visited; // Visited node set. 5413 5414 // Get alias information for node. 5415 SDOperand Ptr; 5416 int64_t Size; 5417 const Value *SrcValue; 5418 int SrcValueOffset; 5419 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset); 5420 5421 // Starting off. 5422 Chains.push_back(OriginalChain); 5423 5424 // Look at each chain and determine if it is an alias. If so, add it to the 5425 // aliases list. If not, then continue up the chain looking for the next 5426 // candidate. 5427 while (!Chains.empty()) { 5428 SDOperand Chain = Chains.back(); 5429 Chains.pop_back(); 5430 5431 // Don't bother if we've been before. 5432 if (Visited.find(Chain.Val) != Visited.end()) continue; 5433 Visited.insert(Chain.Val); 5434 5435 switch (Chain.getOpcode()) { 5436 case ISD::EntryToken: 5437 // Entry token is ideal chain operand, but handled in FindBetterChain. 5438 break; 5439 5440 case ISD::LOAD: 5441 case ISD::STORE: { 5442 // Get alias information for Chain. 5443 SDOperand OpPtr; 5444 int64_t OpSize; 5445 const Value *OpSrcValue; 5446 int OpSrcValueOffset; 5447 bool IsOpLoad = FindAliasInfo(Chain.Val, OpPtr, OpSize, 5448 OpSrcValue, OpSrcValueOffset); 5449 5450 // If chain is alias then stop here. 5451 if (!(IsLoad && IsOpLoad) && 5452 isAlias(Ptr, Size, SrcValue, SrcValueOffset, 5453 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) { 5454 Aliases.push_back(Chain); 5455 } else { 5456 // Look further up the chain. 5457 Chains.push_back(Chain.getOperand(0)); 5458 // Clean up old chain. 5459 AddToWorkList(Chain.Val); 5460 } 5461 break; 5462 } 5463 5464 case ISD::TokenFactor: 5465 // We have to check each of the operands of the token factor, so we queue 5466 // then up. Adding the operands to the queue (stack) in reverse order 5467 // maintains the original order and increases the likelihood that getNode 5468 // will find a matching token factor (CSE.) 5469 for (unsigned n = Chain.getNumOperands(); n;) 5470 Chains.push_back(Chain.getOperand(--n)); 5471 // Eliminate the token factor if we can. 5472 AddToWorkList(Chain.Val); 5473 break; 5474 5475 default: 5476 // For all other instructions we will just have to take what we can get. 5477 Aliases.push_back(Chain); 5478 break; 5479 } 5480 } 5481} 5482 5483/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 5484/// for a better chain (aliasing node.) 5485SDOperand DAGCombiner::FindBetterChain(SDNode *N, SDOperand OldChain) { 5486 SmallVector<SDOperand, 8> Aliases; // Ops for replacing token factor. 5487 5488 // Accumulate all the aliases to this node. 5489 GatherAllAliases(N, OldChain, Aliases); 5490 5491 if (Aliases.size() == 0) { 5492 // If no operands then chain to entry token. 5493 return DAG.getEntryNode(); 5494 } else if (Aliases.size() == 1) { 5495 // If a single operand then chain to it. We don't need to revisit it. 5496 return Aliases[0]; 5497 } 5498 5499 // Construct a custom tailored token factor. 5500 SDOperand NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 5501 &Aliases[0], Aliases.size()); 5502 5503 // Make sure the old chain gets cleaned up. 5504 if (NewChain != OldChain) AddToWorkList(OldChain.Val); 5505 5506 return NewChain; 5507} 5508 5509// SelectionDAG::Combine - This is the entry point for the file. 5510// 5511void SelectionDAG::Combine(bool RunningAfterLegalize, AliasAnalysis &AA) { 5512 if (!RunningAfterLegalize && ViewDAGCombine1) 5513 viewGraph(); 5514 if (RunningAfterLegalize && ViewDAGCombine2) 5515 viewGraph(); 5516 /// run - This is the main entry point to this class. 5517 /// 5518 DAGCombiner(*this, AA).Run(RunningAfterLegalize); 5519} 5520