DAGCombiner.cpp revision d1aed7aaf7047873b8878502859905159eaf5362
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Nate Begeman and is distributed under the 6// University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// FIXME: Missing folds 14// sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into 15// a sequence of multiplies, shifts, and adds. This should be controlled by 16// some kind of hint from the target that int div is expensive. 17// various folds of mulh[s,u] by constants such as -1, powers of 2, etc. 18// 19// FIXME: select C, pow2, pow2 -> something smart 20// FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z) 21// FIXME: Dead stores -> nuke 22// FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!) 23// FIXME: mul (x, const) -> shifts + adds 24// FIXME: undef values 25// FIXME: divide by zero is currently left unfolded. do we want to turn this 26// into an undef? 27// FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false 28// 29//===----------------------------------------------------------------------===// 30 31#define DEBUG_TYPE "dagcombine" 32#include "llvm/ADT/Statistic.h" 33#include "llvm/CodeGen/SelectionDAG.h" 34#include "llvm/Support/Debug.h" 35#include "llvm/Support/MathExtras.h" 36#include "llvm/Target/TargetLowering.h" 37#include "llvm/Support/Compiler.h" 38#include "llvm/Support/CommandLine.h" 39#include <algorithm> 40#include <cmath> 41#include <iostream> 42using namespace llvm; 43 44namespace { 45 static Statistic<> NodesCombined ("dagcombiner", 46 "Number of dag nodes combined"); 47 48 49#ifndef NDEBUG 50static cl::opt<bool> 51 CombinerAA("combiner-alias-analysis", cl::Hidden, 52 cl::desc("Turn on alias analysis turning testing")); 53#else 54 static const bool CombinerAA = 0; 55#endif 56 57class VISIBILITY_HIDDEN DAGCombiner { 58 SelectionDAG &DAG; 59 TargetLowering &TLI; 60 bool AfterLegalize; 61 62 // Worklist of all of the nodes that need to be simplified. 63 std::vector<SDNode*> WorkList; 64 65 /// AddUsersToWorkList - When an instruction is simplified, add all users of 66 /// the instruction to the work lists because they might get more simplified 67 /// now. 68 /// 69 void AddUsersToWorkList(SDNode *N) { 70 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 71 UI != UE; ++UI) 72 WorkList.push_back(*UI); 73 } 74 75 /// removeFromWorkList - remove all instances of N from the worklist. 76 /// 77 void removeFromWorkList(SDNode *N) { 78 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 79 WorkList.end()); 80 } 81 82 public: 83 void AddToWorkList(SDNode *N) { 84 WorkList.push_back(N); 85 } 86 87 SDOperand CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo) { 88 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 89 ++NodesCombined; 90 DEBUG(std::cerr << "\nReplacing "; N->dump(); 91 std::cerr << "\nWith: "; To[0].Val->dump(&DAG); 92 std::cerr << " and " << NumTo-1 << " other values\n"); 93 std::vector<SDNode*> NowDead; 94 DAG.ReplaceAllUsesWith(N, To, &NowDead); 95 96 // Push the new nodes and any users onto the worklist 97 for (unsigned i = 0, e = NumTo; i != e; ++i) { 98 WorkList.push_back(To[i].Val); 99 AddUsersToWorkList(To[i].Val); 100 } 101 102 // Nodes can end up on the worklist more than once. Make sure we do 103 // not process a node that has been replaced. 104 removeFromWorkList(N); 105 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 106 removeFromWorkList(NowDead[i]); 107 108 // Finally, since the node is now dead, remove it from the graph. 109 DAG.DeleteNode(N); 110 return SDOperand(N, 0); 111 } 112 113 SDOperand CombineTo(SDNode *N, SDOperand Res) { 114 return CombineTo(N, &Res, 1); 115 } 116 117 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) { 118 SDOperand To[] = { Res0, Res1 }; 119 return CombineTo(N, To, 2); 120 } 121 private: 122 123 /// SimplifyDemandedBits - Check the specified integer node value to see if 124 /// it can be simplified or if things it uses can be simplified by bit 125 /// propagation. If so, return true. 126 bool SimplifyDemandedBits(SDOperand Op) { 127 TargetLowering::TargetLoweringOpt TLO(DAG); 128 uint64_t KnownZero, KnownOne; 129 uint64_t Demanded = MVT::getIntVTBitMask(Op.getValueType()); 130 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 131 return false; 132 133 // Revisit the node. 134 WorkList.push_back(Op.Val); 135 136 // Replace the old value with the new one. 137 ++NodesCombined; 138 DEBUG(std::cerr << "\nReplacing "; TLO.Old.Val->dump(); 139 std::cerr << "\nWith: "; TLO.New.Val->dump(&DAG)); 140 141 std::vector<SDNode*> NowDead; 142 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, NowDead); 143 144 // Push the new node and any (possibly new) users onto the worklist. 145 WorkList.push_back(TLO.New.Val); 146 AddUsersToWorkList(TLO.New.Val); 147 148 // Nodes can end up on the worklist more than once. Make sure we do 149 // not process a node that has been replaced. 150 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 151 removeFromWorkList(NowDead[i]); 152 153 // Finally, if the node is now dead, remove it from the graph. The node 154 // may not be dead if the replacement process recursively simplified to 155 // something else needing this node. 156 if (TLO.Old.Val->use_empty()) { 157 removeFromWorkList(TLO.Old.Val); 158 DAG.DeleteNode(TLO.Old.Val); 159 } 160 return true; 161 } 162 163 /// visit - call the node-specific routine that knows how to fold each 164 /// particular type of node. 165 SDOperand visit(SDNode *N); 166 167 // Visitation implementation - Implement dag node combining for different 168 // node types. The semantics are as follows: 169 // Return Value: 170 // SDOperand.Val == 0 - No change was made 171 // SDOperand.Val == N - N was replaced, is dead, and is already handled. 172 // otherwise - N should be replaced by the returned Operand. 173 // 174 SDOperand visitTokenFactor(SDNode *N); 175 SDOperand visitADD(SDNode *N); 176 SDOperand visitSUB(SDNode *N); 177 SDOperand visitMUL(SDNode *N); 178 SDOperand visitSDIV(SDNode *N); 179 SDOperand visitUDIV(SDNode *N); 180 SDOperand visitSREM(SDNode *N); 181 SDOperand visitUREM(SDNode *N); 182 SDOperand visitMULHU(SDNode *N); 183 SDOperand visitMULHS(SDNode *N); 184 SDOperand visitAND(SDNode *N); 185 SDOperand visitOR(SDNode *N); 186 SDOperand visitXOR(SDNode *N); 187 SDOperand visitVBinOp(SDNode *N, ISD::NodeType IntOp, ISD::NodeType FPOp); 188 SDOperand visitSHL(SDNode *N); 189 SDOperand visitSRA(SDNode *N); 190 SDOperand visitSRL(SDNode *N); 191 SDOperand visitCTLZ(SDNode *N); 192 SDOperand visitCTTZ(SDNode *N); 193 SDOperand visitCTPOP(SDNode *N); 194 SDOperand visitSELECT(SDNode *N); 195 SDOperand visitSELECT_CC(SDNode *N); 196 SDOperand visitSETCC(SDNode *N); 197 SDOperand visitSIGN_EXTEND(SDNode *N); 198 SDOperand visitZERO_EXTEND(SDNode *N); 199 SDOperand visitANY_EXTEND(SDNode *N); 200 SDOperand visitSIGN_EXTEND_INREG(SDNode *N); 201 SDOperand visitTRUNCATE(SDNode *N); 202 SDOperand visitBIT_CONVERT(SDNode *N); 203 SDOperand visitVBIT_CONVERT(SDNode *N); 204 SDOperand visitFADD(SDNode *N); 205 SDOperand visitFSUB(SDNode *N); 206 SDOperand visitFMUL(SDNode *N); 207 SDOperand visitFDIV(SDNode *N); 208 SDOperand visitFREM(SDNode *N); 209 SDOperand visitFCOPYSIGN(SDNode *N); 210 SDOperand visitSINT_TO_FP(SDNode *N); 211 SDOperand visitUINT_TO_FP(SDNode *N); 212 SDOperand visitFP_TO_SINT(SDNode *N); 213 SDOperand visitFP_TO_UINT(SDNode *N); 214 SDOperand visitFP_ROUND(SDNode *N); 215 SDOperand visitFP_ROUND_INREG(SDNode *N); 216 SDOperand visitFP_EXTEND(SDNode *N); 217 SDOperand visitFNEG(SDNode *N); 218 SDOperand visitFABS(SDNode *N); 219 SDOperand visitBRCOND(SDNode *N); 220 SDOperand visitBR_CC(SDNode *N); 221 SDOperand visitLOAD(SDNode *N); 222 SDOperand visitXEXTLOAD(SDNode *N); 223 SDOperand visitSTORE(SDNode *N); 224 SDOperand visitINSERT_VECTOR_ELT(SDNode *N); 225 SDOperand visitVINSERT_VECTOR_ELT(SDNode *N); 226 SDOperand visitVBUILD_VECTOR(SDNode *N); 227 SDOperand visitVECTOR_SHUFFLE(SDNode *N); 228 SDOperand visitVVECTOR_SHUFFLE(SDNode *N); 229 230 SDOperand XformToShuffleWithZero(SDNode *N); 231 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS); 232 233 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS); 234 SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N); 235 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2); 236 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2, 237 SDOperand N3, ISD::CondCode CC); 238 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, 239 ISD::CondCode Cond, bool foldBooleans = true); 240 SDOperand ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *, MVT::ValueType); 241 SDOperand BuildSDIV(SDNode *N); 242 SDOperand BuildUDIV(SDNode *N); 243 SDNode *MatchRotate(SDOperand LHS, SDOperand RHS); 244 bool isNotAlias(SDOperand Ptr1, SDOperand Ptr2); 245public: 246 DAGCombiner(SelectionDAG &D) 247 : DAG(D), TLI(D.getTargetLoweringInfo()), AfterLegalize(false) {} 248 249 /// Run - runs the dag combiner on all nodes in the work list 250 void Run(bool RunningAfterLegalize); 251 }; 252} 253 254//===----------------------------------------------------------------------===// 255// TargetLowering::DAGCombinerInfo implementation 256//===----------------------------------------------------------------------===// 257 258void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 259 ((DAGCombiner*)DC)->AddToWorkList(N); 260} 261 262SDOperand TargetLowering::DAGCombinerInfo:: 263CombineTo(SDNode *N, const std::vector<SDOperand> &To) { 264 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size()); 265} 266 267SDOperand TargetLowering::DAGCombinerInfo:: 268CombineTo(SDNode *N, SDOperand Res) { 269 return ((DAGCombiner*)DC)->CombineTo(N, Res); 270} 271 272 273SDOperand TargetLowering::DAGCombinerInfo:: 274CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) { 275 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1); 276} 277 278 279 280 281//===----------------------------------------------------------------------===// 282 283 284// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 285// that selects between the values 1 and 0, making it equivalent to a setcc. 286// Also, set the incoming LHS, RHS, and CC references to the appropriate 287// nodes based on the type of node we are checking. This simplifies life a 288// bit for the callers. 289static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS, 290 SDOperand &CC) { 291 if (N.getOpcode() == ISD::SETCC) { 292 LHS = N.getOperand(0); 293 RHS = N.getOperand(1); 294 CC = N.getOperand(2); 295 return true; 296 } 297 if (N.getOpcode() == ISD::SELECT_CC && 298 N.getOperand(2).getOpcode() == ISD::Constant && 299 N.getOperand(3).getOpcode() == ISD::Constant && 300 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 && 301 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 302 LHS = N.getOperand(0); 303 RHS = N.getOperand(1); 304 CC = N.getOperand(4); 305 return true; 306 } 307 return false; 308} 309 310// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 311// one use. If this is true, it allows the users to invert the operation for 312// free when it is profitable to do so. 313static bool isOneUseSetCC(SDOperand N) { 314 SDOperand N0, N1, N2; 315 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse()) 316 return true; 317 return false; 318} 319 320SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){ 321 MVT::ValueType VT = N0.getValueType(); 322 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 323 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 324 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 325 if (isa<ConstantSDNode>(N1)) { 326 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1); 327 AddToWorkList(OpNode.Val); 328 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0)); 329 } else if (N0.hasOneUse()) { 330 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1); 331 AddToWorkList(OpNode.Val); 332 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1)); 333 } 334 } 335 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 336 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 337 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 338 if (isa<ConstantSDNode>(N0)) { 339 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0); 340 AddToWorkList(OpNode.Val); 341 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0)); 342 } else if (N1.hasOneUse()) { 343 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0); 344 AddToWorkList(OpNode.Val); 345 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1)); 346 } 347 } 348 return SDOperand(); 349} 350 351void DAGCombiner::Run(bool RunningAfterLegalize) { 352 // set the instance variable, so that the various visit routines may use it. 353 AfterLegalize = RunningAfterLegalize; 354 355 // Add all the dag nodes to the worklist. 356 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 357 E = DAG.allnodes_end(); I != E; ++I) 358 WorkList.push_back(I); 359 360 // Create a dummy node (which is not added to allnodes), that adds a reference 361 // to the root node, preventing it from being deleted, and tracking any 362 // changes of the root. 363 HandleSDNode Dummy(DAG.getRoot()); 364 365 366 /// DagCombineInfo - Expose the DAG combiner to the target combiner impls. 367 TargetLowering::DAGCombinerInfo 368 DagCombineInfo(DAG, !RunningAfterLegalize, this); 369 370 // while the worklist isn't empty, inspect the node on the end of it and 371 // try and combine it. 372 while (!WorkList.empty()) { 373 SDNode *N = WorkList.back(); 374 WorkList.pop_back(); 375 376 // If N has no uses, it is dead. Make sure to revisit all N's operands once 377 // N is deleted from the DAG, since they too may now be dead or may have a 378 // reduced number of uses, allowing other xforms. 379 if (N->use_empty() && N != &Dummy) { 380 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 381 WorkList.push_back(N->getOperand(i).Val); 382 383 removeFromWorkList(N); 384 DAG.DeleteNode(N); 385 continue; 386 } 387 388 SDOperand RV = visit(N); 389 390 // If nothing happened, try a target-specific DAG combine. 391 if (RV.Val == 0) { 392 assert(N->getOpcode() != ISD::DELETED_NODE && 393 "Node was deleted but visit returned NULL!"); 394 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 395 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) 396 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 397 } 398 399 if (RV.Val) { 400 ++NodesCombined; 401 // If we get back the same node we passed in, rather than a new node or 402 // zero, we know that the node must have defined multiple values and 403 // CombineTo was used. Since CombineTo takes care of the worklist 404 // mechanics for us, we have no work to do in this case. 405 if (RV.Val != N) { 406 assert(N->getOpcode() != ISD::DELETED_NODE && 407 RV.Val->getOpcode() != ISD::DELETED_NODE && 408 "Node was deleted but visit returned new node!"); 409 410 DEBUG(std::cerr << "\nReplacing "; N->dump(); 411 std::cerr << "\nWith: "; RV.Val->dump(&DAG); 412 std::cerr << '\n'); 413 std::vector<SDNode*> NowDead; 414 SDOperand OpV = RV; 415 DAG.ReplaceAllUsesWith(N, &OpV, &NowDead); 416 417 // Push the new node and any users onto the worklist 418 WorkList.push_back(RV.Val); 419 AddUsersToWorkList(RV.Val); 420 421 // Nodes can end up on the worklist more than once. Make sure we do 422 // not process a node that has been replaced. 423 removeFromWorkList(N); 424 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 425 removeFromWorkList(NowDead[i]); 426 427 // Finally, since the node is now dead, remove it from the graph. 428 DAG.DeleteNode(N); 429 } 430 } 431 } 432 433 // If the root changed (e.g. it was a dead load, update the root). 434 DAG.setRoot(Dummy.getValue()); 435} 436 437SDOperand DAGCombiner::visit(SDNode *N) { 438 switch(N->getOpcode()) { 439 default: break; 440 case ISD::TokenFactor: return visitTokenFactor(N); 441 case ISD::ADD: return visitADD(N); 442 case ISD::SUB: return visitSUB(N); 443 case ISD::MUL: return visitMUL(N); 444 case ISD::SDIV: return visitSDIV(N); 445 case ISD::UDIV: return visitUDIV(N); 446 case ISD::SREM: return visitSREM(N); 447 case ISD::UREM: return visitUREM(N); 448 case ISD::MULHU: return visitMULHU(N); 449 case ISD::MULHS: return visitMULHS(N); 450 case ISD::AND: return visitAND(N); 451 case ISD::OR: return visitOR(N); 452 case ISD::XOR: return visitXOR(N); 453 case ISD::SHL: return visitSHL(N); 454 case ISD::SRA: return visitSRA(N); 455 case ISD::SRL: return visitSRL(N); 456 case ISD::CTLZ: return visitCTLZ(N); 457 case ISD::CTTZ: return visitCTTZ(N); 458 case ISD::CTPOP: return visitCTPOP(N); 459 case ISD::SELECT: return visitSELECT(N); 460 case ISD::SELECT_CC: return visitSELECT_CC(N); 461 case ISD::SETCC: return visitSETCC(N); 462 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 463 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 464 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 465 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 466 case ISD::TRUNCATE: return visitTRUNCATE(N); 467 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 468 case ISD::VBIT_CONVERT: return visitVBIT_CONVERT(N); 469 case ISD::FADD: return visitFADD(N); 470 case ISD::FSUB: return visitFSUB(N); 471 case ISD::FMUL: return visitFMUL(N); 472 case ISD::FDIV: return visitFDIV(N); 473 case ISD::FREM: return visitFREM(N); 474 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 475 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 476 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 477 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 478 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 479 case ISD::FP_ROUND: return visitFP_ROUND(N); 480 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 481 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 482 case ISD::FNEG: return visitFNEG(N); 483 case ISD::FABS: return visitFABS(N); 484 case ISD::BRCOND: return visitBRCOND(N); 485 case ISD::BR_CC: return visitBR_CC(N); 486 case ISD::LOAD: return visitLOAD(N); 487 case ISD::EXTLOAD: 488 case ISD::SEXTLOAD: 489 case ISD::ZEXTLOAD: return visitXEXTLOAD(N); 490 case ISD::STORE: return visitSTORE(N); 491 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 492 case ISD::VINSERT_VECTOR_ELT: return visitVINSERT_VECTOR_ELT(N); 493 case ISD::VBUILD_VECTOR: return visitVBUILD_VECTOR(N); 494 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 495 case ISD::VVECTOR_SHUFFLE: return visitVVECTOR_SHUFFLE(N); 496 case ISD::VADD: return visitVBinOp(N, ISD::ADD , ISD::FADD); 497 case ISD::VSUB: return visitVBinOp(N, ISD::SUB , ISD::FSUB); 498 case ISD::VMUL: return visitVBinOp(N, ISD::MUL , ISD::FMUL); 499 case ISD::VSDIV: return visitVBinOp(N, ISD::SDIV, ISD::FDIV); 500 case ISD::VUDIV: return visitVBinOp(N, ISD::UDIV, ISD::UDIV); 501 case ISD::VAND: return visitVBinOp(N, ISD::AND , ISD::AND); 502 case ISD::VOR: return visitVBinOp(N, ISD::OR , ISD::OR); 503 case ISD::VXOR: return visitVBinOp(N, ISD::XOR , ISD::XOR); 504 } 505 return SDOperand(); 506} 507 508SDOperand DAGCombiner::visitTokenFactor(SDNode *N) { 509 SmallVector<SDOperand, 8> Ops; 510 bool Changed = false; 511 512 // If the token factor has two operands and one is the entry token, replace 513 // the token factor with the other operand. 514 if (N->getNumOperands() == 2) { 515 if (N->getOperand(0).getOpcode() == ISD::EntryToken || 516 N->getOperand(0) == N->getOperand(1)) 517 return N->getOperand(1); 518 if (N->getOperand(1).getOpcode() == ISD::EntryToken) 519 return N->getOperand(0); 520 } 521 522 // fold (tokenfactor (tokenfactor)) -> tokenfactor 523 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 524 SDOperand Op = N->getOperand(i); 525 if (Op.getOpcode() == ISD::TokenFactor && Op.hasOneUse()) { 526 AddToWorkList(Op.Val); // Remove dead node. 527 Changed = true; 528 for (unsigned j = 0, e = Op.getNumOperands(); j != e; ++j) 529 Ops.push_back(Op.getOperand(j)); 530 } else if (i == 0 || N->getOperand(i) != N->getOperand(i-1)) { 531 Ops.push_back(Op); 532 } else { 533 // Deleted an operand that was the same as the last one. 534 Changed = true; 535 } 536 } 537 if (Changed) 538 return DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size()); 539 return SDOperand(); 540} 541 542SDOperand DAGCombiner::visitADD(SDNode *N) { 543 SDOperand N0 = N->getOperand(0); 544 SDOperand N1 = N->getOperand(1); 545 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 546 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 547 MVT::ValueType VT = N0.getValueType(); 548 549 // fold (add c1, c2) -> c1+c2 550 if (N0C && N1C) 551 return DAG.getNode(ISD::ADD, VT, N0, N1); 552 // canonicalize constant to RHS 553 if (N0C && !N1C) 554 return DAG.getNode(ISD::ADD, VT, N1, N0); 555 // fold (add x, 0) -> x 556 if (N1C && N1C->isNullValue()) 557 return N0; 558 // fold ((c1-A)+c2) -> (c1+c2)-A 559 if (N1C && N0.getOpcode() == ISD::SUB) 560 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 561 return DAG.getNode(ISD::SUB, VT, 562 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT), 563 N0.getOperand(1)); 564 // reassociate add 565 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1); 566 if (RADD.Val != 0) 567 return RADD; 568 // fold ((0-A) + B) -> B-A 569 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 570 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 571 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1)); 572 // fold (A + (0-B)) -> A-B 573 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 574 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 575 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1)); 576 // fold (A+(B-A)) -> B 577 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 578 return N1.getOperand(0); 579 580 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0))) 581 return SDOperand(N, 0); 582 583 // fold (a+b) -> (a|b) iff a and b share no bits. 584 if (MVT::isInteger(VT) && !MVT::isVector(VT)) { 585 uint64_t LHSZero, LHSOne; 586 uint64_t RHSZero, RHSOne; 587 uint64_t Mask = MVT::getIntVTBitMask(VT); 588 TLI.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 589 if (LHSZero) { 590 TLI.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 591 592 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 593 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 594 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 595 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 596 return DAG.getNode(ISD::OR, VT, N0, N1); 597 } 598 } 599 600 return SDOperand(); 601} 602 603SDOperand DAGCombiner::visitSUB(SDNode *N) { 604 SDOperand N0 = N->getOperand(0); 605 SDOperand N1 = N->getOperand(1); 606 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 607 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 608 MVT::ValueType VT = N0.getValueType(); 609 610 // fold (sub x, x) -> 0 611 if (N0 == N1) 612 return DAG.getConstant(0, N->getValueType(0)); 613 // fold (sub c1, c2) -> c1-c2 614 if (N0C && N1C) 615 return DAG.getNode(ISD::SUB, VT, N0, N1); 616 // fold (sub x, c) -> (add x, -c) 617 if (N1C) 618 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT)); 619 // fold (A+B)-A -> B 620 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 621 return N0.getOperand(1); 622 // fold (A+B)-B -> A 623 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 624 return N0.getOperand(0); 625 return SDOperand(); 626} 627 628SDOperand DAGCombiner::visitMUL(SDNode *N) { 629 SDOperand N0 = N->getOperand(0); 630 SDOperand N1 = N->getOperand(1); 631 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 632 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 633 MVT::ValueType VT = N0.getValueType(); 634 635 // fold (mul c1, c2) -> c1*c2 636 if (N0C && N1C) 637 return DAG.getNode(ISD::MUL, VT, N0, N1); 638 // canonicalize constant to RHS 639 if (N0C && !N1C) 640 return DAG.getNode(ISD::MUL, VT, N1, N0); 641 // fold (mul x, 0) -> 0 642 if (N1C && N1C->isNullValue()) 643 return N1; 644 // fold (mul x, -1) -> 0-x 645 if (N1C && N1C->isAllOnesValue()) 646 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 647 // fold (mul x, (1 << c)) -> x << c 648 if (N1C && isPowerOf2_64(N1C->getValue())) 649 return DAG.getNode(ISD::SHL, VT, N0, 650 DAG.getConstant(Log2_64(N1C->getValue()), 651 TLI.getShiftAmountTy())); 652 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 653 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) { 654 // FIXME: If the input is something that is easily negated (e.g. a 655 // single-use add), we should put the negate there. 656 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), 657 DAG.getNode(ISD::SHL, VT, N0, 658 DAG.getConstant(Log2_64(-N1C->getSignExtended()), 659 TLI.getShiftAmountTy()))); 660 } 661 662 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 663 if (N1C && N0.getOpcode() == ISD::SHL && 664 isa<ConstantSDNode>(N0.getOperand(1))) { 665 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1)); 666 AddToWorkList(C3.Val); 667 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3); 668 } 669 670 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 671 // use. 672 { 673 SDOperand Sh(0,0), Y(0,0); 674 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 675 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 676 N0.Val->hasOneUse()) { 677 Sh = N0; Y = N1; 678 } else if (N1.getOpcode() == ISD::SHL && 679 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) { 680 Sh = N1; Y = N0; 681 } 682 if (Sh.Val) { 683 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y); 684 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1)); 685 } 686 } 687 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 688 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() && 689 isa<ConstantSDNode>(N0.getOperand(1))) { 690 return DAG.getNode(ISD::ADD, VT, 691 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1), 692 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1)); 693 } 694 695 // reassociate mul 696 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1); 697 if (RMUL.Val != 0) 698 return RMUL; 699 return SDOperand(); 700} 701 702SDOperand DAGCombiner::visitSDIV(SDNode *N) { 703 SDOperand N0 = N->getOperand(0); 704 SDOperand N1 = N->getOperand(1); 705 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 706 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 707 MVT::ValueType VT = N->getValueType(0); 708 709 // fold (sdiv c1, c2) -> c1/c2 710 if (N0C && N1C && !N1C->isNullValue()) 711 return DAG.getNode(ISD::SDIV, VT, N0, N1); 712 // fold (sdiv X, 1) -> X 713 if (N1C && N1C->getSignExtended() == 1LL) 714 return N0; 715 // fold (sdiv X, -1) -> 0-X 716 if (N1C && N1C->isAllOnesValue()) 717 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 718 // If we know the sign bits of both operands are zero, strength reduce to a 719 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 720 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 721 if (TLI.MaskedValueIsZero(N1, SignBit) && 722 TLI.MaskedValueIsZero(N0, SignBit)) 723 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1); 724 // fold (sdiv X, pow2) -> simple ops after legalize 725 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() && 726 (isPowerOf2_64(N1C->getSignExtended()) || 727 isPowerOf2_64(-N1C->getSignExtended()))) { 728 // If dividing by powers of two is cheap, then don't perform the following 729 // fold. 730 if (TLI.isPow2DivCheap()) 731 return SDOperand(); 732 int64_t pow2 = N1C->getSignExtended(); 733 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 734 unsigned lg2 = Log2_64(abs2); 735 // Splat the sign bit into the register 736 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0, 737 DAG.getConstant(MVT::getSizeInBits(VT)-1, 738 TLI.getShiftAmountTy())); 739 AddToWorkList(SGN.Val); 740 // Add (N0 < 0) ? abs2 - 1 : 0; 741 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN, 742 DAG.getConstant(MVT::getSizeInBits(VT)-lg2, 743 TLI.getShiftAmountTy())); 744 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL); 745 AddToWorkList(SRL.Val); 746 AddToWorkList(ADD.Val); // Divide by pow2 747 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD, 748 DAG.getConstant(lg2, TLI.getShiftAmountTy())); 749 // If we're dividing by a positive value, we're done. Otherwise, we must 750 // negate the result. 751 if (pow2 > 0) 752 return SRA; 753 AddToWorkList(SRA.Val); 754 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA); 755 } 756 // if integer divide is expensive and we satisfy the requirements, emit an 757 // alternate sequence. 758 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) && 759 !TLI.isIntDivCheap()) { 760 SDOperand Op = BuildSDIV(N); 761 if (Op.Val) return Op; 762 } 763 return SDOperand(); 764} 765 766SDOperand DAGCombiner::visitUDIV(SDNode *N) { 767 SDOperand N0 = N->getOperand(0); 768 SDOperand N1 = N->getOperand(1); 769 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 770 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 771 MVT::ValueType VT = N->getValueType(0); 772 773 // fold (udiv c1, c2) -> c1/c2 774 if (N0C && N1C && !N1C->isNullValue()) 775 return DAG.getNode(ISD::UDIV, VT, N0, N1); 776 // fold (udiv x, (1 << c)) -> x >>u c 777 if (N1C && isPowerOf2_64(N1C->getValue())) 778 return DAG.getNode(ISD::SRL, VT, N0, 779 DAG.getConstant(Log2_64(N1C->getValue()), 780 TLI.getShiftAmountTy())); 781 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 782 if (N1.getOpcode() == ISD::SHL) { 783 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 784 if (isPowerOf2_64(SHC->getValue())) { 785 MVT::ValueType ADDVT = N1.getOperand(1).getValueType(); 786 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1), 787 DAG.getConstant(Log2_64(SHC->getValue()), 788 ADDVT)); 789 AddToWorkList(Add.Val); 790 return DAG.getNode(ISD::SRL, VT, N0, Add); 791 } 792 } 793 } 794 // fold (udiv x, c) -> alternate 795 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) { 796 SDOperand Op = BuildUDIV(N); 797 if (Op.Val) return Op; 798 } 799 return SDOperand(); 800} 801 802SDOperand DAGCombiner::visitSREM(SDNode *N) { 803 SDOperand N0 = N->getOperand(0); 804 SDOperand N1 = N->getOperand(1); 805 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 806 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 807 MVT::ValueType VT = N->getValueType(0); 808 809 // fold (srem c1, c2) -> c1%c2 810 if (N0C && N1C && !N1C->isNullValue()) 811 return DAG.getNode(ISD::SREM, VT, N0, N1); 812 // If we know the sign bits of both operands are zero, strength reduce to a 813 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 814 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 815 if (TLI.MaskedValueIsZero(N1, SignBit) && 816 TLI.MaskedValueIsZero(N0, SignBit)) 817 return DAG.getNode(ISD::UREM, VT, N0, N1); 818 return SDOperand(); 819} 820 821SDOperand DAGCombiner::visitUREM(SDNode *N) { 822 SDOperand N0 = N->getOperand(0); 823 SDOperand N1 = N->getOperand(1); 824 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 825 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 826 MVT::ValueType VT = N->getValueType(0); 827 828 // fold (urem c1, c2) -> c1%c2 829 if (N0C && N1C && !N1C->isNullValue()) 830 return DAG.getNode(ISD::UREM, VT, N0, N1); 831 // fold (urem x, pow2) -> (and x, pow2-1) 832 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue())) 833 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT)); 834 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 835 if (N1.getOpcode() == ISD::SHL) { 836 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 837 if (isPowerOf2_64(SHC->getValue())) { 838 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT)); 839 AddToWorkList(Add.Val); 840 return DAG.getNode(ISD::AND, VT, N0, Add); 841 } 842 } 843 } 844 return SDOperand(); 845} 846 847SDOperand DAGCombiner::visitMULHS(SDNode *N) { 848 SDOperand N0 = N->getOperand(0); 849 SDOperand N1 = N->getOperand(1); 850 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 851 852 // fold (mulhs x, 0) -> 0 853 if (N1C && N1C->isNullValue()) 854 return N1; 855 // fold (mulhs x, 1) -> (sra x, size(x)-1) 856 if (N1C && N1C->getValue() == 1) 857 return DAG.getNode(ISD::SRA, N0.getValueType(), N0, 858 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1, 859 TLI.getShiftAmountTy())); 860 return SDOperand(); 861} 862 863SDOperand DAGCombiner::visitMULHU(SDNode *N) { 864 SDOperand N0 = N->getOperand(0); 865 SDOperand N1 = N->getOperand(1); 866 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 867 868 // fold (mulhu x, 0) -> 0 869 if (N1C && N1C->isNullValue()) 870 return N1; 871 // fold (mulhu x, 1) -> 0 872 if (N1C && N1C->getValue() == 1) 873 return DAG.getConstant(0, N0.getValueType()); 874 return SDOperand(); 875} 876 877/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 878/// two operands of the same opcode, try to simplify it. 879SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 880 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1); 881 MVT::ValueType VT = N0.getValueType(); 882 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 883 884 // For each of OP in AND/OR/XOR: 885 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 886 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 887 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 888 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) 889 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND|| 890 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) && 891 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 892 SDOperand ORNode = DAG.getNode(N->getOpcode(), 893 N0.getOperand(0).getValueType(), 894 N0.getOperand(0), N1.getOperand(0)); 895 AddToWorkList(ORNode.Val); 896 return DAG.getNode(N0.getOpcode(), VT, ORNode); 897 } 898 899 // For each of OP in SHL/SRL/SRA/AND... 900 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 901 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 902 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 903 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 904 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 905 N0.getOperand(1) == N1.getOperand(1)) { 906 SDOperand ORNode = DAG.getNode(N->getOpcode(), 907 N0.getOperand(0).getValueType(), 908 N0.getOperand(0), N1.getOperand(0)); 909 AddToWorkList(ORNode.Val); 910 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1)); 911 } 912 913 return SDOperand(); 914} 915 916SDOperand DAGCombiner::visitAND(SDNode *N) { 917 SDOperand N0 = N->getOperand(0); 918 SDOperand N1 = N->getOperand(1); 919 SDOperand LL, LR, RL, RR, CC0, CC1; 920 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 921 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 922 MVT::ValueType VT = N1.getValueType(); 923 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 924 925 // fold (and c1, c2) -> c1&c2 926 if (N0C && N1C) 927 return DAG.getNode(ISD::AND, VT, N0, N1); 928 // canonicalize constant to RHS 929 if (N0C && !N1C) 930 return DAG.getNode(ISD::AND, VT, N1, N0); 931 // fold (and x, -1) -> x 932 if (N1C && N1C->isAllOnesValue()) 933 return N0; 934 // if (and x, c) is known to be zero, return 0 935 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) 936 return DAG.getConstant(0, VT); 937 // reassociate and 938 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1); 939 if (RAND.Val != 0) 940 return RAND; 941 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 942 if (N1C && N0.getOpcode() == ISD::OR) 943 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 944 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue()) 945 return N1; 946 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 947 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 948 unsigned InMask = MVT::getIntVTBitMask(N0.getOperand(0).getValueType()); 949 if (TLI.MaskedValueIsZero(N0.getOperand(0), 950 ~N1C->getValue() & InMask)) { 951 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(), 952 N0.getOperand(0)); 953 954 // Replace uses of the AND with uses of the Zero extend node. 955 CombineTo(N, Zext); 956 957 // We actually want to replace all uses of the any_extend with the 958 // zero_extend, to avoid duplicating things. This will later cause this 959 // AND to be folded. 960 CombineTo(N0.Val, Zext); 961 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 962 } 963 } 964 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 965 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 966 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 967 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 968 969 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 970 MVT::isInteger(LL.getValueType())) { 971 // fold (X == 0) & (Y == 0) -> (X|Y == 0) 972 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) { 973 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 974 AddToWorkList(ORNode.Val); 975 return DAG.getSetCC(VT, ORNode, LR, Op1); 976 } 977 // fold (X == -1) & (Y == -1) -> (X&Y == -1) 978 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 979 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 980 AddToWorkList(ANDNode.Val); 981 return DAG.getSetCC(VT, ANDNode, LR, Op1); 982 } 983 // fold (X > -1) & (Y > -1) -> (X|Y > -1) 984 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 985 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 986 AddToWorkList(ORNode.Val); 987 return DAG.getSetCC(VT, ORNode, LR, Op1); 988 } 989 } 990 // canonicalize equivalent to ll == rl 991 if (LL == RR && LR == RL) { 992 Op1 = ISD::getSetCCSwappedOperands(Op1); 993 std::swap(RL, RR); 994 } 995 if (LL == RL && LR == RR) { 996 bool isInteger = MVT::isInteger(LL.getValueType()); 997 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 998 if (Result != ISD::SETCC_INVALID) 999 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1000 } 1001 } 1002 1003 // Simplify: and (op x...), (op y...) -> (op (and x, y)) 1004 if (N0.getOpcode() == N1.getOpcode()) { 1005 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1006 if (Tmp.Val) return Tmp; 1007 } 1008 1009 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1010 // fold (and (sra)) -> (and (srl)) when possible. 1011 if (!MVT::isVector(VT) && 1012 SimplifyDemandedBits(SDOperand(N, 0))) 1013 return SDOperand(N, 0); 1014 // fold (zext_inreg (extload x)) -> (zextload x) 1015 if (N0.getOpcode() == ISD::EXTLOAD) { 1016 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT(); 1017 // If we zero all the possible extended bits, then we can turn this into 1018 // a zextload if we are running before legalize or the operation is legal. 1019 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && 1020 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) { 1021 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), 1022 N0.getOperand(1), N0.getOperand(2), 1023 EVT); 1024 AddToWorkList(N); 1025 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1026 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1027 } 1028 } 1029 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1030 if (N0.getOpcode() == ISD::SEXTLOAD && N0.hasOneUse()) { 1031 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT(); 1032 // If we zero all the possible extended bits, then we can turn this into 1033 // a zextload if we are running before legalize or the operation is legal. 1034 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && 1035 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) { 1036 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), 1037 N0.getOperand(1), N0.getOperand(2), 1038 EVT); 1039 AddToWorkList(N); 1040 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1041 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1042 } 1043 } 1044 1045 // fold (and (load x), 255) -> (zextload x, i8) 1046 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1047 if (N1C && 1048 (N0.getOpcode() == ISD::LOAD || N0.getOpcode() == ISD::EXTLOAD || 1049 N0.getOpcode() == ISD::ZEXTLOAD) && 1050 N0.hasOneUse()) { 1051 MVT::ValueType EVT, LoadedVT; 1052 if (N1C->getValue() == 255) 1053 EVT = MVT::i8; 1054 else if (N1C->getValue() == 65535) 1055 EVT = MVT::i16; 1056 else if (N1C->getValue() == ~0U) 1057 EVT = MVT::i32; 1058 else 1059 EVT = MVT::Other; 1060 1061 LoadedVT = N0.getOpcode() == ISD::LOAD ? VT : 1062 cast<VTSDNode>(N0.getOperand(3))->getVT(); 1063 if (EVT != MVT::Other && LoadedVT > EVT && 1064 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) { 1065 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 1066 // For big endian targets, we need to add an offset to the pointer to load 1067 // the correct bytes. For little endian systems, we merely need to read 1068 // fewer bytes from the same pointer. 1069 unsigned PtrOff = 1070 (MVT::getSizeInBits(LoadedVT) - MVT::getSizeInBits(EVT)) / 8; 1071 SDOperand NewPtr = N0.getOperand(1); 1072 if (!TLI.isLittleEndian()) 1073 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, 1074 DAG.getConstant(PtrOff, PtrType)); 1075 AddToWorkList(NewPtr.Val); 1076 SDOperand Load = 1077 DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), NewPtr, 1078 N0.getOperand(2), EVT); 1079 AddToWorkList(N); 1080 CombineTo(N0.Val, Load, Load.getValue(1)); 1081 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1082 } 1083 } 1084 1085 return SDOperand(); 1086} 1087 1088SDOperand DAGCombiner::visitOR(SDNode *N) { 1089 SDOperand N0 = N->getOperand(0); 1090 SDOperand N1 = N->getOperand(1); 1091 SDOperand LL, LR, RL, RR, CC0, CC1; 1092 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1093 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1094 MVT::ValueType VT = N1.getValueType(); 1095 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1096 1097 // fold (or c1, c2) -> c1|c2 1098 if (N0C && N1C) 1099 return DAG.getNode(ISD::OR, VT, N0, N1); 1100 // canonicalize constant to RHS 1101 if (N0C && !N1C) 1102 return DAG.getNode(ISD::OR, VT, N1, N0); 1103 // fold (or x, 0) -> x 1104 if (N1C && N1C->isNullValue()) 1105 return N0; 1106 // fold (or x, -1) -> -1 1107 if (N1C && N1C->isAllOnesValue()) 1108 return N1; 1109 // fold (or x, c) -> c iff (x & ~c) == 0 1110 if (N1C && 1111 TLI.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)))) 1112 return N1; 1113 // reassociate or 1114 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1); 1115 if (ROR.Val != 0) 1116 return ROR; 1117 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 1118 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() && 1119 isa<ConstantSDNode>(N0.getOperand(1))) { 1120 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 1121 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0), 1122 N1), 1123 DAG.getConstant(N1C->getValue() | C1->getValue(), VT)); 1124 } 1125 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 1126 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1127 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1128 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1129 1130 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1131 MVT::isInteger(LL.getValueType())) { 1132 // fold (X != 0) | (Y != 0) -> (X|Y != 0) 1133 // fold (X < 0) | (Y < 0) -> (X|Y < 0) 1134 if (cast<ConstantSDNode>(LR)->getValue() == 0 && 1135 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 1136 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1137 AddToWorkList(ORNode.Val); 1138 return DAG.getSetCC(VT, ORNode, LR, Op1); 1139 } 1140 // fold (X != -1) | (Y != -1) -> (X&Y != -1) 1141 // fold (X > -1) | (Y > -1) -> (X&Y > -1) 1142 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 1143 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 1144 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1145 AddToWorkList(ANDNode.Val); 1146 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1147 } 1148 } 1149 // canonicalize equivalent to ll == rl 1150 if (LL == RR && LR == RL) { 1151 Op1 = ISD::getSetCCSwappedOperands(Op1); 1152 std::swap(RL, RR); 1153 } 1154 if (LL == RL && LR == RR) { 1155 bool isInteger = MVT::isInteger(LL.getValueType()); 1156 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 1157 if (Result != ISD::SETCC_INVALID) 1158 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1159 } 1160 } 1161 1162 // Simplify: or (op x...), (op y...) -> (op (or x, y)) 1163 if (N0.getOpcode() == N1.getOpcode()) { 1164 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1165 if (Tmp.Val) return Tmp; 1166 } 1167 1168 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible. 1169 if (N0.getOpcode() == ISD::AND && 1170 N1.getOpcode() == ISD::AND && 1171 N0.getOperand(1).getOpcode() == ISD::Constant && 1172 N1.getOperand(1).getOpcode() == ISD::Constant && 1173 // Don't increase # computations. 1174 (N0.Val->hasOneUse() || N1.Val->hasOneUse())) { 1175 // We can only do this xform if we know that bits from X that are set in C2 1176 // but not in C1 are already zero. Likewise for Y. 1177 uint64_t LHSMask = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1178 uint64_t RHSMask = cast<ConstantSDNode>(N1.getOperand(1))->getValue(); 1179 1180 if (TLI.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 1181 TLI.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 1182 SDOperand X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0)); 1183 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT)); 1184 } 1185 } 1186 1187 1188 // See if this is some rotate idiom. 1189 if (SDNode *Rot = MatchRotate(N0, N1)) 1190 return SDOperand(Rot, 0); 1191 1192 return SDOperand(); 1193} 1194 1195 1196/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 1197static bool MatchRotateHalf(SDOperand Op, SDOperand &Shift, SDOperand &Mask) { 1198 if (Op.getOpcode() == ISD::AND) { 1199 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1200 Mask = Op.getOperand(1); 1201 Op = Op.getOperand(0); 1202 } else { 1203 return false; 1204 } 1205 } 1206 1207 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 1208 Shift = Op; 1209 return true; 1210 } 1211 return false; 1212} 1213 1214 1215// MatchRotate - Handle an 'or' of two operands. If this is one of the many 1216// idioms for rotate, and if the target supports rotation instructions, generate 1217// a rot[lr]. 1218SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) { 1219 // Must be a legal type. Expanded an promoted things won't work with rotates. 1220 MVT::ValueType VT = LHS.getValueType(); 1221 if (!TLI.isTypeLegal(VT)) return 0; 1222 1223 // The target must have at least one rotate flavor. 1224 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT); 1225 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT); 1226 if (!HasROTL && !HasROTR) return 0; 1227 1228 // Match "(X shl/srl V1) & V2" where V2 may not be present. 1229 SDOperand LHSShift; // The shift. 1230 SDOperand LHSMask; // AND value if any. 1231 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 1232 return 0; // Not part of a rotate. 1233 1234 SDOperand RHSShift; // The shift. 1235 SDOperand RHSMask; // AND value if any. 1236 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 1237 return 0; // Not part of a rotate. 1238 1239 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 1240 return 0; // Not shifting the same value. 1241 1242 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 1243 return 0; // Shifts must disagree. 1244 1245 // Canonicalize shl to left side in a shl/srl pair. 1246 if (RHSShift.getOpcode() == ISD::SHL) { 1247 std::swap(LHS, RHS); 1248 std::swap(LHSShift, RHSShift); 1249 std::swap(LHSMask , RHSMask ); 1250 } 1251 1252 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1253 1254 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 1255 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 1256 if (LHSShift.getOperand(1).getOpcode() == ISD::Constant && 1257 RHSShift.getOperand(1).getOpcode() == ISD::Constant) { 1258 uint64_t LShVal = cast<ConstantSDNode>(LHSShift.getOperand(1))->getValue(); 1259 uint64_t RShVal = cast<ConstantSDNode>(RHSShift.getOperand(1))->getValue(); 1260 if ((LShVal + RShVal) != OpSizeInBits) 1261 return 0; 1262 1263 SDOperand Rot; 1264 if (HasROTL) 1265 Rot = DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0), 1266 LHSShift.getOperand(1)); 1267 else 1268 Rot = DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0), 1269 RHSShift.getOperand(1)); 1270 1271 // If there is an AND of either shifted operand, apply it to the result. 1272 if (LHSMask.Val || RHSMask.Val) { 1273 uint64_t Mask = MVT::getIntVTBitMask(VT); 1274 1275 if (LHSMask.Val) { 1276 uint64_t RHSBits = (1ULL << LShVal)-1; 1277 Mask &= cast<ConstantSDNode>(LHSMask)->getValue() | RHSBits; 1278 } 1279 if (RHSMask.Val) { 1280 uint64_t LHSBits = ~((1ULL << (OpSizeInBits-RShVal))-1); 1281 Mask &= cast<ConstantSDNode>(RHSMask)->getValue() | LHSBits; 1282 } 1283 1284 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT)); 1285 } 1286 1287 return Rot.Val; 1288 } 1289 1290 // If there is a mask here, and we have a variable shift, we can't be sure 1291 // that we're masking out the right stuff. 1292 if (LHSMask.Val || RHSMask.Val) 1293 return 0; 1294 1295 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 1296 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 1297 if (RHSShift.getOperand(1).getOpcode() == ISD::SUB && 1298 LHSShift.getOperand(1) == RHSShift.getOperand(1).getOperand(1)) { 1299 if (ConstantSDNode *SUBC = 1300 dyn_cast<ConstantSDNode>(RHSShift.getOperand(1).getOperand(0))) { 1301 if (SUBC->getValue() == OpSizeInBits) 1302 if (HasROTL) 1303 return DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0), 1304 LHSShift.getOperand(1)).Val; 1305 else 1306 return DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0), 1307 LHSShift.getOperand(1)).Val; 1308 } 1309 } 1310 1311 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 1312 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 1313 if (LHSShift.getOperand(1).getOpcode() == ISD::SUB && 1314 RHSShift.getOperand(1) == LHSShift.getOperand(1).getOperand(1)) { 1315 if (ConstantSDNode *SUBC = 1316 dyn_cast<ConstantSDNode>(LHSShift.getOperand(1).getOperand(0))) { 1317 if (SUBC->getValue() == OpSizeInBits) 1318 if (HasROTL) 1319 return DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0), 1320 LHSShift.getOperand(1)).Val; 1321 else 1322 return DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0), 1323 RHSShift.getOperand(1)).Val; 1324 } 1325 } 1326 1327 return 0; 1328} 1329 1330 1331SDOperand DAGCombiner::visitXOR(SDNode *N) { 1332 SDOperand N0 = N->getOperand(0); 1333 SDOperand N1 = N->getOperand(1); 1334 SDOperand LHS, RHS, CC; 1335 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1336 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1337 MVT::ValueType VT = N0.getValueType(); 1338 1339 // fold (xor c1, c2) -> c1^c2 1340 if (N0C && N1C) 1341 return DAG.getNode(ISD::XOR, VT, N0, N1); 1342 // canonicalize constant to RHS 1343 if (N0C && !N1C) 1344 return DAG.getNode(ISD::XOR, VT, N1, N0); 1345 // fold (xor x, 0) -> x 1346 if (N1C && N1C->isNullValue()) 1347 return N0; 1348 // reassociate xor 1349 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1); 1350 if (RXOR.Val != 0) 1351 return RXOR; 1352 // fold !(x cc y) -> (x !cc y) 1353 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 1354 bool isInt = MVT::isInteger(LHS.getValueType()); 1355 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 1356 isInt); 1357 if (N0.getOpcode() == ISD::SETCC) 1358 return DAG.getSetCC(VT, LHS, RHS, NotCC); 1359 if (N0.getOpcode() == ISD::SELECT_CC) 1360 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC); 1361 assert(0 && "Unhandled SetCC Equivalent!"); 1362 abort(); 1363 } 1364 // fold !(x or y) -> (!x and !y) iff x or y are setcc 1365 if (N1C && N1C->getValue() == 1 && 1366 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 1367 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 1368 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 1369 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 1370 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 1371 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 1372 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 1373 return DAG.getNode(NewOpcode, VT, LHS, RHS); 1374 } 1375 } 1376 // fold !(x or y) -> (!x and !y) iff x or y are constants 1377 if (N1C && N1C->isAllOnesValue() && 1378 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 1379 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 1380 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 1381 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 1382 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 1383 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 1384 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 1385 return DAG.getNode(NewOpcode, VT, LHS, RHS); 1386 } 1387 } 1388 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2) 1389 if (N1C && N0.getOpcode() == ISD::XOR) { 1390 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 1391 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 1392 if (N00C) 1393 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1), 1394 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT)); 1395 if (N01C) 1396 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0), 1397 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT)); 1398 } 1399 // fold (xor x, x) -> 0 1400 if (N0 == N1) { 1401 if (!MVT::isVector(VT)) { 1402 return DAG.getConstant(0, VT); 1403 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 1404 // Produce a vector of zeros. 1405 SDOperand El = DAG.getConstant(0, MVT::getVectorBaseType(VT)); 1406 std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El); 1407 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 1408 } 1409 } 1410 1411 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 1412 if (N0.getOpcode() == N1.getOpcode()) { 1413 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1414 if (Tmp.Val) return Tmp; 1415 } 1416 1417 // Simplify the expression using non-local knowledge. 1418 if (!MVT::isVector(VT) && 1419 SimplifyDemandedBits(SDOperand(N, 0))) 1420 return SDOperand(N, 0); 1421 1422 return SDOperand(); 1423} 1424 1425SDOperand DAGCombiner::visitSHL(SDNode *N) { 1426 SDOperand N0 = N->getOperand(0); 1427 SDOperand N1 = N->getOperand(1); 1428 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1429 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1430 MVT::ValueType VT = N0.getValueType(); 1431 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1432 1433 // fold (shl c1, c2) -> c1<<c2 1434 if (N0C && N1C) 1435 return DAG.getNode(ISD::SHL, VT, N0, N1); 1436 // fold (shl 0, x) -> 0 1437 if (N0C && N0C->isNullValue()) 1438 return N0; 1439 // fold (shl x, c >= size(x)) -> undef 1440 if (N1C && N1C->getValue() >= OpSizeInBits) 1441 return DAG.getNode(ISD::UNDEF, VT); 1442 // fold (shl x, 0) -> x 1443 if (N1C && N1C->isNullValue()) 1444 return N0; 1445 // if (shl x, c) is known to be zero, return 0 1446 if (TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) 1447 return DAG.getConstant(0, VT); 1448 if (SimplifyDemandedBits(SDOperand(N, 0))) 1449 return SDOperand(N, 0); 1450 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2) 1451 if (N1C && N0.getOpcode() == ISD::SHL && 1452 N0.getOperand(1).getOpcode() == ISD::Constant) { 1453 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1454 uint64_t c2 = N1C->getValue(); 1455 if (c1 + c2 > OpSizeInBits) 1456 return DAG.getConstant(0, VT); 1457 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0), 1458 DAG.getConstant(c1 + c2, N1.getValueType())); 1459 } 1460 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or 1461 // (srl (and x, -1 << c1), c1-c2) 1462 if (N1C && N0.getOpcode() == ISD::SRL && 1463 N0.getOperand(1).getOpcode() == ISD::Constant) { 1464 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1465 uint64_t c2 = N1C->getValue(); 1466 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0), 1467 DAG.getConstant(~0ULL << c1, VT)); 1468 if (c2 > c1) 1469 return DAG.getNode(ISD::SHL, VT, Mask, 1470 DAG.getConstant(c2-c1, N1.getValueType())); 1471 else 1472 return DAG.getNode(ISD::SRL, VT, Mask, 1473 DAG.getConstant(c1-c2, N1.getValueType())); 1474 } 1475 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1) 1476 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 1477 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 1478 DAG.getConstant(~0ULL << N1C->getValue(), VT)); 1479 // fold (shl (add x, c1), c2) -> (add (shl x, c2), c1<<c2) 1480 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() && 1481 isa<ConstantSDNode>(N0.getOperand(1))) { 1482 return DAG.getNode(ISD::ADD, VT, 1483 DAG.getNode(ISD::SHL, VT, N0.getOperand(0), N1), 1484 DAG.getNode(ISD::SHL, VT, N0.getOperand(1), N1)); 1485 } 1486 return SDOperand(); 1487} 1488 1489SDOperand DAGCombiner::visitSRA(SDNode *N) { 1490 SDOperand N0 = N->getOperand(0); 1491 SDOperand N1 = N->getOperand(1); 1492 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1493 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1494 MVT::ValueType VT = N0.getValueType(); 1495 1496 // fold (sra c1, c2) -> c1>>c2 1497 if (N0C && N1C) 1498 return DAG.getNode(ISD::SRA, VT, N0, N1); 1499 // fold (sra 0, x) -> 0 1500 if (N0C && N0C->isNullValue()) 1501 return N0; 1502 // fold (sra -1, x) -> -1 1503 if (N0C && N0C->isAllOnesValue()) 1504 return N0; 1505 // fold (sra x, c >= size(x)) -> undef 1506 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT)) 1507 return DAG.getNode(ISD::UNDEF, VT); 1508 // fold (sra x, 0) -> x 1509 if (N1C && N1C->isNullValue()) 1510 return N0; 1511 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 1512 // sext_inreg. 1513 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 1514 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue(); 1515 MVT::ValueType EVT; 1516 switch (LowBits) { 1517 default: EVT = MVT::Other; break; 1518 case 1: EVT = MVT::i1; break; 1519 case 8: EVT = MVT::i8; break; 1520 case 16: EVT = MVT::i16; break; 1521 case 32: EVT = MVT::i32; break; 1522 } 1523 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT)) 1524 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), 1525 DAG.getValueType(EVT)); 1526 } 1527 1528 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2) 1529 if (N1C && N0.getOpcode() == ISD::SRA) { 1530 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1531 unsigned Sum = N1C->getValue() + C1->getValue(); 1532 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1; 1533 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), 1534 DAG.getConstant(Sum, N1C->getValueType(0))); 1535 } 1536 } 1537 1538 // Simplify, based on bits shifted out of the LHS. 1539 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 1540 return SDOperand(N, 0); 1541 1542 1543 // If the sign bit is known to be zero, switch this to a SRL. 1544 if (TLI.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT))) 1545 return DAG.getNode(ISD::SRL, VT, N0, N1); 1546 return SDOperand(); 1547} 1548 1549SDOperand DAGCombiner::visitSRL(SDNode *N) { 1550 SDOperand N0 = N->getOperand(0); 1551 SDOperand N1 = N->getOperand(1); 1552 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1553 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1554 MVT::ValueType VT = N0.getValueType(); 1555 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1556 1557 // fold (srl c1, c2) -> c1 >>u c2 1558 if (N0C && N1C) 1559 return DAG.getNode(ISD::SRL, VT, N0, N1); 1560 // fold (srl 0, x) -> 0 1561 if (N0C && N0C->isNullValue()) 1562 return N0; 1563 // fold (srl x, c >= size(x)) -> undef 1564 if (N1C && N1C->getValue() >= OpSizeInBits) 1565 return DAG.getNode(ISD::UNDEF, VT); 1566 // fold (srl x, 0) -> x 1567 if (N1C && N1C->isNullValue()) 1568 return N0; 1569 // if (srl x, c) is known to be zero, return 0 1570 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits))) 1571 return DAG.getConstant(0, VT); 1572 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2) 1573 if (N1C && N0.getOpcode() == ISD::SRL && 1574 N0.getOperand(1).getOpcode() == ISD::Constant) { 1575 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1576 uint64_t c2 = N1C->getValue(); 1577 if (c1 + c2 > OpSizeInBits) 1578 return DAG.getConstant(0, VT); 1579 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 1580 DAG.getConstant(c1 + c2, N1.getValueType())); 1581 } 1582 1583 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 1584 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1585 // Shifting in all undef bits? 1586 MVT::ValueType SmallVT = N0.getOperand(0).getValueType(); 1587 if (N1C->getValue() >= MVT::getSizeInBits(SmallVT)) 1588 return DAG.getNode(ISD::UNDEF, VT); 1589 1590 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1); 1591 AddToWorkList(SmallShift.Val); 1592 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift); 1593 } 1594 1595 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 1596 if (N1C && N0.getOpcode() == ISD::CTLZ && 1597 N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) { 1598 uint64_t KnownZero, KnownOne, Mask = MVT::getIntVTBitMask(VT); 1599 TLI.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 1600 1601 // If any of the input bits are KnownOne, then the input couldn't be all 1602 // zeros, thus the result of the srl will always be zero. 1603 if (KnownOne) return DAG.getConstant(0, VT); 1604 1605 // If all of the bits input the to ctlz node are known to be zero, then 1606 // the result of the ctlz is "32" and the result of the shift is one. 1607 uint64_t UnknownBits = ~KnownZero & Mask; 1608 if (UnknownBits == 0) return DAG.getConstant(1, VT); 1609 1610 // Otherwise, check to see if there is exactly one bit input to the ctlz. 1611 if ((UnknownBits & (UnknownBits-1)) == 0) { 1612 // Okay, we know that only that the single bit specified by UnknownBits 1613 // could be set on input to the CTLZ node. If this bit is set, the SRL 1614 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 1615 // to an SRL,XOR pair, which is likely to simplify more. 1616 unsigned ShAmt = CountTrailingZeros_64(UnknownBits); 1617 SDOperand Op = N0.getOperand(0); 1618 if (ShAmt) { 1619 Op = DAG.getNode(ISD::SRL, VT, Op, 1620 DAG.getConstant(ShAmt, TLI.getShiftAmountTy())); 1621 AddToWorkList(Op.Val); 1622 } 1623 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT)); 1624 } 1625 } 1626 1627 return SDOperand(); 1628} 1629 1630SDOperand DAGCombiner::visitCTLZ(SDNode *N) { 1631 SDOperand N0 = N->getOperand(0); 1632 MVT::ValueType VT = N->getValueType(0); 1633 1634 // fold (ctlz c1) -> c2 1635 if (isa<ConstantSDNode>(N0)) 1636 return DAG.getNode(ISD::CTLZ, VT, N0); 1637 return SDOperand(); 1638} 1639 1640SDOperand DAGCombiner::visitCTTZ(SDNode *N) { 1641 SDOperand N0 = N->getOperand(0); 1642 MVT::ValueType VT = N->getValueType(0); 1643 1644 // fold (cttz c1) -> c2 1645 if (isa<ConstantSDNode>(N0)) 1646 return DAG.getNode(ISD::CTTZ, VT, N0); 1647 return SDOperand(); 1648} 1649 1650SDOperand DAGCombiner::visitCTPOP(SDNode *N) { 1651 SDOperand N0 = N->getOperand(0); 1652 MVT::ValueType VT = N->getValueType(0); 1653 1654 // fold (ctpop c1) -> c2 1655 if (isa<ConstantSDNode>(N0)) 1656 return DAG.getNode(ISD::CTPOP, VT, N0); 1657 return SDOperand(); 1658} 1659 1660SDOperand DAGCombiner::visitSELECT(SDNode *N) { 1661 SDOperand N0 = N->getOperand(0); 1662 SDOperand N1 = N->getOperand(1); 1663 SDOperand N2 = N->getOperand(2); 1664 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1665 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1666 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 1667 MVT::ValueType VT = N->getValueType(0); 1668 1669 // fold select C, X, X -> X 1670 if (N1 == N2) 1671 return N1; 1672 // fold select true, X, Y -> X 1673 if (N0C && !N0C->isNullValue()) 1674 return N1; 1675 // fold select false, X, Y -> Y 1676 if (N0C && N0C->isNullValue()) 1677 return N2; 1678 // fold select C, 1, X -> C | X 1679 if (MVT::i1 == VT && N1C && N1C->getValue() == 1) 1680 return DAG.getNode(ISD::OR, VT, N0, N2); 1681 // fold select C, 0, X -> ~C & X 1682 // FIXME: this should check for C type == X type, not i1? 1683 if (MVT::i1 == VT && N1C && N1C->isNullValue()) { 1684 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 1685 AddToWorkList(XORNode.Val); 1686 return DAG.getNode(ISD::AND, VT, XORNode, N2); 1687 } 1688 // fold select C, X, 1 -> ~C | X 1689 if (MVT::i1 == VT && N2C && N2C->getValue() == 1) { 1690 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 1691 AddToWorkList(XORNode.Val); 1692 return DAG.getNode(ISD::OR, VT, XORNode, N1); 1693 } 1694 // fold select C, X, 0 -> C & X 1695 // FIXME: this should check for C type == X type, not i1? 1696 if (MVT::i1 == VT && N2C && N2C->isNullValue()) 1697 return DAG.getNode(ISD::AND, VT, N0, N1); 1698 // fold X ? X : Y --> X ? 1 : Y --> X | Y 1699 if (MVT::i1 == VT && N0 == N1) 1700 return DAG.getNode(ISD::OR, VT, N0, N2); 1701 // fold X ? Y : X --> X ? Y : 0 --> X & Y 1702 if (MVT::i1 == VT && N0 == N2) 1703 return DAG.getNode(ISD::AND, VT, N0, N1); 1704 1705 // If we can fold this based on the true/false value, do so. 1706 if (SimplifySelectOps(N, N1, N2)) 1707 return SDOperand(N, 0); // Don't revisit N. 1708 1709 // fold selects based on a setcc into other things, such as min/max/abs 1710 if (N0.getOpcode() == ISD::SETCC) 1711 // FIXME: 1712 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 1713 // having to say they don't support SELECT_CC on every type the DAG knows 1714 // about, since there is no way to mark an opcode illegal at all value types 1715 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other)) 1716 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1), 1717 N1, N2, N0.getOperand(2)); 1718 else 1719 return SimplifySelect(N0, N1, N2); 1720 return SDOperand(); 1721} 1722 1723SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) { 1724 SDOperand N0 = N->getOperand(0); 1725 SDOperand N1 = N->getOperand(1); 1726 SDOperand N2 = N->getOperand(2); 1727 SDOperand N3 = N->getOperand(3); 1728 SDOperand N4 = N->getOperand(4); 1729 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1730 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1731 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 1732 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 1733 1734 // fold select_cc lhs, rhs, x, x, cc -> x 1735 if (N2 == N3) 1736 return N2; 1737 1738 // Determine if the condition we're dealing with is constant 1739 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 1740 1741 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) { 1742 if (SCCC->getValue()) 1743 return N2; // cond always true -> true val 1744 else 1745 return N3; // cond always false -> false val 1746 } 1747 1748 // Fold to a simpler select_cc 1749 if (SCC.Val && SCC.getOpcode() == ISD::SETCC) 1750 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(), 1751 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 1752 SCC.getOperand(2)); 1753 1754 // If we can fold this based on the true/false value, do so. 1755 if (SimplifySelectOps(N, N2, N3)) 1756 return SDOperand(N, 0); // Don't revisit N. 1757 1758 // fold select_cc into other things, such as min/max/abs 1759 return SimplifySelectCC(N0, N1, N2, N3, CC); 1760} 1761 1762SDOperand DAGCombiner::visitSETCC(SDNode *N) { 1763 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 1764 cast<CondCodeSDNode>(N->getOperand(2))->get()); 1765} 1766 1767SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 1768 SDOperand N0 = N->getOperand(0); 1769 MVT::ValueType VT = N->getValueType(0); 1770 1771 // fold (sext c1) -> c1 1772 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0)) 1773 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0); 1774 1775 // fold (sext (sext x)) -> (sext x) 1776 // fold (sext (aext x)) -> (sext x) 1777 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 1778 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0)); 1779 1780 // fold (sext (truncate x)) -> (sextinreg x). 1781 if (N0.getOpcode() == ISD::TRUNCATE && 1782 (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 1783 N0.getValueType()))) { 1784 SDOperand Op = N0.getOperand(0); 1785 if (Op.getValueType() < VT) { 1786 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 1787 } else if (Op.getValueType() > VT) { 1788 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 1789 } 1790 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op, 1791 DAG.getValueType(N0.getValueType())); 1792 } 1793 1794 // fold (sext (load x)) -> (sext (truncate (sextload x))) 1795 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() && 1796 (!AfterLegalize||TLI.isOperationLegal(ISD::SEXTLOAD, N0.getValueType()))){ 1797 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), 1798 N0.getOperand(1), N0.getOperand(2), 1799 N0.getValueType()); 1800 CombineTo(N, ExtLoad); 1801 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 1802 ExtLoad.getValue(1)); 1803 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1804 } 1805 1806 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 1807 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 1808 if ((N0.getOpcode() == ISD::SEXTLOAD || N0.getOpcode() == ISD::EXTLOAD) && 1809 N0.hasOneUse()) { 1810 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT(); 1811 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), 1812 N0.getOperand(1), N0.getOperand(2), EVT); 1813 CombineTo(N, ExtLoad); 1814 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 1815 ExtLoad.getValue(1)); 1816 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1817 } 1818 1819 return SDOperand(); 1820} 1821 1822SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) { 1823 SDOperand N0 = N->getOperand(0); 1824 MVT::ValueType VT = N->getValueType(0); 1825 1826 // fold (zext c1) -> c1 1827 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0)) 1828 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 1829 // fold (zext (zext x)) -> (zext x) 1830 // fold (zext (aext x)) -> (zext x) 1831 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 1832 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0)); 1833 1834 // fold (zext (truncate x)) -> (and x, mask) 1835 if (N0.getOpcode() == ISD::TRUNCATE && 1836 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) { 1837 SDOperand Op = N0.getOperand(0); 1838 if (Op.getValueType() < VT) { 1839 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 1840 } else if (Op.getValueType() > VT) { 1841 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 1842 } 1843 return DAG.getZeroExtendInReg(Op, N0.getValueType()); 1844 } 1845 1846 // fold (zext (and (trunc x), cst)) -> (and x, cst). 1847 if (N0.getOpcode() == ISD::AND && 1848 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 1849 N0.getOperand(1).getOpcode() == ISD::Constant) { 1850 SDOperand X = N0.getOperand(0).getOperand(0); 1851 if (X.getValueType() < VT) { 1852 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 1853 } else if (X.getValueType() > VT) { 1854 X = DAG.getNode(ISD::TRUNCATE, VT, X); 1855 } 1856 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1857 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 1858 } 1859 1860 // fold (zext (load x)) -> (zext (truncate (zextload x))) 1861 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() && 1862 (!AfterLegalize||TLI.isOperationLegal(ISD::ZEXTLOAD, N0.getValueType()))){ 1863 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), 1864 N0.getOperand(1), N0.getOperand(2), 1865 N0.getValueType()); 1866 CombineTo(N, ExtLoad); 1867 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 1868 ExtLoad.getValue(1)); 1869 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1870 } 1871 1872 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 1873 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 1874 if ((N0.getOpcode() == ISD::ZEXTLOAD || N0.getOpcode() == ISD::EXTLOAD) && 1875 N0.hasOneUse()) { 1876 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT(); 1877 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), 1878 N0.getOperand(1), N0.getOperand(2), EVT); 1879 CombineTo(N, ExtLoad); 1880 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 1881 ExtLoad.getValue(1)); 1882 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1883 } 1884 return SDOperand(); 1885} 1886 1887SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) { 1888 SDOperand N0 = N->getOperand(0); 1889 MVT::ValueType VT = N->getValueType(0); 1890 1891 // fold (aext c1) -> c1 1892 if (isa<ConstantSDNode>(N0)) 1893 return DAG.getNode(ISD::ANY_EXTEND, VT, N0); 1894 // fold (aext (aext x)) -> (aext x) 1895 // fold (aext (zext x)) -> (zext x) 1896 // fold (aext (sext x)) -> (sext x) 1897 if (N0.getOpcode() == ISD::ANY_EXTEND || 1898 N0.getOpcode() == ISD::ZERO_EXTEND || 1899 N0.getOpcode() == ISD::SIGN_EXTEND) 1900 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 1901 1902 // fold (aext (truncate x)) 1903 if (N0.getOpcode() == ISD::TRUNCATE) { 1904 SDOperand TruncOp = N0.getOperand(0); 1905 if (TruncOp.getValueType() == VT) 1906 return TruncOp; // x iff x size == zext size. 1907 if (TruncOp.getValueType() > VT) 1908 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp); 1909 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp); 1910 } 1911 1912 // fold (aext (and (trunc x), cst)) -> (and x, cst). 1913 if (N0.getOpcode() == ISD::AND && 1914 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 1915 N0.getOperand(1).getOpcode() == ISD::Constant) { 1916 SDOperand X = N0.getOperand(0).getOperand(0); 1917 if (X.getValueType() < VT) { 1918 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 1919 } else if (X.getValueType() > VT) { 1920 X = DAG.getNode(ISD::TRUNCATE, VT, X); 1921 } 1922 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1923 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 1924 } 1925 1926 // fold (aext (load x)) -> (aext (truncate (extload x))) 1927 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() && 1928 (!AfterLegalize||TLI.isOperationLegal(ISD::EXTLOAD, N0.getValueType()))) { 1929 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, N0.getOperand(0), 1930 N0.getOperand(1), N0.getOperand(2), 1931 N0.getValueType()); 1932 CombineTo(N, ExtLoad); 1933 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 1934 ExtLoad.getValue(1)); 1935 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1936 } 1937 1938 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 1939 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 1940 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 1941 if ((N0.getOpcode() == ISD::ZEXTLOAD || N0.getOpcode() == ISD::EXTLOAD || 1942 N0.getOpcode() == ISD::SEXTLOAD) && 1943 N0.hasOneUse()) { 1944 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT(); 1945 SDOperand ExtLoad = DAG.getExtLoad(N0.getOpcode(), VT, N0.getOperand(0), 1946 N0.getOperand(1), N0.getOperand(2), EVT); 1947 CombineTo(N, ExtLoad); 1948 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 1949 ExtLoad.getValue(1)); 1950 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1951 } 1952 return SDOperand(); 1953} 1954 1955 1956SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 1957 SDOperand N0 = N->getOperand(0); 1958 SDOperand N1 = N->getOperand(1); 1959 MVT::ValueType VT = N->getValueType(0); 1960 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT(); 1961 unsigned EVTBits = MVT::getSizeInBits(EVT); 1962 1963 // fold (sext_in_reg c1) -> c1 1964 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 1965 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1); 1966 1967 // If the input is already sign extended, just drop the extension. 1968 if (TLI.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1) 1969 return N0; 1970 1971 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 1972 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1973 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) { 1974 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); 1975 } 1976 1977 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero 1978 if (TLI.MaskedValueIsZero(N0, 1ULL << (EVTBits-1))) 1979 return DAG.getZeroExtendInReg(N0, EVT); 1980 1981 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24 1982 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible. 1983 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 1984 if (N0.getOpcode() == ISD::SRL) { 1985 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1986 if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) { 1987 // We can turn this into an SRA iff the input to the SRL is already sign 1988 // extended enough. 1989 unsigned InSignBits = TLI.ComputeNumSignBits(N0.getOperand(0)); 1990 if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits) 1991 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1)); 1992 } 1993 } 1994 1995 // fold (sext_inreg (extload x)) -> (sextload x) 1996 if (N0.getOpcode() == ISD::EXTLOAD && 1997 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() && 1998 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) { 1999 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), 2000 N0.getOperand(1), N0.getOperand(2), 2001 EVT); 2002 CombineTo(N, ExtLoad); 2003 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 2004 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2005 } 2006 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 2007 if (N0.getOpcode() == ISD::ZEXTLOAD && N0.hasOneUse() && 2008 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() && 2009 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) { 2010 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), 2011 N0.getOperand(1), N0.getOperand(2), 2012 EVT); 2013 CombineTo(N, ExtLoad); 2014 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 2015 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2016 } 2017 return SDOperand(); 2018} 2019 2020SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) { 2021 SDOperand N0 = N->getOperand(0); 2022 MVT::ValueType VT = N->getValueType(0); 2023 2024 // noop truncate 2025 if (N0.getValueType() == N->getValueType(0)) 2026 return N0; 2027 // fold (truncate c1) -> c1 2028 if (isa<ConstantSDNode>(N0)) 2029 return DAG.getNode(ISD::TRUNCATE, VT, N0); 2030 // fold (truncate (truncate x)) -> (truncate x) 2031 if (N0.getOpcode() == ISD::TRUNCATE) 2032 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 2033 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 2034 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| 2035 N0.getOpcode() == ISD::ANY_EXTEND) { 2036 if (N0.getValueType() < VT) 2037 // if the source is smaller than the dest, we still need an extend 2038 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 2039 else if (N0.getValueType() > VT) 2040 // if the source is larger than the dest, than we just need the truncate 2041 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 2042 else 2043 // if the source and dest are the same type, we can drop both the extend 2044 // and the truncate 2045 return N0.getOperand(0); 2046 } 2047 // fold (truncate (load x)) -> (smaller load x) 2048 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) { 2049 assert(MVT::getSizeInBits(N0.getValueType()) > MVT::getSizeInBits(VT) && 2050 "Cannot truncate to larger type!"); 2051 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 2052 // For big endian targets, we need to add an offset to the pointer to load 2053 // the correct bytes. For little endian systems, we merely need to read 2054 // fewer bytes from the same pointer. 2055 uint64_t PtrOff = 2056 (MVT::getSizeInBits(N0.getValueType()) - MVT::getSizeInBits(VT)) / 8; 2057 SDOperand NewPtr = TLI.isLittleEndian() ? N0.getOperand(1) : 2058 DAG.getNode(ISD::ADD, PtrType, N0.getOperand(1), 2059 DAG.getConstant(PtrOff, PtrType)); 2060 AddToWorkList(NewPtr.Val); 2061 SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), NewPtr,N0.getOperand(2)); 2062 AddToWorkList(N); 2063 CombineTo(N0.Val, Load, Load.getValue(1)); 2064 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2065 } 2066 return SDOperand(); 2067} 2068 2069SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) { 2070 SDOperand N0 = N->getOperand(0); 2071 MVT::ValueType VT = N->getValueType(0); 2072 2073 // If the input is a constant, let getNode() fold it. 2074 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 2075 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0); 2076 if (Res.Val != N) return Res; 2077 } 2078 2079 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2) 2080 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 2081 2082 // fold (conv (load x)) -> (load (conv*)x) 2083 // FIXME: These xforms need to know that the resultant load doesn't need a 2084 // higher alignment than the original! 2085 if (0 && N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) { 2086 SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), N0.getOperand(1), 2087 N0.getOperand(2)); 2088 AddToWorkList(N); 2089 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load), 2090 Load.getValue(1)); 2091 return Load; 2092 } 2093 2094 return SDOperand(); 2095} 2096 2097SDOperand DAGCombiner::visitVBIT_CONVERT(SDNode *N) { 2098 SDOperand N0 = N->getOperand(0); 2099 MVT::ValueType VT = N->getValueType(0); 2100 2101 // If the input is a VBUILD_VECTOR with all constant elements, fold this now. 2102 // First check to see if this is all constant. 2103 if (N0.getOpcode() == ISD::VBUILD_VECTOR && N0.Val->hasOneUse() && 2104 VT == MVT::Vector) { 2105 bool isSimple = true; 2106 for (unsigned i = 0, e = N0.getNumOperands()-2; i != e; ++i) 2107 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 2108 N0.getOperand(i).getOpcode() != ISD::Constant && 2109 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 2110 isSimple = false; 2111 break; 2112 } 2113 2114 MVT::ValueType DestEltVT = cast<VTSDNode>(N->getOperand(2))->getVT(); 2115 if (isSimple && !MVT::isVector(DestEltVT)) { 2116 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(N0.Val, DestEltVT); 2117 } 2118 } 2119 2120 return SDOperand(); 2121} 2122 2123/// ConstantFoldVBIT_CONVERTofVBUILD_VECTOR - We know that BV is a vbuild_vector 2124/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 2125/// destination element value type. 2126SDOperand DAGCombiner:: 2127ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) { 2128 MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType(); 2129 2130 // If this is already the right type, we're done. 2131 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0); 2132 2133 unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT); 2134 unsigned DstBitSize = MVT::getSizeInBits(DstEltVT); 2135 2136 // If this is a conversion of N elements of one type to N elements of another 2137 // type, convert each element. This handles FP<->INT cases. 2138 if (SrcBitSize == DstBitSize) { 2139 SmallVector<SDOperand, 8> Ops; 2140 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) { 2141 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i))); 2142 AddToWorkList(Ops.back().Val); 2143 } 2144 Ops.push_back(*(BV->op_end()-2)); // Add num elements. 2145 Ops.push_back(DAG.getValueType(DstEltVT)); 2146 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size()); 2147 } 2148 2149 // Otherwise, we're growing or shrinking the elements. To avoid having to 2150 // handle annoying details of growing/shrinking FP values, we convert them to 2151 // int first. 2152 if (MVT::isFloatingPoint(SrcEltVT)) { 2153 // Convert the input float vector to a int vector where the elements are the 2154 // same sizes. 2155 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 2156 MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 2157 BV = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, IntVT).Val; 2158 SrcEltVT = IntVT; 2159 } 2160 2161 // Now we know the input is an integer vector. If the output is a FP type, 2162 // convert to integer first, then to FP of the right size. 2163 if (MVT::isFloatingPoint(DstEltVT)) { 2164 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 2165 MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 2166 SDNode *Tmp = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, TmpVT).Val; 2167 2168 // Next, convert to FP elements of the same size. 2169 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(Tmp, DstEltVT); 2170 } 2171 2172 // Okay, we know the src/dst types are both integers of differing types. 2173 // Handling growing first. 2174 assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT)); 2175 if (SrcBitSize < DstBitSize) { 2176 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 2177 2178 SmallVector<SDOperand, 8> Ops; 2179 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; 2180 i += NumInputsPerOutput) { 2181 bool isLE = TLI.isLittleEndian(); 2182 uint64_t NewBits = 0; 2183 bool EltIsUndef = true; 2184 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 2185 // Shift the previously computed bits over. 2186 NewBits <<= SrcBitSize; 2187 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 2188 if (Op.getOpcode() == ISD::UNDEF) continue; 2189 EltIsUndef = false; 2190 2191 NewBits |= cast<ConstantSDNode>(Op)->getValue(); 2192 } 2193 2194 if (EltIsUndef) 2195 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 2196 else 2197 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 2198 } 2199 2200 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements. 2201 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size. 2202 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size()); 2203 } 2204 2205 // Finally, this must be the case where we are shrinking elements: each input 2206 // turns into multiple outputs. 2207 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 2208 SmallVector<SDOperand, 8> Ops; 2209 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) { 2210 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 2211 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 2212 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 2213 continue; 2214 } 2215 uint64_t OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getValue(); 2216 2217 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 2218 unsigned ThisVal = OpVal & ((1ULL << DstBitSize)-1); 2219 OpVal >>= DstBitSize; 2220 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 2221 } 2222 2223 // For big endian targets, swap the order of the pieces of each element. 2224 if (!TLI.isLittleEndian()) 2225 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 2226 } 2227 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements. 2228 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size. 2229 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size()); 2230} 2231 2232 2233 2234SDOperand DAGCombiner::visitFADD(SDNode *N) { 2235 SDOperand N0 = N->getOperand(0); 2236 SDOperand N1 = N->getOperand(1); 2237 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2238 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2239 MVT::ValueType VT = N->getValueType(0); 2240 2241 // fold (fadd c1, c2) -> c1+c2 2242 if (N0CFP && N1CFP) 2243 return DAG.getNode(ISD::FADD, VT, N0, N1); 2244 // canonicalize constant to RHS 2245 if (N0CFP && !N1CFP) 2246 return DAG.getNode(ISD::FADD, VT, N1, N0); 2247 // fold (A + (-B)) -> A-B 2248 if (N1.getOpcode() == ISD::FNEG) 2249 return DAG.getNode(ISD::FSUB, VT, N0, N1.getOperand(0)); 2250 // fold ((-A) + B) -> B-A 2251 if (N0.getOpcode() == ISD::FNEG) 2252 return DAG.getNode(ISD::FSUB, VT, N1, N0.getOperand(0)); 2253 return SDOperand(); 2254} 2255 2256SDOperand DAGCombiner::visitFSUB(SDNode *N) { 2257 SDOperand N0 = N->getOperand(0); 2258 SDOperand N1 = N->getOperand(1); 2259 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2260 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2261 MVT::ValueType VT = N->getValueType(0); 2262 2263 // fold (fsub c1, c2) -> c1-c2 2264 if (N0CFP && N1CFP) 2265 return DAG.getNode(ISD::FSUB, VT, N0, N1); 2266 // fold (A-(-B)) -> A+B 2267 if (N1.getOpcode() == ISD::FNEG) 2268 return DAG.getNode(ISD::FADD, VT, N0, N1.getOperand(0)); 2269 return SDOperand(); 2270} 2271 2272SDOperand DAGCombiner::visitFMUL(SDNode *N) { 2273 SDOperand N0 = N->getOperand(0); 2274 SDOperand N1 = N->getOperand(1); 2275 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2276 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2277 MVT::ValueType VT = N->getValueType(0); 2278 2279 // fold (fmul c1, c2) -> c1*c2 2280 if (N0CFP && N1CFP) 2281 return DAG.getNode(ISD::FMUL, VT, N0, N1); 2282 // canonicalize constant to RHS 2283 if (N0CFP && !N1CFP) 2284 return DAG.getNode(ISD::FMUL, VT, N1, N0); 2285 // fold (fmul X, 2.0) -> (fadd X, X) 2286 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 2287 return DAG.getNode(ISD::FADD, VT, N0, N0); 2288 return SDOperand(); 2289} 2290 2291SDOperand DAGCombiner::visitFDIV(SDNode *N) { 2292 SDOperand N0 = N->getOperand(0); 2293 SDOperand N1 = N->getOperand(1); 2294 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2295 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2296 MVT::ValueType VT = N->getValueType(0); 2297 2298 // fold (fdiv c1, c2) -> c1/c2 2299 if (N0CFP && N1CFP) 2300 return DAG.getNode(ISD::FDIV, VT, N0, N1); 2301 return SDOperand(); 2302} 2303 2304SDOperand DAGCombiner::visitFREM(SDNode *N) { 2305 SDOperand N0 = N->getOperand(0); 2306 SDOperand N1 = N->getOperand(1); 2307 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2308 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2309 MVT::ValueType VT = N->getValueType(0); 2310 2311 // fold (frem c1, c2) -> fmod(c1,c2) 2312 if (N0CFP && N1CFP) 2313 return DAG.getNode(ISD::FREM, VT, N0, N1); 2314 return SDOperand(); 2315} 2316 2317SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) { 2318 SDOperand N0 = N->getOperand(0); 2319 SDOperand N1 = N->getOperand(1); 2320 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2321 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2322 MVT::ValueType VT = N->getValueType(0); 2323 2324 if (N0CFP && N1CFP) // Constant fold 2325 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1); 2326 2327 if (N1CFP) { 2328 // copysign(x, c1) -> fabs(x) iff ispos(c1) 2329 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 2330 union { 2331 double d; 2332 int64_t i; 2333 } u; 2334 u.d = N1CFP->getValue(); 2335 if (u.i >= 0) 2336 return DAG.getNode(ISD::FABS, VT, N0); 2337 else 2338 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0)); 2339 } 2340 2341 // copysign(fabs(x), y) -> copysign(x, y) 2342 // copysign(fneg(x), y) -> copysign(x, y) 2343 // copysign(copysign(x,z), y) -> copysign(x, y) 2344 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 2345 N0.getOpcode() == ISD::FCOPYSIGN) 2346 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1); 2347 2348 // copysign(x, abs(y)) -> abs(x) 2349 if (N1.getOpcode() == ISD::FABS) 2350 return DAG.getNode(ISD::FABS, VT, N0); 2351 2352 // copysign(x, copysign(y,z)) -> copysign(x, z) 2353 if (N1.getOpcode() == ISD::FCOPYSIGN) 2354 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1)); 2355 2356 // copysign(x, fp_extend(y)) -> copysign(x, y) 2357 // copysign(x, fp_round(y)) -> copysign(x, y) 2358 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 2359 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0)); 2360 2361 return SDOperand(); 2362} 2363 2364 2365 2366SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) { 2367 SDOperand N0 = N->getOperand(0); 2368 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2369 MVT::ValueType VT = N->getValueType(0); 2370 2371 // fold (sint_to_fp c1) -> c1fp 2372 if (N0C) 2373 return DAG.getNode(ISD::SINT_TO_FP, VT, N0); 2374 return SDOperand(); 2375} 2376 2377SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) { 2378 SDOperand N0 = N->getOperand(0); 2379 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2380 MVT::ValueType VT = N->getValueType(0); 2381 2382 // fold (uint_to_fp c1) -> c1fp 2383 if (N0C) 2384 return DAG.getNode(ISD::UINT_TO_FP, VT, N0); 2385 return SDOperand(); 2386} 2387 2388SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) { 2389 SDOperand N0 = N->getOperand(0); 2390 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2391 MVT::ValueType VT = N->getValueType(0); 2392 2393 // fold (fp_to_sint c1fp) -> c1 2394 if (N0CFP) 2395 return DAG.getNode(ISD::FP_TO_SINT, VT, N0); 2396 return SDOperand(); 2397} 2398 2399SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) { 2400 SDOperand N0 = N->getOperand(0); 2401 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2402 MVT::ValueType VT = N->getValueType(0); 2403 2404 // fold (fp_to_uint c1fp) -> c1 2405 if (N0CFP) 2406 return DAG.getNode(ISD::FP_TO_UINT, VT, N0); 2407 return SDOperand(); 2408} 2409 2410SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) { 2411 SDOperand N0 = N->getOperand(0); 2412 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2413 MVT::ValueType VT = N->getValueType(0); 2414 2415 // fold (fp_round c1fp) -> c1fp 2416 if (N0CFP) 2417 return DAG.getNode(ISD::FP_ROUND, VT, N0); 2418 2419 // fold (fp_round (fp_extend x)) -> x 2420 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 2421 return N0.getOperand(0); 2422 2423 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 2424 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) { 2425 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0)); 2426 AddToWorkList(Tmp.Val); 2427 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1)); 2428 } 2429 2430 return SDOperand(); 2431} 2432 2433SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 2434 SDOperand N0 = N->getOperand(0); 2435 MVT::ValueType VT = N->getValueType(0); 2436 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 2437 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2438 2439 // fold (fp_round_inreg c1fp) -> c1fp 2440 if (N0CFP) { 2441 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT); 2442 return DAG.getNode(ISD::FP_EXTEND, VT, Round); 2443 } 2444 return SDOperand(); 2445} 2446 2447SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) { 2448 SDOperand N0 = N->getOperand(0); 2449 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2450 MVT::ValueType VT = N->getValueType(0); 2451 2452 // fold (fp_extend c1fp) -> c1fp 2453 if (N0CFP) 2454 return DAG.getNode(ISD::FP_EXTEND, VT, N0); 2455 2456 // fold (fpext (load x)) -> (fpext (fpround (extload x))) 2457 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() && 2458 (!AfterLegalize||TLI.isOperationLegal(ISD::EXTLOAD, N0.getValueType()))) { 2459 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, N0.getOperand(0), 2460 N0.getOperand(1), N0.getOperand(2), 2461 N0.getValueType()); 2462 CombineTo(N, ExtLoad); 2463 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad), 2464 ExtLoad.getValue(1)); 2465 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2466 } 2467 2468 2469 return SDOperand(); 2470} 2471 2472SDOperand DAGCombiner::visitFNEG(SDNode *N) { 2473 SDOperand N0 = N->getOperand(0); 2474 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2475 MVT::ValueType VT = N->getValueType(0); 2476 2477 // fold (fneg c1) -> -c1 2478 if (N0CFP) 2479 return DAG.getNode(ISD::FNEG, VT, N0); 2480 // fold (fneg (sub x, y)) -> (sub y, x) 2481 if (N0.getOpcode() == ISD::SUB) 2482 return DAG.getNode(ISD::SUB, VT, N0.getOperand(1), N0.getOperand(0)); 2483 // fold (fneg (fneg x)) -> x 2484 if (N0.getOpcode() == ISD::FNEG) 2485 return N0.getOperand(0); 2486 return SDOperand(); 2487} 2488 2489SDOperand DAGCombiner::visitFABS(SDNode *N) { 2490 SDOperand N0 = N->getOperand(0); 2491 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2492 MVT::ValueType VT = N->getValueType(0); 2493 2494 // fold (fabs c1) -> fabs(c1) 2495 if (N0CFP) 2496 return DAG.getNode(ISD::FABS, VT, N0); 2497 // fold (fabs (fabs x)) -> (fabs x) 2498 if (N0.getOpcode() == ISD::FABS) 2499 return N->getOperand(0); 2500 // fold (fabs (fneg x)) -> (fabs x) 2501 // fold (fabs (fcopysign x, y)) -> (fabs x) 2502 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 2503 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0)); 2504 2505 return SDOperand(); 2506} 2507 2508SDOperand DAGCombiner::visitBRCOND(SDNode *N) { 2509 SDOperand Chain = N->getOperand(0); 2510 SDOperand N1 = N->getOperand(1); 2511 SDOperand N2 = N->getOperand(2); 2512 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2513 2514 // never taken branch, fold to chain 2515 if (N1C && N1C->isNullValue()) 2516 return Chain; 2517 // unconditional branch 2518 if (N1C && N1C->getValue() == 1) 2519 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 2520 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 2521 // on the target. 2522 if (N1.getOpcode() == ISD::SETCC && 2523 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) { 2524 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2), 2525 N1.getOperand(0), N1.getOperand(1), N2); 2526 } 2527 return SDOperand(); 2528} 2529 2530// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 2531// 2532SDOperand DAGCombiner::visitBR_CC(SDNode *N) { 2533 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 2534 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 2535 2536 // Use SimplifySetCC to simplify SETCC's. 2537 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false); 2538 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val); 2539 2540 // fold br_cc true, dest -> br dest (unconditional branch) 2541 if (SCCC && SCCC->getValue()) 2542 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0), 2543 N->getOperand(4)); 2544 // fold br_cc false, dest -> unconditional fall through 2545 if (SCCC && SCCC->isNullValue()) 2546 return N->getOperand(0); 2547 // fold to a simpler setcc 2548 if (Simp.Val && Simp.getOpcode() == ISD::SETCC) 2549 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0), 2550 Simp.getOperand(2), Simp.getOperand(0), 2551 Simp.getOperand(1), N->getOperand(4)); 2552 return SDOperand(); 2553} 2554 2555SDOperand DAGCombiner::visitLOAD(SDNode *N) { 2556 SDOperand Chain = N->getOperand(0); 2557 SDOperand Ptr = N->getOperand(1); 2558 SDOperand SrcValue = N->getOperand(2); 2559 2560 // If there are no uses of the loaded value, change uses of the chain value 2561 // into uses of the chain input (i.e. delete the dead load). 2562 if (N->hasNUsesOfValue(0, 0)) 2563 return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain); 2564 2565 // If this load is directly stored, replace the load value with the stored 2566 // value. 2567 // TODO: Handle store large -> read small portion. 2568 // TODO: Handle TRUNCSTORE/EXTLOAD 2569 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr && 2570 Chain.getOperand(1).getValueType() == N->getValueType(0)) 2571 return CombineTo(N, Chain.getOperand(1), Chain); 2572 2573 return SDOperand(); 2574} 2575 2576/// visitXEXTLOAD - Handle EXTLOAD/ZEXTLOAD/SEXTLOAD. 2577SDOperand DAGCombiner::visitXEXTLOAD(SDNode *N) { 2578 SDOperand Chain = N->getOperand(0); 2579 SDOperand Ptr = N->getOperand(1); 2580 SDOperand SrcValue = N->getOperand(2); 2581 SDOperand EVT = N->getOperand(3); 2582 2583 // If there are no uses of the loaded value, change uses of the chain value 2584 // into uses of the chain input (i.e. delete the dead load). 2585 if (N->hasNUsesOfValue(0, 0)) 2586 return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain); 2587 2588 return SDOperand(); 2589} 2590 2591/// isNotAlias - Return true if we have definitive knowlege that the two 2592/// addresses don't overlap. 2593bool DAGCombiner::isNotAlias(SDOperand Ptr1, SDOperand Ptr2) { 2594 // Mind the flag. 2595 if (!CombinerAA) return false; 2596 2597 // If they are the same then they are simple aliases. 2598 if (Ptr1 == Ptr2) return false; 2599 2600 // If either operand is a frame value (not the same location from above test) 2601 // then they can't alias. 2602 FrameIndexSDNode *FI1 = dyn_cast<FrameIndexSDNode>(Ptr1); 2603 FrameIndexSDNode *FI2 = dyn_cast<FrameIndexSDNode>(Ptr2); 2604 if (FI1 || FI2) { 2605 return true; 2606 } 2607 2608 // Otherwise we don't know and have to play it safe. 2609 return false; 2610} 2611 2612SDOperand DAGCombiner::visitSTORE(SDNode *N) { 2613 SDOperand Chain = N->getOperand(0); 2614 SDOperand Value = N->getOperand(1); 2615 SDOperand Ptr = N->getOperand(2); 2616 SDOperand SrcValue = N->getOperand(3); 2617 2618 // If this is a store that kills a previous store, remove the previous store. 2619 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr && 2620 Chain.Val->hasOneUse() /* Avoid introducing DAG cycles */ && 2621 // Make sure that these stores are the same value type: 2622 // FIXME: we really care that the second store is >= size of the first. 2623 Value.getValueType() == Chain.getOperand(1).getValueType()) { 2624 // Create a new store of Value that replaces both stores. 2625 SDNode *PrevStore = Chain.Val; 2626 if (PrevStore->getOperand(1) == Value) // Same value multiply stored. 2627 return Chain; 2628 SDOperand NewStore = DAG.getNode(ISD::STORE, MVT::Other, 2629 PrevStore->getOperand(0), Value, Ptr, 2630 SrcValue); 2631 CombineTo(N, NewStore); // Nuke this store. 2632 CombineTo(PrevStore, NewStore); // Nuke the previous store. 2633 return SDOperand(N, 0); 2634 } 2635 2636 // If this is a store of a bit convert, store the input value. 2637 // FIXME: This needs to know that the resultant store does not need a 2638 // higher alignment than the original. 2639 if (0 && Value.getOpcode() == ISD::BIT_CONVERT) 2640 return DAG.getNode(ISD::STORE, MVT::Other, Chain, Value.getOperand(0), 2641 Ptr, SrcValue); 2642 2643 // If the previous store is not an alias then break artificial chain. 2644 if (Chain.getOpcode() == ISD::STORE && isNotAlias(Ptr, Chain.getOperand(2))) { 2645 // Replace the chain to void dependency. 2646 SDNode *PrevStore = Chain.Val; 2647 SDOperand ReplStore = DAG.getNode(ISD::STORE, MVT::Other, 2648 PrevStore->getOperand(0), Value, Ptr, 2649 SrcValue); 2650 // Create token to keep both stores around. 2651 SDOperand Token = DAG.getNode(ISD::TokenFactor, MVT::Other, 2652 Chain, ReplStore); 2653 // Replace uses with token. 2654 CombineTo(N, Token); 2655 // Don't recombine on token. 2656 return SDOperand(N, 0); 2657 } 2658 2659 return SDOperand(); 2660} 2661 2662SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 2663 SDOperand InVec = N->getOperand(0); 2664 SDOperand InVal = N->getOperand(1); 2665 SDOperand EltNo = N->getOperand(2); 2666 2667 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 2668 // vector with the inserted element. 2669 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 2670 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 2671 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end()); 2672 if (Elt < Ops.size()) 2673 Ops[Elt] = InVal; 2674 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(), 2675 &Ops[0], Ops.size()); 2676 } 2677 2678 return SDOperand(); 2679} 2680 2681SDOperand DAGCombiner::visitVINSERT_VECTOR_ELT(SDNode *N) { 2682 SDOperand InVec = N->getOperand(0); 2683 SDOperand InVal = N->getOperand(1); 2684 SDOperand EltNo = N->getOperand(2); 2685 SDOperand NumElts = N->getOperand(3); 2686 SDOperand EltType = N->getOperand(4); 2687 2688 // If the invec is a VBUILD_VECTOR and if EltNo is a constant, build a new 2689 // vector with the inserted element. 2690 if (InVec.getOpcode() == ISD::VBUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 2691 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 2692 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end()); 2693 if (Elt < Ops.size()-2) 2694 Ops[Elt] = InVal; 2695 return DAG.getNode(ISD::VBUILD_VECTOR, InVec.getValueType(), 2696 &Ops[0], Ops.size()); 2697 } 2698 2699 return SDOperand(); 2700} 2701 2702SDOperand DAGCombiner::visitVBUILD_VECTOR(SDNode *N) { 2703 unsigned NumInScalars = N->getNumOperands()-2; 2704 SDOperand NumElts = N->getOperand(NumInScalars); 2705 SDOperand EltType = N->getOperand(NumInScalars+1); 2706 2707 // Check to see if this is a VBUILD_VECTOR of a bunch of VEXTRACT_VECTOR_ELT 2708 // operations. If so, and if the EXTRACT_ELT vector inputs come from at most 2709 // two distinct vectors, turn this into a shuffle node. 2710 SDOperand VecIn1, VecIn2; 2711 for (unsigned i = 0; i != NumInScalars; ++i) { 2712 // Ignore undef inputs. 2713 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 2714 2715 // If this input is something other than a VEXTRACT_VECTOR_ELT with a 2716 // constant index, bail out. 2717 if (N->getOperand(i).getOpcode() != ISD::VEXTRACT_VECTOR_ELT || 2718 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 2719 VecIn1 = VecIn2 = SDOperand(0, 0); 2720 break; 2721 } 2722 2723 // If the input vector type disagrees with the result of the vbuild_vector, 2724 // we can't make a shuffle. 2725 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0); 2726 if (*(ExtractedFromVec.Val->op_end()-2) != NumElts || 2727 *(ExtractedFromVec.Val->op_end()-1) != EltType) { 2728 VecIn1 = VecIn2 = SDOperand(0, 0); 2729 break; 2730 } 2731 2732 // Otherwise, remember this. We allow up to two distinct input vectors. 2733 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 2734 continue; 2735 2736 if (VecIn1.Val == 0) { 2737 VecIn1 = ExtractedFromVec; 2738 } else if (VecIn2.Val == 0) { 2739 VecIn2 = ExtractedFromVec; 2740 } else { 2741 // Too many inputs. 2742 VecIn1 = VecIn2 = SDOperand(0, 0); 2743 break; 2744 } 2745 } 2746 2747 // If everything is good, we can make a shuffle operation. 2748 if (VecIn1.Val) { 2749 SmallVector<SDOperand, 8> BuildVecIndices; 2750 for (unsigned i = 0; i != NumInScalars; ++i) { 2751 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 2752 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); 2753 continue; 2754 } 2755 2756 SDOperand Extract = N->getOperand(i); 2757 2758 // If extracting from the first vector, just use the index directly. 2759 if (Extract.getOperand(0) == VecIn1) { 2760 BuildVecIndices.push_back(Extract.getOperand(1)); 2761 continue; 2762 } 2763 2764 // Otherwise, use InIdx + VecSize 2765 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue(); 2766 BuildVecIndices.push_back(DAG.getConstant(Idx+NumInScalars, MVT::i32)); 2767 } 2768 2769 // Add count and size info. 2770 BuildVecIndices.push_back(NumElts); 2771 BuildVecIndices.push_back(DAG.getValueType(MVT::i32)); 2772 2773 // Return the new VVECTOR_SHUFFLE node. 2774 SDOperand Ops[5]; 2775 Ops[0] = VecIn1; 2776 if (VecIn2.Val) { 2777 Ops[1] = VecIn2; 2778 } else { 2779 // Use an undef vbuild_vector as input for the second operand. 2780 std::vector<SDOperand> UnOps(NumInScalars, 2781 DAG.getNode(ISD::UNDEF, 2782 cast<VTSDNode>(EltType)->getVT())); 2783 UnOps.push_back(NumElts); 2784 UnOps.push_back(EltType); 2785 Ops[1] = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, 2786 &UnOps[0], UnOps.size()); 2787 AddToWorkList(Ops[1].Val); 2788 } 2789 Ops[2] = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, 2790 &BuildVecIndices[0], BuildVecIndices.size()); 2791 Ops[3] = NumElts; 2792 Ops[4] = EltType; 2793 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, Ops, 5); 2794 } 2795 2796 return SDOperand(); 2797} 2798 2799SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 2800 SDOperand ShufMask = N->getOperand(2); 2801 unsigned NumElts = ShufMask.getNumOperands(); 2802 2803 // If the shuffle mask is an identity operation on the LHS, return the LHS. 2804 bool isIdentity = true; 2805 for (unsigned i = 0; i != NumElts; ++i) { 2806 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 2807 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) { 2808 isIdentity = false; 2809 break; 2810 } 2811 } 2812 if (isIdentity) return N->getOperand(0); 2813 2814 // If the shuffle mask is an identity operation on the RHS, return the RHS. 2815 isIdentity = true; 2816 for (unsigned i = 0; i != NumElts; ++i) { 2817 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 2818 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) { 2819 isIdentity = false; 2820 break; 2821 } 2822 } 2823 if (isIdentity) return N->getOperand(1); 2824 2825 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not 2826 // needed at all. 2827 bool isUnary = true; 2828 bool isSplat = true; 2829 int VecNum = -1; 2830 unsigned BaseIdx = 0; 2831 for (unsigned i = 0; i != NumElts; ++i) 2832 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) { 2833 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue(); 2834 int V = (Idx < NumElts) ? 0 : 1; 2835 if (VecNum == -1) { 2836 VecNum = V; 2837 BaseIdx = Idx; 2838 } else { 2839 if (BaseIdx != Idx) 2840 isSplat = false; 2841 if (VecNum != V) { 2842 isUnary = false; 2843 break; 2844 } 2845 } 2846 } 2847 2848 SDOperand N0 = N->getOperand(0); 2849 SDOperand N1 = N->getOperand(1); 2850 // Normalize unary shuffle so the RHS is undef. 2851 if (isUnary && VecNum == 1) 2852 std::swap(N0, N1); 2853 2854 // If it is a splat, check if the argument vector is a build_vector with 2855 // all scalar elements the same. 2856 if (isSplat) { 2857 SDNode *V = N0.Val; 2858 if (V->getOpcode() == ISD::BIT_CONVERT) 2859 V = V->getOperand(0).Val; 2860 if (V->getOpcode() == ISD::BUILD_VECTOR) { 2861 unsigned NumElems = V->getNumOperands()-2; 2862 if (NumElems > BaseIdx) { 2863 SDOperand Base; 2864 bool AllSame = true; 2865 for (unsigned i = 0; i != NumElems; ++i) { 2866 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 2867 Base = V->getOperand(i); 2868 break; 2869 } 2870 } 2871 // Splat of <u, u, u, u>, return <u, u, u, u> 2872 if (!Base.Val) 2873 return N0; 2874 for (unsigned i = 0; i != NumElems; ++i) { 2875 if (V->getOperand(i).getOpcode() != ISD::UNDEF && 2876 V->getOperand(i) != Base) { 2877 AllSame = false; 2878 break; 2879 } 2880 } 2881 // Splat of <x, x, x, x>, return <x, x, x, x> 2882 if (AllSame) 2883 return N0; 2884 } 2885 } 2886 } 2887 2888 // If it is a unary or the LHS and the RHS are the same node, turn the RHS 2889 // into an undef. 2890 if (isUnary || N0 == N1) { 2891 if (N0.getOpcode() == ISD::UNDEF) 2892 return DAG.getNode(ISD::UNDEF, N->getValueType(0)); 2893 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the 2894 // first operand. 2895 SmallVector<SDOperand, 8> MappedOps; 2896 for (unsigned i = 0, e = ShufMask.getNumOperands(); i != e; ++i) { 2897 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || 2898 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) { 2899 MappedOps.push_back(ShufMask.getOperand(i)); 2900 } else { 2901 unsigned NewIdx = 2902 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts; 2903 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32)); 2904 } 2905 } 2906 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(), 2907 &MappedOps[0], MappedOps.size()); 2908 AddToWorkList(ShufMask.Val); 2909 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0), 2910 N0, 2911 DAG.getNode(ISD::UNDEF, N->getValueType(0)), 2912 ShufMask); 2913 } 2914 2915 return SDOperand(); 2916} 2917 2918SDOperand DAGCombiner::visitVVECTOR_SHUFFLE(SDNode *N) { 2919 SDOperand ShufMask = N->getOperand(2); 2920 unsigned NumElts = ShufMask.getNumOperands()-2; 2921 2922 // If the shuffle mask is an identity operation on the LHS, return the LHS. 2923 bool isIdentity = true; 2924 for (unsigned i = 0; i != NumElts; ++i) { 2925 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 2926 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) { 2927 isIdentity = false; 2928 break; 2929 } 2930 } 2931 if (isIdentity) return N->getOperand(0); 2932 2933 // If the shuffle mask is an identity operation on the RHS, return the RHS. 2934 isIdentity = true; 2935 for (unsigned i = 0; i != NumElts; ++i) { 2936 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 2937 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) { 2938 isIdentity = false; 2939 break; 2940 } 2941 } 2942 if (isIdentity) return N->getOperand(1); 2943 2944 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not 2945 // needed at all. 2946 bool isUnary = true; 2947 bool isSplat = true; 2948 int VecNum = -1; 2949 unsigned BaseIdx = 0; 2950 for (unsigned i = 0; i != NumElts; ++i) 2951 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) { 2952 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue(); 2953 int V = (Idx < NumElts) ? 0 : 1; 2954 if (VecNum == -1) { 2955 VecNum = V; 2956 BaseIdx = Idx; 2957 } else { 2958 if (BaseIdx != Idx) 2959 isSplat = false; 2960 if (VecNum != V) { 2961 isUnary = false; 2962 break; 2963 } 2964 } 2965 } 2966 2967 SDOperand N0 = N->getOperand(0); 2968 SDOperand N1 = N->getOperand(1); 2969 // Normalize unary shuffle so the RHS is undef. 2970 if (isUnary && VecNum == 1) 2971 std::swap(N0, N1); 2972 2973 // If it is a splat, check if the argument vector is a build_vector with 2974 // all scalar elements the same. 2975 if (isSplat) { 2976 SDNode *V = N0.Val; 2977 if (V->getOpcode() == ISD::VBIT_CONVERT) 2978 V = V->getOperand(0).Val; 2979 if (V->getOpcode() == ISD::VBUILD_VECTOR) { 2980 unsigned NumElems = V->getNumOperands()-2; 2981 if (NumElems > BaseIdx) { 2982 SDOperand Base; 2983 bool AllSame = true; 2984 for (unsigned i = 0; i != NumElems; ++i) { 2985 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 2986 Base = V->getOperand(i); 2987 break; 2988 } 2989 } 2990 // Splat of <u, u, u, u>, return <u, u, u, u> 2991 if (!Base.Val) 2992 return N0; 2993 for (unsigned i = 0; i != NumElems; ++i) { 2994 if (V->getOperand(i).getOpcode() != ISD::UNDEF && 2995 V->getOperand(i) != Base) { 2996 AllSame = false; 2997 break; 2998 } 2999 } 3000 // Splat of <x, x, x, x>, return <x, x, x, x> 3001 if (AllSame) 3002 return N0; 3003 } 3004 } 3005 } 3006 3007 // If it is a unary or the LHS and the RHS are the same node, turn the RHS 3008 // into an undef. 3009 if (isUnary || N0 == N1) { 3010 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the 3011 // first operand. 3012 SmallVector<SDOperand, 8> MappedOps; 3013 for (unsigned i = 0; i != NumElts; ++i) { 3014 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || 3015 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) { 3016 MappedOps.push_back(ShufMask.getOperand(i)); 3017 } else { 3018 unsigned NewIdx = 3019 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts; 3020 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32)); 3021 } 3022 } 3023 // Add the type/#elts values. 3024 MappedOps.push_back(ShufMask.getOperand(NumElts)); 3025 MappedOps.push_back(ShufMask.getOperand(NumElts+1)); 3026 3027 ShufMask = DAG.getNode(ISD::VBUILD_VECTOR, ShufMask.getValueType(), 3028 &MappedOps[0], MappedOps.size()); 3029 AddToWorkList(ShufMask.Val); 3030 3031 // Build the undef vector. 3032 SDOperand UDVal = DAG.getNode(ISD::UNDEF, MappedOps[0].getValueType()); 3033 for (unsigned i = 0; i != NumElts; ++i) 3034 MappedOps[i] = UDVal; 3035 MappedOps[NumElts ] = *(N0.Val->op_end()-2); 3036 MappedOps[NumElts+1] = *(N0.Val->op_end()-1); 3037 UDVal = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, 3038 &MappedOps[0], MappedOps.size()); 3039 3040 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, 3041 N0, UDVal, ShufMask, 3042 MappedOps[NumElts], MappedOps[NumElts+1]); 3043 } 3044 3045 return SDOperand(); 3046} 3047 3048/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 3049/// a VAND to a vector_shuffle with the destination vector and a zero vector. 3050/// e.g. VAND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 3051/// vector_shuffle V, Zero, <0, 4, 2, 4> 3052SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) { 3053 SDOperand LHS = N->getOperand(0); 3054 SDOperand RHS = N->getOperand(1); 3055 if (N->getOpcode() == ISD::VAND) { 3056 SDOperand DstVecSize = *(LHS.Val->op_end()-2); 3057 SDOperand DstVecEVT = *(LHS.Val->op_end()-1); 3058 if (RHS.getOpcode() == ISD::VBIT_CONVERT) 3059 RHS = RHS.getOperand(0); 3060 if (RHS.getOpcode() == ISD::VBUILD_VECTOR) { 3061 std::vector<SDOperand> IdxOps; 3062 unsigned NumOps = RHS.getNumOperands(); 3063 unsigned NumElts = NumOps-2; 3064 MVT::ValueType EVT = cast<VTSDNode>(RHS.getOperand(NumOps-1))->getVT(); 3065 for (unsigned i = 0; i != NumElts; ++i) { 3066 SDOperand Elt = RHS.getOperand(i); 3067 if (!isa<ConstantSDNode>(Elt)) 3068 return SDOperand(); 3069 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 3070 IdxOps.push_back(DAG.getConstant(i, EVT)); 3071 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 3072 IdxOps.push_back(DAG.getConstant(NumElts, EVT)); 3073 else 3074 return SDOperand(); 3075 } 3076 3077 // Let's see if the target supports this vector_shuffle. 3078 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG)) 3079 return SDOperand(); 3080 3081 // Return the new VVECTOR_SHUFFLE node. 3082 SDOperand NumEltsNode = DAG.getConstant(NumElts, MVT::i32); 3083 SDOperand EVTNode = DAG.getValueType(EVT); 3084 std::vector<SDOperand> Ops; 3085 LHS = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, LHS, NumEltsNode, 3086 EVTNode); 3087 Ops.push_back(LHS); 3088 AddToWorkList(LHS.Val); 3089 std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT)); 3090 ZeroOps.push_back(NumEltsNode); 3091 ZeroOps.push_back(EVTNode); 3092 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, 3093 &ZeroOps[0], ZeroOps.size())); 3094 IdxOps.push_back(NumEltsNode); 3095 IdxOps.push_back(EVTNode); 3096 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, 3097 &IdxOps[0], IdxOps.size())); 3098 Ops.push_back(NumEltsNode); 3099 Ops.push_back(EVTNode); 3100 SDOperand Result = DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, 3101 &Ops[0], Ops.size()); 3102 if (NumEltsNode != DstVecSize || EVTNode != DstVecEVT) { 3103 Result = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Result, 3104 DstVecSize, DstVecEVT); 3105 } 3106 return Result; 3107 } 3108 } 3109 return SDOperand(); 3110} 3111 3112/// visitVBinOp - Visit a binary vector operation, like VADD. IntOp indicates 3113/// the scalar operation of the vop if it is operating on an integer vector 3114/// (e.g. ADD) and FPOp indicates the FP version (e.g. FADD). 3115SDOperand DAGCombiner::visitVBinOp(SDNode *N, ISD::NodeType IntOp, 3116 ISD::NodeType FPOp) { 3117 MVT::ValueType EltType = cast<VTSDNode>(*(N->op_end()-1))->getVT(); 3118 ISD::NodeType ScalarOp = MVT::isInteger(EltType) ? IntOp : FPOp; 3119 SDOperand LHS = N->getOperand(0); 3120 SDOperand RHS = N->getOperand(1); 3121 SDOperand Shuffle = XformToShuffleWithZero(N); 3122 if (Shuffle.Val) return Shuffle; 3123 3124 // If the LHS and RHS are VBUILD_VECTOR nodes, see if we can constant fold 3125 // this operation. 3126 if (LHS.getOpcode() == ISD::VBUILD_VECTOR && 3127 RHS.getOpcode() == ISD::VBUILD_VECTOR) { 3128 SmallVector<SDOperand, 8> Ops; 3129 for (unsigned i = 0, e = LHS.getNumOperands()-2; i != e; ++i) { 3130 SDOperand LHSOp = LHS.getOperand(i); 3131 SDOperand RHSOp = RHS.getOperand(i); 3132 // If these two elements can't be folded, bail out. 3133 if ((LHSOp.getOpcode() != ISD::UNDEF && 3134 LHSOp.getOpcode() != ISD::Constant && 3135 LHSOp.getOpcode() != ISD::ConstantFP) || 3136 (RHSOp.getOpcode() != ISD::UNDEF && 3137 RHSOp.getOpcode() != ISD::Constant && 3138 RHSOp.getOpcode() != ISD::ConstantFP)) 3139 break; 3140 // Can't fold divide by zero. 3141 if (N->getOpcode() == ISD::VSDIV || N->getOpcode() == ISD::VUDIV) { 3142 if ((RHSOp.getOpcode() == ISD::Constant && 3143 cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) || 3144 (RHSOp.getOpcode() == ISD::ConstantFP && 3145 !cast<ConstantFPSDNode>(RHSOp.Val)->getValue())) 3146 break; 3147 } 3148 Ops.push_back(DAG.getNode(ScalarOp, EltType, LHSOp, RHSOp)); 3149 AddToWorkList(Ops.back().Val); 3150 assert((Ops.back().getOpcode() == ISD::UNDEF || 3151 Ops.back().getOpcode() == ISD::Constant || 3152 Ops.back().getOpcode() == ISD::ConstantFP) && 3153 "Scalar binop didn't fold!"); 3154 } 3155 3156 if (Ops.size() == LHS.getNumOperands()-2) { 3157 Ops.push_back(*(LHS.Val->op_end()-2)); 3158 Ops.push_back(*(LHS.Val->op_end()-1)); 3159 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size()); 3160 } 3161 } 3162 3163 return SDOperand(); 3164} 3165 3166SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){ 3167 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 3168 3169 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2, 3170 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 3171 // If we got a simplified select_cc node back from SimplifySelectCC, then 3172 // break it down into a new SETCC node, and a new SELECT node, and then return 3173 // the SELECT node, since we were called with a SELECT node. 3174 if (SCC.Val) { 3175 // Check to see if we got a select_cc back (to turn into setcc/select). 3176 // Otherwise, just return whatever node we got back, like fabs. 3177 if (SCC.getOpcode() == ISD::SELECT_CC) { 3178 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(), 3179 SCC.getOperand(0), SCC.getOperand(1), 3180 SCC.getOperand(4)); 3181 AddToWorkList(SETCC.Val); 3182 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2), 3183 SCC.getOperand(3), SETCC); 3184 } 3185 return SCC; 3186 } 3187 return SDOperand(); 3188} 3189 3190/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 3191/// are the two values being selected between, see if we can simplify the 3192/// select. Callers of this should assume that TheSelect is deleted if this 3193/// returns true. As such, they should return the appropriate thing (e.g. the 3194/// node) back to the top-level of the DAG combiner loop to avoid it being 3195/// looked at. 3196/// 3197bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS, 3198 SDOperand RHS) { 3199 3200 // If this is a select from two identical things, try to pull the operation 3201 // through the select. 3202 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 3203#if 0 3204 std::cerr << "SELECT: ["; LHS.Val->dump(); 3205 std::cerr << "] ["; RHS.Val->dump(); 3206 std::cerr << "]\n"; 3207#endif 3208 3209 // If this is a load and the token chain is identical, replace the select 3210 // of two loads with a load through a select of the address to load from. 3211 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 3212 // constants have been dropped into the constant pool. 3213 if ((LHS.getOpcode() == ISD::LOAD || 3214 LHS.getOpcode() == ISD::EXTLOAD || 3215 LHS.getOpcode() == ISD::ZEXTLOAD || 3216 LHS.getOpcode() == ISD::SEXTLOAD) && 3217 // Token chains must be identical. 3218 LHS.getOperand(0) == RHS.getOperand(0) && 3219 // If this is an EXTLOAD, the VT's must match. 3220 (LHS.getOpcode() == ISD::LOAD || 3221 LHS.getOperand(3) == RHS.getOperand(3))) { 3222 // FIXME: this conflates two src values, discarding one. This is not 3223 // the right thing to do, but nothing uses srcvalues now. When they do, 3224 // turn SrcValue into a list of locations. 3225 SDOperand Addr; 3226 if (TheSelect->getOpcode() == ISD::SELECT) 3227 Addr = DAG.getNode(ISD::SELECT, LHS.getOperand(1).getValueType(), 3228 TheSelect->getOperand(0), LHS.getOperand(1), 3229 RHS.getOperand(1)); 3230 else 3231 Addr = DAG.getNode(ISD::SELECT_CC, LHS.getOperand(1).getValueType(), 3232 TheSelect->getOperand(0), 3233 TheSelect->getOperand(1), 3234 LHS.getOperand(1), RHS.getOperand(1), 3235 TheSelect->getOperand(4)); 3236 3237 SDOperand Load; 3238 if (LHS.getOpcode() == ISD::LOAD) 3239 Load = DAG.getLoad(TheSelect->getValueType(0), LHS.getOperand(0), 3240 Addr, LHS.getOperand(2)); 3241 else 3242 Load = DAG.getExtLoad(LHS.getOpcode(), TheSelect->getValueType(0), 3243 LHS.getOperand(0), Addr, LHS.getOperand(2), 3244 cast<VTSDNode>(LHS.getOperand(3))->getVT()); 3245 // Users of the select now use the result of the load. 3246 CombineTo(TheSelect, Load); 3247 3248 // Users of the old loads now use the new load's chain. We know the 3249 // old-load value is dead now. 3250 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1)); 3251 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1)); 3252 return true; 3253 } 3254 } 3255 3256 return false; 3257} 3258 3259SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1, 3260 SDOperand N2, SDOperand N3, 3261 ISD::CondCode CC) { 3262 3263 MVT::ValueType VT = N2.getValueType(); 3264 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 3265 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 3266 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 3267 3268 // Determine if the condition we're dealing with is constant 3269 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 3270 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 3271 3272 // fold select_cc true, x, y -> x 3273 if (SCCC && SCCC->getValue()) 3274 return N2; 3275 // fold select_cc false, x, y -> y 3276 if (SCCC && SCCC->getValue() == 0) 3277 return N3; 3278 3279 // Check to see if we can simplify the select into an fabs node 3280 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 3281 // Allow either -0.0 or 0.0 3282 if (CFP->getValue() == 0.0) { 3283 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 3284 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 3285 N0 == N2 && N3.getOpcode() == ISD::FNEG && 3286 N2 == N3.getOperand(0)) 3287 return DAG.getNode(ISD::FABS, VT, N0); 3288 3289 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 3290 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 3291 N0 == N3 && N2.getOpcode() == ISD::FNEG && 3292 N2.getOperand(0) == N3) 3293 return DAG.getNode(ISD::FABS, VT, N3); 3294 } 3295 } 3296 3297 // Check to see if we can perform the "gzip trick", transforming 3298 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 3299 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 3300 MVT::isInteger(N0.getValueType()) && 3301 MVT::isInteger(N2.getValueType()) && 3302 (N1C->isNullValue() || // (a < 0) ? b : 0 3303 (N1C->getValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 3304 MVT::ValueType XType = N0.getValueType(); 3305 MVT::ValueType AType = N2.getValueType(); 3306 if (XType >= AType) { 3307 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 3308 // single-bit constant. 3309 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) { 3310 unsigned ShCtV = Log2_64(N2C->getValue()); 3311 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1; 3312 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy()); 3313 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt); 3314 AddToWorkList(Shift.Val); 3315 if (XType > AType) { 3316 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 3317 AddToWorkList(Shift.Val); 3318 } 3319 return DAG.getNode(ISD::AND, AType, Shift, N2); 3320 } 3321 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 3322 DAG.getConstant(MVT::getSizeInBits(XType)-1, 3323 TLI.getShiftAmountTy())); 3324 AddToWorkList(Shift.Val); 3325 if (XType > AType) { 3326 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 3327 AddToWorkList(Shift.Val); 3328 } 3329 return DAG.getNode(ISD::AND, AType, Shift, N2); 3330 } 3331 } 3332 3333 // fold select C, 16, 0 -> shl C, 4 3334 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) && 3335 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) { 3336 // Get a SetCC of the condition 3337 // FIXME: Should probably make sure that setcc is legal if we ever have a 3338 // target where it isn't. 3339 SDOperand Temp, SCC; 3340 // cast from setcc result type to select result type 3341 if (AfterLegalize) { 3342 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 3343 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType()); 3344 } else { 3345 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC); 3346 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 3347 } 3348 AddToWorkList(SCC.Val); 3349 AddToWorkList(Temp.Val); 3350 // shl setcc result by log2 n2c 3351 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp, 3352 DAG.getConstant(Log2_64(N2C->getValue()), 3353 TLI.getShiftAmountTy())); 3354 } 3355 3356 // Check to see if this is the equivalent of setcc 3357 // FIXME: Turn all of these into setcc if setcc if setcc is legal 3358 // otherwise, go ahead with the folds. 3359 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) { 3360 MVT::ValueType XType = N0.getValueType(); 3361 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) { 3362 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 3363 if (Res.getValueType() != VT) 3364 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res); 3365 return Res; 3366 } 3367 3368 // seteq X, 0 -> srl (ctlz X, log2(size(X))) 3369 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 3370 TLI.isOperationLegal(ISD::CTLZ, XType)) { 3371 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0); 3372 return DAG.getNode(ISD::SRL, XType, Ctlz, 3373 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)), 3374 TLI.getShiftAmountTy())); 3375 } 3376 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) 3377 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 3378 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType), 3379 N0); 3380 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0, 3381 DAG.getConstant(~0ULL, XType)); 3382 return DAG.getNode(ISD::SRL, XType, 3383 DAG.getNode(ISD::AND, XType, NegN0, NotN0), 3384 DAG.getConstant(MVT::getSizeInBits(XType)-1, 3385 TLI.getShiftAmountTy())); 3386 } 3387 // setgt X, -1 -> xor (srl (X, size(X)-1), 1) 3388 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 3389 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0, 3390 DAG.getConstant(MVT::getSizeInBits(XType)-1, 3391 TLI.getShiftAmountTy())); 3392 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType)); 3393 } 3394 } 3395 3396 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 3397 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 3398 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 3399 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) { 3400 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0))) { 3401 MVT::ValueType XType = N0.getValueType(); 3402 if (SubC->isNullValue() && MVT::isInteger(XType)) { 3403 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 3404 DAG.getConstant(MVT::getSizeInBits(XType)-1, 3405 TLI.getShiftAmountTy())); 3406 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 3407 AddToWorkList(Shift.Val); 3408 AddToWorkList(Add.Val); 3409 return DAG.getNode(ISD::XOR, XType, Add, Shift); 3410 } 3411 } 3412 } 3413 3414 return SDOperand(); 3415} 3416 3417SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0, 3418 SDOperand N1, ISD::CondCode Cond, 3419 bool foldBooleans) { 3420 // These setcc operations always fold. 3421 switch (Cond) { 3422 default: break; 3423 case ISD::SETFALSE: 3424 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 3425 case ISD::SETTRUE: 3426 case ISD::SETTRUE2: return DAG.getConstant(1, VT); 3427 } 3428 3429 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) { 3430 uint64_t C1 = N1C->getValue(); 3431 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val)) { 3432 uint64_t C0 = N0C->getValue(); 3433 3434 // Sign extend the operands if required 3435 if (ISD::isSignedIntSetCC(Cond)) { 3436 C0 = N0C->getSignExtended(); 3437 C1 = N1C->getSignExtended(); 3438 } 3439 3440 switch (Cond) { 3441 default: assert(0 && "Unknown integer setcc!"); 3442 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT); 3443 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT); 3444 case ISD::SETULT: return DAG.getConstant(C0 < C1, VT); 3445 case ISD::SETUGT: return DAG.getConstant(C0 > C1, VT); 3446 case ISD::SETULE: return DAG.getConstant(C0 <= C1, VT); 3447 case ISD::SETUGE: return DAG.getConstant(C0 >= C1, VT); 3448 case ISD::SETLT: return DAG.getConstant((int64_t)C0 < (int64_t)C1, VT); 3449 case ISD::SETGT: return DAG.getConstant((int64_t)C0 > (int64_t)C1, VT); 3450 case ISD::SETLE: return DAG.getConstant((int64_t)C0 <= (int64_t)C1, VT); 3451 case ISD::SETGE: return DAG.getConstant((int64_t)C0 >= (int64_t)C1, VT); 3452 } 3453 } else { 3454 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an 3455 // equality comparison, then we're just comparing whether X itself is 3456 // zero. 3457 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) && 3458 N0.getOperand(0).getOpcode() == ISD::CTLZ && 3459 N0.getOperand(1).getOpcode() == ISD::Constant) { 3460 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 3461 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 3462 ShAmt == Log2_32(MVT::getSizeInBits(N0.getValueType()))) { 3463 if ((C1 == 0) == (Cond == ISD::SETEQ)) { 3464 // (srl (ctlz x), 5) == 0 -> X != 0 3465 // (srl (ctlz x), 5) != 1 -> X != 0 3466 Cond = ISD::SETNE; 3467 } else { 3468 // (srl (ctlz x), 5) != 0 -> X == 0 3469 // (srl (ctlz x), 5) == 1 -> X == 0 3470 Cond = ISD::SETEQ; 3471 } 3472 SDOperand Zero = DAG.getConstant(0, N0.getValueType()); 3473 return DAG.getSetCC(VT, N0.getOperand(0).getOperand(0), 3474 Zero, Cond); 3475 } 3476 } 3477 3478 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 3479 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 3480 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType()); 3481 3482 // If the comparison constant has bits in the upper part, the 3483 // zero-extended value could never match. 3484 if (C1 & (~0ULL << InSize)) { 3485 unsigned VSize = MVT::getSizeInBits(N0.getValueType()); 3486 switch (Cond) { 3487 case ISD::SETUGT: 3488 case ISD::SETUGE: 3489 case ISD::SETEQ: return DAG.getConstant(0, VT); 3490 case ISD::SETULT: 3491 case ISD::SETULE: 3492 case ISD::SETNE: return DAG.getConstant(1, VT); 3493 case ISD::SETGT: 3494 case ISD::SETGE: 3495 // True if the sign bit of C1 is set. 3496 return DAG.getConstant((C1 & (1ULL << VSize)) != 0, VT); 3497 case ISD::SETLT: 3498 case ISD::SETLE: 3499 // True if the sign bit of C1 isn't set. 3500 return DAG.getConstant((C1 & (1ULL << VSize)) == 0, VT); 3501 default: 3502 break; 3503 } 3504 } 3505 3506 // Otherwise, we can perform the comparison with the low bits. 3507 switch (Cond) { 3508 case ISD::SETEQ: 3509 case ISD::SETNE: 3510 case ISD::SETUGT: 3511 case ISD::SETUGE: 3512 case ISD::SETULT: 3513 case ISD::SETULE: 3514 return DAG.getSetCC(VT, N0.getOperand(0), 3515 DAG.getConstant(C1, N0.getOperand(0).getValueType()), 3516 Cond); 3517 default: 3518 break; // todo, be more careful with signed comparisons 3519 } 3520 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 3521 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 3522 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 3523 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy); 3524 MVT::ValueType ExtDstTy = N0.getValueType(); 3525 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy); 3526 3527 // If the extended part has any inconsistent bits, it cannot ever 3528 // compare equal. In other words, they have to be all ones or all 3529 // zeros. 3530 uint64_t ExtBits = 3531 (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1)); 3532 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits) 3533 return DAG.getConstant(Cond == ISD::SETNE, VT); 3534 3535 SDOperand ZextOp; 3536 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType(); 3537 if (Op0Ty == ExtSrcTy) { 3538 ZextOp = N0.getOperand(0); 3539 } else { 3540 int64_t Imm = ~0ULL >> (64-ExtSrcTyBits); 3541 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0), 3542 DAG.getConstant(Imm, Op0Ty)); 3543 } 3544 AddToWorkList(ZextOp.Val); 3545 // Otherwise, make this a use of a zext. 3546 return DAG.getSetCC(VT, ZextOp, 3547 DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)), 3548 ExtDstTy), 3549 Cond); 3550 } else if ((N1C->getValue() == 0 || N1C->getValue() == 1) && 3551 (Cond == ISD::SETEQ || Cond == ISD::SETNE) && 3552 (N0.getOpcode() == ISD::XOR || 3553 (N0.getOpcode() == ISD::AND && 3554 N0.getOperand(0).getOpcode() == ISD::XOR && 3555 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) && 3556 isa<ConstantSDNode>(N0.getOperand(1)) && 3557 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == 1) { 3558 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We can 3559 // only do this if the top bits are known zero. 3560 if (TLI.MaskedValueIsZero(N1, 3561 MVT::getIntVTBitMask(N0.getValueType())-1)) { 3562 // Okay, get the un-inverted input value. 3563 SDOperand Val; 3564 if (N0.getOpcode() == ISD::XOR) 3565 Val = N0.getOperand(0); 3566 else { 3567 assert(N0.getOpcode() == ISD::AND && 3568 N0.getOperand(0).getOpcode() == ISD::XOR); 3569 // ((X^1)&1)^1 -> X & 1 3570 Val = DAG.getNode(ISD::AND, N0.getValueType(), 3571 N0.getOperand(0).getOperand(0), N0.getOperand(1)); 3572 } 3573 return DAG.getSetCC(VT, Val, N1, 3574 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 3575 } 3576 } 3577 3578 uint64_t MinVal, MaxVal; 3579 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0)); 3580 if (ISD::isSignedIntSetCC(Cond)) { 3581 MinVal = 1ULL << (OperandBitSize-1); 3582 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined. 3583 MaxVal = ~0ULL >> (65-OperandBitSize); 3584 else 3585 MaxVal = 0; 3586 } else { 3587 MinVal = 0; 3588 MaxVal = ~0ULL >> (64-OperandBitSize); 3589 } 3590 3591 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 3592 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 3593 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 3594 --C1; // X >= C0 --> X > (C0-1) 3595 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()), 3596 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 3597 } 3598 3599 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 3600 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 3601 ++C1; // X <= C0 --> X < (C0+1) 3602 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()), 3603 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 3604 } 3605 3606 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 3607 return DAG.getConstant(0, VT); // X < MIN --> false 3608 3609 // Canonicalize setgt X, Min --> setne X, Min 3610 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 3611 return DAG.getSetCC(VT, N0, N1, ISD::SETNE); 3612 // Canonicalize setlt X, Max --> setne X, Max 3613 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) 3614 return DAG.getSetCC(VT, N0, N1, ISD::SETNE); 3615 3616 // If we have setult X, 1, turn it into seteq X, 0 3617 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 3618 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()), 3619 ISD::SETEQ); 3620 // If we have setugt X, Max-1, turn it into seteq X, Max 3621 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 3622 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()), 3623 ISD::SETEQ); 3624 3625 // If we have "setcc X, C0", check to see if we can shrink the immediate 3626 // by changing cc. 3627 3628 // SETUGT X, SINTMAX -> SETLT X, 0 3629 if (Cond == ISD::SETUGT && OperandBitSize != 1 && 3630 C1 == (~0ULL >> (65-OperandBitSize))) 3631 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()), 3632 ISD::SETLT); 3633 3634 // FIXME: Implement the rest of these. 3635 3636 // Fold bit comparisons when we can. 3637 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 3638 VT == N0.getValueType() && N0.getOpcode() == ISD::AND) 3639 if (ConstantSDNode *AndRHS = 3640 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3641 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 3642 // Perform the xform if the AND RHS is a single bit. 3643 if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) { 3644 return DAG.getNode(ISD::SRL, VT, N0, 3645 DAG.getConstant(Log2_64(AndRHS->getValue()), 3646 TLI.getShiftAmountTy())); 3647 } 3648 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) { 3649 // (X & 8) == 8 --> (X & 8) >> 3 3650 // Perform the xform if C1 is a single bit. 3651 if ((C1 & (C1-1)) == 0) { 3652 return DAG.getNode(ISD::SRL, VT, N0, 3653 DAG.getConstant(Log2_64(C1),TLI.getShiftAmountTy())); 3654 } 3655 } 3656 } 3657 } 3658 } else if (isa<ConstantSDNode>(N0.Val)) { 3659 // Ensure that the constant occurs on the RHS. 3660 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 3661 } 3662 3663 if (ConstantFPSDNode *N0C = dyn_cast<ConstantFPSDNode>(N0.Val)) 3664 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) { 3665 double C0 = N0C->getValue(), C1 = N1C->getValue(); 3666 3667 switch (Cond) { 3668 default: break; // FIXME: Implement the rest of these! 3669 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT); 3670 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT); 3671 case ISD::SETLT: return DAG.getConstant(C0 < C1, VT); 3672 case ISD::SETGT: return DAG.getConstant(C0 > C1, VT); 3673 case ISD::SETLE: return DAG.getConstant(C0 <= C1, VT); 3674 case ISD::SETGE: return DAG.getConstant(C0 >= C1, VT); 3675 } 3676 } else { 3677 // Ensure that the constant occurs on the RHS. 3678 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 3679 } 3680 3681 if (N0 == N1) { 3682 // We can always fold X == Y for integer setcc's. 3683 if (MVT::isInteger(N0.getValueType())) 3684 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 3685 unsigned UOF = ISD::getUnorderedFlavor(Cond); 3686 if (UOF == 2) // FP operators that are undefined on NaNs. 3687 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 3688 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 3689 return DAG.getConstant(UOF, VT); 3690 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 3691 // if it is not already. 3692 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; 3693 if (NewCond != Cond) 3694 return DAG.getSetCC(VT, N0, N1, NewCond); 3695 } 3696 3697 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 3698 MVT::isInteger(N0.getValueType())) { 3699 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 3700 N0.getOpcode() == ISD::XOR) { 3701 // Simplify (X+Y) == (X+Z) --> Y == Z 3702 if (N0.getOpcode() == N1.getOpcode()) { 3703 if (N0.getOperand(0) == N1.getOperand(0)) 3704 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond); 3705 if (N0.getOperand(1) == N1.getOperand(1)) 3706 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond); 3707 if (DAG.isCommutativeBinOp(N0.getOpcode())) { 3708 // If X op Y == Y op X, try other combinations. 3709 if (N0.getOperand(0) == N1.getOperand(1)) 3710 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond); 3711 if (N0.getOperand(1) == N1.getOperand(0)) 3712 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond); 3713 } 3714 } 3715 3716 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 3717 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3718 // Turn (X+C1) == C2 --> X == C2-C1 3719 if (N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse()) { 3720 return DAG.getSetCC(VT, N0.getOperand(0), 3721 DAG.getConstant(RHSC->getValue()-LHSR->getValue(), 3722 N0.getValueType()), Cond); 3723 } 3724 3725 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. 3726 if (N0.getOpcode() == ISD::XOR) 3727 // If we know that all of the inverted bits are zero, don't bother 3728 // performing the inversion. 3729 if (TLI.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getValue())) 3730 return DAG.getSetCC(VT, N0.getOperand(0), 3731 DAG.getConstant(LHSR->getValue()^RHSC->getValue(), 3732 N0.getValueType()), Cond); 3733 } 3734 3735 // Turn (C1-X) == C2 --> X == C1-C2 3736 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { 3737 if (N0.getOpcode() == ISD::SUB && N0.Val->hasOneUse()) { 3738 return DAG.getSetCC(VT, N0.getOperand(1), 3739 DAG.getConstant(SUBC->getValue()-RHSC->getValue(), 3740 N0.getValueType()), Cond); 3741 } 3742 } 3743 } 3744 3745 // Simplify (X+Z) == X --> Z == 0 3746 if (N0.getOperand(0) == N1) 3747 return DAG.getSetCC(VT, N0.getOperand(1), 3748 DAG.getConstant(0, N0.getValueType()), Cond); 3749 if (N0.getOperand(1) == N1) { 3750 if (DAG.isCommutativeBinOp(N0.getOpcode())) 3751 return DAG.getSetCC(VT, N0.getOperand(0), 3752 DAG.getConstant(0, N0.getValueType()), Cond); 3753 else { 3754 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 3755 // (Z-X) == X --> Z == X<<1 3756 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), 3757 N1, 3758 DAG.getConstant(1,TLI.getShiftAmountTy())); 3759 AddToWorkList(SH.Val); 3760 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond); 3761 } 3762 } 3763 } 3764 3765 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 3766 N1.getOpcode() == ISD::XOR) { 3767 // Simplify X == (X+Z) --> Z == 0 3768 if (N1.getOperand(0) == N0) { 3769 return DAG.getSetCC(VT, N1.getOperand(1), 3770 DAG.getConstant(0, N1.getValueType()), Cond); 3771 } else if (N1.getOperand(1) == N0) { 3772 if (DAG.isCommutativeBinOp(N1.getOpcode())) { 3773 return DAG.getSetCC(VT, N1.getOperand(0), 3774 DAG.getConstant(0, N1.getValueType()), Cond); 3775 } else { 3776 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 3777 // X == (Z-X) --> X<<1 == Z 3778 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0, 3779 DAG.getConstant(1,TLI.getShiftAmountTy())); 3780 AddToWorkList(SH.Val); 3781 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond); 3782 } 3783 } 3784 } 3785 } 3786 3787 // Fold away ALL boolean setcc's. 3788 SDOperand Temp; 3789 if (N0.getValueType() == MVT::i1 && foldBooleans) { 3790 switch (Cond) { 3791 default: assert(0 && "Unknown integer setcc!"); 3792 case ISD::SETEQ: // X == Y -> (X^Y)^1 3793 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 3794 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1)); 3795 AddToWorkList(Temp.Val); 3796 break; 3797 case ISD::SETNE: // X != Y --> (X^Y) 3798 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 3799 break; 3800 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y 3801 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y 3802 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 3803 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp); 3804 AddToWorkList(Temp.Val); 3805 break; 3806 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X 3807 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X 3808 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 3809 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp); 3810 AddToWorkList(Temp.Val); 3811 break; 3812 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y 3813 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y 3814 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 3815 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp); 3816 AddToWorkList(Temp.Val); 3817 break; 3818 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X 3819 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X 3820 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 3821 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp); 3822 break; 3823 } 3824 if (VT != MVT::i1) { 3825 AddToWorkList(N0.Val); 3826 // FIXME: If running after legalize, we probably can't do this. 3827 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 3828 } 3829 return N0; 3830 } 3831 3832 // Could not fold it. 3833 return SDOperand(); 3834} 3835 3836/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 3837/// return a DAG expression to select that will generate the same value by 3838/// multiplying by a magic number. See: 3839/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 3840SDOperand DAGCombiner::BuildSDIV(SDNode *N) { 3841 std::vector<SDNode*> Built; 3842 SDOperand S = TLI.BuildSDIV(N, DAG, &Built); 3843 3844 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 3845 ii != ee; ++ii) 3846 AddToWorkList(*ii); 3847 return S; 3848} 3849 3850/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 3851/// return a DAG expression to select that will generate the same value by 3852/// multiplying by a magic number. See: 3853/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 3854SDOperand DAGCombiner::BuildUDIV(SDNode *N) { 3855 std::vector<SDNode*> Built; 3856 SDOperand S = TLI.BuildUDIV(N, DAG, &Built); 3857 3858 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 3859 ii != ee; ++ii) 3860 AddToWorkList(*ii); 3861 return S; 3862} 3863 3864// SelectionDAG::Combine - This is the entry point for the file. 3865// 3866void SelectionDAG::Combine(bool RunningAfterLegalize) { 3867 /// run - This is the main entry point to this class. 3868 /// 3869 DAGCombiner(*this).Run(RunningAfterLegalize); 3870} 3871