DAGCombiner.cpp revision d1feb58735159bd11f17c9732883dc9b323f61e8
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "dagcombine" 16#include "llvm/CodeGen/SelectionDAG.h" 17#include "llvm/CodeGen/MachineFunction.h" 18#include "llvm/CodeGen/MachineFrameInfo.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Target/TargetData.h" 21#include "llvm/Target/TargetFrameInfo.h" 22#include "llvm/Target/TargetLowering.h" 23#include "llvm/Target/TargetMachine.h" 24#include "llvm/Target/TargetOptions.h" 25#include "llvm/ADT/SmallPtrSet.h" 26#include "llvm/ADT/Statistic.h" 27#include "llvm/Support/Compiler.h" 28#include "llvm/Support/CommandLine.h" 29#include "llvm/Support/Debug.h" 30#include "llvm/Support/MathExtras.h" 31#include <algorithm> 32#include <set> 33using namespace llvm; 34 35STATISTIC(NodesCombined , "Number of dag nodes combined"); 36STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 37STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 38 39namespace { 40 static cl::opt<bool> 41 CombinerAA("combiner-alias-analysis", cl::Hidden, 42 cl::desc("Turn on alias analysis during testing")); 43 44 static cl::opt<bool> 45 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 46 cl::desc("Include global information in alias analysis")); 47 48//------------------------------ DAGCombiner ---------------------------------// 49 50 class VISIBILITY_HIDDEN DAGCombiner { 51 SelectionDAG &DAG; 52 TargetLowering &TLI; 53 CombineLevel Level; 54 bool LegalOperations; 55 bool LegalTypes; 56 bool Fast; 57 58 // Worklist of all of the nodes that need to be simplified. 59 std::vector<SDNode*> WorkList; 60 61 // AA - Used for DAG load/store alias analysis. 62 AliasAnalysis &AA; 63 64 /// AddUsersToWorkList - When an instruction is simplified, add all users of 65 /// the instruction to the work lists because they might get more simplified 66 /// now. 67 /// 68 void AddUsersToWorkList(SDNode *N) { 69 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 70 UI != UE; ++UI) 71 AddToWorkList(*UI); 72 } 73 74 /// visit - call the node-specific routine that knows how to fold each 75 /// particular type of node. 76 SDValue visit(SDNode *N); 77 78 public: 79 /// AddToWorkList - Add to the work list making sure it's instance is at the 80 /// the back (next to be processed.) 81 void AddToWorkList(SDNode *N) { 82 removeFromWorkList(N); 83 WorkList.push_back(N); 84 } 85 86 /// removeFromWorkList - remove all instances of N from the worklist. 87 /// 88 void removeFromWorkList(SDNode *N) { 89 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 90 WorkList.end()); 91 } 92 93 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 94 bool AddTo = true); 95 96 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 97 return CombineTo(N, &Res, 1, AddTo); 98 } 99 100 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 101 bool AddTo = true) { 102 SDValue To[] = { Res0, Res1 }; 103 return CombineTo(N, To, 2, AddTo); 104 } 105 106 private: 107 108 /// SimplifyDemandedBits - Check the specified integer node value to see if 109 /// it can be simplified or if things it uses can be simplified by bit 110 /// propagation. If so, return true. 111 bool SimplifyDemandedBits(SDValue Op) { 112 APInt Demanded = APInt::getAllOnesValue(Op.getValueSizeInBits()); 113 return SimplifyDemandedBits(Op, Demanded); 114 } 115 116 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 117 118 bool CombineToPreIndexedLoadStore(SDNode *N); 119 bool CombineToPostIndexedLoadStore(SDNode *N); 120 121 122 /// combine - call the node-specific routine that knows how to fold each 123 /// particular type of node. If that doesn't do anything, try the 124 /// target-specific DAG combines. 125 SDValue combine(SDNode *N); 126 127 // Visitation implementation - Implement dag node combining for different 128 // node types. The semantics are as follows: 129 // Return Value: 130 // SDValue.getNode() == 0 - No change was made 131 // SDValue.getNode() == N - N was replaced, is dead and has been handled. 132 // otherwise - N should be replaced by the returned Operand. 133 // 134 SDValue visitTokenFactor(SDNode *N); 135 SDValue visitMERGE_VALUES(SDNode *N); 136 SDValue visitADD(SDNode *N); 137 SDValue visitSUB(SDNode *N); 138 SDValue visitADDC(SDNode *N); 139 SDValue visitADDE(SDNode *N); 140 SDValue visitMUL(SDNode *N); 141 SDValue visitSDIV(SDNode *N); 142 SDValue visitUDIV(SDNode *N); 143 SDValue visitSREM(SDNode *N); 144 SDValue visitUREM(SDNode *N); 145 SDValue visitMULHU(SDNode *N); 146 SDValue visitMULHS(SDNode *N); 147 SDValue visitSMUL_LOHI(SDNode *N); 148 SDValue visitUMUL_LOHI(SDNode *N); 149 SDValue visitSDIVREM(SDNode *N); 150 SDValue visitUDIVREM(SDNode *N); 151 SDValue visitAND(SDNode *N); 152 SDValue visitOR(SDNode *N); 153 SDValue visitXOR(SDNode *N); 154 SDValue SimplifyVBinOp(SDNode *N); 155 SDValue visitSHL(SDNode *N); 156 SDValue visitSRA(SDNode *N); 157 SDValue visitSRL(SDNode *N); 158 SDValue visitCTLZ(SDNode *N); 159 SDValue visitCTTZ(SDNode *N); 160 SDValue visitCTPOP(SDNode *N); 161 SDValue visitSELECT(SDNode *N); 162 SDValue visitSELECT_CC(SDNode *N); 163 SDValue visitSETCC(SDNode *N); 164 SDValue visitSIGN_EXTEND(SDNode *N); 165 SDValue visitZERO_EXTEND(SDNode *N); 166 SDValue visitANY_EXTEND(SDNode *N); 167 SDValue visitSIGN_EXTEND_INREG(SDNode *N); 168 SDValue visitTRUNCATE(SDNode *N); 169 SDValue visitBIT_CONVERT(SDNode *N); 170 SDValue visitBUILD_PAIR(SDNode *N); 171 SDValue visitFADD(SDNode *N); 172 SDValue visitFSUB(SDNode *N); 173 SDValue visitFMUL(SDNode *N); 174 SDValue visitFDIV(SDNode *N); 175 SDValue visitFREM(SDNode *N); 176 SDValue visitFCOPYSIGN(SDNode *N); 177 SDValue visitSINT_TO_FP(SDNode *N); 178 SDValue visitUINT_TO_FP(SDNode *N); 179 SDValue visitFP_TO_SINT(SDNode *N); 180 SDValue visitFP_TO_UINT(SDNode *N); 181 SDValue visitFP_ROUND(SDNode *N); 182 SDValue visitFP_ROUND_INREG(SDNode *N); 183 SDValue visitFP_EXTEND(SDNode *N); 184 SDValue visitFNEG(SDNode *N); 185 SDValue visitFABS(SDNode *N); 186 SDValue visitBRCOND(SDNode *N); 187 SDValue visitBR_CC(SDNode *N); 188 SDValue visitLOAD(SDNode *N); 189 SDValue visitSTORE(SDNode *N); 190 SDValue visitINSERT_VECTOR_ELT(SDNode *N); 191 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 192 SDValue visitBUILD_VECTOR(SDNode *N); 193 SDValue visitCONCAT_VECTORS(SDNode *N); 194 SDValue visitVECTOR_SHUFFLE(SDNode *N); 195 196 SDValue XformToShuffleWithZero(SDNode *N); 197 SDValue ReassociateOps(unsigned Opc, SDValue LHS, SDValue RHS); 198 199 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 200 201 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 202 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 203 SDValue SimplifySelect(SDValue N0, SDValue N1, SDValue N2); 204 SDValue SimplifySelectCC(SDValue N0, SDValue N1, SDValue N2, 205 SDValue N3, ISD::CondCode CC, 206 bool NotExtCompare = false); 207 SDValue SimplifySetCC(MVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 208 bool foldBooleans = true); 209 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 210 unsigned HiOp); 211 SDValue CombineConsecutiveLoads(SDNode *N, MVT VT); 212 SDValue ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT); 213 SDValue BuildSDIV(SDNode *N); 214 SDValue BuildUDIV(SDNode *N); 215 SDNode *MatchRotate(SDValue LHS, SDValue RHS); 216 SDValue ReduceLoadWidth(SDNode *N); 217 218 SDValue GetDemandedBits(SDValue V, const APInt &Mask); 219 220 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 221 /// looking for aliasing nodes and adding them to the Aliases vector. 222 void GatherAllAliases(SDNode *N, SDValue OriginalChain, 223 SmallVector<SDValue, 8> &Aliases); 224 225 /// isAlias - Return true if there is any possibility that the two addresses 226 /// overlap. 227 bool isAlias(SDValue Ptr1, int64_t Size1, 228 const Value *SrcValue1, int SrcValueOffset1, 229 SDValue Ptr2, int64_t Size2, 230 const Value *SrcValue2, int SrcValueOffset2); 231 232 /// FindAliasInfo - Extracts the relevant alias information from the memory 233 /// node. Returns true if the operand was a load. 234 bool FindAliasInfo(SDNode *N, 235 SDValue &Ptr, int64_t &Size, 236 const Value *&SrcValue, int &SrcValueOffset); 237 238 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 239 /// looking for a better chain (aliasing node.) 240 SDValue FindBetterChain(SDNode *N, SDValue Chain); 241 242public: 243 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, bool fast) 244 : DAG(D), 245 TLI(D.getTargetLoweringInfo()), 246 Level(Unrestricted), 247 LegalOperations(false), 248 LegalTypes(false), 249 Fast(fast), 250 AA(A) {} 251 252 /// Run - runs the dag combiner on all nodes in the work list 253 void Run(CombineLevel AtLevel); 254 }; 255} 256 257 258namespace { 259/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 260/// nodes from the worklist. 261class VISIBILITY_HIDDEN WorkListRemover : 262 public SelectionDAG::DAGUpdateListener { 263 DAGCombiner &DC; 264public: 265 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {} 266 267 virtual void NodeDeleted(SDNode *N, SDNode *E) { 268 DC.removeFromWorkList(N); 269 } 270 271 virtual void NodeUpdated(SDNode *N) { 272 // Ignore updates. 273 } 274}; 275} 276 277//===----------------------------------------------------------------------===// 278// TargetLowering::DAGCombinerInfo implementation 279//===----------------------------------------------------------------------===// 280 281void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 282 ((DAGCombiner*)DC)->AddToWorkList(N); 283} 284 285SDValue TargetLowering::DAGCombinerInfo:: 286CombineTo(SDNode *N, const std::vector<SDValue> &To) { 287 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size()); 288} 289 290SDValue TargetLowering::DAGCombinerInfo:: 291CombineTo(SDNode *N, SDValue Res) { 292 return ((DAGCombiner*)DC)->CombineTo(N, Res); 293} 294 295 296SDValue TargetLowering::DAGCombinerInfo:: 297CombineTo(SDNode *N, SDValue Res0, SDValue Res1) { 298 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1); 299} 300 301 302//===----------------------------------------------------------------------===// 303// Helper Functions 304//===----------------------------------------------------------------------===// 305 306/// isNegatibleForFree - Return 1 if we can compute the negated form of the 307/// specified expression for the same cost as the expression itself, or 2 if we 308/// can compute the negated form more cheaply than the expression itself. 309static char isNegatibleForFree(SDValue Op, bool LegalOperations, 310 unsigned Depth = 0) { 311 // No compile time optimizations on this type. 312 if (Op.getValueType() == MVT::ppcf128) 313 return 0; 314 315 // fneg is removable even if it has multiple uses. 316 if (Op.getOpcode() == ISD::FNEG) return 2; 317 318 // Don't allow anything with multiple uses. 319 if (!Op.hasOneUse()) return 0; 320 321 // Don't recurse exponentially. 322 if (Depth > 6) return 0; 323 324 switch (Op.getOpcode()) { 325 default: return false; 326 case ISD::ConstantFP: 327 // Don't invert constant FP values after legalize. The negated constant 328 // isn't necessarily legal. 329 return LegalOperations ? 0 : 1; 330 case ISD::FADD: 331 // FIXME: determine better conditions for this xform. 332 if (!UnsafeFPMath) return 0; 333 334 // -(A+B) -> -A - B 335 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 336 return V; 337 // -(A+B) -> -B - A 338 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 339 case ISD::FSUB: 340 // We can't turn -(A-B) into B-A when we honor signed zeros. 341 if (!UnsafeFPMath) return 0; 342 343 // -(A-B) -> B-A 344 return 1; 345 346 case ISD::FMUL: 347 case ISD::FDIV: 348 if (HonorSignDependentRoundingFPMath()) return 0; 349 350 // -(X*Y) -> (-X * Y) or (X*-Y) 351 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 352 return V; 353 354 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 355 356 case ISD::FP_EXTEND: 357 case ISD::FP_ROUND: 358 case ISD::FSIN: 359 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1); 360 } 361} 362 363/// GetNegatedExpression - If isNegatibleForFree returns true, this function 364/// returns the newly negated expression. 365static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 366 bool LegalOperations, unsigned Depth = 0) { 367 // fneg is removable even if it has multiple uses. 368 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 369 370 // Don't allow anything with multiple uses. 371 assert(Op.hasOneUse() && "Unknown reuse!"); 372 373 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 374 switch (Op.getOpcode()) { 375 default: assert(0 && "Unknown code"); 376 case ISD::ConstantFP: { 377 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 378 V.changeSign(); 379 return DAG.getConstantFP(V, Op.getValueType()); 380 } 381 case ISD::FADD: 382 // FIXME: determine better conditions for this xform. 383 assert(UnsafeFPMath); 384 385 // -(A+B) -> -A - B 386 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 387 return DAG.getNode(ISD::FSUB, Op.getValueType(), 388 GetNegatedExpression(Op.getOperand(0), DAG, 389 LegalOperations, Depth+1), 390 Op.getOperand(1)); 391 // -(A+B) -> -B - A 392 return DAG.getNode(ISD::FSUB, Op.getValueType(), 393 GetNegatedExpression(Op.getOperand(1), DAG, 394 LegalOperations, Depth+1), 395 Op.getOperand(0)); 396 case ISD::FSUB: 397 // We can't turn -(A-B) into B-A when we honor signed zeros. 398 assert(UnsafeFPMath); 399 400 // -(0-B) -> B 401 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 402 if (N0CFP->getValueAPF().isZero()) 403 return Op.getOperand(1); 404 405 // -(A-B) -> B-A 406 return DAG.getNode(ISD::FSUB, Op.getValueType(), Op.getOperand(1), 407 Op.getOperand(0)); 408 409 case ISD::FMUL: 410 case ISD::FDIV: 411 assert(!HonorSignDependentRoundingFPMath()); 412 413 // -(X*Y) -> -X * Y 414 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 415 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 416 GetNegatedExpression(Op.getOperand(0), DAG, 417 LegalOperations, Depth+1), 418 Op.getOperand(1)); 419 420 // -(X*Y) -> X * -Y 421 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 422 Op.getOperand(0), 423 GetNegatedExpression(Op.getOperand(1), DAG, 424 LegalOperations, Depth+1)); 425 426 case ISD::FP_EXTEND: 427 case ISD::FSIN: 428 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 429 GetNegatedExpression(Op.getOperand(0), DAG, 430 LegalOperations, Depth+1)); 431 case ISD::FP_ROUND: 432 return DAG.getNode(ISD::FP_ROUND, Op.getValueType(), 433 GetNegatedExpression(Op.getOperand(0), DAG, 434 LegalOperations, Depth+1), 435 Op.getOperand(1)); 436 } 437} 438 439 440// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 441// that selects between the values 1 and 0, making it equivalent to a setcc. 442// Also, set the incoming LHS, RHS, and CC references to the appropriate 443// nodes based on the type of node we are checking. This simplifies life a 444// bit for the callers. 445static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 446 SDValue &CC) { 447 if (N.getOpcode() == ISD::SETCC) { 448 LHS = N.getOperand(0); 449 RHS = N.getOperand(1); 450 CC = N.getOperand(2); 451 return true; 452 } 453 if (N.getOpcode() == ISD::SELECT_CC && 454 N.getOperand(2).getOpcode() == ISD::Constant && 455 N.getOperand(3).getOpcode() == ISD::Constant && 456 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 457 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 458 LHS = N.getOperand(0); 459 RHS = N.getOperand(1); 460 CC = N.getOperand(4); 461 return true; 462 } 463 return false; 464} 465 466// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 467// one use. If this is true, it allows the users to invert the operation for 468// free when it is profitable to do so. 469static bool isOneUseSetCC(SDValue N) { 470 SDValue N0, N1, N2; 471 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 472 return true; 473 return false; 474} 475 476SDValue DAGCombiner::ReassociateOps(unsigned Opc, SDValue N0, SDValue N1){ 477 MVT VT = N0.getValueType(); 478 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 479 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 480 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 481 if (isa<ConstantSDNode>(N1)) { 482 SDValue OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1); 483 AddToWorkList(OpNode.getNode()); 484 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0)); 485 } else if (N0.hasOneUse()) { 486 SDValue OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1); 487 AddToWorkList(OpNode.getNode()); 488 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1)); 489 } 490 } 491 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 492 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 493 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 494 if (isa<ConstantSDNode>(N0)) { 495 SDValue OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0); 496 AddToWorkList(OpNode.getNode()); 497 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0)); 498 } else if (N1.hasOneUse()) { 499 SDValue OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0); 500 AddToWorkList(OpNode.getNode()); 501 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1)); 502 } 503 } 504 return SDValue(); 505} 506 507SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 508 bool AddTo) { 509 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 510 ++NodesCombined; 511 DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG)); 512 DOUT << "\nWith: "; DEBUG(To[0].getNode()->dump(&DAG)); 513 DOUT << " and " << NumTo-1 << " other values\n"; 514 WorkListRemover DeadNodes(*this); 515 DAG.ReplaceAllUsesWith(N, To, &DeadNodes); 516 517 if (AddTo) { 518 // Push the new nodes and any users onto the worklist 519 for (unsigned i = 0, e = NumTo; i != e; ++i) { 520 AddToWorkList(To[i].getNode()); 521 AddUsersToWorkList(To[i].getNode()); 522 } 523 } 524 525 // Nodes can be reintroduced into the worklist. Make sure we do not 526 // process a node that has been replaced. 527 removeFromWorkList(N); 528 529 // Finally, since the node is now dead, remove it from the graph. 530 DAG.DeleteNode(N); 531 return SDValue(N, 0); 532} 533 534/// SimplifyDemandedBits - Check the specified integer node value to see if 535/// it can be simplified or if things it uses can be simplified by bit 536/// propagation. If so, return true. 537bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 538 TargetLowering::TargetLoweringOpt TLO(DAG); 539 APInt KnownZero, KnownOne; 540 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 541 return false; 542 543 // Revisit the node. 544 AddToWorkList(Op.getNode()); 545 546 // Replace the old value with the new one. 547 ++NodesCombined; 548 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.getNode()->dump(&DAG)); 549 DOUT << "\nWith: "; DEBUG(TLO.New.getNode()->dump(&DAG)); 550 DOUT << '\n'; 551 552 // Replace all uses. If any nodes become isomorphic to other nodes and 553 // are deleted, make sure to remove them from our worklist. 554 WorkListRemover DeadNodes(*this); 555 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 556 557 // Push the new node and any (possibly new) users onto the worklist. 558 AddToWorkList(TLO.New.getNode()); 559 AddUsersToWorkList(TLO.New.getNode()); 560 561 // Finally, if the node is now dead, remove it from the graph. The node 562 // may not be dead if the replacement process recursively simplified to 563 // something else needing this node. 564 if (TLO.Old.getNode()->use_empty()) { 565 removeFromWorkList(TLO.Old.getNode()); 566 567 // If the operands of this node are only used by the node, they will now 568 // be dead. Make sure to visit them first to delete dead nodes early. 569 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i) 570 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse()) 571 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode()); 572 573 DAG.DeleteNode(TLO.Old.getNode()); 574 } 575 return true; 576} 577 578//===----------------------------------------------------------------------===// 579// Main DAG Combiner implementation 580//===----------------------------------------------------------------------===// 581 582void DAGCombiner::Run(CombineLevel AtLevel) { 583 // set the instance variables, so that the various visit routines may use it. 584 Level = AtLevel; 585 LegalOperations = Level >= NoIllegalOperations; 586 LegalTypes = Level >= NoIllegalTypes; 587 588 // Add all the dag nodes to the worklist. 589 WorkList.reserve(DAG.allnodes_size()); 590 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 591 E = DAG.allnodes_end(); I != E; ++I) 592 WorkList.push_back(I); 593 594 // Create a dummy node (which is not added to allnodes), that adds a reference 595 // to the root node, preventing it from being deleted, and tracking any 596 // changes of the root. 597 HandleSDNode Dummy(DAG.getRoot()); 598 599 // The root of the dag may dangle to deleted nodes until the dag combiner is 600 // done. Set it to null to avoid confusion. 601 DAG.setRoot(SDValue()); 602 603 // while the worklist isn't empty, inspect the node on the end of it and 604 // try and combine it. 605 while (!WorkList.empty()) { 606 SDNode *N = WorkList.back(); 607 WorkList.pop_back(); 608 609 // If N has no uses, it is dead. Make sure to revisit all N's operands once 610 // N is deleted from the DAG, since they too may now be dead or may have a 611 // reduced number of uses, allowing other xforms. 612 if (N->use_empty() && N != &Dummy) { 613 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 614 AddToWorkList(N->getOperand(i).getNode()); 615 616 DAG.DeleteNode(N); 617 continue; 618 } 619 620 SDValue RV = combine(N); 621 622 if (RV.getNode() == 0) 623 continue; 624 625 ++NodesCombined; 626 627 // If we get back the same node we passed in, rather than a new node or 628 // zero, we know that the node must have defined multiple values and 629 // CombineTo was used. Since CombineTo takes care of the worklist 630 // mechanics for us, we have no work to do in this case. 631 if (RV.getNode() == N) 632 continue; 633 634 assert(N->getOpcode() != ISD::DELETED_NODE && 635 RV.getNode()->getOpcode() != ISD::DELETED_NODE && 636 "Node was deleted but visit returned new node!"); 637 638 DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG)); 639 DOUT << "\nWith: "; DEBUG(RV.getNode()->dump(&DAG)); 640 DOUT << '\n'; 641 WorkListRemover DeadNodes(*this); 642 if (N->getNumValues() == RV.getNode()->getNumValues()) 643 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes); 644 else { 645 assert(N->getValueType(0) == RV.getValueType() && 646 N->getNumValues() == 1 && "Type mismatch"); 647 SDValue OpV = RV; 648 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes); 649 } 650 651 // Push the new node and any users onto the worklist 652 AddToWorkList(RV.getNode()); 653 AddUsersToWorkList(RV.getNode()); 654 655 // Add any uses of the old node to the worklist in case this node is the 656 // last one that uses them. They may become dead after this node is 657 // deleted. 658 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 659 AddToWorkList(N->getOperand(i).getNode()); 660 661 // Nodes can be reintroduced into the worklist. Make sure we do not 662 // process a node that has been replaced. 663 removeFromWorkList(N); 664 665 // Finally, since the node is now dead, remove it from the graph. 666 DAG.DeleteNode(N); 667 } 668 669 // If the root changed (e.g. it was a dead load, update the root). 670 DAG.setRoot(Dummy.getValue()); 671} 672 673SDValue DAGCombiner::visit(SDNode *N) { 674 switch(N->getOpcode()) { 675 default: break; 676 case ISD::TokenFactor: return visitTokenFactor(N); 677 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 678 case ISD::ADD: return visitADD(N); 679 case ISD::SUB: return visitSUB(N); 680 case ISD::ADDC: return visitADDC(N); 681 case ISD::ADDE: return visitADDE(N); 682 case ISD::MUL: return visitMUL(N); 683 case ISD::SDIV: return visitSDIV(N); 684 case ISD::UDIV: return visitUDIV(N); 685 case ISD::SREM: return visitSREM(N); 686 case ISD::UREM: return visitUREM(N); 687 case ISD::MULHU: return visitMULHU(N); 688 case ISD::MULHS: return visitMULHS(N); 689 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 690 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 691 case ISD::SDIVREM: return visitSDIVREM(N); 692 case ISD::UDIVREM: return visitUDIVREM(N); 693 case ISD::AND: return visitAND(N); 694 case ISD::OR: return visitOR(N); 695 case ISD::XOR: return visitXOR(N); 696 case ISD::SHL: return visitSHL(N); 697 case ISD::SRA: return visitSRA(N); 698 case ISD::SRL: return visitSRL(N); 699 case ISD::CTLZ: return visitCTLZ(N); 700 case ISD::CTTZ: return visitCTTZ(N); 701 case ISD::CTPOP: return visitCTPOP(N); 702 case ISD::SELECT: return visitSELECT(N); 703 case ISD::SELECT_CC: return visitSELECT_CC(N); 704 case ISD::SETCC: return visitSETCC(N); 705 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 706 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 707 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 708 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 709 case ISD::TRUNCATE: return visitTRUNCATE(N); 710 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 711 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 712 case ISD::FADD: return visitFADD(N); 713 case ISD::FSUB: return visitFSUB(N); 714 case ISD::FMUL: return visitFMUL(N); 715 case ISD::FDIV: return visitFDIV(N); 716 case ISD::FREM: return visitFREM(N); 717 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 718 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 719 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 720 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 721 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 722 case ISD::FP_ROUND: return visitFP_ROUND(N); 723 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 724 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 725 case ISD::FNEG: return visitFNEG(N); 726 case ISD::FABS: return visitFABS(N); 727 case ISD::BRCOND: return visitBRCOND(N); 728 case ISD::BR_CC: return visitBR_CC(N); 729 case ISD::LOAD: return visitLOAD(N); 730 case ISD::STORE: return visitSTORE(N); 731 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 732 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 733 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 734 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 735 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 736 } 737 return SDValue(); 738} 739 740SDValue DAGCombiner::combine(SDNode *N) { 741 742 SDValue RV = visit(N); 743 744 // If nothing happened, try a target-specific DAG combine. 745 if (RV.getNode() == 0) { 746 assert(N->getOpcode() != ISD::DELETED_NODE && 747 "Node was deleted but visit returned NULL!"); 748 749 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 750 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 751 752 // Expose the DAG combiner to the target combiner impls. 753 TargetLowering::DAGCombinerInfo 754 DagCombineInfo(DAG, Level == Unrestricted, false, this); 755 756 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 757 } 758 } 759 760 // If N is a commutative binary node, try commuting it to enable more 761 // sdisel CSE. 762 if (RV.getNode() == 0 && 763 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 764 N->getNumValues() == 1) { 765 SDValue N0 = N->getOperand(0); 766 SDValue N1 = N->getOperand(1); 767 // Constant operands are canonicalized to RHS. 768 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 769 SDValue Ops[] = { N1, N0 }; 770 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 771 Ops, 2); 772 if (CSENode) 773 return SDValue(CSENode, 0); 774 } 775 } 776 777 return RV; 778} 779 780/// getInputChainForNode - Given a node, return its input chain if it has one, 781/// otherwise return a null sd operand. 782static SDValue getInputChainForNode(SDNode *N) { 783 if (unsigned NumOps = N->getNumOperands()) { 784 if (N->getOperand(0).getValueType() == MVT::Other) 785 return N->getOperand(0); 786 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 787 return N->getOperand(NumOps-1); 788 for (unsigned i = 1; i < NumOps-1; ++i) 789 if (N->getOperand(i).getValueType() == MVT::Other) 790 return N->getOperand(i); 791 } 792 return SDValue(0, 0); 793} 794 795SDValue DAGCombiner::visitTokenFactor(SDNode *N) { 796 // If N has two operands, where one has an input chain equal to the other, 797 // the 'other' chain is redundant. 798 if (N->getNumOperands() == 2) { 799 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) 800 return N->getOperand(0); 801 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) 802 return N->getOperand(1); 803 } 804 805 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 806 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 807 SmallPtrSet<SDNode*, 16> SeenOps; 808 bool Changed = false; // If we should replace this token factor. 809 810 // Start out with this token factor. 811 TFs.push_back(N); 812 813 // Iterate through token factors. The TFs grows when new token factors are 814 // encountered. 815 for (unsigned i = 0; i < TFs.size(); ++i) { 816 SDNode *TF = TFs[i]; 817 818 // Check each of the operands. 819 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 820 SDValue Op = TF->getOperand(i); 821 822 switch (Op.getOpcode()) { 823 case ISD::EntryToken: 824 // Entry tokens don't need to be added to the list. They are 825 // rededundant. 826 Changed = true; 827 break; 828 829 case ISD::TokenFactor: 830 if ((CombinerAA || Op.hasOneUse()) && 831 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { 832 // Queue up for processing. 833 TFs.push_back(Op.getNode()); 834 // Clean up in case the token factor is removed. 835 AddToWorkList(Op.getNode()); 836 Changed = true; 837 break; 838 } 839 // Fall thru 840 841 default: 842 // Only add if it isn't already in the list. 843 if (SeenOps.insert(Op.getNode())) 844 Ops.push_back(Op); 845 else 846 Changed = true; 847 break; 848 } 849 } 850 } 851 852 SDValue Result; 853 854 // If we've change things around then replace token factor. 855 if (Changed) { 856 if (Ops.empty()) { 857 // The entry token is the only possible outcome. 858 Result = DAG.getEntryNode(); 859 } else { 860 // New and improved token factor. 861 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size()); 862 } 863 864 // Don't add users to work list. 865 return CombineTo(N, Result, false); 866 } 867 868 return Result; 869} 870 871/// MERGE_VALUES can always be eliminated. 872SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 873 WorkListRemover DeadNodes(*this); 874 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 875 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i), 876 &DeadNodes); 877 removeFromWorkList(N); 878 DAG.DeleteNode(N); 879 return SDValue(N, 0); // Return N so it doesn't get rechecked! 880} 881 882 883static 884SDValue combineShlAddConstant(SDValue N0, SDValue N1, SelectionDAG &DAG) { 885 MVT VT = N0.getValueType(); 886 SDValue N00 = N0.getOperand(0); 887 SDValue N01 = N0.getOperand(1); 888 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 889 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && 890 isa<ConstantSDNode>(N00.getOperand(1))) { 891 N0 = DAG.getNode(ISD::ADD, VT, 892 DAG.getNode(ISD::SHL, VT, N00.getOperand(0), N01), 893 DAG.getNode(ISD::SHL, VT, N00.getOperand(1), N01)); 894 return DAG.getNode(ISD::ADD, VT, N0, N1); 895 } 896 return SDValue(); 897} 898 899static 900SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp, 901 SelectionDAG &DAG, const TargetLowering &TLI, 902 bool LegalOperations) { 903 MVT VT = N->getValueType(0); 904 unsigned Opc = N->getOpcode(); 905 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC; 906 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1); 907 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2); 908 ISD::CondCode CC = ISD::SETCC_INVALID; 909 910 if (isSlctCC) { 911 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get(); 912 } else { 913 SDValue CCOp = Slct.getOperand(0); 914 if (CCOp.getOpcode() == ISD::SETCC) 915 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get(); 916 } 917 918 bool DoXform = false; 919 bool InvCC = false; 920 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) && 921 "Bad input!"); 922 923 if (LHS.getOpcode() == ISD::Constant && 924 cast<ConstantSDNode>(LHS)->isNullValue()) { 925 DoXform = true; 926 } else if (CC != ISD::SETCC_INVALID && 927 RHS.getOpcode() == ISD::Constant && 928 cast<ConstantSDNode>(RHS)->isNullValue()) { 929 std::swap(LHS, RHS); 930 SDValue Op0 = Slct.getOperand(0); 931 MVT OpVT = isSlctCC ? Op0.getValueType() : 932 Op0.getOperand(0).getValueType(); 933 bool isInt = OpVT.isInteger(); 934 CC = ISD::getSetCCInverse(CC, isInt); 935 936 if (LegalOperations && !TLI.isCondCodeLegal(CC, OpVT)) 937 return SDValue(); // Inverse operator isn't legal. 938 939 DoXform = true; 940 InvCC = true; 941 } 942 943 if (DoXform) { 944 SDValue Result = DAG.getNode(Opc, VT, OtherOp, RHS); 945 if (isSlctCC) 946 return DAG.getSelectCC(OtherOp, Result, 947 Slct.getOperand(0), Slct.getOperand(1), CC); 948 SDValue CCOp = Slct.getOperand(0); 949 if (InvCC) 950 CCOp = DAG.getSetCC(CCOp.getValueType(), CCOp.getOperand(0), 951 CCOp.getOperand(1), CC); 952 return DAG.getNode(ISD::SELECT, VT, CCOp, OtherOp, Result); 953 } 954 return SDValue(); 955} 956 957SDValue DAGCombiner::visitADD(SDNode *N) { 958 SDValue N0 = N->getOperand(0); 959 SDValue N1 = N->getOperand(1); 960 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 961 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 962 MVT VT = N0.getValueType(); 963 964 // fold vector ops 965 if (VT.isVector()) { 966 SDValue FoldedVOp = SimplifyVBinOp(N); 967 if (FoldedVOp.getNode()) return FoldedVOp; 968 } 969 970 // fold (add x, undef) -> undef 971 if (N0.getOpcode() == ISD::UNDEF) 972 return N0; 973 if (N1.getOpcode() == ISD::UNDEF) 974 return N1; 975 // fold (add c1, c2) -> c1+c2 976 if (N0C && N1C) 977 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C); 978 // canonicalize constant to RHS 979 if (N0C && !N1C) 980 return DAG.getNode(ISD::ADD, VT, N1, N0); 981 // fold (add x, 0) -> x 982 if (N1C && N1C->isNullValue()) 983 return N0; 984 // fold (add Sym, c) -> Sym+c 985 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 986 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C && 987 GA->getOpcode() == ISD::GlobalAddress) 988 return DAG.getGlobalAddress(GA->getGlobal(), VT, 989 GA->getOffset() + 990 (uint64_t)N1C->getSExtValue()); 991 // fold ((c1-A)+c2) -> (c1+c2)-A 992 if (N1C && N0.getOpcode() == ISD::SUB) 993 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 994 return DAG.getNode(ISD::SUB, VT, 995 DAG.getConstant(N1C->getAPIntValue()+ 996 N0C->getAPIntValue(), VT), 997 N0.getOperand(1)); 998 // reassociate add 999 SDValue RADD = ReassociateOps(ISD::ADD, N0, N1); 1000 if (RADD.getNode() != 0) 1001 return RADD; 1002 // fold ((0-A) + B) -> B-A 1003 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 1004 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 1005 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1)); 1006 // fold (A + (0-B)) -> A-B 1007 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1008 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 1009 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1)); 1010 // fold (A+(B-A)) -> B 1011 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 1012 return N1.getOperand(0); 1013 // fold ((B-A)+A) -> B 1014 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) 1015 return N0.getOperand(0); 1016 // fold (A+(B-(A+C))) to (B-C) 1017 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1018 N0 == N1.getOperand(1).getOperand(0)) { 1019 return DAG.getNode(ISD::SUB, VT, N1.getOperand(0), 1020 N1.getOperand(1).getOperand(1)); 1021 } 1022 // fold (A+(B-(C+A))) to (B-C) 1023 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1024 N0 == N1.getOperand(1).getOperand(1)) { 1025 return DAG.getNode(ISD::SUB, VT, N1.getOperand(0), 1026 N1.getOperand(1).getOperand(0)); 1027 } 1028 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant 1029 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) { 1030 SDValue N00 = N0.getOperand(0); 1031 SDValue N01 = N0.getOperand(1); 1032 SDValue N10 = N1.getOperand(0); 1033 SDValue N11 = N1.getOperand(1); 1034 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10)) { 1035 return DAG.getNode(ISD::SUB, VT, 1036 DAG.getNode(ISD::ADD, VT, N00, N10), 1037 DAG.getNode(ISD::ADD, VT, N01, N11)); 1038 } 1039 } 1040 1041 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 1042 return SDValue(N, 0); 1043 1044 // fold (a+b) -> (a|b) iff a and b share no bits. 1045 if (VT.isInteger() && !VT.isVector()) { 1046 APInt LHSZero, LHSOne; 1047 APInt RHSZero, RHSOne; 1048 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 1049 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1050 if (LHSZero.getBoolValue()) { 1051 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1052 1053 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1054 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1055 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1056 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1057 return DAG.getNode(ISD::OR, VT, N0, N1); 1058 } 1059 } 1060 1061 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1062 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1063 SDValue Result = combineShlAddConstant(N0, N1, DAG); 1064 if (Result.getNode()) return Result; 1065 } 1066 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1067 SDValue Result = combineShlAddConstant(N1, N0, DAG); 1068 if (Result.getNode()) return Result; 1069 } 1070 1071 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c)) 1072 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) { 1073 SDValue Result = combineSelectAndUse(N, N0, N1, DAG, TLI, LegalOperations); 1074 if (Result.getNode()) return Result; 1075 } 1076 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) { 1077 SDValue Result = combineSelectAndUse(N, N1, N0, DAG, TLI, LegalOperations); 1078 if (Result.getNode()) return Result; 1079 } 1080 1081 return SDValue(); 1082} 1083 1084SDValue DAGCombiner::visitADDC(SDNode *N) { 1085 SDValue N0 = N->getOperand(0); 1086 SDValue N1 = N->getOperand(1); 1087 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1088 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1089 MVT VT = N0.getValueType(); 1090 1091 // If the flag result is dead, turn this into an ADD. 1092 if (N->hasNUsesOfValue(0, 1)) 1093 return CombineTo(N, DAG.getNode(ISD::ADD, VT, N1, N0), 1094 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 1095 1096 // canonicalize constant to RHS. 1097 if (N0C && !N1C) 1098 return DAG.getNode(ISD::ADDC, N->getVTList(), N1, N0); 1099 1100 // fold (addc x, 0) -> x + no carry out 1101 if (N1C && N1C->isNullValue()) 1102 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 1103 1104 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1105 APInt LHSZero, LHSOne; 1106 APInt RHSZero, RHSOne; 1107 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 1108 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1109 if (LHSZero.getBoolValue()) { 1110 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1111 1112 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1113 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1114 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1115 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1116 return CombineTo(N, DAG.getNode(ISD::OR, VT, N0, N1), 1117 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 1118 } 1119 1120 return SDValue(); 1121} 1122 1123SDValue DAGCombiner::visitADDE(SDNode *N) { 1124 SDValue N0 = N->getOperand(0); 1125 SDValue N1 = N->getOperand(1); 1126 SDValue CarryIn = N->getOperand(2); 1127 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1128 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1129 //MVT VT = N0.getValueType(); 1130 1131 // canonicalize constant to RHS 1132 if (N0C && !N1C) 1133 return DAG.getNode(ISD::ADDE, N->getVTList(), N1, N0, CarryIn); 1134 1135 // fold (adde x, y, false) -> (addc x, y) 1136 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1137 return DAG.getNode(ISD::ADDC, N->getVTList(), N1, N0); 1138 1139 return SDValue(); 1140} 1141 1142 1143 1144SDValue DAGCombiner::visitSUB(SDNode *N) { 1145 SDValue N0 = N->getOperand(0); 1146 SDValue N1 = N->getOperand(1); 1147 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1148 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1149 MVT VT = N0.getValueType(); 1150 1151 // fold vector ops 1152 if (VT.isVector()) { 1153 SDValue FoldedVOp = SimplifyVBinOp(N); 1154 if (FoldedVOp.getNode()) return FoldedVOp; 1155 } 1156 1157 // fold (sub x, x) -> 0 1158 if (N0 == N1) 1159 return DAG.getConstant(0, N->getValueType(0)); 1160 // fold (sub c1, c2) -> c1-c2 1161 if (N0C && N1C) 1162 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C); 1163 // fold (sub x, c) -> (add x, -c) 1164 if (N1C) 1165 return DAG.getNode(ISD::ADD, VT, N0, 1166 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1167 // fold (A+B)-A -> B 1168 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1169 return N0.getOperand(1); 1170 // fold (A+B)-B -> A 1171 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1172 return N0.getOperand(0); 1173 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c)) 1174 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) { 1175 SDValue Result = combineSelectAndUse(N, N1, N0, DAG, TLI, LegalOperations); 1176 if (Result.getNode()) return Result; 1177 } 1178 // If either operand of a sub is undef, the result is undef 1179 if (N0.getOpcode() == ISD::UNDEF) 1180 return N0; 1181 if (N1.getOpcode() == ISD::UNDEF) 1182 return N1; 1183 1184 // If the relocation model supports it, consider symbol offsets. 1185 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1186 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) { 1187 // fold (sub Sym, c) -> Sym-c 1188 if (N1C && GA->getOpcode() == ISD::GlobalAddress) 1189 return DAG.getGlobalAddress(GA->getGlobal(), VT, 1190 GA->getOffset() - 1191 (uint64_t)N1C->getSExtValue()); 1192 // fold (sub Sym+c1, Sym+c2) -> c1-c2 1193 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1)) 1194 if (GA->getGlobal() == GB->getGlobal()) 1195 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(), 1196 VT); 1197 } 1198 1199 return SDValue(); 1200} 1201 1202SDValue DAGCombiner::visitMUL(SDNode *N) { 1203 SDValue N0 = N->getOperand(0); 1204 SDValue N1 = N->getOperand(1); 1205 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1206 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1207 MVT VT = N0.getValueType(); 1208 1209 // fold vector ops 1210 if (VT.isVector()) { 1211 SDValue FoldedVOp = SimplifyVBinOp(N); 1212 if (FoldedVOp.getNode()) return FoldedVOp; 1213 } 1214 1215 // fold (mul x, undef) -> 0 1216 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1217 return DAG.getConstant(0, VT); 1218 // fold (mul c1, c2) -> c1*c2 1219 if (N0C && N1C) 1220 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C); 1221 // canonicalize constant to RHS 1222 if (N0C && !N1C) 1223 return DAG.getNode(ISD::MUL, VT, N1, N0); 1224 // fold (mul x, 0) -> 0 1225 if (N1C && N1C->isNullValue()) 1226 return N1; 1227 // fold (mul x, -1) -> 0-x 1228 if (N1C && N1C->isAllOnesValue()) 1229 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 1230 // fold (mul x, (1 << c)) -> x << c 1231 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1232 return DAG.getNode(ISD::SHL, VT, N0, 1233 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1234 TLI.getShiftAmountTy())); 1235 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1236 if (N1C && isPowerOf2_64(-N1C->getSExtValue())) { 1237 // FIXME: If the input is something that is easily negated (e.g. a 1238 // single-use add), we should put the negate there. 1239 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), 1240 DAG.getNode(ISD::SHL, VT, N0, 1241 DAG.getConstant(Log2_64(-N1C->getSExtValue()), 1242 TLI.getShiftAmountTy()))); 1243 } 1244 1245 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1246 if (N1C && N0.getOpcode() == ISD::SHL && 1247 isa<ConstantSDNode>(N0.getOperand(1))) { 1248 SDValue C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1)); 1249 AddToWorkList(C3.getNode()); 1250 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3); 1251 } 1252 1253 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1254 // use. 1255 { 1256 SDValue Sh(0,0), Y(0,0); 1257 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1258 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1259 N0.getNode()->hasOneUse()) { 1260 Sh = N0; Y = N1; 1261 } else if (N1.getOpcode() == ISD::SHL && 1262 isa<ConstantSDNode>(N1.getOperand(1)) && 1263 N1.getNode()->hasOneUse()) { 1264 Sh = N1; Y = N0; 1265 } 1266 if (Sh.getNode()) { 1267 SDValue Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y); 1268 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1)); 1269 } 1270 } 1271 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1272 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 1273 isa<ConstantSDNode>(N0.getOperand(1))) { 1274 return DAG.getNode(ISD::ADD, VT, 1275 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1), 1276 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1)); 1277 } 1278 1279 // reassociate mul 1280 SDValue RMUL = ReassociateOps(ISD::MUL, N0, N1); 1281 if (RMUL.getNode() != 0) 1282 return RMUL; 1283 1284 return SDValue(); 1285} 1286 1287SDValue DAGCombiner::visitSDIV(SDNode *N) { 1288 SDValue N0 = N->getOperand(0); 1289 SDValue N1 = N->getOperand(1); 1290 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1291 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1292 MVT VT = N->getValueType(0); 1293 1294 // fold vector ops 1295 if (VT.isVector()) { 1296 SDValue FoldedVOp = SimplifyVBinOp(N); 1297 if (FoldedVOp.getNode()) return FoldedVOp; 1298 } 1299 1300 // fold (sdiv c1, c2) -> c1/c2 1301 if (N0C && N1C && !N1C->isNullValue()) 1302 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); 1303 // fold (sdiv X, 1) -> X 1304 if (N1C && N1C->getSExtValue() == 1LL) 1305 return N0; 1306 // fold (sdiv X, -1) -> 0-X 1307 if (N1C && N1C->isAllOnesValue()) 1308 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 1309 // If we know the sign bits of both operands are zero, strength reduce to a 1310 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1311 if (!VT.isVector()) { 1312 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1313 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1); 1314 } 1315 // fold (sdiv X, pow2) -> simple ops after legalize 1316 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() && 1317 (isPowerOf2_64(N1C->getSExtValue()) || 1318 isPowerOf2_64(-N1C->getSExtValue()))) { 1319 // If dividing by powers of two is cheap, then don't perform the following 1320 // fold. 1321 if (TLI.isPow2DivCheap()) 1322 return SDValue(); 1323 int64_t pow2 = N1C->getSExtValue(); 1324 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1325 unsigned lg2 = Log2_64(abs2); 1326 // Splat the sign bit into the register 1327 SDValue SGN = DAG.getNode(ISD::SRA, VT, N0, 1328 DAG.getConstant(VT.getSizeInBits()-1, 1329 TLI.getShiftAmountTy())); 1330 AddToWorkList(SGN.getNode()); 1331 // Add (N0 < 0) ? abs2 - 1 : 0; 1332 SDValue SRL = DAG.getNode(ISD::SRL, VT, SGN, 1333 DAG.getConstant(VT.getSizeInBits()-lg2, 1334 TLI.getShiftAmountTy())); 1335 SDValue ADD = DAG.getNode(ISD::ADD, VT, N0, SRL); 1336 AddToWorkList(SRL.getNode()); 1337 AddToWorkList(ADD.getNode()); // Divide by pow2 1338 SDValue SRA = DAG.getNode(ISD::SRA, VT, ADD, 1339 DAG.getConstant(lg2, TLI.getShiftAmountTy())); 1340 // If we're dividing by a positive value, we're done. Otherwise, we must 1341 // negate the result. 1342 if (pow2 > 0) 1343 return SRA; 1344 AddToWorkList(SRA.getNode()); 1345 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA); 1346 } 1347 // if integer divide is expensive and we satisfy the requirements, emit an 1348 // alternate sequence. 1349 if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) && 1350 !TLI.isIntDivCheap()) { 1351 SDValue Op = BuildSDIV(N); 1352 if (Op.getNode()) return Op; 1353 } 1354 1355 // undef / X -> 0 1356 if (N0.getOpcode() == ISD::UNDEF) 1357 return DAG.getConstant(0, VT); 1358 // X / undef -> undef 1359 if (N1.getOpcode() == ISD::UNDEF) 1360 return N1; 1361 1362 return SDValue(); 1363} 1364 1365SDValue DAGCombiner::visitUDIV(SDNode *N) { 1366 SDValue N0 = N->getOperand(0); 1367 SDValue N1 = N->getOperand(1); 1368 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1369 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1370 MVT VT = N->getValueType(0); 1371 1372 // fold vector ops 1373 if (VT.isVector()) { 1374 SDValue FoldedVOp = SimplifyVBinOp(N); 1375 if (FoldedVOp.getNode()) return FoldedVOp; 1376 } 1377 1378 // fold (udiv c1, c2) -> c1/c2 1379 if (N0C && N1C && !N1C->isNullValue()) 1380 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); 1381 // fold (udiv x, (1 << c)) -> x >>u c 1382 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1383 return DAG.getNode(ISD::SRL, VT, N0, 1384 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1385 TLI.getShiftAmountTy())); 1386 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1387 if (N1.getOpcode() == ISD::SHL) { 1388 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1389 if (SHC->getAPIntValue().isPowerOf2()) { 1390 MVT ADDVT = N1.getOperand(1).getValueType(); 1391 SDValue Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1), 1392 DAG.getConstant(SHC->getAPIntValue() 1393 .logBase2(), 1394 ADDVT)); 1395 AddToWorkList(Add.getNode()); 1396 return DAG.getNode(ISD::SRL, VT, N0, Add); 1397 } 1398 } 1399 } 1400 // fold (udiv x, c) -> alternate 1401 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1402 SDValue Op = BuildUDIV(N); 1403 if (Op.getNode()) return Op; 1404 } 1405 1406 // undef / X -> 0 1407 if (N0.getOpcode() == ISD::UNDEF) 1408 return DAG.getConstant(0, VT); 1409 // X / undef -> undef 1410 if (N1.getOpcode() == ISD::UNDEF) 1411 return N1; 1412 1413 return SDValue(); 1414} 1415 1416SDValue DAGCombiner::visitSREM(SDNode *N) { 1417 SDValue N0 = N->getOperand(0); 1418 SDValue N1 = N->getOperand(1); 1419 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1420 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1421 MVT VT = N->getValueType(0); 1422 1423 // fold (srem c1, c2) -> c1%c2 1424 if (N0C && N1C && !N1C->isNullValue()) 1425 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); 1426 // If we know the sign bits of both operands are zero, strength reduce to a 1427 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1428 if (!VT.isVector()) { 1429 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1430 return DAG.getNode(ISD::UREM, VT, N0, N1); 1431 } 1432 1433 // If X/C can be simplified by the division-by-constant logic, lower 1434 // X%C to the equivalent of X-X/C*C. 1435 if (N1C && !N1C->isNullValue()) { 1436 SDValue Div = DAG.getNode(ISD::SDIV, VT, N0, N1); 1437 AddToWorkList(Div.getNode()); 1438 SDValue OptimizedDiv = combine(Div.getNode()); 1439 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1440 SDValue Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1); 1441 SDValue Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1442 AddToWorkList(Mul.getNode()); 1443 return Sub; 1444 } 1445 } 1446 1447 // undef % X -> 0 1448 if (N0.getOpcode() == ISD::UNDEF) 1449 return DAG.getConstant(0, VT); 1450 // X % undef -> undef 1451 if (N1.getOpcode() == ISD::UNDEF) 1452 return N1; 1453 1454 return SDValue(); 1455} 1456 1457SDValue DAGCombiner::visitUREM(SDNode *N) { 1458 SDValue N0 = N->getOperand(0); 1459 SDValue N1 = N->getOperand(1); 1460 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1461 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1462 MVT VT = N->getValueType(0); 1463 1464 // fold (urem c1, c2) -> c1%c2 1465 if (N0C && N1C && !N1C->isNullValue()) 1466 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C); 1467 // fold (urem x, pow2) -> (and x, pow2-1) 1468 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 1469 return DAG.getNode(ISD::AND, VT, N0, 1470 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 1471 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1472 if (N1.getOpcode() == ISD::SHL) { 1473 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1474 if (SHC->getAPIntValue().isPowerOf2()) { 1475 SDValue Add = 1476 DAG.getNode(ISD::ADD, VT, N1, 1477 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 1478 VT)); 1479 AddToWorkList(Add.getNode()); 1480 return DAG.getNode(ISD::AND, VT, N0, Add); 1481 } 1482 } 1483 } 1484 1485 // If X/C can be simplified by the division-by-constant logic, lower 1486 // X%C to the equivalent of X-X/C*C. 1487 if (N1C && !N1C->isNullValue()) { 1488 SDValue Div = DAG.getNode(ISD::UDIV, VT, N0, N1); 1489 AddToWorkList(Div.getNode()); 1490 SDValue OptimizedDiv = combine(Div.getNode()); 1491 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1492 SDValue Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1); 1493 SDValue Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1494 AddToWorkList(Mul.getNode()); 1495 return Sub; 1496 } 1497 } 1498 1499 // undef % X -> 0 1500 if (N0.getOpcode() == ISD::UNDEF) 1501 return DAG.getConstant(0, VT); 1502 // X % undef -> undef 1503 if (N1.getOpcode() == ISD::UNDEF) 1504 return N1; 1505 1506 return SDValue(); 1507} 1508 1509SDValue DAGCombiner::visitMULHS(SDNode *N) { 1510 SDValue N0 = N->getOperand(0); 1511 SDValue N1 = N->getOperand(1); 1512 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1513 MVT VT = N->getValueType(0); 1514 1515 // fold (mulhs x, 0) -> 0 1516 if (N1C && N1C->isNullValue()) 1517 return N1; 1518 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1519 if (N1C && N1C->getAPIntValue() == 1) 1520 return DAG.getNode(ISD::SRA, N0.getValueType(), N0, 1521 DAG.getConstant(N0.getValueType().getSizeInBits()-1, 1522 TLI.getShiftAmountTy())); 1523 // fold (mulhs x, undef) -> 0 1524 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1525 return DAG.getConstant(0, VT); 1526 1527 return SDValue(); 1528} 1529 1530SDValue DAGCombiner::visitMULHU(SDNode *N) { 1531 SDValue N0 = N->getOperand(0); 1532 SDValue N1 = N->getOperand(1); 1533 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1534 MVT VT = N->getValueType(0); 1535 1536 // fold (mulhu x, 0) -> 0 1537 if (N1C && N1C->isNullValue()) 1538 return N1; 1539 // fold (mulhu x, 1) -> 0 1540 if (N1C && N1C->getAPIntValue() == 1) 1541 return DAG.getConstant(0, N0.getValueType()); 1542 // fold (mulhu x, undef) -> 0 1543 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1544 return DAG.getConstant(0, VT); 1545 1546 return SDValue(); 1547} 1548 1549/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 1550/// compute two values. LoOp and HiOp give the opcodes for the two computations 1551/// that are being performed. Return true if a simplification was made. 1552/// 1553SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 1554 unsigned HiOp) { 1555 // If the high half is not needed, just compute the low half. 1556 bool HiExists = N->hasAnyUseOfValue(1); 1557 if (!HiExists && 1558 (!LegalOperations || 1559 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 1560 SDValue Res = DAG.getNode(LoOp, N->getValueType(0), N->op_begin(), 1561 N->getNumOperands()); 1562 return CombineTo(N, Res, Res); 1563 } 1564 1565 // If the low half is not needed, just compute the high half. 1566 bool LoExists = N->hasAnyUseOfValue(0); 1567 if (!LoExists && 1568 (!LegalOperations || 1569 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 1570 SDValue Res = DAG.getNode(HiOp, N->getValueType(1), N->op_begin(), 1571 N->getNumOperands()); 1572 return CombineTo(N, Res, Res); 1573 } 1574 1575 // If both halves are used, return as it is. 1576 if (LoExists && HiExists) 1577 return SDValue(); 1578 1579 // If the two computed results can be simplified separately, separate them. 1580 if (LoExists) { 1581 SDValue Lo = DAG.getNode(LoOp, N->getValueType(0), 1582 N->op_begin(), N->getNumOperands()); 1583 AddToWorkList(Lo.getNode()); 1584 SDValue LoOpt = combine(Lo.getNode()); 1585 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && 1586 (!LegalOperations || 1587 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 1588 return CombineTo(N, LoOpt, LoOpt); 1589 } 1590 1591 if (HiExists) { 1592 SDValue Hi = DAG.getNode(HiOp, N->getValueType(1), 1593 N->op_begin(), N->getNumOperands()); 1594 AddToWorkList(Hi.getNode()); 1595 SDValue HiOpt = combine(Hi.getNode()); 1596 if (HiOpt.getNode() && HiOpt != Hi && 1597 (!LegalOperations || 1598 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 1599 return CombineTo(N, HiOpt, HiOpt); 1600 } 1601 return SDValue(); 1602} 1603 1604SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 1605 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 1606 if (Res.getNode()) return Res; 1607 1608 return SDValue(); 1609} 1610 1611SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 1612 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 1613 if (Res.getNode()) return Res; 1614 1615 return SDValue(); 1616} 1617 1618SDValue DAGCombiner::visitSDIVREM(SDNode *N) { 1619 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 1620 if (Res.getNode()) return Res; 1621 1622 return SDValue(); 1623} 1624 1625SDValue DAGCombiner::visitUDIVREM(SDNode *N) { 1626 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 1627 if (Res.getNode()) return Res; 1628 1629 return SDValue(); 1630} 1631 1632/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 1633/// two operands of the same opcode, try to simplify it. 1634SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 1635 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 1636 MVT VT = N0.getValueType(); 1637 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 1638 1639 // For each of OP in AND/OR/XOR: 1640 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 1641 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 1642 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 1643 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) 1644 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND|| 1645 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) && 1646 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1647 SDValue ORNode = DAG.getNode(N->getOpcode(), 1648 N0.getOperand(0).getValueType(), 1649 N0.getOperand(0), N1.getOperand(0)); 1650 AddToWorkList(ORNode.getNode()); 1651 return DAG.getNode(N0.getOpcode(), VT, ORNode); 1652 } 1653 1654 // For each of OP in SHL/SRL/SRA/AND... 1655 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 1656 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 1657 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 1658 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 1659 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 1660 N0.getOperand(1) == N1.getOperand(1)) { 1661 SDValue ORNode = DAG.getNode(N->getOpcode(), 1662 N0.getOperand(0).getValueType(), 1663 N0.getOperand(0), N1.getOperand(0)); 1664 AddToWorkList(ORNode.getNode()); 1665 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1)); 1666 } 1667 1668 return SDValue(); 1669} 1670 1671SDValue DAGCombiner::visitAND(SDNode *N) { 1672 SDValue N0 = N->getOperand(0); 1673 SDValue N1 = N->getOperand(1); 1674 SDValue LL, LR, RL, RR, CC0, CC1; 1675 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1676 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1677 MVT VT = N1.getValueType(); 1678 unsigned BitWidth = VT.getSizeInBits(); 1679 1680 // fold vector ops 1681 if (VT.isVector()) { 1682 SDValue FoldedVOp = SimplifyVBinOp(N); 1683 if (FoldedVOp.getNode()) return FoldedVOp; 1684 } 1685 1686 // fold (and x, undef) -> 0 1687 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1688 return DAG.getConstant(0, VT); 1689 // fold (and c1, c2) -> c1&c2 1690 if (N0C && N1C) 1691 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C); 1692 // canonicalize constant to RHS 1693 if (N0C && !N1C) 1694 return DAG.getNode(ISD::AND, VT, N1, N0); 1695 // fold (and x, -1) -> x 1696 if (N1C && N1C->isAllOnesValue()) 1697 return N0; 1698 // if (and x, c) is known to be zero, return 0 1699 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 1700 APInt::getAllOnesValue(BitWidth))) 1701 return DAG.getConstant(0, VT); 1702 // reassociate and 1703 SDValue RAND = ReassociateOps(ISD::AND, N0, N1); 1704 if (RAND.getNode() != 0) 1705 return RAND; 1706 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 1707 if (N1C && N0.getOpcode() == ISD::OR) 1708 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1709 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 1710 return N1; 1711 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 1712 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1713 SDValue N0Op0 = N0.getOperand(0); 1714 APInt Mask = ~N1C->getAPIntValue(); 1715 Mask.trunc(N0Op0.getValueSizeInBits()); 1716 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 1717 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(), 1718 N0Op0); 1719 1720 // Replace uses of the AND with uses of the Zero extend node. 1721 CombineTo(N, Zext); 1722 1723 // We actually want to replace all uses of the any_extend with the 1724 // zero_extend, to avoid duplicating things. This will later cause this 1725 // AND to be folded. 1726 CombineTo(N0.getNode(), Zext); 1727 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1728 } 1729 } 1730 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 1731 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1732 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1733 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1734 1735 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1736 LL.getValueType().isInteger()) { 1737 // fold (X == 0) & (Y == 0) -> (X|Y == 0) 1738 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 1739 SDValue ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1740 AddToWorkList(ORNode.getNode()); 1741 return DAG.getSetCC(VT, ORNode, LR, Op1); 1742 } 1743 // fold (X == -1) & (Y == -1) -> (X&Y == -1) 1744 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 1745 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1746 AddToWorkList(ANDNode.getNode()); 1747 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1748 } 1749 // fold (X > -1) & (Y > -1) -> (X|Y > -1) 1750 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1751 SDValue ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1752 AddToWorkList(ORNode.getNode()); 1753 return DAG.getSetCC(VT, ORNode, LR, Op1); 1754 } 1755 } 1756 // canonicalize equivalent to ll == rl 1757 if (LL == RR && LR == RL) { 1758 Op1 = ISD::getSetCCSwappedOperands(Op1); 1759 std::swap(RL, RR); 1760 } 1761 if (LL == RL && LR == RR) { 1762 bool isInteger = LL.getValueType().isInteger(); 1763 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1764 if (Result != ISD::SETCC_INVALID && 1765 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 1766 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1767 } 1768 } 1769 1770 // Simplify: and (op x...), (op y...) -> (op (and x, y)) 1771 if (N0.getOpcode() == N1.getOpcode()) { 1772 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1773 if (Tmp.getNode()) return Tmp; 1774 } 1775 1776 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1777 // fold (and (sra)) -> (and (srl)) when possible. 1778 if (!VT.isVector() && 1779 SimplifyDemandedBits(SDValue(N, 0))) 1780 return SDValue(N, 0); 1781 // fold (zext_inreg (extload x)) -> (zextload x) 1782 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { 1783 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1784 MVT EVT = LN0->getMemoryVT(); 1785 // If we zero all the possible extended bits, then we can turn this into 1786 // a zextload if we are running before legalize or the operation is legal. 1787 unsigned BitWidth = N1.getValueSizeInBits(); 1788 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1789 BitWidth - EVT.getSizeInBits())) && 1790 ((!LegalOperations && !LN0->isVolatile()) || 1791 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { 1792 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1793 LN0->getBasePtr(), LN0->getSrcValue(), 1794 LN0->getSrcValueOffset(), EVT, 1795 LN0->isVolatile(), LN0->getAlignment()); 1796 AddToWorkList(N); 1797 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 1798 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1799 } 1800 } 1801 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1802 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 1803 N0.hasOneUse()) { 1804 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1805 MVT EVT = LN0->getMemoryVT(); 1806 // If we zero all the possible extended bits, then we can turn this into 1807 // a zextload if we are running before legalize or the operation is legal. 1808 unsigned BitWidth = N1.getValueSizeInBits(); 1809 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1810 BitWidth - EVT.getSizeInBits())) && 1811 ((!LegalOperations && !LN0->isVolatile()) || 1812 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { 1813 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1814 LN0->getBasePtr(), LN0->getSrcValue(), 1815 LN0->getSrcValueOffset(), EVT, 1816 LN0->isVolatile(), LN0->getAlignment()); 1817 AddToWorkList(N); 1818 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 1819 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1820 } 1821 } 1822 1823 // fold (and (load x), 255) -> (zextload x, i8) 1824 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1825 if (N1C && N0.getOpcode() == ISD::LOAD) { 1826 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1827 if (LN0->getExtensionType() != ISD::SEXTLOAD && 1828 LN0->isUnindexed() && N0.hasOneUse() && 1829 // Do not change the width of a volatile load. 1830 !LN0->isVolatile()) { 1831 MVT EVT = MVT::Other; 1832 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 1833 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())) 1834 EVT = MVT::getIntegerVT(ActiveBits); 1835 1836 MVT LoadedVT = LN0->getMemoryVT(); 1837 // Do not generate loads of non-round integer types since these can 1838 // be expensive (and would be wrong if the type is not byte sized). 1839 if (EVT != MVT::Other && LoadedVT.bitsGT(EVT) && EVT.isRound() && 1840 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { 1841 MVT PtrType = N0.getOperand(1).getValueType(); 1842 // For big endian targets, we need to add an offset to the pointer to 1843 // load the correct bytes. For little endian systems, we merely need to 1844 // read fewer bytes from the same pointer. 1845 unsigned LVTStoreBytes = LoadedVT.getStoreSizeInBits()/8; 1846 unsigned EVTStoreBytes = EVT.getStoreSizeInBits()/8; 1847 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 1848 unsigned Alignment = LN0->getAlignment(); 1849 SDValue NewPtr = LN0->getBasePtr(); 1850 if (TLI.isBigEndian()) { 1851 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, 1852 DAG.getConstant(PtrOff, PtrType)); 1853 Alignment = MinAlign(Alignment, PtrOff); 1854 } 1855 AddToWorkList(NewPtr.getNode()); 1856 SDValue Load = 1857 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr, 1858 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT, 1859 LN0->isVolatile(), Alignment); 1860 AddToWorkList(N); 1861 CombineTo(N0.getNode(), Load, Load.getValue(1)); 1862 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1863 } 1864 } 1865 } 1866 1867 return SDValue(); 1868} 1869 1870SDValue DAGCombiner::visitOR(SDNode *N) { 1871 SDValue N0 = N->getOperand(0); 1872 SDValue N1 = N->getOperand(1); 1873 SDValue LL, LR, RL, RR, CC0, CC1; 1874 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1875 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1876 MVT VT = N1.getValueType(); 1877 1878 // fold vector ops 1879 if (VT.isVector()) { 1880 SDValue FoldedVOp = SimplifyVBinOp(N); 1881 if (FoldedVOp.getNode()) return FoldedVOp; 1882 } 1883 1884 // fold (or x, undef) -> -1 1885 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1886 return DAG.getConstant(~0ULL, VT); 1887 // fold (or c1, c2) -> c1|c2 1888 if (N0C && N1C) 1889 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); 1890 // canonicalize constant to RHS 1891 if (N0C && !N1C) 1892 return DAG.getNode(ISD::OR, VT, N1, N0); 1893 // fold (or x, 0) -> x 1894 if (N1C && N1C->isNullValue()) 1895 return N0; 1896 // fold (or x, -1) -> -1 1897 if (N1C && N1C->isAllOnesValue()) 1898 return N1; 1899 // fold (or x, c) -> c iff (x & ~c) == 0 1900 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 1901 return N1; 1902 // reassociate or 1903 SDValue ROR = ReassociateOps(ISD::OR, N0, N1); 1904 if (ROR.getNode() != 0) 1905 return ROR; 1906 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 1907 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 1908 isa<ConstantSDNode>(N0.getOperand(1))) { 1909 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 1910 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0), 1911 N1), 1912 DAG.getConstant(N1C->getAPIntValue() | 1913 C1->getAPIntValue(), VT)); 1914 } 1915 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 1916 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1917 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1918 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1919 1920 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1921 LL.getValueType().isInteger()) { 1922 // fold (X != 0) | (Y != 0) -> (X|Y != 0) 1923 // fold (X < 0) | (Y < 0) -> (X|Y < 0) 1924 if (cast<ConstantSDNode>(LR)->isNullValue() && 1925 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 1926 SDValue ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1927 AddToWorkList(ORNode.getNode()); 1928 return DAG.getSetCC(VT, ORNode, LR, Op1); 1929 } 1930 // fold (X != -1) | (Y != -1) -> (X&Y != -1) 1931 // fold (X > -1) | (Y > -1) -> (X&Y > -1) 1932 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 1933 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 1934 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1935 AddToWorkList(ANDNode.getNode()); 1936 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1937 } 1938 } 1939 // canonicalize equivalent to ll == rl 1940 if (LL == RR && LR == RL) { 1941 Op1 = ISD::getSetCCSwappedOperands(Op1); 1942 std::swap(RL, RR); 1943 } 1944 if (LL == RL && LR == RR) { 1945 bool isInteger = LL.getValueType().isInteger(); 1946 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 1947 if (Result != ISD::SETCC_INVALID && 1948 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 1949 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1950 } 1951 } 1952 1953 // Simplify: or (op x...), (op y...) -> (op (or x, y)) 1954 if (N0.getOpcode() == N1.getOpcode()) { 1955 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1956 if (Tmp.getNode()) return Tmp; 1957 } 1958 1959 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible. 1960 if (N0.getOpcode() == ISD::AND && 1961 N1.getOpcode() == ISD::AND && 1962 N0.getOperand(1).getOpcode() == ISD::Constant && 1963 N1.getOperand(1).getOpcode() == ISD::Constant && 1964 // Don't increase # computations. 1965 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) { 1966 // We can only do this xform if we know that bits from X that are set in C2 1967 // but not in C1 are already zero. Likewise for Y. 1968 const APInt &LHSMask = 1969 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 1970 const APInt &RHSMask = 1971 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 1972 1973 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 1974 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 1975 SDValue X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0)); 1976 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT)); 1977 } 1978 } 1979 1980 1981 // See if this is some rotate idiom. 1982 if (SDNode *Rot = MatchRotate(N0, N1)) 1983 return SDValue(Rot, 0); 1984 1985 return SDValue(); 1986} 1987 1988 1989/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 1990static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 1991 if (Op.getOpcode() == ISD::AND) { 1992 if (isa<ConstantSDNode>(Op.getOperand(1))) { 1993 Mask = Op.getOperand(1); 1994 Op = Op.getOperand(0); 1995 } else { 1996 return false; 1997 } 1998 } 1999 2000 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 2001 Shift = Op; 2002 return true; 2003 } 2004 return false; 2005} 2006 2007 2008// MatchRotate - Handle an 'or' of two operands. If this is one of the many 2009// idioms for rotate, and if the target supports rotation instructions, generate 2010// a rot[lr]. 2011SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS) { 2012 // Must be a legal type. Expanded 'n promoted things won't work with rotates. 2013 MVT VT = LHS.getValueType(); 2014 if (!TLI.isTypeLegal(VT)) return 0; 2015 2016 // The target must have at least one rotate flavor. 2017 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT); 2018 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT); 2019 if (!HasROTL && !HasROTR) return 0; 2020 2021 // Match "(X shl/srl V1) & V2" where V2 may not be present. 2022 SDValue LHSShift; // The shift. 2023 SDValue LHSMask; // AND value if any. 2024 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 2025 return 0; // Not part of a rotate. 2026 2027 SDValue RHSShift; // The shift. 2028 SDValue RHSMask; // AND value if any. 2029 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 2030 return 0; // Not part of a rotate. 2031 2032 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 2033 return 0; // Not shifting the same value. 2034 2035 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 2036 return 0; // Shifts must disagree. 2037 2038 // Canonicalize shl to left side in a shl/srl pair. 2039 if (RHSShift.getOpcode() == ISD::SHL) { 2040 std::swap(LHS, RHS); 2041 std::swap(LHSShift, RHSShift); 2042 std::swap(LHSMask , RHSMask ); 2043 } 2044 2045 unsigned OpSizeInBits = VT.getSizeInBits(); 2046 SDValue LHSShiftArg = LHSShift.getOperand(0); 2047 SDValue LHSShiftAmt = LHSShift.getOperand(1); 2048 SDValue RHSShiftAmt = RHSShift.getOperand(1); 2049 2050 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 2051 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 2052 if (LHSShiftAmt.getOpcode() == ISD::Constant && 2053 RHSShiftAmt.getOpcode() == ISD::Constant) { 2054 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue(); 2055 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue(); 2056 if ((LShVal + RShVal) != OpSizeInBits) 2057 return 0; 2058 2059 SDValue Rot; 2060 if (HasROTL) 2061 Rot = DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt); 2062 else 2063 Rot = DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt); 2064 2065 // If there is an AND of either shifted operand, apply it to the result. 2066 if (LHSMask.getNode() || RHSMask.getNode()) { 2067 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 2068 2069 if (LHSMask.getNode()) { 2070 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 2071 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 2072 } 2073 if (RHSMask.getNode()) { 2074 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 2075 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 2076 } 2077 2078 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT)); 2079 } 2080 2081 return Rot.getNode(); 2082 } 2083 2084 // If there is a mask here, and we have a variable shift, we can't be sure 2085 // that we're masking out the right stuff. 2086 if (LHSMask.getNode() || RHSMask.getNode()) 2087 return 0; 2088 2089 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 2090 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 2091 if (RHSShiftAmt.getOpcode() == ISD::SUB && 2092 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 2093 if (ConstantSDNode *SUBC = 2094 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 2095 if (SUBC->getAPIntValue() == OpSizeInBits) { 2096 if (HasROTL) 2097 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).getNode(); 2098 else 2099 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).getNode(); 2100 } 2101 } 2102 } 2103 2104 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 2105 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 2106 if (LHSShiftAmt.getOpcode() == ISD::SUB && 2107 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 2108 if (ConstantSDNode *SUBC = 2109 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 2110 if (SUBC->getAPIntValue() == OpSizeInBits) { 2111 if (HasROTR) 2112 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).getNode(); 2113 else 2114 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).getNode(); 2115 } 2116 } 2117 } 2118 2119 // Look for sign/zext/any-extended or truncate cases: 2120 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2121 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2122 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2123 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && 2124 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2125 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2126 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2127 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { 2128 SDValue LExtOp0 = LHSShiftAmt.getOperand(0); 2129 SDValue RExtOp0 = RHSShiftAmt.getOperand(0); 2130 if (RExtOp0.getOpcode() == ISD::SUB && 2131 RExtOp0.getOperand(1) == LExtOp0) { 2132 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2133 // (rotl x, y) 2134 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2135 // (rotr x, (sub 32, y)) 2136 if (ConstantSDNode *SUBC = 2137 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 2138 if (SUBC->getAPIntValue() == OpSizeInBits) { 2139 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, VT, LHSShiftArg, 2140 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 2141 } 2142 } 2143 } else if (LExtOp0.getOpcode() == ISD::SUB && 2144 RExtOp0 == LExtOp0.getOperand(1)) { 2145 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2146 // (rotr x, y) 2147 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2148 // (rotl x, (sub 32, y)) 2149 if (ConstantSDNode *SUBC = 2150 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 2151 if (SUBC->getAPIntValue() == OpSizeInBits) { 2152 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, VT, LHSShiftArg, 2153 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 2154 } 2155 } 2156 } 2157 } 2158 2159 return 0; 2160} 2161 2162 2163SDValue DAGCombiner::visitXOR(SDNode *N) { 2164 SDValue N0 = N->getOperand(0); 2165 SDValue N1 = N->getOperand(1); 2166 SDValue LHS, RHS, CC; 2167 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2168 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2169 MVT VT = N0.getValueType(); 2170 2171 // fold vector ops 2172 if (VT.isVector()) { 2173 SDValue FoldedVOp = SimplifyVBinOp(N); 2174 if (FoldedVOp.getNode()) return FoldedVOp; 2175 } 2176 2177 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 2178 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 2179 return DAG.getConstant(0, VT); 2180 // fold (xor x, undef) -> undef 2181 if (N0.getOpcode() == ISD::UNDEF) 2182 return N0; 2183 if (N1.getOpcode() == ISD::UNDEF) 2184 return N1; 2185 // fold (xor c1, c2) -> c1^c2 2186 if (N0C && N1C) 2187 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); 2188 // canonicalize constant to RHS 2189 if (N0C && !N1C) 2190 return DAG.getNode(ISD::XOR, VT, N1, N0); 2191 // fold (xor x, 0) -> x 2192 if (N1C && N1C->isNullValue()) 2193 return N0; 2194 // reassociate xor 2195 SDValue RXOR = ReassociateOps(ISD::XOR, N0, N1); 2196 if (RXOR.getNode() != 0) 2197 return RXOR; 2198 2199 // fold !(x cc y) -> (x !cc y) 2200 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 2201 bool isInt = LHS.getValueType().isInteger(); 2202 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 2203 isInt); 2204 2205 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) { 2206 switch (N0.getOpcode()) { 2207 default: 2208 assert(0 && "Unhandled SetCC Equivalent!"); 2209 abort(); 2210 case ISD::SETCC: 2211 return DAG.getSetCC(VT, LHS, RHS, NotCC); 2212 case ISD::SELECT_CC: 2213 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2), 2214 N0.getOperand(3), NotCC); 2215 } 2216 } 2217 } 2218 2219 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 2220 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 2221 N0.getNode()->hasOneUse() && 2222 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 2223 SDValue V = N0.getOperand(0); 2224 V = DAG.getNode(ISD::XOR, V.getValueType(), V, 2225 DAG.getConstant(1, V.getValueType())); 2226 AddToWorkList(V.getNode()); 2227 return DAG.getNode(ISD::ZERO_EXTEND, VT, V); 2228 } 2229 2230 // fold !(x or y) -> (!x and !y) iff x or y are setcc 2231 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 2232 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2233 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2234 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 2235 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2236 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 2237 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 2238 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2239 return DAG.getNode(NewOpcode, VT, LHS, RHS); 2240 } 2241 } 2242 // fold !(x or y) -> (!x and !y) iff x or y are constants 2243 if (N1C && N1C->isAllOnesValue() && 2244 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2245 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2246 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 2247 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2248 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 2249 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 2250 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2251 return DAG.getNode(NewOpcode, VT, LHS, RHS); 2252 } 2253 } 2254 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2) 2255 if (N1C && N0.getOpcode() == ISD::XOR) { 2256 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 2257 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2258 if (N00C) 2259 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1), 2260 DAG.getConstant(N1C->getAPIntValue()^ 2261 N00C->getAPIntValue(), VT)); 2262 if (N01C) 2263 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0), 2264 DAG.getConstant(N1C->getAPIntValue()^ 2265 N01C->getAPIntValue(), VT)); 2266 } 2267 // fold (xor x, x) -> 0 2268 if (N0 == N1) { 2269 if (!VT.isVector()) { 2270 return DAG.getConstant(0, VT); 2271 } else if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)){ 2272 // Produce a vector of zeros. 2273 SDValue El = DAG.getConstant(0, VT.getVectorElementType()); 2274 std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 2275 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 2276 } 2277 } 2278 2279 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 2280 if (N0.getOpcode() == N1.getOpcode()) { 2281 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2282 if (Tmp.getNode()) return Tmp; 2283 } 2284 2285 // Simplify the expression using non-local knowledge. 2286 if (!VT.isVector() && 2287 SimplifyDemandedBits(SDValue(N, 0))) 2288 return SDValue(N, 0); 2289 2290 return SDValue(); 2291} 2292 2293/// visitShiftByConstant - Handle transforms common to the three shifts, when 2294/// the shift amount is a constant. 2295SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 2296 SDNode *LHS = N->getOperand(0).getNode(); 2297 if (!LHS->hasOneUse()) return SDValue(); 2298 2299 // We want to pull some binops through shifts, so that we have (and (shift)) 2300 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 2301 // thing happens with address calculations, so it's important to canonicalize 2302 // it. 2303 bool HighBitSet = false; // Can we transform this if the high bit is set? 2304 2305 switch (LHS->getOpcode()) { 2306 default: return SDValue(); 2307 case ISD::OR: 2308 case ISD::XOR: 2309 HighBitSet = false; // We can only transform sra if the high bit is clear. 2310 break; 2311 case ISD::AND: 2312 HighBitSet = true; // We can only transform sra if the high bit is set. 2313 break; 2314 case ISD::ADD: 2315 if (N->getOpcode() != ISD::SHL) 2316 return SDValue(); // only shl(add) not sr[al](add). 2317 HighBitSet = false; // We can only transform sra if the high bit is clear. 2318 break; 2319 } 2320 2321 // We require the RHS of the binop to be a constant as well. 2322 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 2323 if (!BinOpCst) return SDValue(); 2324 2325 2326 // FIXME: disable this for unless the input to the binop is a shift by a 2327 // constant. If it is not a shift, it pessimizes some common cases like: 2328 // 2329 //void foo(int *X, int i) { X[i & 1235] = 1; } 2330 //int bar(int *X, int i) { return X[i & 255]; } 2331 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); 2332 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 2333 BinOpLHSVal->getOpcode() != ISD::SRA && 2334 BinOpLHSVal->getOpcode() != ISD::SRL) || 2335 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 2336 return SDValue(); 2337 2338 MVT VT = N->getValueType(0); 2339 2340 // If this is a signed shift right, and the high bit is modified 2341 // by the logical operation, do not perform the transformation. 2342 // The highBitSet boolean indicates the value of the high bit of 2343 // the constant which would cause it to be modified for this 2344 // operation. 2345 if (N->getOpcode() == ISD::SRA) { 2346 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 2347 if (BinOpRHSSignSet != HighBitSet) 2348 return SDValue(); 2349 } 2350 2351 // Fold the constants, shifting the binop RHS by the shift amount. 2352 SDValue NewRHS = DAG.getNode(N->getOpcode(), N->getValueType(0), 2353 LHS->getOperand(1), N->getOperand(1)); 2354 2355 // Create the new shift. 2356 SDValue NewShift = DAG.getNode(N->getOpcode(), VT, LHS->getOperand(0), 2357 N->getOperand(1)); 2358 2359 // Create the new binop. 2360 return DAG.getNode(LHS->getOpcode(), VT, NewShift, NewRHS); 2361} 2362 2363 2364SDValue DAGCombiner::visitSHL(SDNode *N) { 2365 SDValue N0 = N->getOperand(0); 2366 SDValue N1 = N->getOperand(1); 2367 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2368 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2369 MVT VT = N0.getValueType(); 2370 unsigned OpSizeInBits = VT.getSizeInBits(); 2371 2372 // fold (shl c1, c2) -> c1<<c2 2373 if (N0C && N1C) 2374 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C); 2375 // fold (shl 0, x) -> 0 2376 if (N0C && N0C->isNullValue()) 2377 return N0; 2378 // fold (shl x, c >= size(x)) -> undef 2379 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2380 return DAG.getNode(ISD::UNDEF, VT); 2381 // fold (shl x, 0) -> x 2382 if (N1C && N1C->isNullValue()) 2383 return N0; 2384 // if (shl x, c) is known to be zero, return 0 2385 if (DAG.MaskedValueIsZero(SDValue(N, 0), 2386 APInt::getAllOnesValue(VT.getSizeInBits()))) 2387 return DAG.getConstant(0, VT); 2388 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), c)) 2389 // iff (trunc c) == c 2390 if (N1.getOpcode() == ISD::TRUNCATE && 2391 N1.getOperand(0).getOpcode() == ISD::AND && 2392 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2393 SDValue N101 = N1.getOperand(0).getOperand(1); 2394 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2395 MVT TruncVT = N1.getValueType(); 2396 SDValue N100 = N1.getOperand(0).getOperand(0); 2397 return DAG.getNode(ISD::SHL, VT, N0, 2398 DAG.getNode(ISD::AND, TruncVT, 2399 DAG.getNode(ISD::TRUNCATE, TruncVT, N100), 2400 DAG.getConstant(N101C->getZExtValue(), 2401 TruncVT))); 2402 } 2403 } 2404 2405 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2406 return SDValue(N, 0); 2407 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2) 2408 if (N1C && N0.getOpcode() == ISD::SHL && 2409 N0.getOperand(1).getOpcode() == ISD::Constant) { 2410 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2411 uint64_t c2 = N1C->getZExtValue(); 2412 if (c1 + c2 > OpSizeInBits) 2413 return DAG.getConstant(0, VT); 2414 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0), 2415 DAG.getConstant(c1 + c2, N1.getValueType())); 2416 } 2417 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or 2418 // (srl (and x, -1 << c1), c1-c2) 2419 if (N1C && N0.getOpcode() == ISD::SRL && 2420 N0.getOperand(1).getOpcode() == ISD::Constant) { 2421 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2422 uint64_t c2 = N1C->getZExtValue(); 2423 SDValue Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0), 2424 DAG.getConstant(~0ULL << c1, VT)); 2425 if (c2 > c1) 2426 return DAG.getNode(ISD::SHL, VT, Mask, 2427 DAG.getConstant(c2-c1, N1.getValueType())); 2428 else 2429 return DAG.getNode(ISD::SRL, VT, Mask, 2430 DAG.getConstant(c1-c2, N1.getValueType())); 2431 } 2432 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1) 2433 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 2434 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 2435 DAG.getConstant(~0ULL << N1C->getZExtValue(), VT)); 2436 2437 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2438} 2439 2440SDValue DAGCombiner::visitSRA(SDNode *N) { 2441 SDValue N0 = N->getOperand(0); 2442 SDValue N1 = N->getOperand(1); 2443 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2444 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2445 MVT VT = N0.getValueType(); 2446 2447 // fold (sra c1, c2) -> c1>>c2 2448 if (N0C && N1C) 2449 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); 2450 // fold (sra 0, x) -> 0 2451 if (N0C && N0C->isNullValue()) 2452 return N0; 2453 // fold (sra -1, x) -> -1 2454 if (N0C && N0C->isAllOnesValue()) 2455 return N0; 2456 // fold (sra x, c >= size(x)) -> undef 2457 if (N1C && N1C->getZExtValue() >= VT.getSizeInBits()) 2458 return DAG.getNode(ISD::UNDEF, VT); 2459 // fold (sra x, 0) -> x 2460 if (N1C && N1C->isNullValue()) 2461 return N0; 2462 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 2463 // sext_inreg. 2464 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 2465 unsigned LowBits = VT.getSizeInBits() - (unsigned)N1C->getZExtValue(); 2466 MVT EVT = MVT::getIntegerVT(LowBits); 2467 if ((!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))) 2468 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), 2469 DAG.getValueType(EVT)); 2470 } 2471 2472 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2) 2473 if (N1C && N0.getOpcode() == ISD::SRA) { 2474 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2475 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); 2476 if (Sum >= VT.getSizeInBits()) Sum = VT.getSizeInBits()-1; 2477 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), 2478 DAG.getConstant(Sum, N1C->getValueType(0))); 2479 } 2480 } 2481 2482 // fold sra (shl X, m), result_size - n 2483 // -> (sign_extend (trunc (shl X, result_size - n - m))) for 2484 // result_size - n != m. 2485 // If truncate is free for the target sext(shl) is likely to result in better 2486 // code. 2487 if (N0.getOpcode() == ISD::SHL) { 2488 // Get the two constanst of the shifts, CN0 = m, CN = n. 2489 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2490 if (N01C && N1C) { 2491 // Determine what the truncate's result bitsize and type would be. 2492 unsigned VTValSize = VT.getSizeInBits(); 2493 MVT TruncVT = 2494 MVT::getIntegerVT(VTValSize - N1C->getZExtValue()); 2495 // Determine the residual right-shift amount. 2496 unsigned ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); 2497 2498 // If the shift is not a no-op (in which case this should be just a sign 2499 // extend already), the truncated to type is legal, sign_extend is legal 2500 // on that type, and the the truncate to that type is both legal and free, 2501 // perform the transform. 2502 if (ShiftAmt && 2503 TLI.isOperationLegal(ISD::SIGN_EXTEND, TruncVT) && 2504 TLI.isOperationLegal(ISD::TRUNCATE, VT) && 2505 TLI.isTruncateFree(VT, TruncVT)) { 2506 2507 SDValue Amt = DAG.getConstant(ShiftAmt, TLI.getShiftAmountTy()); 2508 SDValue Shift = DAG.getNode(ISD::SRL, VT, N0.getOperand(0), Amt); 2509 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, TruncVT, Shift); 2510 return DAG.getNode(ISD::SIGN_EXTEND, N->getValueType(0), Trunc); 2511 } 2512 } 2513 } 2514 2515 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), c)) 2516 // iff (trunc c) == c 2517 if (N1.getOpcode() == ISD::TRUNCATE && 2518 N1.getOperand(0).getOpcode() == ISD::AND && 2519 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2520 SDValue N101 = N1.getOperand(0).getOperand(1); 2521 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2522 MVT TruncVT = N1.getValueType(); 2523 SDValue N100 = N1.getOperand(0).getOperand(0); 2524 return DAG.getNode(ISD::SRA, VT, N0, 2525 DAG.getNode(ISD::AND, TruncVT, 2526 DAG.getNode(ISD::TRUNCATE, TruncVT, N100), 2527 DAG.getConstant(N101C->getZExtValue(), 2528 TruncVT))); 2529 } 2530 } 2531 2532 // Simplify, based on bits shifted out of the LHS. 2533 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2534 return SDValue(N, 0); 2535 2536 2537 // If the sign bit is known to be zero, switch this to a SRL. 2538 if (DAG.SignBitIsZero(N0)) 2539 return DAG.getNode(ISD::SRL, VT, N0, N1); 2540 2541 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2542} 2543 2544SDValue DAGCombiner::visitSRL(SDNode *N) { 2545 SDValue N0 = N->getOperand(0); 2546 SDValue N1 = N->getOperand(1); 2547 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2548 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2549 MVT VT = N0.getValueType(); 2550 unsigned OpSizeInBits = VT.getSizeInBits(); 2551 2552 // fold (srl c1, c2) -> c1 >>u c2 2553 if (N0C && N1C) 2554 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); 2555 // fold (srl 0, x) -> 0 2556 if (N0C && N0C->isNullValue()) 2557 return N0; 2558 // fold (srl x, c >= size(x)) -> undef 2559 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2560 return DAG.getNode(ISD::UNDEF, VT); 2561 // fold (srl x, 0) -> x 2562 if (N1C && N1C->isNullValue()) 2563 return N0; 2564 // if (srl x, c) is known to be zero, return 0 2565 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2566 APInt::getAllOnesValue(OpSizeInBits))) 2567 return DAG.getConstant(0, VT); 2568 2569 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2) 2570 if (N1C && N0.getOpcode() == ISD::SRL && 2571 N0.getOperand(1).getOpcode() == ISD::Constant) { 2572 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2573 uint64_t c2 = N1C->getZExtValue(); 2574 if (c1 + c2 > OpSizeInBits) 2575 return DAG.getConstant(0, VT); 2576 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 2577 DAG.getConstant(c1 + c2, N1.getValueType())); 2578 } 2579 2580 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 2581 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2582 // Shifting in all undef bits? 2583 MVT SmallVT = N0.getOperand(0).getValueType(); 2584 if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) 2585 return DAG.getNode(ISD::UNDEF, VT); 2586 2587 SDValue SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1); 2588 AddToWorkList(SmallShift.getNode()); 2589 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift); 2590 } 2591 2592 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 2593 // bit, which is unmodified by sra. 2594 if (N1C && N1C->getZExtValue()+1 == VT.getSizeInBits()) { 2595 if (N0.getOpcode() == ISD::SRA) 2596 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1); 2597 } 2598 2599 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 2600 if (N1C && N0.getOpcode() == ISD::CTLZ && 2601 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 2602 APInt KnownZero, KnownOne; 2603 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 2604 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 2605 2606 // If any of the input bits are KnownOne, then the input couldn't be all 2607 // zeros, thus the result of the srl will always be zero. 2608 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 2609 2610 // If all of the bits input the to ctlz node are known to be zero, then 2611 // the result of the ctlz is "32" and the result of the shift is one. 2612 APInt UnknownBits = ~KnownZero & Mask; 2613 if (UnknownBits == 0) return DAG.getConstant(1, VT); 2614 2615 // Otherwise, check to see if there is exactly one bit input to the ctlz. 2616 if ((UnknownBits & (UnknownBits-1)) == 0) { 2617 // Okay, we know that only that the single bit specified by UnknownBits 2618 // could be set on input to the CTLZ node. If this bit is set, the SRL 2619 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 2620 // to an SRL,XOR pair, which is likely to simplify more. 2621 unsigned ShAmt = UnknownBits.countTrailingZeros(); 2622 SDValue Op = N0.getOperand(0); 2623 if (ShAmt) { 2624 Op = DAG.getNode(ISD::SRL, VT, Op, 2625 DAG.getConstant(ShAmt, TLI.getShiftAmountTy())); 2626 AddToWorkList(Op.getNode()); 2627 } 2628 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT)); 2629 } 2630 } 2631 2632 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), c)) 2633 // iff (trunc c) == c 2634 if (N1.getOpcode() == ISD::TRUNCATE && 2635 N1.getOperand(0).getOpcode() == ISD::AND && 2636 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2637 SDValue N101 = N1.getOperand(0).getOperand(1); 2638 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2639 MVT TruncVT = N1.getValueType(); 2640 SDValue N100 = N1.getOperand(0).getOperand(0); 2641 return DAG.getNode(ISD::SRL, VT, N0, 2642 DAG.getNode(ISD::AND, TruncVT, 2643 DAG.getNode(ISD::TRUNCATE, TruncVT, N100), 2644 DAG.getConstant(N101C->getZExtValue(), 2645 TruncVT))); 2646 } 2647 } 2648 2649 // fold operands of srl based on knowledge that the low bits are not 2650 // demanded. 2651 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2652 return SDValue(N, 0); 2653 2654 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2655} 2656 2657SDValue DAGCombiner::visitCTLZ(SDNode *N) { 2658 SDValue N0 = N->getOperand(0); 2659 MVT VT = N->getValueType(0); 2660 2661 // fold (ctlz c1) -> c2 2662 if (isa<ConstantSDNode>(N0)) 2663 return DAG.getNode(ISD::CTLZ, VT, N0); 2664 return SDValue(); 2665} 2666 2667SDValue DAGCombiner::visitCTTZ(SDNode *N) { 2668 SDValue N0 = N->getOperand(0); 2669 MVT VT = N->getValueType(0); 2670 2671 // fold (cttz c1) -> c2 2672 if (isa<ConstantSDNode>(N0)) 2673 return DAG.getNode(ISD::CTTZ, VT, N0); 2674 return SDValue(); 2675} 2676 2677SDValue DAGCombiner::visitCTPOP(SDNode *N) { 2678 SDValue N0 = N->getOperand(0); 2679 MVT VT = N->getValueType(0); 2680 2681 // fold (ctpop c1) -> c2 2682 if (isa<ConstantSDNode>(N0)) 2683 return DAG.getNode(ISD::CTPOP, VT, N0); 2684 return SDValue(); 2685} 2686 2687SDValue DAGCombiner::visitSELECT(SDNode *N) { 2688 SDValue N0 = N->getOperand(0); 2689 SDValue N1 = N->getOperand(1); 2690 SDValue N2 = N->getOperand(2); 2691 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2692 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2693 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 2694 MVT VT = N->getValueType(0); 2695 MVT VT0 = N0.getValueType(); 2696 2697 // fold select C, X, X -> X 2698 if (N1 == N2) 2699 return N1; 2700 // fold select true, X, Y -> X 2701 if (N0C && !N0C->isNullValue()) 2702 return N1; 2703 // fold select false, X, Y -> Y 2704 if (N0C && N0C->isNullValue()) 2705 return N2; 2706 // fold select C, 1, X -> C | X 2707 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 2708 return DAG.getNode(ISD::OR, VT, N0, N2); 2709 // fold select C, 0, 1 -> ~C 2710 if (VT.isInteger() && VT0.isInteger() && 2711 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 2712 SDValue XORNode = DAG.getNode(ISD::XOR, VT0, N0, DAG.getConstant(1, VT0)); 2713 if (VT == VT0) 2714 return XORNode; 2715 AddToWorkList(XORNode.getNode()); 2716 if (VT.bitsGT(VT0)) 2717 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode); 2718 return DAG.getNode(ISD::TRUNCATE, VT, XORNode); 2719 } 2720 // fold select C, 0, X -> ~C & X 2721 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 2722 SDValue XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 2723 AddToWorkList(XORNode.getNode()); 2724 return DAG.getNode(ISD::AND, VT, XORNode, N2); 2725 } 2726 // fold select C, X, 1 -> ~C | X 2727 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 2728 SDValue XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 2729 AddToWorkList(XORNode.getNode()); 2730 return DAG.getNode(ISD::OR, VT, XORNode, N1); 2731 } 2732 // fold select C, X, 0 -> C & X 2733 // FIXME: this should check for C type == X type, not i1? 2734 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 2735 return DAG.getNode(ISD::AND, VT, N0, N1); 2736 // fold X ? X : Y --> X ? 1 : Y --> X | Y 2737 if (VT == MVT::i1 && N0 == N1) 2738 return DAG.getNode(ISD::OR, VT, N0, N2); 2739 // fold X ? Y : X --> X ? Y : 0 --> X & Y 2740 if (VT == MVT::i1 && N0 == N2) 2741 return DAG.getNode(ISD::AND, VT, N0, N1); 2742 2743 // If we can fold this based on the true/false value, do so. 2744 if (SimplifySelectOps(N, N1, N2)) 2745 return SDValue(N, 0); // Don't revisit N. 2746 2747 // fold selects based on a setcc into other things, such as min/max/abs 2748 if (N0.getOpcode() == ISD::SETCC) { 2749 // FIXME: 2750 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 2751 // having to say they don't support SELECT_CC on every type the DAG knows 2752 // about, since there is no way to mark an opcode illegal at all value types 2753 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other)) 2754 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1), 2755 N1, N2, N0.getOperand(2)); 2756 else 2757 return SimplifySelect(N0, N1, N2); 2758 } 2759 return SDValue(); 2760} 2761 2762SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 2763 SDValue N0 = N->getOperand(0); 2764 SDValue N1 = N->getOperand(1); 2765 SDValue N2 = N->getOperand(2); 2766 SDValue N3 = N->getOperand(3); 2767 SDValue N4 = N->getOperand(4); 2768 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 2769 2770 // fold select_cc lhs, rhs, x, x, cc -> x 2771 if (N2 == N3) 2772 return N2; 2773 2774 // Determine if the condition we're dealing with is constant 2775 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0), N0, N1, CC, false); 2776 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 2777 2778 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) { 2779 if (!SCCC->isNullValue()) 2780 return N2; // cond always true -> true val 2781 else 2782 return N3; // cond always false -> false val 2783 } 2784 2785 // Fold to a simpler select_cc 2786 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) 2787 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(), 2788 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 2789 SCC.getOperand(2)); 2790 2791 // If we can fold this based on the true/false value, do so. 2792 if (SimplifySelectOps(N, N2, N3)) 2793 return SDValue(N, 0); // Don't revisit N. 2794 2795 // fold select_cc into other things, such as min/max/abs 2796 return SimplifySelectCC(N0, N1, N2, N3, CC); 2797} 2798 2799SDValue DAGCombiner::visitSETCC(SDNode *N) { 2800 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 2801 cast<CondCodeSDNode>(N->getOperand(2))->get()); 2802} 2803 2804// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 2805// "fold ({s|z}ext (load x)) -> ({s|z}ext (truncate ({s|z}extload x)))" 2806// transformation. Returns true if extension are possible and the above 2807// mentioned transformation is profitable. 2808static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 2809 unsigned ExtOpc, 2810 SmallVector<SDNode*, 4> &ExtendNodes, 2811 TargetLowering &TLI) { 2812 bool HasCopyToRegUses = false; 2813 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 2814 for (SDNode::use_iterator UI = N0.getNode()->use_begin(), 2815 UE = N0.getNode()->use_end(); 2816 UI != UE; ++UI) { 2817 SDNode *User = *UI; 2818 if (User == N) 2819 continue; 2820 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 2821 if (User->getOpcode() == ISD::SETCC) { 2822 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 2823 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 2824 // Sign bits will be lost after a zext. 2825 return false; 2826 bool Add = false; 2827 for (unsigned i = 0; i != 2; ++i) { 2828 SDValue UseOp = User->getOperand(i); 2829 if (UseOp == N0) 2830 continue; 2831 if (!isa<ConstantSDNode>(UseOp)) 2832 return false; 2833 Add = true; 2834 } 2835 if (Add) 2836 ExtendNodes.push_back(User); 2837 } else { 2838 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2839 SDValue UseOp = User->getOperand(i); 2840 if (UseOp == N0) { 2841 // If truncate from extended type to original load type is free 2842 // on this target, then it's ok to extend a CopyToReg. 2843 if (isTruncFree && User->getOpcode() == ISD::CopyToReg) 2844 HasCopyToRegUses = true; 2845 else 2846 return false; 2847 } 2848 } 2849 } 2850 } 2851 2852 if (HasCopyToRegUses) { 2853 bool BothLiveOut = false; 2854 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 2855 UI != UE; ++UI) { 2856 SDNode *User = *UI; 2857 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2858 SDValue UseOp = User->getOperand(i); 2859 if (UseOp.getNode() == N && UseOp.getResNo() == 0) { 2860 BothLiveOut = true; 2861 break; 2862 } 2863 } 2864 } 2865 if (BothLiveOut) 2866 // Both unextended and extended values are live out. There had better be 2867 // good a reason for the transformation. 2868 return ExtendNodes.size(); 2869 } 2870 return true; 2871} 2872 2873SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 2874 SDValue N0 = N->getOperand(0); 2875 MVT VT = N->getValueType(0); 2876 2877 // fold (sext c1) -> c1 2878 if (isa<ConstantSDNode>(N0)) 2879 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0); 2880 2881 // fold (sext (sext x)) -> (sext x) 2882 // fold (sext (aext x)) -> (sext x) 2883 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2884 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0)); 2885 2886 if (N0.getOpcode() == ISD::TRUNCATE) { 2887 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 2888 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 2889 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 2890 if (NarrowLoad.getNode()) { 2891 if (NarrowLoad.getNode() != N0.getNode()) 2892 CombineTo(N0.getNode(), NarrowLoad); 2893 return DAG.getNode(ISD::SIGN_EXTEND, VT, NarrowLoad); 2894 } 2895 2896 // See if the value being truncated is already sign extended. If so, just 2897 // eliminate the trunc/sext pair. 2898 SDValue Op = N0.getOperand(0); 2899 unsigned OpBits = Op.getValueType().getSizeInBits(); 2900 unsigned MidBits = N0.getValueType().getSizeInBits(); 2901 unsigned DestBits = VT.getSizeInBits(); 2902 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 2903 2904 if (OpBits == DestBits) { 2905 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 2906 // bits, it is already ready. 2907 if (NumSignBits > DestBits-MidBits) 2908 return Op; 2909 } else if (OpBits < DestBits) { 2910 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 2911 // bits, just sext from i32. 2912 if (NumSignBits > OpBits-MidBits) 2913 return DAG.getNode(ISD::SIGN_EXTEND, VT, Op); 2914 } else { 2915 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 2916 // bits, just truncate to i32. 2917 if (NumSignBits > OpBits-MidBits) 2918 return DAG.getNode(ISD::TRUNCATE, VT, Op); 2919 } 2920 2921 // fold (sext (truncate x)) -> (sextinreg x). 2922 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 2923 N0.getValueType())) { 2924 if (Op.getValueType().bitsLT(VT)) 2925 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2926 else if (Op.getValueType().bitsGT(VT)) 2927 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2928 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op, 2929 DAG.getValueType(N0.getValueType())); 2930 } 2931 } 2932 2933 // fold (sext (load x)) -> (sext (truncate (sextload x))) 2934 if (ISD::isNON_EXTLoad(N0.getNode()) && 2935 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 2936 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { 2937 bool DoXform = true; 2938 SmallVector<SDNode*, 4> SetCCs; 2939 if (!N0.hasOneUse()) 2940 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 2941 if (DoXform) { 2942 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2943 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2944 LN0->getBasePtr(), LN0->getSrcValue(), 2945 LN0->getSrcValueOffset(), 2946 N0.getValueType(), 2947 LN0->isVolatile(), LN0->getAlignment()); 2948 CombineTo(N, ExtLoad); 2949 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad); 2950 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 2951 // Extend SetCC uses if necessary. 2952 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 2953 SDNode *SetCC = SetCCs[i]; 2954 SmallVector<SDValue, 4> Ops; 2955 for (unsigned j = 0; j != 2; ++j) { 2956 SDValue SOp = SetCC->getOperand(j); 2957 if (SOp == Trunc) 2958 Ops.push_back(ExtLoad); 2959 else 2960 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, VT, SOp)); 2961 } 2962 Ops.push_back(SetCC->getOperand(2)); 2963 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0), 2964 &Ops[0], Ops.size())); 2965 } 2966 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2967 } 2968 } 2969 2970 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 2971 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 2972 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 2973 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 2974 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2975 MVT EVT = LN0->getMemoryVT(); 2976 if ((!LegalOperations && !LN0->isVolatile()) || 2977 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT)) { 2978 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2979 LN0->getBasePtr(), LN0->getSrcValue(), 2980 LN0->getSrcValueOffset(), EVT, 2981 LN0->isVolatile(), LN0->getAlignment()); 2982 CombineTo(N, ExtLoad); 2983 CombineTo(N0.getNode(), 2984 DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2985 ExtLoad.getValue(1)); 2986 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2987 } 2988 } 2989 2990 // sext(setcc x,y,cc) -> select_cc x, y, -1, 0, cc 2991 if (N0.getOpcode() == ISD::SETCC) { 2992 SDValue SCC = 2993 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 2994 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT), 2995 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 2996 if (SCC.getNode()) return SCC; 2997 } 2998 2999 // fold (sext x) -> (zext x) if the sign bit is known zero. 3000 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 3001 DAG.SignBitIsZero(N0)) 3002 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 3003 3004 return SDValue(); 3005} 3006 3007SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 3008 SDValue N0 = N->getOperand(0); 3009 MVT VT = N->getValueType(0); 3010 3011 // fold (zext c1) -> c1 3012 if (isa<ConstantSDNode>(N0)) 3013 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 3014 // fold (zext (zext x)) -> (zext x) 3015 // fold (zext (aext x)) -> (zext x) 3016 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 3017 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0)); 3018 3019 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 3020 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 3021 if (N0.getOpcode() == ISD::TRUNCATE) { 3022 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3023 if (NarrowLoad.getNode()) { 3024 if (NarrowLoad.getNode() != N0.getNode()) 3025 CombineTo(N0.getNode(), NarrowLoad); 3026 return DAG.getNode(ISD::ZERO_EXTEND, VT, NarrowLoad); 3027 } 3028 } 3029 3030 // fold (zext (truncate x)) -> (and x, mask) 3031 if (N0.getOpcode() == ISD::TRUNCATE && 3032 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) { 3033 SDValue Op = N0.getOperand(0); 3034 if (Op.getValueType().bitsLT(VT)) { 3035 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 3036 } else if (Op.getValueType().bitsGT(VT)) { 3037 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 3038 } 3039 return DAG.getZeroExtendInReg(Op, N0.getValueType()); 3040 } 3041 3042 // fold (zext (and (trunc x), cst)) -> (and x, cst). 3043 if (N0.getOpcode() == ISD::AND && 3044 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3045 N0.getOperand(1).getOpcode() == ISD::Constant) { 3046 SDValue X = N0.getOperand(0).getOperand(0); 3047 if (X.getValueType().bitsLT(VT)) { 3048 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 3049 } else if (X.getValueType().bitsGT(VT)) { 3050 X = DAG.getNode(ISD::TRUNCATE, VT, X); 3051 } 3052 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3053 Mask.zext(VT.getSizeInBits()); 3054 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 3055 } 3056 3057 // fold (zext (load x)) -> (zext (truncate (zextload x))) 3058 if (ISD::isNON_EXTLoad(N0.getNode()) && 3059 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3060 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 3061 bool DoXform = true; 3062 SmallVector<SDNode*, 4> SetCCs; 3063 if (!N0.hasOneUse()) 3064 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 3065 if (DoXform) { 3066 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3067 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 3068 LN0->getBasePtr(), LN0->getSrcValue(), 3069 LN0->getSrcValueOffset(), 3070 N0.getValueType(), 3071 LN0->isVolatile(), LN0->getAlignment()); 3072 CombineTo(N, ExtLoad); 3073 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad); 3074 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3075 // Extend SetCC uses if necessary. 3076 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3077 SDNode *SetCC = SetCCs[i]; 3078 SmallVector<SDValue, 4> Ops; 3079 for (unsigned j = 0; j != 2; ++j) { 3080 SDValue SOp = SetCC->getOperand(j); 3081 if (SOp == Trunc) 3082 Ops.push_back(ExtLoad); 3083 else 3084 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, VT, SOp)); 3085 } 3086 Ops.push_back(SetCC->getOperand(2)); 3087 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0), 3088 &Ops[0], Ops.size())); 3089 } 3090 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3091 } 3092 } 3093 3094 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 3095 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 3096 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3097 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3098 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3099 MVT EVT = LN0->getMemoryVT(); 3100 if ((!LegalOperations && !LN0->isVolatile()) || 3101 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT)) { 3102 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 3103 LN0->getBasePtr(), LN0->getSrcValue(), 3104 LN0->getSrcValueOffset(), EVT, 3105 LN0->isVolatile(), LN0->getAlignment()); 3106 CombineTo(N, ExtLoad); 3107 CombineTo(N0.getNode(), 3108 DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 3109 ExtLoad.getValue(1)); 3110 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3111 } 3112 } 3113 3114 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3115 if (N0.getOpcode() == ISD::SETCC) { 3116 SDValue SCC = 3117 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 3118 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3119 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3120 if (SCC.getNode()) return SCC; 3121 } 3122 3123 return SDValue(); 3124} 3125 3126SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 3127 SDValue N0 = N->getOperand(0); 3128 MVT VT = N->getValueType(0); 3129 3130 // fold (aext c1) -> c1 3131 if (isa<ConstantSDNode>(N0)) 3132 return DAG.getNode(ISD::ANY_EXTEND, VT, N0); 3133 // fold (aext (aext x)) -> (aext x) 3134 // fold (aext (zext x)) -> (zext x) 3135 // fold (aext (sext x)) -> (sext x) 3136 if (N0.getOpcode() == ISD::ANY_EXTEND || 3137 N0.getOpcode() == ISD::ZERO_EXTEND || 3138 N0.getOpcode() == ISD::SIGN_EXTEND) 3139 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 3140 3141 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 3142 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 3143 if (N0.getOpcode() == ISD::TRUNCATE) { 3144 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3145 if (NarrowLoad.getNode()) { 3146 if (NarrowLoad.getNode() != N0.getNode()) 3147 CombineTo(N0.getNode(), NarrowLoad); 3148 return DAG.getNode(ISD::ANY_EXTEND, VT, NarrowLoad); 3149 } 3150 } 3151 3152 // fold (aext (truncate x)) 3153 if (N0.getOpcode() == ISD::TRUNCATE) { 3154 SDValue TruncOp = N0.getOperand(0); 3155 if (TruncOp.getValueType() == VT) 3156 return TruncOp; // x iff x size == zext size. 3157 if (TruncOp.getValueType().bitsGT(VT)) 3158 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp); 3159 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp); 3160 } 3161 3162 // fold (aext (and (trunc x), cst)) -> (and x, cst). 3163 if (N0.getOpcode() == ISD::AND && 3164 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3165 N0.getOperand(1).getOpcode() == ISD::Constant) { 3166 SDValue X = N0.getOperand(0).getOperand(0); 3167 if (X.getValueType().bitsLT(VT)) { 3168 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 3169 } else if (X.getValueType().bitsGT(VT)) { 3170 X = DAG.getNode(ISD::TRUNCATE, VT, X); 3171 } 3172 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3173 Mask.zext(VT.getSizeInBits()); 3174 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 3175 } 3176 3177 // fold (aext (load x)) -> (aext (truncate (extload x))) 3178 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 3179 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3180 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 3181 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3182 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 3183 LN0->getBasePtr(), LN0->getSrcValue(), 3184 LN0->getSrcValueOffset(), 3185 N0.getValueType(), 3186 LN0->isVolatile(), LN0->getAlignment()); 3187 CombineTo(N, ExtLoad); 3188 // Redirect any chain users to the new load. 3189 DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), 3190 SDValue(ExtLoad.getNode(), 1)); 3191 // If any node needs the original loaded value, recompute it. 3192 if (!LN0->use_empty()) 3193 CombineTo(LN0, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 3194 ExtLoad.getValue(1)); 3195 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3196 } 3197 3198 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 3199 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 3200 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 3201 if (N0.getOpcode() == ISD::LOAD && 3202 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3203 N0.hasOneUse()) { 3204 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3205 MVT EVT = LN0->getMemoryVT(); 3206 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT, 3207 LN0->getChain(), LN0->getBasePtr(), 3208 LN0->getSrcValue(), 3209 LN0->getSrcValueOffset(), EVT, 3210 LN0->isVolatile(), LN0->getAlignment()); 3211 CombineTo(N, ExtLoad); 3212 CombineTo(N0.getNode(), 3213 DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 3214 ExtLoad.getValue(1)); 3215 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3216 } 3217 3218 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3219 if (N0.getOpcode() == ISD::SETCC) { 3220 SDValue SCC = 3221 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 3222 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3223 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3224 if (SCC.getNode()) 3225 return SCC; 3226 } 3227 3228 return SDValue(); 3229} 3230 3231/// GetDemandedBits - See if the specified operand can be simplified with the 3232/// knowledge that only the bits specified by Mask are used. If so, return the 3233/// simpler operand, otherwise return a null SDValue. 3234SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 3235 switch (V.getOpcode()) { 3236 default: break; 3237 case ISD::OR: 3238 case ISD::XOR: 3239 // If the LHS or RHS don't contribute bits to the or, drop them. 3240 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 3241 return V.getOperand(1); 3242 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 3243 return V.getOperand(0); 3244 break; 3245 case ISD::SRL: 3246 // Only look at single-use SRLs. 3247 if (!V.getNode()->hasOneUse()) 3248 break; 3249 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 3250 // See if we can recursively simplify the LHS. 3251 unsigned Amt = RHSC->getZExtValue(); 3252 APInt NewMask = Mask << Amt; 3253 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 3254 if (SimplifyLHS.getNode()) { 3255 return DAG.getNode(ISD::SRL, V.getValueType(), 3256 SimplifyLHS, V.getOperand(1)); 3257 } 3258 } 3259 } 3260 return SDValue(); 3261} 3262 3263/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 3264/// bits and then truncated to a narrower type and where N is a multiple 3265/// of number of bits of the narrower type, transform it to a narrower load 3266/// from address + N / num of bits of new type. If the result is to be 3267/// extended, also fold the extension to form a extending load. 3268SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 3269 unsigned Opc = N->getOpcode(); 3270 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 3271 SDValue N0 = N->getOperand(0); 3272 MVT VT = N->getValueType(0); 3273 MVT EVT = N->getValueType(0); 3274 3275 // This transformation isn't valid for vector loads. 3276 if (VT.isVector()) 3277 return SDValue(); 3278 3279 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then 3280 // extended to VT. 3281 if (Opc == ISD::SIGN_EXTEND_INREG) { 3282 ExtType = ISD::SEXTLOAD; 3283 EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3284 if (LegalOperations && !TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT)) 3285 return SDValue(); 3286 } 3287 3288 unsigned EVTBits = EVT.getSizeInBits(); 3289 unsigned ShAmt = 0; 3290 bool CombineSRL = false; 3291 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 3292 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3293 ShAmt = N01->getZExtValue(); 3294 // Is the shift amount a multiple of size of VT? 3295 if ((ShAmt & (EVTBits-1)) == 0) { 3296 N0 = N0.getOperand(0); 3297 if (N0.getValueType().getSizeInBits() <= EVTBits) 3298 return SDValue(); 3299 CombineSRL = true; 3300 } 3301 } 3302 } 3303 3304 // Do not generate loads of non-round integer types since these can 3305 // be expensive (and would be wrong if the type is not byte sized). 3306 if (isa<LoadSDNode>(N0) && N0.hasOneUse() && VT.isRound() && 3307 cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() > EVTBits && 3308 // Do not change the width of a volatile load. 3309 !cast<LoadSDNode>(N0)->isVolatile()) { 3310 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3311 MVT PtrType = N0.getOperand(1).getValueType(); 3312 // For big endian targets, we need to adjust the offset to the pointer to 3313 // load the correct bytes. 3314 if (TLI.isBigEndian()) { 3315 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 3316 unsigned EVTStoreBits = EVT.getStoreSizeInBits(); 3317 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 3318 } 3319 uint64_t PtrOff = ShAmt / 8; 3320 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 3321 SDValue NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(), 3322 DAG.getConstant(PtrOff, PtrType)); 3323 AddToWorkList(NewPtr.getNode()); 3324 SDValue Load = (ExtType == ISD::NON_EXTLOAD) 3325 ? DAG.getLoad(VT, LN0->getChain(), NewPtr, 3326 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3327 LN0->isVolatile(), NewAlign) 3328 : DAG.getExtLoad(ExtType, VT, LN0->getChain(), NewPtr, 3329 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3330 EVT, LN0->isVolatile(), NewAlign); 3331 AddToWorkList(N); 3332 if (CombineSRL) { 3333 WorkListRemover DeadNodes(*this); 3334 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), 3335 &DeadNodes); 3336 CombineTo(N->getOperand(0).getNode(), Load); 3337 } else 3338 CombineTo(N0.getNode(), Load, Load.getValue(1)); 3339 if (ShAmt) { 3340 if (Opc == ISD::SIGN_EXTEND_INREG) 3341 return DAG.getNode(Opc, VT, Load, N->getOperand(1)); 3342 else 3343 return DAG.getNode(Opc, VT, Load); 3344 } 3345 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3346 } 3347 3348 return SDValue(); 3349} 3350 3351 3352SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 3353 SDValue N0 = N->getOperand(0); 3354 SDValue N1 = N->getOperand(1); 3355 MVT VT = N->getValueType(0); 3356 MVT EVT = cast<VTSDNode>(N1)->getVT(); 3357 unsigned VTBits = VT.getSizeInBits(); 3358 unsigned EVTBits = EVT.getSizeInBits(); 3359 3360 // fold (sext_in_reg c1) -> c1 3361 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 3362 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1); 3363 3364 // If the input is already sign extended, just drop the extension. 3365 if (DAG.ComputeNumSignBits(N0) >= VT.getSizeInBits()-EVTBits+1) 3366 return N0; 3367 3368 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 3369 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 3370 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 3371 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); 3372 } 3373 3374 // fold (sext_in_reg (sext x)) -> (sext x) 3375 // fold (sext_in_reg (aext x)) -> (sext x) 3376 // if x is small enough. 3377 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 3378 SDValue N00 = N0.getOperand(0); 3379 if (N00.getValueType().getSizeInBits() < EVTBits) 3380 return DAG.getNode(ISD::SIGN_EXTEND, VT, N00, N1); 3381 } 3382 3383 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 3384 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 3385 return DAG.getZeroExtendInReg(N0, EVT); 3386 3387 // fold operands of sext_in_reg based on knowledge that the top bits are not 3388 // demanded. 3389 if (SimplifyDemandedBits(SDValue(N, 0))) 3390 return SDValue(N, 0); 3391 3392 // fold (sext_in_reg (load x)) -> (smaller sextload x) 3393 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 3394 SDValue NarrowLoad = ReduceLoadWidth(N); 3395 if (NarrowLoad.getNode()) 3396 return NarrowLoad; 3397 3398 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24 3399 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible. 3400 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 3401 if (N0.getOpcode() == ISD::SRL) { 3402 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 3403 if (ShAmt->getZExtValue()+EVTBits <= VT.getSizeInBits()) { 3404 // We can turn this into an SRA iff the input to the SRL is already sign 3405 // extended enough. 3406 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 3407 if (VT.getSizeInBits()-(ShAmt->getZExtValue()+EVTBits) < InSignBits) 3408 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1)); 3409 } 3410 } 3411 3412 // fold (sext_inreg (extload x)) -> (sextload x) 3413 if (ISD::isEXTLoad(N0.getNode()) && 3414 ISD::isUNINDEXEDLoad(N0.getNode()) && 3415 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3416 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3417 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 3418 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3419 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 3420 LN0->getBasePtr(), LN0->getSrcValue(), 3421 LN0->getSrcValueOffset(), EVT, 3422 LN0->isVolatile(), LN0->getAlignment()); 3423 CombineTo(N, ExtLoad); 3424 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 3425 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3426 } 3427 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 3428 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3429 N0.hasOneUse() && 3430 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3431 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3432 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 3433 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3434 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 3435 LN0->getBasePtr(), LN0->getSrcValue(), 3436 LN0->getSrcValueOffset(), EVT, 3437 LN0->isVolatile(), LN0->getAlignment()); 3438 CombineTo(N, ExtLoad); 3439 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 3440 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3441 } 3442 return SDValue(); 3443} 3444 3445SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 3446 SDValue N0 = N->getOperand(0); 3447 MVT VT = N->getValueType(0); 3448 3449 // noop truncate 3450 if (N0.getValueType() == N->getValueType(0)) 3451 return N0; 3452 // fold (truncate c1) -> c1 3453 if (isa<ConstantSDNode>(N0)) 3454 return DAG.getNode(ISD::TRUNCATE, VT, N0); 3455 // fold (truncate (truncate x)) -> (truncate x) 3456 if (N0.getOpcode() == ISD::TRUNCATE) 3457 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 3458 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 3459 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| 3460 N0.getOpcode() == ISD::ANY_EXTEND) { 3461 if (N0.getOperand(0).getValueType().bitsLT(VT)) 3462 // if the source is smaller than the dest, we still need an extend 3463 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 3464 else if (N0.getOperand(0).getValueType().bitsGT(VT)) 3465 // if the source is larger than the dest, than we just need the truncate 3466 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 3467 else 3468 // if the source and dest are the same type, we can drop both the extend 3469 // and the truncate 3470 return N0.getOperand(0); 3471 } 3472 3473 // See if we can simplify the input to this truncate through knowledge that 3474 // only the low bits are being used. For example "trunc (or (shl x, 8), y)" 3475 // -> trunc y 3476 SDValue Shorter = 3477 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 3478 VT.getSizeInBits())); 3479 if (Shorter.getNode()) 3480 return DAG.getNode(ISD::TRUNCATE, VT, Shorter); 3481 3482 // fold (truncate (load x)) -> (smaller load x) 3483 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 3484 return ReduceLoadWidth(N); 3485} 3486 3487static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 3488 SDValue Elt = N->getOperand(i); 3489 if (Elt.getOpcode() != ISD::MERGE_VALUES) 3490 return Elt.getNode(); 3491 return Elt.getOperand(Elt.getResNo()).getNode(); 3492} 3493 3494/// CombineConsecutiveLoads - build_pair (load, load) -> load 3495/// if load locations are consecutive. 3496SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, MVT VT) { 3497 assert(N->getOpcode() == ISD::BUILD_PAIR); 3498 3499 SDNode *LD1 = getBuildPairElt(N, 0); 3500 if (!ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse()) 3501 return SDValue(); 3502 MVT LD1VT = LD1->getValueType(0); 3503 SDNode *LD2 = getBuildPairElt(N, 1); 3504 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 3505 if (ISD::isNON_EXTLoad(LD2) && 3506 LD2->hasOneUse() && 3507 // If both are volatile this would reduce the number of volatile loads. 3508 // If one is volatile it might be ok, but play conservative and bail out. 3509 !cast<LoadSDNode>(LD1)->isVolatile() && 3510 !cast<LoadSDNode>(LD2)->isVolatile() && 3511 TLI.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1, MFI)) { 3512 LoadSDNode *LD = cast<LoadSDNode>(LD1); 3513 unsigned Align = LD->getAlignment(); 3514 unsigned NewAlign = TLI.getTargetData()-> 3515 getABITypeAlignment(VT.getTypeForMVT()); 3516 if (NewAlign <= Align && 3517 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) 3518 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), 3519 LD->getSrcValue(), LD->getSrcValueOffset(), 3520 false, Align); 3521 } 3522 return SDValue(); 3523} 3524 3525SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) { 3526 SDValue N0 = N->getOperand(0); 3527 MVT VT = N->getValueType(0); 3528 3529 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 3530 // Only do this before legalize, since afterward the target may be depending 3531 // on the bitconvert. 3532 // First check to see if this is all constant. 3533 if (!LegalTypes && 3534 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 3535 VT.isVector()) { 3536 bool isSimple = true; 3537 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 3538 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 3539 N0.getOperand(i).getOpcode() != ISD::Constant && 3540 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 3541 isSimple = false; 3542 break; 3543 } 3544 3545 MVT DestEltVT = N->getValueType(0).getVectorElementType(); 3546 assert(!DestEltVT.isVector() && 3547 "Element type of vector ValueType must not be vector!"); 3548 if (isSimple) { 3549 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.getNode(), DestEltVT); 3550 } 3551 } 3552 3553 // If the input is a constant, let getNode fold it. 3554 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 3555 SDValue Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0); 3556 if (Res.getNode() != N) return Res; 3557 } 3558 3559 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2) 3560 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3561 3562 // fold (conv (load x)) -> (load (conv*)x) 3563 // If the resultant load doesn't need a higher alignment than the original! 3564 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 3565 // Do not change the width of a volatile load. 3566 !cast<LoadSDNode>(N0)->isVolatile() && 3567 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) { 3568 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3569 unsigned Align = TLI.getTargetData()-> 3570 getABITypeAlignment(VT.getTypeForMVT()); 3571 unsigned OrigAlign = LN0->getAlignment(); 3572 if (Align <= OrigAlign) { 3573 SDValue Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(), 3574 LN0->getSrcValue(), LN0->getSrcValueOffset(), 3575 LN0->isVolatile(), OrigAlign); 3576 AddToWorkList(N); 3577 CombineTo(N0.getNode(), 3578 DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load), 3579 Load.getValue(1)); 3580 return Load; 3581 } 3582 } 3583 3584 // Fold bitconvert(fneg(x)) -> xor(bitconvert(x), signbit) 3585 // Fold bitconvert(fabs(x)) -> and(bitconvert(x), ~signbit) 3586 // This often reduces constant pool loads. 3587 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && 3588 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) { 3589 SDValue NewConv = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3590 AddToWorkList(NewConv.getNode()); 3591 3592 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3593 if (N0.getOpcode() == ISD::FNEG) 3594 return DAG.getNode(ISD::XOR, VT, NewConv, DAG.getConstant(SignBit, VT)); 3595 assert(N0.getOpcode() == ISD::FABS); 3596 return DAG.getNode(ISD::AND, VT, NewConv, DAG.getConstant(~SignBit, VT)); 3597 } 3598 3599 // Fold bitconvert(fcopysign(cst, x)) -> bitconvert(x)&sign | cst&~sign' 3600 // Note that we don't handle copysign(x,cst) because this can always be folded 3601 // to an fneg or fabs. 3602 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 3603 isa<ConstantFPSDNode>(N0.getOperand(0)) && 3604 VT.isInteger() && !VT.isVector()) { 3605 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 3606 MVT IntXVT = MVT::getIntegerVT(OrigXWidth); 3607 if (TLI.isTypeLegal(IntXVT) || !LegalTypes) { 3608 SDValue X = DAG.getNode(ISD::BIT_CONVERT, IntXVT, N0.getOperand(1)); 3609 AddToWorkList(X.getNode()); 3610 3611 // If X has a different width than the result/lhs, sext it or truncate it. 3612 unsigned VTWidth = VT.getSizeInBits(); 3613 if (OrigXWidth < VTWidth) { 3614 X = DAG.getNode(ISD::SIGN_EXTEND, VT, X); 3615 AddToWorkList(X.getNode()); 3616 } else if (OrigXWidth > VTWidth) { 3617 // To get the sign bit in the right place, we have to shift it right 3618 // before truncating. 3619 X = DAG.getNode(ISD::SRL, X.getValueType(), X, 3620 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 3621 AddToWorkList(X.getNode()); 3622 X = DAG.getNode(ISD::TRUNCATE, VT, X); 3623 AddToWorkList(X.getNode()); 3624 } 3625 3626 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3627 X = DAG.getNode(ISD::AND, VT, X, DAG.getConstant(SignBit, VT)); 3628 AddToWorkList(X.getNode()); 3629 3630 SDValue Cst = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3631 Cst = DAG.getNode(ISD::AND, VT, Cst, DAG.getConstant(~SignBit, VT)); 3632 AddToWorkList(Cst.getNode()); 3633 3634 return DAG.getNode(ISD::OR, VT, X, Cst); 3635 } 3636 } 3637 3638 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 3639 if (N0.getOpcode() == ISD::BUILD_PAIR) { 3640 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT); 3641 if (CombineLD.getNode()) 3642 return CombineLD; 3643 } 3644 3645 return SDValue(); 3646} 3647 3648SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 3649 MVT VT = N->getValueType(0); 3650 return CombineConsecutiveLoads(N, VT); 3651} 3652 3653/// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector 3654/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 3655/// destination element value type. 3656SDValue DAGCombiner:: 3657ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT DstEltVT) { 3658 MVT SrcEltVT = BV->getOperand(0).getValueType(); 3659 3660 // If this is already the right type, we're done. 3661 if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 3662 3663 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 3664 unsigned DstBitSize = DstEltVT.getSizeInBits(); 3665 3666 // If this is a conversion of N elements of one type to N elements of another 3667 // type, convert each element. This handles FP<->INT cases. 3668 if (SrcBitSize == DstBitSize) { 3669 SmallVector<SDValue, 8> Ops; 3670 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3671 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i))); 3672 AddToWorkList(Ops.back().getNode()); 3673 } 3674 MVT VT = MVT::getVectorVT(DstEltVT, 3675 BV->getValueType(0).getVectorNumElements()); 3676 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3677 } 3678 3679 // Otherwise, we're growing or shrinking the elements. To avoid having to 3680 // handle annoying details of growing/shrinking FP values, we convert them to 3681 // int first. 3682 if (SrcEltVT.isFloatingPoint()) { 3683 // Convert the input float vector to a int vector where the elements are the 3684 // same sizes. 3685 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 3686 MVT IntVT = MVT::getIntegerVT(SrcEltVT.getSizeInBits()); 3687 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode(); 3688 SrcEltVT = IntVT; 3689 } 3690 3691 // Now we know the input is an integer vector. If the output is a FP type, 3692 // convert to integer first, then to FP of the right size. 3693 if (DstEltVT.isFloatingPoint()) { 3694 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 3695 MVT TmpVT = MVT::getIntegerVT(DstEltVT.getSizeInBits()); 3696 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).getNode(); 3697 3698 // Next, convert to FP elements of the same size. 3699 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT); 3700 } 3701 3702 // Okay, we know the src/dst types are both integers of differing types. 3703 // Handling growing first. 3704 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 3705 if (SrcBitSize < DstBitSize) { 3706 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 3707 3708 SmallVector<SDValue, 8> Ops; 3709 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 3710 i += NumInputsPerOutput) { 3711 bool isLE = TLI.isLittleEndian(); 3712 APInt NewBits = APInt(DstBitSize, 0); 3713 bool EltIsUndef = true; 3714 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 3715 // Shift the previously computed bits over. 3716 NewBits <<= SrcBitSize; 3717 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 3718 if (Op.getOpcode() == ISD::UNDEF) continue; 3719 EltIsUndef = false; 3720 3721 NewBits |= 3722 APInt(cast<ConstantSDNode>(Op)->getAPIntValue()).zext(DstBitSize); 3723 } 3724 3725 if (EltIsUndef) 3726 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 3727 else 3728 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 3729 } 3730 3731 MVT VT = MVT::getVectorVT(DstEltVT, Ops.size()); 3732 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3733 } 3734 3735 // Finally, this must be the case where we are shrinking elements: each input 3736 // turns into multiple outputs. 3737 bool isS2V = ISD::isScalarToVector(BV); 3738 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 3739 MVT VT = MVT::getVectorVT(DstEltVT, NumOutputsPerInput*BV->getNumOperands()); 3740 SmallVector<SDValue, 8> Ops; 3741 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3742 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 3743 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 3744 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 3745 continue; 3746 } 3747 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getAPIntValue(); 3748 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 3749 APInt ThisVal = APInt(OpVal).trunc(DstBitSize); 3750 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 3751 if (isS2V && i == 0 && j == 0 && APInt(ThisVal).zext(SrcBitSize) == OpVal) 3752 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 3753 return DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Ops[0]); 3754 OpVal = OpVal.lshr(DstBitSize); 3755 } 3756 3757 // For big endian targets, swap the order of the pieces of each element. 3758 if (TLI.isBigEndian()) 3759 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 3760 } 3761 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3762} 3763 3764 3765 3766SDValue DAGCombiner::visitFADD(SDNode *N) { 3767 SDValue N0 = N->getOperand(0); 3768 SDValue N1 = N->getOperand(1); 3769 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3770 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3771 MVT VT = N->getValueType(0); 3772 3773 // fold vector ops 3774 if (VT.isVector()) { 3775 SDValue FoldedVOp = SimplifyVBinOp(N); 3776 if (FoldedVOp.getNode()) return FoldedVOp; 3777 } 3778 3779 // fold (fadd c1, c2) -> c1+c2 3780 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3781 return DAG.getNode(ISD::FADD, VT, N0, N1); 3782 // canonicalize constant to RHS 3783 if (N0CFP && !N1CFP) 3784 return DAG.getNode(ISD::FADD, VT, N1, N0); 3785 // fold (A + (-B)) -> A-B 3786 if (isNegatibleForFree(N1, LegalOperations) == 2) 3787 return DAG.getNode(ISD::FSUB, VT, N0, 3788 GetNegatedExpression(N1, DAG, LegalOperations)); 3789 // fold ((-A) + B) -> B-A 3790 if (isNegatibleForFree(N0, LegalOperations) == 2) 3791 return DAG.getNode(ISD::FSUB, VT, N1, 3792 GetNegatedExpression(N0, DAG, LegalOperations)); 3793 3794 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 3795 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 3796 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3797 return DAG.getNode(ISD::FADD, VT, N0.getOperand(0), 3798 DAG.getNode(ISD::FADD, VT, N0.getOperand(1), N1)); 3799 3800 return SDValue(); 3801} 3802 3803SDValue DAGCombiner::visitFSUB(SDNode *N) { 3804 SDValue N0 = N->getOperand(0); 3805 SDValue N1 = N->getOperand(1); 3806 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3807 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3808 MVT VT = N->getValueType(0); 3809 3810 // fold vector ops 3811 if (VT.isVector()) { 3812 SDValue FoldedVOp = SimplifyVBinOp(N); 3813 if (FoldedVOp.getNode()) return FoldedVOp; 3814 } 3815 3816 // fold (fsub c1, c2) -> c1-c2 3817 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3818 return DAG.getNode(ISD::FSUB, VT, N0, N1); 3819 // fold (0-B) -> -B 3820 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { 3821 if (isNegatibleForFree(N1, LegalOperations)) 3822 return GetNegatedExpression(N1, DAG, LegalOperations); 3823 return DAG.getNode(ISD::FNEG, VT, N1); 3824 } 3825 // fold (A-(-B)) -> A+B 3826 if (isNegatibleForFree(N1, LegalOperations)) 3827 return DAG.getNode(ISD::FADD, VT, N0, 3828 GetNegatedExpression(N1, DAG, LegalOperations)); 3829 3830 return SDValue(); 3831} 3832 3833SDValue DAGCombiner::visitFMUL(SDNode *N) { 3834 SDValue N0 = N->getOperand(0); 3835 SDValue N1 = N->getOperand(1); 3836 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3837 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3838 MVT VT = N->getValueType(0); 3839 3840 // fold vector ops 3841 if (VT.isVector()) { 3842 SDValue FoldedVOp = SimplifyVBinOp(N); 3843 if (FoldedVOp.getNode()) return FoldedVOp; 3844 } 3845 3846 // fold (fmul c1, c2) -> c1*c2 3847 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3848 return DAG.getNode(ISD::FMUL, VT, N0, N1); 3849 // canonicalize constant to RHS 3850 if (N0CFP && !N1CFP) 3851 return DAG.getNode(ISD::FMUL, VT, N1, N0); 3852 // fold (fmul X, 2.0) -> (fadd X, X) 3853 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 3854 return DAG.getNode(ISD::FADD, VT, N0, N0); 3855 // fold (fmul X, -1.0) -> (fneg X) 3856 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 3857 return DAG.getNode(ISD::FNEG, VT, N0); 3858 3859 // -X * -Y -> X*Y 3860 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 3861 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 3862 // Both can be negated for free, check to see if at least one is cheaper 3863 // negated. 3864 if (LHSNeg == 2 || RHSNeg == 2) 3865 return DAG.getNode(ISD::FMUL, VT, 3866 GetNegatedExpression(N0, DAG, LegalOperations), 3867 GetNegatedExpression(N1, DAG, LegalOperations)); 3868 } 3869 } 3870 3871 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 3872 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 3873 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3874 return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0), 3875 DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1)); 3876 3877 return SDValue(); 3878} 3879 3880SDValue DAGCombiner::visitFDIV(SDNode *N) { 3881 SDValue N0 = N->getOperand(0); 3882 SDValue N1 = N->getOperand(1); 3883 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3884 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3885 MVT VT = N->getValueType(0); 3886 3887 // fold vector ops 3888 if (VT.isVector()) { 3889 SDValue FoldedVOp = SimplifyVBinOp(N); 3890 if (FoldedVOp.getNode()) return FoldedVOp; 3891 } 3892 3893 // fold (fdiv c1, c2) -> c1/c2 3894 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3895 return DAG.getNode(ISD::FDIV, VT, N0, N1); 3896 3897 3898 // -X / -Y -> X*Y 3899 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 3900 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 3901 // Both can be negated for free, check to see if at least one is cheaper 3902 // negated. 3903 if (LHSNeg == 2 || RHSNeg == 2) 3904 return DAG.getNode(ISD::FDIV, VT, 3905 GetNegatedExpression(N0, DAG, LegalOperations), 3906 GetNegatedExpression(N1, DAG, LegalOperations)); 3907 } 3908 } 3909 3910 return SDValue(); 3911} 3912 3913SDValue DAGCombiner::visitFREM(SDNode *N) { 3914 SDValue N0 = N->getOperand(0); 3915 SDValue N1 = N->getOperand(1); 3916 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3917 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3918 MVT VT = N->getValueType(0); 3919 3920 // fold (frem c1, c2) -> fmod(c1,c2) 3921 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3922 return DAG.getNode(ISD::FREM, VT, N0, N1); 3923 3924 return SDValue(); 3925} 3926 3927SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 3928 SDValue N0 = N->getOperand(0); 3929 SDValue N1 = N->getOperand(1); 3930 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3931 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3932 MVT VT = N->getValueType(0); 3933 3934 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 3935 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1); 3936 3937 if (N1CFP) { 3938 const APFloat& V = N1CFP->getValueAPF(); 3939 // copysign(x, c1) -> fabs(x) iff ispos(c1) 3940 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 3941 if (!V.isNegative()) 3942 return DAG.getNode(ISD::FABS, VT, N0); 3943 else 3944 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0)); 3945 } 3946 3947 // copysign(fabs(x), y) -> copysign(x, y) 3948 // copysign(fneg(x), y) -> copysign(x, y) 3949 // copysign(copysign(x,z), y) -> copysign(x, y) 3950 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 3951 N0.getOpcode() == ISD::FCOPYSIGN) 3952 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1); 3953 3954 // copysign(x, abs(y)) -> abs(x) 3955 if (N1.getOpcode() == ISD::FABS) 3956 return DAG.getNode(ISD::FABS, VT, N0); 3957 3958 // copysign(x, copysign(y,z)) -> copysign(x, z) 3959 if (N1.getOpcode() == ISD::FCOPYSIGN) 3960 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1)); 3961 3962 // copysign(x, fp_extend(y)) -> copysign(x, y) 3963 // copysign(x, fp_round(y)) -> copysign(x, y) 3964 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 3965 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0)); 3966 3967 return SDValue(); 3968} 3969 3970 3971 3972SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 3973 SDValue N0 = N->getOperand(0); 3974 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3975 MVT VT = N->getValueType(0); 3976 MVT OpVT = N0.getValueType(); 3977 3978 // fold (sint_to_fp c1) -> c1fp 3979 if (N0C && OpVT != MVT::ppcf128) 3980 return DAG.getNode(ISD::SINT_TO_FP, VT, N0); 3981 3982 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 3983 // but UINT_TO_FP is legal on this target, try to convert. 3984 if (!TLI.isOperationLegal(ISD::SINT_TO_FP, OpVT) && 3985 TLI.isOperationLegal(ISD::UINT_TO_FP, OpVT)) { 3986 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 3987 if (DAG.SignBitIsZero(N0)) 3988 return DAG.getNode(ISD::UINT_TO_FP, VT, N0); 3989 } 3990 3991 3992 return SDValue(); 3993} 3994 3995SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 3996 SDValue N0 = N->getOperand(0); 3997 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3998 MVT VT = N->getValueType(0); 3999 MVT OpVT = N0.getValueType(); 4000 4001 // fold (uint_to_fp c1) -> c1fp 4002 if (N0C && OpVT != MVT::ppcf128) 4003 return DAG.getNode(ISD::UINT_TO_FP, VT, N0); 4004 4005 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 4006 // but SINT_TO_FP is legal on this target, try to convert. 4007 if (!TLI.isOperationLegal(ISD::UINT_TO_FP, OpVT) && 4008 TLI.isOperationLegal(ISD::SINT_TO_FP, OpVT)) { 4009 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 4010 if (DAG.SignBitIsZero(N0)) 4011 return DAG.getNode(ISD::SINT_TO_FP, VT, N0); 4012 } 4013 4014 return SDValue(); 4015} 4016 4017SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 4018 SDValue N0 = N->getOperand(0); 4019 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4020 MVT VT = N->getValueType(0); 4021 4022 // fold (fp_to_sint c1fp) -> c1 4023 if (N0CFP) 4024 return DAG.getNode(ISD::FP_TO_SINT, VT, N0); 4025 return SDValue(); 4026} 4027 4028SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 4029 SDValue N0 = N->getOperand(0); 4030 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4031 MVT VT = N->getValueType(0); 4032 4033 // fold (fp_to_uint c1fp) -> c1 4034 if (N0CFP && VT != MVT::ppcf128) 4035 return DAG.getNode(ISD::FP_TO_UINT, VT, N0); 4036 return SDValue(); 4037} 4038 4039SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 4040 SDValue N0 = N->getOperand(0); 4041 SDValue N1 = N->getOperand(1); 4042 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4043 MVT VT = N->getValueType(0); 4044 4045 // fold (fp_round c1fp) -> c1fp 4046 if (N0CFP && N0.getValueType() != MVT::ppcf128) 4047 return DAG.getNode(ISD::FP_ROUND, VT, N0, N1); 4048 4049 // fold (fp_round (fp_extend x)) -> x 4050 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 4051 return N0.getOperand(0); 4052 4053 // fold (fp_round (fp_round x)) -> (fp_round x) 4054 if (N0.getOpcode() == ISD::FP_ROUND) { 4055 // This is a value preserving truncation if both round's are. 4056 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 4057 N0.getNode()->getConstantOperandVal(1) == 1; 4058 return DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0), 4059 DAG.getIntPtrConstant(IsTrunc)); 4060 } 4061 4062 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 4063 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { 4064 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0), N1); 4065 AddToWorkList(Tmp.getNode()); 4066 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1)); 4067 } 4068 4069 return SDValue(); 4070} 4071 4072SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 4073 SDValue N0 = N->getOperand(0); 4074 MVT VT = N->getValueType(0); 4075 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 4076 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4077 4078 // fold (fp_round_inreg c1fp) -> c1fp 4079 if (N0CFP && (TLI.isTypeLegal(EVT) || !LegalTypes)) { 4080 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT); 4081 return DAG.getNode(ISD::FP_EXTEND, VT, Round); 4082 } 4083 return SDValue(); 4084} 4085 4086SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 4087 SDValue N0 = N->getOperand(0); 4088 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4089 MVT VT = N->getValueType(0); 4090 4091 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 4092 if (N->hasOneUse() && 4093 N->use_begin().getUse().getSDValue().getOpcode() == ISD::FP_ROUND) 4094 return SDValue(); 4095 4096 // fold (fp_extend c1fp) -> c1fp 4097 if (N0CFP && VT != MVT::ppcf128) 4098 return DAG.getNode(ISD::FP_EXTEND, VT, N0); 4099 4100 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 4101 // value of X. 4102 if (N0.getOpcode() == ISD::FP_ROUND 4103 && N0.getNode()->getConstantOperandVal(1) == 1) { 4104 SDValue In = N0.getOperand(0); 4105 if (In.getValueType() == VT) return In; 4106 if (VT.bitsLT(In.getValueType())) 4107 return DAG.getNode(ISD::FP_ROUND, VT, In, N0.getOperand(1)); 4108 return DAG.getNode(ISD::FP_EXTEND, VT, In); 4109 } 4110 4111 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 4112 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 4113 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4114 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 4115 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4116 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 4117 LN0->getBasePtr(), LN0->getSrcValue(), 4118 LN0->getSrcValueOffset(), 4119 N0.getValueType(), 4120 LN0->isVolatile(), LN0->getAlignment()); 4121 CombineTo(N, ExtLoad); 4122 CombineTo(N0.getNode(), DAG.getNode(ISD::FP_ROUND, N0.getValueType(), 4123 ExtLoad, DAG.getIntPtrConstant(1)), 4124 ExtLoad.getValue(1)); 4125 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4126 } 4127 4128 return SDValue(); 4129} 4130 4131SDValue DAGCombiner::visitFNEG(SDNode *N) { 4132 SDValue N0 = N->getOperand(0); 4133 4134 if (isNegatibleForFree(N0, LegalOperations)) 4135 return GetNegatedExpression(N0, DAG, LegalOperations); 4136 4137 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 4138 // constant pool values. 4139 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() && 4140 N0.getOperand(0).getValueType().isInteger() && 4141 !N0.getOperand(0).getValueType().isVector()) { 4142 SDValue Int = N0.getOperand(0); 4143 MVT IntVT = Int.getValueType(); 4144 if (IntVT.isInteger() && !IntVT.isVector()) { 4145 Int = DAG.getNode(ISD::XOR, IntVT, Int, 4146 DAG.getConstant(IntVT.getIntegerVTSignBit(), IntVT)); 4147 AddToWorkList(Int.getNode()); 4148 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int); 4149 } 4150 } 4151 4152 return SDValue(); 4153} 4154 4155SDValue DAGCombiner::visitFABS(SDNode *N) { 4156 SDValue N0 = N->getOperand(0); 4157 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4158 MVT VT = N->getValueType(0); 4159 4160 // fold (fabs c1) -> fabs(c1) 4161 if (N0CFP && VT != MVT::ppcf128) 4162 return DAG.getNode(ISD::FABS, VT, N0); 4163 // fold (fabs (fabs x)) -> (fabs x) 4164 if (N0.getOpcode() == ISD::FABS) 4165 return N->getOperand(0); 4166 // fold (fabs (fneg x)) -> (fabs x) 4167 // fold (fabs (fcopysign x, y)) -> (fabs x) 4168 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 4169 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0)); 4170 4171 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 4172 // constant pool values. 4173 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() && 4174 N0.getOperand(0).getValueType().isInteger() && 4175 !N0.getOperand(0).getValueType().isVector()) { 4176 SDValue Int = N0.getOperand(0); 4177 MVT IntVT = Int.getValueType(); 4178 if (IntVT.isInteger() && !IntVT.isVector()) { 4179 Int = DAG.getNode(ISD::AND, IntVT, Int, 4180 DAG.getConstant(~IntVT.getIntegerVTSignBit(), IntVT)); 4181 AddToWorkList(Int.getNode()); 4182 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int); 4183 } 4184 } 4185 4186 return SDValue(); 4187} 4188 4189SDValue DAGCombiner::visitBRCOND(SDNode *N) { 4190 SDValue Chain = N->getOperand(0); 4191 SDValue N1 = N->getOperand(1); 4192 SDValue N2 = N->getOperand(2); 4193 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 4194 4195 // never taken branch, fold to chain 4196 if (N1C && N1C->isNullValue()) 4197 return Chain; 4198 // unconditional branch 4199 if (N1C && N1C->getAPIntValue() == 1) 4200 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 4201 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 4202 // on the target. 4203 if (N1.getOpcode() == ISD::SETCC && 4204 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) { 4205 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2), 4206 N1.getOperand(0), N1.getOperand(1), N2); 4207 } 4208 return SDValue(); 4209} 4210 4211// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 4212// 4213SDValue DAGCombiner::visitBR_CC(SDNode *N) { 4214 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 4215 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 4216 4217 // Use SimplifySetCC to simplify SETCC's. 4218 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS), 4219 CondLHS, CondRHS, CC->get(), false); 4220 if (Simp.getNode()) AddToWorkList(Simp.getNode()); 4221 4222 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.getNode()); 4223 4224 // fold br_cc true, dest -> br dest (unconditional branch) 4225 if (SCCC && !SCCC->isNullValue()) 4226 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0), 4227 N->getOperand(4)); 4228 // fold br_cc false, dest -> unconditional fall through 4229 if (SCCC && SCCC->isNullValue()) 4230 return N->getOperand(0); 4231 4232 // fold to a simpler setcc 4233 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) 4234 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0), 4235 Simp.getOperand(2), Simp.getOperand(0), 4236 Simp.getOperand(1), N->getOperand(4)); 4237 return SDValue(); 4238} 4239 4240 4241/// CombineToPreIndexedLoadStore - Try turning a load / store into a 4242/// pre-indexed load / store when the base pointer is an add or subtract 4243/// and it has other uses besides the load / store. After the 4244/// transformation, the new indexed load / store has effectively folded 4245/// the add / subtract in and all of its other uses are redirected to the 4246/// new load / store. 4247bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 4248 if (!LegalOperations) 4249 return false; 4250 4251 bool isLoad = true; 4252 SDValue Ptr; 4253 MVT VT; 4254 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4255 if (LD->isIndexed()) 4256 return false; 4257 VT = LD->getMemoryVT(); 4258 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 4259 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 4260 return false; 4261 Ptr = LD->getBasePtr(); 4262 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4263 if (ST->isIndexed()) 4264 return false; 4265 VT = ST->getMemoryVT(); 4266 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 4267 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 4268 return false; 4269 Ptr = ST->getBasePtr(); 4270 isLoad = false; 4271 } else 4272 return false; 4273 4274 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 4275 // out. There is no reason to make this a preinc/predec. 4276 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 4277 Ptr.getNode()->hasOneUse()) 4278 return false; 4279 4280 // Ask the target to do addressing mode selection. 4281 SDValue BasePtr; 4282 SDValue Offset; 4283 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4284 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 4285 return false; 4286 // Don't create a indexed load / store with zero offset. 4287 if (isa<ConstantSDNode>(Offset) && 4288 cast<ConstantSDNode>(Offset)->isNullValue()) 4289 return false; 4290 4291 // Try turning it into a pre-indexed load / store except when: 4292 // 1) The new base ptr is a frame index. 4293 // 2) If N is a store and the new base ptr is either the same as or is a 4294 // predecessor of the value being stored. 4295 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 4296 // that would create a cycle. 4297 // 4) All uses are load / store ops that use it as old base ptr. 4298 4299 // Check #1. Preinc'ing a frame index would require copying the stack pointer 4300 // (plus the implicit offset) to a register to preinc anyway. 4301 if (isa<FrameIndexSDNode>(BasePtr)) 4302 return false; 4303 4304 // Check #2. 4305 if (!isLoad) { 4306 SDValue Val = cast<StoreSDNode>(N)->getValue(); 4307 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode())) 4308 return false; 4309 } 4310 4311 // Now check for #3 and #4. 4312 bool RealUse = false; 4313 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 4314 E = Ptr.getNode()->use_end(); I != E; ++I) { 4315 SDNode *Use = *I; 4316 if (Use == N) 4317 continue; 4318 if (Use->isPredecessorOf(N)) 4319 return false; 4320 4321 if (!((Use->getOpcode() == ISD::LOAD && 4322 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 4323 (Use->getOpcode() == ISD::STORE && 4324 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))) 4325 RealUse = true; 4326 } 4327 if (!RealUse) 4328 return false; 4329 4330 SDValue Result; 4331 if (isLoad) 4332 Result = DAG.getIndexedLoad(SDValue(N,0), BasePtr, Offset, AM); 4333 else 4334 Result = DAG.getIndexedStore(SDValue(N,0), BasePtr, Offset, AM); 4335 ++PreIndexedNodes; 4336 ++NodesCombined; 4337 DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG)); 4338 DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG)); 4339 DOUT << '\n'; 4340 WorkListRemover DeadNodes(*this); 4341 if (isLoad) { 4342 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 4343 &DeadNodes); 4344 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 4345 &DeadNodes); 4346 } else { 4347 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 4348 &DeadNodes); 4349 } 4350 4351 // Finally, since the node is now dead, remove it from the graph. 4352 DAG.DeleteNode(N); 4353 4354 // Replace the uses of Ptr with uses of the updated base value. 4355 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 4356 &DeadNodes); 4357 removeFromWorkList(Ptr.getNode()); 4358 DAG.DeleteNode(Ptr.getNode()); 4359 4360 return true; 4361} 4362 4363/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 4364/// add / sub of the base pointer node into a post-indexed load / store. 4365/// The transformation folded the add / subtract into the new indexed 4366/// load / store effectively and all of its uses are redirected to the 4367/// new load / store. 4368bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 4369 if (!LegalOperations) 4370 return false; 4371 4372 bool isLoad = true; 4373 SDValue Ptr; 4374 MVT VT; 4375 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4376 if (LD->isIndexed()) 4377 return false; 4378 VT = LD->getMemoryVT(); 4379 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 4380 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 4381 return false; 4382 Ptr = LD->getBasePtr(); 4383 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4384 if (ST->isIndexed()) 4385 return false; 4386 VT = ST->getMemoryVT(); 4387 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 4388 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 4389 return false; 4390 Ptr = ST->getBasePtr(); 4391 isLoad = false; 4392 } else 4393 return false; 4394 4395 if (Ptr.getNode()->hasOneUse()) 4396 return false; 4397 4398 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 4399 E = Ptr.getNode()->use_end(); I != E; ++I) { 4400 SDNode *Op = *I; 4401 if (Op == N || 4402 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 4403 continue; 4404 4405 SDValue BasePtr; 4406 SDValue Offset; 4407 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4408 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 4409 if (Ptr == Offset) 4410 std::swap(BasePtr, Offset); 4411 if (Ptr != BasePtr) 4412 continue; 4413 // Don't create a indexed load / store with zero offset. 4414 if (isa<ConstantSDNode>(Offset) && 4415 cast<ConstantSDNode>(Offset)->isNullValue()) 4416 continue; 4417 4418 // Try turning it into a post-indexed load / store except when 4419 // 1) All uses are load / store ops that use it as base ptr. 4420 // 2) Op must be independent of N, i.e. Op is neither a predecessor 4421 // nor a successor of N. Otherwise, if Op is folded that would 4422 // create a cycle. 4423 4424 // Check for #1. 4425 bool TryNext = false; 4426 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), 4427 EE = BasePtr.getNode()->use_end(); II != EE; ++II) { 4428 SDNode *Use = *II; 4429 if (Use == Ptr.getNode()) 4430 continue; 4431 4432 // If all the uses are load / store addresses, then don't do the 4433 // transformation. 4434 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 4435 bool RealUse = false; 4436 for (SDNode::use_iterator III = Use->use_begin(), 4437 EEE = Use->use_end(); III != EEE; ++III) { 4438 SDNode *UseUse = *III; 4439 if (!((UseUse->getOpcode() == ISD::LOAD && 4440 cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) || 4441 (UseUse->getOpcode() == ISD::STORE && 4442 cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use))) 4443 RealUse = true; 4444 } 4445 4446 if (!RealUse) { 4447 TryNext = true; 4448 break; 4449 } 4450 } 4451 } 4452 if (TryNext) 4453 continue; 4454 4455 // Check for #2 4456 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 4457 SDValue Result = isLoad 4458 ? DAG.getIndexedLoad(SDValue(N,0), BasePtr, Offset, AM) 4459 : DAG.getIndexedStore(SDValue(N,0), BasePtr, Offset, AM); 4460 ++PostIndexedNodes; 4461 ++NodesCombined; 4462 DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG)); 4463 DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG)); 4464 DOUT << '\n'; 4465 WorkListRemover DeadNodes(*this); 4466 if (isLoad) { 4467 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 4468 &DeadNodes); 4469 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 4470 &DeadNodes); 4471 } else { 4472 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 4473 &DeadNodes); 4474 } 4475 4476 // Finally, since the node is now dead, remove it from the graph. 4477 DAG.DeleteNode(N); 4478 4479 // Replace the uses of Use with uses of the updated base value. 4480 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 4481 Result.getValue(isLoad ? 1 : 0), 4482 &DeadNodes); 4483 removeFromWorkList(Op); 4484 DAG.DeleteNode(Op); 4485 return true; 4486 } 4487 } 4488 } 4489 return false; 4490} 4491 4492/// InferAlignment - If we can infer some alignment information from this 4493/// pointer, return it. 4494static unsigned InferAlignment(SDValue Ptr, SelectionDAG &DAG) { 4495 // If this is a direct reference to a stack slot, use information about the 4496 // stack slot's alignment. 4497 int FrameIdx = 1 << 31; 4498 int64_t FrameOffset = 0; 4499 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Ptr)) { 4500 FrameIdx = FI->getIndex(); 4501 } else if (Ptr.getOpcode() == ISD::ADD && 4502 isa<ConstantSDNode>(Ptr.getOperand(1)) && 4503 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 4504 FrameIdx = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 4505 FrameOffset = Ptr.getConstantOperandVal(1); 4506 } 4507 4508 if (FrameIdx != (1 << 31)) { 4509 // FIXME: Handle FI+CST. 4510 const MachineFrameInfo &MFI = *DAG.getMachineFunction().getFrameInfo(); 4511 if (MFI.isFixedObjectIndex(FrameIdx)) { 4512 int64_t ObjectOffset = MFI.getObjectOffset(FrameIdx) + FrameOffset; 4513 4514 // The alignment of the frame index can be determined from its offset from 4515 // the incoming frame position. If the frame object is at offset 32 and 4516 // the stack is guaranteed to be 16-byte aligned, then we know that the 4517 // object is 16-byte aligned. 4518 unsigned StackAlign = DAG.getTarget().getFrameInfo()->getStackAlignment(); 4519 unsigned Align = MinAlign(ObjectOffset, StackAlign); 4520 4521 // Finally, the frame object itself may have a known alignment. Factor 4522 // the alignment + offset into a new alignment. For example, if we know 4523 // the FI is 8 byte aligned, but the pointer is 4 off, we really have a 4524 // 4-byte alignment of the resultant pointer. Likewise align 4 + 4-byte 4525 // offset = 4-byte alignment, align 4 + 1-byte offset = align 1, etc. 4526 unsigned FIInfoAlign = MinAlign(MFI.getObjectAlignment(FrameIdx), 4527 FrameOffset); 4528 return std::max(Align, FIInfoAlign); 4529 } 4530 } 4531 4532 return 0; 4533} 4534 4535SDValue DAGCombiner::visitLOAD(SDNode *N) { 4536 LoadSDNode *LD = cast<LoadSDNode>(N); 4537 SDValue Chain = LD->getChain(); 4538 SDValue Ptr = LD->getBasePtr(); 4539 4540 // Try to infer better alignment information than the load already has. 4541 if (!Fast && LD->isUnindexed()) { 4542 if (unsigned Align = InferAlignment(Ptr, DAG)) { 4543 if (Align > LD->getAlignment()) 4544 return DAG.getExtLoad(LD->getExtensionType(), LD->getValueType(0), 4545 Chain, Ptr, LD->getSrcValue(), 4546 LD->getSrcValueOffset(), LD->getMemoryVT(), 4547 LD->isVolatile(), Align); 4548 } 4549 } 4550 4551 4552 // If load is not volatile and there are no uses of the loaded value (and 4553 // the updated indexed value in case of indexed loads), change uses of the 4554 // chain value into uses of the chain input (i.e. delete the dead load). 4555 if (!LD->isVolatile()) { 4556 if (N->getValueType(1) == MVT::Other) { 4557 // Unindexed loads. 4558 if (N->hasNUsesOfValue(0, 0)) { 4559 // It's not safe to use the two value CombineTo variant here. e.g. 4560 // v1, chain2 = load chain1, loc 4561 // v2, chain3 = load chain2, loc 4562 // v3 = add v2, c 4563 // Now we replace use of chain2 with chain1. This makes the second load 4564 // isomorphic to the one we are deleting, and thus makes this load live. 4565 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4566 DOUT << "\nWith chain: "; DEBUG(Chain.getNode()->dump(&DAG)); 4567 DOUT << "\n"; 4568 WorkListRemover DeadNodes(*this); 4569 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes); 4570 if (N->use_empty()) { 4571 removeFromWorkList(N); 4572 DAG.DeleteNode(N); 4573 } 4574 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4575 } 4576 } else { 4577 // Indexed loads. 4578 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 4579 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 4580 SDValue Undef = DAG.getNode(ISD::UNDEF, N->getValueType(0)); 4581 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4582 DOUT << "\nWith: "; DEBUG(Undef.getNode()->dump(&DAG)); 4583 DOUT << " and 2 other values\n"; 4584 WorkListRemover DeadNodes(*this); 4585 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes); 4586 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 4587 DAG.getNode(ISD::UNDEF, N->getValueType(1)), 4588 &DeadNodes); 4589 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes); 4590 removeFromWorkList(N); 4591 DAG.DeleteNode(N); 4592 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4593 } 4594 } 4595 } 4596 4597 // If this load is directly stored, replace the load value with the stored 4598 // value. 4599 // TODO: Handle store large -> read small portion. 4600 // TODO: Handle TRUNCSTORE/LOADEXT 4601 if (LD->getExtensionType() == ISD::NON_EXTLOAD && 4602 !LD->isVolatile()) { 4603 if (ISD::isNON_TRUNCStore(Chain.getNode())) { 4604 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 4605 if (PrevST->getBasePtr() == Ptr && 4606 PrevST->getValue().getValueType() == N->getValueType(0)) 4607 return CombineTo(N, Chain.getOperand(1), Chain); 4608 } 4609 } 4610 4611 if (CombinerAA) { 4612 // Walk up chain skipping non-aliasing memory nodes. 4613 SDValue BetterChain = FindBetterChain(N, Chain); 4614 4615 // If there is a better chain. 4616 if (Chain != BetterChain) { 4617 SDValue ReplLoad; 4618 4619 // Replace the chain to void dependency. 4620 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 4621 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr, 4622 LD->getSrcValue(), LD->getSrcValueOffset(), 4623 LD->isVolatile(), LD->getAlignment()); 4624 } else { 4625 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), 4626 LD->getValueType(0), 4627 BetterChain, Ptr, LD->getSrcValue(), 4628 LD->getSrcValueOffset(), 4629 LD->getMemoryVT(), 4630 LD->isVolatile(), 4631 LD->getAlignment()); 4632 } 4633 4634 // Create token factor to keep old chain connected. 4635 SDValue Token = DAG.getNode(ISD::TokenFactor, MVT::Other, 4636 Chain, ReplLoad.getValue(1)); 4637 4638 // Replace uses with load result and token factor. Don't add users 4639 // to work list. 4640 return CombineTo(N, ReplLoad.getValue(0), Token, false); 4641 } 4642 } 4643 4644 // Try transforming N to an indexed load. 4645 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4646 return SDValue(N, 0); 4647 4648 return SDValue(); 4649} 4650 4651 4652SDValue DAGCombiner::visitSTORE(SDNode *N) { 4653 StoreSDNode *ST = cast<StoreSDNode>(N); 4654 SDValue Chain = ST->getChain(); 4655 SDValue Value = ST->getValue(); 4656 SDValue Ptr = ST->getBasePtr(); 4657 4658 // Try to infer better alignment information than the store already has. 4659 if (!Fast && ST->isUnindexed()) { 4660 if (unsigned Align = InferAlignment(Ptr, DAG)) { 4661 if (Align > ST->getAlignment()) 4662 return DAG.getTruncStore(Chain, Value, Ptr, ST->getSrcValue(), 4663 ST->getSrcValueOffset(), ST->getMemoryVT(), 4664 ST->isVolatile(), Align); 4665 } 4666 } 4667 4668 // If this is a store of a bit convert, store the input value if the 4669 // resultant store does not need a higher alignment than the original. 4670 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() && 4671 ST->isUnindexed()) { 4672 unsigned Align = ST->getAlignment(); 4673 MVT SVT = Value.getOperand(0).getValueType(); 4674 unsigned OrigAlign = TLI.getTargetData()-> 4675 getABITypeAlignment(SVT.getTypeForMVT()); 4676 if (Align <= OrigAlign && 4677 ((!LegalOperations && !ST->isVolatile()) || 4678 TLI.isOperationLegal(ISD::STORE, SVT))) 4679 return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), 4680 ST->getSrcValueOffset(), ST->isVolatile(), OrigAlign); 4681 } 4682 4683 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 4684 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 4685 // NOTE: If the original store is volatile, this transform must not increase 4686 // the number of stores. For example, on x86-32 an f64 can be stored in one 4687 // processor operation but an i64 (which is not legal) requires two. So the 4688 // transform should not be done in this case. 4689 if (Value.getOpcode() != ISD::TargetConstantFP) { 4690 SDValue Tmp; 4691 switch (CFP->getValueType(0).getSimpleVT()) { 4692 default: assert(0 && "Unknown FP type"); 4693 case MVT::f80: // We don't do this for these yet. 4694 case MVT::f128: 4695 case MVT::ppcf128: 4696 break; 4697 case MVT::f32: 4698 if (((TLI.isTypeLegal(MVT::i32) || !LegalTypes) && !LegalOperations && 4699 !ST->isVolatile()) || TLI.isOperationLegal(ISD::STORE, MVT::i32)) { 4700 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 4701 bitcastToAPInt().getZExtValue(), MVT::i32); 4702 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 4703 ST->getSrcValueOffset(), ST->isVolatile(), 4704 ST->getAlignment()); 4705 } 4706 break; 4707 case MVT::f64: 4708 if (((TLI.isTypeLegal(MVT::i64) || !LegalTypes) && !LegalOperations && 4709 !ST->isVolatile()) || TLI.isOperationLegal(ISD::STORE, MVT::i64)) { 4710 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 4711 getZExtValue(), MVT::i64); 4712 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 4713 ST->getSrcValueOffset(), ST->isVolatile(), 4714 ST->getAlignment()); 4715 } else if (!ST->isVolatile() && 4716 TLI.isOperationLegal(ISD::STORE, MVT::i32)) { 4717 // Many FP stores are not made apparent until after legalize, e.g. for 4718 // argument passing. Since this is so common, custom legalize the 4719 // 64-bit integer store into two 32-bit stores. 4720 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); 4721 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 4722 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 4723 if (TLI.isBigEndian()) std::swap(Lo, Hi); 4724 4725 int SVOffset = ST->getSrcValueOffset(); 4726 unsigned Alignment = ST->getAlignment(); 4727 bool isVolatile = ST->isVolatile(); 4728 4729 SDValue St0 = DAG.getStore(Chain, Lo, Ptr, ST->getSrcValue(), 4730 ST->getSrcValueOffset(), 4731 isVolatile, ST->getAlignment()); 4732 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 4733 DAG.getConstant(4, Ptr.getValueType())); 4734 SVOffset += 4; 4735 Alignment = MinAlign(Alignment, 4U); 4736 SDValue St1 = DAG.getStore(Chain, Hi, Ptr, ST->getSrcValue(), 4737 SVOffset, isVolatile, Alignment); 4738 return DAG.getNode(ISD::TokenFactor, MVT::Other, St0, St1); 4739 } 4740 break; 4741 } 4742 } 4743 } 4744 4745 if (CombinerAA) { 4746 // Walk up chain skipping non-aliasing memory nodes. 4747 SDValue BetterChain = FindBetterChain(N, Chain); 4748 4749 // If there is a better chain. 4750 if (Chain != BetterChain) { 4751 // Replace the chain to avoid dependency. 4752 SDValue ReplStore; 4753 if (ST->isTruncatingStore()) { 4754 ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr, 4755 ST->getSrcValue(),ST->getSrcValueOffset(), 4756 ST->getMemoryVT(), 4757 ST->isVolatile(), ST->getAlignment()); 4758 } else { 4759 ReplStore = DAG.getStore(BetterChain, Value, Ptr, 4760 ST->getSrcValue(), ST->getSrcValueOffset(), 4761 ST->isVolatile(), ST->getAlignment()); 4762 } 4763 4764 // Create token to keep both nodes around. 4765 SDValue Token = 4766 DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore); 4767 4768 // Don't add users to work list. 4769 return CombineTo(N, Token, false); 4770 } 4771 } 4772 4773 // Try transforming N to an indexed store. 4774 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4775 return SDValue(N, 0); 4776 4777 // FIXME: is there such a thing as a truncating indexed store? 4778 if (ST->isTruncatingStore() && ST->isUnindexed() && 4779 Value.getValueType().isInteger()) { 4780 // See if we can simplify the input to this truncstore with knowledge that 4781 // only the low bits are being used. For example: 4782 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 4783 SDValue Shorter = 4784 GetDemandedBits(Value, 4785 APInt::getLowBitsSet(Value.getValueSizeInBits(), 4786 ST->getMemoryVT().getSizeInBits())); 4787 AddToWorkList(Value.getNode()); 4788 if (Shorter.getNode()) 4789 return DAG.getTruncStore(Chain, Shorter, Ptr, ST->getSrcValue(), 4790 ST->getSrcValueOffset(), ST->getMemoryVT(), 4791 ST->isVolatile(), ST->getAlignment()); 4792 4793 // Otherwise, see if we can simplify the operation with 4794 // SimplifyDemandedBits, which only works if the value has a single use. 4795 if (SimplifyDemandedBits(Value, 4796 APInt::getLowBitsSet( 4797 Value.getValueSizeInBits(), 4798 ST->getMemoryVT().getSizeInBits()))) 4799 return SDValue(N, 0); 4800 } 4801 4802 // If this is a load followed by a store to the same location, then the store 4803 // is dead/noop. 4804 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 4805 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 4806 ST->isUnindexed() && !ST->isVolatile() && 4807 // There can't be any side effects between the load and store, such as 4808 // a call or store. 4809 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 4810 // The store is dead, remove it. 4811 return Chain; 4812 } 4813 } 4814 4815 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 4816 // truncating store. We can do this even if this is already a truncstore. 4817 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 4818 && Value.getNode()->hasOneUse() && ST->isUnindexed() && 4819 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 4820 ST->getMemoryVT())) { 4821 return DAG.getTruncStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), 4822 ST->getSrcValueOffset(), ST->getMemoryVT(), 4823 ST->isVolatile(), ST->getAlignment()); 4824 } 4825 4826 return SDValue(); 4827} 4828 4829SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 4830 SDValue InVec = N->getOperand(0); 4831 SDValue InVal = N->getOperand(1); 4832 SDValue EltNo = N->getOperand(2); 4833 4834 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 4835 // vector with the inserted element. 4836 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 4837 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 4838 SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(), 4839 InVec.getNode()->op_end()); 4840 if (Elt < Ops.size()) 4841 Ops[Elt] = InVal; 4842 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(), 4843 &Ops[0], Ops.size()); 4844 } 4845 4846 return SDValue(); 4847} 4848 4849SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 4850 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 4851 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 4852 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 4853 4854 // Perform only after legalization to ensure build_vector / vector_shuffle 4855 // optimizations have already been done. 4856 if (!LegalOperations) return SDValue(); 4857 4858 SDValue InVec = N->getOperand(0); 4859 SDValue EltNo = N->getOperand(1); 4860 4861 if (isa<ConstantSDNode>(EltNo)) { 4862 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 4863 bool NewLoad = false; 4864 MVT VT = InVec.getValueType(); 4865 MVT EVT = VT.getVectorElementType(); 4866 MVT LVT = EVT; 4867 if (InVec.getOpcode() == ISD::BIT_CONVERT) { 4868 MVT BCVT = InVec.getOperand(0).getValueType(); 4869 if (!BCVT.isVector() || EVT.bitsGT(BCVT.getVectorElementType())) 4870 return SDValue(); 4871 InVec = InVec.getOperand(0); 4872 EVT = BCVT.getVectorElementType(); 4873 NewLoad = true; 4874 } 4875 4876 LoadSDNode *LN0 = NULL; 4877 if (ISD::isNormalLoad(InVec.getNode())) 4878 LN0 = cast<LoadSDNode>(InVec); 4879 else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 4880 InVec.getOperand(0).getValueType() == EVT && 4881 ISD::isNormalLoad(InVec.getOperand(0).getNode())) { 4882 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 4883 } else if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE) { 4884 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 4885 // => 4886 // (load $addr+1*size) 4887 unsigned Idx = cast<ConstantSDNode>(InVec.getOperand(2). 4888 getOperand(Elt))->getZExtValue(); 4889 unsigned NumElems = InVec.getOperand(2).getNumOperands(); 4890 InVec = (Idx < NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 4891 if (InVec.getOpcode() == ISD::BIT_CONVERT) 4892 InVec = InVec.getOperand(0); 4893 if (ISD::isNormalLoad(InVec.getNode())) { 4894 LN0 = cast<LoadSDNode>(InVec); 4895 Elt = (Idx < NumElems) ? Idx : Idx - NumElems; 4896 } 4897 } 4898 if (!LN0 || !LN0->hasOneUse() || LN0->isVolatile()) 4899 return SDValue(); 4900 4901 unsigned Align = LN0->getAlignment(); 4902 if (NewLoad) { 4903 // Check the resultant load doesn't need a higher alignment than the 4904 // original load. 4905 unsigned NewAlign = TLI.getTargetData()-> 4906 getABITypeAlignment(LVT.getTypeForMVT()); 4907 if (NewAlign > Align || !TLI.isOperationLegal(ISD::LOAD, LVT)) 4908 return SDValue(); 4909 Align = NewAlign; 4910 } 4911 4912 SDValue NewPtr = LN0->getBasePtr(); 4913 if (Elt) { 4914 unsigned PtrOff = LVT.getSizeInBits() * Elt / 8; 4915 MVT PtrType = NewPtr.getValueType(); 4916 if (TLI.isBigEndian()) 4917 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 4918 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, 4919 DAG.getConstant(PtrOff, PtrType)); 4920 } 4921 return DAG.getLoad(LVT, LN0->getChain(), NewPtr, 4922 LN0->getSrcValue(), LN0->getSrcValueOffset(), 4923 LN0->isVolatile(), Align); 4924 } 4925 return SDValue(); 4926} 4927 4928 4929SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 4930 unsigned NumInScalars = N->getNumOperands(); 4931 MVT VT = N->getValueType(0); 4932 unsigned NumElts = VT.getVectorNumElements(); 4933 MVT EltType = VT.getVectorElementType(); 4934 4935 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 4936 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 4937 // at most two distinct vectors, turn this into a shuffle node. 4938 SDValue VecIn1, VecIn2; 4939 for (unsigned i = 0; i != NumInScalars; ++i) { 4940 // Ignore undef inputs. 4941 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 4942 4943 // If this input is something other than a EXTRACT_VECTOR_ELT with a 4944 // constant index, bail out. 4945 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 4946 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 4947 VecIn1 = VecIn2 = SDValue(0, 0); 4948 break; 4949 } 4950 4951 // If the input vector type disagrees with the result of the build_vector, 4952 // we can't make a shuffle. 4953 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 4954 if (ExtractedFromVec.getValueType() != VT) { 4955 VecIn1 = VecIn2 = SDValue(0, 0); 4956 break; 4957 } 4958 4959 // Otherwise, remember this. We allow up to two distinct input vectors. 4960 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 4961 continue; 4962 4963 if (VecIn1.getNode() == 0) { 4964 VecIn1 = ExtractedFromVec; 4965 } else if (VecIn2.getNode() == 0) { 4966 VecIn2 = ExtractedFromVec; 4967 } else { 4968 // Too many inputs. 4969 VecIn1 = VecIn2 = SDValue(0, 0); 4970 break; 4971 } 4972 } 4973 4974 // If everything is good, we can make a shuffle operation. 4975 if (VecIn1.getNode()) { 4976 SmallVector<SDValue, 8> BuildVecIndices; 4977 for (unsigned i = 0; i != NumInScalars; ++i) { 4978 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 4979 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, TLI.getPointerTy())); 4980 continue; 4981 } 4982 4983 SDValue Extract = N->getOperand(i); 4984 4985 // If extracting from the first vector, just use the index directly. 4986 if (Extract.getOperand(0) == VecIn1) { 4987 BuildVecIndices.push_back(Extract.getOperand(1)); 4988 continue; 4989 } 4990 4991 // Otherwise, use InIdx + VecSize 4992 unsigned Idx = 4993 cast<ConstantSDNode>(Extract.getOperand(1))->getZExtValue(); 4994 BuildVecIndices.push_back(DAG.getIntPtrConstant(Idx+NumInScalars)); 4995 } 4996 4997 // Add count and size info. 4998 MVT BuildVecVT = MVT::getVectorVT(TLI.getPointerTy(), NumElts); 4999 if (!TLI.isTypeLegal(BuildVecVT) && LegalTypes) 5000 return SDValue(); 5001 5002 // Return the new VECTOR_SHUFFLE node. 5003 SDValue Ops[5]; 5004 Ops[0] = VecIn1; 5005 if (VecIn2.getNode()) { 5006 Ops[1] = VecIn2; 5007 } else { 5008 // Use an undef build_vector as input for the second operand. 5009 std::vector<SDValue> UnOps(NumInScalars, 5010 DAG.getNode(ISD::UNDEF, 5011 EltType)); 5012 Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, VT, 5013 &UnOps[0], UnOps.size()); 5014 AddToWorkList(Ops[1].getNode()); 5015 } 5016 Ops[2] = DAG.getNode(ISD::BUILD_VECTOR, BuildVecVT, 5017 &BuildVecIndices[0], BuildVecIndices.size()); 5018 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Ops, 3); 5019 } 5020 5021 return SDValue(); 5022} 5023 5024SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 5025 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 5026 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 5027 // inputs come from at most two distinct vectors, turn this into a shuffle 5028 // node. 5029 5030 // If we only have one input vector, we don't need to do any concatenation. 5031 if (N->getNumOperands() == 1) { 5032 return N->getOperand(0); 5033 } 5034 5035 return SDValue(); 5036} 5037 5038SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 5039 SDValue ShufMask = N->getOperand(2); 5040 unsigned NumElts = ShufMask.getNumOperands(); 5041 5042 SDValue N0 = N->getOperand(0); 5043 SDValue N1 = N->getOperand(1); 5044 5045 assert(N0.getValueType().getVectorNumElements() == NumElts && 5046 "Vector shuffle must be normalized in DAG"); 5047 5048 // If the shuffle mask is an identity operation on the LHS, return the LHS. 5049 bool isIdentity = true; 5050 for (unsigned i = 0; i != NumElts; ++i) { 5051 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 5052 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() != i) { 5053 isIdentity = false; 5054 break; 5055 } 5056 } 5057 if (isIdentity) return N->getOperand(0); 5058 5059 // If the shuffle mask is an identity operation on the RHS, return the RHS. 5060 isIdentity = true; 5061 for (unsigned i = 0; i != NumElts; ++i) { 5062 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 5063 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() != 5064 i+NumElts) { 5065 isIdentity = false; 5066 break; 5067 } 5068 } 5069 if (isIdentity) return N->getOperand(1); 5070 5071 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not 5072 // needed at all. 5073 bool isUnary = true; 5074 bool isSplat = true; 5075 int VecNum = -1; 5076 unsigned BaseIdx = 0; 5077 for (unsigned i = 0; i != NumElts; ++i) 5078 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) { 5079 unsigned Idx=cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue(); 5080 int V = (Idx < NumElts) ? 0 : 1; 5081 if (VecNum == -1) { 5082 VecNum = V; 5083 BaseIdx = Idx; 5084 } else { 5085 if (BaseIdx != Idx) 5086 isSplat = false; 5087 if (VecNum != V) { 5088 isUnary = false; 5089 break; 5090 } 5091 } 5092 } 5093 5094 // Normalize unary shuffle so the RHS is undef. 5095 if (isUnary && VecNum == 1) 5096 std::swap(N0, N1); 5097 5098 // If it is a splat, check if the argument vector is a build_vector with 5099 // all scalar elements the same. 5100 if (isSplat) { 5101 SDNode *V = N0.getNode(); 5102 5103 // If this is a bit convert that changes the element type of the vector but 5104 // not the number of vector elements, look through it. Be careful not to 5105 // look though conversions that change things like v4f32 to v2f64. 5106 if (V->getOpcode() == ISD::BIT_CONVERT) { 5107 SDValue ConvInput = V->getOperand(0); 5108 if (ConvInput.getValueType().isVector() && 5109 ConvInput.getValueType().getVectorNumElements() == NumElts) 5110 V = ConvInput.getNode(); 5111 } 5112 5113 if (V->getOpcode() == ISD::BUILD_VECTOR) { 5114 unsigned NumElems = V->getNumOperands(); 5115 if (NumElems > BaseIdx) { 5116 SDValue Base; 5117 bool AllSame = true; 5118 for (unsigned i = 0; i != NumElems; ++i) { 5119 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 5120 Base = V->getOperand(i); 5121 break; 5122 } 5123 } 5124 // Splat of <u, u, u, u>, return <u, u, u, u> 5125 if (!Base.getNode()) 5126 return N0; 5127 for (unsigned i = 0; i != NumElems; ++i) { 5128 if (V->getOperand(i) != Base) { 5129 AllSame = false; 5130 break; 5131 } 5132 } 5133 // Splat of <x, x, x, x>, return <x, x, x, x> 5134 if (AllSame) 5135 return N0; 5136 } 5137 } 5138 } 5139 5140 // If it is a unary or the LHS and the RHS are the same node, turn the RHS 5141 // into an undef. 5142 if (isUnary || N0 == N1) { 5143 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the 5144 // first operand. 5145 SmallVector<SDValue, 8> MappedOps; 5146 for (unsigned i = 0; i != NumElts; ++i) { 5147 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || 5148 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() < 5149 NumElts) { 5150 MappedOps.push_back(ShufMask.getOperand(i)); 5151 } else { 5152 unsigned NewIdx = 5153 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() - 5154 NumElts; 5155 MappedOps.push_back(DAG.getConstant(NewIdx, 5156 ShufMask.getOperand(i).getValueType())); 5157 } 5158 } 5159 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(), 5160 &MappedOps[0], MappedOps.size()); 5161 AddToWorkList(ShufMask.getNode()); 5162 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0), 5163 N0, 5164 DAG.getNode(ISD::UNDEF, N->getValueType(0)), 5165 ShufMask); 5166 } 5167 5168 return SDValue(); 5169} 5170 5171/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 5172/// an AND to a vector_shuffle with the destination vector and a zero vector. 5173/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 5174/// vector_shuffle V, Zero, <0, 4, 2, 4> 5175SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 5176 SDValue LHS = N->getOperand(0); 5177 SDValue RHS = N->getOperand(1); 5178 if (N->getOpcode() == ISD::AND) { 5179 if (RHS.getOpcode() == ISD::BIT_CONVERT) 5180 RHS = RHS.getOperand(0); 5181 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 5182 std::vector<SDValue> IdxOps; 5183 unsigned NumOps = RHS.getNumOperands(); 5184 unsigned NumElts = NumOps; 5185 for (unsigned i = 0; i != NumElts; ++i) { 5186 SDValue Elt = RHS.getOperand(i); 5187 if (!isa<ConstantSDNode>(Elt)) 5188 return SDValue(); 5189 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 5190 IdxOps.push_back(DAG.getIntPtrConstant(i)); 5191 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 5192 IdxOps.push_back(DAG.getIntPtrConstant(NumElts)); 5193 else 5194 return SDValue(); 5195 } 5196 5197 // Let's see if the target supports this vector_shuffle. 5198 if (!TLI.isVectorClearMaskLegal(IdxOps, TLI.getPointerTy(), DAG)) 5199 return SDValue(); 5200 5201 // Return the new VECTOR_SHUFFLE node. 5202 MVT EVT = RHS.getValueType().getVectorElementType(); 5203 MVT VT = MVT::getVectorVT(EVT, NumElts); 5204 MVT MaskVT = MVT::getVectorVT(TLI.getPointerTy(), NumElts); 5205 std::vector<SDValue> Ops; 5206 LHS = DAG.getNode(ISD::BIT_CONVERT, VT, LHS); 5207 Ops.push_back(LHS); 5208 AddToWorkList(LHS.getNode()); 5209 std::vector<SDValue> ZeroOps(NumElts, DAG.getConstant(0, EVT)); 5210 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT, 5211 &ZeroOps[0], ZeroOps.size())); 5212 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 5213 &IdxOps[0], IdxOps.size())); 5214 SDValue Result = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, 5215 &Ops[0], Ops.size()); 5216 if (VT != N->getValueType(0)) 5217 Result = DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Result); 5218 return Result; 5219 } 5220 } 5221 return SDValue(); 5222} 5223 5224/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 5225SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 5226 // After legalize, the target may be depending on adds and other 5227 // binary ops to provide legal ways to construct constants or other 5228 // things. Simplifying them may result in a loss of legality. 5229 if (LegalOperations) return SDValue(); 5230 5231 MVT VT = N->getValueType(0); 5232 assert(VT.isVector() && "SimplifyVBinOp only works on vectors!"); 5233 5234 MVT EltType = VT.getVectorElementType(); 5235 SDValue LHS = N->getOperand(0); 5236 SDValue RHS = N->getOperand(1); 5237 SDValue Shuffle = XformToShuffleWithZero(N); 5238 if (Shuffle.getNode()) return Shuffle; 5239 5240 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 5241 // this operation. 5242 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 5243 RHS.getOpcode() == ISD::BUILD_VECTOR) { 5244 SmallVector<SDValue, 8> Ops; 5245 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 5246 SDValue LHSOp = LHS.getOperand(i); 5247 SDValue RHSOp = RHS.getOperand(i); 5248 // If these two elements can't be folded, bail out. 5249 if ((LHSOp.getOpcode() != ISD::UNDEF && 5250 LHSOp.getOpcode() != ISD::Constant && 5251 LHSOp.getOpcode() != ISD::ConstantFP) || 5252 (RHSOp.getOpcode() != ISD::UNDEF && 5253 RHSOp.getOpcode() != ISD::Constant && 5254 RHSOp.getOpcode() != ISD::ConstantFP)) 5255 break; 5256 // Can't fold divide by zero. 5257 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 5258 N->getOpcode() == ISD::FDIV) { 5259 if ((RHSOp.getOpcode() == ISD::Constant && 5260 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) || 5261 (RHSOp.getOpcode() == ISD::ConstantFP && 5262 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero())) 5263 break; 5264 } 5265 Ops.push_back(DAG.getNode(N->getOpcode(), EltType, LHSOp, RHSOp)); 5266 AddToWorkList(Ops.back().getNode()); 5267 assert((Ops.back().getOpcode() == ISD::UNDEF || 5268 Ops.back().getOpcode() == ISD::Constant || 5269 Ops.back().getOpcode() == ISD::ConstantFP) && 5270 "Scalar binop didn't fold!"); 5271 } 5272 5273 if (Ops.size() == LHS.getNumOperands()) { 5274 MVT VT = LHS.getValueType(); 5275 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 5276 } 5277 } 5278 5279 return SDValue(); 5280} 5281 5282SDValue DAGCombiner::SimplifySelect(SDValue N0, SDValue N1, SDValue N2){ 5283 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 5284 5285 SDValue SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2, 5286 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 5287 // If we got a simplified select_cc node back from SimplifySelectCC, then 5288 // break it down into a new SETCC node, and a new SELECT node, and then return 5289 // the SELECT node, since we were called with a SELECT node. 5290 if (SCC.getNode()) { 5291 // Check to see if we got a select_cc back (to turn into setcc/select). 5292 // Otherwise, just return whatever node we got back, like fabs. 5293 if (SCC.getOpcode() == ISD::SELECT_CC) { 5294 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(), 5295 SCC.getOperand(0), SCC.getOperand(1), 5296 SCC.getOperand(4)); 5297 AddToWorkList(SETCC.getNode()); 5298 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2), 5299 SCC.getOperand(3), SETCC); 5300 } 5301 return SCC; 5302 } 5303 return SDValue(); 5304} 5305 5306/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 5307/// are the two values being selected between, see if we can simplify the 5308/// select. Callers of this should assume that TheSelect is deleted if this 5309/// returns true. As such, they should return the appropriate thing (e.g. the 5310/// node) back to the top-level of the DAG combiner loop to avoid it being 5311/// looked at. 5312/// 5313bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 5314 SDValue RHS) { 5315 5316 // If this is a select from two identical things, try to pull the operation 5317 // through the select. 5318 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 5319 // If this is a load and the token chain is identical, replace the select 5320 // of two loads with a load through a select of the address to load from. 5321 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 5322 // constants have been dropped into the constant pool. 5323 if (LHS.getOpcode() == ISD::LOAD && 5324 // Do not let this transformation reduce the number of volatile loads. 5325 !cast<LoadSDNode>(LHS)->isVolatile() && 5326 !cast<LoadSDNode>(RHS)->isVolatile() && 5327 // Token chains must be identical. 5328 LHS.getOperand(0) == RHS.getOperand(0)) { 5329 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 5330 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 5331 5332 // If this is an EXTLOAD, the VT's must match. 5333 if (LLD->getMemoryVT() == RLD->getMemoryVT()) { 5334 // FIXME: this conflates two src values, discarding one. This is not 5335 // the right thing to do, but nothing uses srcvalues now. When they do, 5336 // turn SrcValue into a list of locations. 5337 SDValue Addr; 5338 if (TheSelect->getOpcode() == ISD::SELECT) { 5339 // Check that the condition doesn't reach either load. If so, folding 5340 // this will induce a cycle into the DAG. 5341 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5342 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode())) { 5343 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(), 5344 TheSelect->getOperand(0), LLD->getBasePtr(), 5345 RLD->getBasePtr()); 5346 } 5347 } else { 5348 // Check that the condition doesn't reach either load. If so, folding 5349 // this will induce a cycle into the DAG. 5350 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5351 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5352 !LLD->isPredecessorOf(TheSelect->getOperand(1).getNode()) && 5353 !RLD->isPredecessorOf(TheSelect->getOperand(1).getNode())) { 5354 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(), 5355 TheSelect->getOperand(0), 5356 TheSelect->getOperand(1), 5357 LLD->getBasePtr(), RLD->getBasePtr(), 5358 TheSelect->getOperand(4)); 5359 } 5360 } 5361 5362 if (Addr.getNode()) { 5363 SDValue Load; 5364 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) 5365 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(), 5366 Addr,LLD->getSrcValue(), 5367 LLD->getSrcValueOffset(), 5368 LLD->isVolatile(), 5369 LLD->getAlignment()); 5370 else { 5371 Load = DAG.getExtLoad(LLD->getExtensionType(), 5372 TheSelect->getValueType(0), 5373 LLD->getChain(), Addr, LLD->getSrcValue(), 5374 LLD->getSrcValueOffset(), 5375 LLD->getMemoryVT(), 5376 LLD->isVolatile(), 5377 LLD->getAlignment()); 5378 } 5379 // Users of the select now use the result of the load. 5380 CombineTo(TheSelect, Load); 5381 5382 // Users of the old loads now use the new load's chain. We know the 5383 // old-load value is dead now. 5384 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); 5385 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); 5386 return true; 5387 } 5388 } 5389 } 5390 } 5391 5392 return false; 5393} 5394 5395SDValue DAGCombiner::SimplifySelectCC(SDValue N0, SDValue N1, 5396 SDValue N2, SDValue N3, 5397 ISD::CondCode CC, bool NotExtCompare) { 5398 5399 MVT VT = N2.getValueType(); 5400 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 5401 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 5402 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); 5403 5404 // Determine if the condition we're dealing with is constant 5405 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0), N0, N1, CC, false); 5406 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 5407 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode()); 5408 5409 // fold select_cc true, x, y -> x 5410 if (SCCC && !SCCC->isNullValue()) 5411 return N2; 5412 // fold select_cc false, x, y -> y 5413 if (SCCC && SCCC->isNullValue()) 5414 return N3; 5415 5416 // Check to see if we can simplify the select into an fabs node 5417 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 5418 // Allow either -0.0 or 0.0 5419 if (CFP->getValueAPF().isZero()) { 5420 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 5421 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 5422 N0 == N2 && N3.getOpcode() == ISD::FNEG && 5423 N2 == N3.getOperand(0)) 5424 return DAG.getNode(ISD::FABS, VT, N0); 5425 5426 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 5427 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 5428 N0 == N3 && N2.getOpcode() == ISD::FNEG && 5429 N2.getOperand(0) == N3) 5430 return DAG.getNode(ISD::FABS, VT, N3); 5431 } 5432 } 5433 5434 // Check to see if we can perform the "gzip trick", transforming 5435 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 5436 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 5437 N0.getValueType().isInteger() && 5438 N2.getValueType().isInteger() && 5439 (N1C->isNullValue() || // (a < 0) ? b : 0 5440 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 5441 MVT XType = N0.getValueType(); 5442 MVT AType = N2.getValueType(); 5443 if (XType.bitsGE(AType)) { 5444 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 5445 // single-bit constant. 5446 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 5447 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 5448 ShCtV = XType.getSizeInBits()-ShCtV-1; 5449 SDValue ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy()); 5450 SDValue Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt); 5451 AddToWorkList(Shift.getNode()); 5452 if (XType.bitsGT(AType)) { 5453 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 5454 AddToWorkList(Shift.getNode()); 5455 } 5456 return DAG.getNode(ISD::AND, AType, Shift, N2); 5457 } 5458 SDValue Shift = DAG.getNode(ISD::SRA, XType, N0, 5459 DAG.getConstant(XType.getSizeInBits()-1, 5460 TLI.getShiftAmountTy())); 5461 AddToWorkList(Shift.getNode()); 5462 if (XType.bitsGT(AType)) { 5463 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 5464 AddToWorkList(Shift.getNode()); 5465 } 5466 return DAG.getNode(ISD::AND, AType, Shift, N2); 5467 } 5468 } 5469 5470 // fold select C, 16, 0 -> shl C, 4 5471 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 5472 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) { 5473 5474 // If the caller doesn't want us to simplify this into a zext of a compare, 5475 // don't do it. 5476 if (NotExtCompare && N2C->getAPIntValue() == 1) 5477 return SDValue(); 5478 5479 // Get a SetCC of the condition 5480 // FIXME: Should probably make sure that setcc is legal if we ever have a 5481 // target where it isn't. 5482 SDValue Temp, SCC; 5483 // cast from setcc result type to select result type 5484 if (LegalTypes) { 5485 SCC = DAG.getSetCC(TLI.getSetCCResultType(N0), N0, N1, CC); 5486 if (N2.getValueType().bitsLT(SCC.getValueType())) 5487 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType()); 5488 else 5489 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 5490 } else { 5491 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC); 5492 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 5493 } 5494 AddToWorkList(SCC.getNode()); 5495 AddToWorkList(Temp.getNode()); 5496 5497 if (N2C->getAPIntValue() == 1) 5498 return Temp; 5499 // shl setcc result by log2 n2c 5500 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp, 5501 DAG.getConstant(N2C->getAPIntValue().logBase2(), 5502 TLI.getShiftAmountTy())); 5503 } 5504 5505 // Check to see if this is the equivalent of setcc 5506 // FIXME: Turn all of these into setcc if setcc if setcc is legal 5507 // otherwise, go ahead with the folds. 5508 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 5509 MVT XType = N0.getValueType(); 5510 if (!LegalOperations || 5511 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(N0))) { 5512 SDValue Res = DAG.getSetCC(TLI.getSetCCResultType(N0), N0, N1, CC); 5513 if (Res.getValueType() != VT) 5514 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res); 5515 return Res; 5516 } 5517 5518 // seteq X, 0 -> srl (ctlz X, log2(size(X))) 5519 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 5520 (!LegalOperations || 5521 TLI.isOperationLegal(ISD::CTLZ, XType))) { 5522 SDValue Ctlz = DAG.getNode(ISD::CTLZ, XType, N0); 5523 return DAG.getNode(ISD::SRL, XType, Ctlz, 5524 DAG.getConstant(Log2_32(XType.getSizeInBits()), 5525 TLI.getShiftAmountTy())); 5526 } 5527 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) 5528 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 5529 SDValue NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType), 5530 N0); 5531 SDValue NotN0 = DAG.getNode(ISD::XOR, XType, N0, 5532 DAG.getConstant(~0ULL, XType)); 5533 return DAG.getNode(ISD::SRL, XType, 5534 DAG.getNode(ISD::AND, XType, NegN0, NotN0), 5535 DAG.getConstant(XType.getSizeInBits()-1, 5536 TLI.getShiftAmountTy())); 5537 } 5538 // setgt X, -1 -> xor (srl (X, size(X)-1), 1) 5539 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 5540 SDValue Sign = DAG.getNode(ISD::SRL, XType, N0, 5541 DAG.getConstant(XType.getSizeInBits()-1, 5542 TLI.getShiftAmountTy())); 5543 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType)); 5544 } 5545 } 5546 5547 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 5548 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5549 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 5550 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) && 5551 N2.getOperand(0) == N1 && N0.getValueType().isInteger()) { 5552 MVT XType = N0.getValueType(); 5553 SDValue Shift = DAG.getNode(ISD::SRA, XType, N0, 5554 DAG.getConstant(XType.getSizeInBits()-1, 5555 TLI.getShiftAmountTy())); 5556 SDValue Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 5557 AddToWorkList(Shift.getNode()); 5558 AddToWorkList(Add.getNode()); 5559 return DAG.getNode(ISD::XOR, XType, Add, Shift); 5560 } 5561 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X -> 5562 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5563 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT && 5564 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) { 5565 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 5566 MVT XType = N0.getValueType(); 5567 if (SubC->isNullValue() && XType.isInteger()) { 5568 SDValue Shift = DAG.getNode(ISD::SRA, XType, N0, 5569 DAG.getConstant(XType.getSizeInBits()-1, 5570 TLI.getShiftAmountTy())); 5571 SDValue Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 5572 AddToWorkList(Shift.getNode()); 5573 AddToWorkList(Add.getNode()); 5574 return DAG.getNode(ISD::XOR, XType, Add, Shift); 5575 } 5576 } 5577 } 5578 5579 return SDValue(); 5580} 5581 5582/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 5583SDValue DAGCombiner::SimplifySetCC(MVT VT, SDValue N0, 5584 SDValue N1, ISD::CondCode Cond, 5585 bool foldBooleans) { 5586 TargetLowering::DAGCombinerInfo 5587 DagCombineInfo(DAG, Level == Unrestricted, false, this); 5588 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo); 5589} 5590 5591/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 5592/// return a DAG expression to select that will generate the same value by 5593/// multiplying by a magic number. See: 5594/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 5595SDValue DAGCombiner::BuildSDIV(SDNode *N) { 5596 std::vector<SDNode*> Built; 5597 SDValue S = TLI.BuildSDIV(N, DAG, &Built); 5598 5599 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 5600 ii != ee; ++ii) 5601 AddToWorkList(*ii); 5602 return S; 5603} 5604 5605/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 5606/// return a DAG expression to select that will generate the same value by 5607/// multiplying by a magic number. See: 5608/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 5609SDValue DAGCombiner::BuildUDIV(SDNode *N) { 5610 std::vector<SDNode*> Built; 5611 SDValue S = TLI.BuildUDIV(N, DAG, &Built); 5612 5613 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 5614 ii != ee; ++ii) 5615 AddToWorkList(*ii); 5616 return S; 5617} 5618 5619/// FindBaseOffset - Return true if base is known not to alias with anything 5620/// but itself. Provides base object and offset as results. 5621static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset) { 5622 // Assume it is a primitive operation. 5623 Base = Ptr; Offset = 0; 5624 5625 // If it's an adding a simple constant then integrate the offset. 5626 if (Base.getOpcode() == ISD::ADD) { 5627 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 5628 Base = Base.getOperand(0); 5629 Offset += C->getZExtValue(); 5630 } 5631 } 5632 5633 // If it's any of the following then it can't alias with anything but itself. 5634 return isa<FrameIndexSDNode>(Base) || 5635 isa<ConstantPoolSDNode>(Base) || 5636 isa<GlobalAddressSDNode>(Base); 5637} 5638 5639/// isAlias - Return true if there is any possibility that the two addresses 5640/// overlap. 5641bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, 5642 const Value *SrcValue1, int SrcValueOffset1, 5643 SDValue Ptr2, int64_t Size2, 5644 const Value *SrcValue2, int SrcValueOffset2) 5645{ 5646 // If they are the same then they must be aliases. 5647 if (Ptr1 == Ptr2) return true; 5648 5649 // Gather base node and offset information. 5650 SDValue Base1, Base2; 5651 int64_t Offset1, Offset2; 5652 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1); 5653 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2); 5654 5655 // If they have a same base address then... 5656 if (Base1 == Base2) { 5657 // Check to see if the addresses overlap. 5658 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 5659 } 5660 5661 // If we know both bases then they can't alias. 5662 if (KnownBase1 && KnownBase2) return false; 5663 5664 if (CombinerGlobalAA) { 5665 // Use alias analysis information. 5666 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 5667 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 5668 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 5669 AliasAnalysis::AliasResult AAResult = 5670 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2); 5671 if (AAResult == AliasAnalysis::NoAlias) 5672 return false; 5673 } 5674 5675 // Otherwise we have to assume they alias. 5676 return true; 5677} 5678 5679/// FindAliasInfo - Extracts the relevant alias information from the memory 5680/// node. Returns true if the operand was a load. 5681bool DAGCombiner::FindAliasInfo(SDNode *N, 5682 SDValue &Ptr, int64_t &Size, 5683 const Value *&SrcValue, int &SrcValueOffset) { 5684 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 5685 Ptr = LD->getBasePtr(); 5686 Size = LD->getMemoryVT().getSizeInBits() >> 3; 5687 SrcValue = LD->getSrcValue(); 5688 SrcValueOffset = LD->getSrcValueOffset(); 5689 return true; 5690 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 5691 Ptr = ST->getBasePtr(); 5692 Size = ST->getMemoryVT().getSizeInBits() >> 3; 5693 SrcValue = ST->getSrcValue(); 5694 SrcValueOffset = ST->getSrcValueOffset(); 5695 } else { 5696 assert(0 && "FindAliasInfo expected a memory operand"); 5697 } 5698 5699 return false; 5700} 5701 5702/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 5703/// looking for aliasing nodes and adding them to the Aliases vector. 5704void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 5705 SmallVector<SDValue, 8> &Aliases) { 5706 SmallVector<SDValue, 8> Chains; // List of chains to visit. 5707 std::set<SDNode *> Visited; // Visited node set. 5708 5709 // Get alias information for node. 5710 SDValue Ptr; 5711 int64_t Size; 5712 const Value *SrcValue; 5713 int SrcValueOffset; 5714 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset); 5715 5716 // Starting off. 5717 Chains.push_back(OriginalChain); 5718 5719 // Look at each chain and determine if it is an alias. If so, add it to the 5720 // aliases list. If not, then continue up the chain looking for the next 5721 // candidate. 5722 while (!Chains.empty()) { 5723 SDValue Chain = Chains.back(); 5724 Chains.pop_back(); 5725 5726 // Don't bother if we've been before. 5727 if (Visited.find(Chain.getNode()) != Visited.end()) continue; 5728 Visited.insert(Chain.getNode()); 5729 5730 switch (Chain.getOpcode()) { 5731 case ISD::EntryToken: 5732 // Entry token is ideal chain operand, but handled in FindBetterChain. 5733 break; 5734 5735 case ISD::LOAD: 5736 case ISD::STORE: { 5737 // Get alias information for Chain. 5738 SDValue OpPtr; 5739 int64_t OpSize; 5740 const Value *OpSrcValue; 5741 int OpSrcValueOffset; 5742 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, 5743 OpSrcValue, OpSrcValueOffset); 5744 5745 // If chain is alias then stop here. 5746 if (!(IsLoad && IsOpLoad) && 5747 isAlias(Ptr, Size, SrcValue, SrcValueOffset, 5748 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) { 5749 Aliases.push_back(Chain); 5750 } else { 5751 // Look further up the chain. 5752 Chains.push_back(Chain.getOperand(0)); 5753 // Clean up old chain. 5754 AddToWorkList(Chain.getNode()); 5755 } 5756 break; 5757 } 5758 5759 case ISD::TokenFactor: 5760 // We have to check each of the operands of the token factor, so we queue 5761 // then up. Adding the operands to the queue (stack) in reverse order 5762 // maintains the original order and increases the likelihood that getNode 5763 // will find a matching token factor (CSE.) 5764 for (unsigned n = Chain.getNumOperands(); n;) 5765 Chains.push_back(Chain.getOperand(--n)); 5766 // Eliminate the token factor if we can. 5767 AddToWorkList(Chain.getNode()); 5768 break; 5769 5770 default: 5771 // For all other instructions we will just have to take what we can get. 5772 Aliases.push_back(Chain); 5773 break; 5774 } 5775 } 5776} 5777 5778/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 5779/// for a better chain (aliasing node.) 5780SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 5781 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 5782 5783 // Accumulate all the aliases to this node. 5784 GatherAllAliases(N, OldChain, Aliases); 5785 5786 if (Aliases.size() == 0) { 5787 // If no operands then chain to entry token. 5788 return DAG.getEntryNode(); 5789 } else if (Aliases.size() == 1) { 5790 // If a single operand then chain to it. We don't need to revisit it. 5791 return Aliases[0]; 5792 } 5793 5794 // Construct a custom tailored token factor. 5795 SDValue NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 5796 &Aliases[0], Aliases.size()); 5797 5798 // Make sure the old chain gets cleaned up. 5799 if (NewChain != OldChain) AddToWorkList(OldChain.getNode()); 5800 5801 return NewChain; 5802} 5803 5804// SelectionDAG::Combine - This is the entry point for the file. 5805// 5806void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, bool Fast) { 5807 /// run - This is the main entry point to this class. 5808 /// 5809 DAGCombiner(*this, AA, Fast).Run(Level); 5810} 5811