DAGCombiner.cpp revision d32a96063395c27fc0ef1cbfa8ae987f3e19ac13
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "dagcombine" 16#include "llvm/CodeGen/SelectionDAG.h" 17#include "llvm/CodeGen/MachineFunction.h" 18#include "llvm/CodeGen/MachineFrameInfo.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Target/TargetData.h" 21#include "llvm/Target/TargetFrameInfo.h" 22#include "llvm/Target/TargetLowering.h" 23#include "llvm/Target/TargetMachine.h" 24#include "llvm/Target/TargetOptions.h" 25#include "llvm/ADT/SmallPtrSet.h" 26#include "llvm/ADT/Statistic.h" 27#include "llvm/Support/Compiler.h" 28#include "llvm/Support/CommandLine.h" 29#include "llvm/Support/Debug.h" 30#include "llvm/Support/MathExtras.h" 31#include <algorithm> 32#include <set> 33using namespace llvm; 34 35STATISTIC(NodesCombined , "Number of dag nodes combined"); 36STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 37STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 38 39namespace { 40 static cl::opt<bool> 41 CombinerAA("combiner-alias-analysis", cl::Hidden, 42 cl::desc("Turn on alias analysis during testing")); 43 44 static cl::opt<bool> 45 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 46 cl::desc("Include global information in alias analysis")); 47 48//------------------------------ DAGCombiner ---------------------------------// 49 50 class VISIBILITY_HIDDEN DAGCombiner { 51 SelectionDAG &DAG; 52 TargetLowering &TLI; 53 CombineLevel Level; 54 bool LegalOperations; 55 bool LegalTypes; 56 bool Fast; 57 58 // Worklist of all of the nodes that need to be simplified. 59 std::vector<SDNode*> WorkList; 60 61 // AA - Used for DAG load/store alias analysis. 62 AliasAnalysis &AA; 63 64 /// AddUsersToWorkList - When an instruction is simplified, add all users of 65 /// the instruction to the work lists because they might get more simplified 66 /// now. 67 /// 68 void AddUsersToWorkList(SDNode *N) { 69 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 70 UI != UE; ++UI) 71 AddToWorkList(*UI); 72 } 73 74 /// visit - call the node-specific routine that knows how to fold each 75 /// particular type of node. 76 SDValue visit(SDNode *N); 77 78 public: 79 /// AddToWorkList - Add to the work list making sure it's instance is at the 80 /// the back (next to be processed.) 81 void AddToWorkList(SDNode *N) { 82 removeFromWorkList(N); 83 WorkList.push_back(N); 84 } 85 86 /// removeFromWorkList - remove all instances of N from the worklist. 87 /// 88 void removeFromWorkList(SDNode *N) { 89 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 90 WorkList.end()); 91 } 92 93 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 94 bool AddTo = true); 95 96 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 97 return CombineTo(N, &Res, 1, AddTo); 98 } 99 100 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 101 bool AddTo = true) { 102 SDValue To[] = { Res0, Res1 }; 103 return CombineTo(N, To, 2, AddTo); 104 } 105 106 private: 107 108 /// SimplifyDemandedBits - Check the specified integer node value to see if 109 /// it can be simplified or if things it uses can be simplified by bit 110 /// propagation. If so, return true. 111 bool SimplifyDemandedBits(SDValue Op) { 112 APInt Demanded = APInt::getAllOnesValue(Op.getValueSizeInBits()); 113 return SimplifyDemandedBits(Op, Demanded); 114 } 115 116 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 117 118 bool CombineToPreIndexedLoadStore(SDNode *N); 119 bool CombineToPostIndexedLoadStore(SDNode *N); 120 121 122 /// combine - call the node-specific routine that knows how to fold each 123 /// particular type of node. If that doesn't do anything, try the 124 /// target-specific DAG combines. 125 SDValue combine(SDNode *N); 126 127 // Visitation implementation - Implement dag node combining for different 128 // node types. The semantics are as follows: 129 // Return Value: 130 // SDValue.getNode() == 0 - No change was made 131 // SDValue.getNode() == N - N was replaced, is dead and has been handled. 132 // otherwise - N should be replaced by the returned Operand. 133 // 134 SDValue visitTokenFactor(SDNode *N); 135 SDValue visitMERGE_VALUES(SDNode *N); 136 SDValue visitADD(SDNode *N); 137 SDValue visitSUB(SDNode *N); 138 SDValue visitADDC(SDNode *N); 139 SDValue visitADDE(SDNode *N); 140 SDValue visitMUL(SDNode *N); 141 SDValue visitSDIV(SDNode *N); 142 SDValue visitUDIV(SDNode *N); 143 SDValue visitSREM(SDNode *N); 144 SDValue visitUREM(SDNode *N); 145 SDValue visitMULHU(SDNode *N); 146 SDValue visitMULHS(SDNode *N); 147 SDValue visitSMUL_LOHI(SDNode *N); 148 SDValue visitUMUL_LOHI(SDNode *N); 149 SDValue visitSDIVREM(SDNode *N); 150 SDValue visitUDIVREM(SDNode *N); 151 SDValue visitAND(SDNode *N); 152 SDValue visitOR(SDNode *N); 153 SDValue visitXOR(SDNode *N); 154 SDValue SimplifyVBinOp(SDNode *N); 155 SDValue visitSHL(SDNode *N); 156 SDValue visitSRA(SDNode *N); 157 SDValue visitSRL(SDNode *N); 158 SDValue visitCTLZ(SDNode *N); 159 SDValue visitCTTZ(SDNode *N); 160 SDValue visitCTPOP(SDNode *N); 161 SDValue visitSELECT(SDNode *N); 162 SDValue visitSELECT_CC(SDNode *N); 163 SDValue visitSETCC(SDNode *N); 164 SDValue visitSIGN_EXTEND(SDNode *N); 165 SDValue visitZERO_EXTEND(SDNode *N); 166 SDValue visitANY_EXTEND(SDNode *N); 167 SDValue visitSIGN_EXTEND_INREG(SDNode *N); 168 SDValue visitTRUNCATE(SDNode *N); 169 SDValue visitBIT_CONVERT(SDNode *N); 170 SDValue visitBUILD_PAIR(SDNode *N); 171 SDValue visitFADD(SDNode *N); 172 SDValue visitFSUB(SDNode *N); 173 SDValue visitFMUL(SDNode *N); 174 SDValue visitFDIV(SDNode *N); 175 SDValue visitFREM(SDNode *N); 176 SDValue visitFCOPYSIGN(SDNode *N); 177 SDValue visitSINT_TO_FP(SDNode *N); 178 SDValue visitUINT_TO_FP(SDNode *N); 179 SDValue visitFP_TO_SINT(SDNode *N); 180 SDValue visitFP_TO_UINT(SDNode *N); 181 SDValue visitFP_ROUND(SDNode *N); 182 SDValue visitFP_ROUND_INREG(SDNode *N); 183 SDValue visitFP_EXTEND(SDNode *N); 184 SDValue visitFNEG(SDNode *N); 185 SDValue visitFABS(SDNode *N); 186 SDValue visitBRCOND(SDNode *N); 187 SDValue visitBR_CC(SDNode *N); 188 SDValue visitLOAD(SDNode *N); 189 SDValue visitSTORE(SDNode *N); 190 SDValue visitINSERT_VECTOR_ELT(SDNode *N); 191 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 192 SDValue visitBUILD_VECTOR(SDNode *N); 193 SDValue visitCONCAT_VECTORS(SDNode *N); 194 SDValue visitVECTOR_SHUFFLE(SDNode *N); 195 196 SDValue XformToShuffleWithZero(SDNode *N); 197 SDValue ReassociateOps(unsigned Opc, SDValue LHS, SDValue RHS); 198 199 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 200 201 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 202 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 203 SDValue SimplifySelect(SDValue N0, SDValue N1, SDValue N2); 204 SDValue SimplifySelectCC(SDValue N0, SDValue N1, SDValue N2, 205 SDValue N3, ISD::CondCode CC, 206 bool NotExtCompare = false); 207 SDValue SimplifySetCC(MVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 208 bool foldBooleans = true); 209 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 210 unsigned HiOp); 211 SDValue CombineConsecutiveLoads(SDNode *N, MVT VT); 212 SDValue ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT); 213 SDValue BuildSDIV(SDNode *N); 214 SDValue BuildUDIV(SDNode *N); 215 SDNode *MatchRotate(SDValue LHS, SDValue RHS); 216 SDValue ReduceLoadWidth(SDNode *N); 217 218 SDValue GetDemandedBits(SDValue V, const APInt &Mask); 219 220 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 221 /// looking for aliasing nodes and adding them to the Aliases vector. 222 void GatherAllAliases(SDNode *N, SDValue OriginalChain, 223 SmallVector<SDValue, 8> &Aliases); 224 225 /// isAlias - Return true if there is any possibility that the two addresses 226 /// overlap. 227 bool isAlias(SDValue Ptr1, int64_t Size1, 228 const Value *SrcValue1, int SrcValueOffset1, 229 SDValue Ptr2, int64_t Size2, 230 const Value *SrcValue2, int SrcValueOffset2); 231 232 /// FindAliasInfo - Extracts the relevant alias information from the memory 233 /// node. Returns true if the operand was a load. 234 bool FindAliasInfo(SDNode *N, 235 SDValue &Ptr, int64_t &Size, 236 const Value *&SrcValue, int &SrcValueOffset); 237 238 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 239 /// looking for a better chain (aliasing node.) 240 SDValue FindBetterChain(SDNode *N, SDValue Chain); 241 242public: 243 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, bool fast) 244 : DAG(D), 245 TLI(D.getTargetLoweringInfo()), 246 Level(Unrestricted), 247 LegalOperations(false), 248 LegalTypes(false), 249 Fast(fast), 250 AA(A) {} 251 252 /// Run - runs the dag combiner on all nodes in the work list 253 void Run(CombineLevel AtLevel); 254 }; 255} 256 257 258namespace { 259/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 260/// nodes from the worklist. 261class VISIBILITY_HIDDEN WorkListRemover : 262 public SelectionDAG::DAGUpdateListener { 263 DAGCombiner &DC; 264public: 265 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {} 266 267 virtual void NodeDeleted(SDNode *N, SDNode *E) { 268 DC.removeFromWorkList(N); 269 } 270 271 virtual void NodeUpdated(SDNode *N) { 272 // Ignore updates. 273 } 274}; 275} 276 277//===----------------------------------------------------------------------===// 278// TargetLowering::DAGCombinerInfo implementation 279//===----------------------------------------------------------------------===// 280 281void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 282 ((DAGCombiner*)DC)->AddToWorkList(N); 283} 284 285SDValue TargetLowering::DAGCombinerInfo:: 286CombineTo(SDNode *N, const std::vector<SDValue> &To) { 287 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size()); 288} 289 290SDValue TargetLowering::DAGCombinerInfo:: 291CombineTo(SDNode *N, SDValue Res) { 292 return ((DAGCombiner*)DC)->CombineTo(N, Res); 293} 294 295 296SDValue TargetLowering::DAGCombinerInfo:: 297CombineTo(SDNode *N, SDValue Res0, SDValue Res1) { 298 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1); 299} 300 301 302//===----------------------------------------------------------------------===// 303// Helper Functions 304//===----------------------------------------------------------------------===// 305 306/// isNegatibleForFree - Return 1 if we can compute the negated form of the 307/// specified expression for the same cost as the expression itself, or 2 if we 308/// can compute the negated form more cheaply than the expression itself. 309static char isNegatibleForFree(SDValue Op, bool LegalOperations, 310 unsigned Depth = 0) { 311 // No compile time optimizations on this type. 312 if (Op.getValueType() == MVT::ppcf128) 313 return 0; 314 315 // fneg is removable even if it has multiple uses. 316 if (Op.getOpcode() == ISD::FNEG) return 2; 317 318 // Don't allow anything with multiple uses. 319 if (!Op.hasOneUse()) return 0; 320 321 // Don't recurse exponentially. 322 if (Depth > 6) return 0; 323 324 switch (Op.getOpcode()) { 325 default: return false; 326 case ISD::ConstantFP: 327 // Don't invert constant FP values after legalize. The negated constant 328 // isn't necessarily legal. 329 return LegalOperations ? 0 : 1; 330 case ISD::FADD: 331 // FIXME: determine better conditions for this xform. 332 if (!UnsafeFPMath) return 0; 333 334 // -(A+B) -> -A - B 335 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 336 return V; 337 // -(A+B) -> -B - A 338 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 339 case ISD::FSUB: 340 // We can't turn -(A-B) into B-A when we honor signed zeros. 341 if (!UnsafeFPMath) return 0; 342 343 // -(A-B) -> B-A 344 return 1; 345 346 case ISD::FMUL: 347 case ISD::FDIV: 348 if (HonorSignDependentRoundingFPMath()) return 0; 349 350 // -(X*Y) -> (-X * Y) or (X*-Y) 351 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 352 return V; 353 354 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 355 356 case ISD::FP_EXTEND: 357 case ISD::FP_ROUND: 358 case ISD::FSIN: 359 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1); 360 } 361} 362 363/// GetNegatedExpression - If isNegatibleForFree returns true, this function 364/// returns the newly negated expression. 365static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 366 bool LegalOperations, unsigned Depth = 0) { 367 // fneg is removable even if it has multiple uses. 368 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 369 370 // Don't allow anything with multiple uses. 371 assert(Op.hasOneUse() && "Unknown reuse!"); 372 373 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 374 switch (Op.getOpcode()) { 375 default: assert(0 && "Unknown code"); 376 case ISD::ConstantFP: { 377 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 378 V.changeSign(); 379 return DAG.getConstantFP(V, Op.getValueType()); 380 } 381 case ISD::FADD: 382 // FIXME: determine better conditions for this xform. 383 assert(UnsafeFPMath); 384 385 // -(A+B) -> -A - B 386 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 387 return DAG.getNode(ISD::FSUB, Op.getValueType(), 388 GetNegatedExpression(Op.getOperand(0), DAG, 389 LegalOperations, Depth+1), 390 Op.getOperand(1)); 391 // -(A+B) -> -B - A 392 return DAG.getNode(ISD::FSUB, Op.getValueType(), 393 GetNegatedExpression(Op.getOperand(1), DAG, 394 LegalOperations, Depth+1), 395 Op.getOperand(0)); 396 case ISD::FSUB: 397 // We can't turn -(A-B) into B-A when we honor signed zeros. 398 assert(UnsafeFPMath); 399 400 // -(0-B) -> B 401 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 402 if (N0CFP->getValueAPF().isZero()) 403 return Op.getOperand(1); 404 405 // -(A-B) -> B-A 406 return DAG.getNode(ISD::FSUB, Op.getValueType(), Op.getOperand(1), 407 Op.getOperand(0)); 408 409 case ISD::FMUL: 410 case ISD::FDIV: 411 assert(!HonorSignDependentRoundingFPMath()); 412 413 // -(X*Y) -> -X * Y 414 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 415 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 416 GetNegatedExpression(Op.getOperand(0), DAG, 417 LegalOperations, Depth+1), 418 Op.getOperand(1)); 419 420 // -(X*Y) -> X * -Y 421 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 422 Op.getOperand(0), 423 GetNegatedExpression(Op.getOperand(1), DAG, 424 LegalOperations, Depth+1)); 425 426 case ISD::FP_EXTEND: 427 case ISD::FSIN: 428 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 429 GetNegatedExpression(Op.getOperand(0), DAG, 430 LegalOperations, Depth+1)); 431 case ISD::FP_ROUND: 432 return DAG.getNode(ISD::FP_ROUND, Op.getValueType(), 433 GetNegatedExpression(Op.getOperand(0), DAG, 434 LegalOperations, Depth+1), 435 Op.getOperand(1)); 436 } 437} 438 439 440// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 441// that selects between the values 1 and 0, making it equivalent to a setcc. 442// Also, set the incoming LHS, RHS, and CC references to the appropriate 443// nodes based on the type of node we are checking. This simplifies life a 444// bit for the callers. 445static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 446 SDValue &CC) { 447 if (N.getOpcode() == ISD::SETCC) { 448 LHS = N.getOperand(0); 449 RHS = N.getOperand(1); 450 CC = N.getOperand(2); 451 return true; 452 } 453 if (N.getOpcode() == ISD::SELECT_CC && 454 N.getOperand(2).getOpcode() == ISD::Constant && 455 N.getOperand(3).getOpcode() == ISD::Constant && 456 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 457 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 458 LHS = N.getOperand(0); 459 RHS = N.getOperand(1); 460 CC = N.getOperand(4); 461 return true; 462 } 463 return false; 464} 465 466// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 467// one use. If this is true, it allows the users to invert the operation for 468// free when it is profitable to do so. 469static bool isOneUseSetCC(SDValue N) { 470 SDValue N0, N1, N2; 471 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 472 return true; 473 return false; 474} 475 476SDValue DAGCombiner::ReassociateOps(unsigned Opc, SDValue N0, SDValue N1){ 477 MVT VT = N0.getValueType(); 478 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 479 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 480 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 481 if (isa<ConstantSDNode>(N1)) { 482 SDValue OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1); 483 AddToWorkList(OpNode.getNode()); 484 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0)); 485 } else if (N0.hasOneUse()) { 486 SDValue OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1); 487 AddToWorkList(OpNode.getNode()); 488 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1)); 489 } 490 } 491 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 492 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 493 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 494 if (isa<ConstantSDNode>(N0)) { 495 SDValue OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0); 496 AddToWorkList(OpNode.getNode()); 497 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0)); 498 } else if (N1.hasOneUse()) { 499 SDValue OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0); 500 AddToWorkList(OpNode.getNode()); 501 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1)); 502 } 503 } 504 return SDValue(); 505} 506 507SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 508 bool AddTo) { 509 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 510 ++NodesCombined; 511 DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG)); 512 DOUT << "\nWith: "; DEBUG(To[0].getNode()->dump(&DAG)); 513 DOUT << " and " << NumTo-1 << " other values\n"; 514 WorkListRemover DeadNodes(*this); 515 DAG.ReplaceAllUsesWith(N, To, &DeadNodes); 516 517 if (AddTo) { 518 // Push the new nodes and any users onto the worklist 519 for (unsigned i = 0, e = NumTo; i != e; ++i) { 520 AddToWorkList(To[i].getNode()); 521 AddUsersToWorkList(To[i].getNode()); 522 } 523 } 524 525 // Nodes can be reintroduced into the worklist. Make sure we do not 526 // process a node that has been replaced. 527 removeFromWorkList(N); 528 529 // Finally, since the node is now dead, remove it from the graph. 530 DAG.DeleteNode(N); 531 return SDValue(N, 0); 532} 533 534/// SimplifyDemandedBits - Check the specified integer node value to see if 535/// it can be simplified or if things it uses can be simplified by bit 536/// propagation. If so, return true. 537bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 538 TargetLowering::TargetLoweringOpt TLO(DAG); 539 APInt KnownZero, KnownOne; 540 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 541 return false; 542 543 // Revisit the node. 544 AddToWorkList(Op.getNode()); 545 546 // Replace the old value with the new one. 547 ++NodesCombined; 548 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.getNode()->dump(&DAG)); 549 DOUT << "\nWith: "; DEBUG(TLO.New.getNode()->dump(&DAG)); 550 DOUT << '\n'; 551 552 // Replace all uses. If any nodes become isomorphic to other nodes and 553 // are deleted, make sure to remove them from our worklist. 554 WorkListRemover DeadNodes(*this); 555 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 556 557 // Push the new node and any (possibly new) users onto the worklist. 558 AddToWorkList(TLO.New.getNode()); 559 AddUsersToWorkList(TLO.New.getNode()); 560 561 // Finally, if the node is now dead, remove it from the graph. The node 562 // may not be dead if the replacement process recursively simplified to 563 // something else needing this node. 564 if (TLO.Old.getNode()->use_empty()) { 565 removeFromWorkList(TLO.Old.getNode()); 566 567 // If the operands of this node are only used by the node, they will now 568 // be dead. Make sure to visit them first to delete dead nodes early. 569 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i) 570 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse()) 571 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode()); 572 573 DAG.DeleteNode(TLO.Old.getNode()); 574 } 575 return true; 576} 577 578//===----------------------------------------------------------------------===// 579// Main DAG Combiner implementation 580//===----------------------------------------------------------------------===// 581 582void DAGCombiner::Run(CombineLevel AtLevel) { 583 // set the instance variables, so that the various visit routines may use it. 584 Level = AtLevel; 585 LegalOperations = Level >= NoIllegalOperations; 586 LegalTypes = Level >= NoIllegalTypes; 587 588 // Add all the dag nodes to the worklist. 589 WorkList.reserve(DAG.allnodes_size()); 590 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 591 E = DAG.allnodes_end(); I != E; ++I) 592 WorkList.push_back(I); 593 594 // Create a dummy node (which is not added to allnodes), that adds a reference 595 // to the root node, preventing it from being deleted, and tracking any 596 // changes of the root. 597 HandleSDNode Dummy(DAG.getRoot()); 598 599 // The root of the dag may dangle to deleted nodes until the dag combiner is 600 // done. Set it to null to avoid confusion. 601 DAG.setRoot(SDValue()); 602 603 // while the worklist isn't empty, inspect the node on the end of it and 604 // try and combine it. 605 while (!WorkList.empty()) { 606 SDNode *N = WorkList.back(); 607 WorkList.pop_back(); 608 609 // If N has no uses, it is dead. Make sure to revisit all N's operands once 610 // N is deleted from the DAG, since they too may now be dead or may have a 611 // reduced number of uses, allowing other xforms. 612 if (N->use_empty() && N != &Dummy) { 613 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 614 AddToWorkList(N->getOperand(i).getNode()); 615 616 DAG.DeleteNode(N); 617 continue; 618 } 619 620 SDValue RV = combine(N); 621 622 if (RV.getNode() == 0) 623 continue; 624 625 ++NodesCombined; 626 627 // If we get back the same node we passed in, rather than a new node or 628 // zero, we know that the node must have defined multiple values and 629 // CombineTo was used. Since CombineTo takes care of the worklist 630 // mechanics for us, we have no work to do in this case. 631 if (RV.getNode() == N) 632 continue; 633 634 assert(N->getOpcode() != ISD::DELETED_NODE && 635 RV.getNode()->getOpcode() != ISD::DELETED_NODE && 636 "Node was deleted but visit returned new node!"); 637 638 DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG)); 639 DOUT << "\nWith: "; DEBUG(RV.getNode()->dump(&DAG)); 640 DOUT << '\n'; 641 WorkListRemover DeadNodes(*this); 642 if (N->getNumValues() == RV.getNode()->getNumValues()) 643 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes); 644 else { 645 assert(N->getValueType(0) == RV.getValueType() && 646 N->getNumValues() == 1 && "Type mismatch"); 647 SDValue OpV = RV; 648 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes); 649 } 650 651 // Push the new node and any users onto the worklist 652 AddToWorkList(RV.getNode()); 653 AddUsersToWorkList(RV.getNode()); 654 655 // Add any uses of the old node to the worklist in case this node is the 656 // last one that uses them. They may become dead after this node is 657 // deleted. 658 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 659 AddToWorkList(N->getOperand(i).getNode()); 660 661 // Nodes can be reintroduced into the worklist. Make sure we do not 662 // process a node that has been replaced. 663 removeFromWorkList(N); 664 665 // Finally, since the node is now dead, remove it from the graph. 666 DAG.DeleteNode(N); 667 } 668 669 // If the root changed (e.g. it was a dead load, update the root). 670 DAG.setRoot(Dummy.getValue()); 671} 672 673SDValue DAGCombiner::visit(SDNode *N) { 674 switch(N->getOpcode()) { 675 default: break; 676 case ISD::TokenFactor: return visitTokenFactor(N); 677 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 678 case ISD::ADD: return visitADD(N); 679 case ISD::SUB: return visitSUB(N); 680 case ISD::ADDC: return visitADDC(N); 681 case ISD::ADDE: return visitADDE(N); 682 case ISD::MUL: return visitMUL(N); 683 case ISD::SDIV: return visitSDIV(N); 684 case ISD::UDIV: return visitUDIV(N); 685 case ISD::SREM: return visitSREM(N); 686 case ISD::UREM: return visitUREM(N); 687 case ISD::MULHU: return visitMULHU(N); 688 case ISD::MULHS: return visitMULHS(N); 689 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 690 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 691 case ISD::SDIVREM: return visitSDIVREM(N); 692 case ISD::UDIVREM: return visitUDIVREM(N); 693 case ISD::AND: return visitAND(N); 694 case ISD::OR: return visitOR(N); 695 case ISD::XOR: return visitXOR(N); 696 case ISD::SHL: return visitSHL(N); 697 case ISD::SRA: return visitSRA(N); 698 case ISD::SRL: return visitSRL(N); 699 case ISD::CTLZ: return visitCTLZ(N); 700 case ISD::CTTZ: return visitCTTZ(N); 701 case ISD::CTPOP: return visitCTPOP(N); 702 case ISD::SELECT: return visitSELECT(N); 703 case ISD::SELECT_CC: return visitSELECT_CC(N); 704 case ISD::SETCC: return visitSETCC(N); 705 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 706 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 707 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 708 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 709 case ISD::TRUNCATE: return visitTRUNCATE(N); 710 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 711 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 712 case ISD::FADD: return visitFADD(N); 713 case ISD::FSUB: return visitFSUB(N); 714 case ISD::FMUL: return visitFMUL(N); 715 case ISD::FDIV: return visitFDIV(N); 716 case ISD::FREM: return visitFREM(N); 717 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 718 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 719 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 720 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 721 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 722 case ISD::FP_ROUND: return visitFP_ROUND(N); 723 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 724 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 725 case ISD::FNEG: return visitFNEG(N); 726 case ISD::FABS: return visitFABS(N); 727 case ISD::BRCOND: return visitBRCOND(N); 728 case ISD::BR_CC: return visitBR_CC(N); 729 case ISD::LOAD: return visitLOAD(N); 730 case ISD::STORE: return visitSTORE(N); 731 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 732 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 733 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 734 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 735 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 736 } 737 return SDValue(); 738} 739 740SDValue DAGCombiner::combine(SDNode *N) { 741 742 SDValue RV = visit(N); 743 744 // If nothing happened, try a target-specific DAG combine. 745 if (RV.getNode() == 0) { 746 assert(N->getOpcode() != ISD::DELETED_NODE && 747 "Node was deleted but visit returned NULL!"); 748 749 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 750 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 751 752 // Expose the DAG combiner to the target combiner impls. 753 TargetLowering::DAGCombinerInfo 754 DagCombineInfo(DAG, Level == Unrestricted, false, this); 755 756 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 757 } 758 } 759 760 // If N is a commutative binary node, try commuting it to enable more 761 // sdisel CSE. 762 if (RV.getNode() == 0 && 763 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 764 N->getNumValues() == 1) { 765 SDValue N0 = N->getOperand(0); 766 SDValue N1 = N->getOperand(1); 767 // Constant operands are canonicalized to RHS. 768 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 769 SDValue Ops[] = { N1, N0 }; 770 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 771 Ops, 2); 772 if (CSENode) 773 return SDValue(CSENode, 0); 774 } 775 } 776 777 return RV; 778} 779 780/// getInputChainForNode - Given a node, return its input chain if it has one, 781/// otherwise return a null sd operand. 782static SDValue getInputChainForNode(SDNode *N) { 783 if (unsigned NumOps = N->getNumOperands()) { 784 if (N->getOperand(0).getValueType() == MVT::Other) 785 return N->getOperand(0); 786 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 787 return N->getOperand(NumOps-1); 788 for (unsigned i = 1; i < NumOps-1; ++i) 789 if (N->getOperand(i).getValueType() == MVT::Other) 790 return N->getOperand(i); 791 } 792 return SDValue(0, 0); 793} 794 795SDValue DAGCombiner::visitTokenFactor(SDNode *N) { 796 // If N has two operands, where one has an input chain equal to the other, 797 // the 'other' chain is redundant. 798 if (N->getNumOperands() == 2) { 799 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) 800 return N->getOperand(0); 801 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) 802 return N->getOperand(1); 803 } 804 805 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 806 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 807 SmallPtrSet<SDNode*, 16> SeenOps; 808 bool Changed = false; // If we should replace this token factor. 809 810 // Start out with this token factor. 811 TFs.push_back(N); 812 813 // Iterate through token factors. The TFs grows when new token factors are 814 // encountered. 815 for (unsigned i = 0; i < TFs.size(); ++i) { 816 SDNode *TF = TFs[i]; 817 818 // Check each of the operands. 819 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 820 SDValue Op = TF->getOperand(i); 821 822 switch (Op.getOpcode()) { 823 case ISD::EntryToken: 824 // Entry tokens don't need to be added to the list. They are 825 // rededundant. 826 Changed = true; 827 break; 828 829 case ISD::TokenFactor: 830 if ((CombinerAA || Op.hasOneUse()) && 831 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { 832 // Queue up for processing. 833 TFs.push_back(Op.getNode()); 834 // Clean up in case the token factor is removed. 835 AddToWorkList(Op.getNode()); 836 Changed = true; 837 break; 838 } 839 // Fall thru 840 841 default: 842 // Only add if it isn't already in the list. 843 if (SeenOps.insert(Op.getNode())) 844 Ops.push_back(Op); 845 else 846 Changed = true; 847 break; 848 } 849 } 850 } 851 852 SDValue Result; 853 854 // If we've change things around then replace token factor. 855 if (Changed) { 856 if (Ops.empty()) { 857 // The entry token is the only possible outcome. 858 Result = DAG.getEntryNode(); 859 } else { 860 // New and improved token factor. 861 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size()); 862 } 863 864 // Don't add users to work list. 865 return CombineTo(N, Result, false); 866 } 867 868 return Result; 869} 870 871/// MERGE_VALUES can always be eliminated. 872SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 873 WorkListRemover DeadNodes(*this); 874 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 875 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i), 876 &DeadNodes); 877 removeFromWorkList(N); 878 DAG.DeleteNode(N); 879 return SDValue(N, 0); // Return N so it doesn't get rechecked! 880} 881 882 883static 884SDValue combineShlAddConstant(SDValue N0, SDValue N1, SelectionDAG &DAG) { 885 MVT VT = N0.getValueType(); 886 SDValue N00 = N0.getOperand(0); 887 SDValue N01 = N0.getOperand(1); 888 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 889 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && 890 isa<ConstantSDNode>(N00.getOperand(1))) { 891 N0 = DAG.getNode(ISD::ADD, VT, 892 DAG.getNode(ISD::SHL, VT, N00.getOperand(0), N01), 893 DAG.getNode(ISD::SHL, VT, N00.getOperand(1), N01)); 894 return DAG.getNode(ISD::ADD, VT, N0, N1); 895 } 896 return SDValue(); 897} 898 899static 900SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp, 901 SelectionDAG &DAG, const TargetLowering &TLI, 902 bool LegalOperations) { 903 MVT VT = N->getValueType(0); 904 unsigned Opc = N->getOpcode(); 905 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC; 906 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1); 907 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2); 908 ISD::CondCode CC = ISD::SETCC_INVALID; 909 910 if (isSlctCC) { 911 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get(); 912 } else { 913 SDValue CCOp = Slct.getOperand(0); 914 if (CCOp.getOpcode() == ISD::SETCC) 915 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get(); 916 } 917 918 bool DoXform = false; 919 bool InvCC = false; 920 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) && 921 "Bad input!"); 922 923 if (LHS.getOpcode() == ISD::Constant && 924 cast<ConstantSDNode>(LHS)->isNullValue()) { 925 DoXform = true; 926 } else if (CC != ISD::SETCC_INVALID && 927 RHS.getOpcode() == ISD::Constant && 928 cast<ConstantSDNode>(RHS)->isNullValue()) { 929 std::swap(LHS, RHS); 930 SDValue Op0 = Slct.getOperand(0); 931 MVT OpVT = isSlctCC ? Op0.getValueType() : 932 Op0.getOperand(0).getValueType(); 933 bool isInt = OpVT.isInteger(); 934 CC = ISD::getSetCCInverse(CC, isInt); 935 936 if (LegalOperations && !TLI.isCondCodeLegal(CC, OpVT)) 937 return SDValue(); // Inverse operator isn't legal. 938 939 DoXform = true; 940 InvCC = true; 941 } 942 943 if (DoXform) { 944 SDValue Result = DAG.getNode(Opc, VT, OtherOp, RHS); 945 if (isSlctCC) 946 return DAG.getSelectCC(OtherOp, Result, 947 Slct.getOperand(0), Slct.getOperand(1), CC); 948 SDValue CCOp = Slct.getOperand(0); 949 if (InvCC) 950 CCOp = DAG.getSetCC(CCOp.getValueType(), CCOp.getOperand(0), 951 CCOp.getOperand(1), CC); 952 return DAG.getNode(ISD::SELECT, VT, CCOp, OtherOp, Result); 953 } 954 return SDValue(); 955} 956 957SDValue DAGCombiner::visitADD(SDNode *N) { 958 SDValue N0 = N->getOperand(0); 959 SDValue N1 = N->getOperand(1); 960 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 961 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 962 MVT VT = N0.getValueType(); 963 964 // fold vector ops 965 if (VT.isVector()) { 966 SDValue FoldedVOp = SimplifyVBinOp(N); 967 if (FoldedVOp.getNode()) return FoldedVOp; 968 } 969 970 // fold (add x, undef) -> undef 971 if (N0.getOpcode() == ISD::UNDEF) 972 return N0; 973 if (N1.getOpcode() == ISD::UNDEF) 974 return N1; 975 // fold (add c1, c2) -> c1+c2 976 if (N0C && N1C) 977 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C); 978 // canonicalize constant to RHS 979 if (N0C && !N1C) 980 return DAG.getNode(ISD::ADD, VT, N1, N0); 981 // fold (add x, 0) -> x 982 if (N1C && N1C->isNullValue()) 983 return N0; 984 // fold (add Sym, c) -> Sym+c 985 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 986 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C && 987 GA->getOpcode() == ISD::GlobalAddress) 988 return DAG.getGlobalAddress(GA->getGlobal(), VT, 989 GA->getOffset() + 990 (uint64_t)N1C->getSExtValue()); 991 // fold ((c1-A)+c2) -> (c1+c2)-A 992 if (N1C && N0.getOpcode() == ISD::SUB) 993 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 994 return DAG.getNode(ISD::SUB, VT, 995 DAG.getConstant(N1C->getAPIntValue()+ 996 N0C->getAPIntValue(), VT), 997 N0.getOperand(1)); 998 // reassociate add 999 SDValue RADD = ReassociateOps(ISD::ADD, N0, N1); 1000 if (RADD.getNode() != 0) 1001 return RADD; 1002 // fold ((0-A) + B) -> B-A 1003 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 1004 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 1005 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1)); 1006 // fold (A + (0-B)) -> A-B 1007 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1008 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 1009 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1)); 1010 // fold (A+(B-A)) -> B 1011 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 1012 return N1.getOperand(0); 1013 // fold ((B-A)+A) -> B 1014 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) 1015 return N0.getOperand(0); 1016 // fold (A+(B-(A+C))) to (B-C) 1017 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1018 N0 == N1.getOperand(1).getOperand(0)) { 1019 return DAG.getNode(ISD::SUB, VT, N1.getOperand(0), 1020 N1.getOperand(1).getOperand(1)); 1021 } 1022 // fold (A+(B-(C+A))) to (B-C) 1023 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1024 N0 == N1.getOperand(1).getOperand(1)) { 1025 return DAG.getNode(ISD::SUB, VT, N1.getOperand(0), 1026 N1.getOperand(1).getOperand(0)); 1027 } 1028 // fold (A+((B-A)+or-C)) to (B+or-C) 1029 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && 1030 N1.getOperand(0).getOpcode() == ISD::SUB && 1031 N0 == N1.getOperand(0).getOperand(1)) { 1032 return DAG.getNode(N1.getOpcode(), VT, N1.getOperand(0).getOperand(0), 1033 N1.getOperand(1)); 1034 } 1035 1036 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant 1037 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) { 1038 SDValue N00 = N0.getOperand(0); 1039 SDValue N01 = N0.getOperand(1); 1040 SDValue N10 = N1.getOperand(0); 1041 SDValue N11 = N1.getOperand(1); 1042 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10)) { 1043 return DAG.getNode(ISD::SUB, VT, 1044 DAG.getNode(ISD::ADD, VT, N00, N10), 1045 DAG.getNode(ISD::ADD, VT, N01, N11)); 1046 } 1047 } 1048 1049 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 1050 return SDValue(N, 0); 1051 1052 // fold (a+b) -> (a|b) iff a and b share no bits. 1053 if (VT.isInteger() && !VT.isVector()) { 1054 APInt LHSZero, LHSOne; 1055 APInt RHSZero, RHSOne; 1056 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 1057 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1058 if (LHSZero.getBoolValue()) { 1059 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1060 1061 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1062 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1063 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1064 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1065 return DAG.getNode(ISD::OR, VT, N0, N1); 1066 } 1067 } 1068 1069 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1070 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1071 SDValue Result = combineShlAddConstant(N0, N1, DAG); 1072 if (Result.getNode()) return Result; 1073 } 1074 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1075 SDValue Result = combineShlAddConstant(N1, N0, DAG); 1076 if (Result.getNode()) return Result; 1077 } 1078 1079 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c)) 1080 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) { 1081 SDValue Result = combineSelectAndUse(N, N0, N1, DAG, TLI, LegalOperations); 1082 if (Result.getNode()) return Result; 1083 } 1084 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) { 1085 SDValue Result = combineSelectAndUse(N, N1, N0, DAG, TLI, LegalOperations); 1086 if (Result.getNode()) return Result; 1087 } 1088 1089 return SDValue(); 1090} 1091 1092SDValue DAGCombiner::visitADDC(SDNode *N) { 1093 SDValue N0 = N->getOperand(0); 1094 SDValue N1 = N->getOperand(1); 1095 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1096 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1097 MVT VT = N0.getValueType(); 1098 1099 // If the flag result is dead, turn this into an ADD. 1100 if (N->hasNUsesOfValue(0, 1)) 1101 return CombineTo(N, DAG.getNode(ISD::ADD, VT, N1, N0), 1102 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 1103 1104 // canonicalize constant to RHS. 1105 if (N0C && !N1C) 1106 return DAG.getNode(ISD::ADDC, N->getVTList(), N1, N0); 1107 1108 // fold (addc x, 0) -> x + no carry out 1109 if (N1C && N1C->isNullValue()) 1110 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 1111 1112 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1113 APInt LHSZero, LHSOne; 1114 APInt RHSZero, RHSOne; 1115 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 1116 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1117 if (LHSZero.getBoolValue()) { 1118 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1119 1120 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1121 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1122 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1123 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1124 return CombineTo(N, DAG.getNode(ISD::OR, VT, N0, N1), 1125 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 1126 } 1127 1128 return SDValue(); 1129} 1130 1131SDValue DAGCombiner::visitADDE(SDNode *N) { 1132 SDValue N0 = N->getOperand(0); 1133 SDValue N1 = N->getOperand(1); 1134 SDValue CarryIn = N->getOperand(2); 1135 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1136 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1137 //MVT VT = N0.getValueType(); 1138 1139 // canonicalize constant to RHS 1140 if (N0C && !N1C) 1141 return DAG.getNode(ISD::ADDE, N->getVTList(), N1, N0, CarryIn); 1142 1143 // fold (adde x, y, false) -> (addc x, y) 1144 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1145 return DAG.getNode(ISD::ADDC, N->getVTList(), N1, N0); 1146 1147 return SDValue(); 1148} 1149 1150 1151 1152SDValue DAGCombiner::visitSUB(SDNode *N) { 1153 SDValue N0 = N->getOperand(0); 1154 SDValue N1 = N->getOperand(1); 1155 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1156 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1157 MVT VT = N0.getValueType(); 1158 1159 // fold vector ops 1160 if (VT.isVector()) { 1161 SDValue FoldedVOp = SimplifyVBinOp(N); 1162 if (FoldedVOp.getNode()) return FoldedVOp; 1163 } 1164 1165 // fold (sub x, x) -> 0 1166 if (N0 == N1) 1167 return DAG.getConstant(0, N->getValueType(0)); 1168 // fold (sub c1, c2) -> c1-c2 1169 if (N0C && N1C) 1170 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C); 1171 // fold (sub x, c) -> (add x, -c) 1172 if (N1C) 1173 return DAG.getNode(ISD::ADD, VT, N0, 1174 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1175 // fold (A+B)-A -> B 1176 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1177 return N0.getOperand(1); 1178 // fold (A+B)-B -> A 1179 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1180 return N0.getOperand(0); 1181 // fold ((A+(B+or-C))-B) -> A+or-C 1182 if (N0.getOpcode() == ISD::ADD && 1183 (N0.getOperand(1).getOpcode() == ISD::SUB || 1184 N0.getOperand(1).getOpcode() == ISD::ADD) && 1185 N0.getOperand(1).getOperand(0) == N1) 1186 return DAG.getNode(N0.getOperand(1).getOpcode(), VT, N0.getOperand(0), 1187 N0.getOperand(1).getOperand(1)); 1188 // fold ((A+(C+B))-B) -> A+C 1189 if (N0.getOpcode() == ISD::ADD && 1190 N0.getOperand(1).getOpcode() == ISD::ADD && 1191 N0.getOperand(1).getOperand(1) == N1) 1192 return DAG.getNode(ISD::ADD, VT, N0.getOperand(0), 1193 N0.getOperand(1).getOperand(0)); 1194 // fold ((A-(B-C))-C) -> A-B 1195 if (N0.getOpcode() == ISD::SUB && 1196 N0.getOperand(1).getOpcode() == ISD::SUB && 1197 N0.getOperand(1).getOperand(1) == N1) 1198 return DAG.getNode(ISD::SUB, VT, N0.getOperand(0), 1199 N0.getOperand(1).getOperand(0)); 1200 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c)) 1201 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) { 1202 SDValue Result = combineSelectAndUse(N, N1, N0, DAG, TLI, LegalOperations); 1203 if (Result.getNode()) return Result; 1204 } 1205 // If either operand of a sub is undef, the result is undef 1206 if (N0.getOpcode() == ISD::UNDEF) 1207 return N0; 1208 if (N1.getOpcode() == ISD::UNDEF) 1209 return N1; 1210 1211 // If the relocation model supports it, consider symbol offsets. 1212 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1213 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) { 1214 // fold (sub Sym, c) -> Sym-c 1215 if (N1C && GA->getOpcode() == ISD::GlobalAddress) 1216 return DAG.getGlobalAddress(GA->getGlobal(), VT, 1217 GA->getOffset() - 1218 (uint64_t)N1C->getSExtValue()); 1219 // fold (sub Sym+c1, Sym+c2) -> c1-c2 1220 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1)) 1221 if (GA->getGlobal() == GB->getGlobal()) 1222 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(), 1223 VT); 1224 } 1225 1226 return SDValue(); 1227} 1228 1229SDValue DAGCombiner::visitMUL(SDNode *N) { 1230 SDValue N0 = N->getOperand(0); 1231 SDValue N1 = N->getOperand(1); 1232 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1233 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1234 MVT VT = N0.getValueType(); 1235 1236 // fold vector ops 1237 if (VT.isVector()) { 1238 SDValue FoldedVOp = SimplifyVBinOp(N); 1239 if (FoldedVOp.getNode()) return FoldedVOp; 1240 } 1241 1242 // fold (mul x, undef) -> 0 1243 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1244 return DAG.getConstant(0, VT); 1245 // fold (mul c1, c2) -> c1*c2 1246 if (N0C && N1C) 1247 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C); 1248 // canonicalize constant to RHS 1249 if (N0C && !N1C) 1250 return DAG.getNode(ISD::MUL, VT, N1, N0); 1251 // fold (mul x, 0) -> 0 1252 if (N1C && N1C->isNullValue()) 1253 return N1; 1254 // fold (mul x, -1) -> 0-x 1255 if (N1C && N1C->isAllOnesValue()) 1256 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 1257 // fold (mul x, (1 << c)) -> x << c 1258 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1259 return DAG.getNode(ISD::SHL, VT, N0, 1260 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1261 TLI.getShiftAmountTy())); 1262 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1263 if (N1C && isPowerOf2_64(-N1C->getSExtValue())) { 1264 // FIXME: If the input is something that is easily negated (e.g. a 1265 // single-use add), we should put the negate there. 1266 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), 1267 DAG.getNode(ISD::SHL, VT, N0, 1268 DAG.getConstant(Log2_64(-N1C->getSExtValue()), 1269 TLI.getShiftAmountTy()))); 1270 } 1271 1272 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1273 if (N1C && N0.getOpcode() == ISD::SHL && 1274 isa<ConstantSDNode>(N0.getOperand(1))) { 1275 SDValue C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1)); 1276 AddToWorkList(C3.getNode()); 1277 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3); 1278 } 1279 1280 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1281 // use. 1282 { 1283 SDValue Sh(0,0), Y(0,0); 1284 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1285 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1286 N0.getNode()->hasOneUse()) { 1287 Sh = N0; Y = N1; 1288 } else if (N1.getOpcode() == ISD::SHL && 1289 isa<ConstantSDNode>(N1.getOperand(1)) && 1290 N1.getNode()->hasOneUse()) { 1291 Sh = N1; Y = N0; 1292 } 1293 if (Sh.getNode()) { 1294 SDValue Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y); 1295 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1)); 1296 } 1297 } 1298 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1299 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 1300 isa<ConstantSDNode>(N0.getOperand(1))) { 1301 return DAG.getNode(ISD::ADD, VT, 1302 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1), 1303 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1)); 1304 } 1305 1306 // reassociate mul 1307 SDValue RMUL = ReassociateOps(ISD::MUL, N0, N1); 1308 if (RMUL.getNode() != 0) 1309 return RMUL; 1310 1311 return SDValue(); 1312} 1313 1314SDValue DAGCombiner::visitSDIV(SDNode *N) { 1315 SDValue N0 = N->getOperand(0); 1316 SDValue N1 = N->getOperand(1); 1317 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1318 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1319 MVT VT = N->getValueType(0); 1320 1321 // fold vector ops 1322 if (VT.isVector()) { 1323 SDValue FoldedVOp = SimplifyVBinOp(N); 1324 if (FoldedVOp.getNode()) return FoldedVOp; 1325 } 1326 1327 // fold (sdiv c1, c2) -> c1/c2 1328 if (N0C && N1C && !N1C->isNullValue()) 1329 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); 1330 // fold (sdiv X, 1) -> X 1331 if (N1C && N1C->getSExtValue() == 1LL) 1332 return N0; 1333 // fold (sdiv X, -1) -> 0-X 1334 if (N1C && N1C->isAllOnesValue()) 1335 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 1336 // If we know the sign bits of both operands are zero, strength reduce to a 1337 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1338 if (!VT.isVector()) { 1339 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1340 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1); 1341 } 1342 // fold (sdiv X, pow2) -> simple ops after legalize 1343 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() && 1344 (isPowerOf2_64(N1C->getSExtValue()) || 1345 isPowerOf2_64(-N1C->getSExtValue()))) { 1346 // If dividing by powers of two is cheap, then don't perform the following 1347 // fold. 1348 if (TLI.isPow2DivCheap()) 1349 return SDValue(); 1350 int64_t pow2 = N1C->getSExtValue(); 1351 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1352 unsigned lg2 = Log2_64(abs2); 1353 // Splat the sign bit into the register 1354 SDValue SGN = DAG.getNode(ISD::SRA, VT, N0, 1355 DAG.getConstant(VT.getSizeInBits()-1, 1356 TLI.getShiftAmountTy())); 1357 AddToWorkList(SGN.getNode()); 1358 // Add (N0 < 0) ? abs2 - 1 : 0; 1359 SDValue SRL = DAG.getNode(ISD::SRL, VT, SGN, 1360 DAG.getConstant(VT.getSizeInBits()-lg2, 1361 TLI.getShiftAmountTy())); 1362 SDValue ADD = DAG.getNode(ISD::ADD, VT, N0, SRL); 1363 AddToWorkList(SRL.getNode()); 1364 AddToWorkList(ADD.getNode()); // Divide by pow2 1365 SDValue SRA = DAG.getNode(ISD::SRA, VT, ADD, 1366 DAG.getConstant(lg2, TLI.getShiftAmountTy())); 1367 // If we're dividing by a positive value, we're done. Otherwise, we must 1368 // negate the result. 1369 if (pow2 > 0) 1370 return SRA; 1371 AddToWorkList(SRA.getNode()); 1372 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA); 1373 } 1374 // if integer divide is expensive and we satisfy the requirements, emit an 1375 // alternate sequence. 1376 if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) && 1377 !TLI.isIntDivCheap()) { 1378 SDValue Op = BuildSDIV(N); 1379 if (Op.getNode()) return Op; 1380 } 1381 1382 // undef / X -> 0 1383 if (N0.getOpcode() == ISD::UNDEF) 1384 return DAG.getConstant(0, VT); 1385 // X / undef -> undef 1386 if (N1.getOpcode() == ISD::UNDEF) 1387 return N1; 1388 1389 return SDValue(); 1390} 1391 1392SDValue DAGCombiner::visitUDIV(SDNode *N) { 1393 SDValue N0 = N->getOperand(0); 1394 SDValue N1 = N->getOperand(1); 1395 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1396 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1397 MVT VT = N->getValueType(0); 1398 1399 // fold vector ops 1400 if (VT.isVector()) { 1401 SDValue FoldedVOp = SimplifyVBinOp(N); 1402 if (FoldedVOp.getNode()) return FoldedVOp; 1403 } 1404 1405 // fold (udiv c1, c2) -> c1/c2 1406 if (N0C && N1C && !N1C->isNullValue()) 1407 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); 1408 // fold (udiv x, (1 << c)) -> x >>u c 1409 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1410 return DAG.getNode(ISD::SRL, VT, N0, 1411 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1412 TLI.getShiftAmountTy())); 1413 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1414 if (N1.getOpcode() == ISD::SHL) { 1415 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1416 if (SHC->getAPIntValue().isPowerOf2()) { 1417 MVT ADDVT = N1.getOperand(1).getValueType(); 1418 SDValue Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1), 1419 DAG.getConstant(SHC->getAPIntValue() 1420 .logBase2(), 1421 ADDVT)); 1422 AddToWorkList(Add.getNode()); 1423 return DAG.getNode(ISD::SRL, VT, N0, Add); 1424 } 1425 } 1426 } 1427 // fold (udiv x, c) -> alternate 1428 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1429 SDValue Op = BuildUDIV(N); 1430 if (Op.getNode()) return Op; 1431 } 1432 1433 // undef / X -> 0 1434 if (N0.getOpcode() == ISD::UNDEF) 1435 return DAG.getConstant(0, VT); 1436 // X / undef -> undef 1437 if (N1.getOpcode() == ISD::UNDEF) 1438 return N1; 1439 1440 return SDValue(); 1441} 1442 1443SDValue DAGCombiner::visitSREM(SDNode *N) { 1444 SDValue N0 = N->getOperand(0); 1445 SDValue N1 = N->getOperand(1); 1446 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1447 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1448 MVT VT = N->getValueType(0); 1449 1450 // fold (srem c1, c2) -> c1%c2 1451 if (N0C && N1C && !N1C->isNullValue()) 1452 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); 1453 // If we know the sign bits of both operands are zero, strength reduce to a 1454 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1455 if (!VT.isVector()) { 1456 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1457 return DAG.getNode(ISD::UREM, VT, N0, N1); 1458 } 1459 1460 // If X/C can be simplified by the division-by-constant logic, lower 1461 // X%C to the equivalent of X-X/C*C. 1462 if (N1C && !N1C->isNullValue()) { 1463 SDValue Div = DAG.getNode(ISD::SDIV, VT, N0, N1); 1464 AddToWorkList(Div.getNode()); 1465 SDValue OptimizedDiv = combine(Div.getNode()); 1466 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1467 SDValue Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1); 1468 SDValue Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1469 AddToWorkList(Mul.getNode()); 1470 return Sub; 1471 } 1472 } 1473 1474 // undef % X -> 0 1475 if (N0.getOpcode() == ISD::UNDEF) 1476 return DAG.getConstant(0, VT); 1477 // X % undef -> undef 1478 if (N1.getOpcode() == ISD::UNDEF) 1479 return N1; 1480 1481 return SDValue(); 1482} 1483 1484SDValue DAGCombiner::visitUREM(SDNode *N) { 1485 SDValue N0 = N->getOperand(0); 1486 SDValue N1 = N->getOperand(1); 1487 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1488 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1489 MVT VT = N->getValueType(0); 1490 1491 // fold (urem c1, c2) -> c1%c2 1492 if (N0C && N1C && !N1C->isNullValue()) 1493 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C); 1494 // fold (urem x, pow2) -> (and x, pow2-1) 1495 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 1496 return DAG.getNode(ISD::AND, VT, N0, 1497 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 1498 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1499 if (N1.getOpcode() == ISD::SHL) { 1500 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1501 if (SHC->getAPIntValue().isPowerOf2()) { 1502 SDValue Add = 1503 DAG.getNode(ISD::ADD, VT, N1, 1504 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 1505 VT)); 1506 AddToWorkList(Add.getNode()); 1507 return DAG.getNode(ISD::AND, VT, N0, Add); 1508 } 1509 } 1510 } 1511 1512 // If X/C can be simplified by the division-by-constant logic, lower 1513 // X%C to the equivalent of X-X/C*C. 1514 if (N1C && !N1C->isNullValue()) { 1515 SDValue Div = DAG.getNode(ISD::UDIV, VT, N0, N1); 1516 AddToWorkList(Div.getNode()); 1517 SDValue OptimizedDiv = combine(Div.getNode()); 1518 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1519 SDValue Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1); 1520 SDValue Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1521 AddToWorkList(Mul.getNode()); 1522 return Sub; 1523 } 1524 } 1525 1526 // undef % X -> 0 1527 if (N0.getOpcode() == ISD::UNDEF) 1528 return DAG.getConstant(0, VT); 1529 // X % undef -> undef 1530 if (N1.getOpcode() == ISD::UNDEF) 1531 return N1; 1532 1533 return SDValue(); 1534} 1535 1536SDValue DAGCombiner::visitMULHS(SDNode *N) { 1537 SDValue N0 = N->getOperand(0); 1538 SDValue N1 = N->getOperand(1); 1539 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1540 MVT VT = N->getValueType(0); 1541 1542 // fold (mulhs x, 0) -> 0 1543 if (N1C && N1C->isNullValue()) 1544 return N1; 1545 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1546 if (N1C && N1C->getAPIntValue() == 1) 1547 return DAG.getNode(ISD::SRA, N0.getValueType(), N0, 1548 DAG.getConstant(N0.getValueType().getSizeInBits()-1, 1549 TLI.getShiftAmountTy())); 1550 // fold (mulhs x, undef) -> 0 1551 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1552 return DAG.getConstant(0, VT); 1553 1554 return SDValue(); 1555} 1556 1557SDValue DAGCombiner::visitMULHU(SDNode *N) { 1558 SDValue N0 = N->getOperand(0); 1559 SDValue N1 = N->getOperand(1); 1560 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1561 MVT VT = N->getValueType(0); 1562 1563 // fold (mulhu x, 0) -> 0 1564 if (N1C && N1C->isNullValue()) 1565 return N1; 1566 // fold (mulhu x, 1) -> 0 1567 if (N1C && N1C->getAPIntValue() == 1) 1568 return DAG.getConstant(0, N0.getValueType()); 1569 // fold (mulhu x, undef) -> 0 1570 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1571 return DAG.getConstant(0, VT); 1572 1573 return SDValue(); 1574} 1575 1576/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 1577/// compute two values. LoOp and HiOp give the opcodes for the two computations 1578/// that are being performed. Return true if a simplification was made. 1579/// 1580SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 1581 unsigned HiOp) { 1582 // If the high half is not needed, just compute the low half. 1583 bool HiExists = N->hasAnyUseOfValue(1); 1584 if (!HiExists && 1585 (!LegalOperations || 1586 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 1587 SDValue Res = DAG.getNode(LoOp, N->getValueType(0), N->op_begin(), 1588 N->getNumOperands()); 1589 return CombineTo(N, Res, Res); 1590 } 1591 1592 // If the low half is not needed, just compute the high half. 1593 bool LoExists = N->hasAnyUseOfValue(0); 1594 if (!LoExists && 1595 (!LegalOperations || 1596 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 1597 SDValue Res = DAG.getNode(HiOp, N->getValueType(1), N->op_begin(), 1598 N->getNumOperands()); 1599 return CombineTo(N, Res, Res); 1600 } 1601 1602 // If both halves are used, return as it is. 1603 if (LoExists && HiExists) 1604 return SDValue(); 1605 1606 // If the two computed results can be simplified separately, separate them. 1607 if (LoExists) { 1608 SDValue Lo = DAG.getNode(LoOp, N->getValueType(0), 1609 N->op_begin(), N->getNumOperands()); 1610 AddToWorkList(Lo.getNode()); 1611 SDValue LoOpt = combine(Lo.getNode()); 1612 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && 1613 (!LegalOperations || 1614 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 1615 return CombineTo(N, LoOpt, LoOpt); 1616 } 1617 1618 if (HiExists) { 1619 SDValue Hi = DAG.getNode(HiOp, N->getValueType(1), 1620 N->op_begin(), N->getNumOperands()); 1621 AddToWorkList(Hi.getNode()); 1622 SDValue HiOpt = combine(Hi.getNode()); 1623 if (HiOpt.getNode() && HiOpt != Hi && 1624 (!LegalOperations || 1625 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 1626 return CombineTo(N, HiOpt, HiOpt); 1627 } 1628 return SDValue(); 1629} 1630 1631SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 1632 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 1633 if (Res.getNode()) return Res; 1634 1635 return SDValue(); 1636} 1637 1638SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 1639 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 1640 if (Res.getNode()) return Res; 1641 1642 return SDValue(); 1643} 1644 1645SDValue DAGCombiner::visitSDIVREM(SDNode *N) { 1646 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 1647 if (Res.getNode()) return Res; 1648 1649 return SDValue(); 1650} 1651 1652SDValue DAGCombiner::visitUDIVREM(SDNode *N) { 1653 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 1654 if (Res.getNode()) return Res; 1655 1656 return SDValue(); 1657} 1658 1659/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 1660/// two operands of the same opcode, try to simplify it. 1661SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 1662 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 1663 MVT VT = N0.getValueType(); 1664 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 1665 1666 // For each of OP in AND/OR/XOR: 1667 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 1668 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 1669 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 1670 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) 1671 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND|| 1672 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) && 1673 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1674 SDValue ORNode = DAG.getNode(N->getOpcode(), 1675 N0.getOperand(0).getValueType(), 1676 N0.getOperand(0), N1.getOperand(0)); 1677 AddToWorkList(ORNode.getNode()); 1678 return DAG.getNode(N0.getOpcode(), VT, ORNode); 1679 } 1680 1681 // For each of OP in SHL/SRL/SRA/AND... 1682 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 1683 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 1684 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 1685 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 1686 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 1687 N0.getOperand(1) == N1.getOperand(1)) { 1688 SDValue ORNode = DAG.getNode(N->getOpcode(), 1689 N0.getOperand(0).getValueType(), 1690 N0.getOperand(0), N1.getOperand(0)); 1691 AddToWorkList(ORNode.getNode()); 1692 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1)); 1693 } 1694 1695 return SDValue(); 1696} 1697 1698SDValue DAGCombiner::visitAND(SDNode *N) { 1699 SDValue N0 = N->getOperand(0); 1700 SDValue N1 = N->getOperand(1); 1701 SDValue LL, LR, RL, RR, CC0, CC1; 1702 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1703 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1704 MVT VT = N1.getValueType(); 1705 unsigned BitWidth = VT.getSizeInBits(); 1706 1707 // fold vector ops 1708 if (VT.isVector()) { 1709 SDValue FoldedVOp = SimplifyVBinOp(N); 1710 if (FoldedVOp.getNode()) return FoldedVOp; 1711 } 1712 1713 // fold (and x, undef) -> 0 1714 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1715 return DAG.getConstant(0, VT); 1716 // fold (and c1, c2) -> c1&c2 1717 if (N0C && N1C) 1718 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C); 1719 // canonicalize constant to RHS 1720 if (N0C && !N1C) 1721 return DAG.getNode(ISD::AND, VT, N1, N0); 1722 // fold (and x, -1) -> x 1723 if (N1C && N1C->isAllOnesValue()) 1724 return N0; 1725 // if (and x, c) is known to be zero, return 0 1726 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 1727 APInt::getAllOnesValue(BitWidth))) 1728 return DAG.getConstant(0, VT); 1729 // reassociate and 1730 SDValue RAND = ReassociateOps(ISD::AND, N0, N1); 1731 if (RAND.getNode() != 0) 1732 return RAND; 1733 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 1734 if (N1C && N0.getOpcode() == ISD::OR) 1735 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1736 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 1737 return N1; 1738 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 1739 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1740 SDValue N0Op0 = N0.getOperand(0); 1741 APInt Mask = ~N1C->getAPIntValue(); 1742 Mask.trunc(N0Op0.getValueSizeInBits()); 1743 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 1744 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(), 1745 N0Op0); 1746 1747 // Replace uses of the AND with uses of the Zero extend node. 1748 CombineTo(N, Zext); 1749 1750 // We actually want to replace all uses of the any_extend with the 1751 // zero_extend, to avoid duplicating things. This will later cause this 1752 // AND to be folded. 1753 CombineTo(N0.getNode(), Zext); 1754 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1755 } 1756 } 1757 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 1758 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1759 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1760 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1761 1762 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1763 LL.getValueType().isInteger()) { 1764 // fold (X == 0) & (Y == 0) -> (X|Y == 0) 1765 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 1766 SDValue ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1767 AddToWorkList(ORNode.getNode()); 1768 return DAG.getSetCC(VT, ORNode, LR, Op1); 1769 } 1770 // fold (X == -1) & (Y == -1) -> (X&Y == -1) 1771 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 1772 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1773 AddToWorkList(ANDNode.getNode()); 1774 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1775 } 1776 // fold (X > -1) & (Y > -1) -> (X|Y > -1) 1777 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1778 SDValue ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1779 AddToWorkList(ORNode.getNode()); 1780 return DAG.getSetCC(VT, ORNode, LR, Op1); 1781 } 1782 } 1783 // canonicalize equivalent to ll == rl 1784 if (LL == RR && LR == RL) { 1785 Op1 = ISD::getSetCCSwappedOperands(Op1); 1786 std::swap(RL, RR); 1787 } 1788 if (LL == RL && LR == RR) { 1789 bool isInteger = LL.getValueType().isInteger(); 1790 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1791 if (Result != ISD::SETCC_INVALID && 1792 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 1793 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1794 } 1795 } 1796 1797 // Simplify: and (op x...), (op y...) -> (op (and x, y)) 1798 if (N0.getOpcode() == N1.getOpcode()) { 1799 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1800 if (Tmp.getNode()) return Tmp; 1801 } 1802 1803 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1804 // fold (and (sra)) -> (and (srl)) when possible. 1805 if (!VT.isVector() && 1806 SimplifyDemandedBits(SDValue(N, 0))) 1807 return SDValue(N, 0); 1808 // fold (zext_inreg (extload x)) -> (zextload x) 1809 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { 1810 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1811 MVT EVT = LN0->getMemoryVT(); 1812 // If we zero all the possible extended bits, then we can turn this into 1813 // a zextload if we are running before legalize or the operation is legal. 1814 unsigned BitWidth = N1.getValueSizeInBits(); 1815 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1816 BitWidth - EVT.getSizeInBits())) && 1817 ((!LegalOperations && !LN0->isVolatile()) || 1818 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { 1819 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1820 LN0->getBasePtr(), LN0->getSrcValue(), 1821 LN0->getSrcValueOffset(), EVT, 1822 LN0->isVolatile(), LN0->getAlignment()); 1823 AddToWorkList(N); 1824 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 1825 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1826 } 1827 } 1828 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1829 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 1830 N0.hasOneUse()) { 1831 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1832 MVT EVT = LN0->getMemoryVT(); 1833 // If we zero all the possible extended bits, then we can turn this into 1834 // a zextload if we are running before legalize or the operation is legal. 1835 unsigned BitWidth = N1.getValueSizeInBits(); 1836 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1837 BitWidth - EVT.getSizeInBits())) && 1838 ((!LegalOperations && !LN0->isVolatile()) || 1839 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { 1840 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1841 LN0->getBasePtr(), LN0->getSrcValue(), 1842 LN0->getSrcValueOffset(), EVT, 1843 LN0->isVolatile(), LN0->getAlignment()); 1844 AddToWorkList(N); 1845 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 1846 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1847 } 1848 } 1849 1850 // fold (and (load x), 255) -> (zextload x, i8) 1851 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1852 if (N1C && N0.getOpcode() == ISD::LOAD) { 1853 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1854 if (LN0->getExtensionType() != ISD::SEXTLOAD && 1855 LN0->isUnindexed() && N0.hasOneUse() && 1856 // Do not change the width of a volatile load. 1857 !LN0->isVolatile()) { 1858 MVT EVT = MVT::Other; 1859 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 1860 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())) 1861 EVT = MVT::getIntegerVT(ActiveBits); 1862 1863 MVT LoadedVT = LN0->getMemoryVT(); 1864 // Do not generate loads of non-round integer types since these can 1865 // be expensive (and would be wrong if the type is not byte sized). 1866 if (EVT != MVT::Other && LoadedVT.bitsGT(EVT) && EVT.isRound() && 1867 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { 1868 MVT PtrType = N0.getOperand(1).getValueType(); 1869 // For big endian targets, we need to add an offset to the pointer to 1870 // load the correct bytes. For little endian systems, we merely need to 1871 // read fewer bytes from the same pointer. 1872 unsigned LVTStoreBytes = LoadedVT.getStoreSizeInBits()/8; 1873 unsigned EVTStoreBytes = EVT.getStoreSizeInBits()/8; 1874 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 1875 unsigned Alignment = LN0->getAlignment(); 1876 SDValue NewPtr = LN0->getBasePtr(); 1877 if (TLI.isBigEndian()) { 1878 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, 1879 DAG.getConstant(PtrOff, PtrType)); 1880 Alignment = MinAlign(Alignment, PtrOff); 1881 } 1882 AddToWorkList(NewPtr.getNode()); 1883 SDValue Load = 1884 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr, 1885 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT, 1886 LN0->isVolatile(), Alignment); 1887 AddToWorkList(N); 1888 CombineTo(N0.getNode(), Load, Load.getValue(1)); 1889 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1890 } 1891 } 1892 } 1893 1894 return SDValue(); 1895} 1896 1897SDValue DAGCombiner::visitOR(SDNode *N) { 1898 SDValue N0 = N->getOperand(0); 1899 SDValue N1 = N->getOperand(1); 1900 SDValue LL, LR, RL, RR, CC0, CC1; 1901 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1902 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1903 MVT VT = N1.getValueType(); 1904 1905 // fold vector ops 1906 if (VT.isVector()) { 1907 SDValue FoldedVOp = SimplifyVBinOp(N); 1908 if (FoldedVOp.getNode()) return FoldedVOp; 1909 } 1910 1911 // fold (or x, undef) -> -1 1912 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1913 return DAG.getConstant(~0ULL, VT); 1914 // fold (or c1, c2) -> c1|c2 1915 if (N0C && N1C) 1916 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); 1917 // canonicalize constant to RHS 1918 if (N0C && !N1C) 1919 return DAG.getNode(ISD::OR, VT, N1, N0); 1920 // fold (or x, 0) -> x 1921 if (N1C && N1C->isNullValue()) 1922 return N0; 1923 // fold (or x, -1) -> -1 1924 if (N1C && N1C->isAllOnesValue()) 1925 return N1; 1926 // fold (or x, c) -> c iff (x & ~c) == 0 1927 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 1928 return N1; 1929 // reassociate or 1930 SDValue ROR = ReassociateOps(ISD::OR, N0, N1); 1931 if (ROR.getNode() != 0) 1932 return ROR; 1933 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 1934 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 1935 isa<ConstantSDNode>(N0.getOperand(1))) { 1936 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 1937 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0), 1938 N1), 1939 DAG.getConstant(N1C->getAPIntValue() | 1940 C1->getAPIntValue(), VT)); 1941 } 1942 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 1943 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1944 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1945 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1946 1947 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1948 LL.getValueType().isInteger()) { 1949 // fold (X != 0) | (Y != 0) -> (X|Y != 0) 1950 // fold (X < 0) | (Y < 0) -> (X|Y < 0) 1951 if (cast<ConstantSDNode>(LR)->isNullValue() && 1952 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 1953 SDValue ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1954 AddToWorkList(ORNode.getNode()); 1955 return DAG.getSetCC(VT, ORNode, LR, Op1); 1956 } 1957 // fold (X != -1) | (Y != -1) -> (X&Y != -1) 1958 // fold (X > -1) | (Y > -1) -> (X&Y > -1) 1959 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 1960 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 1961 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1962 AddToWorkList(ANDNode.getNode()); 1963 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1964 } 1965 } 1966 // canonicalize equivalent to ll == rl 1967 if (LL == RR && LR == RL) { 1968 Op1 = ISD::getSetCCSwappedOperands(Op1); 1969 std::swap(RL, RR); 1970 } 1971 if (LL == RL && LR == RR) { 1972 bool isInteger = LL.getValueType().isInteger(); 1973 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 1974 if (Result != ISD::SETCC_INVALID && 1975 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 1976 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1977 } 1978 } 1979 1980 // Simplify: or (op x...), (op y...) -> (op (or x, y)) 1981 if (N0.getOpcode() == N1.getOpcode()) { 1982 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1983 if (Tmp.getNode()) return Tmp; 1984 } 1985 1986 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible. 1987 if (N0.getOpcode() == ISD::AND && 1988 N1.getOpcode() == ISD::AND && 1989 N0.getOperand(1).getOpcode() == ISD::Constant && 1990 N1.getOperand(1).getOpcode() == ISD::Constant && 1991 // Don't increase # computations. 1992 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) { 1993 // We can only do this xform if we know that bits from X that are set in C2 1994 // but not in C1 are already zero. Likewise for Y. 1995 const APInt &LHSMask = 1996 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 1997 const APInt &RHSMask = 1998 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 1999 2000 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 2001 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 2002 SDValue X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0)); 2003 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT)); 2004 } 2005 } 2006 2007 2008 // See if this is some rotate idiom. 2009 if (SDNode *Rot = MatchRotate(N0, N1)) 2010 return SDValue(Rot, 0); 2011 2012 return SDValue(); 2013} 2014 2015 2016/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 2017static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 2018 if (Op.getOpcode() == ISD::AND) { 2019 if (isa<ConstantSDNode>(Op.getOperand(1))) { 2020 Mask = Op.getOperand(1); 2021 Op = Op.getOperand(0); 2022 } else { 2023 return false; 2024 } 2025 } 2026 2027 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 2028 Shift = Op; 2029 return true; 2030 } 2031 return false; 2032} 2033 2034 2035// MatchRotate - Handle an 'or' of two operands. If this is one of the many 2036// idioms for rotate, and if the target supports rotation instructions, generate 2037// a rot[lr]. 2038SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS) { 2039 // Must be a legal type. Expanded 'n promoted things won't work with rotates. 2040 MVT VT = LHS.getValueType(); 2041 if (!TLI.isTypeLegal(VT)) return 0; 2042 2043 // The target must have at least one rotate flavor. 2044 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT); 2045 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT); 2046 if (!HasROTL && !HasROTR) return 0; 2047 2048 // Match "(X shl/srl V1) & V2" where V2 may not be present. 2049 SDValue LHSShift; // The shift. 2050 SDValue LHSMask; // AND value if any. 2051 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 2052 return 0; // Not part of a rotate. 2053 2054 SDValue RHSShift; // The shift. 2055 SDValue RHSMask; // AND value if any. 2056 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 2057 return 0; // Not part of a rotate. 2058 2059 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 2060 return 0; // Not shifting the same value. 2061 2062 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 2063 return 0; // Shifts must disagree. 2064 2065 // Canonicalize shl to left side in a shl/srl pair. 2066 if (RHSShift.getOpcode() == ISD::SHL) { 2067 std::swap(LHS, RHS); 2068 std::swap(LHSShift, RHSShift); 2069 std::swap(LHSMask , RHSMask ); 2070 } 2071 2072 unsigned OpSizeInBits = VT.getSizeInBits(); 2073 SDValue LHSShiftArg = LHSShift.getOperand(0); 2074 SDValue LHSShiftAmt = LHSShift.getOperand(1); 2075 SDValue RHSShiftAmt = RHSShift.getOperand(1); 2076 2077 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 2078 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 2079 if (LHSShiftAmt.getOpcode() == ISD::Constant && 2080 RHSShiftAmt.getOpcode() == ISD::Constant) { 2081 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue(); 2082 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue(); 2083 if ((LShVal + RShVal) != OpSizeInBits) 2084 return 0; 2085 2086 SDValue Rot; 2087 if (HasROTL) 2088 Rot = DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt); 2089 else 2090 Rot = DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt); 2091 2092 // If there is an AND of either shifted operand, apply it to the result. 2093 if (LHSMask.getNode() || RHSMask.getNode()) { 2094 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 2095 2096 if (LHSMask.getNode()) { 2097 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 2098 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 2099 } 2100 if (RHSMask.getNode()) { 2101 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 2102 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 2103 } 2104 2105 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT)); 2106 } 2107 2108 return Rot.getNode(); 2109 } 2110 2111 // If there is a mask here, and we have a variable shift, we can't be sure 2112 // that we're masking out the right stuff. 2113 if (LHSMask.getNode() || RHSMask.getNode()) 2114 return 0; 2115 2116 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 2117 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 2118 if (RHSShiftAmt.getOpcode() == ISD::SUB && 2119 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 2120 if (ConstantSDNode *SUBC = 2121 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 2122 if (SUBC->getAPIntValue() == OpSizeInBits) { 2123 if (HasROTL) 2124 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).getNode(); 2125 else 2126 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).getNode(); 2127 } 2128 } 2129 } 2130 2131 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 2132 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 2133 if (LHSShiftAmt.getOpcode() == ISD::SUB && 2134 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 2135 if (ConstantSDNode *SUBC = 2136 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 2137 if (SUBC->getAPIntValue() == OpSizeInBits) { 2138 if (HasROTR) 2139 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).getNode(); 2140 else 2141 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).getNode(); 2142 } 2143 } 2144 } 2145 2146 // Look for sign/zext/any-extended or truncate cases: 2147 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2148 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2149 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2150 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && 2151 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2152 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2153 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2154 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { 2155 SDValue LExtOp0 = LHSShiftAmt.getOperand(0); 2156 SDValue RExtOp0 = RHSShiftAmt.getOperand(0); 2157 if (RExtOp0.getOpcode() == ISD::SUB && 2158 RExtOp0.getOperand(1) == LExtOp0) { 2159 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2160 // (rotl x, y) 2161 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2162 // (rotr x, (sub 32, y)) 2163 if (ConstantSDNode *SUBC = 2164 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 2165 if (SUBC->getAPIntValue() == OpSizeInBits) { 2166 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, VT, LHSShiftArg, 2167 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 2168 } 2169 } 2170 } else if (LExtOp0.getOpcode() == ISD::SUB && 2171 RExtOp0 == LExtOp0.getOperand(1)) { 2172 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2173 // (rotr x, y) 2174 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2175 // (rotl x, (sub 32, y)) 2176 if (ConstantSDNode *SUBC = 2177 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 2178 if (SUBC->getAPIntValue() == OpSizeInBits) { 2179 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, VT, LHSShiftArg, 2180 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 2181 } 2182 } 2183 } 2184 } 2185 2186 return 0; 2187} 2188 2189 2190SDValue DAGCombiner::visitXOR(SDNode *N) { 2191 SDValue N0 = N->getOperand(0); 2192 SDValue N1 = N->getOperand(1); 2193 SDValue LHS, RHS, CC; 2194 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2195 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2196 MVT VT = N0.getValueType(); 2197 2198 // fold vector ops 2199 if (VT.isVector()) { 2200 SDValue FoldedVOp = SimplifyVBinOp(N); 2201 if (FoldedVOp.getNode()) return FoldedVOp; 2202 } 2203 2204 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 2205 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 2206 return DAG.getConstant(0, VT); 2207 // fold (xor x, undef) -> undef 2208 if (N0.getOpcode() == ISD::UNDEF) 2209 return N0; 2210 if (N1.getOpcode() == ISD::UNDEF) 2211 return N1; 2212 // fold (xor c1, c2) -> c1^c2 2213 if (N0C && N1C) 2214 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); 2215 // canonicalize constant to RHS 2216 if (N0C && !N1C) 2217 return DAG.getNode(ISD::XOR, VT, N1, N0); 2218 // fold (xor x, 0) -> x 2219 if (N1C && N1C->isNullValue()) 2220 return N0; 2221 // reassociate xor 2222 SDValue RXOR = ReassociateOps(ISD::XOR, N0, N1); 2223 if (RXOR.getNode() != 0) 2224 return RXOR; 2225 2226 // fold !(x cc y) -> (x !cc y) 2227 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 2228 bool isInt = LHS.getValueType().isInteger(); 2229 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 2230 isInt); 2231 2232 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) { 2233 switch (N0.getOpcode()) { 2234 default: 2235 assert(0 && "Unhandled SetCC Equivalent!"); 2236 abort(); 2237 case ISD::SETCC: 2238 return DAG.getSetCC(VT, LHS, RHS, NotCC); 2239 case ISD::SELECT_CC: 2240 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2), 2241 N0.getOperand(3), NotCC); 2242 } 2243 } 2244 } 2245 2246 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 2247 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 2248 N0.getNode()->hasOneUse() && 2249 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 2250 SDValue V = N0.getOperand(0); 2251 V = DAG.getNode(ISD::XOR, V.getValueType(), V, 2252 DAG.getConstant(1, V.getValueType())); 2253 AddToWorkList(V.getNode()); 2254 return DAG.getNode(ISD::ZERO_EXTEND, VT, V); 2255 } 2256 2257 // fold !(x or y) -> (!x and !y) iff x or y are setcc 2258 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 2259 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2260 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2261 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 2262 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2263 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 2264 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 2265 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2266 return DAG.getNode(NewOpcode, VT, LHS, RHS); 2267 } 2268 } 2269 // fold !(x or y) -> (!x and !y) iff x or y are constants 2270 if (N1C && N1C->isAllOnesValue() && 2271 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2272 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2273 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 2274 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2275 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 2276 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 2277 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2278 return DAG.getNode(NewOpcode, VT, LHS, RHS); 2279 } 2280 } 2281 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2) 2282 if (N1C && N0.getOpcode() == ISD::XOR) { 2283 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 2284 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2285 if (N00C) 2286 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1), 2287 DAG.getConstant(N1C->getAPIntValue()^ 2288 N00C->getAPIntValue(), VT)); 2289 if (N01C) 2290 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0), 2291 DAG.getConstant(N1C->getAPIntValue()^ 2292 N01C->getAPIntValue(), VT)); 2293 } 2294 // fold (xor x, x) -> 0 2295 if (N0 == N1) { 2296 if (!VT.isVector()) { 2297 return DAG.getConstant(0, VT); 2298 } else if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)){ 2299 // Produce a vector of zeros. 2300 SDValue El = DAG.getConstant(0, VT.getVectorElementType()); 2301 std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 2302 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 2303 } 2304 } 2305 2306 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 2307 if (N0.getOpcode() == N1.getOpcode()) { 2308 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2309 if (Tmp.getNode()) return Tmp; 2310 } 2311 2312 // Simplify the expression using non-local knowledge. 2313 if (!VT.isVector() && 2314 SimplifyDemandedBits(SDValue(N, 0))) 2315 return SDValue(N, 0); 2316 2317 return SDValue(); 2318} 2319 2320/// visitShiftByConstant - Handle transforms common to the three shifts, when 2321/// the shift amount is a constant. 2322SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 2323 SDNode *LHS = N->getOperand(0).getNode(); 2324 if (!LHS->hasOneUse()) return SDValue(); 2325 2326 // We want to pull some binops through shifts, so that we have (and (shift)) 2327 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 2328 // thing happens with address calculations, so it's important to canonicalize 2329 // it. 2330 bool HighBitSet = false; // Can we transform this if the high bit is set? 2331 2332 switch (LHS->getOpcode()) { 2333 default: return SDValue(); 2334 case ISD::OR: 2335 case ISD::XOR: 2336 HighBitSet = false; // We can only transform sra if the high bit is clear. 2337 break; 2338 case ISD::AND: 2339 HighBitSet = true; // We can only transform sra if the high bit is set. 2340 break; 2341 case ISD::ADD: 2342 if (N->getOpcode() != ISD::SHL) 2343 return SDValue(); // only shl(add) not sr[al](add). 2344 HighBitSet = false; // We can only transform sra if the high bit is clear. 2345 break; 2346 } 2347 2348 // We require the RHS of the binop to be a constant as well. 2349 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 2350 if (!BinOpCst) return SDValue(); 2351 2352 2353 // FIXME: disable this for unless the input to the binop is a shift by a 2354 // constant. If it is not a shift, it pessimizes some common cases like: 2355 // 2356 //void foo(int *X, int i) { X[i & 1235] = 1; } 2357 //int bar(int *X, int i) { return X[i & 255]; } 2358 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); 2359 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 2360 BinOpLHSVal->getOpcode() != ISD::SRA && 2361 BinOpLHSVal->getOpcode() != ISD::SRL) || 2362 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 2363 return SDValue(); 2364 2365 MVT VT = N->getValueType(0); 2366 2367 // If this is a signed shift right, and the high bit is modified 2368 // by the logical operation, do not perform the transformation. 2369 // The highBitSet boolean indicates the value of the high bit of 2370 // the constant which would cause it to be modified for this 2371 // operation. 2372 if (N->getOpcode() == ISD::SRA) { 2373 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 2374 if (BinOpRHSSignSet != HighBitSet) 2375 return SDValue(); 2376 } 2377 2378 // Fold the constants, shifting the binop RHS by the shift amount. 2379 SDValue NewRHS = DAG.getNode(N->getOpcode(), N->getValueType(0), 2380 LHS->getOperand(1), N->getOperand(1)); 2381 2382 // Create the new shift. 2383 SDValue NewShift = DAG.getNode(N->getOpcode(), VT, LHS->getOperand(0), 2384 N->getOperand(1)); 2385 2386 // Create the new binop. 2387 return DAG.getNode(LHS->getOpcode(), VT, NewShift, NewRHS); 2388} 2389 2390 2391SDValue DAGCombiner::visitSHL(SDNode *N) { 2392 SDValue N0 = N->getOperand(0); 2393 SDValue N1 = N->getOperand(1); 2394 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2395 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2396 MVT VT = N0.getValueType(); 2397 unsigned OpSizeInBits = VT.getSizeInBits(); 2398 2399 // fold (shl c1, c2) -> c1<<c2 2400 if (N0C && N1C) 2401 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C); 2402 // fold (shl 0, x) -> 0 2403 if (N0C && N0C->isNullValue()) 2404 return N0; 2405 // fold (shl x, c >= size(x)) -> undef 2406 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2407 return DAG.getNode(ISD::UNDEF, VT); 2408 // fold (shl x, 0) -> x 2409 if (N1C && N1C->isNullValue()) 2410 return N0; 2411 // if (shl x, c) is known to be zero, return 0 2412 if (DAG.MaskedValueIsZero(SDValue(N, 0), 2413 APInt::getAllOnesValue(VT.getSizeInBits()))) 2414 return DAG.getConstant(0, VT); 2415 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), c)) 2416 // iff (trunc c) == c 2417 if (N1.getOpcode() == ISD::TRUNCATE && 2418 N1.getOperand(0).getOpcode() == ISD::AND && 2419 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2420 SDValue N101 = N1.getOperand(0).getOperand(1); 2421 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2422 MVT TruncVT = N1.getValueType(); 2423 SDValue N100 = N1.getOperand(0).getOperand(0); 2424 return DAG.getNode(ISD::SHL, VT, N0, 2425 DAG.getNode(ISD::AND, TruncVT, 2426 DAG.getNode(ISD::TRUNCATE, TruncVT, N100), 2427 DAG.getConstant(N101C->getZExtValue(), 2428 TruncVT))); 2429 } 2430 } 2431 2432 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2433 return SDValue(N, 0); 2434 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2) 2435 if (N1C && N0.getOpcode() == ISD::SHL && 2436 N0.getOperand(1).getOpcode() == ISD::Constant) { 2437 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2438 uint64_t c2 = N1C->getZExtValue(); 2439 if (c1 + c2 > OpSizeInBits) 2440 return DAG.getConstant(0, VT); 2441 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0), 2442 DAG.getConstant(c1 + c2, N1.getValueType())); 2443 } 2444 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or 2445 // (srl (and x, -1 << c1), c1-c2) 2446 if (N1C && N0.getOpcode() == ISD::SRL && 2447 N0.getOperand(1).getOpcode() == ISD::Constant) { 2448 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2449 uint64_t c2 = N1C->getZExtValue(); 2450 SDValue Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0), 2451 DAG.getConstant(~0ULL << c1, VT)); 2452 if (c2 > c1) 2453 return DAG.getNode(ISD::SHL, VT, Mask, 2454 DAG.getConstant(c2-c1, N1.getValueType())); 2455 else 2456 return DAG.getNode(ISD::SRL, VT, Mask, 2457 DAG.getConstant(c1-c2, N1.getValueType())); 2458 } 2459 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1) 2460 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 2461 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 2462 DAG.getConstant(~0ULL << N1C->getZExtValue(), VT)); 2463 2464 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2465} 2466 2467SDValue DAGCombiner::visitSRA(SDNode *N) { 2468 SDValue N0 = N->getOperand(0); 2469 SDValue N1 = N->getOperand(1); 2470 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2471 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2472 MVT VT = N0.getValueType(); 2473 2474 // fold (sra c1, c2) -> c1>>c2 2475 if (N0C && N1C) 2476 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); 2477 // fold (sra 0, x) -> 0 2478 if (N0C && N0C->isNullValue()) 2479 return N0; 2480 // fold (sra -1, x) -> -1 2481 if (N0C && N0C->isAllOnesValue()) 2482 return N0; 2483 // fold (sra x, c >= size(x)) -> undef 2484 if (N1C && N1C->getZExtValue() >= VT.getSizeInBits()) 2485 return DAG.getNode(ISD::UNDEF, VT); 2486 // fold (sra x, 0) -> x 2487 if (N1C && N1C->isNullValue()) 2488 return N0; 2489 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 2490 // sext_inreg. 2491 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 2492 unsigned LowBits = VT.getSizeInBits() - (unsigned)N1C->getZExtValue(); 2493 MVT EVT = MVT::getIntegerVT(LowBits); 2494 if ((!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))) 2495 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), 2496 DAG.getValueType(EVT)); 2497 } 2498 2499 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2) 2500 if (N1C && N0.getOpcode() == ISD::SRA) { 2501 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2502 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); 2503 if (Sum >= VT.getSizeInBits()) Sum = VT.getSizeInBits()-1; 2504 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), 2505 DAG.getConstant(Sum, N1C->getValueType(0))); 2506 } 2507 } 2508 2509 // fold sra (shl X, m), result_size - n 2510 // -> (sign_extend (trunc (shl X, result_size - n - m))) for 2511 // result_size - n != m. 2512 // If truncate is free for the target sext(shl) is likely to result in better 2513 // code. 2514 if (N0.getOpcode() == ISD::SHL) { 2515 // Get the two constanst of the shifts, CN0 = m, CN = n. 2516 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2517 if (N01C && N1C) { 2518 // Determine what the truncate's result bitsize and type would be. 2519 unsigned VTValSize = VT.getSizeInBits(); 2520 MVT TruncVT = 2521 MVT::getIntegerVT(VTValSize - N1C->getZExtValue()); 2522 // Determine the residual right-shift amount. 2523 unsigned ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); 2524 2525 // If the shift is not a no-op (in which case this should be just a sign 2526 // extend already), the truncated to type is legal, sign_extend is legal 2527 // on that type, and the the truncate to that type is both legal and free, 2528 // perform the transform. 2529 if (ShiftAmt && 2530 TLI.isOperationLegal(ISD::SIGN_EXTEND, TruncVT) && 2531 TLI.isOperationLegal(ISD::TRUNCATE, VT) && 2532 TLI.isTruncateFree(VT, TruncVT)) { 2533 2534 SDValue Amt = DAG.getConstant(ShiftAmt, TLI.getShiftAmountTy()); 2535 SDValue Shift = DAG.getNode(ISD::SRL, VT, N0.getOperand(0), Amt); 2536 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, TruncVT, Shift); 2537 return DAG.getNode(ISD::SIGN_EXTEND, N->getValueType(0), Trunc); 2538 } 2539 } 2540 } 2541 2542 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), c)) 2543 // iff (trunc c) == c 2544 if (N1.getOpcode() == ISD::TRUNCATE && 2545 N1.getOperand(0).getOpcode() == ISD::AND && 2546 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2547 SDValue N101 = N1.getOperand(0).getOperand(1); 2548 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2549 MVT TruncVT = N1.getValueType(); 2550 SDValue N100 = N1.getOperand(0).getOperand(0); 2551 return DAG.getNode(ISD::SRA, VT, N0, 2552 DAG.getNode(ISD::AND, TruncVT, 2553 DAG.getNode(ISD::TRUNCATE, TruncVT, N100), 2554 DAG.getConstant(N101C->getZExtValue(), 2555 TruncVT))); 2556 } 2557 } 2558 2559 // Simplify, based on bits shifted out of the LHS. 2560 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2561 return SDValue(N, 0); 2562 2563 2564 // If the sign bit is known to be zero, switch this to a SRL. 2565 if (DAG.SignBitIsZero(N0)) 2566 return DAG.getNode(ISD::SRL, VT, N0, N1); 2567 2568 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2569} 2570 2571SDValue DAGCombiner::visitSRL(SDNode *N) { 2572 SDValue N0 = N->getOperand(0); 2573 SDValue N1 = N->getOperand(1); 2574 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2575 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2576 MVT VT = N0.getValueType(); 2577 unsigned OpSizeInBits = VT.getSizeInBits(); 2578 2579 // fold (srl c1, c2) -> c1 >>u c2 2580 if (N0C && N1C) 2581 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); 2582 // fold (srl 0, x) -> 0 2583 if (N0C && N0C->isNullValue()) 2584 return N0; 2585 // fold (srl x, c >= size(x)) -> undef 2586 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2587 return DAG.getNode(ISD::UNDEF, VT); 2588 // fold (srl x, 0) -> x 2589 if (N1C && N1C->isNullValue()) 2590 return N0; 2591 // if (srl x, c) is known to be zero, return 0 2592 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2593 APInt::getAllOnesValue(OpSizeInBits))) 2594 return DAG.getConstant(0, VT); 2595 2596 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2) 2597 if (N1C && N0.getOpcode() == ISD::SRL && 2598 N0.getOperand(1).getOpcode() == ISD::Constant) { 2599 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2600 uint64_t c2 = N1C->getZExtValue(); 2601 if (c1 + c2 > OpSizeInBits) 2602 return DAG.getConstant(0, VT); 2603 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 2604 DAG.getConstant(c1 + c2, N1.getValueType())); 2605 } 2606 2607 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 2608 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2609 // Shifting in all undef bits? 2610 MVT SmallVT = N0.getOperand(0).getValueType(); 2611 if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) 2612 return DAG.getNode(ISD::UNDEF, VT); 2613 2614 SDValue SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1); 2615 AddToWorkList(SmallShift.getNode()); 2616 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift); 2617 } 2618 2619 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 2620 // bit, which is unmodified by sra. 2621 if (N1C && N1C->getZExtValue()+1 == VT.getSizeInBits()) { 2622 if (N0.getOpcode() == ISD::SRA) 2623 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1); 2624 } 2625 2626 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 2627 if (N1C && N0.getOpcode() == ISD::CTLZ && 2628 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 2629 APInt KnownZero, KnownOne; 2630 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 2631 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 2632 2633 // If any of the input bits are KnownOne, then the input couldn't be all 2634 // zeros, thus the result of the srl will always be zero. 2635 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 2636 2637 // If all of the bits input the to ctlz node are known to be zero, then 2638 // the result of the ctlz is "32" and the result of the shift is one. 2639 APInt UnknownBits = ~KnownZero & Mask; 2640 if (UnknownBits == 0) return DAG.getConstant(1, VT); 2641 2642 // Otherwise, check to see if there is exactly one bit input to the ctlz. 2643 if ((UnknownBits & (UnknownBits-1)) == 0) { 2644 // Okay, we know that only that the single bit specified by UnknownBits 2645 // could be set on input to the CTLZ node. If this bit is set, the SRL 2646 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 2647 // to an SRL,XOR pair, which is likely to simplify more. 2648 unsigned ShAmt = UnknownBits.countTrailingZeros(); 2649 SDValue Op = N0.getOperand(0); 2650 if (ShAmt) { 2651 Op = DAG.getNode(ISD::SRL, VT, Op, 2652 DAG.getConstant(ShAmt, TLI.getShiftAmountTy())); 2653 AddToWorkList(Op.getNode()); 2654 } 2655 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT)); 2656 } 2657 } 2658 2659 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), c)) 2660 // iff (trunc c) == c 2661 if (N1.getOpcode() == ISD::TRUNCATE && 2662 N1.getOperand(0).getOpcode() == ISD::AND && 2663 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2664 SDValue N101 = N1.getOperand(0).getOperand(1); 2665 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2666 MVT TruncVT = N1.getValueType(); 2667 SDValue N100 = N1.getOperand(0).getOperand(0); 2668 return DAG.getNode(ISD::SRL, VT, N0, 2669 DAG.getNode(ISD::AND, TruncVT, 2670 DAG.getNode(ISD::TRUNCATE, TruncVT, N100), 2671 DAG.getConstant(N101C->getZExtValue(), 2672 TruncVT))); 2673 } 2674 } 2675 2676 // fold operands of srl based on knowledge that the low bits are not 2677 // demanded. 2678 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2679 return SDValue(N, 0); 2680 2681 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2682} 2683 2684SDValue DAGCombiner::visitCTLZ(SDNode *N) { 2685 SDValue N0 = N->getOperand(0); 2686 MVT VT = N->getValueType(0); 2687 2688 // fold (ctlz c1) -> c2 2689 if (isa<ConstantSDNode>(N0)) 2690 return DAG.getNode(ISD::CTLZ, VT, N0); 2691 return SDValue(); 2692} 2693 2694SDValue DAGCombiner::visitCTTZ(SDNode *N) { 2695 SDValue N0 = N->getOperand(0); 2696 MVT VT = N->getValueType(0); 2697 2698 // fold (cttz c1) -> c2 2699 if (isa<ConstantSDNode>(N0)) 2700 return DAG.getNode(ISD::CTTZ, VT, N0); 2701 return SDValue(); 2702} 2703 2704SDValue DAGCombiner::visitCTPOP(SDNode *N) { 2705 SDValue N0 = N->getOperand(0); 2706 MVT VT = N->getValueType(0); 2707 2708 // fold (ctpop c1) -> c2 2709 if (isa<ConstantSDNode>(N0)) 2710 return DAG.getNode(ISD::CTPOP, VT, N0); 2711 return SDValue(); 2712} 2713 2714SDValue DAGCombiner::visitSELECT(SDNode *N) { 2715 SDValue N0 = N->getOperand(0); 2716 SDValue N1 = N->getOperand(1); 2717 SDValue N2 = N->getOperand(2); 2718 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2719 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2720 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 2721 MVT VT = N->getValueType(0); 2722 MVT VT0 = N0.getValueType(); 2723 2724 // fold select C, X, X -> X 2725 if (N1 == N2) 2726 return N1; 2727 // fold select true, X, Y -> X 2728 if (N0C && !N0C->isNullValue()) 2729 return N1; 2730 // fold select false, X, Y -> Y 2731 if (N0C && N0C->isNullValue()) 2732 return N2; 2733 // fold select C, 1, X -> C | X 2734 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 2735 return DAG.getNode(ISD::OR, VT, N0, N2); 2736 // fold select C, 0, 1 -> ~C 2737 if (VT.isInteger() && VT0.isInteger() && 2738 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 2739 SDValue XORNode = DAG.getNode(ISD::XOR, VT0, N0, DAG.getConstant(1, VT0)); 2740 if (VT == VT0) 2741 return XORNode; 2742 AddToWorkList(XORNode.getNode()); 2743 if (VT.bitsGT(VT0)) 2744 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode); 2745 return DAG.getNode(ISD::TRUNCATE, VT, XORNode); 2746 } 2747 // fold select C, 0, X -> ~C & X 2748 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 2749 SDValue XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 2750 AddToWorkList(XORNode.getNode()); 2751 return DAG.getNode(ISD::AND, VT, XORNode, N2); 2752 } 2753 // fold select C, X, 1 -> ~C | X 2754 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 2755 SDValue XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 2756 AddToWorkList(XORNode.getNode()); 2757 return DAG.getNode(ISD::OR, VT, XORNode, N1); 2758 } 2759 // fold select C, X, 0 -> C & X 2760 // FIXME: this should check for C type == X type, not i1? 2761 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 2762 return DAG.getNode(ISD::AND, VT, N0, N1); 2763 // fold X ? X : Y --> X ? 1 : Y --> X | Y 2764 if (VT == MVT::i1 && N0 == N1) 2765 return DAG.getNode(ISD::OR, VT, N0, N2); 2766 // fold X ? Y : X --> X ? Y : 0 --> X & Y 2767 if (VT == MVT::i1 && N0 == N2) 2768 return DAG.getNode(ISD::AND, VT, N0, N1); 2769 2770 // If we can fold this based on the true/false value, do so. 2771 if (SimplifySelectOps(N, N1, N2)) 2772 return SDValue(N, 0); // Don't revisit N. 2773 2774 // fold selects based on a setcc into other things, such as min/max/abs 2775 if (N0.getOpcode() == ISD::SETCC) { 2776 // FIXME: 2777 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 2778 // having to say they don't support SELECT_CC on every type the DAG knows 2779 // about, since there is no way to mark an opcode illegal at all value types 2780 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other)) 2781 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1), 2782 N1, N2, N0.getOperand(2)); 2783 else 2784 return SimplifySelect(N0, N1, N2); 2785 } 2786 return SDValue(); 2787} 2788 2789SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 2790 SDValue N0 = N->getOperand(0); 2791 SDValue N1 = N->getOperand(1); 2792 SDValue N2 = N->getOperand(2); 2793 SDValue N3 = N->getOperand(3); 2794 SDValue N4 = N->getOperand(4); 2795 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 2796 2797 // fold select_cc lhs, rhs, x, x, cc -> x 2798 if (N2 == N3) 2799 return N2; 2800 2801 // Determine if the condition we're dealing with is constant 2802 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0), N0, N1, CC, false); 2803 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 2804 2805 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) { 2806 if (!SCCC->isNullValue()) 2807 return N2; // cond always true -> true val 2808 else 2809 return N3; // cond always false -> false val 2810 } 2811 2812 // Fold to a simpler select_cc 2813 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) 2814 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(), 2815 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 2816 SCC.getOperand(2)); 2817 2818 // If we can fold this based on the true/false value, do so. 2819 if (SimplifySelectOps(N, N2, N3)) 2820 return SDValue(N, 0); // Don't revisit N. 2821 2822 // fold select_cc into other things, such as min/max/abs 2823 return SimplifySelectCC(N0, N1, N2, N3, CC); 2824} 2825 2826SDValue DAGCombiner::visitSETCC(SDNode *N) { 2827 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 2828 cast<CondCodeSDNode>(N->getOperand(2))->get()); 2829} 2830 2831// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 2832// "fold ({s|z}ext (load x)) -> ({s|z}ext (truncate ({s|z}extload x)))" 2833// transformation. Returns true if extension are possible and the above 2834// mentioned transformation is profitable. 2835static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 2836 unsigned ExtOpc, 2837 SmallVector<SDNode*, 4> &ExtendNodes, 2838 TargetLowering &TLI) { 2839 bool HasCopyToRegUses = false; 2840 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 2841 for (SDNode::use_iterator UI = N0.getNode()->use_begin(), 2842 UE = N0.getNode()->use_end(); 2843 UI != UE; ++UI) { 2844 SDNode *User = *UI; 2845 if (User == N) 2846 continue; 2847 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 2848 if (User->getOpcode() == ISD::SETCC) { 2849 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 2850 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 2851 // Sign bits will be lost after a zext. 2852 return false; 2853 bool Add = false; 2854 for (unsigned i = 0; i != 2; ++i) { 2855 SDValue UseOp = User->getOperand(i); 2856 if (UseOp == N0) 2857 continue; 2858 if (!isa<ConstantSDNode>(UseOp)) 2859 return false; 2860 Add = true; 2861 } 2862 if (Add) 2863 ExtendNodes.push_back(User); 2864 } else { 2865 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2866 SDValue UseOp = User->getOperand(i); 2867 if (UseOp == N0) { 2868 // If truncate from extended type to original load type is free 2869 // on this target, then it's ok to extend a CopyToReg. 2870 if (isTruncFree && User->getOpcode() == ISD::CopyToReg) 2871 HasCopyToRegUses = true; 2872 else 2873 return false; 2874 } 2875 } 2876 } 2877 } 2878 2879 if (HasCopyToRegUses) { 2880 bool BothLiveOut = false; 2881 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 2882 UI != UE; ++UI) { 2883 SDNode *User = *UI; 2884 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2885 SDValue UseOp = User->getOperand(i); 2886 if (UseOp.getNode() == N && UseOp.getResNo() == 0) { 2887 BothLiveOut = true; 2888 break; 2889 } 2890 } 2891 } 2892 if (BothLiveOut) 2893 // Both unextended and extended values are live out. There had better be 2894 // good a reason for the transformation. 2895 return ExtendNodes.size(); 2896 } 2897 return true; 2898} 2899 2900SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 2901 SDValue N0 = N->getOperand(0); 2902 MVT VT = N->getValueType(0); 2903 2904 // fold (sext c1) -> c1 2905 if (isa<ConstantSDNode>(N0)) 2906 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0); 2907 2908 // fold (sext (sext x)) -> (sext x) 2909 // fold (sext (aext x)) -> (sext x) 2910 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2911 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0)); 2912 2913 if (N0.getOpcode() == ISD::TRUNCATE) { 2914 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 2915 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 2916 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 2917 if (NarrowLoad.getNode()) { 2918 if (NarrowLoad.getNode() != N0.getNode()) 2919 CombineTo(N0.getNode(), NarrowLoad); 2920 return DAG.getNode(ISD::SIGN_EXTEND, VT, NarrowLoad); 2921 } 2922 2923 // See if the value being truncated is already sign extended. If so, just 2924 // eliminate the trunc/sext pair. 2925 SDValue Op = N0.getOperand(0); 2926 unsigned OpBits = Op.getValueType().getSizeInBits(); 2927 unsigned MidBits = N0.getValueType().getSizeInBits(); 2928 unsigned DestBits = VT.getSizeInBits(); 2929 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 2930 2931 if (OpBits == DestBits) { 2932 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 2933 // bits, it is already ready. 2934 if (NumSignBits > DestBits-MidBits) 2935 return Op; 2936 } else if (OpBits < DestBits) { 2937 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 2938 // bits, just sext from i32. 2939 if (NumSignBits > OpBits-MidBits) 2940 return DAG.getNode(ISD::SIGN_EXTEND, VT, Op); 2941 } else { 2942 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 2943 // bits, just truncate to i32. 2944 if (NumSignBits > OpBits-MidBits) 2945 return DAG.getNode(ISD::TRUNCATE, VT, Op); 2946 } 2947 2948 // fold (sext (truncate x)) -> (sextinreg x). 2949 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 2950 N0.getValueType())) { 2951 if (Op.getValueType().bitsLT(VT)) 2952 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2953 else if (Op.getValueType().bitsGT(VT)) 2954 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2955 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op, 2956 DAG.getValueType(N0.getValueType())); 2957 } 2958 } 2959 2960 // fold (sext (load x)) -> (sext (truncate (sextload x))) 2961 if (ISD::isNON_EXTLoad(N0.getNode()) && 2962 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 2963 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { 2964 bool DoXform = true; 2965 SmallVector<SDNode*, 4> SetCCs; 2966 if (!N0.hasOneUse()) 2967 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 2968 if (DoXform) { 2969 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2970 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2971 LN0->getBasePtr(), LN0->getSrcValue(), 2972 LN0->getSrcValueOffset(), 2973 N0.getValueType(), 2974 LN0->isVolatile(), LN0->getAlignment()); 2975 CombineTo(N, ExtLoad); 2976 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad); 2977 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 2978 // Extend SetCC uses if necessary. 2979 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 2980 SDNode *SetCC = SetCCs[i]; 2981 SmallVector<SDValue, 4> Ops; 2982 for (unsigned j = 0; j != 2; ++j) { 2983 SDValue SOp = SetCC->getOperand(j); 2984 if (SOp == Trunc) 2985 Ops.push_back(ExtLoad); 2986 else 2987 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, VT, SOp)); 2988 } 2989 Ops.push_back(SetCC->getOperand(2)); 2990 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0), 2991 &Ops[0], Ops.size())); 2992 } 2993 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2994 } 2995 } 2996 2997 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 2998 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 2999 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3000 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3001 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3002 MVT EVT = LN0->getMemoryVT(); 3003 if ((!LegalOperations && !LN0->isVolatile()) || 3004 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT)) { 3005 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 3006 LN0->getBasePtr(), LN0->getSrcValue(), 3007 LN0->getSrcValueOffset(), EVT, 3008 LN0->isVolatile(), LN0->getAlignment()); 3009 CombineTo(N, ExtLoad); 3010 CombineTo(N0.getNode(), 3011 DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 3012 ExtLoad.getValue(1)); 3013 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3014 } 3015 } 3016 3017 // sext(setcc x,y,cc) -> select_cc x, y, -1, 0, cc 3018 if (N0.getOpcode() == ISD::SETCC) { 3019 SDValue SCC = 3020 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 3021 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT), 3022 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3023 if (SCC.getNode()) return SCC; 3024 } 3025 3026 // fold (sext x) -> (zext x) if the sign bit is known zero. 3027 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 3028 DAG.SignBitIsZero(N0)) 3029 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 3030 3031 return SDValue(); 3032} 3033 3034SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 3035 SDValue N0 = N->getOperand(0); 3036 MVT VT = N->getValueType(0); 3037 3038 // fold (zext c1) -> c1 3039 if (isa<ConstantSDNode>(N0)) 3040 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 3041 // fold (zext (zext x)) -> (zext x) 3042 // fold (zext (aext x)) -> (zext x) 3043 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 3044 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0)); 3045 3046 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 3047 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 3048 if (N0.getOpcode() == ISD::TRUNCATE) { 3049 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3050 if (NarrowLoad.getNode()) { 3051 if (NarrowLoad.getNode() != N0.getNode()) 3052 CombineTo(N0.getNode(), NarrowLoad); 3053 return DAG.getNode(ISD::ZERO_EXTEND, VT, NarrowLoad); 3054 } 3055 } 3056 3057 // fold (zext (truncate x)) -> (and x, mask) 3058 if (N0.getOpcode() == ISD::TRUNCATE && 3059 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) { 3060 SDValue Op = N0.getOperand(0); 3061 if (Op.getValueType().bitsLT(VT)) { 3062 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 3063 } else if (Op.getValueType().bitsGT(VT)) { 3064 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 3065 } 3066 return DAG.getZeroExtendInReg(Op, N0.getValueType()); 3067 } 3068 3069 // fold (zext (and (trunc x), cst)) -> (and x, cst). 3070 if (N0.getOpcode() == ISD::AND && 3071 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3072 N0.getOperand(1).getOpcode() == ISD::Constant) { 3073 SDValue X = N0.getOperand(0).getOperand(0); 3074 if (X.getValueType().bitsLT(VT)) { 3075 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 3076 } else if (X.getValueType().bitsGT(VT)) { 3077 X = DAG.getNode(ISD::TRUNCATE, VT, X); 3078 } 3079 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3080 Mask.zext(VT.getSizeInBits()); 3081 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 3082 } 3083 3084 // fold (zext (load x)) -> (zext (truncate (zextload x))) 3085 if (ISD::isNON_EXTLoad(N0.getNode()) && 3086 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3087 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 3088 bool DoXform = true; 3089 SmallVector<SDNode*, 4> SetCCs; 3090 if (!N0.hasOneUse()) 3091 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 3092 if (DoXform) { 3093 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3094 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 3095 LN0->getBasePtr(), LN0->getSrcValue(), 3096 LN0->getSrcValueOffset(), 3097 N0.getValueType(), 3098 LN0->isVolatile(), LN0->getAlignment()); 3099 CombineTo(N, ExtLoad); 3100 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad); 3101 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3102 // Extend SetCC uses if necessary. 3103 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3104 SDNode *SetCC = SetCCs[i]; 3105 SmallVector<SDValue, 4> Ops; 3106 for (unsigned j = 0; j != 2; ++j) { 3107 SDValue SOp = SetCC->getOperand(j); 3108 if (SOp == Trunc) 3109 Ops.push_back(ExtLoad); 3110 else 3111 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, VT, SOp)); 3112 } 3113 Ops.push_back(SetCC->getOperand(2)); 3114 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0), 3115 &Ops[0], Ops.size())); 3116 } 3117 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3118 } 3119 } 3120 3121 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 3122 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 3123 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3124 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3125 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3126 MVT EVT = LN0->getMemoryVT(); 3127 if ((!LegalOperations && !LN0->isVolatile()) || 3128 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT)) { 3129 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 3130 LN0->getBasePtr(), LN0->getSrcValue(), 3131 LN0->getSrcValueOffset(), EVT, 3132 LN0->isVolatile(), LN0->getAlignment()); 3133 CombineTo(N, ExtLoad); 3134 CombineTo(N0.getNode(), 3135 DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 3136 ExtLoad.getValue(1)); 3137 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3138 } 3139 } 3140 3141 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3142 if (N0.getOpcode() == ISD::SETCC) { 3143 SDValue SCC = 3144 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 3145 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3146 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3147 if (SCC.getNode()) return SCC; 3148 } 3149 3150 return SDValue(); 3151} 3152 3153SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 3154 SDValue N0 = N->getOperand(0); 3155 MVT VT = N->getValueType(0); 3156 3157 // fold (aext c1) -> c1 3158 if (isa<ConstantSDNode>(N0)) 3159 return DAG.getNode(ISD::ANY_EXTEND, VT, N0); 3160 // fold (aext (aext x)) -> (aext x) 3161 // fold (aext (zext x)) -> (zext x) 3162 // fold (aext (sext x)) -> (sext x) 3163 if (N0.getOpcode() == ISD::ANY_EXTEND || 3164 N0.getOpcode() == ISD::ZERO_EXTEND || 3165 N0.getOpcode() == ISD::SIGN_EXTEND) 3166 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 3167 3168 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 3169 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 3170 if (N0.getOpcode() == ISD::TRUNCATE) { 3171 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3172 if (NarrowLoad.getNode()) { 3173 if (NarrowLoad.getNode() != N0.getNode()) 3174 CombineTo(N0.getNode(), NarrowLoad); 3175 return DAG.getNode(ISD::ANY_EXTEND, VT, NarrowLoad); 3176 } 3177 } 3178 3179 // fold (aext (truncate x)) 3180 if (N0.getOpcode() == ISD::TRUNCATE) { 3181 SDValue TruncOp = N0.getOperand(0); 3182 if (TruncOp.getValueType() == VT) 3183 return TruncOp; // x iff x size == zext size. 3184 if (TruncOp.getValueType().bitsGT(VT)) 3185 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp); 3186 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp); 3187 } 3188 3189 // fold (aext (and (trunc x), cst)) -> (and x, cst). 3190 if (N0.getOpcode() == ISD::AND && 3191 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3192 N0.getOperand(1).getOpcode() == ISD::Constant) { 3193 SDValue X = N0.getOperand(0).getOperand(0); 3194 if (X.getValueType().bitsLT(VT)) { 3195 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 3196 } else if (X.getValueType().bitsGT(VT)) { 3197 X = DAG.getNode(ISD::TRUNCATE, VT, X); 3198 } 3199 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3200 Mask.zext(VT.getSizeInBits()); 3201 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 3202 } 3203 3204 // fold (aext (load x)) -> (aext (truncate (extload x))) 3205 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 3206 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3207 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 3208 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3209 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 3210 LN0->getBasePtr(), LN0->getSrcValue(), 3211 LN0->getSrcValueOffset(), 3212 N0.getValueType(), 3213 LN0->isVolatile(), LN0->getAlignment()); 3214 CombineTo(N, ExtLoad); 3215 // Redirect any chain users to the new load. 3216 DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), 3217 SDValue(ExtLoad.getNode(), 1)); 3218 // If any node needs the original loaded value, recompute it. 3219 if (!LN0->use_empty()) 3220 CombineTo(LN0, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 3221 ExtLoad.getValue(1)); 3222 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3223 } 3224 3225 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 3226 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 3227 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 3228 if (N0.getOpcode() == ISD::LOAD && 3229 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3230 N0.hasOneUse()) { 3231 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3232 MVT EVT = LN0->getMemoryVT(); 3233 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT, 3234 LN0->getChain(), LN0->getBasePtr(), 3235 LN0->getSrcValue(), 3236 LN0->getSrcValueOffset(), EVT, 3237 LN0->isVolatile(), LN0->getAlignment()); 3238 CombineTo(N, ExtLoad); 3239 CombineTo(N0.getNode(), 3240 DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 3241 ExtLoad.getValue(1)); 3242 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3243 } 3244 3245 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3246 if (N0.getOpcode() == ISD::SETCC) { 3247 SDValue SCC = 3248 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 3249 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3250 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3251 if (SCC.getNode()) 3252 return SCC; 3253 } 3254 3255 return SDValue(); 3256} 3257 3258/// GetDemandedBits - See if the specified operand can be simplified with the 3259/// knowledge that only the bits specified by Mask are used. If so, return the 3260/// simpler operand, otherwise return a null SDValue. 3261SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 3262 switch (V.getOpcode()) { 3263 default: break; 3264 case ISD::OR: 3265 case ISD::XOR: 3266 // If the LHS or RHS don't contribute bits to the or, drop them. 3267 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 3268 return V.getOperand(1); 3269 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 3270 return V.getOperand(0); 3271 break; 3272 case ISD::SRL: 3273 // Only look at single-use SRLs. 3274 if (!V.getNode()->hasOneUse()) 3275 break; 3276 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 3277 // See if we can recursively simplify the LHS. 3278 unsigned Amt = RHSC->getZExtValue(); 3279 APInt NewMask = Mask << Amt; 3280 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 3281 if (SimplifyLHS.getNode()) { 3282 return DAG.getNode(ISD::SRL, V.getValueType(), 3283 SimplifyLHS, V.getOperand(1)); 3284 } 3285 } 3286 } 3287 return SDValue(); 3288} 3289 3290/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 3291/// bits and then truncated to a narrower type and where N is a multiple 3292/// of number of bits of the narrower type, transform it to a narrower load 3293/// from address + N / num of bits of new type. If the result is to be 3294/// extended, also fold the extension to form a extending load. 3295SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 3296 unsigned Opc = N->getOpcode(); 3297 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 3298 SDValue N0 = N->getOperand(0); 3299 MVT VT = N->getValueType(0); 3300 MVT EVT = N->getValueType(0); 3301 3302 // This transformation isn't valid for vector loads. 3303 if (VT.isVector()) 3304 return SDValue(); 3305 3306 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then 3307 // extended to VT. 3308 if (Opc == ISD::SIGN_EXTEND_INREG) { 3309 ExtType = ISD::SEXTLOAD; 3310 EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3311 if (LegalOperations && !TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT)) 3312 return SDValue(); 3313 } 3314 3315 unsigned EVTBits = EVT.getSizeInBits(); 3316 unsigned ShAmt = 0; 3317 bool CombineSRL = false; 3318 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 3319 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3320 ShAmt = N01->getZExtValue(); 3321 // Is the shift amount a multiple of size of VT? 3322 if ((ShAmt & (EVTBits-1)) == 0) { 3323 N0 = N0.getOperand(0); 3324 if (N0.getValueType().getSizeInBits() <= EVTBits) 3325 return SDValue(); 3326 CombineSRL = true; 3327 } 3328 } 3329 } 3330 3331 // Do not generate loads of non-round integer types since these can 3332 // be expensive (and would be wrong if the type is not byte sized). 3333 if (isa<LoadSDNode>(N0) && N0.hasOneUse() && VT.isRound() && 3334 cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() > EVTBits && 3335 // Do not change the width of a volatile load. 3336 !cast<LoadSDNode>(N0)->isVolatile()) { 3337 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3338 MVT PtrType = N0.getOperand(1).getValueType(); 3339 // For big endian targets, we need to adjust the offset to the pointer to 3340 // load the correct bytes. 3341 if (TLI.isBigEndian()) { 3342 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 3343 unsigned EVTStoreBits = EVT.getStoreSizeInBits(); 3344 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 3345 } 3346 uint64_t PtrOff = ShAmt / 8; 3347 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 3348 SDValue NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(), 3349 DAG.getConstant(PtrOff, PtrType)); 3350 AddToWorkList(NewPtr.getNode()); 3351 SDValue Load = (ExtType == ISD::NON_EXTLOAD) 3352 ? DAG.getLoad(VT, LN0->getChain(), NewPtr, 3353 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3354 LN0->isVolatile(), NewAlign) 3355 : DAG.getExtLoad(ExtType, VT, LN0->getChain(), NewPtr, 3356 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3357 EVT, LN0->isVolatile(), NewAlign); 3358 AddToWorkList(N); 3359 if (CombineSRL) { 3360 WorkListRemover DeadNodes(*this); 3361 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), 3362 &DeadNodes); 3363 CombineTo(N->getOperand(0).getNode(), Load); 3364 } else 3365 CombineTo(N0.getNode(), Load, Load.getValue(1)); 3366 if (ShAmt) { 3367 if (Opc == ISD::SIGN_EXTEND_INREG) 3368 return DAG.getNode(Opc, VT, Load, N->getOperand(1)); 3369 else 3370 return DAG.getNode(Opc, VT, Load); 3371 } 3372 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3373 } 3374 3375 return SDValue(); 3376} 3377 3378 3379SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 3380 SDValue N0 = N->getOperand(0); 3381 SDValue N1 = N->getOperand(1); 3382 MVT VT = N->getValueType(0); 3383 MVT EVT = cast<VTSDNode>(N1)->getVT(); 3384 unsigned VTBits = VT.getSizeInBits(); 3385 unsigned EVTBits = EVT.getSizeInBits(); 3386 3387 // fold (sext_in_reg c1) -> c1 3388 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 3389 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1); 3390 3391 // If the input is already sign extended, just drop the extension. 3392 if (DAG.ComputeNumSignBits(N0) >= VT.getSizeInBits()-EVTBits+1) 3393 return N0; 3394 3395 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 3396 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 3397 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 3398 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); 3399 } 3400 3401 // fold (sext_in_reg (sext x)) -> (sext x) 3402 // fold (sext_in_reg (aext x)) -> (sext x) 3403 // if x is small enough. 3404 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 3405 SDValue N00 = N0.getOperand(0); 3406 if (N00.getValueType().getSizeInBits() < EVTBits) 3407 return DAG.getNode(ISD::SIGN_EXTEND, VT, N00, N1); 3408 } 3409 3410 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 3411 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 3412 return DAG.getZeroExtendInReg(N0, EVT); 3413 3414 // fold operands of sext_in_reg based on knowledge that the top bits are not 3415 // demanded. 3416 if (SimplifyDemandedBits(SDValue(N, 0))) 3417 return SDValue(N, 0); 3418 3419 // fold (sext_in_reg (load x)) -> (smaller sextload x) 3420 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 3421 SDValue NarrowLoad = ReduceLoadWidth(N); 3422 if (NarrowLoad.getNode()) 3423 return NarrowLoad; 3424 3425 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24 3426 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible. 3427 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 3428 if (N0.getOpcode() == ISD::SRL) { 3429 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 3430 if (ShAmt->getZExtValue()+EVTBits <= VT.getSizeInBits()) { 3431 // We can turn this into an SRA iff the input to the SRL is already sign 3432 // extended enough. 3433 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 3434 if (VT.getSizeInBits()-(ShAmt->getZExtValue()+EVTBits) < InSignBits) 3435 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1)); 3436 } 3437 } 3438 3439 // fold (sext_inreg (extload x)) -> (sextload x) 3440 if (ISD::isEXTLoad(N0.getNode()) && 3441 ISD::isUNINDEXEDLoad(N0.getNode()) && 3442 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3443 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3444 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 3445 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3446 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 3447 LN0->getBasePtr(), LN0->getSrcValue(), 3448 LN0->getSrcValueOffset(), EVT, 3449 LN0->isVolatile(), LN0->getAlignment()); 3450 CombineTo(N, ExtLoad); 3451 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 3452 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3453 } 3454 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 3455 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3456 N0.hasOneUse() && 3457 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3458 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3459 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 3460 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3461 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 3462 LN0->getBasePtr(), LN0->getSrcValue(), 3463 LN0->getSrcValueOffset(), EVT, 3464 LN0->isVolatile(), LN0->getAlignment()); 3465 CombineTo(N, ExtLoad); 3466 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 3467 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3468 } 3469 return SDValue(); 3470} 3471 3472SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 3473 SDValue N0 = N->getOperand(0); 3474 MVT VT = N->getValueType(0); 3475 3476 // noop truncate 3477 if (N0.getValueType() == N->getValueType(0)) 3478 return N0; 3479 // fold (truncate c1) -> c1 3480 if (isa<ConstantSDNode>(N0)) 3481 return DAG.getNode(ISD::TRUNCATE, VT, N0); 3482 // fold (truncate (truncate x)) -> (truncate x) 3483 if (N0.getOpcode() == ISD::TRUNCATE) 3484 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 3485 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 3486 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| 3487 N0.getOpcode() == ISD::ANY_EXTEND) { 3488 if (N0.getOperand(0).getValueType().bitsLT(VT)) 3489 // if the source is smaller than the dest, we still need an extend 3490 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 3491 else if (N0.getOperand(0).getValueType().bitsGT(VT)) 3492 // if the source is larger than the dest, than we just need the truncate 3493 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 3494 else 3495 // if the source and dest are the same type, we can drop both the extend 3496 // and the truncate 3497 return N0.getOperand(0); 3498 } 3499 3500 // See if we can simplify the input to this truncate through knowledge that 3501 // only the low bits are being used. For example "trunc (or (shl x, 8), y)" 3502 // -> trunc y 3503 SDValue Shorter = 3504 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 3505 VT.getSizeInBits())); 3506 if (Shorter.getNode()) 3507 return DAG.getNode(ISD::TRUNCATE, VT, Shorter); 3508 3509 // fold (truncate (load x)) -> (smaller load x) 3510 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 3511 return ReduceLoadWidth(N); 3512} 3513 3514static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 3515 SDValue Elt = N->getOperand(i); 3516 if (Elt.getOpcode() != ISD::MERGE_VALUES) 3517 return Elt.getNode(); 3518 return Elt.getOperand(Elt.getResNo()).getNode(); 3519} 3520 3521/// CombineConsecutiveLoads - build_pair (load, load) -> load 3522/// if load locations are consecutive. 3523SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, MVT VT) { 3524 assert(N->getOpcode() == ISD::BUILD_PAIR); 3525 3526 SDNode *LD1 = getBuildPairElt(N, 0); 3527 if (!ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse()) 3528 return SDValue(); 3529 MVT LD1VT = LD1->getValueType(0); 3530 SDNode *LD2 = getBuildPairElt(N, 1); 3531 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 3532 if (ISD::isNON_EXTLoad(LD2) && 3533 LD2->hasOneUse() && 3534 // If both are volatile this would reduce the number of volatile loads. 3535 // If one is volatile it might be ok, but play conservative and bail out. 3536 !cast<LoadSDNode>(LD1)->isVolatile() && 3537 !cast<LoadSDNode>(LD2)->isVolatile() && 3538 TLI.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1, MFI)) { 3539 LoadSDNode *LD = cast<LoadSDNode>(LD1); 3540 unsigned Align = LD->getAlignment(); 3541 unsigned NewAlign = TLI.getTargetData()-> 3542 getABITypeAlignment(VT.getTypeForMVT()); 3543 if (NewAlign <= Align && 3544 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) 3545 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), 3546 LD->getSrcValue(), LD->getSrcValueOffset(), 3547 false, Align); 3548 } 3549 return SDValue(); 3550} 3551 3552SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) { 3553 SDValue N0 = N->getOperand(0); 3554 MVT VT = N->getValueType(0); 3555 3556 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 3557 // Only do this before legalize, since afterward the target may be depending 3558 // on the bitconvert. 3559 // First check to see if this is all constant. 3560 if (!LegalTypes && 3561 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 3562 VT.isVector()) { 3563 bool isSimple = true; 3564 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 3565 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 3566 N0.getOperand(i).getOpcode() != ISD::Constant && 3567 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 3568 isSimple = false; 3569 break; 3570 } 3571 3572 MVT DestEltVT = N->getValueType(0).getVectorElementType(); 3573 assert(!DestEltVT.isVector() && 3574 "Element type of vector ValueType must not be vector!"); 3575 if (isSimple) { 3576 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.getNode(), DestEltVT); 3577 } 3578 } 3579 3580 // If the input is a constant, let getNode fold it. 3581 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 3582 SDValue Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0); 3583 if (Res.getNode() != N) return Res; 3584 } 3585 3586 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2) 3587 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3588 3589 // fold (conv (load x)) -> (load (conv*)x) 3590 // If the resultant load doesn't need a higher alignment than the original! 3591 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 3592 // Do not change the width of a volatile load. 3593 !cast<LoadSDNode>(N0)->isVolatile() && 3594 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) { 3595 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3596 unsigned Align = TLI.getTargetData()-> 3597 getABITypeAlignment(VT.getTypeForMVT()); 3598 unsigned OrigAlign = LN0->getAlignment(); 3599 if (Align <= OrigAlign) { 3600 SDValue Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(), 3601 LN0->getSrcValue(), LN0->getSrcValueOffset(), 3602 LN0->isVolatile(), OrigAlign); 3603 AddToWorkList(N); 3604 CombineTo(N0.getNode(), 3605 DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load), 3606 Load.getValue(1)); 3607 return Load; 3608 } 3609 } 3610 3611 // Fold bitconvert(fneg(x)) -> xor(bitconvert(x), signbit) 3612 // Fold bitconvert(fabs(x)) -> and(bitconvert(x), ~signbit) 3613 // This often reduces constant pool loads. 3614 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && 3615 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) { 3616 SDValue NewConv = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3617 AddToWorkList(NewConv.getNode()); 3618 3619 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3620 if (N0.getOpcode() == ISD::FNEG) 3621 return DAG.getNode(ISD::XOR, VT, NewConv, DAG.getConstant(SignBit, VT)); 3622 assert(N0.getOpcode() == ISD::FABS); 3623 return DAG.getNode(ISD::AND, VT, NewConv, DAG.getConstant(~SignBit, VT)); 3624 } 3625 3626 // Fold bitconvert(fcopysign(cst, x)) -> bitconvert(x)&sign | cst&~sign' 3627 // Note that we don't handle copysign(x,cst) because this can always be folded 3628 // to an fneg or fabs. 3629 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 3630 isa<ConstantFPSDNode>(N0.getOperand(0)) && 3631 VT.isInteger() && !VT.isVector()) { 3632 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 3633 MVT IntXVT = MVT::getIntegerVT(OrigXWidth); 3634 if (TLI.isTypeLegal(IntXVT) || !LegalTypes) { 3635 SDValue X = DAG.getNode(ISD::BIT_CONVERT, IntXVT, N0.getOperand(1)); 3636 AddToWorkList(X.getNode()); 3637 3638 // If X has a different width than the result/lhs, sext it or truncate it. 3639 unsigned VTWidth = VT.getSizeInBits(); 3640 if (OrigXWidth < VTWidth) { 3641 X = DAG.getNode(ISD::SIGN_EXTEND, VT, X); 3642 AddToWorkList(X.getNode()); 3643 } else if (OrigXWidth > VTWidth) { 3644 // To get the sign bit in the right place, we have to shift it right 3645 // before truncating. 3646 X = DAG.getNode(ISD::SRL, X.getValueType(), X, 3647 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 3648 AddToWorkList(X.getNode()); 3649 X = DAG.getNode(ISD::TRUNCATE, VT, X); 3650 AddToWorkList(X.getNode()); 3651 } 3652 3653 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3654 X = DAG.getNode(ISD::AND, VT, X, DAG.getConstant(SignBit, VT)); 3655 AddToWorkList(X.getNode()); 3656 3657 SDValue Cst = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3658 Cst = DAG.getNode(ISD::AND, VT, Cst, DAG.getConstant(~SignBit, VT)); 3659 AddToWorkList(Cst.getNode()); 3660 3661 return DAG.getNode(ISD::OR, VT, X, Cst); 3662 } 3663 } 3664 3665 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 3666 if (N0.getOpcode() == ISD::BUILD_PAIR) { 3667 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT); 3668 if (CombineLD.getNode()) 3669 return CombineLD; 3670 } 3671 3672 return SDValue(); 3673} 3674 3675SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 3676 MVT VT = N->getValueType(0); 3677 return CombineConsecutiveLoads(N, VT); 3678} 3679 3680/// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector 3681/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 3682/// destination element value type. 3683SDValue DAGCombiner:: 3684ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT DstEltVT) { 3685 MVT SrcEltVT = BV->getOperand(0).getValueType(); 3686 3687 // If this is already the right type, we're done. 3688 if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 3689 3690 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 3691 unsigned DstBitSize = DstEltVT.getSizeInBits(); 3692 3693 // If this is a conversion of N elements of one type to N elements of another 3694 // type, convert each element. This handles FP<->INT cases. 3695 if (SrcBitSize == DstBitSize) { 3696 SmallVector<SDValue, 8> Ops; 3697 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3698 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i))); 3699 AddToWorkList(Ops.back().getNode()); 3700 } 3701 MVT VT = MVT::getVectorVT(DstEltVT, 3702 BV->getValueType(0).getVectorNumElements()); 3703 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3704 } 3705 3706 // Otherwise, we're growing or shrinking the elements. To avoid having to 3707 // handle annoying details of growing/shrinking FP values, we convert them to 3708 // int first. 3709 if (SrcEltVT.isFloatingPoint()) { 3710 // Convert the input float vector to a int vector where the elements are the 3711 // same sizes. 3712 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 3713 MVT IntVT = MVT::getIntegerVT(SrcEltVT.getSizeInBits()); 3714 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode(); 3715 SrcEltVT = IntVT; 3716 } 3717 3718 // Now we know the input is an integer vector. If the output is a FP type, 3719 // convert to integer first, then to FP of the right size. 3720 if (DstEltVT.isFloatingPoint()) { 3721 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 3722 MVT TmpVT = MVT::getIntegerVT(DstEltVT.getSizeInBits()); 3723 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).getNode(); 3724 3725 // Next, convert to FP elements of the same size. 3726 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT); 3727 } 3728 3729 // Okay, we know the src/dst types are both integers of differing types. 3730 // Handling growing first. 3731 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 3732 if (SrcBitSize < DstBitSize) { 3733 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 3734 3735 SmallVector<SDValue, 8> Ops; 3736 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 3737 i += NumInputsPerOutput) { 3738 bool isLE = TLI.isLittleEndian(); 3739 APInt NewBits = APInt(DstBitSize, 0); 3740 bool EltIsUndef = true; 3741 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 3742 // Shift the previously computed bits over. 3743 NewBits <<= SrcBitSize; 3744 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 3745 if (Op.getOpcode() == ISD::UNDEF) continue; 3746 EltIsUndef = false; 3747 3748 NewBits |= 3749 APInt(cast<ConstantSDNode>(Op)->getAPIntValue()).zext(DstBitSize); 3750 } 3751 3752 if (EltIsUndef) 3753 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 3754 else 3755 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 3756 } 3757 3758 MVT VT = MVT::getVectorVT(DstEltVT, Ops.size()); 3759 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3760 } 3761 3762 // Finally, this must be the case where we are shrinking elements: each input 3763 // turns into multiple outputs. 3764 bool isS2V = ISD::isScalarToVector(BV); 3765 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 3766 MVT VT = MVT::getVectorVT(DstEltVT, NumOutputsPerInput*BV->getNumOperands()); 3767 SmallVector<SDValue, 8> Ops; 3768 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3769 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 3770 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 3771 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 3772 continue; 3773 } 3774 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getAPIntValue(); 3775 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 3776 APInt ThisVal = APInt(OpVal).trunc(DstBitSize); 3777 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 3778 if (isS2V && i == 0 && j == 0 && APInt(ThisVal).zext(SrcBitSize) == OpVal) 3779 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 3780 return DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Ops[0]); 3781 OpVal = OpVal.lshr(DstBitSize); 3782 } 3783 3784 // For big endian targets, swap the order of the pieces of each element. 3785 if (TLI.isBigEndian()) 3786 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 3787 } 3788 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3789} 3790 3791 3792 3793SDValue DAGCombiner::visitFADD(SDNode *N) { 3794 SDValue N0 = N->getOperand(0); 3795 SDValue N1 = N->getOperand(1); 3796 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3797 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3798 MVT VT = N->getValueType(0); 3799 3800 // fold vector ops 3801 if (VT.isVector()) { 3802 SDValue FoldedVOp = SimplifyVBinOp(N); 3803 if (FoldedVOp.getNode()) return FoldedVOp; 3804 } 3805 3806 // fold (fadd c1, c2) -> c1+c2 3807 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3808 return DAG.getNode(ISD::FADD, VT, N0, N1); 3809 // canonicalize constant to RHS 3810 if (N0CFP && !N1CFP) 3811 return DAG.getNode(ISD::FADD, VT, N1, N0); 3812 // fold (A + (-B)) -> A-B 3813 if (isNegatibleForFree(N1, LegalOperations) == 2) 3814 return DAG.getNode(ISD::FSUB, VT, N0, 3815 GetNegatedExpression(N1, DAG, LegalOperations)); 3816 // fold ((-A) + B) -> B-A 3817 if (isNegatibleForFree(N0, LegalOperations) == 2) 3818 return DAG.getNode(ISD::FSUB, VT, N1, 3819 GetNegatedExpression(N0, DAG, LegalOperations)); 3820 3821 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 3822 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 3823 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3824 return DAG.getNode(ISD::FADD, VT, N0.getOperand(0), 3825 DAG.getNode(ISD::FADD, VT, N0.getOperand(1), N1)); 3826 3827 return SDValue(); 3828} 3829 3830SDValue DAGCombiner::visitFSUB(SDNode *N) { 3831 SDValue N0 = N->getOperand(0); 3832 SDValue N1 = N->getOperand(1); 3833 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3834 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3835 MVT VT = N->getValueType(0); 3836 3837 // fold vector ops 3838 if (VT.isVector()) { 3839 SDValue FoldedVOp = SimplifyVBinOp(N); 3840 if (FoldedVOp.getNode()) return FoldedVOp; 3841 } 3842 3843 // fold (fsub c1, c2) -> c1-c2 3844 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3845 return DAG.getNode(ISD::FSUB, VT, N0, N1); 3846 // fold (0-B) -> -B 3847 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { 3848 if (isNegatibleForFree(N1, LegalOperations)) 3849 return GetNegatedExpression(N1, DAG, LegalOperations); 3850 return DAG.getNode(ISD::FNEG, VT, N1); 3851 } 3852 // fold (A-(-B)) -> A+B 3853 if (isNegatibleForFree(N1, LegalOperations)) 3854 return DAG.getNode(ISD::FADD, VT, N0, 3855 GetNegatedExpression(N1, DAG, LegalOperations)); 3856 3857 return SDValue(); 3858} 3859 3860SDValue DAGCombiner::visitFMUL(SDNode *N) { 3861 SDValue N0 = N->getOperand(0); 3862 SDValue N1 = N->getOperand(1); 3863 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3864 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3865 MVT VT = N->getValueType(0); 3866 3867 // fold vector ops 3868 if (VT.isVector()) { 3869 SDValue FoldedVOp = SimplifyVBinOp(N); 3870 if (FoldedVOp.getNode()) return FoldedVOp; 3871 } 3872 3873 // fold (fmul c1, c2) -> c1*c2 3874 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3875 return DAG.getNode(ISD::FMUL, VT, N0, N1); 3876 // canonicalize constant to RHS 3877 if (N0CFP && !N1CFP) 3878 return DAG.getNode(ISD::FMUL, VT, N1, N0); 3879 // fold (fmul X, 2.0) -> (fadd X, X) 3880 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 3881 return DAG.getNode(ISD::FADD, VT, N0, N0); 3882 // fold (fmul X, -1.0) -> (fneg X) 3883 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 3884 return DAG.getNode(ISD::FNEG, VT, N0); 3885 3886 // -X * -Y -> X*Y 3887 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 3888 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 3889 // Both can be negated for free, check to see if at least one is cheaper 3890 // negated. 3891 if (LHSNeg == 2 || RHSNeg == 2) 3892 return DAG.getNode(ISD::FMUL, VT, 3893 GetNegatedExpression(N0, DAG, LegalOperations), 3894 GetNegatedExpression(N1, DAG, LegalOperations)); 3895 } 3896 } 3897 3898 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 3899 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 3900 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3901 return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0), 3902 DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1)); 3903 3904 return SDValue(); 3905} 3906 3907SDValue DAGCombiner::visitFDIV(SDNode *N) { 3908 SDValue N0 = N->getOperand(0); 3909 SDValue N1 = N->getOperand(1); 3910 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3911 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3912 MVT VT = N->getValueType(0); 3913 3914 // fold vector ops 3915 if (VT.isVector()) { 3916 SDValue FoldedVOp = SimplifyVBinOp(N); 3917 if (FoldedVOp.getNode()) return FoldedVOp; 3918 } 3919 3920 // fold (fdiv c1, c2) -> c1/c2 3921 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3922 return DAG.getNode(ISD::FDIV, VT, N0, N1); 3923 3924 3925 // -X / -Y -> X*Y 3926 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 3927 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 3928 // Both can be negated for free, check to see if at least one is cheaper 3929 // negated. 3930 if (LHSNeg == 2 || RHSNeg == 2) 3931 return DAG.getNode(ISD::FDIV, VT, 3932 GetNegatedExpression(N0, DAG, LegalOperations), 3933 GetNegatedExpression(N1, DAG, LegalOperations)); 3934 } 3935 } 3936 3937 return SDValue(); 3938} 3939 3940SDValue DAGCombiner::visitFREM(SDNode *N) { 3941 SDValue N0 = N->getOperand(0); 3942 SDValue N1 = N->getOperand(1); 3943 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3944 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3945 MVT VT = N->getValueType(0); 3946 3947 // fold (frem c1, c2) -> fmod(c1,c2) 3948 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3949 return DAG.getNode(ISD::FREM, VT, N0, N1); 3950 3951 return SDValue(); 3952} 3953 3954SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 3955 SDValue N0 = N->getOperand(0); 3956 SDValue N1 = N->getOperand(1); 3957 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3958 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3959 MVT VT = N->getValueType(0); 3960 3961 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 3962 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1); 3963 3964 if (N1CFP) { 3965 const APFloat& V = N1CFP->getValueAPF(); 3966 // copysign(x, c1) -> fabs(x) iff ispos(c1) 3967 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 3968 if (!V.isNegative()) 3969 return DAG.getNode(ISD::FABS, VT, N0); 3970 else 3971 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0)); 3972 } 3973 3974 // copysign(fabs(x), y) -> copysign(x, y) 3975 // copysign(fneg(x), y) -> copysign(x, y) 3976 // copysign(copysign(x,z), y) -> copysign(x, y) 3977 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 3978 N0.getOpcode() == ISD::FCOPYSIGN) 3979 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1); 3980 3981 // copysign(x, abs(y)) -> abs(x) 3982 if (N1.getOpcode() == ISD::FABS) 3983 return DAG.getNode(ISD::FABS, VT, N0); 3984 3985 // copysign(x, copysign(y,z)) -> copysign(x, z) 3986 if (N1.getOpcode() == ISD::FCOPYSIGN) 3987 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1)); 3988 3989 // copysign(x, fp_extend(y)) -> copysign(x, y) 3990 // copysign(x, fp_round(y)) -> copysign(x, y) 3991 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 3992 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0)); 3993 3994 return SDValue(); 3995} 3996 3997 3998 3999SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 4000 SDValue N0 = N->getOperand(0); 4001 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4002 MVT VT = N->getValueType(0); 4003 MVT OpVT = N0.getValueType(); 4004 4005 // fold (sint_to_fp c1) -> c1fp 4006 if (N0C && OpVT != MVT::ppcf128) 4007 return DAG.getNode(ISD::SINT_TO_FP, VT, N0); 4008 4009 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 4010 // but UINT_TO_FP is legal on this target, try to convert. 4011 if (!TLI.isOperationLegal(ISD::SINT_TO_FP, OpVT) && 4012 TLI.isOperationLegal(ISD::UINT_TO_FP, OpVT)) { 4013 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 4014 if (DAG.SignBitIsZero(N0)) 4015 return DAG.getNode(ISD::UINT_TO_FP, VT, N0); 4016 } 4017 4018 4019 return SDValue(); 4020} 4021 4022SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 4023 SDValue N0 = N->getOperand(0); 4024 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4025 MVT VT = N->getValueType(0); 4026 MVT OpVT = N0.getValueType(); 4027 4028 // fold (uint_to_fp c1) -> c1fp 4029 if (N0C && OpVT != MVT::ppcf128) 4030 return DAG.getNode(ISD::UINT_TO_FP, VT, N0); 4031 4032 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 4033 // but SINT_TO_FP is legal on this target, try to convert. 4034 if (!TLI.isOperationLegal(ISD::UINT_TO_FP, OpVT) && 4035 TLI.isOperationLegal(ISD::SINT_TO_FP, OpVT)) { 4036 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 4037 if (DAG.SignBitIsZero(N0)) 4038 return DAG.getNode(ISD::SINT_TO_FP, VT, N0); 4039 } 4040 4041 return SDValue(); 4042} 4043 4044SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 4045 SDValue N0 = N->getOperand(0); 4046 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4047 MVT VT = N->getValueType(0); 4048 4049 // fold (fp_to_sint c1fp) -> c1 4050 if (N0CFP) 4051 return DAG.getNode(ISD::FP_TO_SINT, VT, N0); 4052 return SDValue(); 4053} 4054 4055SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 4056 SDValue N0 = N->getOperand(0); 4057 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4058 MVT VT = N->getValueType(0); 4059 4060 // fold (fp_to_uint c1fp) -> c1 4061 if (N0CFP && VT != MVT::ppcf128) 4062 return DAG.getNode(ISD::FP_TO_UINT, VT, N0); 4063 return SDValue(); 4064} 4065 4066SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 4067 SDValue N0 = N->getOperand(0); 4068 SDValue N1 = N->getOperand(1); 4069 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4070 MVT VT = N->getValueType(0); 4071 4072 // fold (fp_round c1fp) -> c1fp 4073 if (N0CFP && N0.getValueType() != MVT::ppcf128) 4074 return DAG.getNode(ISD::FP_ROUND, VT, N0, N1); 4075 4076 // fold (fp_round (fp_extend x)) -> x 4077 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 4078 return N0.getOperand(0); 4079 4080 // fold (fp_round (fp_round x)) -> (fp_round x) 4081 if (N0.getOpcode() == ISD::FP_ROUND) { 4082 // This is a value preserving truncation if both round's are. 4083 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 4084 N0.getNode()->getConstantOperandVal(1) == 1; 4085 return DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0), 4086 DAG.getIntPtrConstant(IsTrunc)); 4087 } 4088 4089 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 4090 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { 4091 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0), N1); 4092 AddToWorkList(Tmp.getNode()); 4093 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1)); 4094 } 4095 4096 return SDValue(); 4097} 4098 4099SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 4100 SDValue N0 = N->getOperand(0); 4101 MVT VT = N->getValueType(0); 4102 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 4103 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4104 4105 // fold (fp_round_inreg c1fp) -> c1fp 4106 if (N0CFP && (TLI.isTypeLegal(EVT) || !LegalTypes)) { 4107 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT); 4108 return DAG.getNode(ISD::FP_EXTEND, VT, Round); 4109 } 4110 return SDValue(); 4111} 4112 4113SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 4114 SDValue N0 = N->getOperand(0); 4115 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4116 MVT VT = N->getValueType(0); 4117 4118 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 4119 if (N->hasOneUse() && 4120 N->use_begin().getUse().getSDValue().getOpcode() == ISD::FP_ROUND) 4121 return SDValue(); 4122 4123 // fold (fp_extend c1fp) -> c1fp 4124 if (N0CFP && VT != MVT::ppcf128) 4125 return DAG.getNode(ISD::FP_EXTEND, VT, N0); 4126 4127 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 4128 // value of X. 4129 if (N0.getOpcode() == ISD::FP_ROUND 4130 && N0.getNode()->getConstantOperandVal(1) == 1) { 4131 SDValue In = N0.getOperand(0); 4132 if (In.getValueType() == VT) return In; 4133 if (VT.bitsLT(In.getValueType())) 4134 return DAG.getNode(ISD::FP_ROUND, VT, In, N0.getOperand(1)); 4135 return DAG.getNode(ISD::FP_EXTEND, VT, In); 4136 } 4137 4138 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 4139 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 4140 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4141 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 4142 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4143 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 4144 LN0->getBasePtr(), LN0->getSrcValue(), 4145 LN0->getSrcValueOffset(), 4146 N0.getValueType(), 4147 LN0->isVolatile(), LN0->getAlignment()); 4148 CombineTo(N, ExtLoad); 4149 CombineTo(N0.getNode(), DAG.getNode(ISD::FP_ROUND, N0.getValueType(), 4150 ExtLoad, DAG.getIntPtrConstant(1)), 4151 ExtLoad.getValue(1)); 4152 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4153 } 4154 4155 return SDValue(); 4156} 4157 4158SDValue DAGCombiner::visitFNEG(SDNode *N) { 4159 SDValue N0 = N->getOperand(0); 4160 4161 if (isNegatibleForFree(N0, LegalOperations)) 4162 return GetNegatedExpression(N0, DAG, LegalOperations); 4163 4164 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 4165 // constant pool values. 4166 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() && 4167 N0.getOperand(0).getValueType().isInteger() && 4168 !N0.getOperand(0).getValueType().isVector()) { 4169 SDValue Int = N0.getOperand(0); 4170 MVT IntVT = Int.getValueType(); 4171 if (IntVT.isInteger() && !IntVT.isVector()) { 4172 Int = DAG.getNode(ISD::XOR, IntVT, Int, 4173 DAG.getConstant(IntVT.getIntegerVTSignBit(), IntVT)); 4174 AddToWorkList(Int.getNode()); 4175 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int); 4176 } 4177 } 4178 4179 return SDValue(); 4180} 4181 4182SDValue DAGCombiner::visitFABS(SDNode *N) { 4183 SDValue N0 = N->getOperand(0); 4184 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4185 MVT VT = N->getValueType(0); 4186 4187 // fold (fabs c1) -> fabs(c1) 4188 if (N0CFP && VT != MVT::ppcf128) 4189 return DAG.getNode(ISD::FABS, VT, N0); 4190 // fold (fabs (fabs x)) -> (fabs x) 4191 if (N0.getOpcode() == ISD::FABS) 4192 return N->getOperand(0); 4193 // fold (fabs (fneg x)) -> (fabs x) 4194 // fold (fabs (fcopysign x, y)) -> (fabs x) 4195 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 4196 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0)); 4197 4198 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 4199 // constant pool values. 4200 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() && 4201 N0.getOperand(0).getValueType().isInteger() && 4202 !N0.getOperand(0).getValueType().isVector()) { 4203 SDValue Int = N0.getOperand(0); 4204 MVT IntVT = Int.getValueType(); 4205 if (IntVT.isInteger() && !IntVT.isVector()) { 4206 Int = DAG.getNode(ISD::AND, IntVT, Int, 4207 DAG.getConstant(~IntVT.getIntegerVTSignBit(), IntVT)); 4208 AddToWorkList(Int.getNode()); 4209 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int); 4210 } 4211 } 4212 4213 return SDValue(); 4214} 4215 4216SDValue DAGCombiner::visitBRCOND(SDNode *N) { 4217 SDValue Chain = N->getOperand(0); 4218 SDValue N1 = N->getOperand(1); 4219 SDValue N2 = N->getOperand(2); 4220 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 4221 4222 // never taken branch, fold to chain 4223 if (N1C && N1C->isNullValue()) 4224 return Chain; 4225 // unconditional branch 4226 if (N1C && N1C->getAPIntValue() == 1) 4227 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 4228 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 4229 // on the target. 4230 if (N1.getOpcode() == ISD::SETCC && 4231 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) { 4232 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2), 4233 N1.getOperand(0), N1.getOperand(1), N2); 4234 } 4235 return SDValue(); 4236} 4237 4238// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 4239// 4240SDValue DAGCombiner::visitBR_CC(SDNode *N) { 4241 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 4242 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 4243 4244 // Use SimplifySetCC to simplify SETCC's. 4245 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS), 4246 CondLHS, CondRHS, CC->get(), false); 4247 if (Simp.getNode()) AddToWorkList(Simp.getNode()); 4248 4249 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.getNode()); 4250 4251 // fold br_cc true, dest -> br dest (unconditional branch) 4252 if (SCCC && !SCCC->isNullValue()) 4253 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0), 4254 N->getOperand(4)); 4255 // fold br_cc false, dest -> unconditional fall through 4256 if (SCCC && SCCC->isNullValue()) 4257 return N->getOperand(0); 4258 4259 // fold to a simpler setcc 4260 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) 4261 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0), 4262 Simp.getOperand(2), Simp.getOperand(0), 4263 Simp.getOperand(1), N->getOperand(4)); 4264 return SDValue(); 4265} 4266 4267 4268/// CombineToPreIndexedLoadStore - Try turning a load / store into a 4269/// pre-indexed load / store when the base pointer is an add or subtract 4270/// and it has other uses besides the load / store. After the 4271/// transformation, the new indexed load / store has effectively folded 4272/// the add / subtract in and all of its other uses are redirected to the 4273/// new load / store. 4274bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 4275 if (!LegalOperations) 4276 return false; 4277 4278 bool isLoad = true; 4279 SDValue Ptr; 4280 MVT VT; 4281 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4282 if (LD->isIndexed()) 4283 return false; 4284 VT = LD->getMemoryVT(); 4285 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 4286 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 4287 return false; 4288 Ptr = LD->getBasePtr(); 4289 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4290 if (ST->isIndexed()) 4291 return false; 4292 VT = ST->getMemoryVT(); 4293 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 4294 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 4295 return false; 4296 Ptr = ST->getBasePtr(); 4297 isLoad = false; 4298 } else 4299 return false; 4300 4301 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 4302 // out. There is no reason to make this a preinc/predec. 4303 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 4304 Ptr.getNode()->hasOneUse()) 4305 return false; 4306 4307 // Ask the target to do addressing mode selection. 4308 SDValue BasePtr; 4309 SDValue Offset; 4310 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4311 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 4312 return false; 4313 // Don't create a indexed load / store with zero offset. 4314 if (isa<ConstantSDNode>(Offset) && 4315 cast<ConstantSDNode>(Offset)->isNullValue()) 4316 return false; 4317 4318 // Try turning it into a pre-indexed load / store except when: 4319 // 1) The new base ptr is a frame index. 4320 // 2) If N is a store and the new base ptr is either the same as or is a 4321 // predecessor of the value being stored. 4322 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 4323 // that would create a cycle. 4324 // 4) All uses are load / store ops that use it as old base ptr. 4325 4326 // Check #1. Preinc'ing a frame index would require copying the stack pointer 4327 // (plus the implicit offset) to a register to preinc anyway. 4328 if (isa<FrameIndexSDNode>(BasePtr)) 4329 return false; 4330 4331 // Check #2. 4332 if (!isLoad) { 4333 SDValue Val = cast<StoreSDNode>(N)->getValue(); 4334 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode())) 4335 return false; 4336 } 4337 4338 // Now check for #3 and #4. 4339 bool RealUse = false; 4340 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 4341 E = Ptr.getNode()->use_end(); I != E; ++I) { 4342 SDNode *Use = *I; 4343 if (Use == N) 4344 continue; 4345 if (Use->isPredecessorOf(N)) 4346 return false; 4347 4348 if (!((Use->getOpcode() == ISD::LOAD && 4349 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 4350 (Use->getOpcode() == ISD::STORE && 4351 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))) 4352 RealUse = true; 4353 } 4354 if (!RealUse) 4355 return false; 4356 4357 SDValue Result; 4358 if (isLoad) 4359 Result = DAG.getIndexedLoad(SDValue(N,0), BasePtr, Offset, AM); 4360 else 4361 Result = DAG.getIndexedStore(SDValue(N,0), BasePtr, Offset, AM); 4362 ++PreIndexedNodes; 4363 ++NodesCombined; 4364 DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG)); 4365 DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG)); 4366 DOUT << '\n'; 4367 WorkListRemover DeadNodes(*this); 4368 if (isLoad) { 4369 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 4370 &DeadNodes); 4371 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 4372 &DeadNodes); 4373 } else { 4374 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 4375 &DeadNodes); 4376 } 4377 4378 // Finally, since the node is now dead, remove it from the graph. 4379 DAG.DeleteNode(N); 4380 4381 // Replace the uses of Ptr with uses of the updated base value. 4382 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 4383 &DeadNodes); 4384 removeFromWorkList(Ptr.getNode()); 4385 DAG.DeleteNode(Ptr.getNode()); 4386 4387 return true; 4388} 4389 4390/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 4391/// add / sub of the base pointer node into a post-indexed load / store. 4392/// The transformation folded the add / subtract into the new indexed 4393/// load / store effectively and all of its uses are redirected to the 4394/// new load / store. 4395bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 4396 if (!LegalOperations) 4397 return false; 4398 4399 bool isLoad = true; 4400 SDValue Ptr; 4401 MVT VT; 4402 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4403 if (LD->isIndexed()) 4404 return false; 4405 VT = LD->getMemoryVT(); 4406 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 4407 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 4408 return false; 4409 Ptr = LD->getBasePtr(); 4410 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4411 if (ST->isIndexed()) 4412 return false; 4413 VT = ST->getMemoryVT(); 4414 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 4415 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 4416 return false; 4417 Ptr = ST->getBasePtr(); 4418 isLoad = false; 4419 } else 4420 return false; 4421 4422 if (Ptr.getNode()->hasOneUse()) 4423 return false; 4424 4425 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 4426 E = Ptr.getNode()->use_end(); I != E; ++I) { 4427 SDNode *Op = *I; 4428 if (Op == N || 4429 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 4430 continue; 4431 4432 SDValue BasePtr; 4433 SDValue Offset; 4434 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4435 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 4436 if (Ptr == Offset) 4437 std::swap(BasePtr, Offset); 4438 if (Ptr != BasePtr) 4439 continue; 4440 // Don't create a indexed load / store with zero offset. 4441 if (isa<ConstantSDNode>(Offset) && 4442 cast<ConstantSDNode>(Offset)->isNullValue()) 4443 continue; 4444 4445 // Try turning it into a post-indexed load / store except when 4446 // 1) All uses are load / store ops that use it as base ptr. 4447 // 2) Op must be independent of N, i.e. Op is neither a predecessor 4448 // nor a successor of N. Otherwise, if Op is folded that would 4449 // create a cycle. 4450 4451 // Check for #1. 4452 bool TryNext = false; 4453 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), 4454 EE = BasePtr.getNode()->use_end(); II != EE; ++II) { 4455 SDNode *Use = *II; 4456 if (Use == Ptr.getNode()) 4457 continue; 4458 4459 // If all the uses are load / store addresses, then don't do the 4460 // transformation. 4461 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 4462 bool RealUse = false; 4463 for (SDNode::use_iterator III = Use->use_begin(), 4464 EEE = Use->use_end(); III != EEE; ++III) { 4465 SDNode *UseUse = *III; 4466 if (!((UseUse->getOpcode() == ISD::LOAD && 4467 cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) || 4468 (UseUse->getOpcode() == ISD::STORE && 4469 cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use))) 4470 RealUse = true; 4471 } 4472 4473 if (!RealUse) { 4474 TryNext = true; 4475 break; 4476 } 4477 } 4478 } 4479 if (TryNext) 4480 continue; 4481 4482 // Check for #2 4483 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 4484 SDValue Result = isLoad 4485 ? DAG.getIndexedLoad(SDValue(N,0), BasePtr, Offset, AM) 4486 : DAG.getIndexedStore(SDValue(N,0), BasePtr, Offset, AM); 4487 ++PostIndexedNodes; 4488 ++NodesCombined; 4489 DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG)); 4490 DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG)); 4491 DOUT << '\n'; 4492 WorkListRemover DeadNodes(*this); 4493 if (isLoad) { 4494 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 4495 &DeadNodes); 4496 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 4497 &DeadNodes); 4498 } else { 4499 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 4500 &DeadNodes); 4501 } 4502 4503 // Finally, since the node is now dead, remove it from the graph. 4504 DAG.DeleteNode(N); 4505 4506 // Replace the uses of Use with uses of the updated base value. 4507 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 4508 Result.getValue(isLoad ? 1 : 0), 4509 &DeadNodes); 4510 removeFromWorkList(Op); 4511 DAG.DeleteNode(Op); 4512 return true; 4513 } 4514 } 4515 } 4516 return false; 4517} 4518 4519/// InferAlignment - If we can infer some alignment information from this 4520/// pointer, return it. 4521static unsigned InferAlignment(SDValue Ptr, SelectionDAG &DAG) { 4522 // If this is a direct reference to a stack slot, use information about the 4523 // stack slot's alignment. 4524 int FrameIdx = 1 << 31; 4525 int64_t FrameOffset = 0; 4526 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Ptr)) { 4527 FrameIdx = FI->getIndex(); 4528 } else if (Ptr.getOpcode() == ISD::ADD && 4529 isa<ConstantSDNode>(Ptr.getOperand(1)) && 4530 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 4531 FrameIdx = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 4532 FrameOffset = Ptr.getConstantOperandVal(1); 4533 } 4534 4535 if (FrameIdx != (1 << 31)) { 4536 // FIXME: Handle FI+CST. 4537 const MachineFrameInfo &MFI = *DAG.getMachineFunction().getFrameInfo(); 4538 if (MFI.isFixedObjectIndex(FrameIdx)) { 4539 int64_t ObjectOffset = MFI.getObjectOffset(FrameIdx) + FrameOffset; 4540 4541 // The alignment of the frame index can be determined from its offset from 4542 // the incoming frame position. If the frame object is at offset 32 and 4543 // the stack is guaranteed to be 16-byte aligned, then we know that the 4544 // object is 16-byte aligned. 4545 unsigned StackAlign = DAG.getTarget().getFrameInfo()->getStackAlignment(); 4546 unsigned Align = MinAlign(ObjectOffset, StackAlign); 4547 4548 // Finally, the frame object itself may have a known alignment. Factor 4549 // the alignment + offset into a new alignment. For example, if we know 4550 // the FI is 8 byte aligned, but the pointer is 4 off, we really have a 4551 // 4-byte alignment of the resultant pointer. Likewise align 4 + 4-byte 4552 // offset = 4-byte alignment, align 4 + 1-byte offset = align 1, etc. 4553 unsigned FIInfoAlign = MinAlign(MFI.getObjectAlignment(FrameIdx), 4554 FrameOffset); 4555 return std::max(Align, FIInfoAlign); 4556 } 4557 } 4558 4559 return 0; 4560} 4561 4562SDValue DAGCombiner::visitLOAD(SDNode *N) { 4563 LoadSDNode *LD = cast<LoadSDNode>(N); 4564 SDValue Chain = LD->getChain(); 4565 SDValue Ptr = LD->getBasePtr(); 4566 4567 // Try to infer better alignment information than the load already has. 4568 if (!Fast && LD->isUnindexed()) { 4569 if (unsigned Align = InferAlignment(Ptr, DAG)) { 4570 if (Align > LD->getAlignment()) 4571 return DAG.getExtLoad(LD->getExtensionType(), LD->getValueType(0), 4572 Chain, Ptr, LD->getSrcValue(), 4573 LD->getSrcValueOffset(), LD->getMemoryVT(), 4574 LD->isVolatile(), Align); 4575 } 4576 } 4577 4578 4579 // If load is not volatile and there are no uses of the loaded value (and 4580 // the updated indexed value in case of indexed loads), change uses of the 4581 // chain value into uses of the chain input (i.e. delete the dead load). 4582 if (!LD->isVolatile()) { 4583 if (N->getValueType(1) == MVT::Other) { 4584 // Unindexed loads. 4585 if (N->hasNUsesOfValue(0, 0)) { 4586 // It's not safe to use the two value CombineTo variant here. e.g. 4587 // v1, chain2 = load chain1, loc 4588 // v2, chain3 = load chain2, loc 4589 // v3 = add v2, c 4590 // Now we replace use of chain2 with chain1. This makes the second load 4591 // isomorphic to the one we are deleting, and thus makes this load live. 4592 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4593 DOUT << "\nWith chain: "; DEBUG(Chain.getNode()->dump(&DAG)); 4594 DOUT << "\n"; 4595 WorkListRemover DeadNodes(*this); 4596 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes); 4597 if (N->use_empty()) { 4598 removeFromWorkList(N); 4599 DAG.DeleteNode(N); 4600 } 4601 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4602 } 4603 } else { 4604 // Indexed loads. 4605 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 4606 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 4607 SDValue Undef = DAG.getNode(ISD::UNDEF, N->getValueType(0)); 4608 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4609 DOUT << "\nWith: "; DEBUG(Undef.getNode()->dump(&DAG)); 4610 DOUT << " and 2 other values\n"; 4611 WorkListRemover DeadNodes(*this); 4612 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes); 4613 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 4614 DAG.getNode(ISD::UNDEF, N->getValueType(1)), 4615 &DeadNodes); 4616 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes); 4617 removeFromWorkList(N); 4618 DAG.DeleteNode(N); 4619 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4620 } 4621 } 4622 } 4623 4624 // If this load is directly stored, replace the load value with the stored 4625 // value. 4626 // TODO: Handle store large -> read small portion. 4627 // TODO: Handle TRUNCSTORE/LOADEXT 4628 if (LD->getExtensionType() == ISD::NON_EXTLOAD && 4629 !LD->isVolatile()) { 4630 if (ISD::isNON_TRUNCStore(Chain.getNode())) { 4631 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 4632 if (PrevST->getBasePtr() == Ptr && 4633 PrevST->getValue().getValueType() == N->getValueType(0)) 4634 return CombineTo(N, Chain.getOperand(1), Chain); 4635 } 4636 } 4637 4638 if (CombinerAA) { 4639 // Walk up chain skipping non-aliasing memory nodes. 4640 SDValue BetterChain = FindBetterChain(N, Chain); 4641 4642 // If there is a better chain. 4643 if (Chain != BetterChain) { 4644 SDValue ReplLoad; 4645 4646 // Replace the chain to void dependency. 4647 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 4648 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr, 4649 LD->getSrcValue(), LD->getSrcValueOffset(), 4650 LD->isVolatile(), LD->getAlignment()); 4651 } else { 4652 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), 4653 LD->getValueType(0), 4654 BetterChain, Ptr, LD->getSrcValue(), 4655 LD->getSrcValueOffset(), 4656 LD->getMemoryVT(), 4657 LD->isVolatile(), 4658 LD->getAlignment()); 4659 } 4660 4661 // Create token factor to keep old chain connected. 4662 SDValue Token = DAG.getNode(ISD::TokenFactor, MVT::Other, 4663 Chain, ReplLoad.getValue(1)); 4664 4665 // Replace uses with load result and token factor. Don't add users 4666 // to work list. 4667 return CombineTo(N, ReplLoad.getValue(0), Token, false); 4668 } 4669 } 4670 4671 // Try transforming N to an indexed load. 4672 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4673 return SDValue(N, 0); 4674 4675 return SDValue(); 4676} 4677 4678 4679SDValue DAGCombiner::visitSTORE(SDNode *N) { 4680 StoreSDNode *ST = cast<StoreSDNode>(N); 4681 SDValue Chain = ST->getChain(); 4682 SDValue Value = ST->getValue(); 4683 SDValue Ptr = ST->getBasePtr(); 4684 4685 // Try to infer better alignment information than the store already has. 4686 if (!Fast && ST->isUnindexed()) { 4687 if (unsigned Align = InferAlignment(Ptr, DAG)) { 4688 if (Align > ST->getAlignment()) 4689 return DAG.getTruncStore(Chain, Value, Ptr, ST->getSrcValue(), 4690 ST->getSrcValueOffset(), ST->getMemoryVT(), 4691 ST->isVolatile(), Align); 4692 } 4693 } 4694 4695 // If this is a store of a bit convert, store the input value if the 4696 // resultant store does not need a higher alignment than the original. 4697 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() && 4698 ST->isUnindexed()) { 4699 unsigned Align = ST->getAlignment(); 4700 MVT SVT = Value.getOperand(0).getValueType(); 4701 unsigned OrigAlign = TLI.getTargetData()-> 4702 getABITypeAlignment(SVT.getTypeForMVT()); 4703 if (Align <= OrigAlign && 4704 ((!LegalOperations && !ST->isVolatile()) || 4705 TLI.isOperationLegal(ISD::STORE, SVT))) 4706 return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), 4707 ST->getSrcValueOffset(), ST->isVolatile(), OrigAlign); 4708 } 4709 4710 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 4711 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 4712 // NOTE: If the original store is volatile, this transform must not increase 4713 // the number of stores. For example, on x86-32 an f64 can be stored in one 4714 // processor operation but an i64 (which is not legal) requires two. So the 4715 // transform should not be done in this case. 4716 if (Value.getOpcode() != ISD::TargetConstantFP) { 4717 SDValue Tmp; 4718 switch (CFP->getValueType(0).getSimpleVT()) { 4719 default: assert(0 && "Unknown FP type"); 4720 case MVT::f80: // We don't do this for these yet. 4721 case MVT::f128: 4722 case MVT::ppcf128: 4723 break; 4724 case MVT::f32: 4725 if (((TLI.isTypeLegal(MVT::i32) || !LegalTypes) && !LegalOperations && 4726 !ST->isVolatile()) || TLI.isOperationLegal(ISD::STORE, MVT::i32)) { 4727 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 4728 bitcastToAPInt().getZExtValue(), MVT::i32); 4729 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 4730 ST->getSrcValueOffset(), ST->isVolatile(), 4731 ST->getAlignment()); 4732 } 4733 break; 4734 case MVT::f64: 4735 if (((TLI.isTypeLegal(MVT::i64) || !LegalTypes) && !LegalOperations && 4736 !ST->isVolatile()) || TLI.isOperationLegal(ISD::STORE, MVT::i64)) { 4737 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 4738 getZExtValue(), MVT::i64); 4739 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 4740 ST->getSrcValueOffset(), ST->isVolatile(), 4741 ST->getAlignment()); 4742 } else if (!ST->isVolatile() && 4743 TLI.isOperationLegal(ISD::STORE, MVT::i32)) { 4744 // Many FP stores are not made apparent until after legalize, e.g. for 4745 // argument passing. Since this is so common, custom legalize the 4746 // 64-bit integer store into two 32-bit stores. 4747 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); 4748 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 4749 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 4750 if (TLI.isBigEndian()) std::swap(Lo, Hi); 4751 4752 int SVOffset = ST->getSrcValueOffset(); 4753 unsigned Alignment = ST->getAlignment(); 4754 bool isVolatile = ST->isVolatile(); 4755 4756 SDValue St0 = DAG.getStore(Chain, Lo, Ptr, ST->getSrcValue(), 4757 ST->getSrcValueOffset(), 4758 isVolatile, ST->getAlignment()); 4759 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 4760 DAG.getConstant(4, Ptr.getValueType())); 4761 SVOffset += 4; 4762 Alignment = MinAlign(Alignment, 4U); 4763 SDValue St1 = DAG.getStore(Chain, Hi, Ptr, ST->getSrcValue(), 4764 SVOffset, isVolatile, Alignment); 4765 return DAG.getNode(ISD::TokenFactor, MVT::Other, St0, St1); 4766 } 4767 break; 4768 } 4769 } 4770 } 4771 4772 if (CombinerAA) { 4773 // Walk up chain skipping non-aliasing memory nodes. 4774 SDValue BetterChain = FindBetterChain(N, Chain); 4775 4776 // If there is a better chain. 4777 if (Chain != BetterChain) { 4778 // Replace the chain to avoid dependency. 4779 SDValue ReplStore; 4780 if (ST->isTruncatingStore()) { 4781 ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr, 4782 ST->getSrcValue(),ST->getSrcValueOffset(), 4783 ST->getMemoryVT(), 4784 ST->isVolatile(), ST->getAlignment()); 4785 } else { 4786 ReplStore = DAG.getStore(BetterChain, Value, Ptr, 4787 ST->getSrcValue(), ST->getSrcValueOffset(), 4788 ST->isVolatile(), ST->getAlignment()); 4789 } 4790 4791 // Create token to keep both nodes around. 4792 SDValue Token = 4793 DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore); 4794 4795 // Don't add users to work list. 4796 return CombineTo(N, Token, false); 4797 } 4798 } 4799 4800 // Try transforming N to an indexed store. 4801 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4802 return SDValue(N, 0); 4803 4804 // FIXME: is there such a thing as a truncating indexed store? 4805 if (ST->isTruncatingStore() && ST->isUnindexed() && 4806 Value.getValueType().isInteger()) { 4807 // See if we can simplify the input to this truncstore with knowledge that 4808 // only the low bits are being used. For example: 4809 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 4810 SDValue Shorter = 4811 GetDemandedBits(Value, 4812 APInt::getLowBitsSet(Value.getValueSizeInBits(), 4813 ST->getMemoryVT().getSizeInBits())); 4814 AddToWorkList(Value.getNode()); 4815 if (Shorter.getNode()) 4816 return DAG.getTruncStore(Chain, Shorter, Ptr, ST->getSrcValue(), 4817 ST->getSrcValueOffset(), ST->getMemoryVT(), 4818 ST->isVolatile(), ST->getAlignment()); 4819 4820 // Otherwise, see if we can simplify the operation with 4821 // SimplifyDemandedBits, which only works if the value has a single use. 4822 if (SimplifyDemandedBits(Value, 4823 APInt::getLowBitsSet( 4824 Value.getValueSizeInBits(), 4825 ST->getMemoryVT().getSizeInBits()))) 4826 return SDValue(N, 0); 4827 } 4828 4829 // If this is a load followed by a store to the same location, then the store 4830 // is dead/noop. 4831 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 4832 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 4833 ST->isUnindexed() && !ST->isVolatile() && 4834 // There can't be any side effects between the load and store, such as 4835 // a call or store. 4836 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 4837 // The store is dead, remove it. 4838 return Chain; 4839 } 4840 } 4841 4842 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 4843 // truncating store. We can do this even if this is already a truncstore. 4844 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 4845 && Value.getNode()->hasOneUse() && ST->isUnindexed() && 4846 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 4847 ST->getMemoryVT())) { 4848 return DAG.getTruncStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), 4849 ST->getSrcValueOffset(), ST->getMemoryVT(), 4850 ST->isVolatile(), ST->getAlignment()); 4851 } 4852 4853 return SDValue(); 4854} 4855 4856SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 4857 SDValue InVec = N->getOperand(0); 4858 SDValue InVal = N->getOperand(1); 4859 SDValue EltNo = N->getOperand(2); 4860 4861 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 4862 // vector with the inserted element. 4863 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 4864 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 4865 SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(), 4866 InVec.getNode()->op_end()); 4867 if (Elt < Ops.size()) 4868 Ops[Elt] = InVal; 4869 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(), 4870 &Ops[0], Ops.size()); 4871 } 4872 4873 return SDValue(); 4874} 4875 4876SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 4877 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 4878 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 4879 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 4880 4881 // Perform only after legalization to ensure build_vector / vector_shuffle 4882 // optimizations have already been done. 4883 if (!LegalOperations) return SDValue(); 4884 4885 SDValue InVec = N->getOperand(0); 4886 SDValue EltNo = N->getOperand(1); 4887 4888 if (isa<ConstantSDNode>(EltNo)) { 4889 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 4890 bool NewLoad = false; 4891 bool BCNumEltsChanged = false; 4892 MVT VT = InVec.getValueType(); 4893 MVT EVT = VT.getVectorElementType(); 4894 MVT LVT = EVT; 4895 if (InVec.getOpcode() == ISD::BIT_CONVERT) { 4896 MVT BCVT = InVec.getOperand(0).getValueType(); 4897 if (!BCVT.isVector() || EVT.bitsGT(BCVT.getVectorElementType())) 4898 return SDValue(); 4899 if (VT.getVectorNumElements() != BCVT.getVectorNumElements()) 4900 BCNumEltsChanged = true; 4901 InVec = InVec.getOperand(0); 4902 EVT = BCVT.getVectorElementType(); 4903 NewLoad = true; 4904 } 4905 4906 LoadSDNode *LN0 = NULL; 4907 if (ISD::isNormalLoad(InVec.getNode())) 4908 LN0 = cast<LoadSDNode>(InVec); 4909 else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 4910 InVec.getOperand(0).getValueType() == EVT && 4911 ISD::isNormalLoad(InVec.getOperand(0).getNode())) { 4912 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 4913 } else if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE) { 4914 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 4915 // => 4916 // (load $addr+1*size) 4917 4918 // If the bit convert changed the number of elements, it is unsafe 4919 // to examine the mask. 4920 if (BCNumEltsChanged) 4921 return SDValue(); 4922 unsigned Idx = cast<ConstantSDNode>(InVec.getOperand(2). 4923 getOperand(Elt))->getZExtValue(); 4924 unsigned NumElems = InVec.getOperand(2).getNumOperands(); 4925 InVec = (Idx < NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 4926 if (InVec.getOpcode() == ISD::BIT_CONVERT) 4927 InVec = InVec.getOperand(0); 4928 if (ISD::isNormalLoad(InVec.getNode())) { 4929 LN0 = cast<LoadSDNode>(InVec); 4930 Elt = (Idx < NumElems) ? Idx : Idx - NumElems; 4931 } 4932 } 4933 if (!LN0 || !LN0->hasOneUse() || LN0->isVolatile()) 4934 return SDValue(); 4935 4936 unsigned Align = LN0->getAlignment(); 4937 if (NewLoad) { 4938 // Check the resultant load doesn't need a higher alignment than the 4939 // original load. 4940 unsigned NewAlign = TLI.getTargetData()-> 4941 getABITypeAlignment(LVT.getTypeForMVT()); 4942 if (NewAlign > Align || !TLI.isOperationLegal(ISD::LOAD, LVT)) 4943 return SDValue(); 4944 Align = NewAlign; 4945 } 4946 4947 SDValue NewPtr = LN0->getBasePtr(); 4948 if (Elt) { 4949 unsigned PtrOff = LVT.getSizeInBits() * Elt / 8; 4950 MVT PtrType = NewPtr.getValueType(); 4951 if (TLI.isBigEndian()) 4952 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 4953 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, 4954 DAG.getConstant(PtrOff, PtrType)); 4955 } 4956 return DAG.getLoad(LVT, LN0->getChain(), NewPtr, 4957 LN0->getSrcValue(), LN0->getSrcValueOffset(), 4958 LN0->isVolatile(), Align); 4959 } 4960 return SDValue(); 4961} 4962 4963 4964SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 4965 unsigned NumInScalars = N->getNumOperands(); 4966 MVT VT = N->getValueType(0); 4967 unsigned NumElts = VT.getVectorNumElements(); 4968 MVT EltType = VT.getVectorElementType(); 4969 4970 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 4971 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 4972 // at most two distinct vectors, turn this into a shuffle node. 4973 SDValue VecIn1, VecIn2; 4974 for (unsigned i = 0; i != NumInScalars; ++i) { 4975 // Ignore undef inputs. 4976 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 4977 4978 // If this input is something other than a EXTRACT_VECTOR_ELT with a 4979 // constant index, bail out. 4980 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 4981 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 4982 VecIn1 = VecIn2 = SDValue(0, 0); 4983 break; 4984 } 4985 4986 // If the input vector type disagrees with the result of the build_vector, 4987 // we can't make a shuffle. 4988 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 4989 if (ExtractedFromVec.getValueType() != VT) { 4990 VecIn1 = VecIn2 = SDValue(0, 0); 4991 break; 4992 } 4993 4994 // Otherwise, remember this. We allow up to two distinct input vectors. 4995 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 4996 continue; 4997 4998 if (VecIn1.getNode() == 0) { 4999 VecIn1 = ExtractedFromVec; 5000 } else if (VecIn2.getNode() == 0) { 5001 VecIn2 = ExtractedFromVec; 5002 } else { 5003 // Too many inputs. 5004 VecIn1 = VecIn2 = SDValue(0, 0); 5005 break; 5006 } 5007 } 5008 5009 // If everything is good, we can make a shuffle operation. 5010 if (VecIn1.getNode()) { 5011 SmallVector<SDValue, 8> BuildVecIndices; 5012 for (unsigned i = 0; i != NumInScalars; ++i) { 5013 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 5014 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, TLI.getPointerTy())); 5015 continue; 5016 } 5017 5018 SDValue Extract = N->getOperand(i); 5019 5020 // If extracting from the first vector, just use the index directly. 5021 if (Extract.getOperand(0) == VecIn1) { 5022 BuildVecIndices.push_back(Extract.getOperand(1)); 5023 continue; 5024 } 5025 5026 // Otherwise, use InIdx + VecSize 5027 unsigned Idx = 5028 cast<ConstantSDNode>(Extract.getOperand(1))->getZExtValue(); 5029 BuildVecIndices.push_back(DAG.getIntPtrConstant(Idx+NumInScalars)); 5030 } 5031 5032 // Add count and size info. 5033 MVT BuildVecVT = MVT::getVectorVT(TLI.getPointerTy(), NumElts); 5034 if (!TLI.isTypeLegal(BuildVecVT) && LegalTypes) 5035 return SDValue(); 5036 5037 // Return the new VECTOR_SHUFFLE node. 5038 SDValue Ops[5]; 5039 Ops[0] = VecIn1; 5040 if (VecIn2.getNode()) { 5041 Ops[1] = VecIn2; 5042 } else { 5043 // Use an undef build_vector as input for the second operand. 5044 std::vector<SDValue> UnOps(NumInScalars, 5045 DAG.getNode(ISD::UNDEF, 5046 EltType)); 5047 Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, VT, 5048 &UnOps[0], UnOps.size()); 5049 AddToWorkList(Ops[1].getNode()); 5050 } 5051 Ops[2] = DAG.getNode(ISD::BUILD_VECTOR, BuildVecVT, 5052 &BuildVecIndices[0], BuildVecIndices.size()); 5053 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Ops, 3); 5054 } 5055 5056 return SDValue(); 5057} 5058 5059SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 5060 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 5061 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 5062 // inputs come from at most two distinct vectors, turn this into a shuffle 5063 // node. 5064 5065 // If we only have one input vector, we don't need to do any concatenation. 5066 if (N->getNumOperands() == 1) { 5067 return N->getOperand(0); 5068 } 5069 5070 return SDValue(); 5071} 5072 5073SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 5074 SDValue ShufMask = N->getOperand(2); 5075 unsigned NumElts = ShufMask.getNumOperands(); 5076 5077 SDValue N0 = N->getOperand(0); 5078 SDValue N1 = N->getOperand(1); 5079 5080 assert(N0.getValueType().getVectorNumElements() == NumElts && 5081 "Vector shuffle must be normalized in DAG"); 5082 5083 // If the shuffle mask is an identity operation on the LHS, return the LHS. 5084 bool isIdentity = true; 5085 for (unsigned i = 0; i != NumElts; ++i) { 5086 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 5087 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() != i) { 5088 isIdentity = false; 5089 break; 5090 } 5091 } 5092 if (isIdentity) return N->getOperand(0); 5093 5094 // If the shuffle mask is an identity operation on the RHS, return the RHS. 5095 isIdentity = true; 5096 for (unsigned i = 0; i != NumElts; ++i) { 5097 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 5098 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() != 5099 i+NumElts) { 5100 isIdentity = false; 5101 break; 5102 } 5103 } 5104 if (isIdentity) return N->getOperand(1); 5105 5106 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not 5107 // needed at all. 5108 bool isUnary = true; 5109 bool isSplat = true; 5110 int VecNum = -1; 5111 unsigned BaseIdx = 0; 5112 for (unsigned i = 0; i != NumElts; ++i) 5113 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) { 5114 unsigned Idx=cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue(); 5115 int V = (Idx < NumElts) ? 0 : 1; 5116 if (VecNum == -1) { 5117 VecNum = V; 5118 BaseIdx = Idx; 5119 } else { 5120 if (BaseIdx != Idx) 5121 isSplat = false; 5122 if (VecNum != V) { 5123 isUnary = false; 5124 break; 5125 } 5126 } 5127 } 5128 5129 // Normalize unary shuffle so the RHS is undef. 5130 if (isUnary && VecNum == 1) 5131 std::swap(N0, N1); 5132 5133 // If it is a splat, check if the argument vector is a build_vector with 5134 // all scalar elements the same. 5135 if (isSplat) { 5136 SDNode *V = N0.getNode(); 5137 5138 // If this is a bit convert that changes the element type of the vector but 5139 // not the number of vector elements, look through it. Be careful not to 5140 // look though conversions that change things like v4f32 to v2f64. 5141 if (V->getOpcode() == ISD::BIT_CONVERT) { 5142 SDValue ConvInput = V->getOperand(0); 5143 if (ConvInput.getValueType().isVector() && 5144 ConvInput.getValueType().getVectorNumElements() == NumElts) 5145 V = ConvInput.getNode(); 5146 } 5147 5148 if (V->getOpcode() == ISD::BUILD_VECTOR) { 5149 unsigned NumElems = V->getNumOperands(); 5150 if (NumElems > BaseIdx) { 5151 SDValue Base; 5152 bool AllSame = true; 5153 for (unsigned i = 0; i != NumElems; ++i) { 5154 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 5155 Base = V->getOperand(i); 5156 break; 5157 } 5158 } 5159 // Splat of <u, u, u, u>, return <u, u, u, u> 5160 if (!Base.getNode()) 5161 return N0; 5162 for (unsigned i = 0; i != NumElems; ++i) { 5163 if (V->getOperand(i) != Base) { 5164 AllSame = false; 5165 break; 5166 } 5167 } 5168 // Splat of <x, x, x, x>, return <x, x, x, x> 5169 if (AllSame) 5170 return N0; 5171 } 5172 } 5173 } 5174 5175 // If it is a unary or the LHS and the RHS are the same node, turn the RHS 5176 // into an undef. 5177 if (isUnary || N0 == N1) { 5178 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the 5179 // first operand. 5180 SmallVector<SDValue, 8> MappedOps; 5181 for (unsigned i = 0; i != NumElts; ++i) { 5182 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || 5183 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() < 5184 NumElts) { 5185 MappedOps.push_back(ShufMask.getOperand(i)); 5186 } else { 5187 unsigned NewIdx = 5188 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() - 5189 NumElts; 5190 MappedOps.push_back(DAG.getConstant(NewIdx, 5191 ShufMask.getOperand(i).getValueType())); 5192 } 5193 } 5194 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(), 5195 &MappedOps[0], MappedOps.size()); 5196 AddToWorkList(ShufMask.getNode()); 5197 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0), 5198 N0, 5199 DAG.getNode(ISD::UNDEF, N->getValueType(0)), 5200 ShufMask); 5201 } 5202 5203 return SDValue(); 5204} 5205 5206/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 5207/// an AND to a vector_shuffle with the destination vector and a zero vector. 5208/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 5209/// vector_shuffle V, Zero, <0, 4, 2, 4> 5210SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 5211 SDValue LHS = N->getOperand(0); 5212 SDValue RHS = N->getOperand(1); 5213 if (N->getOpcode() == ISD::AND) { 5214 if (RHS.getOpcode() == ISD::BIT_CONVERT) 5215 RHS = RHS.getOperand(0); 5216 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 5217 std::vector<SDValue> IdxOps; 5218 unsigned NumOps = RHS.getNumOperands(); 5219 unsigned NumElts = NumOps; 5220 for (unsigned i = 0; i != NumElts; ++i) { 5221 SDValue Elt = RHS.getOperand(i); 5222 if (!isa<ConstantSDNode>(Elt)) 5223 return SDValue(); 5224 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 5225 IdxOps.push_back(DAG.getIntPtrConstant(i)); 5226 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 5227 IdxOps.push_back(DAG.getIntPtrConstant(NumElts)); 5228 else 5229 return SDValue(); 5230 } 5231 5232 // Let's see if the target supports this vector_shuffle. 5233 if (!TLI.isVectorClearMaskLegal(IdxOps, TLI.getPointerTy(), DAG)) 5234 return SDValue(); 5235 5236 // Return the new VECTOR_SHUFFLE node. 5237 MVT EVT = RHS.getValueType().getVectorElementType(); 5238 MVT VT = MVT::getVectorVT(EVT, NumElts); 5239 MVT MaskVT = MVT::getVectorVT(TLI.getPointerTy(), NumElts); 5240 std::vector<SDValue> Ops; 5241 LHS = DAG.getNode(ISD::BIT_CONVERT, VT, LHS); 5242 Ops.push_back(LHS); 5243 AddToWorkList(LHS.getNode()); 5244 std::vector<SDValue> ZeroOps(NumElts, DAG.getConstant(0, EVT)); 5245 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT, 5246 &ZeroOps[0], ZeroOps.size())); 5247 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 5248 &IdxOps[0], IdxOps.size())); 5249 SDValue Result = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, 5250 &Ops[0], Ops.size()); 5251 if (VT != N->getValueType(0)) 5252 Result = DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Result); 5253 return Result; 5254 } 5255 } 5256 return SDValue(); 5257} 5258 5259/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 5260SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 5261 // After legalize, the target may be depending on adds and other 5262 // binary ops to provide legal ways to construct constants or other 5263 // things. Simplifying them may result in a loss of legality. 5264 if (LegalOperations) return SDValue(); 5265 5266 MVT VT = N->getValueType(0); 5267 assert(VT.isVector() && "SimplifyVBinOp only works on vectors!"); 5268 5269 MVT EltType = VT.getVectorElementType(); 5270 SDValue LHS = N->getOperand(0); 5271 SDValue RHS = N->getOperand(1); 5272 SDValue Shuffle = XformToShuffleWithZero(N); 5273 if (Shuffle.getNode()) return Shuffle; 5274 5275 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 5276 // this operation. 5277 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 5278 RHS.getOpcode() == ISD::BUILD_VECTOR) { 5279 SmallVector<SDValue, 8> Ops; 5280 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 5281 SDValue LHSOp = LHS.getOperand(i); 5282 SDValue RHSOp = RHS.getOperand(i); 5283 // If these two elements can't be folded, bail out. 5284 if ((LHSOp.getOpcode() != ISD::UNDEF && 5285 LHSOp.getOpcode() != ISD::Constant && 5286 LHSOp.getOpcode() != ISD::ConstantFP) || 5287 (RHSOp.getOpcode() != ISD::UNDEF && 5288 RHSOp.getOpcode() != ISD::Constant && 5289 RHSOp.getOpcode() != ISD::ConstantFP)) 5290 break; 5291 // Can't fold divide by zero. 5292 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 5293 N->getOpcode() == ISD::FDIV) { 5294 if ((RHSOp.getOpcode() == ISD::Constant && 5295 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) || 5296 (RHSOp.getOpcode() == ISD::ConstantFP && 5297 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero())) 5298 break; 5299 } 5300 Ops.push_back(DAG.getNode(N->getOpcode(), EltType, LHSOp, RHSOp)); 5301 AddToWorkList(Ops.back().getNode()); 5302 assert((Ops.back().getOpcode() == ISD::UNDEF || 5303 Ops.back().getOpcode() == ISD::Constant || 5304 Ops.back().getOpcode() == ISD::ConstantFP) && 5305 "Scalar binop didn't fold!"); 5306 } 5307 5308 if (Ops.size() == LHS.getNumOperands()) { 5309 MVT VT = LHS.getValueType(); 5310 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 5311 } 5312 } 5313 5314 return SDValue(); 5315} 5316 5317SDValue DAGCombiner::SimplifySelect(SDValue N0, SDValue N1, SDValue N2){ 5318 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 5319 5320 SDValue SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2, 5321 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 5322 // If we got a simplified select_cc node back from SimplifySelectCC, then 5323 // break it down into a new SETCC node, and a new SELECT node, and then return 5324 // the SELECT node, since we were called with a SELECT node. 5325 if (SCC.getNode()) { 5326 // Check to see if we got a select_cc back (to turn into setcc/select). 5327 // Otherwise, just return whatever node we got back, like fabs. 5328 if (SCC.getOpcode() == ISD::SELECT_CC) { 5329 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(), 5330 SCC.getOperand(0), SCC.getOperand(1), 5331 SCC.getOperand(4)); 5332 AddToWorkList(SETCC.getNode()); 5333 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2), 5334 SCC.getOperand(3), SETCC); 5335 } 5336 return SCC; 5337 } 5338 return SDValue(); 5339} 5340 5341/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 5342/// are the two values being selected between, see if we can simplify the 5343/// select. Callers of this should assume that TheSelect is deleted if this 5344/// returns true. As such, they should return the appropriate thing (e.g. the 5345/// node) back to the top-level of the DAG combiner loop to avoid it being 5346/// looked at. 5347/// 5348bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 5349 SDValue RHS) { 5350 5351 // If this is a select from two identical things, try to pull the operation 5352 // through the select. 5353 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 5354 // If this is a load and the token chain is identical, replace the select 5355 // of two loads with a load through a select of the address to load from. 5356 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 5357 // constants have been dropped into the constant pool. 5358 if (LHS.getOpcode() == ISD::LOAD && 5359 // Do not let this transformation reduce the number of volatile loads. 5360 !cast<LoadSDNode>(LHS)->isVolatile() && 5361 !cast<LoadSDNode>(RHS)->isVolatile() && 5362 // Token chains must be identical. 5363 LHS.getOperand(0) == RHS.getOperand(0)) { 5364 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 5365 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 5366 5367 // If this is an EXTLOAD, the VT's must match. 5368 if (LLD->getMemoryVT() == RLD->getMemoryVT()) { 5369 // FIXME: this conflates two src values, discarding one. This is not 5370 // the right thing to do, but nothing uses srcvalues now. When they do, 5371 // turn SrcValue into a list of locations. 5372 SDValue Addr; 5373 if (TheSelect->getOpcode() == ISD::SELECT) { 5374 // Check that the condition doesn't reach either load. If so, folding 5375 // this will induce a cycle into the DAG. 5376 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5377 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode())) { 5378 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(), 5379 TheSelect->getOperand(0), LLD->getBasePtr(), 5380 RLD->getBasePtr()); 5381 } 5382 } else { 5383 // Check that the condition doesn't reach either load. If so, folding 5384 // this will induce a cycle into the DAG. 5385 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5386 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5387 !LLD->isPredecessorOf(TheSelect->getOperand(1).getNode()) && 5388 !RLD->isPredecessorOf(TheSelect->getOperand(1).getNode())) { 5389 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(), 5390 TheSelect->getOperand(0), 5391 TheSelect->getOperand(1), 5392 LLD->getBasePtr(), RLD->getBasePtr(), 5393 TheSelect->getOperand(4)); 5394 } 5395 } 5396 5397 if (Addr.getNode()) { 5398 SDValue Load; 5399 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) 5400 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(), 5401 Addr,LLD->getSrcValue(), 5402 LLD->getSrcValueOffset(), 5403 LLD->isVolatile(), 5404 LLD->getAlignment()); 5405 else { 5406 Load = DAG.getExtLoad(LLD->getExtensionType(), 5407 TheSelect->getValueType(0), 5408 LLD->getChain(), Addr, LLD->getSrcValue(), 5409 LLD->getSrcValueOffset(), 5410 LLD->getMemoryVT(), 5411 LLD->isVolatile(), 5412 LLD->getAlignment()); 5413 } 5414 // Users of the select now use the result of the load. 5415 CombineTo(TheSelect, Load); 5416 5417 // Users of the old loads now use the new load's chain. We know the 5418 // old-load value is dead now. 5419 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); 5420 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); 5421 return true; 5422 } 5423 } 5424 } 5425 } 5426 5427 return false; 5428} 5429 5430SDValue DAGCombiner::SimplifySelectCC(SDValue N0, SDValue N1, 5431 SDValue N2, SDValue N3, 5432 ISD::CondCode CC, bool NotExtCompare) { 5433 5434 MVT VT = N2.getValueType(); 5435 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 5436 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 5437 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); 5438 5439 // Determine if the condition we're dealing with is constant 5440 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0), N0, N1, CC, false); 5441 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 5442 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode()); 5443 5444 // fold select_cc true, x, y -> x 5445 if (SCCC && !SCCC->isNullValue()) 5446 return N2; 5447 // fold select_cc false, x, y -> y 5448 if (SCCC && SCCC->isNullValue()) 5449 return N3; 5450 5451 // Check to see if we can simplify the select into an fabs node 5452 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 5453 // Allow either -0.0 or 0.0 5454 if (CFP->getValueAPF().isZero()) { 5455 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 5456 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 5457 N0 == N2 && N3.getOpcode() == ISD::FNEG && 5458 N2 == N3.getOperand(0)) 5459 return DAG.getNode(ISD::FABS, VT, N0); 5460 5461 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 5462 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 5463 N0 == N3 && N2.getOpcode() == ISD::FNEG && 5464 N2.getOperand(0) == N3) 5465 return DAG.getNode(ISD::FABS, VT, N3); 5466 } 5467 } 5468 5469 // Check to see if we can perform the "gzip trick", transforming 5470 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 5471 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 5472 N0.getValueType().isInteger() && 5473 N2.getValueType().isInteger() && 5474 (N1C->isNullValue() || // (a < 0) ? b : 0 5475 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 5476 MVT XType = N0.getValueType(); 5477 MVT AType = N2.getValueType(); 5478 if (XType.bitsGE(AType)) { 5479 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 5480 // single-bit constant. 5481 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 5482 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 5483 ShCtV = XType.getSizeInBits()-ShCtV-1; 5484 SDValue ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy()); 5485 SDValue Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt); 5486 AddToWorkList(Shift.getNode()); 5487 if (XType.bitsGT(AType)) { 5488 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 5489 AddToWorkList(Shift.getNode()); 5490 } 5491 return DAG.getNode(ISD::AND, AType, Shift, N2); 5492 } 5493 SDValue Shift = DAG.getNode(ISD::SRA, XType, N0, 5494 DAG.getConstant(XType.getSizeInBits()-1, 5495 TLI.getShiftAmountTy())); 5496 AddToWorkList(Shift.getNode()); 5497 if (XType.bitsGT(AType)) { 5498 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 5499 AddToWorkList(Shift.getNode()); 5500 } 5501 return DAG.getNode(ISD::AND, AType, Shift, N2); 5502 } 5503 } 5504 5505 // fold select C, 16, 0 -> shl C, 4 5506 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 5507 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) { 5508 5509 // If the caller doesn't want us to simplify this into a zext of a compare, 5510 // don't do it. 5511 if (NotExtCompare && N2C->getAPIntValue() == 1) 5512 return SDValue(); 5513 5514 // Get a SetCC of the condition 5515 // FIXME: Should probably make sure that setcc is legal if we ever have a 5516 // target where it isn't. 5517 SDValue Temp, SCC; 5518 // cast from setcc result type to select result type 5519 if (LegalTypes) { 5520 SCC = DAG.getSetCC(TLI.getSetCCResultType(N0), N0, N1, CC); 5521 if (N2.getValueType().bitsLT(SCC.getValueType())) 5522 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType()); 5523 else 5524 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 5525 } else { 5526 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC); 5527 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 5528 } 5529 AddToWorkList(SCC.getNode()); 5530 AddToWorkList(Temp.getNode()); 5531 5532 if (N2C->getAPIntValue() == 1) 5533 return Temp; 5534 // shl setcc result by log2 n2c 5535 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp, 5536 DAG.getConstant(N2C->getAPIntValue().logBase2(), 5537 TLI.getShiftAmountTy())); 5538 } 5539 5540 // Check to see if this is the equivalent of setcc 5541 // FIXME: Turn all of these into setcc if setcc if setcc is legal 5542 // otherwise, go ahead with the folds. 5543 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 5544 MVT XType = N0.getValueType(); 5545 if (!LegalOperations || 5546 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(N0))) { 5547 SDValue Res = DAG.getSetCC(TLI.getSetCCResultType(N0), N0, N1, CC); 5548 if (Res.getValueType() != VT) 5549 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res); 5550 return Res; 5551 } 5552 5553 // seteq X, 0 -> srl (ctlz X, log2(size(X))) 5554 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 5555 (!LegalOperations || 5556 TLI.isOperationLegal(ISD::CTLZ, XType))) { 5557 SDValue Ctlz = DAG.getNode(ISD::CTLZ, XType, N0); 5558 return DAG.getNode(ISD::SRL, XType, Ctlz, 5559 DAG.getConstant(Log2_32(XType.getSizeInBits()), 5560 TLI.getShiftAmountTy())); 5561 } 5562 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) 5563 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 5564 SDValue NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType), 5565 N0); 5566 SDValue NotN0 = DAG.getNode(ISD::XOR, XType, N0, 5567 DAG.getConstant(~0ULL, XType)); 5568 return DAG.getNode(ISD::SRL, XType, 5569 DAG.getNode(ISD::AND, XType, NegN0, NotN0), 5570 DAG.getConstant(XType.getSizeInBits()-1, 5571 TLI.getShiftAmountTy())); 5572 } 5573 // setgt X, -1 -> xor (srl (X, size(X)-1), 1) 5574 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 5575 SDValue Sign = DAG.getNode(ISD::SRL, XType, N0, 5576 DAG.getConstant(XType.getSizeInBits()-1, 5577 TLI.getShiftAmountTy())); 5578 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType)); 5579 } 5580 } 5581 5582 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 5583 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5584 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 5585 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) && 5586 N2.getOperand(0) == N1 && N0.getValueType().isInteger()) { 5587 MVT XType = N0.getValueType(); 5588 SDValue Shift = DAG.getNode(ISD::SRA, XType, N0, 5589 DAG.getConstant(XType.getSizeInBits()-1, 5590 TLI.getShiftAmountTy())); 5591 SDValue Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 5592 AddToWorkList(Shift.getNode()); 5593 AddToWorkList(Add.getNode()); 5594 return DAG.getNode(ISD::XOR, XType, Add, Shift); 5595 } 5596 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X -> 5597 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5598 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT && 5599 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) { 5600 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 5601 MVT XType = N0.getValueType(); 5602 if (SubC->isNullValue() && XType.isInteger()) { 5603 SDValue Shift = DAG.getNode(ISD::SRA, XType, N0, 5604 DAG.getConstant(XType.getSizeInBits()-1, 5605 TLI.getShiftAmountTy())); 5606 SDValue Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 5607 AddToWorkList(Shift.getNode()); 5608 AddToWorkList(Add.getNode()); 5609 return DAG.getNode(ISD::XOR, XType, Add, Shift); 5610 } 5611 } 5612 } 5613 5614 return SDValue(); 5615} 5616 5617/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 5618SDValue DAGCombiner::SimplifySetCC(MVT VT, SDValue N0, 5619 SDValue N1, ISD::CondCode Cond, 5620 bool foldBooleans) { 5621 TargetLowering::DAGCombinerInfo 5622 DagCombineInfo(DAG, Level == Unrestricted, false, this); 5623 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo); 5624} 5625 5626/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 5627/// return a DAG expression to select that will generate the same value by 5628/// multiplying by a magic number. See: 5629/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 5630SDValue DAGCombiner::BuildSDIV(SDNode *N) { 5631 std::vector<SDNode*> Built; 5632 SDValue S = TLI.BuildSDIV(N, DAG, &Built); 5633 5634 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 5635 ii != ee; ++ii) 5636 AddToWorkList(*ii); 5637 return S; 5638} 5639 5640/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 5641/// return a DAG expression to select that will generate the same value by 5642/// multiplying by a magic number. See: 5643/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 5644SDValue DAGCombiner::BuildUDIV(SDNode *N) { 5645 std::vector<SDNode*> Built; 5646 SDValue S = TLI.BuildUDIV(N, DAG, &Built); 5647 5648 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 5649 ii != ee; ++ii) 5650 AddToWorkList(*ii); 5651 return S; 5652} 5653 5654/// FindBaseOffset - Return true if base is known not to alias with anything 5655/// but itself. Provides base object and offset as results. 5656static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset) { 5657 // Assume it is a primitive operation. 5658 Base = Ptr; Offset = 0; 5659 5660 // If it's an adding a simple constant then integrate the offset. 5661 if (Base.getOpcode() == ISD::ADD) { 5662 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 5663 Base = Base.getOperand(0); 5664 Offset += C->getZExtValue(); 5665 } 5666 } 5667 5668 // If it's any of the following then it can't alias with anything but itself. 5669 return isa<FrameIndexSDNode>(Base) || 5670 isa<ConstantPoolSDNode>(Base) || 5671 isa<GlobalAddressSDNode>(Base); 5672} 5673 5674/// isAlias - Return true if there is any possibility that the two addresses 5675/// overlap. 5676bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, 5677 const Value *SrcValue1, int SrcValueOffset1, 5678 SDValue Ptr2, int64_t Size2, 5679 const Value *SrcValue2, int SrcValueOffset2) 5680{ 5681 // If they are the same then they must be aliases. 5682 if (Ptr1 == Ptr2) return true; 5683 5684 // Gather base node and offset information. 5685 SDValue Base1, Base2; 5686 int64_t Offset1, Offset2; 5687 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1); 5688 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2); 5689 5690 // If they have a same base address then... 5691 if (Base1 == Base2) { 5692 // Check to see if the addresses overlap. 5693 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 5694 } 5695 5696 // If we know both bases then they can't alias. 5697 if (KnownBase1 && KnownBase2) return false; 5698 5699 if (CombinerGlobalAA) { 5700 // Use alias analysis information. 5701 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 5702 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 5703 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 5704 AliasAnalysis::AliasResult AAResult = 5705 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2); 5706 if (AAResult == AliasAnalysis::NoAlias) 5707 return false; 5708 } 5709 5710 // Otherwise we have to assume they alias. 5711 return true; 5712} 5713 5714/// FindAliasInfo - Extracts the relevant alias information from the memory 5715/// node. Returns true if the operand was a load. 5716bool DAGCombiner::FindAliasInfo(SDNode *N, 5717 SDValue &Ptr, int64_t &Size, 5718 const Value *&SrcValue, int &SrcValueOffset) { 5719 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 5720 Ptr = LD->getBasePtr(); 5721 Size = LD->getMemoryVT().getSizeInBits() >> 3; 5722 SrcValue = LD->getSrcValue(); 5723 SrcValueOffset = LD->getSrcValueOffset(); 5724 return true; 5725 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 5726 Ptr = ST->getBasePtr(); 5727 Size = ST->getMemoryVT().getSizeInBits() >> 3; 5728 SrcValue = ST->getSrcValue(); 5729 SrcValueOffset = ST->getSrcValueOffset(); 5730 } else { 5731 assert(0 && "FindAliasInfo expected a memory operand"); 5732 } 5733 5734 return false; 5735} 5736 5737/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 5738/// looking for aliasing nodes and adding them to the Aliases vector. 5739void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 5740 SmallVector<SDValue, 8> &Aliases) { 5741 SmallVector<SDValue, 8> Chains; // List of chains to visit. 5742 std::set<SDNode *> Visited; // Visited node set. 5743 5744 // Get alias information for node. 5745 SDValue Ptr; 5746 int64_t Size; 5747 const Value *SrcValue; 5748 int SrcValueOffset; 5749 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset); 5750 5751 // Starting off. 5752 Chains.push_back(OriginalChain); 5753 5754 // Look at each chain and determine if it is an alias. If so, add it to the 5755 // aliases list. If not, then continue up the chain looking for the next 5756 // candidate. 5757 while (!Chains.empty()) { 5758 SDValue Chain = Chains.back(); 5759 Chains.pop_back(); 5760 5761 // Don't bother if we've been before. 5762 if (Visited.find(Chain.getNode()) != Visited.end()) continue; 5763 Visited.insert(Chain.getNode()); 5764 5765 switch (Chain.getOpcode()) { 5766 case ISD::EntryToken: 5767 // Entry token is ideal chain operand, but handled in FindBetterChain. 5768 break; 5769 5770 case ISD::LOAD: 5771 case ISD::STORE: { 5772 // Get alias information for Chain. 5773 SDValue OpPtr; 5774 int64_t OpSize; 5775 const Value *OpSrcValue; 5776 int OpSrcValueOffset; 5777 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, 5778 OpSrcValue, OpSrcValueOffset); 5779 5780 // If chain is alias then stop here. 5781 if (!(IsLoad && IsOpLoad) && 5782 isAlias(Ptr, Size, SrcValue, SrcValueOffset, 5783 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) { 5784 Aliases.push_back(Chain); 5785 } else { 5786 // Look further up the chain. 5787 Chains.push_back(Chain.getOperand(0)); 5788 // Clean up old chain. 5789 AddToWorkList(Chain.getNode()); 5790 } 5791 break; 5792 } 5793 5794 case ISD::TokenFactor: 5795 // We have to check each of the operands of the token factor, so we queue 5796 // then up. Adding the operands to the queue (stack) in reverse order 5797 // maintains the original order and increases the likelihood that getNode 5798 // will find a matching token factor (CSE.) 5799 for (unsigned n = Chain.getNumOperands(); n;) 5800 Chains.push_back(Chain.getOperand(--n)); 5801 // Eliminate the token factor if we can. 5802 AddToWorkList(Chain.getNode()); 5803 break; 5804 5805 default: 5806 // For all other instructions we will just have to take what we can get. 5807 Aliases.push_back(Chain); 5808 break; 5809 } 5810 } 5811} 5812 5813/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 5814/// for a better chain (aliasing node.) 5815SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 5816 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 5817 5818 // Accumulate all the aliases to this node. 5819 GatherAllAliases(N, OldChain, Aliases); 5820 5821 if (Aliases.size() == 0) { 5822 // If no operands then chain to entry token. 5823 return DAG.getEntryNode(); 5824 } else if (Aliases.size() == 1) { 5825 // If a single operand then chain to it. We don't need to revisit it. 5826 return Aliases[0]; 5827 } 5828 5829 // Construct a custom tailored token factor. 5830 SDValue NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 5831 &Aliases[0], Aliases.size()); 5832 5833 // Make sure the old chain gets cleaned up. 5834 if (NewChain != OldChain) AddToWorkList(OldChain.getNode()); 5835 5836 return NewChain; 5837} 5838 5839// SelectionDAG::Combine - This is the entry point for the file. 5840// 5841void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, bool Fast) { 5842 /// run - This is the main entry point to this class. 5843 /// 5844 DAGCombiner(*this, AA, Fast).Run(Level); 5845} 5846