DAGCombiner.cpp revision d3fd6d2b25fc4e932ac796664ae7f4cd810ced8a
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Nate Begeman and is distributed under the 6// University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "dagcombine" 16#include "llvm/CodeGen/SelectionDAG.h" 17#include "llvm/Analysis/AliasAnalysis.h" 18#include "llvm/Target/TargetData.h" 19#include "llvm/Target/TargetLowering.h" 20#include "llvm/Target/TargetMachine.h" 21#include "llvm/Target/TargetOptions.h" 22#include "llvm/ADT/SmallPtrSet.h" 23#include "llvm/ADT/Statistic.h" 24#include "llvm/Support/Compiler.h" 25#include "llvm/Support/CommandLine.h" 26#include "llvm/Support/Debug.h" 27#include "llvm/Support/MathExtras.h" 28#include <algorithm> 29using namespace llvm; 30 31STATISTIC(NodesCombined , "Number of dag nodes combined"); 32STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 33STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 34 35namespace { 36#ifndef NDEBUG 37 static cl::opt<bool> 38 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 39 cl::desc("Pop up a window to show dags before the first " 40 "dag combine pass")); 41 static cl::opt<bool> 42 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 43 cl::desc("Pop up a window to show dags before the second " 44 "dag combine pass")); 45#else 46 static const bool ViewDAGCombine1 = false; 47 static const bool ViewDAGCombine2 = false; 48#endif 49 50 static cl::opt<bool> 51 CombinerAA("combiner-alias-analysis", cl::Hidden, 52 cl::desc("Turn on alias analysis during testing")); 53 54 static cl::opt<bool> 55 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 56 cl::desc("Include global information in alias analysis")); 57 58//------------------------------ DAGCombiner ---------------------------------// 59 60 class VISIBILITY_HIDDEN DAGCombiner { 61 SelectionDAG &DAG; 62 TargetLowering &TLI; 63 bool AfterLegalize; 64 65 // Worklist of all of the nodes that need to be simplified. 66 std::vector<SDNode*> WorkList; 67 68 // AA - Used for DAG load/store alias analysis. 69 AliasAnalysis &AA; 70 71 /// AddUsersToWorkList - When an instruction is simplified, add all users of 72 /// the instruction to the work lists because they might get more simplified 73 /// now. 74 /// 75 void AddUsersToWorkList(SDNode *N) { 76 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 77 UI != UE; ++UI) 78 AddToWorkList(*UI); 79 } 80 81 /// removeFromWorkList - remove all instances of N from the worklist. 82 /// 83 void removeFromWorkList(SDNode *N) { 84 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 85 WorkList.end()); 86 } 87 88 /// visit - call the node-specific routine that knows how to fold each 89 /// particular type of node. 90 SDOperand visit(SDNode *N); 91 92 public: 93 /// AddToWorkList - Add to the work list making sure it's instance is at the 94 /// the back (next to be processed.) 95 void AddToWorkList(SDNode *N) { 96 removeFromWorkList(N); 97 WorkList.push_back(N); 98 } 99 100 SDOperand CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo, 101 bool AddTo = true) { 102 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 103 ++NodesCombined; 104 DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG)); 105 DOUT << "\nWith: "; DEBUG(To[0].Val->dump(&DAG)); 106 DOUT << " and " << NumTo-1 << " other values\n"; 107 std::vector<SDNode*> NowDead; 108 DAG.ReplaceAllUsesWith(N, To, &NowDead); 109 110 if (AddTo) { 111 // Push the new nodes and any users onto the worklist 112 for (unsigned i = 0, e = NumTo; i != e; ++i) { 113 AddToWorkList(To[i].Val); 114 AddUsersToWorkList(To[i].Val); 115 } 116 } 117 118 // Nodes can be reintroduced into the worklist. Make sure we do not 119 // process a node that has been replaced. 120 removeFromWorkList(N); 121 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 122 removeFromWorkList(NowDead[i]); 123 124 // Finally, since the node is now dead, remove it from the graph. 125 DAG.DeleteNode(N); 126 return SDOperand(N, 0); 127 } 128 129 SDOperand CombineTo(SDNode *N, SDOperand Res, bool AddTo = true) { 130 return CombineTo(N, &Res, 1, AddTo); 131 } 132 133 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1, 134 bool AddTo = true) { 135 SDOperand To[] = { Res0, Res1 }; 136 return CombineTo(N, To, 2, AddTo); 137 } 138 private: 139 140 /// SimplifyDemandedBits - Check the specified integer node value to see if 141 /// it can be simplified or if things it uses can be simplified by bit 142 /// propagation. If so, return true. 143 bool SimplifyDemandedBits(SDOperand Op, uint64_t Demanded = ~0ULL) { 144 TargetLowering::TargetLoweringOpt TLO(DAG); 145 uint64_t KnownZero, KnownOne; 146 Demanded &= MVT::getIntVTBitMask(Op.getValueType()); 147 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 148 return false; 149 150 // Revisit the node. 151 AddToWorkList(Op.Val); 152 153 // Replace the old value with the new one. 154 ++NodesCombined; 155 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.Val->dump(&DAG)); 156 DOUT << "\nWith: "; DEBUG(TLO.New.Val->dump(&DAG)); 157 DOUT << '\n'; 158 159 std::vector<SDNode*> NowDead; 160 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &NowDead); 161 162 // Push the new node and any (possibly new) users onto the worklist. 163 AddToWorkList(TLO.New.Val); 164 AddUsersToWorkList(TLO.New.Val); 165 166 // Nodes can end up on the worklist more than once. Make sure we do 167 // not process a node that has been replaced. 168 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 169 removeFromWorkList(NowDead[i]); 170 171 // Finally, if the node is now dead, remove it from the graph. The node 172 // may not be dead if the replacement process recursively simplified to 173 // something else needing this node. 174 if (TLO.Old.Val->use_empty()) { 175 removeFromWorkList(TLO.Old.Val); 176 177 // If the operands of this node are only used by the node, they will now 178 // be dead. Make sure to visit them first to delete dead nodes early. 179 for (unsigned i = 0, e = TLO.Old.Val->getNumOperands(); i != e; ++i) 180 if (TLO.Old.Val->getOperand(i).Val->hasOneUse()) 181 AddToWorkList(TLO.Old.Val->getOperand(i).Val); 182 183 DAG.DeleteNode(TLO.Old.Val); 184 } 185 return true; 186 } 187 188 bool CombineToPreIndexedLoadStore(SDNode *N); 189 bool CombineToPostIndexedLoadStore(SDNode *N); 190 191 192 /// combine - call the node-specific routine that knows how to fold each 193 /// particular type of node. If that doesn't do anything, try the 194 /// target-specific DAG combines. 195 SDOperand combine(SDNode *N); 196 197 // Visitation implementation - Implement dag node combining for different 198 // node types. The semantics are as follows: 199 // Return Value: 200 // SDOperand.Val == 0 - No change was made 201 // SDOperand.Val == N - N was replaced, is dead, and is already handled. 202 // otherwise - N should be replaced by the returned Operand. 203 // 204 SDOperand visitTokenFactor(SDNode *N); 205 SDOperand visitADD(SDNode *N); 206 SDOperand visitSUB(SDNode *N); 207 SDOperand visitADDC(SDNode *N); 208 SDOperand visitADDE(SDNode *N); 209 SDOperand visitMUL(SDNode *N); 210 SDOperand visitSDIV(SDNode *N); 211 SDOperand visitUDIV(SDNode *N); 212 SDOperand visitSREM(SDNode *N); 213 SDOperand visitUREM(SDNode *N); 214 SDOperand visitMULHU(SDNode *N); 215 SDOperand visitMULHS(SDNode *N); 216 SDOperand visitSMUL_LOHI(SDNode *N); 217 SDOperand visitUMUL_LOHI(SDNode *N); 218 SDOperand visitSDIVREM(SDNode *N); 219 SDOperand visitUDIVREM(SDNode *N); 220 SDOperand visitAND(SDNode *N); 221 SDOperand visitOR(SDNode *N); 222 SDOperand visitXOR(SDNode *N); 223 SDOperand SimplifyVBinOp(SDNode *N); 224 SDOperand visitSHL(SDNode *N); 225 SDOperand visitSRA(SDNode *N); 226 SDOperand visitSRL(SDNode *N); 227 SDOperand visitCTLZ(SDNode *N); 228 SDOperand visitCTTZ(SDNode *N); 229 SDOperand visitCTPOP(SDNode *N); 230 SDOperand visitSELECT(SDNode *N); 231 SDOperand visitSELECT_CC(SDNode *N); 232 SDOperand visitSETCC(SDNode *N); 233 SDOperand visitSIGN_EXTEND(SDNode *N); 234 SDOperand visitZERO_EXTEND(SDNode *N); 235 SDOperand visitANY_EXTEND(SDNode *N); 236 SDOperand visitSIGN_EXTEND_INREG(SDNode *N); 237 SDOperand visitTRUNCATE(SDNode *N); 238 SDOperand visitBIT_CONVERT(SDNode *N); 239 SDOperand visitFADD(SDNode *N); 240 SDOperand visitFSUB(SDNode *N); 241 SDOperand visitFMUL(SDNode *N); 242 SDOperand visitFDIV(SDNode *N); 243 SDOperand visitFREM(SDNode *N); 244 SDOperand visitFCOPYSIGN(SDNode *N); 245 SDOperand visitSINT_TO_FP(SDNode *N); 246 SDOperand visitUINT_TO_FP(SDNode *N); 247 SDOperand visitFP_TO_SINT(SDNode *N); 248 SDOperand visitFP_TO_UINT(SDNode *N); 249 SDOperand visitFP_ROUND(SDNode *N); 250 SDOperand visitFP_ROUND_INREG(SDNode *N); 251 SDOperand visitFP_EXTEND(SDNode *N); 252 SDOperand visitFNEG(SDNode *N); 253 SDOperand visitFABS(SDNode *N); 254 SDOperand visitBRCOND(SDNode *N); 255 SDOperand visitBR_CC(SDNode *N); 256 SDOperand visitLOAD(SDNode *N); 257 SDOperand visitSTORE(SDNode *N); 258 SDOperand visitINSERT_VECTOR_ELT(SDNode *N); 259 SDOperand visitEXTRACT_VECTOR_ELT(SDNode *N); 260 SDOperand visitBUILD_VECTOR(SDNode *N); 261 SDOperand visitCONCAT_VECTORS(SDNode *N); 262 SDOperand visitVECTOR_SHUFFLE(SDNode *N); 263 264 SDOperand XformToShuffleWithZero(SDNode *N); 265 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS); 266 267 SDOperand visitShiftByConstant(SDNode *N, unsigned Amt); 268 269 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS); 270 SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N); 271 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2); 272 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2, 273 SDOperand N3, ISD::CondCode CC, 274 bool NotExtCompare = false); 275 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, 276 ISD::CondCode Cond, bool foldBooleans = true); 277 bool SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, unsigned HiOp); 278 SDOperand ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT::ValueType); 279 SDOperand BuildSDIV(SDNode *N); 280 SDOperand BuildUDIV(SDNode *N); 281 SDNode *MatchRotate(SDOperand LHS, SDOperand RHS); 282 SDOperand ReduceLoadWidth(SDNode *N); 283 284 SDOperand GetDemandedBits(SDOperand V, uint64_t Mask); 285 286 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 287 /// looking for aliasing nodes and adding them to the Aliases vector. 288 void GatherAllAliases(SDNode *N, SDOperand OriginalChain, 289 SmallVector<SDOperand, 8> &Aliases); 290 291 /// isAlias - Return true if there is any possibility that the two addresses 292 /// overlap. 293 bool isAlias(SDOperand Ptr1, int64_t Size1, 294 const Value *SrcValue1, int SrcValueOffset1, 295 SDOperand Ptr2, int64_t Size2, 296 const Value *SrcValue2, int SrcValueOffset2); 297 298 /// FindAliasInfo - Extracts the relevant alias information from the memory 299 /// node. Returns true if the operand was a load. 300 bool FindAliasInfo(SDNode *N, 301 SDOperand &Ptr, int64_t &Size, 302 const Value *&SrcValue, int &SrcValueOffset); 303 304 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 305 /// looking for a better chain (aliasing node.) 306 SDOperand FindBetterChain(SDNode *N, SDOperand Chain); 307 308public: 309 DAGCombiner(SelectionDAG &D, AliasAnalysis &A) 310 : DAG(D), 311 TLI(D.getTargetLoweringInfo()), 312 AfterLegalize(false), 313 AA(A) {} 314 315 /// Run - runs the dag combiner on all nodes in the work list 316 void Run(bool RunningAfterLegalize); 317 }; 318} 319 320//===----------------------------------------------------------------------===// 321// TargetLowering::DAGCombinerInfo implementation 322//===----------------------------------------------------------------------===// 323 324void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 325 ((DAGCombiner*)DC)->AddToWorkList(N); 326} 327 328SDOperand TargetLowering::DAGCombinerInfo:: 329CombineTo(SDNode *N, const std::vector<SDOperand> &To) { 330 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size()); 331} 332 333SDOperand TargetLowering::DAGCombinerInfo:: 334CombineTo(SDNode *N, SDOperand Res) { 335 return ((DAGCombiner*)DC)->CombineTo(N, Res); 336} 337 338 339SDOperand TargetLowering::DAGCombinerInfo:: 340CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) { 341 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1); 342} 343 344 345//===----------------------------------------------------------------------===// 346// Helper Functions 347//===----------------------------------------------------------------------===// 348 349/// isNegatibleForFree - Return 1 if we can compute the negated form of the 350/// specified expression for the same cost as the expression itself, or 2 if we 351/// can compute the negated form more cheaply than the expression itself. 352static char isNegatibleForFree(SDOperand Op, unsigned Depth = 0) { 353 // No compile time optimizations on this type. 354 if (Op.getValueType() == MVT::ppcf128) 355 return 0; 356 357 // fneg is removable even if it has multiple uses. 358 if (Op.getOpcode() == ISD::FNEG) return 2; 359 360 // Don't allow anything with multiple uses. 361 if (!Op.hasOneUse()) return 0; 362 363 // Don't recurse exponentially. 364 if (Depth > 6) return 0; 365 366 switch (Op.getOpcode()) { 367 default: return false; 368 case ISD::ConstantFP: 369 return 1; 370 case ISD::FADD: 371 // FIXME: determine better conditions for this xform. 372 if (!UnsafeFPMath) return 0; 373 374 // -(A+B) -> -A - B 375 if (char V = isNegatibleForFree(Op.getOperand(0), Depth+1)) 376 return V; 377 // -(A+B) -> -B - A 378 return isNegatibleForFree(Op.getOperand(1), Depth+1); 379 case ISD::FSUB: 380 // We can't turn -(A-B) into B-A when we honor signed zeros. 381 if (!UnsafeFPMath) return 0; 382 383 // -(A-B) -> B-A 384 return 1; 385 386 case ISD::FMUL: 387 case ISD::FDIV: 388 if (HonorSignDependentRoundingFPMath()) return 0; 389 390 // -(X*Y) -> (-X * Y) or (X*-Y) 391 if (char V = isNegatibleForFree(Op.getOperand(0), Depth+1)) 392 return V; 393 394 return isNegatibleForFree(Op.getOperand(1), Depth+1); 395 396 case ISD::FP_EXTEND: 397 case ISD::FP_ROUND: 398 case ISD::FSIN: 399 return isNegatibleForFree(Op.getOperand(0), Depth+1); 400 } 401} 402 403/// GetNegatedExpression - If isNegatibleForFree returns true, this function 404/// returns the newly negated expression. 405static SDOperand GetNegatedExpression(SDOperand Op, SelectionDAG &DAG, 406 unsigned Depth = 0) { 407 // fneg is removable even if it has multiple uses. 408 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 409 410 // Don't allow anything with multiple uses. 411 assert(Op.hasOneUse() && "Unknown reuse!"); 412 413 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 414 switch (Op.getOpcode()) { 415 default: assert(0 && "Unknown code"); 416 case ISD::ConstantFP: { 417 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 418 V.changeSign(); 419 return DAG.getConstantFP(V, Op.getValueType()); 420 } 421 case ISD::FADD: 422 // FIXME: determine better conditions for this xform. 423 assert(UnsafeFPMath); 424 425 // -(A+B) -> -A - B 426 if (isNegatibleForFree(Op.getOperand(0), Depth+1)) 427 return DAG.getNode(ISD::FSUB, Op.getValueType(), 428 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1), 429 Op.getOperand(1)); 430 // -(A+B) -> -B - A 431 return DAG.getNode(ISD::FSUB, Op.getValueType(), 432 GetNegatedExpression(Op.getOperand(1), DAG, Depth+1), 433 Op.getOperand(0)); 434 case ISD::FSUB: 435 // We can't turn -(A-B) into B-A when we honor signed zeros. 436 assert(UnsafeFPMath); 437 438 // -(0-B) -> B 439 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 440 if (N0CFP->getValueAPF().isZero()) 441 return Op.getOperand(1); 442 443 // -(A-B) -> B-A 444 return DAG.getNode(ISD::FSUB, Op.getValueType(), Op.getOperand(1), 445 Op.getOperand(0)); 446 447 case ISD::FMUL: 448 case ISD::FDIV: 449 assert(!HonorSignDependentRoundingFPMath()); 450 451 // -(X*Y) -> -X * Y 452 if (isNegatibleForFree(Op.getOperand(0), Depth+1)) 453 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 454 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1), 455 Op.getOperand(1)); 456 457 // -(X*Y) -> X * -Y 458 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 459 Op.getOperand(0), 460 GetNegatedExpression(Op.getOperand(1), DAG, Depth+1)); 461 462 case ISD::FP_EXTEND: 463 case ISD::FP_ROUND: 464 case ISD::FSIN: 465 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 466 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1)); 467 } 468} 469 470 471// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 472// that selects between the values 1 and 0, making it equivalent to a setcc. 473// Also, set the incoming LHS, RHS, and CC references to the appropriate 474// nodes based on the type of node we are checking. This simplifies life a 475// bit for the callers. 476static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS, 477 SDOperand &CC) { 478 if (N.getOpcode() == ISD::SETCC) { 479 LHS = N.getOperand(0); 480 RHS = N.getOperand(1); 481 CC = N.getOperand(2); 482 return true; 483 } 484 if (N.getOpcode() == ISD::SELECT_CC && 485 N.getOperand(2).getOpcode() == ISD::Constant && 486 N.getOperand(3).getOpcode() == ISD::Constant && 487 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 && 488 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 489 LHS = N.getOperand(0); 490 RHS = N.getOperand(1); 491 CC = N.getOperand(4); 492 return true; 493 } 494 return false; 495} 496 497// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 498// one use. If this is true, it allows the users to invert the operation for 499// free when it is profitable to do so. 500static bool isOneUseSetCC(SDOperand N) { 501 SDOperand N0, N1, N2; 502 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse()) 503 return true; 504 return false; 505} 506 507SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){ 508 MVT::ValueType VT = N0.getValueType(); 509 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 510 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 511 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 512 if (isa<ConstantSDNode>(N1)) { 513 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1); 514 AddToWorkList(OpNode.Val); 515 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0)); 516 } else if (N0.hasOneUse()) { 517 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1); 518 AddToWorkList(OpNode.Val); 519 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1)); 520 } 521 } 522 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 523 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 524 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 525 if (isa<ConstantSDNode>(N0)) { 526 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0); 527 AddToWorkList(OpNode.Val); 528 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0)); 529 } else if (N1.hasOneUse()) { 530 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0); 531 AddToWorkList(OpNode.Val); 532 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1)); 533 } 534 } 535 return SDOperand(); 536} 537 538//===----------------------------------------------------------------------===// 539// Main DAG Combiner implementation 540//===----------------------------------------------------------------------===// 541 542void DAGCombiner::Run(bool RunningAfterLegalize) { 543 // set the instance variable, so that the various visit routines may use it. 544 AfterLegalize = RunningAfterLegalize; 545 546 // Add all the dag nodes to the worklist. 547 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 548 E = DAG.allnodes_end(); I != E; ++I) 549 WorkList.push_back(I); 550 551 // Create a dummy node (which is not added to allnodes), that adds a reference 552 // to the root node, preventing it from being deleted, and tracking any 553 // changes of the root. 554 HandleSDNode Dummy(DAG.getRoot()); 555 556 // The root of the dag may dangle to deleted nodes until the dag combiner is 557 // done. Set it to null to avoid confusion. 558 DAG.setRoot(SDOperand()); 559 560 // while the worklist isn't empty, inspect the node on the end of it and 561 // try and combine it. 562 while (!WorkList.empty()) { 563 SDNode *N = WorkList.back(); 564 WorkList.pop_back(); 565 566 // If N has no uses, it is dead. Make sure to revisit all N's operands once 567 // N is deleted from the DAG, since they too may now be dead or may have a 568 // reduced number of uses, allowing other xforms. 569 if (N->use_empty() && N != &Dummy) { 570 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 571 AddToWorkList(N->getOperand(i).Val); 572 573 DAG.DeleteNode(N); 574 continue; 575 } 576 577 SDOperand RV = combine(N); 578 579 if (RV.Val) { 580 ++NodesCombined; 581 // If we get back the same node we passed in, rather than a new node or 582 // zero, we know that the node must have defined multiple values and 583 // CombineTo was used. Since CombineTo takes care of the worklist 584 // mechanics for us, we have no work to do in this case. 585 if (RV.Val != N) { 586 assert(N->getOpcode() != ISD::DELETED_NODE && 587 RV.Val->getOpcode() != ISD::DELETED_NODE && 588 "Node was deleted but visit returned new node!"); 589 590 DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG)); 591 DOUT << "\nWith: "; DEBUG(RV.Val->dump(&DAG)); 592 DOUT << '\n'; 593 std::vector<SDNode*> NowDead; 594 if (N->getNumValues() == RV.Val->getNumValues()) 595 DAG.ReplaceAllUsesWith(N, RV.Val, &NowDead); 596 else { 597 assert(N->getValueType(0) == RV.getValueType() && "Type mismatch"); 598 SDOperand OpV = RV; 599 DAG.ReplaceAllUsesWith(N, &OpV, &NowDead); 600 } 601 602 // Push the new node and any users onto the worklist 603 AddToWorkList(RV.Val); 604 AddUsersToWorkList(RV.Val); 605 606 // Nodes can be reintroduced into the worklist. Make sure we do not 607 // process a node that has been replaced. 608 removeFromWorkList(N); 609 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 610 removeFromWorkList(NowDead[i]); 611 612 // Finally, since the node is now dead, remove it from the graph. 613 DAG.DeleteNode(N); 614 } 615 } 616 } 617 618 // If the root changed (e.g. it was a dead load, update the root). 619 DAG.setRoot(Dummy.getValue()); 620} 621 622SDOperand DAGCombiner::visit(SDNode *N) { 623 switch(N->getOpcode()) { 624 default: break; 625 case ISD::TokenFactor: return visitTokenFactor(N); 626 case ISD::ADD: return visitADD(N); 627 case ISD::SUB: return visitSUB(N); 628 case ISD::ADDC: return visitADDC(N); 629 case ISD::ADDE: return visitADDE(N); 630 case ISD::MUL: return visitMUL(N); 631 case ISD::SDIV: return visitSDIV(N); 632 case ISD::UDIV: return visitUDIV(N); 633 case ISD::SREM: return visitSREM(N); 634 case ISD::UREM: return visitUREM(N); 635 case ISD::MULHU: return visitMULHU(N); 636 case ISD::MULHS: return visitMULHS(N); 637 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 638 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 639 case ISD::SDIVREM: return visitSDIVREM(N); 640 case ISD::UDIVREM: return visitUDIVREM(N); 641 case ISD::AND: return visitAND(N); 642 case ISD::OR: return visitOR(N); 643 case ISD::XOR: return visitXOR(N); 644 case ISD::SHL: return visitSHL(N); 645 case ISD::SRA: return visitSRA(N); 646 case ISD::SRL: return visitSRL(N); 647 case ISD::CTLZ: return visitCTLZ(N); 648 case ISD::CTTZ: return visitCTTZ(N); 649 case ISD::CTPOP: return visitCTPOP(N); 650 case ISD::SELECT: return visitSELECT(N); 651 case ISD::SELECT_CC: return visitSELECT_CC(N); 652 case ISD::SETCC: return visitSETCC(N); 653 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 654 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 655 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 656 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 657 case ISD::TRUNCATE: return visitTRUNCATE(N); 658 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 659 case ISD::FADD: return visitFADD(N); 660 case ISD::FSUB: return visitFSUB(N); 661 case ISD::FMUL: return visitFMUL(N); 662 case ISD::FDIV: return visitFDIV(N); 663 case ISD::FREM: return visitFREM(N); 664 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 665 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 666 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 667 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 668 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 669 case ISD::FP_ROUND: return visitFP_ROUND(N); 670 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 671 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 672 case ISD::FNEG: return visitFNEG(N); 673 case ISD::FABS: return visitFABS(N); 674 case ISD::BRCOND: return visitBRCOND(N); 675 case ISD::BR_CC: return visitBR_CC(N); 676 case ISD::LOAD: return visitLOAD(N); 677 case ISD::STORE: return visitSTORE(N); 678 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 679 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 680 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 681 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 682 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 683 } 684 return SDOperand(); 685} 686 687SDOperand DAGCombiner::combine(SDNode *N) { 688 689 SDOperand RV = visit(N); 690 691 // If nothing happened, try a target-specific DAG combine. 692 if (RV.Val == 0) { 693 assert(N->getOpcode() != ISD::DELETED_NODE && 694 "Node was deleted but visit returned NULL!"); 695 696 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 697 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 698 699 // Expose the DAG combiner to the target combiner impls. 700 TargetLowering::DAGCombinerInfo 701 DagCombineInfo(DAG, !AfterLegalize, false, this); 702 703 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 704 } 705 } 706 707 return RV; 708} 709 710/// getInputChainForNode - Given a node, return its input chain if it has one, 711/// otherwise return a null sd operand. 712static SDOperand getInputChainForNode(SDNode *N) { 713 if (unsigned NumOps = N->getNumOperands()) { 714 if (N->getOperand(0).getValueType() == MVT::Other) 715 return N->getOperand(0); 716 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 717 return N->getOperand(NumOps-1); 718 for (unsigned i = 1; i < NumOps-1; ++i) 719 if (N->getOperand(i).getValueType() == MVT::Other) 720 return N->getOperand(i); 721 } 722 return SDOperand(0, 0); 723} 724 725SDOperand DAGCombiner::visitTokenFactor(SDNode *N) { 726 // If N has two operands, where one has an input chain equal to the other, 727 // the 'other' chain is redundant. 728 if (N->getNumOperands() == 2) { 729 if (getInputChainForNode(N->getOperand(0).Val) == N->getOperand(1)) 730 return N->getOperand(0); 731 if (getInputChainForNode(N->getOperand(1).Val) == N->getOperand(0)) 732 return N->getOperand(1); 733 } 734 735 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 736 SmallVector<SDOperand, 8> Ops; // Ops for replacing token factor. 737 SmallPtrSet<SDNode*, 16> SeenOps; 738 bool Changed = false; // If we should replace this token factor. 739 740 // Start out with this token factor. 741 TFs.push_back(N); 742 743 // Iterate through token factors. The TFs grows when new token factors are 744 // encountered. 745 for (unsigned i = 0; i < TFs.size(); ++i) { 746 SDNode *TF = TFs[i]; 747 748 // Check each of the operands. 749 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 750 SDOperand Op = TF->getOperand(i); 751 752 switch (Op.getOpcode()) { 753 case ISD::EntryToken: 754 // Entry tokens don't need to be added to the list. They are 755 // rededundant. 756 Changed = true; 757 break; 758 759 case ISD::TokenFactor: 760 if ((CombinerAA || Op.hasOneUse()) && 761 std::find(TFs.begin(), TFs.end(), Op.Val) == TFs.end()) { 762 // Queue up for processing. 763 TFs.push_back(Op.Val); 764 // Clean up in case the token factor is removed. 765 AddToWorkList(Op.Val); 766 Changed = true; 767 break; 768 } 769 // Fall thru 770 771 default: 772 // Only add if it isn't already in the list. 773 if (SeenOps.insert(Op.Val)) 774 Ops.push_back(Op); 775 else 776 Changed = true; 777 break; 778 } 779 } 780 } 781 782 SDOperand Result; 783 784 // If we've change things around then replace token factor. 785 if (Changed) { 786 if (Ops.size() == 0) { 787 // The entry token is the only possible outcome. 788 Result = DAG.getEntryNode(); 789 } else { 790 // New and improved token factor. 791 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size()); 792 } 793 794 // Don't add users to work list. 795 return CombineTo(N, Result, false); 796 } 797 798 return Result; 799} 800 801static 802SDOperand combineShlAddConstant(SDOperand N0, SDOperand N1, SelectionDAG &DAG) { 803 MVT::ValueType VT = N0.getValueType(); 804 SDOperand N00 = N0.getOperand(0); 805 SDOperand N01 = N0.getOperand(1); 806 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 807 if (N01C && N00.getOpcode() == ISD::ADD && N00.Val->hasOneUse() && 808 isa<ConstantSDNode>(N00.getOperand(1))) { 809 N0 = DAG.getNode(ISD::ADD, VT, 810 DAG.getNode(ISD::SHL, VT, N00.getOperand(0), N01), 811 DAG.getNode(ISD::SHL, VT, N00.getOperand(1), N01)); 812 return DAG.getNode(ISD::ADD, VT, N0, N1); 813 } 814 return SDOperand(); 815} 816 817static 818SDOperand combineSelectAndUse(SDNode *N, SDOperand Slct, SDOperand OtherOp, 819 SelectionDAG &DAG) { 820 MVT::ValueType VT = N->getValueType(0); 821 unsigned Opc = N->getOpcode(); 822 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC; 823 SDOperand LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1); 824 SDOperand RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2); 825 ISD::CondCode CC = ISD::SETCC_INVALID; 826 if (isSlctCC) 827 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get(); 828 else { 829 SDOperand CCOp = Slct.getOperand(0); 830 if (CCOp.getOpcode() == ISD::SETCC) 831 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get(); 832 } 833 834 bool DoXform = false; 835 bool InvCC = false; 836 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) && 837 "Bad input!"); 838 if (LHS.getOpcode() == ISD::Constant && 839 cast<ConstantSDNode>(LHS)->isNullValue()) 840 DoXform = true; 841 else if (CC != ISD::SETCC_INVALID && 842 RHS.getOpcode() == ISD::Constant && 843 cast<ConstantSDNode>(RHS)->isNullValue()) { 844 std::swap(LHS, RHS); 845 bool isInt = MVT::isInteger(isSlctCC ? Slct.getOperand(0).getValueType() 846 : Slct.getOperand(0).getOperand(0).getValueType()); 847 CC = ISD::getSetCCInverse(CC, isInt); 848 DoXform = true; 849 InvCC = true; 850 } 851 852 if (DoXform) { 853 SDOperand Result = DAG.getNode(Opc, VT, OtherOp, RHS); 854 if (isSlctCC) 855 return DAG.getSelectCC(OtherOp, Result, 856 Slct.getOperand(0), Slct.getOperand(1), CC); 857 SDOperand CCOp = Slct.getOperand(0); 858 if (InvCC) 859 CCOp = DAG.getSetCC(CCOp.getValueType(), CCOp.getOperand(0), 860 CCOp.getOperand(1), CC); 861 return DAG.getNode(ISD::SELECT, VT, CCOp, OtherOp, Result); 862 } 863 return SDOperand(); 864} 865 866SDOperand DAGCombiner::visitADD(SDNode *N) { 867 SDOperand N0 = N->getOperand(0); 868 SDOperand N1 = N->getOperand(1); 869 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 870 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 871 MVT::ValueType VT = N0.getValueType(); 872 873 // fold vector ops 874 if (MVT::isVector(VT)) { 875 SDOperand FoldedVOp = SimplifyVBinOp(N); 876 if (FoldedVOp.Val) return FoldedVOp; 877 } 878 879 // fold (add x, undef) -> undef 880 if (N0.getOpcode() == ISD::UNDEF) 881 return N0; 882 if (N1.getOpcode() == ISD::UNDEF) 883 return N1; 884 // fold (add c1, c2) -> c1+c2 885 if (N0C && N1C) 886 return DAG.getNode(ISD::ADD, VT, N0, N1); 887 // canonicalize constant to RHS 888 if (N0C && !N1C) 889 return DAG.getNode(ISD::ADD, VT, N1, N0); 890 // fold (add x, 0) -> x 891 if (N1C && N1C->isNullValue()) 892 return N0; 893 // fold ((c1-A)+c2) -> (c1+c2)-A 894 if (N1C && N0.getOpcode() == ISD::SUB) 895 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 896 return DAG.getNode(ISD::SUB, VT, 897 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT), 898 N0.getOperand(1)); 899 // reassociate add 900 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1); 901 if (RADD.Val != 0) 902 return RADD; 903 // fold ((0-A) + B) -> B-A 904 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 905 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 906 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1)); 907 // fold (A + (0-B)) -> A-B 908 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 909 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 910 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1)); 911 // fold (A+(B-A)) -> B 912 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 913 return N1.getOperand(0); 914 915 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0))) 916 return SDOperand(N, 0); 917 918 // fold (a+b) -> (a|b) iff a and b share no bits. 919 if (MVT::isInteger(VT) && !MVT::isVector(VT)) { 920 uint64_t LHSZero, LHSOne; 921 uint64_t RHSZero, RHSOne; 922 uint64_t Mask = MVT::getIntVTBitMask(VT); 923 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 924 if (LHSZero) { 925 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 926 927 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 928 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 929 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 930 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 931 return DAG.getNode(ISD::OR, VT, N0, N1); 932 } 933 } 934 935 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 936 if (N0.getOpcode() == ISD::SHL && N0.Val->hasOneUse()) { 937 SDOperand Result = combineShlAddConstant(N0, N1, DAG); 938 if (Result.Val) return Result; 939 } 940 if (N1.getOpcode() == ISD::SHL && N1.Val->hasOneUse()) { 941 SDOperand Result = combineShlAddConstant(N1, N0, DAG); 942 if (Result.Val) return Result; 943 } 944 945 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c)) 946 if (N0.getOpcode() == ISD::SELECT && N0.Val->hasOneUse()) { 947 SDOperand Result = combineSelectAndUse(N, N0, N1, DAG); 948 if (Result.Val) return Result; 949 } 950 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) { 951 SDOperand Result = combineSelectAndUse(N, N1, N0, DAG); 952 if (Result.Val) return Result; 953 } 954 955 return SDOperand(); 956} 957 958SDOperand DAGCombiner::visitADDC(SDNode *N) { 959 SDOperand N0 = N->getOperand(0); 960 SDOperand N1 = N->getOperand(1); 961 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 962 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 963 MVT::ValueType VT = N0.getValueType(); 964 965 // If the flag result is dead, turn this into an ADD. 966 if (N->hasNUsesOfValue(0, 1)) 967 return CombineTo(N, DAG.getNode(ISD::ADD, VT, N1, N0), 968 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 969 970 // canonicalize constant to RHS. 971 if (N0C && !N1C) { 972 SDOperand Ops[] = { N1, N0 }; 973 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2); 974 } 975 976 // fold (addc x, 0) -> x + no carry out 977 if (N1C && N1C->isNullValue()) 978 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 979 980 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 981 uint64_t LHSZero, LHSOne; 982 uint64_t RHSZero, RHSOne; 983 uint64_t Mask = MVT::getIntVTBitMask(VT); 984 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 985 if (LHSZero) { 986 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 987 988 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 989 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 990 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 991 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 992 return CombineTo(N, DAG.getNode(ISD::OR, VT, N0, N1), 993 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 994 } 995 996 return SDOperand(); 997} 998 999SDOperand DAGCombiner::visitADDE(SDNode *N) { 1000 SDOperand N0 = N->getOperand(0); 1001 SDOperand N1 = N->getOperand(1); 1002 SDOperand CarryIn = N->getOperand(2); 1003 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1004 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1005 //MVT::ValueType VT = N0.getValueType(); 1006 1007 // canonicalize constant to RHS 1008 if (N0C && !N1C) { 1009 SDOperand Ops[] = { N1, N0, CarryIn }; 1010 return DAG.getNode(ISD::ADDE, N->getVTList(), Ops, 3); 1011 } 1012 1013 // fold (adde x, y, false) -> (addc x, y) 1014 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) { 1015 SDOperand Ops[] = { N1, N0 }; 1016 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2); 1017 } 1018 1019 return SDOperand(); 1020} 1021 1022 1023 1024SDOperand DAGCombiner::visitSUB(SDNode *N) { 1025 SDOperand N0 = N->getOperand(0); 1026 SDOperand N1 = N->getOperand(1); 1027 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1028 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1029 MVT::ValueType VT = N0.getValueType(); 1030 1031 // fold vector ops 1032 if (MVT::isVector(VT)) { 1033 SDOperand FoldedVOp = SimplifyVBinOp(N); 1034 if (FoldedVOp.Val) return FoldedVOp; 1035 } 1036 1037 // fold (sub x, x) -> 0 1038 if (N0 == N1) 1039 return DAG.getConstant(0, N->getValueType(0)); 1040 // fold (sub c1, c2) -> c1-c2 1041 if (N0C && N1C) 1042 return DAG.getNode(ISD::SUB, VT, N0, N1); 1043 // fold (sub x, c) -> (add x, -c) 1044 if (N1C) 1045 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT)); 1046 // fold (A+B)-A -> B 1047 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1048 return N0.getOperand(1); 1049 // fold (A+B)-B -> A 1050 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1051 return N0.getOperand(0); 1052 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c)) 1053 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) { 1054 SDOperand Result = combineSelectAndUse(N, N1, N0, DAG); 1055 if (Result.Val) return Result; 1056 } 1057 // If either operand of a sub is undef, the result is undef 1058 if (N0.getOpcode() == ISD::UNDEF) 1059 return N0; 1060 if (N1.getOpcode() == ISD::UNDEF) 1061 return N1; 1062 1063 return SDOperand(); 1064} 1065 1066SDOperand DAGCombiner::visitMUL(SDNode *N) { 1067 SDOperand N0 = N->getOperand(0); 1068 SDOperand N1 = N->getOperand(1); 1069 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1070 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1071 MVT::ValueType VT = N0.getValueType(); 1072 1073 // fold vector ops 1074 if (MVT::isVector(VT)) { 1075 SDOperand FoldedVOp = SimplifyVBinOp(N); 1076 if (FoldedVOp.Val) return FoldedVOp; 1077 } 1078 1079 // fold (mul x, undef) -> 0 1080 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1081 return DAG.getConstant(0, VT); 1082 // fold (mul c1, c2) -> c1*c2 1083 if (N0C && N1C) 1084 return DAG.getNode(ISD::MUL, VT, N0, N1); 1085 // canonicalize constant to RHS 1086 if (N0C && !N1C) 1087 return DAG.getNode(ISD::MUL, VT, N1, N0); 1088 // fold (mul x, 0) -> 0 1089 if (N1C && N1C->isNullValue()) 1090 return N1; 1091 // fold (mul x, -1) -> 0-x 1092 if (N1C && N1C->isAllOnesValue()) 1093 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 1094 // fold (mul x, (1 << c)) -> x << c 1095 if (N1C && isPowerOf2_64(N1C->getValue())) 1096 return DAG.getNode(ISD::SHL, VT, N0, 1097 DAG.getConstant(Log2_64(N1C->getValue()), 1098 TLI.getShiftAmountTy())); 1099 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1100 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) { 1101 // FIXME: If the input is something that is easily negated (e.g. a 1102 // single-use add), we should put the negate there. 1103 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), 1104 DAG.getNode(ISD::SHL, VT, N0, 1105 DAG.getConstant(Log2_64(-N1C->getSignExtended()), 1106 TLI.getShiftAmountTy()))); 1107 } 1108 1109 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1110 if (N1C && N0.getOpcode() == ISD::SHL && 1111 isa<ConstantSDNode>(N0.getOperand(1))) { 1112 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1)); 1113 AddToWorkList(C3.Val); 1114 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3); 1115 } 1116 1117 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1118 // use. 1119 { 1120 SDOperand Sh(0,0), Y(0,0); 1121 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1122 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1123 N0.Val->hasOneUse()) { 1124 Sh = N0; Y = N1; 1125 } else if (N1.getOpcode() == ISD::SHL && 1126 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) { 1127 Sh = N1; Y = N0; 1128 } 1129 if (Sh.Val) { 1130 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y); 1131 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1)); 1132 } 1133 } 1134 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1135 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() && 1136 isa<ConstantSDNode>(N0.getOperand(1))) { 1137 return DAG.getNode(ISD::ADD, VT, 1138 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1), 1139 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1)); 1140 } 1141 1142 // reassociate mul 1143 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1); 1144 if (RMUL.Val != 0) 1145 return RMUL; 1146 1147 return SDOperand(); 1148} 1149 1150SDOperand DAGCombiner::visitSDIV(SDNode *N) { 1151 SDOperand N0 = N->getOperand(0); 1152 SDOperand N1 = N->getOperand(1); 1153 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1154 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1155 MVT::ValueType VT = N->getValueType(0); 1156 1157 // fold vector ops 1158 if (MVT::isVector(VT)) { 1159 SDOperand FoldedVOp = SimplifyVBinOp(N); 1160 if (FoldedVOp.Val) return FoldedVOp; 1161 } 1162 1163 // fold (sdiv c1, c2) -> c1/c2 1164 if (N0C && N1C && !N1C->isNullValue()) 1165 return DAG.getNode(ISD::SDIV, VT, N0, N1); 1166 // fold (sdiv X, 1) -> X 1167 if (N1C && N1C->getSignExtended() == 1LL) 1168 return N0; 1169 // fold (sdiv X, -1) -> 0-X 1170 if (N1C && N1C->isAllOnesValue()) 1171 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 1172 // If we know the sign bits of both operands are zero, strength reduce to a 1173 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1174 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 1175 if (DAG.MaskedValueIsZero(N1, SignBit) && 1176 DAG.MaskedValueIsZero(N0, SignBit)) 1177 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1); 1178 // fold (sdiv X, pow2) -> simple ops after legalize 1179 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() && 1180 (isPowerOf2_64(N1C->getSignExtended()) || 1181 isPowerOf2_64(-N1C->getSignExtended()))) { 1182 // If dividing by powers of two is cheap, then don't perform the following 1183 // fold. 1184 if (TLI.isPow2DivCheap()) 1185 return SDOperand(); 1186 int64_t pow2 = N1C->getSignExtended(); 1187 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1188 unsigned lg2 = Log2_64(abs2); 1189 // Splat the sign bit into the register 1190 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0, 1191 DAG.getConstant(MVT::getSizeInBits(VT)-1, 1192 TLI.getShiftAmountTy())); 1193 AddToWorkList(SGN.Val); 1194 // Add (N0 < 0) ? abs2 - 1 : 0; 1195 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN, 1196 DAG.getConstant(MVT::getSizeInBits(VT)-lg2, 1197 TLI.getShiftAmountTy())); 1198 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL); 1199 AddToWorkList(SRL.Val); 1200 AddToWorkList(ADD.Val); // Divide by pow2 1201 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD, 1202 DAG.getConstant(lg2, TLI.getShiftAmountTy())); 1203 // If we're dividing by a positive value, we're done. Otherwise, we must 1204 // negate the result. 1205 if (pow2 > 0) 1206 return SRA; 1207 AddToWorkList(SRA.Val); 1208 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA); 1209 } 1210 // if integer divide is expensive and we satisfy the requirements, emit an 1211 // alternate sequence. 1212 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) && 1213 !TLI.isIntDivCheap()) { 1214 SDOperand Op = BuildSDIV(N); 1215 if (Op.Val) return Op; 1216 } 1217 1218 // undef / X -> 0 1219 if (N0.getOpcode() == ISD::UNDEF) 1220 return DAG.getConstant(0, VT); 1221 // X / undef -> undef 1222 if (N1.getOpcode() == ISD::UNDEF) 1223 return N1; 1224 1225 return SDOperand(); 1226} 1227 1228SDOperand DAGCombiner::visitUDIV(SDNode *N) { 1229 SDOperand N0 = N->getOperand(0); 1230 SDOperand N1 = N->getOperand(1); 1231 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1232 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1233 MVT::ValueType VT = N->getValueType(0); 1234 1235 // fold vector ops 1236 if (MVT::isVector(VT)) { 1237 SDOperand FoldedVOp = SimplifyVBinOp(N); 1238 if (FoldedVOp.Val) return FoldedVOp; 1239 } 1240 1241 // fold (udiv c1, c2) -> c1/c2 1242 if (N0C && N1C && !N1C->isNullValue()) 1243 return DAG.getNode(ISD::UDIV, VT, N0, N1); 1244 // fold (udiv x, (1 << c)) -> x >>u c 1245 if (N1C && isPowerOf2_64(N1C->getValue())) 1246 return DAG.getNode(ISD::SRL, VT, N0, 1247 DAG.getConstant(Log2_64(N1C->getValue()), 1248 TLI.getShiftAmountTy())); 1249 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1250 if (N1.getOpcode() == ISD::SHL) { 1251 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1252 if (isPowerOf2_64(SHC->getValue())) { 1253 MVT::ValueType ADDVT = N1.getOperand(1).getValueType(); 1254 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1), 1255 DAG.getConstant(Log2_64(SHC->getValue()), 1256 ADDVT)); 1257 AddToWorkList(Add.Val); 1258 return DAG.getNode(ISD::SRL, VT, N0, Add); 1259 } 1260 } 1261 } 1262 // fold (udiv x, c) -> alternate 1263 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) { 1264 SDOperand Op = BuildUDIV(N); 1265 if (Op.Val) return Op; 1266 } 1267 1268 // undef / X -> 0 1269 if (N0.getOpcode() == ISD::UNDEF) 1270 return DAG.getConstant(0, VT); 1271 // X / undef -> undef 1272 if (N1.getOpcode() == ISD::UNDEF) 1273 return N1; 1274 1275 return SDOperand(); 1276} 1277 1278SDOperand DAGCombiner::visitSREM(SDNode *N) { 1279 SDOperand N0 = N->getOperand(0); 1280 SDOperand N1 = N->getOperand(1); 1281 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1282 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1283 MVT::ValueType VT = N->getValueType(0); 1284 1285 // fold (srem c1, c2) -> c1%c2 1286 if (N0C && N1C && !N1C->isNullValue()) 1287 return DAG.getNode(ISD::SREM, VT, N0, N1); 1288 // If we know the sign bits of both operands are zero, strength reduce to a 1289 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1290 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 1291 if (DAG.MaskedValueIsZero(N1, SignBit) && 1292 DAG.MaskedValueIsZero(N0, SignBit)) 1293 return DAG.getNode(ISD::UREM, VT, N0, N1); 1294 1295 // If X/C can be simplified by the division-by-constant logic, lower 1296 // X%C to the equivalent of X-X/C*C. 1297 if (N1C && !N1C->isNullValue()) { 1298 SDOperand Div = DAG.getNode(ISD::SDIV, VT, N0, N1); 1299 SDOperand OptimizedDiv = combine(Div.Val); 1300 if (OptimizedDiv.Val && OptimizedDiv.Val != Div.Val) { 1301 SDOperand Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1); 1302 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1303 AddToWorkList(Mul.Val); 1304 return Sub; 1305 } 1306 } 1307 1308 // undef % X -> 0 1309 if (N0.getOpcode() == ISD::UNDEF) 1310 return DAG.getConstant(0, VT); 1311 // X % undef -> undef 1312 if (N1.getOpcode() == ISD::UNDEF) 1313 return N1; 1314 1315 return SDOperand(); 1316} 1317 1318SDOperand DAGCombiner::visitUREM(SDNode *N) { 1319 SDOperand N0 = N->getOperand(0); 1320 SDOperand N1 = N->getOperand(1); 1321 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1322 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1323 MVT::ValueType VT = N->getValueType(0); 1324 1325 // fold (urem c1, c2) -> c1%c2 1326 if (N0C && N1C && !N1C->isNullValue()) 1327 return DAG.getNode(ISD::UREM, VT, N0, N1); 1328 // fold (urem x, pow2) -> (and x, pow2-1) 1329 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue())) 1330 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT)); 1331 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1332 if (N1.getOpcode() == ISD::SHL) { 1333 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1334 if (isPowerOf2_64(SHC->getValue())) { 1335 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT)); 1336 AddToWorkList(Add.Val); 1337 return DAG.getNode(ISD::AND, VT, N0, Add); 1338 } 1339 } 1340 } 1341 1342 // If X/C can be simplified by the division-by-constant logic, lower 1343 // X%C to the equivalent of X-X/C*C. 1344 if (N1C && !N1C->isNullValue()) { 1345 SDOperand Div = DAG.getNode(ISD::UDIV, VT, N0, N1); 1346 SDOperand OptimizedDiv = combine(Div.Val); 1347 if (OptimizedDiv.Val && OptimizedDiv.Val != Div.Val) { 1348 SDOperand Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1); 1349 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1350 AddToWorkList(Mul.Val); 1351 return Sub; 1352 } 1353 } 1354 1355 // undef % X -> 0 1356 if (N0.getOpcode() == ISD::UNDEF) 1357 return DAG.getConstant(0, VT); 1358 // X % undef -> undef 1359 if (N1.getOpcode() == ISD::UNDEF) 1360 return N1; 1361 1362 return SDOperand(); 1363} 1364 1365SDOperand DAGCombiner::visitMULHS(SDNode *N) { 1366 SDOperand N0 = N->getOperand(0); 1367 SDOperand N1 = N->getOperand(1); 1368 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1369 MVT::ValueType VT = N->getValueType(0); 1370 1371 // fold (mulhs x, 0) -> 0 1372 if (N1C && N1C->isNullValue()) 1373 return N1; 1374 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1375 if (N1C && N1C->getValue() == 1) 1376 return DAG.getNode(ISD::SRA, N0.getValueType(), N0, 1377 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1, 1378 TLI.getShiftAmountTy())); 1379 // fold (mulhs x, undef) -> 0 1380 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1381 return DAG.getConstant(0, VT); 1382 1383 return SDOperand(); 1384} 1385 1386SDOperand DAGCombiner::visitMULHU(SDNode *N) { 1387 SDOperand N0 = N->getOperand(0); 1388 SDOperand N1 = N->getOperand(1); 1389 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1390 MVT::ValueType VT = N->getValueType(0); 1391 1392 // fold (mulhu x, 0) -> 0 1393 if (N1C && N1C->isNullValue()) 1394 return N1; 1395 // fold (mulhu x, 1) -> 0 1396 if (N1C && N1C->getValue() == 1) 1397 return DAG.getConstant(0, N0.getValueType()); 1398 // fold (mulhu x, undef) -> 0 1399 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1400 return DAG.getConstant(0, VT); 1401 1402 return SDOperand(); 1403} 1404 1405/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 1406/// compute two values. LoOp and HiOp give the opcodes for the two computations 1407/// that are being performed. Return true if a simplification was made. 1408/// 1409bool DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, 1410 unsigned LoOp, unsigned HiOp) { 1411 // If the high half is not needed, just compute the low half. 1412 bool HiExists = N->hasAnyUseOfValue(1); 1413 if (!HiExists && 1414 (!AfterLegalize || 1415 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 1416 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), 1417 DAG.getNode(LoOp, N->getValueType(0), 1418 N->op_begin(), 1419 N->getNumOperands())); 1420 return true; 1421 } 1422 1423 // If the low half is not needed, just compute the high half. 1424 bool LoExists = N->hasAnyUseOfValue(0); 1425 if (!LoExists && 1426 (!AfterLegalize || 1427 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 1428 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), 1429 DAG.getNode(HiOp, N->getValueType(1), 1430 N->op_begin(), 1431 N->getNumOperands())); 1432 return true; 1433 } 1434 1435 // If both halves are used, return as it is. 1436 if (LoExists && HiExists) 1437 return false; 1438 1439 // If the two computed results can be simplified separately, separate them. 1440 bool RetVal = false; 1441 if (LoExists) { 1442 SDOperand Lo = DAG.getNode(LoOp, N->getValueType(0), 1443 N->op_begin(), N->getNumOperands()); 1444 SDOperand LoOpt = combine(Lo.Val); 1445 if (LoOpt.Val && LoOpt != Lo && 1446 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())) { 1447 RetVal = true; 1448 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), LoOpt); 1449 } 1450 } 1451 1452 if (HiExists) { 1453 SDOperand Hi = DAG.getNode(HiOp, N->getValueType(1), 1454 N->op_begin(), N->getNumOperands()); 1455 SDOperand HiOpt = combine(Hi.Val); 1456 if (HiOpt.Val && HiOpt != Hi && 1457 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())) { 1458 RetVal = true; 1459 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), HiOpt); 1460 } 1461 } 1462 1463 return RetVal; 1464} 1465 1466SDOperand DAGCombiner::visitSMUL_LOHI(SDNode *N) { 1467 1468 if (SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS)) 1469 return SDOperand(); 1470 1471 return SDOperand(); 1472} 1473 1474SDOperand DAGCombiner::visitUMUL_LOHI(SDNode *N) { 1475 1476 if (SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU)) 1477 return SDOperand(); 1478 1479 return SDOperand(); 1480} 1481 1482SDOperand DAGCombiner::visitSDIVREM(SDNode *N) { 1483 1484 if (SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM)) 1485 return SDOperand(); 1486 1487 return SDOperand(); 1488} 1489 1490SDOperand DAGCombiner::visitUDIVREM(SDNode *N) { 1491 1492 if (SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM)) 1493 return SDOperand(); 1494 1495 return SDOperand(); 1496} 1497 1498/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 1499/// two operands of the same opcode, try to simplify it. 1500SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 1501 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1); 1502 MVT::ValueType VT = N0.getValueType(); 1503 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 1504 1505 // For each of OP in AND/OR/XOR: 1506 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 1507 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 1508 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 1509 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) 1510 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND|| 1511 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) && 1512 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1513 SDOperand ORNode = DAG.getNode(N->getOpcode(), 1514 N0.getOperand(0).getValueType(), 1515 N0.getOperand(0), N1.getOperand(0)); 1516 AddToWorkList(ORNode.Val); 1517 return DAG.getNode(N0.getOpcode(), VT, ORNode); 1518 } 1519 1520 // For each of OP in SHL/SRL/SRA/AND... 1521 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 1522 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 1523 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 1524 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 1525 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 1526 N0.getOperand(1) == N1.getOperand(1)) { 1527 SDOperand ORNode = DAG.getNode(N->getOpcode(), 1528 N0.getOperand(0).getValueType(), 1529 N0.getOperand(0), N1.getOperand(0)); 1530 AddToWorkList(ORNode.Val); 1531 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1)); 1532 } 1533 1534 return SDOperand(); 1535} 1536 1537SDOperand DAGCombiner::visitAND(SDNode *N) { 1538 SDOperand N0 = N->getOperand(0); 1539 SDOperand N1 = N->getOperand(1); 1540 SDOperand LL, LR, RL, RR, CC0, CC1; 1541 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1542 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1543 MVT::ValueType VT = N1.getValueType(); 1544 1545 // fold vector ops 1546 if (MVT::isVector(VT)) { 1547 SDOperand FoldedVOp = SimplifyVBinOp(N); 1548 if (FoldedVOp.Val) return FoldedVOp; 1549 } 1550 1551 // fold (and x, undef) -> 0 1552 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1553 return DAG.getConstant(0, VT); 1554 // fold (and c1, c2) -> c1&c2 1555 if (N0C && N1C) 1556 return DAG.getNode(ISD::AND, VT, N0, N1); 1557 // canonicalize constant to RHS 1558 if (N0C && !N1C) 1559 return DAG.getNode(ISD::AND, VT, N1, N0); 1560 // fold (and x, -1) -> x 1561 if (N1C && N1C->isAllOnesValue()) 1562 return N0; 1563 // if (and x, c) is known to be zero, return 0 1564 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) 1565 return DAG.getConstant(0, VT); 1566 // reassociate and 1567 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1); 1568 if (RAND.Val != 0) 1569 return RAND; 1570 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 1571 if (N1C && N0.getOpcode() == ISD::OR) 1572 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1573 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue()) 1574 return N1; 1575 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 1576 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1577 unsigned InMask = MVT::getIntVTBitMask(N0.getOperand(0).getValueType()); 1578 if (DAG.MaskedValueIsZero(N0.getOperand(0), 1579 ~N1C->getValue() & InMask)) { 1580 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(), 1581 N0.getOperand(0)); 1582 1583 // Replace uses of the AND with uses of the Zero extend node. 1584 CombineTo(N, Zext); 1585 1586 // We actually want to replace all uses of the any_extend with the 1587 // zero_extend, to avoid duplicating things. This will later cause this 1588 // AND to be folded. 1589 CombineTo(N0.Val, Zext); 1590 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1591 } 1592 } 1593 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 1594 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1595 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1596 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1597 1598 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1599 MVT::isInteger(LL.getValueType())) { 1600 // fold (X == 0) & (Y == 0) -> (X|Y == 0) 1601 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) { 1602 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1603 AddToWorkList(ORNode.Val); 1604 return DAG.getSetCC(VT, ORNode, LR, Op1); 1605 } 1606 // fold (X == -1) & (Y == -1) -> (X&Y == -1) 1607 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 1608 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1609 AddToWorkList(ANDNode.Val); 1610 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1611 } 1612 // fold (X > -1) & (Y > -1) -> (X|Y > -1) 1613 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1614 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1615 AddToWorkList(ORNode.Val); 1616 return DAG.getSetCC(VT, ORNode, LR, Op1); 1617 } 1618 } 1619 // canonicalize equivalent to ll == rl 1620 if (LL == RR && LR == RL) { 1621 Op1 = ISD::getSetCCSwappedOperands(Op1); 1622 std::swap(RL, RR); 1623 } 1624 if (LL == RL && LR == RR) { 1625 bool isInteger = MVT::isInteger(LL.getValueType()); 1626 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1627 if (Result != ISD::SETCC_INVALID) 1628 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1629 } 1630 } 1631 1632 // Simplify: and (op x...), (op y...) -> (op (and x, y)) 1633 if (N0.getOpcode() == N1.getOpcode()) { 1634 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1635 if (Tmp.Val) return Tmp; 1636 } 1637 1638 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1639 // fold (and (sra)) -> (and (srl)) when possible. 1640 if (!MVT::isVector(VT) && 1641 SimplifyDemandedBits(SDOperand(N, 0))) 1642 return SDOperand(N, 0); 1643 // fold (zext_inreg (extload x)) -> (zextload x) 1644 if (ISD::isEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val)) { 1645 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1646 MVT::ValueType EVT = LN0->getLoadedVT(); 1647 // If we zero all the possible extended bits, then we can turn this into 1648 // a zextload if we are running before legalize or the operation is legal. 1649 if (DAG.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && 1650 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1651 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1652 LN0->getBasePtr(), LN0->getSrcValue(), 1653 LN0->getSrcValueOffset(), EVT, 1654 LN0->isVolatile(), 1655 LN0->getAlignment()); 1656 AddToWorkList(N); 1657 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1658 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1659 } 1660 } 1661 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1662 if (ISD::isSEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 1663 N0.hasOneUse()) { 1664 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1665 MVT::ValueType EVT = LN0->getLoadedVT(); 1666 // If we zero all the possible extended bits, then we can turn this into 1667 // a zextload if we are running before legalize or the operation is legal. 1668 if (DAG.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && 1669 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1670 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1671 LN0->getBasePtr(), LN0->getSrcValue(), 1672 LN0->getSrcValueOffset(), EVT, 1673 LN0->isVolatile(), 1674 LN0->getAlignment()); 1675 AddToWorkList(N); 1676 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1677 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1678 } 1679 } 1680 1681 // fold (and (load x), 255) -> (zextload x, i8) 1682 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1683 if (N1C && N0.getOpcode() == ISD::LOAD) { 1684 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1685 if (LN0->getExtensionType() != ISD::SEXTLOAD && 1686 LN0->getAddressingMode() == ISD::UNINDEXED && 1687 N0.hasOneUse()) { 1688 MVT::ValueType EVT, LoadedVT; 1689 if (N1C->getValue() == 255) 1690 EVT = MVT::i8; 1691 else if (N1C->getValue() == 65535) 1692 EVT = MVT::i16; 1693 else if (N1C->getValue() == ~0U) 1694 EVT = MVT::i32; 1695 else 1696 EVT = MVT::Other; 1697 1698 LoadedVT = LN0->getLoadedVT(); 1699 if (EVT != MVT::Other && LoadedVT > EVT && 1700 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1701 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 1702 // For big endian targets, we need to add an offset to the pointer to 1703 // load the correct bytes. For little endian systems, we merely need to 1704 // read fewer bytes from the same pointer. 1705 unsigned LVTStoreBytes = MVT::getStoreSizeInBits(LoadedVT)/8; 1706 unsigned EVTStoreBytes = MVT::getStoreSizeInBits(EVT)/8; 1707 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 1708 unsigned Alignment = LN0->getAlignment(); 1709 SDOperand NewPtr = LN0->getBasePtr(); 1710 if (!TLI.isLittleEndian()) { 1711 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, 1712 DAG.getConstant(PtrOff, PtrType)); 1713 Alignment = MinAlign(Alignment, PtrOff); 1714 } 1715 AddToWorkList(NewPtr.Val); 1716 SDOperand Load = 1717 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr, 1718 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT, 1719 LN0->isVolatile(), Alignment); 1720 AddToWorkList(N); 1721 CombineTo(N0.Val, Load, Load.getValue(1)); 1722 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1723 } 1724 } 1725 } 1726 1727 return SDOperand(); 1728} 1729 1730SDOperand DAGCombiner::visitOR(SDNode *N) { 1731 SDOperand N0 = N->getOperand(0); 1732 SDOperand N1 = N->getOperand(1); 1733 SDOperand LL, LR, RL, RR, CC0, CC1; 1734 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1735 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1736 MVT::ValueType VT = N1.getValueType(); 1737 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1738 1739 // fold vector ops 1740 if (MVT::isVector(VT)) { 1741 SDOperand FoldedVOp = SimplifyVBinOp(N); 1742 if (FoldedVOp.Val) return FoldedVOp; 1743 } 1744 1745 // fold (or x, undef) -> -1 1746 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1747 return DAG.getConstant(~0ULL, VT); 1748 // fold (or c1, c2) -> c1|c2 1749 if (N0C && N1C) 1750 return DAG.getNode(ISD::OR, VT, N0, N1); 1751 // canonicalize constant to RHS 1752 if (N0C && !N1C) 1753 return DAG.getNode(ISD::OR, VT, N1, N0); 1754 // fold (or x, 0) -> x 1755 if (N1C && N1C->isNullValue()) 1756 return N0; 1757 // fold (or x, -1) -> -1 1758 if (N1C && N1C->isAllOnesValue()) 1759 return N1; 1760 // fold (or x, c) -> c iff (x & ~c) == 0 1761 if (N1C && 1762 DAG.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)))) 1763 return N1; 1764 // reassociate or 1765 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1); 1766 if (ROR.Val != 0) 1767 return ROR; 1768 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 1769 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() && 1770 isa<ConstantSDNode>(N0.getOperand(1))) { 1771 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 1772 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0), 1773 N1), 1774 DAG.getConstant(N1C->getValue() | C1->getValue(), VT)); 1775 } 1776 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 1777 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1778 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1779 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1780 1781 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1782 MVT::isInteger(LL.getValueType())) { 1783 // fold (X != 0) | (Y != 0) -> (X|Y != 0) 1784 // fold (X < 0) | (Y < 0) -> (X|Y < 0) 1785 if (cast<ConstantSDNode>(LR)->getValue() == 0 && 1786 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 1787 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1788 AddToWorkList(ORNode.Val); 1789 return DAG.getSetCC(VT, ORNode, LR, Op1); 1790 } 1791 // fold (X != -1) | (Y != -1) -> (X&Y != -1) 1792 // fold (X > -1) | (Y > -1) -> (X&Y > -1) 1793 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 1794 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 1795 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1796 AddToWorkList(ANDNode.Val); 1797 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1798 } 1799 } 1800 // canonicalize equivalent to ll == rl 1801 if (LL == RR && LR == RL) { 1802 Op1 = ISD::getSetCCSwappedOperands(Op1); 1803 std::swap(RL, RR); 1804 } 1805 if (LL == RL && LR == RR) { 1806 bool isInteger = MVT::isInteger(LL.getValueType()); 1807 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 1808 if (Result != ISD::SETCC_INVALID) 1809 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1810 } 1811 } 1812 1813 // Simplify: or (op x...), (op y...) -> (op (or x, y)) 1814 if (N0.getOpcode() == N1.getOpcode()) { 1815 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1816 if (Tmp.Val) return Tmp; 1817 } 1818 1819 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible. 1820 if (N0.getOpcode() == ISD::AND && 1821 N1.getOpcode() == ISD::AND && 1822 N0.getOperand(1).getOpcode() == ISD::Constant && 1823 N1.getOperand(1).getOpcode() == ISD::Constant && 1824 // Don't increase # computations. 1825 (N0.Val->hasOneUse() || N1.Val->hasOneUse())) { 1826 // We can only do this xform if we know that bits from X that are set in C2 1827 // but not in C1 are already zero. Likewise for Y. 1828 uint64_t LHSMask = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1829 uint64_t RHSMask = cast<ConstantSDNode>(N1.getOperand(1))->getValue(); 1830 1831 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 1832 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 1833 SDOperand X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0)); 1834 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT)); 1835 } 1836 } 1837 1838 1839 // See if this is some rotate idiom. 1840 if (SDNode *Rot = MatchRotate(N0, N1)) 1841 return SDOperand(Rot, 0); 1842 1843 return SDOperand(); 1844} 1845 1846 1847/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 1848static bool MatchRotateHalf(SDOperand Op, SDOperand &Shift, SDOperand &Mask) { 1849 if (Op.getOpcode() == ISD::AND) { 1850 if (isa<ConstantSDNode>(Op.getOperand(1))) { 1851 Mask = Op.getOperand(1); 1852 Op = Op.getOperand(0); 1853 } else { 1854 return false; 1855 } 1856 } 1857 1858 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 1859 Shift = Op; 1860 return true; 1861 } 1862 return false; 1863} 1864 1865 1866// MatchRotate - Handle an 'or' of two operands. If this is one of the many 1867// idioms for rotate, and if the target supports rotation instructions, generate 1868// a rot[lr]. 1869SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) { 1870 // Must be a legal type. Expanded an promoted things won't work with rotates. 1871 MVT::ValueType VT = LHS.getValueType(); 1872 if (!TLI.isTypeLegal(VT)) return 0; 1873 1874 // The target must have at least one rotate flavor. 1875 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT); 1876 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT); 1877 if (!HasROTL && !HasROTR) return 0; 1878 1879 // Match "(X shl/srl V1) & V2" where V2 may not be present. 1880 SDOperand LHSShift; // The shift. 1881 SDOperand LHSMask; // AND value if any. 1882 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 1883 return 0; // Not part of a rotate. 1884 1885 SDOperand RHSShift; // The shift. 1886 SDOperand RHSMask; // AND value if any. 1887 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 1888 return 0; // Not part of a rotate. 1889 1890 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 1891 return 0; // Not shifting the same value. 1892 1893 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 1894 return 0; // Shifts must disagree. 1895 1896 // Canonicalize shl to left side in a shl/srl pair. 1897 if (RHSShift.getOpcode() == ISD::SHL) { 1898 std::swap(LHS, RHS); 1899 std::swap(LHSShift, RHSShift); 1900 std::swap(LHSMask , RHSMask ); 1901 } 1902 1903 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1904 SDOperand LHSShiftArg = LHSShift.getOperand(0); 1905 SDOperand LHSShiftAmt = LHSShift.getOperand(1); 1906 SDOperand RHSShiftAmt = RHSShift.getOperand(1); 1907 1908 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 1909 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 1910 if (LHSShiftAmt.getOpcode() == ISD::Constant && 1911 RHSShiftAmt.getOpcode() == ISD::Constant) { 1912 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getValue(); 1913 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getValue(); 1914 if ((LShVal + RShVal) != OpSizeInBits) 1915 return 0; 1916 1917 SDOperand Rot; 1918 if (HasROTL) 1919 Rot = DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt); 1920 else 1921 Rot = DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt); 1922 1923 // If there is an AND of either shifted operand, apply it to the result. 1924 if (LHSMask.Val || RHSMask.Val) { 1925 uint64_t Mask = MVT::getIntVTBitMask(VT); 1926 1927 if (LHSMask.Val) { 1928 uint64_t RHSBits = (1ULL << LShVal)-1; 1929 Mask &= cast<ConstantSDNode>(LHSMask)->getValue() | RHSBits; 1930 } 1931 if (RHSMask.Val) { 1932 uint64_t LHSBits = ~((1ULL << (OpSizeInBits-RShVal))-1); 1933 Mask &= cast<ConstantSDNode>(RHSMask)->getValue() | LHSBits; 1934 } 1935 1936 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT)); 1937 } 1938 1939 return Rot.Val; 1940 } 1941 1942 // If there is a mask here, and we have a variable shift, we can't be sure 1943 // that we're masking out the right stuff. 1944 if (LHSMask.Val || RHSMask.Val) 1945 return 0; 1946 1947 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 1948 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 1949 if (RHSShiftAmt.getOpcode() == ISD::SUB && 1950 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 1951 if (ConstantSDNode *SUBC = 1952 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 1953 if (SUBC->getValue() == OpSizeInBits) 1954 if (HasROTL) 1955 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 1956 else 1957 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 1958 } 1959 } 1960 1961 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 1962 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 1963 if (LHSShiftAmt.getOpcode() == ISD::SUB && 1964 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 1965 if (ConstantSDNode *SUBC = 1966 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 1967 if (SUBC->getValue() == OpSizeInBits) 1968 if (HasROTL) 1969 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 1970 else 1971 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 1972 } 1973 } 1974 1975 // Look for sign/zext/any-extended cases: 1976 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 1977 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 1978 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND) && 1979 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 1980 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 1981 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND)) { 1982 SDOperand LExtOp0 = LHSShiftAmt.getOperand(0); 1983 SDOperand RExtOp0 = RHSShiftAmt.getOperand(0); 1984 if (RExtOp0.getOpcode() == ISD::SUB && 1985 RExtOp0.getOperand(1) == LExtOp0) { 1986 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 1987 // (rotr x, y) 1988 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 1989 // (rotl x, (sub 32, y)) 1990 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 1991 if (SUBC->getValue() == OpSizeInBits) { 1992 if (HasROTL) 1993 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 1994 else 1995 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 1996 } 1997 } 1998 } else if (LExtOp0.getOpcode() == ISD::SUB && 1999 RExtOp0 == LExtOp0.getOperand(1)) { 2000 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -> 2001 // (rotl x, y) 2002 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -> 2003 // (rotr x, (sub 32, y)) 2004 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 2005 if (SUBC->getValue() == OpSizeInBits) { 2006 if (HasROTL) 2007 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, RHSShiftAmt).Val; 2008 else 2009 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 2010 } 2011 } 2012 } 2013 } 2014 2015 return 0; 2016} 2017 2018 2019SDOperand DAGCombiner::visitXOR(SDNode *N) { 2020 SDOperand N0 = N->getOperand(0); 2021 SDOperand N1 = N->getOperand(1); 2022 SDOperand LHS, RHS, CC; 2023 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2024 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2025 MVT::ValueType VT = N0.getValueType(); 2026 2027 // fold vector ops 2028 if (MVT::isVector(VT)) { 2029 SDOperand FoldedVOp = SimplifyVBinOp(N); 2030 if (FoldedVOp.Val) return FoldedVOp; 2031 } 2032 2033 // fold (xor x, undef) -> undef 2034 if (N0.getOpcode() == ISD::UNDEF) 2035 return N0; 2036 if (N1.getOpcode() == ISD::UNDEF) 2037 return N1; 2038 // fold (xor c1, c2) -> c1^c2 2039 if (N0C && N1C) 2040 return DAG.getNode(ISD::XOR, VT, N0, N1); 2041 // canonicalize constant to RHS 2042 if (N0C && !N1C) 2043 return DAG.getNode(ISD::XOR, VT, N1, N0); 2044 // fold (xor x, 0) -> x 2045 if (N1C && N1C->isNullValue()) 2046 return N0; 2047 // reassociate xor 2048 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1); 2049 if (RXOR.Val != 0) 2050 return RXOR; 2051 // fold !(x cc y) -> (x !cc y) 2052 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 2053 bool isInt = MVT::isInteger(LHS.getValueType()); 2054 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 2055 isInt); 2056 if (N0.getOpcode() == ISD::SETCC) 2057 return DAG.getSetCC(VT, LHS, RHS, NotCC); 2058 if (N0.getOpcode() == ISD::SELECT_CC) 2059 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC); 2060 assert(0 && "Unhandled SetCC Equivalent!"); 2061 abort(); 2062 } 2063 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 2064 if (N1C && N1C->getValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 2065 N0.Val->hasOneUse() && isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 2066 SDOperand V = N0.getOperand(0); 2067 V = DAG.getNode(ISD::XOR, V.getValueType(), V, 2068 DAG.getConstant(1, V.getValueType())); 2069 AddToWorkList(V.Val); 2070 return DAG.getNode(ISD::ZERO_EXTEND, VT, V); 2071 } 2072 2073 // fold !(x or y) -> (!x and !y) iff x or y are setcc 2074 if (N1C && N1C->getValue() == 1 && VT == MVT::i1 && 2075 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2076 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2077 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 2078 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2079 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 2080 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 2081 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 2082 return DAG.getNode(NewOpcode, VT, LHS, RHS); 2083 } 2084 } 2085 // fold !(x or y) -> (!x and !y) iff x or y are constants 2086 if (N1C && N1C->isAllOnesValue() && 2087 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2088 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2089 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 2090 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2091 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 2092 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 2093 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 2094 return DAG.getNode(NewOpcode, VT, LHS, RHS); 2095 } 2096 } 2097 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2) 2098 if (N1C && N0.getOpcode() == ISD::XOR) { 2099 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 2100 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2101 if (N00C) 2102 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1), 2103 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT)); 2104 if (N01C) 2105 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0), 2106 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT)); 2107 } 2108 // fold (xor x, x) -> 0 2109 if (N0 == N1) { 2110 if (!MVT::isVector(VT)) { 2111 return DAG.getConstant(0, VT); 2112 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 2113 // Produce a vector of zeros. 2114 SDOperand El = DAG.getConstant(0, MVT::getVectorElementType(VT)); 2115 std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El); 2116 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 2117 } 2118 } 2119 2120 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 2121 if (N0.getOpcode() == N1.getOpcode()) { 2122 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2123 if (Tmp.Val) return Tmp; 2124 } 2125 2126 // Simplify the expression using non-local knowledge. 2127 if (!MVT::isVector(VT) && 2128 SimplifyDemandedBits(SDOperand(N, 0))) 2129 return SDOperand(N, 0); 2130 2131 return SDOperand(); 2132} 2133 2134/// visitShiftByConstant - Handle transforms common to the three shifts, when 2135/// the shift amount is a constant. 2136SDOperand DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 2137 SDNode *LHS = N->getOperand(0).Val; 2138 if (!LHS->hasOneUse()) return SDOperand(); 2139 2140 // We want to pull some binops through shifts, so that we have (and (shift)) 2141 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 2142 // thing happens with address calculations, so it's important to canonicalize 2143 // it. 2144 bool HighBitSet = false; // Can we transform this if the high bit is set? 2145 2146 switch (LHS->getOpcode()) { 2147 default: return SDOperand(); 2148 case ISD::OR: 2149 case ISD::XOR: 2150 HighBitSet = false; // We can only transform sra if the high bit is clear. 2151 break; 2152 case ISD::AND: 2153 HighBitSet = true; // We can only transform sra if the high bit is set. 2154 break; 2155 case ISD::ADD: 2156 if (N->getOpcode() != ISD::SHL) 2157 return SDOperand(); // only shl(add) not sr[al](add). 2158 HighBitSet = false; // We can only transform sra if the high bit is clear. 2159 break; 2160 } 2161 2162 // We require the RHS of the binop to be a constant as well. 2163 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 2164 if (!BinOpCst) return SDOperand(); 2165 2166 2167 // FIXME: disable this for unless the input to the binop is a shift by a 2168 // constant. If it is not a shift, it pessimizes some common cases like: 2169 // 2170 //void foo(int *X, int i) { X[i & 1235] = 1; } 2171 //int bar(int *X, int i) { return X[i & 255]; } 2172 SDNode *BinOpLHSVal = LHS->getOperand(0).Val; 2173 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 2174 BinOpLHSVal->getOpcode() != ISD::SRA && 2175 BinOpLHSVal->getOpcode() != ISD::SRL) || 2176 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 2177 return SDOperand(); 2178 2179 MVT::ValueType VT = N->getValueType(0); 2180 2181 // If this is a signed shift right, and the high bit is modified 2182 // by the logical operation, do not perform the transformation. 2183 // The highBitSet boolean indicates the value of the high bit of 2184 // the constant which would cause it to be modified for this 2185 // operation. 2186 if (N->getOpcode() == ISD::SRA) { 2187 uint64_t BinOpRHSSign = BinOpCst->getValue() >> MVT::getSizeInBits(VT)-1; 2188 if ((bool)BinOpRHSSign != HighBitSet) 2189 return SDOperand(); 2190 } 2191 2192 // Fold the constants, shifting the binop RHS by the shift amount. 2193 SDOperand NewRHS = DAG.getNode(N->getOpcode(), N->getValueType(0), 2194 LHS->getOperand(1), N->getOperand(1)); 2195 2196 // Create the new shift. 2197 SDOperand NewShift = DAG.getNode(N->getOpcode(), VT, LHS->getOperand(0), 2198 N->getOperand(1)); 2199 2200 // Create the new binop. 2201 return DAG.getNode(LHS->getOpcode(), VT, NewShift, NewRHS); 2202} 2203 2204 2205SDOperand DAGCombiner::visitSHL(SDNode *N) { 2206 SDOperand N0 = N->getOperand(0); 2207 SDOperand N1 = N->getOperand(1); 2208 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2209 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2210 MVT::ValueType VT = N0.getValueType(); 2211 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 2212 2213 // fold (shl c1, c2) -> c1<<c2 2214 if (N0C && N1C) 2215 return DAG.getNode(ISD::SHL, VT, N0, N1); 2216 // fold (shl 0, x) -> 0 2217 if (N0C && N0C->isNullValue()) 2218 return N0; 2219 // fold (shl x, c >= size(x)) -> undef 2220 if (N1C && N1C->getValue() >= OpSizeInBits) 2221 return DAG.getNode(ISD::UNDEF, VT); 2222 // fold (shl x, 0) -> x 2223 if (N1C && N1C->isNullValue()) 2224 return N0; 2225 // if (shl x, c) is known to be zero, return 0 2226 if (DAG.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) 2227 return DAG.getConstant(0, VT); 2228 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 2229 return SDOperand(N, 0); 2230 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2) 2231 if (N1C && N0.getOpcode() == ISD::SHL && 2232 N0.getOperand(1).getOpcode() == ISD::Constant) { 2233 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2234 uint64_t c2 = N1C->getValue(); 2235 if (c1 + c2 > OpSizeInBits) 2236 return DAG.getConstant(0, VT); 2237 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0), 2238 DAG.getConstant(c1 + c2, N1.getValueType())); 2239 } 2240 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or 2241 // (srl (and x, -1 << c1), c1-c2) 2242 if (N1C && N0.getOpcode() == ISD::SRL && 2243 N0.getOperand(1).getOpcode() == ISD::Constant) { 2244 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2245 uint64_t c2 = N1C->getValue(); 2246 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0), 2247 DAG.getConstant(~0ULL << c1, VT)); 2248 if (c2 > c1) 2249 return DAG.getNode(ISD::SHL, VT, Mask, 2250 DAG.getConstant(c2-c1, N1.getValueType())); 2251 else 2252 return DAG.getNode(ISD::SRL, VT, Mask, 2253 DAG.getConstant(c1-c2, N1.getValueType())); 2254 } 2255 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1) 2256 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 2257 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 2258 DAG.getConstant(~0ULL << N1C->getValue(), VT)); 2259 2260 return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDOperand(); 2261} 2262 2263SDOperand DAGCombiner::visitSRA(SDNode *N) { 2264 SDOperand N0 = N->getOperand(0); 2265 SDOperand N1 = N->getOperand(1); 2266 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2267 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2268 MVT::ValueType VT = N0.getValueType(); 2269 2270 // fold (sra c1, c2) -> c1>>c2 2271 if (N0C && N1C) 2272 return DAG.getNode(ISD::SRA, VT, N0, N1); 2273 // fold (sra 0, x) -> 0 2274 if (N0C && N0C->isNullValue()) 2275 return N0; 2276 // fold (sra -1, x) -> -1 2277 if (N0C && N0C->isAllOnesValue()) 2278 return N0; 2279 // fold (sra x, c >= size(x)) -> undef 2280 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT)) 2281 return DAG.getNode(ISD::UNDEF, VT); 2282 // fold (sra x, 0) -> x 2283 if (N1C && N1C->isNullValue()) 2284 return N0; 2285 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 2286 // sext_inreg. 2287 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 2288 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue(); 2289 MVT::ValueType EVT; 2290 switch (LowBits) { 2291 default: EVT = MVT::Other; break; 2292 case 1: EVT = MVT::i1; break; 2293 case 8: EVT = MVT::i8; break; 2294 case 16: EVT = MVT::i16; break; 2295 case 32: EVT = MVT::i32; break; 2296 } 2297 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT)) 2298 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), 2299 DAG.getValueType(EVT)); 2300 } 2301 2302 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2) 2303 if (N1C && N0.getOpcode() == ISD::SRA) { 2304 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2305 unsigned Sum = N1C->getValue() + C1->getValue(); 2306 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1; 2307 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), 2308 DAG.getConstant(Sum, N1C->getValueType(0))); 2309 } 2310 } 2311 2312 // Simplify, based on bits shifted out of the LHS. 2313 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 2314 return SDOperand(N, 0); 2315 2316 2317 // If the sign bit is known to be zero, switch this to a SRL. 2318 if (DAG.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT))) 2319 return DAG.getNode(ISD::SRL, VT, N0, N1); 2320 2321 return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDOperand(); 2322} 2323 2324SDOperand DAGCombiner::visitSRL(SDNode *N) { 2325 SDOperand N0 = N->getOperand(0); 2326 SDOperand N1 = N->getOperand(1); 2327 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2328 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2329 MVT::ValueType VT = N0.getValueType(); 2330 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 2331 2332 // fold (srl c1, c2) -> c1 >>u c2 2333 if (N0C && N1C) 2334 return DAG.getNode(ISD::SRL, VT, N0, N1); 2335 // fold (srl 0, x) -> 0 2336 if (N0C && N0C->isNullValue()) 2337 return N0; 2338 // fold (srl x, c >= size(x)) -> undef 2339 if (N1C && N1C->getValue() >= OpSizeInBits) 2340 return DAG.getNode(ISD::UNDEF, VT); 2341 // fold (srl x, 0) -> x 2342 if (N1C && N1C->isNullValue()) 2343 return N0; 2344 // if (srl x, c) is known to be zero, return 0 2345 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits))) 2346 return DAG.getConstant(0, VT); 2347 2348 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2) 2349 if (N1C && N0.getOpcode() == ISD::SRL && 2350 N0.getOperand(1).getOpcode() == ISD::Constant) { 2351 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2352 uint64_t c2 = N1C->getValue(); 2353 if (c1 + c2 > OpSizeInBits) 2354 return DAG.getConstant(0, VT); 2355 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 2356 DAG.getConstant(c1 + c2, N1.getValueType())); 2357 } 2358 2359 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 2360 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2361 // Shifting in all undef bits? 2362 MVT::ValueType SmallVT = N0.getOperand(0).getValueType(); 2363 if (N1C->getValue() >= MVT::getSizeInBits(SmallVT)) 2364 return DAG.getNode(ISD::UNDEF, VT); 2365 2366 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1); 2367 AddToWorkList(SmallShift.Val); 2368 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift); 2369 } 2370 2371 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 2372 // bit, which is unmodified by sra. 2373 if (N1C && N1C->getValue()+1 == MVT::getSizeInBits(VT)) { 2374 if (N0.getOpcode() == ISD::SRA) 2375 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1); 2376 } 2377 2378 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 2379 if (N1C && N0.getOpcode() == ISD::CTLZ && 2380 N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) { 2381 uint64_t KnownZero, KnownOne, Mask = MVT::getIntVTBitMask(VT); 2382 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 2383 2384 // If any of the input bits are KnownOne, then the input couldn't be all 2385 // zeros, thus the result of the srl will always be zero. 2386 if (KnownOne) return DAG.getConstant(0, VT); 2387 2388 // If all of the bits input the to ctlz node are known to be zero, then 2389 // the result of the ctlz is "32" and the result of the shift is one. 2390 uint64_t UnknownBits = ~KnownZero & Mask; 2391 if (UnknownBits == 0) return DAG.getConstant(1, VT); 2392 2393 // Otherwise, check to see if there is exactly one bit input to the ctlz. 2394 if ((UnknownBits & (UnknownBits-1)) == 0) { 2395 // Okay, we know that only that the single bit specified by UnknownBits 2396 // could be set on input to the CTLZ node. If this bit is set, the SRL 2397 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 2398 // to an SRL,XOR pair, which is likely to simplify more. 2399 unsigned ShAmt = CountTrailingZeros_64(UnknownBits); 2400 SDOperand Op = N0.getOperand(0); 2401 if (ShAmt) { 2402 Op = DAG.getNode(ISD::SRL, VT, Op, 2403 DAG.getConstant(ShAmt, TLI.getShiftAmountTy())); 2404 AddToWorkList(Op.Val); 2405 } 2406 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT)); 2407 } 2408 } 2409 2410 // fold operands of srl based on knowledge that the low bits are not 2411 // demanded. 2412 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 2413 return SDOperand(N, 0); 2414 2415 return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDOperand(); 2416} 2417 2418SDOperand DAGCombiner::visitCTLZ(SDNode *N) { 2419 SDOperand N0 = N->getOperand(0); 2420 MVT::ValueType VT = N->getValueType(0); 2421 2422 // fold (ctlz c1) -> c2 2423 if (isa<ConstantSDNode>(N0)) 2424 return DAG.getNode(ISD::CTLZ, VT, N0); 2425 return SDOperand(); 2426} 2427 2428SDOperand DAGCombiner::visitCTTZ(SDNode *N) { 2429 SDOperand N0 = N->getOperand(0); 2430 MVT::ValueType VT = N->getValueType(0); 2431 2432 // fold (cttz c1) -> c2 2433 if (isa<ConstantSDNode>(N0)) 2434 return DAG.getNode(ISD::CTTZ, VT, N0); 2435 return SDOperand(); 2436} 2437 2438SDOperand DAGCombiner::visitCTPOP(SDNode *N) { 2439 SDOperand N0 = N->getOperand(0); 2440 MVT::ValueType VT = N->getValueType(0); 2441 2442 // fold (ctpop c1) -> c2 2443 if (isa<ConstantSDNode>(N0)) 2444 return DAG.getNode(ISD::CTPOP, VT, N0); 2445 return SDOperand(); 2446} 2447 2448SDOperand DAGCombiner::visitSELECT(SDNode *N) { 2449 SDOperand N0 = N->getOperand(0); 2450 SDOperand N1 = N->getOperand(1); 2451 SDOperand N2 = N->getOperand(2); 2452 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2453 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2454 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 2455 MVT::ValueType VT = N->getValueType(0); 2456 MVT::ValueType VT0 = N0.getValueType(); 2457 2458 2459 // Some targets have SETCC types bigger than 1 bit, but do not set all the 2460 // bits to 1; identified by getSetCCResultContents. Watch out for these. 2461 2462 // fold select C, X, X -> X 2463 if (N1 == N2) 2464 return N1; 2465 // fold select true, X, Y -> X 2466 if (N0C && !N0C->isNullValue()) 2467 return N1; 2468 // fold select false, X, Y -> Y 2469 if (N0C && N0C->isNullValue()) 2470 return N2; 2471 // fold select C, 1, X -> C | X 2472 if (MVT::i1 == VT && N1C && N1C->getValue() == 1) 2473 return DAG.getNode(ISD::OR, VT, N0, N2); 2474 // fold select C, 0, 1 -> ~C 2475 if (MVT::isInteger(VT) && MVT::isInteger(VT0) && 2476 N1C && N2C && N1C->isNullValue() && N2C->getValue() == 1) { 2477 SDOperand XORNode = DAG.getNode(ISD::XOR, VT0, N0, DAG.getConstant(1, VT0)); 2478 if (VT == VT0) 2479 return XORNode; 2480 AddToWorkList(XORNode.Val); 2481 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(VT0)) 2482 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode); 2483 return DAG.getNode(ISD::TRUNCATE, VT, XORNode); 2484 } 2485 // fold select C, 0, X -> ~C & X 2486 if (VT == VT0 && N1C && N1C->isNullValue() && 2487 (N0.Val->getOpcode()!=ISD::SETCC || VT==MVT::i1 || 2488 TLI.getSetCCResultContents()== 2489 TargetLowering::ZeroOrNegativeOneSetCCResult)) { 2490 SDOperand XORNode; 2491 XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(~0UL, VT)); 2492 AddToWorkList(XORNode.Val); 2493 return DAG.getNode(ISD::AND, VT, XORNode, N2); 2494 } 2495 // fold select C, X, 1 -> ~C | X 2496 if (VT == VT0 && N2C && N2C->getValue() == 1 && 2497 (N0.Val->getOpcode()!=ISD::SETCC || VT==MVT::i1 || 2498 TLI.getSetCCResultContents()== 2499 TargetLowering::ZeroOrNegativeOneSetCCResult)) { 2500 SDOperand XORNode; 2501 XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(~0UL, VT)); 2502 AddToWorkList(XORNode.Val); 2503 return DAG.getNode(ISD::OR, VT, XORNode, N1); 2504 } 2505 // fold select C, X, 0 -> C & X 2506 // FIXME: this should check for C type == X type, not i1? 2507 if (MVT::i1 == VT && N2C && N2C->isNullValue()) 2508 return DAG.getNode(ISD::AND, VT, N0, N1); 2509 // fold X ? X : Y --> X ? 1 : Y --> X | Y 2510 if (MVT::i1 == VT && N0 == N1) 2511 return DAG.getNode(ISD::OR, VT, N0, N2); 2512 // fold X ? Y : X --> X ? Y : 0 --> X & Y 2513 if (MVT::i1 == VT && N0 == N2) 2514 return DAG.getNode(ISD::AND, VT, N0, N1); 2515 2516 // If we can fold this based on the true/false value, do so. 2517 if (SimplifySelectOps(N, N1, N2)) 2518 return SDOperand(N, 0); // Don't revisit N. 2519 2520 // fold selects based on a setcc into other things, such as min/max/abs 2521 if (N0.getOpcode() == ISD::SETCC) 2522 // FIXME: 2523 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 2524 // having to say they don't support SELECT_CC on every type the DAG knows 2525 // about, since there is no way to mark an opcode illegal at all value types 2526 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other)) 2527 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1), 2528 N1, N2, N0.getOperand(2)); 2529 else 2530 return SimplifySelect(N0, N1, N2); 2531 return SDOperand(); 2532} 2533 2534SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) { 2535 SDOperand N0 = N->getOperand(0); 2536 SDOperand N1 = N->getOperand(1); 2537 SDOperand N2 = N->getOperand(2); 2538 SDOperand N3 = N->getOperand(3); 2539 SDOperand N4 = N->getOperand(4); 2540 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 2541 2542 // fold select_cc lhs, rhs, x, x, cc -> x 2543 if (N2 == N3) 2544 return N2; 2545 2546 // Determine if the condition we're dealing with is constant 2547 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 2548 if (SCC.Val) AddToWorkList(SCC.Val); 2549 2550 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) { 2551 if (SCCC->getValue()) 2552 return N2; // cond always true -> true val 2553 else 2554 return N3; // cond always false -> false val 2555 } 2556 2557 // Fold to a simpler select_cc 2558 if (SCC.Val && SCC.getOpcode() == ISD::SETCC) 2559 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(), 2560 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 2561 SCC.getOperand(2)); 2562 2563 // If we can fold this based on the true/false value, do so. 2564 if (SimplifySelectOps(N, N2, N3)) 2565 return SDOperand(N, 0); // Don't revisit N. 2566 2567 // fold select_cc into other things, such as min/max/abs 2568 return SimplifySelectCC(N0, N1, N2, N3, CC); 2569} 2570 2571SDOperand DAGCombiner::visitSETCC(SDNode *N) { 2572 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 2573 cast<CondCodeSDNode>(N->getOperand(2))->get()); 2574} 2575 2576// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 2577// "fold ({s|z}ext (load x)) -> ({s|z}ext (truncate ({s|z}extload x)))" 2578// transformation. Returns true if extension are possible and the above 2579// mentioned transformation is profitable. 2580static bool ExtendUsesToFormExtLoad(SDNode *N, SDOperand N0, 2581 unsigned ExtOpc, 2582 SmallVector<SDNode*, 4> &ExtendNodes, 2583 TargetLowering &TLI) { 2584 bool HasCopyToRegUses = false; 2585 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 2586 for (SDNode::use_iterator UI = N0.Val->use_begin(), UE = N0.Val->use_end(); 2587 UI != UE; ++UI) { 2588 SDNode *User = *UI; 2589 if (User == N) 2590 continue; 2591 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 2592 if (User->getOpcode() == ISD::SETCC) { 2593 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 2594 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 2595 // Sign bits will be lost after a zext. 2596 return false; 2597 bool Add = false; 2598 for (unsigned i = 0; i != 2; ++i) { 2599 SDOperand UseOp = User->getOperand(i); 2600 if (UseOp == N0) 2601 continue; 2602 if (!isa<ConstantSDNode>(UseOp)) 2603 return false; 2604 Add = true; 2605 } 2606 if (Add) 2607 ExtendNodes.push_back(User); 2608 } else { 2609 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2610 SDOperand UseOp = User->getOperand(i); 2611 if (UseOp == N0) { 2612 // If truncate from extended type to original load type is free 2613 // on this target, then it's ok to extend a CopyToReg. 2614 if (isTruncFree && User->getOpcode() == ISD::CopyToReg) 2615 HasCopyToRegUses = true; 2616 else 2617 return false; 2618 } 2619 } 2620 } 2621 } 2622 2623 if (HasCopyToRegUses) { 2624 bool BothLiveOut = false; 2625 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 2626 UI != UE; ++UI) { 2627 SDNode *User = *UI; 2628 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2629 SDOperand UseOp = User->getOperand(i); 2630 if (UseOp.Val == N && UseOp.ResNo == 0) { 2631 BothLiveOut = true; 2632 break; 2633 } 2634 } 2635 } 2636 if (BothLiveOut) 2637 // Both unextended and extended values are live out. There had better be 2638 // good a reason for the transformation. 2639 return ExtendNodes.size(); 2640 } 2641 return true; 2642} 2643 2644SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 2645 SDOperand N0 = N->getOperand(0); 2646 MVT::ValueType VT = N->getValueType(0); 2647 2648 // fold (sext c1) -> c1 2649 if (isa<ConstantSDNode>(N0)) 2650 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0); 2651 2652 // fold (sext (sext x)) -> (sext x) 2653 // fold (sext (aext x)) -> (sext x) 2654 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2655 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0)); 2656 2657 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 2658 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 2659 if (N0.getOpcode() == ISD::TRUNCATE) { 2660 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2661 if (NarrowLoad.Val) { 2662 if (NarrowLoad.Val != N0.Val) 2663 CombineTo(N0.Val, NarrowLoad); 2664 return DAG.getNode(ISD::SIGN_EXTEND, VT, NarrowLoad); 2665 } 2666 } 2667 2668 // See if the value being truncated is already sign extended. If so, just 2669 // eliminate the trunc/sext pair. 2670 if (N0.getOpcode() == ISD::TRUNCATE) { 2671 SDOperand Op = N0.getOperand(0); 2672 unsigned OpBits = MVT::getSizeInBits(Op.getValueType()); 2673 unsigned MidBits = MVT::getSizeInBits(N0.getValueType()); 2674 unsigned DestBits = MVT::getSizeInBits(VT); 2675 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 2676 2677 if (OpBits == DestBits) { 2678 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 2679 // bits, it is already ready. 2680 if (NumSignBits > DestBits-MidBits) 2681 return Op; 2682 } else if (OpBits < DestBits) { 2683 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 2684 // bits, just sext from i32. 2685 if (NumSignBits > OpBits-MidBits) 2686 return DAG.getNode(ISD::SIGN_EXTEND, VT, Op); 2687 } else { 2688 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 2689 // bits, just truncate to i32. 2690 if (NumSignBits > OpBits-MidBits) 2691 return DAG.getNode(ISD::TRUNCATE, VT, Op); 2692 } 2693 2694 // fold (sext (truncate x)) -> (sextinreg x). 2695 if (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 2696 N0.getValueType())) { 2697 if (Op.getValueType() < VT) 2698 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2699 else if (Op.getValueType() > VT) 2700 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2701 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op, 2702 DAG.getValueType(N0.getValueType())); 2703 } 2704 } 2705 2706 // fold (sext (load x)) -> (sext (truncate (sextload x))) 2707 if (ISD::isNON_EXTLoad(N0.Val) && 2708 (!AfterLegalize||TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType()))){ 2709 bool DoXform = true; 2710 SmallVector<SDNode*, 4> SetCCs; 2711 if (!N0.hasOneUse()) 2712 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 2713 if (DoXform) { 2714 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2715 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2716 LN0->getBasePtr(), LN0->getSrcValue(), 2717 LN0->getSrcValueOffset(), 2718 N0.getValueType(), 2719 LN0->isVolatile(), 2720 LN0->getAlignment()); 2721 CombineTo(N, ExtLoad); 2722 SDOperand Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad); 2723 CombineTo(N0.Val, Trunc, ExtLoad.getValue(1)); 2724 // Extend SetCC uses if necessary. 2725 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 2726 SDNode *SetCC = SetCCs[i]; 2727 SmallVector<SDOperand, 4> Ops; 2728 for (unsigned j = 0; j != 2; ++j) { 2729 SDOperand SOp = SetCC->getOperand(j); 2730 if (SOp == Trunc) 2731 Ops.push_back(ExtLoad); 2732 else 2733 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, VT, SOp)); 2734 } 2735 Ops.push_back(SetCC->getOperand(2)); 2736 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0), 2737 &Ops[0], Ops.size())); 2738 } 2739 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2740 } 2741 } 2742 2743 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 2744 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 2745 if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && 2746 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) { 2747 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2748 MVT::ValueType EVT = LN0->getLoadedVT(); 2749 if (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) { 2750 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2751 LN0->getBasePtr(), LN0->getSrcValue(), 2752 LN0->getSrcValueOffset(), EVT, 2753 LN0->isVolatile(), 2754 LN0->getAlignment()); 2755 CombineTo(N, ExtLoad); 2756 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2757 ExtLoad.getValue(1)); 2758 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2759 } 2760 } 2761 2762 // sext(setcc x,y,cc) -> select_cc x, y, -1, 0, cc 2763 if (N0.getOpcode() == ISD::SETCC) { 2764 SDOperand SCC = 2765 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 2766 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT), 2767 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 2768 if (SCC.Val) return SCC; 2769 } 2770 2771 return SDOperand(); 2772} 2773 2774SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) { 2775 SDOperand N0 = N->getOperand(0); 2776 MVT::ValueType VT = N->getValueType(0); 2777 2778 // fold (zext c1) -> c1 2779 if (isa<ConstantSDNode>(N0)) 2780 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 2781 // fold (zext (zext x)) -> (zext x) 2782 // fold (zext (aext x)) -> (zext x) 2783 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2784 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0)); 2785 2786 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 2787 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 2788 if (N0.getOpcode() == ISD::TRUNCATE) { 2789 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2790 if (NarrowLoad.Val) { 2791 if (NarrowLoad.Val != N0.Val) 2792 CombineTo(N0.Val, NarrowLoad); 2793 return DAG.getNode(ISD::ZERO_EXTEND, VT, NarrowLoad); 2794 } 2795 } 2796 2797 // fold (zext (truncate x)) -> (and x, mask) 2798 if (N0.getOpcode() == ISD::TRUNCATE && 2799 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) { 2800 SDOperand Op = N0.getOperand(0); 2801 if (Op.getValueType() < VT) { 2802 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2803 } else if (Op.getValueType() > VT) { 2804 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2805 } 2806 return DAG.getZeroExtendInReg(Op, N0.getValueType()); 2807 } 2808 2809 // fold (zext (and (trunc x), cst)) -> (and x, cst). 2810 if (N0.getOpcode() == ISD::AND && 2811 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 2812 N0.getOperand(1).getOpcode() == ISD::Constant) { 2813 SDOperand X = N0.getOperand(0).getOperand(0); 2814 if (X.getValueType() < VT) { 2815 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 2816 } else if (X.getValueType() > VT) { 2817 X = DAG.getNode(ISD::TRUNCATE, VT, X); 2818 } 2819 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2820 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 2821 } 2822 2823 // fold (zext (load x)) -> (zext (truncate (zextload x))) 2824 if (ISD::isNON_EXTLoad(N0.Val) && 2825 (!AfterLegalize||TLI.isLoadXLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 2826 bool DoXform = true; 2827 SmallVector<SDNode*, 4> SetCCs; 2828 if (!N0.hasOneUse()) 2829 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 2830 if (DoXform) { 2831 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2832 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 2833 LN0->getBasePtr(), LN0->getSrcValue(), 2834 LN0->getSrcValueOffset(), 2835 N0.getValueType(), 2836 LN0->isVolatile(), 2837 LN0->getAlignment()); 2838 CombineTo(N, ExtLoad); 2839 SDOperand Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad); 2840 CombineTo(N0.Val, Trunc, ExtLoad.getValue(1)); 2841 // Extend SetCC uses if necessary. 2842 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 2843 SDNode *SetCC = SetCCs[i]; 2844 SmallVector<SDOperand, 4> Ops; 2845 for (unsigned j = 0; j != 2; ++j) { 2846 SDOperand SOp = SetCC->getOperand(j); 2847 if (SOp == Trunc) 2848 Ops.push_back(ExtLoad); 2849 else 2850 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, VT, SOp)); 2851 } 2852 Ops.push_back(SetCC->getOperand(2)); 2853 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0), 2854 &Ops[0], Ops.size())); 2855 } 2856 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2857 } 2858 } 2859 2860 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 2861 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 2862 if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && 2863 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) { 2864 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2865 MVT::ValueType EVT = LN0->getLoadedVT(); 2866 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 2867 LN0->getBasePtr(), LN0->getSrcValue(), 2868 LN0->getSrcValueOffset(), EVT, 2869 LN0->isVolatile(), 2870 LN0->getAlignment()); 2871 CombineTo(N, ExtLoad); 2872 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2873 ExtLoad.getValue(1)); 2874 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2875 } 2876 2877 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 2878 if (N0.getOpcode() == ISD::SETCC) { 2879 SDOperand SCC = 2880 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 2881 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 2882 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 2883 if (SCC.Val) return SCC; 2884 } 2885 2886 return SDOperand(); 2887} 2888 2889SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) { 2890 SDOperand N0 = N->getOperand(0); 2891 MVT::ValueType VT = N->getValueType(0); 2892 2893 // fold (aext c1) -> c1 2894 if (isa<ConstantSDNode>(N0)) 2895 return DAG.getNode(ISD::ANY_EXTEND, VT, N0); 2896 // fold (aext (aext x)) -> (aext x) 2897 // fold (aext (zext x)) -> (zext x) 2898 // fold (aext (sext x)) -> (sext x) 2899 if (N0.getOpcode() == ISD::ANY_EXTEND || 2900 N0.getOpcode() == ISD::ZERO_EXTEND || 2901 N0.getOpcode() == ISD::SIGN_EXTEND) 2902 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 2903 2904 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 2905 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 2906 if (N0.getOpcode() == ISD::TRUNCATE) { 2907 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2908 if (NarrowLoad.Val) { 2909 if (NarrowLoad.Val != N0.Val) 2910 CombineTo(N0.Val, NarrowLoad); 2911 return DAG.getNode(ISD::ANY_EXTEND, VT, NarrowLoad); 2912 } 2913 } 2914 2915 // fold (aext (truncate x)) 2916 if (N0.getOpcode() == ISD::TRUNCATE) { 2917 SDOperand TruncOp = N0.getOperand(0); 2918 if (TruncOp.getValueType() == VT) 2919 return TruncOp; // x iff x size == zext size. 2920 if (TruncOp.getValueType() > VT) 2921 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp); 2922 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp); 2923 } 2924 2925 // fold (aext (and (trunc x), cst)) -> (and x, cst). 2926 if (N0.getOpcode() == ISD::AND && 2927 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 2928 N0.getOperand(1).getOpcode() == ISD::Constant) { 2929 SDOperand X = N0.getOperand(0).getOperand(0); 2930 if (X.getValueType() < VT) { 2931 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 2932 } else if (X.getValueType() > VT) { 2933 X = DAG.getNode(ISD::TRUNCATE, VT, X); 2934 } 2935 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2936 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 2937 } 2938 2939 // fold (aext (load x)) -> (aext (truncate (extload x))) 2940 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2941 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) { 2942 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2943 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 2944 LN0->getBasePtr(), LN0->getSrcValue(), 2945 LN0->getSrcValueOffset(), 2946 N0.getValueType(), 2947 LN0->isVolatile(), 2948 LN0->getAlignment()); 2949 CombineTo(N, ExtLoad); 2950 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2951 ExtLoad.getValue(1)); 2952 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2953 } 2954 2955 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 2956 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 2957 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 2958 if (N0.getOpcode() == ISD::LOAD && 2959 !ISD::isNON_EXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 2960 N0.hasOneUse()) { 2961 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2962 MVT::ValueType EVT = LN0->getLoadedVT(); 2963 SDOperand ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT, 2964 LN0->getChain(), LN0->getBasePtr(), 2965 LN0->getSrcValue(), 2966 LN0->getSrcValueOffset(), EVT, 2967 LN0->isVolatile(), 2968 LN0->getAlignment()); 2969 CombineTo(N, ExtLoad); 2970 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2971 ExtLoad.getValue(1)); 2972 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2973 } 2974 2975 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 2976 if (N0.getOpcode() == ISD::SETCC) { 2977 SDOperand SCC = 2978 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 2979 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 2980 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 2981 if (SCC.Val) 2982 return SCC; 2983 } 2984 2985 return SDOperand(); 2986} 2987 2988/// GetDemandedBits - See if the specified operand can be simplified with the 2989/// knowledge that only the bits specified by Mask are used. If so, return the 2990/// simpler operand, otherwise return a null SDOperand. 2991SDOperand DAGCombiner::GetDemandedBits(SDOperand V, uint64_t Mask) { 2992 switch (V.getOpcode()) { 2993 default: break; 2994 case ISD::OR: 2995 case ISD::XOR: 2996 // If the LHS or RHS don't contribute bits to the or, drop them. 2997 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 2998 return V.getOperand(1); 2999 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 3000 return V.getOperand(0); 3001 break; 3002 case ISD::SRL: 3003 // Only look at single-use SRLs. 3004 if (!V.Val->hasOneUse()) 3005 break; 3006 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 3007 // See if we can recursively simplify the LHS. 3008 unsigned Amt = RHSC->getValue(); 3009 Mask = (Mask << Amt) & MVT::getIntVTBitMask(V.getValueType()); 3010 SDOperand SimplifyLHS = GetDemandedBits(V.getOperand(0), Mask); 3011 if (SimplifyLHS.Val) { 3012 return DAG.getNode(ISD::SRL, V.getValueType(), 3013 SimplifyLHS, V.getOperand(1)); 3014 } 3015 } 3016 } 3017 return SDOperand(); 3018} 3019 3020/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 3021/// bits and then truncated to a narrower type and where N is a multiple 3022/// of number of bits of the narrower type, transform it to a narrower load 3023/// from address + N / num of bits of new type. If the result is to be 3024/// extended, also fold the extension to form a extending load. 3025SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) { 3026 unsigned Opc = N->getOpcode(); 3027 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 3028 SDOperand N0 = N->getOperand(0); 3029 MVT::ValueType VT = N->getValueType(0); 3030 MVT::ValueType EVT = N->getValueType(0); 3031 3032 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then 3033 // extended to VT. 3034 if (Opc == ISD::SIGN_EXTEND_INREG) { 3035 ExtType = ISD::SEXTLOAD; 3036 EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3037 if (AfterLegalize && !TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) 3038 return SDOperand(); 3039 } 3040 3041 unsigned EVTBits = MVT::getSizeInBits(EVT); 3042 unsigned ShAmt = 0; 3043 bool CombineSRL = false; 3044 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 3045 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3046 ShAmt = N01->getValue(); 3047 // Is the shift amount a multiple of size of VT? 3048 if ((ShAmt & (EVTBits-1)) == 0) { 3049 N0 = N0.getOperand(0); 3050 if (MVT::getSizeInBits(N0.getValueType()) <= EVTBits) 3051 return SDOperand(); 3052 CombineSRL = true; 3053 } 3054 } 3055 } 3056 3057 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 3058 // Do not allow folding to i1 here. i1 is implicitly stored in memory in 3059 // zero extended form: by shrinking the load, we lose track of the fact 3060 // that it is already zero extended. 3061 // FIXME: This should be reevaluated. 3062 VT != MVT::i1) { 3063 assert(MVT::getSizeInBits(N0.getValueType()) > EVTBits && 3064 "Cannot truncate to larger type!"); 3065 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3066 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 3067 // For big endian targets, we need to adjust the offset to the pointer to 3068 // load the correct bytes. 3069 if (!TLI.isLittleEndian()) { 3070 unsigned LVTStoreBits = MVT::getStoreSizeInBits(N0.getValueType()); 3071 unsigned EVTStoreBits = MVT::getStoreSizeInBits(EVT); 3072 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 3073 } 3074 uint64_t PtrOff = ShAmt / 8; 3075 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 3076 SDOperand NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(), 3077 DAG.getConstant(PtrOff, PtrType)); 3078 AddToWorkList(NewPtr.Val); 3079 SDOperand Load = (ExtType == ISD::NON_EXTLOAD) 3080 ? DAG.getLoad(VT, LN0->getChain(), NewPtr, 3081 LN0->getSrcValue(), LN0->getSrcValueOffset(), 3082 LN0->isVolatile(), NewAlign) 3083 : DAG.getExtLoad(ExtType, VT, LN0->getChain(), NewPtr, 3084 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT, 3085 LN0->isVolatile(), NewAlign); 3086 AddToWorkList(N); 3087 if (CombineSRL) { 3088 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1)); 3089 CombineTo(N->getOperand(0).Val, Load); 3090 } else 3091 CombineTo(N0.Val, Load, Load.getValue(1)); 3092 if (ShAmt) { 3093 if (Opc == ISD::SIGN_EXTEND_INREG) 3094 return DAG.getNode(Opc, VT, Load, N->getOperand(1)); 3095 else 3096 return DAG.getNode(Opc, VT, Load); 3097 } 3098 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3099 } 3100 3101 return SDOperand(); 3102} 3103 3104 3105SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 3106 SDOperand N0 = N->getOperand(0); 3107 SDOperand N1 = N->getOperand(1); 3108 MVT::ValueType VT = N->getValueType(0); 3109 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT(); 3110 unsigned EVTBits = MVT::getSizeInBits(EVT); 3111 3112 // fold (sext_in_reg c1) -> c1 3113 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 3114 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1); 3115 3116 // If the input is already sign extended, just drop the extension. 3117 if (DAG.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1) 3118 return N0; 3119 3120 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 3121 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 3122 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) { 3123 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); 3124 } 3125 3126 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 3127 if (DAG.MaskedValueIsZero(N0, 1ULL << (EVTBits-1))) 3128 return DAG.getZeroExtendInReg(N0, EVT); 3129 3130 // fold operands of sext_in_reg based on knowledge that the top bits are not 3131 // demanded. 3132 if (SimplifyDemandedBits(SDOperand(N, 0))) 3133 return SDOperand(N, 0); 3134 3135 // fold (sext_in_reg (load x)) -> (smaller sextload x) 3136 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 3137 SDOperand NarrowLoad = ReduceLoadWidth(N); 3138 if (NarrowLoad.Val) 3139 return NarrowLoad; 3140 3141 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24 3142 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible. 3143 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 3144 if (N0.getOpcode() == ISD::SRL) { 3145 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 3146 if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) { 3147 // We can turn this into an SRA iff the input to the SRL is already sign 3148 // extended enough. 3149 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 3150 if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits) 3151 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1)); 3152 } 3153 } 3154 3155 // fold (sext_inreg (extload x)) -> (sextload x) 3156 if (ISD::isEXTLoad(N0.Val) && 3157 ISD::isUNINDEXEDLoad(N0.Val) && 3158 EVT == cast<LoadSDNode>(N0)->getLoadedVT() && 3159 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) { 3160 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3161 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 3162 LN0->getBasePtr(), LN0->getSrcValue(), 3163 LN0->getSrcValueOffset(), EVT, 3164 LN0->isVolatile(), 3165 LN0->getAlignment()); 3166 CombineTo(N, ExtLoad); 3167 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 3168 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3169 } 3170 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 3171 if (ISD::isZEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 3172 N0.hasOneUse() && 3173 EVT == cast<LoadSDNode>(N0)->getLoadedVT() && 3174 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) { 3175 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3176 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 3177 LN0->getBasePtr(), LN0->getSrcValue(), 3178 LN0->getSrcValueOffset(), EVT, 3179 LN0->isVolatile(), 3180 LN0->getAlignment()); 3181 CombineTo(N, ExtLoad); 3182 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 3183 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3184 } 3185 return SDOperand(); 3186} 3187 3188SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) { 3189 SDOperand N0 = N->getOperand(0); 3190 MVT::ValueType VT = N->getValueType(0); 3191 3192 // noop truncate 3193 if (N0.getValueType() == N->getValueType(0)) 3194 return N0; 3195 // fold (truncate c1) -> c1 3196 if (isa<ConstantSDNode>(N0)) 3197 return DAG.getNode(ISD::TRUNCATE, VT, N0); 3198 // fold (truncate (truncate x)) -> (truncate x) 3199 if (N0.getOpcode() == ISD::TRUNCATE) 3200 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 3201 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 3202 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| 3203 N0.getOpcode() == ISD::ANY_EXTEND) { 3204 if (N0.getOperand(0).getValueType() < VT) 3205 // if the source is smaller than the dest, we still need an extend 3206 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 3207 else if (N0.getOperand(0).getValueType() > VT) 3208 // if the source is larger than the dest, than we just need the truncate 3209 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 3210 else 3211 // if the source and dest are the same type, we can drop both the extend 3212 // and the truncate 3213 return N0.getOperand(0); 3214 } 3215 3216 // See if we can simplify the input to this truncate through knowledge that 3217 // only the low bits are being used. For example "trunc (or (shl x, 8), y)" 3218 // -> trunc y 3219 SDOperand Shorter = GetDemandedBits(N0, MVT::getIntVTBitMask(VT)); 3220 if (Shorter.Val) 3221 return DAG.getNode(ISD::TRUNCATE, VT, Shorter); 3222 3223 // fold (truncate (load x)) -> (smaller load x) 3224 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 3225 return ReduceLoadWidth(N); 3226} 3227 3228SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) { 3229 SDOperand N0 = N->getOperand(0); 3230 MVT::ValueType VT = N->getValueType(0); 3231 3232 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 3233 // Only do this before legalize, since afterward the target may be depending 3234 // on the bitconvert. 3235 // First check to see if this is all constant. 3236 if (!AfterLegalize && 3237 N0.getOpcode() == ISD::BUILD_VECTOR && N0.Val->hasOneUse() && 3238 MVT::isVector(VT)) { 3239 bool isSimple = true; 3240 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 3241 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 3242 N0.getOperand(i).getOpcode() != ISD::Constant && 3243 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 3244 isSimple = false; 3245 break; 3246 } 3247 3248 MVT::ValueType DestEltVT = MVT::getVectorElementType(N->getValueType(0)); 3249 assert(!MVT::isVector(DestEltVT) && 3250 "Element type of vector ValueType must not be vector!"); 3251 if (isSimple) { 3252 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.Val, DestEltVT); 3253 } 3254 } 3255 3256 // If the input is a constant, let getNode() fold it. 3257 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 3258 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0); 3259 if (Res.Val != N) return Res; 3260 } 3261 3262 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2) 3263 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3264 3265 // fold (conv (load x)) -> (load (conv*)x) 3266 // If the resultant load doesn't need a higher alignment than the original! 3267 if (ISD::isNormalLoad(N0.Val) && N0.hasOneUse() && 3268 TLI.isOperationLegal(ISD::LOAD, VT)) { 3269 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3270 unsigned Align = TLI.getTargetMachine().getTargetData()-> 3271 getABITypeAlignment(MVT::getTypeForValueType(VT)); 3272 unsigned OrigAlign = LN0->getAlignment(); 3273 if (Align <= OrigAlign) { 3274 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(), 3275 LN0->getSrcValue(), LN0->getSrcValueOffset(), 3276 LN0->isVolatile(), Align); 3277 AddToWorkList(N); 3278 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load), 3279 Load.getValue(1)); 3280 return Load; 3281 } 3282 } 3283 3284 return SDOperand(); 3285} 3286 3287/// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector 3288/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 3289/// destination element value type. 3290SDOperand DAGCombiner:: 3291ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) { 3292 MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType(); 3293 3294 // If this is already the right type, we're done. 3295 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0); 3296 3297 unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT); 3298 unsigned DstBitSize = MVT::getSizeInBits(DstEltVT); 3299 3300 // If this is a conversion of N elements of one type to N elements of another 3301 // type, convert each element. This handles FP<->INT cases. 3302 if (SrcBitSize == DstBitSize) { 3303 SmallVector<SDOperand, 8> Ops; 3304 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3305 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i))); 3306 AddToWorkList(Ops.back().Val); 3307 } 3308 MVT::ValueType VT = 3309 MVT::getVectorType(DstEltVT, 3310 MVT::getVectorNumElements(BV->getValueType(0))); 3311 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3312 } 3313 3314 // Otherwise, we're growing or shrinking the elements. To avoid having to 3315 // handle annoying details of growing/shrinking FP values, we convert them to 3316 // int first. 3317 if (MVT::isFloatingPoint(SrcEltVT)) { 3318 // Convert the input float vector to a int vector where the elements are the 3319 // same sizes. 3320 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 3321 MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 3322 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).Val; 3323 SrcEltVT = IntVT; 3324 } 3325 3326 // Now we know the input is an integer vector. If the output is a FP type, 3327 // convert to integer first, then to FP of the right size. 3328 if (MVT::isFloatingPoint(DstEltVT)) { 3329 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 3330 MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 3331 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).Val; 3332 3333 // Next, convert to FP elements of the same size. 3334 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT); 3335 } 3336 3337 // Okay, we know the src/dst types are both integers of differing types. 3338 // Handling growing first. 3339 assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT)); 3340 if (SrcBitSize < DstBitSize) { 3341 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 3342 3343 SmallVector<SDOperand, 8> Ops; 3344 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 3345 i += NumInputsPerOutput) { 3346 bool isLE = TLI.isLittleEndian(); 3347 uint64_t NewBits = 0; 3348 bool EltIsUndef = true; 3349 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 3350 // Shift the previously computed bits over. 3351 NewBits <<= SrcBitSize; 3352 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 3353 if (Op.getOpcode() == ISD::UNDEF) continue; 3354 EltIsUndef = false; 3355 3356 NewBits |= cast<ConstantSDNode>(Op)->getValue(); 3357 } 3358 3359 if (EltIsUndef) 3360 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 3361 else 3362 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 3363 } 3364 3365 MVT::ValueType VT = MVT::getVectorType(DstEltVT, 3366 Ops.size()); 3367 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3368 } 3369 3370 // Finally, this must be the case where we are shrinking elements: each input 3371 // turns into multiple outputs. 3372 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 3373 SmallVector<SDOperand, 8> Ops; 3374 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3375 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 3376 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 3377 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 3378 continue; 3379 } 3380 uint64_t OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getValue(); 3381 3382 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 3383 unsigned ThisVal = OpVal & ((1ULL << DstBitSize)-1); 3384 OpVal >>= DstBitSize; 3385 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 3386 } 3387 3388 // For big endian targets, swap the order of the pieces of each element. 3389 if (!TLI.isLittleEndian()) 3390 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 3391 } 3392 MVT::ValueType VT = MVT::getVectorType(DstEltVT, Ops.size()); 3393 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3394} 3395 3396 3397 3398SDOperand DAGCombiner::visitFADD(SDNode *N) { 3399 SDOperand N0 = N->getOperand(0); 3400 SDOperand N1 = N->getOperand(1); 3401 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3402 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3403 MVT::ValueType VT = N->getValueType(0); 3404 3405 // fold vector ops 3406 if (MVT::isVector(VT)) { 3407 SDOperand FoldedVOp = SimplifyVBinOp(N); 3408 if (FoldedVOp.Val) return FoldedVOp; 3409 } 3410 3411 // fold (fadd c1, c2) -> c1+c2 3412 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3413 return DAG.getNode(ISD::FADD, VT, N0, N1); 3414 // canonicalize constant to RHS 3415 if (N0CFP && !N1CFP) 3416 return DAG.getNode(ISD::FADD, VT, N1, N0); 3417 // fold (A + (-B)) -> A-B 3418 if (isNegatibleForFree(N1) == 2) 3419 return DAG.getNode(ISD::FSUB, VT, N0, GetNegatedExpression(N1, DAG)); 3420 // fold ((-A) + B) -> B-A 3421 if (isNegatibleForFree(N0) == 2) 3422 return DAG.getNode(ISD::FSUB, VT, N1, GetNegatedExpression(N0, DAG)); 3423 3424 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 3425 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 3426 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3427 return DAG.getNode(ISD::FADD, VT, N0.getOperand(0), 3428 DAG.getNode(ISD::FADD, VT, N0.getOperand(1), N1)); 3429 3430 return SDOperand(); 3431} 3432 3433SDOperand DAGCombiner::visitFSUB(SDNode *N) { 3434 SDOperand N0 = N->getOperand(0); 3435 SDOperand N1 = N->getOperand(1); 3436 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3437 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3438 MVT::ValueType VT = N->getValueType(0); 3439 3440 // fold vector ops 3441 if (MVT::isVector(VT)) { 3442 SDOperand FoldedVOp = SimplifyVBinOp(N); 3443 if (FoldedVOp.Val) return FoldedVOp; 3444 } 3445 3446 // fold (fsub c1, c2) -> c1-c2 3447 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3448 return DAG.getNode(ISD::FSUB, VT, N0, N1); 3449 // fold (0-B) -> -B 3450 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { 3451 if (isNegatibleForFree(N1)) 3452 return GetNegatedExpression(N1, DAG); 3453 return DAG.getNode(ISD::FNEG, VT, N1); 3454 } 3455 // fold (A-(-B)) -> A+B 3456 if (isNegatibleForFree(N1)) 3457 return DAG.getNode(ISD::FADD, VT, N0, GetNegatedExpression(N1, DAG)); 3458 3459 return SDOperand(); 3460} 3461 3462SDOperand DAGCombiner::visitFMUL(SDNode *N) { 3463 SDOperand N0 = N->getOperand(0); 3464 SDOperand N1 = N->getOperand(1); 3465 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3466 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3467 MVT::ValueType VT = N->getValueType(0); 3468 3469 // fold vector ops 3470 if (MVT::isVector(VT)) { 3471 SDOperand FoldedVOp = SimplifyVBinOp(N); 3472 if (FoldedVOp.Val) return FoldedVOp; 3473 } 3474 3475 // fold (fmul c1, c2) -> c1*c2 3476 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3477 return DAG.getNode(ISD::FMUL, VT, N0, N1); 3478 // canonicalize constant to RHS 3479 if (N0CFP && !N1CFP) 3480 return DAG.getNode(ISD::FMUL, VT, N1, N0); 3481 // fold (fmul X, 2.0) -> (fadd X, X) 3482 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 3483 return DAG.getNode(ISD::FADD, VT, N0, N0); 3484 // fold (fmul X, -1.0) -> (fneg X) 3485 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 3486 return DAG.getNode(ISD::FNEG, VT, N0); 3487 3488 // -X * -Y -> X*Y 3489 if (char LHSNeg = isNegatibleForFree(N0)) { 3490 if (char RHSNeg = isNegatibleForFree(N1)) { 3491 // Both can be negated for free, check to see if at least one is cheaper 3492 // negated. 3493 if (LHSNeg == 2 || RHSNeg == 2) 3494 return DAG.getNode(ISD::FMUL, VT, GetNegatedExpression(N0, DAG), 3495 GetNegatedExpression(N1, DAG)); 3496 } 3497 } 3498 3499 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 3500 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 3501 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3502 return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0), 3503 DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1)); 3504 3505 return SDOperand(); 3506} 3507 3508SDOperand DAGCombiner::visitFDIV(SDNode *N) { 3509 SDOperand N0 = N->getOperand(0); 3510 SDOperand N1 = N->getOperand(1); 3511 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3512 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3513 MVT::ValueType VT = N->getValueType(0); 3514 3515 // fold vector ops 3516 if (MVT::isVector(VT)) { 3517 SDOperand FoldedVOp = SimplifyVBinOp(N); 3518 if (FoldedVOp.Val) return FoldedVOp; 3519 } 3520 3521 // fold (fdiv c1, c2) -> c1/c2 3522 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3523 return DAG.getNode(ISD::FDIV, VT, N0, N1); 3524 3525 3526 // -X / -Y -> X*Y 3527 if (char LHSNeg = isNegatibleForFree(N0)) { 3528 if (char RHSNeg = isNegatibleForFree(N1)) { 3529 // Both can be negated for free, check to see if at least one is cheaper 3530 // negated. 3531 if (LHSNeg == 2 || RHSNeg == 2) 3532 return DAG.getNode(ISD::FDIV, VT, GetNegatedExpression(N0, DAG), 3533 GetNegatedExpression(N1, DAG)); 3534 } 3535 } 3536 3537 return SDOperand(); 3538} 3539 3540SDOperand DAGCombiner::visitFREM(SDNode *N) { 3541 SDOperand N0 = N->getOperand(0); 3542 SDOperand N1 = N->getOperand(1); 3543 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3544 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3545 MVT::ValueType VT = N->getValueType(0); 3546 3547 // fold (frem c1, c2) -> fmod(c1,c2) 3548 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3549 return DAG.getNode(ISD::FREM, VT, N0, N1); 3550 3551 return SDOperand(); 3552} 3553 3554SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) { 3555 SDOperand N0 = N->getOperand(0); 3556 SDOperand N1 = N->getOperand(1); 3557 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3558 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3559 MVT::ValueType VT = N->getValueType(0); 3560 3561 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 3562 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1); 3563 3564 if (N1CFP) { 3565 const APFloat& V = N1CFP->getValueAPF(); 3566 // copysign(x, c1) -> fabs(x) iff ispos(c1) 3567 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 3568 if (!V.isNegative()) 3569 return DAG.getNode(ISD::FABS, VT, N0); 3570 else 3571 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0)); 3572 } 3573 3574 // copysign(fabs(x), y) -> copysign(x, y) 3575 // copysign(fneg(x), y) -> copysign(x, y) 3576 // copysign(copysign(x,z), y) -> copysign(x, y) 3577 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 3578 N0.getOpcode() == ISD::FCOPYSIGN) 3579 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1); 3580 3581 // copysign(x, abs(y)) -> abs(x) 3582 if (N1.getOpcode() == ISD::FABS) 3583 return DAG.getNode(ISD::FABS, VT, N0); 3584 3585 // copysign(x, copysign(y,z)) -> copysign(x, z) 3586 if (N1.getOpcode() == ISD::FCOPYSIGN) 3587 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1)); 3588 3589 // copysign(x, fp_extend(y)) -> copysign(x, y) 3590 // copysign(x, fp_round(y)) -> copysign(x, y) 3591 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 3592 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0)); 3593 3594 return SDOperand(); 3595} 3596 3597 3598 3599SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) { 3600 SDOperand N0 = N->getOperand(0); 3601 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3602 MVT::ValueType VT = N->getValueType(0); 3603 3604 // fold (sint_to_fp c1) -> c1fp 3605 if (N0C && N0.getValueType() != MVT::ppcf128) 3606 return DAG.getNode(ISD::SINT_TO_FP, VT, N0); 3607 return SDOperand(); 3608} 3609 3610SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) { 3611 SDOperand N0 = N->getOperand(0); 3612 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3613 MVT::ValueType VT = N->getValueType(0); 3614 3615 // fold (uint_to_fp c1) -> c1fp 3616 if (N0C && N0.getValueType() != MVT::ppcf128) 3617 return DAG.getNode(ISD::UINT_TO_FP, VT, N0); 3618 return SDOperand(); 3619} 3620 3621SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) { 3622 SDOperand N0 = N->getOperand(0); 3623 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3624 MVT::ValueType VT = N->getValueType(0); 3625 3626 // fold (fp_to_sint c1fp) -> c1 3627 if (N0CFP) 3628 return DAG.getNode(ISD::FP_TO_SINT, VT, N0); 3629 return SDOperand(); 3630} 3631 3632SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) { 3633 SDOperand N0 = N->getOperand(0); 3634 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3635 MVT::ValueType VT = N->getValueType(0); 3636 3637 // fold (fp_to_uint c1fp) -> c1 3638 if (N0CFP && VT != MVT::ppcf128) 3639 return DAG.getNode(ISD::FP_TO_UINT, VT, N0); 3640 return SDOperand(); 3641} 3642 3643SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) { 3644 SDOperand N0 = N->getOperand(0); 3645 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3646 MVT::ValueType VT = N->getValueType(0); 3647 3648 // fold (fp_round c1fp) -> c1fp 3649 if (N0CFP && N0.getValueType() != MVT::ppcf128) 3650 return DAG.getNode(ISD::FP_ROUND, VT, N0); 3651 3652 // fold (fp_round (fp_extend x)) -> x 3653 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 3654 return N0.getOperand(0); 3655 3656 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 3657 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) { 3658 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0)); 3659 AddToWorkList(Tmp.Val); 3660 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1)); 3661 } 3662 3663 return SDOperand(); 3664} 3665 3666SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 3667 SDOperand N0 = N->getOperand(0); 3668 MVT::ValueType VT = N->getValueType(0); 3669 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3670 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3671 3672 // fold (fp_round_inreg c1fp) -> c1fp 3673 if (N0CFP) { 3674 SDOperand Round = DAG.getConstantFP(N0CFP->getValueAPF(), EVT); 3675 return DAG.getNode(ISD::FP_EXTEND, VT, Round); 3676 } 3677 return SDOperand(); 3678} 3679 3680SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) { 3681 SDOperand N0 = N->getOperand(0); 3682 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3683 MVT::ValueType VT = N->getValueType(0); 3684 3685 // fold (fp_extend c1fp) -> c1fp 3686 if (N0CFP && VT != MVT::ppcf128) 3687 return DAG.getNode(ISD::FP_EXTEND, VT, N0); 3688 3689 // fold (fpext (load x)) -> (fpext (fpround (extload x))) 3690 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 3691 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) { 3692 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3693 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 3694 LN0->getBasePtr(), LN0->getSrcValue(), 3695 LN0->getSrcValueOffset(), 3696 N0.getValueType(), 3697 LN0->isVolatile(), 3698 LN0->getAlignment()); 3699 CombineTo(N, ExtLoad); 3700 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad), 3701 ExtLoad.getValue(1)); 3702 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3703 } 3704 3705 3706 return SDOperand(); 3707} 3708 3709SDOperand DAGCombiner::visitFNEG(SDNode *N) { 3710 SDOperand N0 = N->getOperand(0); 3711 3712 if (isNegatibleForFree(N0)) 3713 return GetNegatedExpression(N0, DAG); 3714 3715 return SDOperand(); 3716} 3717 3718SDOperand DAGCombiner::visitFABS(SDNode *N) { 3719 SDOperand N0 = N->getOperand(0); 3720 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3721 MVT::ValueType VT = N->getValueType(0); 3722 3723 // fold (fabs c1) -> fabs(c1) 3724 if (N0CFP && VT != MVT::ppcf128) 3725 return DAG.getNode(ISD::FABS, VT, N0); 3726 // fold (fabs (fabs x)) -> (fabs x) 3727 if (N0.getOpcode() == ISD::FABS) 3728 return N->getOperand(0); 3729 // fold (fabs (fneg x)) -> (fabs x) 3730 // fold (fabs (fcopysign x, y)) -> (fabs x) 3731 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 3732 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0)); 3733 3734 return SDOperand(); 3735} 3736 3737SDOperand DAGCombiner::visitBRCOND(SDNode *N) { 3738 SDOperand Chain = N->getOperand(0); 3739 SDOperand N1 = N->getOperand(1); 3740 SDOperand N2 = N->getOperand(2); 3741 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3742 3743 // never taken branch, fold to chain 3744 if (N1C && N1C->isNullValue()) 3745 return Chain; 3746 // unconditional branch 3747 if (N1C && N1C->getValue() == 1) 3748 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 3749 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 3750 // on the target. 3751 if (N1.getOpcode() == ISD::SETCC && 3752 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) { 3753 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2), 3754 N1.getOperand(0), N1.getOperand(1), N2); 3755 } 3756 return SDOperand(); 3757} 3758 3759// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 3760// 3761SDOperand DAGCombiner::visitBR_CC(SDNode *N) { 3762 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 3763 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 3764 3765 // Use SimplifySetCC to simplify SETCC's. 3766 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false); 3767 if (Simp.Val) AddToWorkList(Simp.Val); 3768 3769 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val); 3770 3771 // fold br_cc true, dest -> br dest (unconditional branch) 3772 if (SCCC && SCCC->getValue()) 3773 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0), 3774 N->getOperand(4)); 3775 // fold br_cc false, dest -> unconditional fall through 3776 if (SCCC && SCCC->isNullValue()) 3777 return N->getOperand(0); 3778 3779 // fold to a simpler setcc 3780 if (Simp.Val && Simp.getOpcode() == ISD::SETCC) 3781 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0), 3782 Simp.getOperand(2), Simp.getOperand(0), 3783 Simp.getOperand(1), N->getOperand(4)); 3784 return SDOperand(); 3785} 3786 3787 3788/// CombineToPreIndexedLoadStore - Try turning a load / store and a 3789/// pre-indexed load / store when the base pointer is a add or subtract 3790/// and it has other uses besides the load / store. After the 3791/// transformation, the new indexed load / store has effectively folded 3792/// the add / subtract in and all of its other uses are redirected to the 3793/// new load / store. 3794bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 3795 if (!AfterLegalize) 3796 return false; 3797 3798 bool isLoad = true; 3799 SDOperand Ptr; 3800 MVT::ValueType VT; 3801 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 3802 if (LD->getAddressingMode() != ISD::UNINDEXED) 3803 return false; 3804 VT = LD->getLoadedVT(); 3805 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 3806 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 3807 return false; 3808 Ptr = LD->getBasePtr(); 3809 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 3810 if (ST->getAddressingMode() != ISD::UNINDEXED) 3811 return false; 3812 VT = ST->getStoredVT(); 3813 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 3814 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 3815 return false; 3816 Ptr = ST->getBasePtr(); 3817 isLoad = false; 3818 } else 3819 return false; 3820 3821 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 3822 // out. There is no reason to make this a preinc/predec. 3823 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 3824 Ptr.Val->hasOneUse()) 3825 return false; 3826 3827 // Ask the target to do addressing mode selection. 3828 SDOperand BasePtr; 3829 SDOperand Offset; 3830 ISD::MemIndexedMode AM = ISD::UNINDEXED; 3831 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 3832 return false; 3833 // Don't create a indexed load / store with zero offset. 3834 if (isa<ConstantSDNode>(Offset) && 3835 cast<ConstantSDNode>(Offset)->getValue() == 0) 3836 return false; 3837 3838 // Try turning it into a pre-indexed load / store except when: 3839 // 1) The new base ptr is a frame index. 3840 // 2) If N is a store and the new base ptr is either the same as or is a 3841 // predecessor of the value being stored. 3842 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 3843 // that would create a cycle. 3844 // 4) All uses are load / store ops that use it as old base ptr. 3845 3846 // Check #1. Preinc'ing a frame index would require copying the stack pointer 3847 // (plus the implicit offset) to a register to preinc anyway. 3848 if (isa<FrameIndexSDNode>(BasePtr)) 3849 return false; 3850 3851 // Check #2. 3852 if (!isLoad) { 3853 SDOperand Val = cast<StoreSDNode>(N)->getValue(); 3854 if (Val == BasePtr || BasePtr.Val->isPredecessor(Val.Val)) 3855 return false; 3856 } 3857 3858 // Now check for #3 and #4. 3859 bool RealUse = false; 3860 for (SDNode::use_iterator I = Ptr.Val->use_begin(), 3861 E = Ptr.Val->use_end(); I != E; ++I) { 3862 SDNode *Use = *I; 3863 if (Use == N) 3864 continue; 3865 if (Use->isPredecessor(N)) 3866 return false; 3867 3868 if (!((Use->getOpcode() == ISD::LOAD && 3869 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 3870 (Use->getOpcode() == ISD::STORE) && 3871 cast<StoreSDNode>(Use)->getBasePtr() == Ptr)) 3872 RealUse = true; 3873 } 3874 if (!RealUse) 3875 return false; 3876 3877 SDOperand Result; 3878 if (isLoad) 3879 Result = DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM); 3880 else 3881 Result = DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM); 3882 ++PreIndexedNodes; 3883 ++NodesCombined; 3884 DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG)); 3885 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG)); 3886 DOUT << '\n'; 3887 std::vector<SDNode*> NowDead; 3888 if (isLoad) { 3889 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0), 3890 &NowDead); 3891 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2), 3892 &NowDead); 3893 } else { 3894 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1), 3895 &NowDead); 3896 } 3897 3898 // Nodes can end up on the worklist more than once. Make sure we do 3899 // not process a node that has been replaced. 3900 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 3901 removeFromWorkList(NowDead[i]); 3902 // Finally, since the node is now dead, remove it from the graph. 3903 DAG.DeleteNode(N); 3904 3905 // Replace the uses of Ptr with uses of the updated base value. 3906 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 3907 &NowDead); 3908 removeFromWorkList(Ptr.Val); 3909 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 3910 removeFromWorkList(NowDead[i]); 3911 DAG.DeleteNode(Ptr.Val); 3912 3913 return true; 3914} 3915 3916/// CombineToPostIndexedLoadStore - Try combine a load / store with a 3917/// add / sub of the base pointer node into a post-indexed load / store. 3918/// The transformation folded the add / subtract into the new indexed 3919/// load / store effectively and all of its uses are redirected to the 3920/// new load / store. 3921bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 3922 if (!AfterLegalize) 3923 return false; 3924 3925 bool isLoad = true; 3926 SDOperand Ptr; 3927 MVT::ValueType VT; 3928 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 3929 if (LD->getAddressingMode() != ISD::UNINDEXED) 3930 return false; 3931 VT = LD->getLoadedVT(); 3932 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 3933 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 3934 return false; 3935 Ptr = LD->getBasePtr(); 3936 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 3937 if (ST->getAddressingMode() != ISD::UNINDEXED) 3938 return false; 3939 VT = ST->getStoredVT(); 3940 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 3941 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 3942 return false; 3943 Ptr = ST->getBasePtr(); 3944 isLoad = false; 3945 } else 3946 return false; 3947 3948 if (Ptr.Val->hasOneUse()) 3949 return false; 3950 3951 for (SDNode::use_iterator I = Ptr.Val->use_begin(), 3952 E = Ptr.Val->use_end(); I != E; ++I) { 3953 SDNode *Op = *I; 3954 if (Op == N || 3955 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 3956 continue; 3957 3958 SDOperand BasePtr; 3959 SDOperand Offset; 3960 ISD::MemIndexedMode AM = ISD::UNINDEXED; 3961 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 3962 if (Ptr == Offset) 3963 std::swap(BasePtr, Offset); 3964 if (Ptr != BasePtr) 3965 continue; 3966 // Don't create a indexed load / store with zero offset. 3967 if (isa<ConstantSDNode>(Offset) && 3968 cast<ConstantSDNode>(Offset)->getValue() == 0) 3969 continue; 3970 3971 // Try turning it into a post-indexed load / store except when 3972 // 1) All uses are load / store ops that use it as base ptr. 3973 // 2) Op must be independent of N, i.e. Op is neither a predecessor 3974 // nor a successor of N. Otherwise, if Op is folded that would 3975 // create a cycle. 3976 3977 // Check for #1. 3978 bool TryNext = false; 3979 for (SDNode::use_iterator II = BasePtr.Val->use_begin(), 3980 EE = BasePtr.Val->use_end(); II != EE; ++II) { 3981 SDNode *Use = *II; 3982 if (Use == Ptr.Val) 3983 continue; 3984 3985 // If all the uses are load / store addresses, then don't do the 3986 // transformation. 3987 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 3988 bool RealUse = false; 3989 for (SDNode::use_iterator III = Use->use_begin(), 3990 EEE = Use->use_end(); III != EEE; ++III) { 3991 SDNode *UseUse = *III; 3992 if (!((UseUse->getOpcode() == ISD::LOAD && 3993 cast<LoadSDNode>(UseUse)->getBasePtr().Val == Use) || 3994 (UseUse->getOpcode() == ISD::STORE) && 3995 cast<StoreSDNode>(UseUse)->getBasePtr().Val == Use)) 3996 RealUse = true; 3997 } 3998 3999 if (!RealUse) { 4000 TryNext = true; 4001 break; 4002 } 4003 } 4004 } 4005 if (TryNext) 4006 continue; 4007 4008 // Check for #2 4009 if (!Op->isPredecessor(N) && !N->isPredecessor(Op)) { 4010 SDOperand Result = isLoad 4011 ? DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM) 4012 : DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM); 4013 ++PostIndexedNodes; 4014 ++NodesCombined; 4015 DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG)); 4016 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG)); 4017 DOUT << '\n'; 4018 std::vector<SDNode*> NowDead; 4019 if (isLoad) { 4020 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0), 4021 &NowDead); 4022 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2), 4023 &NowDead); 4024 } else { 4025 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1), 4026 &NowDead); 4027 } 4028 4029 // Nodes can end up on the worklist more than once. Make sure we do 4030 // not process a node that has been replaced. 4031 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 4032 removeFromWorkList(NowDead[i]); 4033 // Finally, since the node is now dead, remove it from the graph. 4034 DAG.DeleteNode(N); 4035 4036 // Replace the uses of Use with uses of the updated base value. 4037 DAG.ReplaceAllUsesOfValueWith(SDOperand(Op, 0), 4038 Result.getValue(isLoad ? 1 : 0), 4039 &NowDead); 4040 removeFromWorkList(Op); 4041 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 4042 removeFromWorkList(NowDead[i]); 4043 DAG.DeleteNode(Op); 4044 4045 return true; 4046 } 4047 } 4048 } 4049 return false; 4050} 4051 4052 4053SDOperand DAGCombiner::visitLOAD(SDNode *N) { 4054 LoadSDNode *LD = cast<LoadSDNode>(N); 4055 SDOperand Chain = LD->getChain(); 4056 SDOperand Ptr = LD->getBasePtr(); 4057 4058 // If load is not volatile and there are no uses of the loaded value (and 4059 // the updated indexed value in case of indexed loads), change uses of the 4060 // chain value into uses of the chain input (i.e. delete the dead load). 4061 if (!LD->isVolatile()) { 4062 if (N->getValueType(1) == MVT::Other) { 4063 // Unindexed loads. 4064 if (N->hasNUsesOfValue(0, 0)) 4065 return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain); 4066 } else { 4067 // Indexed loads. 4068 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 4069 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 4070 SDOperand Undef0 = DAG.getNode(ISD::UNDEF, N->getValueType(0)); 4071 SDOperand Undef1 = DAG.getNode(ISD::UNDEF, N->getValueType(1)); 4072 SDOperand To[] = { Undef0, Undef1, Chain }; 4073 return CombineTo(N, To, 3); 4074 } 4075 } 4076 } 4077 4078 // If this load is directly stored, replace the load value with the stored 4079 // value. 4080 // TODO: Handle store large -> read small portion. 4081 // TODO: Handle TRUNCSTORE/LOADEXT 4082 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 4083 if (ISD::isNON_TRUNCStore(Chain.Val)) { 4084 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 4085 if (PrevST->getBasePtr() == Ptr && 4086 PrevST->getValue().getValueType() == N->getValueType(0)) 4087 return CombineTo(N, Chain.getOperand(1), Chain); 4088 } 4089 } 4090 4091 if (CombinerAA) { 4092 // Walk up chain skipping non-aliasing memory nodes. 4093 SDOperand BetterChain = FindBetterChain(N, Chain); 4094 4095 // If there is a better chain. 4096 if (Chain != BetterChain) { 4097 SDOperand ReplLoad; 4098 4099 // Replace the chain to void dependency. 4100 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 4101 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr, 4102 LD->getSrcValue(), LD->getSrcValueOffset(), 4103 LD->isVolatile(), LD->getAlignment()); 4104 } else { 4105 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), 4106 LD->getValueType(0), 4107 BetterChain, Ptr, LD->getSrcValue(), 4108 LD->getSrcValueOffset(), 4109 LD->getLoadedVT(), 4110 LD->isVolatile(), 4111 LD->getAlignment()); 4112 } 4113 4114 // Create token factor to keep old chain connected. 4115 SDOperand Token = DAG.getNode(ISD::TokenFactor, MVT::Other, 4116 Chain, ReplLoad.getValue(1)); 4117 4118 // Replace uses with load result and token factor. Don't add users 4119 // to work list. 4120 return CombineTo(N, ReplLoad.getValue(0), Token, false); 4121 } 4122 } 4123 4124 // Try transforming N to an indexed load. 4125 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4126 return SDOperand(N, 0); 4127 4128 return SDOperand(); 4129} 4130 4131SDOperand DAGCombiner::visitSTORE(SDNode *N) { 4132 StoreSDNode *ST = cast<StoreSDNode>(N); 4133 SDOperand Chain = ST->getChain(); 4134 SDOperand Value = ST->getValue(); 4135 SDOperand Ptr = ST->getBasePtr(); 4136 4137 // If this is a store of a bit convert, store the input value if the 4138 // resultant store does not need a higher alignment than the original. 4139 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() && 4140 ST->getAddressingMode() == ISD::UNINDEXED) { 4141 unsigned Align = ST->getAlignment(); 4142 MVT::ValueType SVT = Value.getOperand(0).getValueType(); 4143 unsigned OrigAlign = TLI.getTargetMachine().getTargetData()-> 4144 getABITypeAlignment(MVT::getTypeForValueType(SVT)); 4145 if (Align <= OrigAlign && TLI.isOperationLegal(ISD::STORE, SVT)) 4146 return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), 4147 ST->getSrcValueOffset(), ST->isVolatile(), Align); 4148 } 4149 4150 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 4151 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 4152 if (Value.getOpcode() != ISD::TargetConstantFP) { 4153 SDOperand Tmp; 4154 switch (CFP->getValueType(0)) { 4155 default: assert(0 && "Unknown FP type"); 4156 case MVT::f80: // We don't do this for these yet. 4157 case MVT::f128: 4158 case MVT::ppcf128: 4159 break; 4160 case MVT::f32: 4161 if (!AfterLegalize || TLI.isTypeLegal(MVT::i32)) { 4162 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 4163 convertToAPInt().getZExtValue(), MVT::i32); 4164 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 4165 ST->getSrcValueOffset(), ST->isVolatile(), 4166 ST->getAlignment()); 4167 } 4168 break; 4169 case MVT::f64: 4170 if (!AfterLegalize || TLI.isTypeLegal(MVT::i64)) { 4171 Tmp = DAG.getConstant(CFP->getValueAPF().convertToAPInt(). 4172 getZExtValue(), MVT::i64); 4173 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 4174 ST->getSrcValueOffset(), ST->isVolatile(), 4175 ST->getAlignment()); 4176 } else if (TLI.isTypeLegal(MVT::i32)) { 4177 // Many FP stores are not made apparent until after legalize, e.g. for 4178 // argument passing. Since this is so common, custom legalize the 4179 // 64-bit integer store into two 32-bit stores. 4180 uint64_t Val = CFP->getValueAPF().convertToAPInt().getZExtValue(); 4181 SDOperand Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 4182 SDOperand Hi = DAG.getConstant(Val >> 32, MVT::i32); 4183 if (!TLI.isLittleEndian()) std::swap(Lo, Hi); 4184 4185 int SVOffset = ST->getSrcValueOffset(); 4186 unsigned Alignment = ST->getAlignment(); 4187 bool isVolatile = ST->isVolatile(); 4188 4189 SDOperand St0 = DAG.getStore(Chain, Lo, Ptr, ST->getSrcValue(), 4190 ST->getSrcValueOffset(), 4191 isVolatile, ST->getAlignment()); 4192 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 4193 DAG.getConstant(4, Ptr.getValueType())); 4194 SVOffset += 4; 4195 Alignment = MinAlign(Alignment, 4U); 4196 SDOperand St1 = DAG.getStore(Chain, Hi, Ptr, ST->getSrcValue(), 4197 SVOffset, isVolatile, Alignment); 4198 return DAG.getNode(ISD::TokenFactor, MVT::Other, St0, St1); 4199 } 4200 break; 4201 } 4202 } 4203 } 4204 4205 if (CombinerAA) { 4206 // Walk up chain skipping non-aliasing memory nodes. 4207 SDOperand BetterChain = FindBetterChain(N, Chain); 4208 4209 // If there is a better chain. 4210 if (Chain != BetterChain) { 4211 // Replace the chain to avoid dependency. 4212 SDOperand ReplStore; 4213 if (ST->isTruncatingStore()) { 4214 ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr, 4215 ST->getSrcValue(), ST->getSrcValueOffset(), ST->getStoredVT(), 4216 ST->isVolatile(), ST->getAlignment()); 4217 } else { 4218 ReplStore = DAG.getStore(BetterChain, Value, Ptr, 4219 ST->getSrcValue(), ST->getSrcValueOffset(), 4220 ST->isVolatile(), ST->getAlignment()); 4221 } 4222 4223 // Create token to keep both nodes around. 4224 SDOperand Token = 4225 DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore); 4226 4227 // Don't add users to work list. 4228 return CombineTo(N, Token, false); 4229 } 4230 } 4231 4232 // Try transforming N to an indexed store. 4233 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4234 return SDOperand(N, 0); 4235 4236 // FIXME: is there such a think as a truncating indexed store? 4237 if (ST->isTruncatingStore() && ST->getAddressingMode() == ISD::UNINDEXED && 4238 MVT::isInteger(Value.getValueType())) { 4239 // See if we can simplify the input to this truncstore with knowledge that 4240 // only the low bits are being used. For example: 4241 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 4242 SDOperand Shorter = 4243 GetDemandedBits(Value, MVT::getIntVTBitMask(ST->getStoredVT())); 4244 AddToWorkList(Value.Val); 4245 if (Shorter.Val) 4246 return DAG.getTruncStore(Chain, Shorter, Ptr, ST->getSrcValue(), 4247 ST->getSrcValueOffset(), ST->getStoredVT(), 4248 ST->isVolatile(), ST->getAlignment()); 4249 4250 // Otherwise, see if we can simplify the operation with 4251 // SimplifyDemandedBits, which only works if the value has a single use. 4252 if (SimplifyDemandedBits(Value, MVT::getIntVTBitMask(ST->getStoredVT()))) 4253 return SDOperand(N, 0); 4254 } 4255 4256 return SDOperand(); 4257} 4258 4259SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 4260 SDOperand InVec = N->getOperand(0); 4261 SDOperand InVal = N->getOperand(1); 4262 SDOperand EltNo = N->getOperand(2); 4263 4264 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 4265 // vector with the inserted element. 4266 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 4267 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 4268 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end()); 4269 if (Elt < Ops.size()) 4270 Ops[Elt] = InVal; 4271 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(), 4272 &Ops[0], Ops.size()); 4273 } 4274 4275 return SDOperand(); 4276} 4277 4278SDOperand DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 4279 SDOperand InVec = N->getOperand(0); 4280 SDOperand EltNo = N->getOperand(1); 4281 4282 // (vextract (v4f32 s2v (f32 load $addr)), 0) -> (f32 load $addr) 4283 // (vextract (v4i32 bc (v4f32 s2v (f32 load $addr))), 0) -> (i32 load $addr) 4284 if (isa<ConstantSDNode>(EltNo)) { 4285 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 4286 bool NewLoad = false; 4287 if (Elt == 0) { 4288 MVT::ValueType VT = InVec.getValueType(); 4289 MVT::ValueType EVT = MVT::getVectorElementType(VT); 4290 MVT::ValueType LVT = EVT; 4291 unsigned NumElts = MVT::getVectorNumElements(VT); 4292 if (InVec.getOpcode() == ISD::BIT_CONVERT) { 4293 MVT::ValueType BCVT = InVec.getOperand(0).getValueType(); 4294 if (!MVT::isVector(BCVT) || 4295 NumElts != MVT::getVectorNumElements(BCVT)) 4296 return SDOperand(); 4297 InVec = InVec.getOperand(0); 4298 EVT = MVT::getVectorElementType(BCVT); 4299 NewLoad = true; 4300 } 4301 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 4302 InVec.getOperand(0).getValueType() == EVT && 4303 ISD::isNormalLoad(InVec.getOperand(0).Val) && 4304 InVec.getOperand(0).hasOneUse()) { 4305 LoadSDNode *LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 4306 unsigned Align = LN0->getAlignment(); 4307 if (NewLoad) { 4308 // Check the resultant load doesn't need a higher alignment than the 4309 // original load. 4310 unsigned NewAlign = TLI.getTargetMachine().getTargetData()-> 4311 getABITypeAlignment(MVT::getTypeForValueType(LVT)); 4312 if (!TLI.isOperationLegal(ISD::LOAD, LVT) || NewAlign > Align) 4313 return SDOperand(); 4314 Align = NewAlign; 4315 } 4316 4317 return DAG.getLoad(LVT, LN0->getChain(), LN0->getBasePtr(), 4318 LN0->getSrcValue(), LN0->getSrcValueOffset(), 4319 LN0->isVolatile(), Align); 4320 } 4321 } 4322 } 4323 return SDOperand(); 4324} 4325 4326 4327SDOperand DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 4328 unsigned NumInScalars = N->getNumOperands(); 4329 MVT::ValueType VT = N->getValueType(0); 4330 unsigned NumElts = MVT::getVectorNumElements(VT); 4331 MVT::ValueType EltType = MVT::getVectorElementType(VT); 4332 4333 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 4334 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 4335 // at most two distinct vectors, turn this into a shuffle node. 4336 SDOperand VecIn1, VecIn2; 4337 for (unsigned i = 0; i != NumInScalars; ++i) { 4338 // Ignore undef inputs. 4339 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 4340 4341 // If this input is something other than a EXTRACT_VECTOR_ELT with a 4342 // constant index, bail out. 4343 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 4344 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 4345 VecIn1 = VecIn2 = SDOperand(0, 0); 4346 break; 4347 } 4348 4349 // If the input vector type disagrees with the result of the build_vector, 4350 // we can't make a shuffle. 4351 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0); 4352 if (ExtractedFromVec.getValueType() != VT) { 4353 VecIn1 = VecIn2 = SDOperand(0, 0); 4354 break; 4355 } 4356 4357 // Otherwise, remember this. We allow up to two distinct input vectors. 4358 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 4359 continue; 4360 4361 if (VecIn1.Val == 0) { 4362 VecIn1 = ExtractedFromVec; 4363 } else if (VecIn2.Val == 0) { 4364 VecIn2 = ExtractedFromVec; 4365 } else { 4366 // Too many inputs. 4367 VecIn1 = VecIn2 = SDOperand(0, 0); 4368 break; 4369 } 4370 } 4371 4372 // If everything is good, we can make a shuffle operation. 4373 if (VecIn1.Val) { 4374 SmallVector<SDOperand, 8> BuildVecIndices; 4375 for (unsigned i = 0; i != NumInScalars; ++i) { 4376 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 4377 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, TLI.getPointerTy())); 4378 continue; 4379 } 4380 4381 SDOperand Extract = N->getOperand(i); 4382 4383 // If extracting from the first vector, just use the index directly. 4384 if (Extract.getOperand(0) == VecIn1) { 4385 BuildVecIndices.push_back(Extract.getOperand(1)); 4386 continue; 4387 } 4388 4389 // Otherwise, use InIdx + VecSize 4390 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue(); 4391 BuildVecIndices.push_back(DAG.getConstant(Idx+NumInScalars, 4392 TLI.getPointerTy())); 4393 } 4394 4395 // Add count and size info. 4396 MVT::ValueType BuildVecVT = 4397 MVT::getVectorType(TLI.getPointerTy(), NumElts); 4398 4399 // Return the new VECTOR_SHUFFLE node. 4400 SDOperand Ops[5]; 4401 Ops[0] = VecIn1; 4402 if (VecIn2.Val) { 4403 Ops[1] = VecIn2; 4404 } else { 4405 // Use an undef build_vector as input for the second operand. 4406 std::vector<SDOperand> UnOps(NumInScalars, 4407 DAG.getNode(ISD::UNDEF, 4408 EltType)); 4409 Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, VT, 4410 &UnOps[0], UnOps.size()); 4411 AddToWorkList(Ops[1].Val); 4412 } 4413 Ops[2] = DAG.getNode(ISD::BUILD_VECTOR, BuildVecVT, 4414 &BuildVecIndices[0], BuildVecIndices.size()); 4415 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Ops, 3); 4416 } 4417 4418 return SDOperand(); 4419} 4420 4421SDOperand DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 4422 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 4423 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 4424 // inputs come from at most two distinct vectors, turn this into a shuffle 4425 // node. 4426 4427 // If we only have one input vector, we don't need to do any concatenation. 4428 if (N->getNumOperands() == 1) { 4429 return N->getOperand(0); 4430 } 4431 4432 return SDOperand(); 4433} 4434 4435SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 4436 SDOperand ShufMask = N->getOperand(2); 4437 unsigned NumElts = ShufMask.getNumOperands(); 4438 4439 // If the shuffle mask is an identity operation on the LHS, return the LHS. 4440 bool isIdentity = true; 4441 for (unsigned i = 0; i != NumElts; ++i) { 4442 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 4443 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) { 4444 isIdentity = false; 4445 break; 4446 } 4447 } 4448 if (isIdentity) return N->getOperand(0); 4449 4450 // If the shuffle mask is an identity operation on the RHS, return the RHS. 4451 isIdentity = true; 4452 for (unsigned i = 0; i != NumElts; ++i) { 4453 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 4454 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) { 4455 isIdentity = false; 4456 break; 4457 } 4458 } 4459 if (isIdentity) return N->getOperand(1); 4460 4461 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not 4462 // needed at all. 4463 bool isUnary = true; 4464 bool isSplat = true; 4465 int VecNum = -1; 4466 unsigned BaseIdx = 0; 4467 for (unsigned i = 0; i != NumElts; ++i) 4468 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) { 4469 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue(); 4470 int V = (Idx < NumElts) ? 0 : 1; 4471 if (VecNum == -1) { 4472 VecNum = V; 4473 BaseIdx = Idx; 4474 } else { 4475 if (BaseIdx != Idx) 4476 isSplat = false; 4477 if (VecNum != V) { 4478 isUnary = false; 4479 break; 4480 } 4481 } 4482 } 4483 4484 SDOperand N0 = N->getOperand(0); 4485 SDOperand N1 = N->getOperand(1); 4486 // Normalize unary shuffle so the RHS is undef. 4487 if (isUnary && VecNum == 1) 4488 std::swap(N0, N1); 4489 4490 // If it is a splat, check if the argument vector is a build_vector with 4491 // all scalar elements the same. 4492 if (isSplat) { 4493 SDNode *V = N0.Val; 4494 4495 // If this is a bit convert that changes the element type of the vector but 4496 // not the number of vector elements, look through it. Be careful not to 4497 // look though conversions that change things like v4f32 to v2f64. 4498 if (V->getOpcode() == ISD::BIT_CONVERT) { 4499 SDOperand ConvInput = V->getOperand(0); 4500 if (MVT::getVectorNumElements(ConvInput.getValueType()) == NumElts) 4501 V = ConvInput.Val; 4502 } 4503 4504 if (V->getOpcode() == ISD::BUILD_VECTOR) { 4505 unsigned NumElems = V->getNumOperands(); 4506 if (NumElems > BaseIdx) { 4507 SDOperand Base; 4508 bool AllSame = true; 4509 for (unsigned i = 0; i != NumElems; ++i) { 4510 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 4511 Base = V->getOperand(i); 4512 break; 4513 } 4514 } 4515 // Splat of <u, u, u, u>, return <u, u, u, u> 4516 if (!Base.Val) 4517 return N0; 4518 for (unsigned i = 0; i != NumElems; ++i) { 4519 if (V->getOperand(i) != Base) { 4520 AllSame = false; 4521 break; 4522 } 4523 } 4524 // Splat of <x, x, x, x>, return <x, x, x, x> 4525 if (AllSame) 4526 return N0; 4527 } 4528 } 4529 } 4530 4531 // If it is a unary or the LHS and the RHS are the same node, turn the RHS 4532 // into an undef. 4533 if (isUnary || N0 == N1) { 4534 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the 4535 // first operand. 4536 SmallVector<SDOperand, 8> MappedOps; 4537 for (unsigned i = 0; i != NumElts; ++i) { 4538 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || 4539 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) { 4540 MappedOps.push_back(ShufMask.getOperand(i)); 4541 } else { 4542 unsigned NewIdx = 4543 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts; 4544 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32)); 4545 } 4546 } 4547 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(), 4548 &MappedOps[0], MappedOps.size()); 4549 AddToWorkList(ShufMask.Val); 4550 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0), 4551 N0, 4552 DAG.getNode(ISD::UNDEF, N->getValueType(0)), 4553 ShufMask); 4554 } 4555 4556 return SDOperand(); 4557} 4558 4559/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 4560/// an AND to a vector_shuffle with the destination vector and a zero vector. 4561/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 4562/// vector_shuffle V, Zero, <0, 4, 2, 4> 4563SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) { 4564 SDOperand LHS = N->getOperand(0); 4565 SDOperand RHS = N->getOperand(1); 4566 if (N->getOpcode() == ISD::AND) { 4567 if (RHS.getOpcode() == ISD::BIT_CONVERT) 4568 RHS = RHS.getOperand(0); 4569 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 4570 std::vector<SDOperand> IdxOps; 4571 unsigned NumOps = RHS.getNumOperands(); 4572 unsigned NumElts = NumOps; 4573 MVT::ValueType EVT = MVT::getVectorElementType(RHS.getValueType()); 4574 for (unsigned i = 0; i != NumElts; ++i) { 4575 SDOperand Elt = RHS.getOperand(i); 4576 if (!isa<ConstantSDNode>(Elt)) 4577 return SDOperand(); 4578 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 4579 IdxOps.push_back(DAG.getConstant(i, EVT)); 4580 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 4581 IdxOps.push_back(DAG.getConstant(NumElts, EVT)); 4582 else 4583 return SDOperand(); 4584 } 4585 4586 // Let's see if the target supports this vector_shuffle. 4587 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG)) 4588 return SDOperand(); 4589 4590 // Return the new VECTOR_SHUFFLE node. 4591 MVT::ValueType VT = MVT::getVectorType(EVT, NumElts); 4592 std::vector<SDOperand> Ops; 4593 LHS = DAG.getNode(ISD::BIT_CONVERT, VT, LHS); 4594 Ops.push_back(LHS); 4595 AddToWorkList(LHS.Val); 4596 std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT)); 4597 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT, 4598 &ZeroOps[0], ZeroOps.size())); 4599 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT, 4600 &IdxOps[0], IdxOps.size())); 4601 SDOperand Result = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, 4602 &Ops[0], Ops.size()); 4603 if (VT != LHS.getValueType()) { 4604 Result = DAG.getNode(ISD::BIT_CONVERT, LHS.getValueType(), Result); 4605 } 4606 return Result; 4607 } 4608 } 4609 return SDOperand(); 4610} 4611 4612/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 4613SDOperand DAGCombiner::SimplifyVBinOp(SDNode *N) { 4614 // After legalize, the target may be depending on adds and other 4615 // binary ops to provide legal ways to construct constants or other 4616 // things. Simplifying them may result in a loss of legality. 4617 if (AfterLegalize) return SDOperand(); 4618 4619 MVT::ValueType VT = N->getValueType(0); 4620 assert(MVT::isVector(VT) && "SimplifyVBinOp only works on vectors!"); 4621 4622 MVT::ValueType EltType = MVT::getVectorElementType(VT); 4623 SDOperand LHS = N->getOperand(0); 4624 SDOperand RHS = N->getOperand(1); 4625 SDOperand Shuffle = XformToShuffleWithZero(N); 4626 if (Shuffle.Val) return Shuffle; 4627 4628 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 4629 // this operation. 4630 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 4631 RHS.getOpcode() == ISD::BUILD_VECTOR) { 4632 SmallVector<SDOperand, 8> Ops; 4633 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 4634 SDOperand LHSOp = LHS.getOperand(i); 4635 SDOperand RHSOp = RHS.getOperand(i); 4636 // If these two elements can't be folded, bail out. 4637 if ((LHSOp.getOpcode() != ISD::UNDEF && 4638 LHSOp.getOpcode() != ISD::Constant && 4639 LHSOp.getOpcode() != ISD::ConstantFP) || 4640 (RHSOp.getOpcode() != ISD::UNDEF && 4641 RHSOp.getOpcode() != ISD::Constant && 4642 RHSOp.getOpcode() != ISD::ConstantFP)) 4643 break; 4644 // Can't fold divide by zero. 4645 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 4646 N->getOpcode() == ISD::FDIV) { 4647 if ((RHSOp.getOpcode() == ISD::Constant && 4648 cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) || 4649 (RHSOp.getOpcode() == ISD::ConstantFP && 4650 cast<ConstantFPSDNode>(RHSOp.Val)->getValueAPF().isZero())) 4651 break; 4652 } 4653 Ops.push_back(DAG.getNode(N->getOpcode(), EltType, LHSOp, RHSOp)); 4654 AddToWorkList(Ops.back().Val); 4655 assert((Ops.back().getOpcode() == ISD::UNDEF || 4656 Ops.back().getOpcode() == ISD::Constant || 4657 Ops.back().getOpcode() == ISD::ConstantFP) && 4658 "Scalar binop didn't fold!"); 4659 } 4660 4661 if (Ops.size() == LHS.getNumOperands()) { 4662 MVT::ValueType VT = LHS.getValueType(); 4663 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 4664 } 4665 } 4666 4667 return SDOperand(); 4668} 4669 4670SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){ 4671 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 4672 4673 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2, 4674 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4675 // If we got a simplified select_cc node back from SimplifySelectCC, then 4676 // break it down into a new SETCC node, and a new SELECT node, and then return 4677 // the SELECT node, since we were called with a SELECT node. 4678 if (SCC.Val) { 4679 // Check to see if we got a select_cc back (to turn into setcc/select). 4680 // Otherwise, just return whatever node we got back, like fabs. 4681 if (SCC.getOpcode() == ISD::SELECT_CC) { 4682 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(), 4683 SCC.getOperand(0), SCC.getOperand(1), 4684 SCC.getOperand(4)); 4685 AddToWorkList(SETCC.Val); 4686 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2), 4687 SCC.getOperand(3), SETCC); 4688 } 4689 return SCC; 4690 } 4691 return SDOperand(); 4692} 4693 4694/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 4695/// are the two values being selected between, see if we can simplify the 4696/// select. Callers of this should assume that TheSelect is deleted if this 4697/// returns true. As such, they should return the appropriate thing (e.g. the 4698/// node) back to the top-level of the DAG combiner loop to avoid it being 4699/// looked at. 4700/// 4701bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS, 4702 SDOperand RHS) { 4703 4704 // If this is a select from two identical things, try to pull the operation 4705 // through the select. 4706 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 4707 // If this is a load and the token chain is identical, replace the select 4708 // of two loads with a load through a select of the address to load from. 4709 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 4710 // constants have been dropped into the constant pool. 4711 if (LHS.getOpcode() == ISD::LOAD && 4712 // Token chains must be identical. 4713 LHS.getOperand(0) == RHS.getOperand(0)) { 4714 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 4715 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 4716 4717 // If this is an EXTLOAD, the VT's must match. 4718 if (LLD->getLoadedVT() == RLD->getLoadedVT()) { 4719 // FIXME: this conflates two src values, discarding one. This is not 4720 // the right thing to do, but nothing uses srcvalues now. When they do, 4721 // turn SrcValue into a list of locations. 4722 SDOperand Addr; 4723 if (TheSelect->getOpcode() == ISD::SELECT) { 4724 // Check that the condition doesn't reach either load. If so, folding 4725 // this will induce a cycle into the DAG. 4726 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) && 4727 !RLD->isPredecessor(TheSelect->getOperand(0).Val)) { 4728 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(), 4729 TheSelect->getOperand(0), LLD->getBasePtr(), 4730 RLD->getBasePtr()); 4731 } 4732 } else { 4733 // Check that the condition doesn't reach either load. If so, folding 4734 // this will induce a cycle into the DAG. 4735 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) && 4736 !RLD->isPredecessor(TheSelect->getOperand(0).Val) && 4737 !LLD->isPredecessor(TheSelect->getOperand(1).Val) && 4738 !RLD->isPredecessor(TheSelect->getOperand(1).Val)) { 4739 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(), 4740 TheSelect->getOperand(0), 4741 TheSelect->getOperand(1), 4742 LLD->getBasePtr(), RLD->getBasePtr(), 4743 TheSelect->getOperand(4)); 4744 } 4745 } 4746 4747 if (Addr.Val) { 4748 SDOperand Load; 4749 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) 4750 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(), 4751 Addr,LLD->getSrcValue(), 4752 LLD->getSrcValueOffset(), 4753 LLD->isVolatile(), 4754 LLD->getAlignment()); 4755 else { 4756 Load = DAG.getExtLoad(LLD->getExtensionType(), 4757 TheSelect->getValueType(0), 4758 LLD->getChain(), Addr, LLD->getSrcValue(), 4759 LLD->getSrcValueOffset(), 4760 LLD->getLoadedVT(), 4761 LLD->isVolatile(), 4762 LLD->getAlignment()); 4763 } 4764 // Users of the select now use the result of the load. 4765 CombineTo(TheSelect, Load); 4766 4767 // Users of the old loads now use the new load's chain. We know the 4768 // old-load value is dead now. 4769 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1)); 4770 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1)); 4771 return true; 4772 } 4773 } 4774 } 4775 } 4776 4777 return false; 4778} 4779 4780SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1, 4781 SDOperand N2, SDOperand N3, 4782 ISD::CondCode CC, bool NotExtCompare) { 4783 4784 MVT::ValueType VT = N2.getValueType(); 4785 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 4786 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 4787 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 4788 4789 // Determine if the condition we're dealing with is constant 4790 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 4791 if (SCC.Val) AddToWorkList(SCC.Val); 4792 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 4793 4794 // fold select_cc true, x, y -> x 4795 if (SCCC && SCCC->getValue()) 4796 return N2; 4797 // fold select_cc false, x, y -> y 4798 if (SCCC && SCCC->getValue() == 0) 4799 return N3; 4800 4801 // Check to see if we can simplify the select into an fabs node 4802 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 4803 // Allow either -0.0 or 0.0 4804 if (CFP->getValueAPF().isZero()) { 4805 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 4806 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 4807 N0 == N2 && N3.getOpcode() == ISD::FNEG && 4808 N2 == N3.getOperand(0)) 4809 return DAG.getNode(ISD::FABS, VT, N0); 4810 4811 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 4812 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 4813 N0 == N3 && N2.getOpcode() == ISD::FNEG && 4814 N2.getOperand(0) == N3) 4815 return DAG.getNode(ISD::FABS, VT, N3); 4816 } 4817 } 4818 4819 // Check to see if we can perform the "gzip trick", transforming 4820 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 4821 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 4822 MVT::isInteger(N0.getValueType()) && 4823 MVT::isInteger(N2.getValueType()) && 4824 (N1C->isNullValue() || // (a < 0) ? b : 0 4825 (N1C->getValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 4826 MVT::ValueType XType = N0.getValueType(); 4827 MVT::ValueType AType = N2.getValueType(); 4828 if (XType >= AType) { 4829 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 4830 // single-bit constant. 4831 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) { 4832 unsigned ShCtV = Log2_64(N2C->getValue()); 4833 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1; 4834 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy()); 4835 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt); 4836 AddToWorkList(Shift.Val); 4837 if (XType > AType) { 4838 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 4839 AddToWorkList(Shift.Val); 4840 } 4841 return DAG.getNode(ISD::AND, AType, Shift, N2); 4842 } 4843 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 4844 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4845 TLI.getShiftAmountTy())); 4846 AddToWorkList(Shift.Val); 4847 if (XType > AType) { 4848 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 4849 AddToWorkList(Shift.Val); 4850 } 4851 return DAG.getNode(ISD::AND, AType, Shift, N2); 4852 } 4853 } 4854 4855 // fold select C, 16, 0 -> shl C, 4 4856 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) && 4857 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) { 4858 4859 // If the caller doesn't want us to simplify this into a zext of a compare, 4860 // don't do it. 4861 if (NotExtCompare && N2C->getValue() == 1) 4862 return SDOperand(); 4863 4864 // Get a SetCC of the condition 4865 // FIXME: Should probably make sure that setcc is legal if we ever have a 4866 // target where it isn't. 4867 SDOperand Temp, SCC; 4868 // cast from setcc result type to select result type 4869 if (AfterLegalize) { 4870 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 4871 if (N2.getValueType() < SCC.getValueType()) 4872 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType()); 4873 else 4874 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 4875 } else { 4876 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC); 4877 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 4878 } 4879 AddToWorkList(SCC.Val); 4880 AddToWorkList(Temp.Val); 4881 4882 if (N2C->getValue() == 1) 4883 return Temp; 4884 // shl setcc result by log2 n2c 4885 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp, 4886 DAG.getConstant(Log2_64(N2C->getValue()), 4887 TLI.getShiftAmountTy())); 4888 } 4889 4890 // Check to see if this is the equivalent of setcc 4891 // FIXME: Turn all of these into setcc if setcc if setcc is legal 4892 // otherwise, go ahead with the folds. 4893 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) { 4894 MVT::ValueType XType = N0.getValueType(); 4895 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) { 4896 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 4897 if (Res.getValueType() != VT) 4898 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res); 4899 return Res; 4900 } 4901 4902 // seteq X, 0 -> srl (ctlz X, log2(size(X))) 4903 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 4904 TLI.isOperationLegal(ISD::CTLZ, XType)) { 4905 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0); 4906 return DAG.getNode(ISD::SRL, XType, Ctlz, 4907 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)), 4908 TLI.getShiftAmountTy())); 4909 } 4910 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) 4911 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 4912 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType), 4913 N0); 4914 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0, 4915 DAG.getConstant(~0ULL, XType)); 4916 return DAG.getNode(ISD::SRL, XType, 4917 DAG.getNode(ISD::AND, XType, NegN0, NotN0), 4918 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4919 TLI.getShiftAmountTy())); 4920 } 4921 // setgt X, -1 -> xor (srl (X, size(X)-1), 1) 4922 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 4923 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0, 4924 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4925 TLI.getShiftAmountTy())); 4926 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType)); 4927 } 4928 } 4929 4930 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 4931 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 4932 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 4933 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) && 4934 N2.getOperand(0) == N1 && MVT::isInteger(N0.getValueType())) { 4935 MVT::ValueType XType = N0.getValueType(); 4936 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 4937 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4938 TLI.getShiftAmountTy())); 4939 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 4940 AddToWorkList(Shift.Val); 4941 AddToWorkList(Add.Val); 4942 return DAG.getNode(ISD::XOR, XType, Add, Shift); 4943 } 4944 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X -> 4945 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 4946 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT && 4947 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) { 4948 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 4949 MVT::ValueType XType = N0.getValueType(); 4950 if (SubC->isNullValue() && MVT::isInteger(XType)) { 4951 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 4952 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4953 TLI.getShiftAmountTy())); 4954 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 4955 AddToWorkList(Shift.Val); 4956 AddToWorkList(Add.Val); 4957 return DAG.getNode(ISD::XOR, XType, Add, Shift); 4958 } 4959 } 4960 } 4961 4962 return SDOperand(); 4963} 4964 4965/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 4966SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0, 4967 SDOperand N1, ISD::CondCode Cond, 4968 bool foldBooleans) { 4969 TargetLowering::DAGCombinerInfo 4970 DagCombineInfo(DAG, !AfterLegalize, false, this); 4971 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo); 4972} 4973 4974/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 4975/// return a DAG expression to select that will generate the same value by 4976/// multiplying by a magic number. See: 4977/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 4978SDOperand DAGCombiner::BuildSDIV(SDNode *N) { 4979 std::vector<SDNode*> Built; 4980 SDOperand S = TLI.BuildSDIV(N, DAG, &Built); 4981 4982 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 4983 ii != ee; ++ii) 4984 AddToWorkList(*ii); 4985 return S; 4986} 4987 4988/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 4989/// return a DAG expression to select that will generate the same value by 4990/// multiplying by a magic number. See: 4991/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 4992SDOperand DAGCombiner::BuildUDIV(SDNode *N) { 4993 std::vector<SDNode*> Built; 4994 SDOperand S = TLI.BuildUDIV(N, DAG, &Built); 4995 4996 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 4997 ii != ee; ++ii) 4998 AddToWorkList(*ii); 4999 return S; 5000} 5001 5002/// FindBaseOffset - Return true if base is known not to alias with anything 5003/// but itself. Provides base object and offset as results. 5004static bool FindBaseOffset(SDOperand Ptr, SDOperand &Base, int64_t &Offset) { 5005 // Assume it is a primitive operation. 5006 Base = Ptr; Offset = 0; 5007 5008 // If it's an adding a simple constant then integrate the offset. 5009 if (Base.getOpcode() == ISD::ADD) { 5010 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 5011 Base = Base.getOperand(0); 5012 Offset += C->getValue(); 5013 } 5014 } 5015 5016 // If it's any of the following then it can't alias with anything but itself. 5017 return isa<FrameIndexSDNode>(Base) || 5018 isa<ConstantPoolSDNode>(Base) || 5019 isa<GlobalAddressSDNode>(Base); 5020} 5021 5022/// isAlias - Return true if there is any possibility that the two addresses 5023/// overlap. 5024bool DAGCombiner::isAlias(SDOperand Ptr1, int64_t Size1, 5025 const Value *SrcValue1, int SrcValueOffset1, 5026 SDOperand Ptr2, int64_t Size2, 5027 const Value *SrcValue2, int SrcValueOffset2) 5028{ 5029 // If they are the same then they must be aliases. 5030 if (Ptr1 == Ptr2) return true; 5031 5032 // Gather base node and offset information. 5033 SDOperand Base1, Base2; 5034 int64_t Offset1, Offset2; 5035 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1); 5036 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2); 5037 5038 // If they have a same base address then... 5039 if (Base1 == Base2) { 5040 // Check to see if the addresses overlap. 5041 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 5042 } 5043 5044 // If we know both bases then they can't alias. 5045 if (KnownBase1 && KnownBase2) return false; 5046 5047 if (CombinerGlobalAA) { 5048 // Use alias analysis information. 5049 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 5050 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 5051 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 5052 AliasAnalysis::AliasResult AAResult = 5053 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2); 5054 if (AAResult == AliasAnalysis::NoAlias) 5055 return false; 5056 } 5057 5058 // Otherwise we have to assume they alias. 5059 return true; 5060} 5061 5062/// FindAliasInfo - Extracts the relevant alias information from the memory 5063/// node. Returns true if the operand was a load. 5064bool DAGCombiner::FindAliasInfo(SDNode *N, 5065 SDOperand &Ptr, int64_t &Size, 5066 const Value *&SrcValue, int &SrcValueOffset) { 5067 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 5068 Ptr = LD->getBasePtr(); 5069 Size = MVT::getSizeInBits(LD->getLoadedVT()) >> 3; 5070 SrcValue = LD->getSrcValue(); 5071 SrcValueOffset = LD->getSrcValueOffset(); 5072 return true; 5073 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 5074 Ptr = ST->getBasePtr(); 5075 Size = MVT::getSizeInBits(ST->getStoredVT()) >> 3; 5076 SrcValue = ST->getSrcValue(); 5077 SrcValueOffset = ST->getSrcValueOffset(); 5078 } else { 5079 assert(0 && "FindAliasInfo expected a memory operand"); 5080 } 5081 5082 return false; 5083} 5084 5085/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 5086/// looking for aliasing nodes and adding them to the Aliases vector. 5087void DAGCombiner::GatherAllAliases(SDNode *N, SDOperand OriginalChain, 5088 SmallVector<SDOperand, 8> &Aliases) { 5089 SmallVector<SDOperand, 8> Chains; // List of chains to visit. 5090 std::set<SDNode *> Visited; // Visited node set. 5091 5092 // Get alias information for node. 5093 SDOperand Ptr; 5094 int64_t Size; 5095 const Value *SrcValue; 5096 int SrcValueOffset; 5097 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset); 5098 5099 // Starting off. 5100 Chains.push_back(OriginalChain); 5101 5102 // Look at each chain and determine if it is an alias. If so, add it to the 5103 // aliases list. If not, then continue up the chain looking for the next 5104 // candidate. 5105 while (!Chains.empty()) { 5106 SDOperand Chain = Chains.back(); 5107 Chains.pop_back(); 5108 5109 // Don't bother if we've been before. 5110 if (Visited.find(Chain.Val) != Visited.end()) continue; 5111 Visited.insert(Chain.Val); 5112 5113 switch (Chain.getOpcode()) { 5114 case ISD::EntryToken: 5115 // Entry token is ideal chain operand, but handled in FindBetterChain. 5116 break; 5117 5118 case ISD::LOAD: 5119 case ISD::STORE: { 5120 // Get alias information for Chain. 5121 SDOperand OpPtr; 5122 int64_t OpSize; 5123 const Value *OpSrcValue; 5124 int OpSrcValueOffset; 5125 bool IsOpLoad = FindAliasInfo(Chain.Val, OpPtr, OpSize, 5126 OpSrcValue, OpSrcValueOffset); 5127 5128 // If chain is alias then stop here. 5129 if (!(IsLoad && IsOpLoad) && 5130 isAlias(Ptr, Size, SrcValue, SrcValueOffset, 5131 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) { 5132 Aliases.push_back(Chain); 5133 } else { 5134 // Look further up the chain. 5135 Chains.push_back(Chain.getOperand(0)); 5136 // Clean up old chain. 5137 AddToWorkList(Chain.Val); 5138 } 5139 break; 5140 } 5141 5142 case ISD::TokenFactor: 5143 // We have to check each of the operands of the token factor, so we queue 5144 // then up. Adding the operands to the queue (stack) in reverse order 5145 // maintains the original order and increases the likelihood that getNode 5146 // will find a matching token factor (CSE.) 5147 for (unsigned n = Chain.getNumOperands(); n;) 5148 Chains.push_back(Chain.getOperand(--n)); 5149 // Eliminate the token factor if we can. 5150 AddToWorkList(Chain.Val); 5151 break; 5152 5153 default: 5154 // For all other instructions we will just have to take what we can get. 5155 Aliases.push_back(Chain); 5156 break; 5157 } 5158 } 5159} 5160 5161/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 5162/// for a better chain (aliasing node.) 5163SDOperand DAGCombiner::FindBetterChain(SDNode *N, SDOperand OldChain) { 5164 SmallVector<SDOperand, 8> Aliases; // Ops for replacing token factor. 5165 5166 // Accumulate all the aliases to this node. 5167 GatherAllAliases(N, OldChain, Aliases); 5168 5169 if (Aliases.size() == 0) { 5170 // If no operands then chain to entry token. 5171 return DAG.getEntryNode(); 5172 } else if (Aliases.size() == 1) { 5173 // If a single operand then chain to it. We don't need to revisit it. 5174 return Aliases[0]; 5175 } 5176 5177 // Construct a custom tailored token factor. 5178 SDOperand NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 5179 &Aliases[0], Aliases.size()); 5180 5181 // Make sure the old chain gets cleaned up. 5182 if (NewChain != OldChain) AddToWorkList(OldChain.Val); 5183 5184 return NewChain; 5185} 5186 5187// SelectionDAG::Combine - This is the entry point for the file. 5188// 5189void SelectionDAG::Combine(bool RunningAfterLegalize, AliasAnalysis &AA) { 5190 if (!RunningAfterLegalize && ViewDAGCombine1) 5191 viewGraph(); 5192 if (RunningAfterLegalize && ViewDAGCombine2) 5193 viewGraph(); 5194 /// run - This is the main entry point to this class. 5195 /// 5196 DAGCombiner(*this, AA).Run(RunningAfterLegalize); 5197} 5198