DAGCombiner.cpp revision d629d80a80bfd6094563000bc82ed37b42acfffa
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// This pass is not a substitute for the LLVM IR instcombine pass. This pass is 14// primarily intended to handle simplification opportunities that are implicit 15// in the LLVM IR and exposed by the various codegen lowering phases. 16// 17//===----------------------------------------------------------------------===// 18 19#define DEBUG_TYPE "dagcombine" 20#include "llvm/CodeGen/SelectionDAG.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/LLVMContext.h" 23#include "llvm/CodeGen/MachineFunction.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/PseudoSourceValue.h" 26#include "llvm/Analysis/AliasAnalysis.h" 27#include "llvm/Target/TargetData.h" 28#include "llvm/Target/TargetFrameInfo.h" 29#include "llvm/Target/TargetLowering.h" 30#include "llvm/Target/TargetMachine.h" 31#include "llvm/Target/TargetOptions.h" 32#include "llvm/ADT/SmallPtrSet.h" 33#include "llvm/ADT/Statistic.h" 34#include "llvm/Support/CommandLine.h" 35#include "llvm/Support/Debug.h" 36#include "llvm/Support/ErrorHandling.h" 37#include "llvm/Support/MathExtras.h" 38#include "llvm/Support/raw_ostream.h" 39#include <algorithm> 40using namespace llvm; 41 42STATISTIC(NodesCombined , "Number of dag nodes combined"); 43STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 44STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 45STATISTIC(OpsNarrowed , "Number of load/op/store narrowed"); 46 47namespace { 48 static cl::opt<bool> 49 CombinerAA("combiner-alias-analysis", cl::Hidden, 50 cl::desc("Turn on alias analysis during testing")); 51 52 static cl::opt<bool> 53 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 54 cl::desc("Include global information in alias analysis")); 55 56//------------------------------ DAGCombiner ---------------------------------// 57 58 class DAGCombiner { 59 SelectionDAG &DAG; 60 const TargetLowering &TLI; 61 CombineLevel Level; 62 CodeGenOpt::Level OptLevel; 63 bool LegalOperations; 64 bool LegalTypes; 65 66 // Worklist of all of the nodes that need to be simplified. 67 std::vector<SDNode*> WorkList; 68 69 // AA - Used for DAG load/store alias analysis. 70 AliasAnalysis &AA; 71 72 /// AddUsersToWorkList - When an instruction is simplified, add all users of 73 /// the instruction to the work lists because they might get more simplified 74 /// now. 75 /// 76 void AddUsersToWorkList(SDNode *N) { 77 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 78 UI != UE; ++UI) 79 AddToWorkList(*UI); 80 } 81 82 /// visit - call the node-specific routine that knows how to fold each 83 /// particular type of node. 84 SDValue visit(SDNode *N); 85 86 public: 87 /// AddToWorkList - Add to the work list making sure it's instance is at the 88 /// the back (next to be processed.) 89 void AddToWorkList(SDNode *N) { 90 removeFromWorkList(N); 91 WorkList.push_back(N); 92 } 93 94 /// removeFromWorkList - remove all instances of N from the worklist. 95 /// 96 void removeFromWorkList(SDNode *N) { 97 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 98 WorkList.end()); 99 } 100 101 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 102 bool AddTo = true); 103 104 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 105 return CombineTo(N, &Res, 1, AddTo); 106 } 107 108 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 109 bool AddTo = true) { 110 SDValue To[] = { Res0, Res1 }; 111 return CombineTo(N, To, 2, AddTo); 112 } 113 114 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO); 115 116 private: 117 118 /// SimplifyDemandedBits - Check the specified integer node value to see if 119 /// it can be simplified or if things it uses can be simplified by bit 120 /// propagation. If so, return true. 121 bool SimplifyDemandedBits(SDValue Op) { 122 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits(); 123 APInt Demanded = APInt::getAllOnesValue(BitWidth); 124 return SimplifyDemandedBits(Op, Demanded); 125 } 126 127 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 128 129 bool CombineToPreIndexedLoadStore(SDNode *N); 130 bool CombineToPostIndexedLoadStore(SDNode *N); 131 132 133 /// combine - call the node-specific routine that knows how to fold each 134 /// particular type of node. If that doesn't do anything, try the 135 /// target-specific DAG combines. 136 SDValue combine(SDNode *N); 137 138 // Visitation implementation - Implement dag node combining for different 139 // node types. The semantics are as follows: 140 // Return Value: 141 // SDValue.getNode() == 0 - No change was made 142 // SDValue.getNode() == N - N was replaced, is dead and has been handled. 143 // otherwise - N should be replaced by the returned Operand. 144 // 145 SDValue visitTokenFactor(SDNode *N); 146 SDValue visitMERGE_VALUES(SDNode *N); 147 SDValue visitADD(SDNode *N); 148 SDValue visitSUB(SDNode *N); 149 SDValue visitADDC(SDNode *N); 150 SDValue visitADDE(SDNode *N); 151 SDValue visitMUL(SDNode *N); 152 SDValue visitSDIV(SDNode *N); 153 SDValue visitUDIV(SDNode *N); 154 SDValue visitSREM(SDNode *N); 155 SDValue visitUREM(SDNode *N); 156 SDValue visitMULHU(SDNode *N); 157 SDValue visitMULHS(SDNode *N); 158 SDValue visitSMUL_LOHI(SDNode *N); 159 SDValue visitUMUL_LOHI(SDNode *N); 160 SDValue visitSDIVREM(SDNode *N); 161 SDValue visitUDIVREM(SDNode *N); 162 SDValue visitAND(SDNode *N); 163 SDValue visitOR(SDNode *N); 164 SDValue visitXOR(SDNode *N); 165 SDValue SimplifyVBinOp(SDNode *N); 166 SDValue visitSHL(SDNode *N); 167 SDValue visitSRA(SDNode *N); 168 SDValue visitSRL(SDNode *N); 169 SDValue visitCTLZ(SDNode *N); 170 SDValue visitCTTZ(SDNode *N); 171 SDValue visitCTPOP(SDNode *N); 172 SDValue visitSELECT(SDNode *N); 173 SDValue visitSELECT_CC(SDNode *N); 174 SDValue visitSETCC(SDNode *N); 175 SDValue visitSIGN_EXTEND(SDNode *N); 176 SDValue visitZERO_EXTEND(SDNode *N); 177 SDValue visitANY_EXTEND(SDNode *N); 178 SDValue visitSIGN_EXTEND_INREG(SDNode *N); 179 SDValue visitTRUNCATE(SDNode *N); 180 SDValue visitBIT_CONVERT(SDNode *N); 181 SDValue visitBUILD_PAIR(SDNode *N); 182 SDValue visitFADD(SDNode *N); 183 SDValue visitFSUB(SDNode *N); 184 SDValue visitFMUL(SDNode *N); 185 SDValue visitFDIV(SDNode *N); 186 SDValue visitFREM(SDNode *N); 187 SDValue visitFCOPYSIGN(SDNode *N); 188 SDValue visitSINT_TO_FP(SDNode *N); 189 SDValue visitUINT_TO_FP(SDNode *N); 190 SDValue visitFP_TO_SINT(SDNode *N); 191 SDValue visitFP_TO_UINT(SDNode *N); 192 SDValue visitFP_ROUND(SDNode *N); 193 SDValue visitFP_ROUND_INREG(SDNode *N); 194 SDValue visitFP_EXTEND(SDNode *N); 195 SDValue visitFNEG(SDNode *N); 196 SDValue visitFABS(SDNode *N); 197 SDValue visitBRCOND(SDNode *N); 198 SDValue visitBR_CC(SDNode *N); 199 SDValue visitLOAD(SDNode *N); 200 SDValue visitSTORE(SDNode *N); 201 SDValue visitINSERT_VECTOR_ELT(SDNode *N); 202 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 203 SDValue visitBUILD_VECTOR(SDNode *N); 204 SDValue visitCONCAT_VECTORS(SDNode *N); 205 SDValue visitVECTOR_SHUFFLE(SDNode *N); 206 207 SDValue XformToShuffleWithZero(SDNode *N); 208 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS); 209 210 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 211 212 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 213 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 214 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2); 215 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2, 216 SDValue N3, ISD::CondCode CC, 217 bool NotExtCompare = false); 218 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 219 DebugLoc DL, bool foldBooleans = true); 220 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 221 unsigned HiOp); 222 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT); 223 SDValue ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, EVT); 224 SDValue BuildSDIV(SDNode *N); 225 SDValue BuildUDIV(SDNode *N); 226 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL); 227 SDValue ReduceLoadWidth(SDNode *N); 228 SDValue ReduceLoadOpStoreWidth(SDNode *N); 229 230 SDValue GetDemandedBits(SDValue V, const APInt &Mask); 231 232 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 233 /// looking for aliasing nodes and adding them to the Aliases vector. 234 void GatherAllAliases(SDNode *N, SDValue OriginalChain, 235 SmallVector<SDValue, 8> &Aliases); 236 237 /// isAlias - Return true if there is any possibility that the two addresses 238 /// overlap. 239 bool isAlias(SDValue Ptr1, int64_t Size1, 240 const Value *SrcValue1, int SrcValueOffset1, 241 unsigned SrcValueAlign1, 242 SDValue Ptr2, int64_t Size2, 243 const Value *SrcValue2, int SrcValueOffset2, 244 unsigned SrcValueAlign2) const; 245 246 /// FindAliasInfo - Extracts the relevant alias information from the memory 247 /// node. Returns true if the operand was a load. 248 bool FindAliasInfo(SDNode *N, 249 SDValue &Ptr, int64_t &Size, 250 const Value *&SrcValue, int &SrcValueOffset, 251 unsigned &SrcValueAlignment) const; 252 253 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 254 /// looking for a better chain (aliasing node.) 255 SDValue FindBetterChain(SDNode *N, SDValue Chain); 256 257 /// getShiftAmountTy - Returns a type large enough to hold any valid 258 /// shift amount - before type legalization these can be huge. 259 EVT getShiftAmountTy() { 260 return LegalTypes ? TLI.getShiftAmountTy() : TLI.getPointerTy(); 261 } 262 263public: 264 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL) 265 : DAG(D), 266 TLI(D.getTargetLoweringInfo()), 267 Level(Unrestricted), 268 OptLevel(OL), 269 LegalOperations(false), 270 LegalTypes(false), 271 AA(A) {} 272 273 /// Run - runs the dag combiner on all nodes in the work list 274 void Run(CombineLevel AtLevel); 275 }; 276} 277 278 279namespace { 280/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 281/// nodes from the worklist. 282class WorkListRemover : public SelectionDAG::DAGUpdateListener { 283 DAGCombiner &DC; 284public: 285 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {} 286 287 virtual void NodeDeleted(SDNode *N, SDNode *E) { 288 DC.removeFromWorkList(N); 289 } 290 291 virtual void NodeUpdated(SDNode *N) { 292 // Ignore updates. 293 } 294}; 295} 296 297//===----------------------------------------------------------------------===// 298// TargetLowering::DAGCombinerInfo implementation 299//===----------------------------------------------------------------------===// 300 301void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 302 ((DAGCombiner*)DC)->AddToWorkList(N); 303} 304 305SDValue TargetLowering::DAGCombinerInfo:: 306CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) { 307 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo); 308} 309 310SDValue TargetLowering::DAGCombinerInfo:: 311CombineTo(SDNode *N, SDValue Res, bool AddTo) { 312 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo); 313} 314 315 316SDValue TargetLowering::DAGCombinerInfo:: 317CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) { 318 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo); 319} 320 321void TargetLowering::DAGCombinerInfo:: 322CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 323 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO); 324} 325 326//===----------------------------------------------------------------------===// 327// Helper Functions 328//===----------------------------------------------------------------------===// 329 330/// isNegatibleForFree - Return 1 if we can compute the negated form of the 331/// specified expression for the same cost as the expression itself, or 2 if we 332/// can compute the negated form more cheaply than the expression itself. 333static char isNegatibleForFree(SDValue Op, bool LegalOperations, 334 unsigned Depth = 0) { 335 // No compile time optimizations on this type. 336 if (Op.getValueType() == MVT::ppcf128) 337 return 0; 338 339 // fneg is removable even if it has multiple uses. 340 if (Op.getOpcode() == ISD::FNEG) return 2; 341 342 // Don't allow anything with multiple uses. 343 if (!Op.hasOneUse()) return 0; 344 345 // Don't recurse exponentially. 346 if (Depth > 6) return 0; 347 348 switch (Op.getOpcode()) { 349 default: return false; 350 case ISD::ConstantFP: 351 // Don't invert constant FP values after legalize. The negated constant 352 // isn't necessarily legal. 353 return LegalOperations ? 0 : 1; 354 case ISD::FADD: 355 // FIXME: determine better conditions for this xform. 356 if (!UnsafeFPMath) return 0; 357 358 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B) 359 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 360 return V; 361 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 362 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 363 case ISD::FSUB: 364 // We can't turn -(A-B) into B-A when we honor signed zeros. 365 if (!UnsafeFPMath) return 0; 366 367 // fold (fneg (fsub A, B)) -> (fsub B, A) 368 return 1; 369 370 case ISD::FMUL: 371 case ISD::FDIV: 372 if (HonorSignDependentRoundingFPMath()) return 0; 373 374 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y)) 375 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 376 return V; 377 378 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 379 380 case ISD::FP_EXTEND: 381 case ISD::FP_ROUND: 382 case ISD::FSIN: 383 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1); 384 } 385} 386 387/// GetNegatedExpression - If isNegatibleForFree returns true, this function 388/// returns the newly negated expression. 389static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 390 bool LegalOperations, unsigned Depth = 0) { 391 // fneg is removable even if it has multiple uses. 392 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 393 394 // Don't allow anything with multiple uses. 395 assert(Op.hasOneUse() && "Unknown reuse!"); 396 397 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 398 switch (Op.getOpcode()) { 399 default: llvm_unreachable("Unknown code"); 400 case ISD::ConstantFP: { 401 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 402 V.changeSign(); 403 return DAG.getConstantFP(V, Op.getValueType()); 404 } 405 case ISD::FADD: 406 // FIXME: determine better conditions for this xform. 407 assert(UnsafeFPMath); 408 409 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 410 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 411 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 412 GetNegatedExpression(Op.getOperand(0), DAG, 413 LegalOperations, Depth+1), 414 Op.getOperand(1)); 415 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 416 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 417 GetNegatedExpression(Op.getOperand(1), DAG, 418 LegalOperations, Depth+1), 419 Op.getOperand(0)); 420 case ISD::FSUB: 421 // We can't turn -(A-B) into B-A when we honor signed zeros. 422 assert(UnsafeFPMath); 423 424 // fold (fneg (fsub 0, B)) -> B 425 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 426 if (N0CFP->getValueAPF().isZero()) 427 return Op.getOperand(1); 428 429 // fold (fneg (fsub A, B)) -> (fsub B, A) 430 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 431 Op.getOperand(1), Op.getOperand(0)); 432 433 case ISD::FMUL: 434 case ISD::FDIV: 435 assert(!HonorSignDependentRoundingFPMath()); 436 437 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) 438 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 439 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 440 GetNegatedExpression(Op.getOperand(0), DAG, 441 LegalOperations, Depth+1), 442 Op.getOperand(1)); 443 444 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y)) 445 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 446 Op.getOperand(0), 447 GetNegatedExpression(Op.getOperand(1), DAG, 448 LegalOperations, Depth+1)); 449 450 case ISD::FP_EXTEND: 451 case ISD::FSIN: 452 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 453 GetNegatedExpression(Op.getOperand(0), DAG, 454 LegalOperations, Depth+1)); 455 case ISD::FP_ROUND: 456 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(), 457 GetNegatedExpression(Op.getOperand(0), DAG, 458 LegalOperations, Depth+1), 459 Op.getOperand(1)); 460 } 461} 462 463 464// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 465// that selects between the values 1 and 0, making it equivalent to a setcc. 466// Also, set the incoming LHS, RHS, and CC references to the appropriate 467// nodes based on the type of node we are checking. This simplifies life a 468// bit for the callers. 469static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 470 SDValue &CC) { 471 if (N.getOpcode() == ISD::SETCC) { 472 LHS = N.getOperand(0); 473 RHS = N.getOperand(1); 474 CC = N.getOperand(2); 475 return true; 476 } 477 if (N.getOpcode() == ISD::SELECT_CC && 478 N.getOperand(2).getOpcode() == ISD::Constant && 479 N.getOperand(3).getOpcode() == ISD::Constant && 480 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 481 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 482 LHS = N.getOperand(0); 483 RHS = N.getOperand(1); 484 CC = N.getOperand(4); 485 return true; 486 } 487 return false; 488} 489 490// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 491// one use. If this is true, it allows the users to invert the operation for 492// free when it is profitable to do so. 493static bool isOneUseSetCC(SDValue N) { 494 SDValue N0, N1, N2; 495 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 496 return true; 497 return false; 498} 499 500SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL, 501 SDValue N0, SDValue N1) { 502 EVT VT = N0.getValueType(); 503 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 504 if (isa<ConstantSDNode>(N1)) { 505 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 506 SDValue OpNode = 507 DAG.FoldConstantArithmetic(Opc, VT, 508 cast<ConstantSDNode>(N0.getOperand(1)), 509 cast<ConstantSDNode>(N1)); 510 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode); 511 } else if (N0.hasOneUse()) { 512 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 513 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 514 N0.getOperand(0), N1); 515 AddToWorkList(OpNode.getNode()); 516 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1)); 517 } 518 } 519 520 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 521 if (isa<ConstantSDNode>(N0)) { 522 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 523 SDValue OpNode = 524 DAG.FoldConstantArithmetic(Opc, VT, 525 cast<ConstantSDNode>(N1.getOperand(1)), 526 cast<ConstantSDNode>(N0)); 527 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode); 528 } else if (N1.hasOneUse()) { 529 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 530 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 531 N1.getOperand(0), N0); 532 AddToWorkList(OpNode.getNode()); 533 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1)); 534 } 535 } 536 537 return SDValue(); 538} 539 540SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 541 bool AddTo) { 542 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 543 ++NodesCombined; 544 DEBUG(errs() << "\nReplacing.1 "; 545 N->dump(&DAG); 546 errs() << "\nWith: "; 547 To[0].getNode()->dump(&DAG); 548 errs() << " and " << NumTo-1 << " other values\n"; 549 for (unsigned i = 0, e = NumTo; i != e; ++i) 550 assert((!To[i].getNode() || 551 N->getValueType(i) == To[i].getValueType()) && 552 "Cannot combine value to value of different type!")); 553 WorkListRemover DeadNodes(*this); 554 DAG.ReplaceAllUsesWith(N, To, &DeadNodes); 555 556 if (AddTo) { 557 // Push the new nodes and any users onto the worklist 558 for (unsigned i = 0, e = NumTo; i != e; ++i) { 559 if (To[i].getNode()) { 560 AddToWorkList(To[i].getNode()); 561 AddUsersToWorkList(To[i].getNode()); 562 } 563 } 564 } 565 566 // Finally, if the node is now dead, remove it from the graph. The node 567 // may not be dead if the replacement process recursively simplified to 568 // something else needing this node. 569 if (N->use_empty()) { 570 // Nodes can be reintroduced into the worklist. Make sure we do not 571 // process a node that has been replaced. 572 removeFromWorkList(N); 573 574 // Finally, since the node is now dead, remove it from the graph. 575 DAG.DeleteNode(N); 576 } 577 return SDValue(N, 0); 578} 579 580void 581DAGCombiner::CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt & 582 TLO) { 583 // Replace all uses. If any nodes become isomorphic to other nodes and 584 // are deleted, make sure to remove them from our worklist. 585 WorkListRemover DeadNodes(*this); 586 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 587 588 // Push the new node and any (possibly new) users onto the worklist. 589 AddToWorkList(TLO.New.getNode()); 590 AddUsersToWorkList(TLO.New.getNode()); 591 592 // Finally, if the node is now dead, remove it from the graph. The node 593 // may not be dead if the replacement process recursively simplified to 594 // something else needing this node. 595 if (TLO.Old.getNode()->use_empty()) { 596 removeFromWorkList(TLO.Old.getNode()); 597 598 // If the operands of this node are only used by the node, they will now 599 // be dead. Make sure to visit them first to delete dead nodes early. 600 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i) 601 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse()) 602 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode()); 603 604 DAG.DeleteNode(TLO.Old.getNode()); 605 } 606} 607 608/// SimplifyDemandedBits - Check the specified integer node value to see if 609/// it can be simplified or if things it uses can be simplified by bit 610/// propagation. If so, return true. 611bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 612 TargetLowering::TargetLoweringOpt TLO(DAG); 613 APInt KnownZero, KnownOne; 614 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 615 return false; 616 617 // Revisit the node. 618 AddToWorkList(Op.getNode()); 619 620 // Replace the old value with the new one. 621 ++NodesCombined; 622 DEBUG(errs() << "\nReplacing.2 "; 623 TLO.Old.getNode()->dump(&DAG); 624 errs() << "\nWith: "; 625 TLO.New.getNode()->dump(&DAG); 626 errs() << '\n'); 627 628 CommitTargetLoweringOpt(TLO); 629 return true; 630} 631 632//===----------------------------------------------------------------------===// 633// Main DAG Combiner implementation 634//===----------------------------------------------------------------------===// 635 636void DAGCombiner::Run(CombineLevel AtLevel) { 637 // set the instance variables, so that the various visit routines may use it. 638 Level = AtLevel; 639 LegalOperations = Level >= NoIllegalOperations; 640 LegalTypes = Level >= NoIllegalTypes; 641 642 // Add all the dag nodes to the worklist. 643 WorkList.reserve(DAG.allnodes_size()); 644 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 645 E = DAG.allnodes_end(); I != E; ++I) 646 WorkList.push_back(I); 647 648 // Create a dummy node (which is not added to allnodes), that adds a reference 649 // to the root node, preventing it from being deleted, and tracking any 650 // changes of the root. 651 HandleSDNode Dummy(DAG.getRoot()); 652 653 // The root of the dag may dangle to deleted nodes until the dag combiner is 654 // done. Set it to null to avoid confusion. 655 DAG.setRoot(SDValue()); 656 657 // while the worklist isn't empty, inspect the node on the end of it and 658 // try and combine it. 659 while (!WorkList.empty()) { 660 SDNode *N = WorkList.back(); 661 WorkList.pop_back(); 662 663 // If N has no uses, it is dead. Make sure to revisit all N's operands once 664 // N is deleted from the DAG, since they too may now be dead or may have a 665 // reduced number of uses, allowing other xforms. 666 if (N->use_empty() && N != &Dummy) { 667 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 668 AddToWorkList(N->getOperand(i).getNode()); 669 670 DAG.DeleteNode(N); 671 continue; 672 } 673 674 SDValue RV = combine(N); 675 676 if (RV.getNode() == 0) 677 continue; 678 679 ++NodesCombined; 680 681 // If we get back the same node we passed in, rather than a new node or 682 // zero, we know that the node must have defined multiple values and 683 // CombineTo was used. Since CombineTo takes care of the worklist 684 // mechanics for us, we have no work to do in this case. 685 if (RV.getNode() == N) 686 continue; 687 688 assert(N->getOpcode() != ISD::DELETED_NODE && 689 RV.getNode()->getOpcode() != ISD::DELETED_NODE && 690 "Node was deleted but visit returned new node!"); 691 692 DEBUG(errs() << "\nReplacing.3 "; 693 N->dump(&DAG); 694 errs() << "\nWith: "; 695 RV.getNode()->dump(&DAG); 696 errs() << '\n'); 697 WorkListRemover DeadNodes(*this); 698 if (N->getNumValues() == RV.getNode()->getNumValues()) 699 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes); 700 else { 701 assert(N->getValueType(0) == RV.getValueType() && 702 N->getNumValues() == 1 && "Type mismatch"); 703 SDValue OpV = RV; 704 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes); 705 } 706 707 // Push the new node and any users onto the worklist 708 AddToWorkList(RV.getNode()); 709 AddUsersToWorkList(RV.getNode()); 710 711 // Add any uses of the old node to the worklist in case this node is the 712 // last one that uses them. They may become dead after this node is 713 // deleted. 714 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 715 AddToWorkList(N->getOperand(i).getNode()); 716 717 // Finally, if the node is now dead, remove it from the graph. The node 718 // may not be dead if the replacement process recursively simplified to 719 // something else needing this node. 720 if (N->use_empty()) { 721 // Nodes can be reintroduced into the worklist. Make sure we do not 722 // process a node that has been replaced. 723 removeFromWorkList(N); 724 725 // Finally, since the node is now dead, remove it from the graph. 726 DAG.DeleteNode(N); 727 } 728 } 729 730 // If the root changed (e.g. it was a dead load, update the root). 731 DAG.setRoot(Dummy.getValue()); 732} 733 734SDValue DAGCombiner::visit(SDNode *N) { 735 switch(N->getOpcode()) { 736 default: break; 737 case ISD::TokenFactor: return visitTokenFactor(N); 738 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 739 case ISD::ADD: return visitADD(N); 740 case ISD::SUB: return visitSUB(N); 741 case ISD::ADDC: return visitADDC(N); 742 case ISD::ADDE: return visitADDE(N); 743 case ISD::MUL: return visitMUL(N); 744 case ISD::SDIV: return visitSDIV(N); 745 case ISD::UDIV: return visitUDIV(N); 746 case ISD::SREM: return visitSREM(N); 747 case ISD::UREM: return visitUREM(N); 748 case ISD::MULHU: return visitMULHU(N); 749 case ISD::MULHS: return visitMULHS(N); 750 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 751 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 752 case ISD::SDIVREM: return visitSDIVREM(N); 753 case ISD::UDIVREM: return visitUDIVREM(N); 754 case ISD::AND: return visitAND(N); 755 case ISD::OR: return visitOR(N); 756 case ISD::XOR: return visitXOR(N); 757 case ISD::SHL: return visitSHL(N); 758 case ISD::SRA: return visitSRA(N); 759 case ISD::SRL: return visitSRL(N); 760 case ISD::CTLZ: return visitCTLZ(N); 761 case ISD::CTTZ: return visitCTTZ(N); 762 case ISD::CTPOP: return visitCTPOP(N); 763 case ISD::SELECT: return visitSELECT(N); 764 case ISD::SELECT_CC: return visitSELECT_CC(N); 765 case ISD::SETCC: return visitSETCC(N); 766 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 767 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 768 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 769 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 770 case ISD::TRUNCATE: return visitTRUNCATE(N); 771 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 772 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 773 case ISD::FADD: return visitFADD(N); 774 case ISD::FSUB: return visitFSUB(N); 775 case ISD::FMUL: return visitFMUL(N); 776 case ISD::FDIV: return visitFDIV(N); 777 case ISD::FREM: return visitFREM(N); 778 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 779 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 780 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 781 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 782 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 783 case ISD::FP_ROUND: return visitFP_ROUND(N); 784 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 785 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 786 case ISD::FNEG: return visitFNEG(N); 787 case ISD::FABS: return visitFABS(N); 788 case ISD::BRCOND: return visitBRCOND(N); 789 case ISD::BR_CC: return visitBR_CC(N); 790 case ISD::LOAD: return visitLOAD(N); 791 case ISD::STORE: return visitSTORE(N); 792 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 793 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 794 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 795 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 796 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 797 } 798 return SDValue(); 799} 800 801SDValue DAGCombiner::combine(SDNode *N) { 802 SDValue RV = visit(N); 803 804 // If nothing happened, try a target-specific DAG combine. 805 if (RV.getNode() == 0) { 806 assert(N->getOpcode() != ISD::DELETED_NODE && 807 "Node was deleted but visit returned NULL!"); 808 809 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 810 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 811 812 // Expose the DAG combiner to the target combiner impls. 813 TargetLowering::DAGCombinerInfo 814 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 815 816 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 817 } 818 } 819 820 // If N is a commutative binary node, try commuting it to enable more 821 // sdisel CSE. 822 if (RV.getNode() == 0 && 823 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 824 N->getNumValues() == 1) { 825 SDValue N0 = N->getOperand(0); 826 SDValue N1 = N->getOperand(1); 827 828 // Constant operands are canonicalized to RHS. 829 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 830 SDValue Ops[] = { N1, N0 }; 831 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 832 Ops, 2); 833 if (CSENode) 834 return SDValue(CSENode, 0); 835 } 836 } 837 838 return RV; 839} 840 841/// getInputChainForNode - Given a node, return its input chain if it has one, 842/// otherwise return a null sd operand. 843static SDValue getInputChainForNode(SDNode *N) { 844 if (unsigned NumOps = N->getNumOperands()) { 845 if (N->getOperand(0).getValueType() == MVT::Other) 846 return N->getOperand(0); 847 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 848 return N->getOperand(NumOps-1); 849 for (unsigned i = 1; i < NumOps-1; ++i) 850 if (N->getOperand(i).getValueType() == MVT::Other) 851 return N->getOperand(i); 852 } 853 return SDValue(); 854} 855 856SDValue DAGCombiner::visitTokenFactor(SDNode *N) { 857 // If N has two operands, where one has an input chain equal to the other, 858 // the 'other' chain is redundant. 859 if (N->getNumOperands() == 2) { 860 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) 861 return N->getOperand(0); 862 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) 863 return N->getOperand(1); 864 } 865 866 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 867 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 868 SmallPtrSet<SDNode*, 16> SeenOps; 869 bool Changed = false; // If we should replace this token factor. 870 871 // Start out with this token factor. 872 TFs.push_back(N); 873 874 // Iterate through token factors. The TFs grows when new token factors are 875 // encountered. 876 for (unsigned i = 0; i < TFs.size(); ++i) { 877 SDNode *TF = TFs[i]; 878 879 // Check each of the operands. 880 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 881 SDValue Op = TF->getOperand(i); 882 883 switch (Op.getOpcode()) { 884 case ISD::EntryToken: 885 // Entry tokens don't need to be added to the list. They are 886 // rededundant. 887 Changed = true; 888 break; 889 890 case ISD::TokenFactor: 891 if (Op.hasOneUse() && 892 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { 893 // Queue up for processing. 894 TFs.push_back(Op.getNode()); 895 // Clean up in case the token factor is removed. 896 AddToWorkList(Op.getNode()); 897 Changed = true; 898 break; 899 } 900 // Fall thru 901 902 default: 903 // Only add if it isn't already in the list. 904 if (SeenOps.insert(Op.getNode())) 905 Ops.push_back(Op); 906 else 907 Changed = true; 908 break; 909 } 910 } 911 } 912 913 SDValue Result; 914 915 // If we've change things around then replace token factor. 916 if (Changed) { 917 if (Ops.empty()) { 918 // The entry token is the only possible outcome. 919 Result = DAG.getEntryNode(); 920 } else { 921 // New and improved token factor. 922 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 923 MVT::Other, &Ops[0], Ops.size()); 924 } 925 926 // Don't add users to work list. 927 return CombineTo(N, Result, false); 928 } 929 930 return Result; 931} 932 933/// MERGE_VALUES can always be eliminated. 934SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 935 WorkListRemover DeadNodes(*this); 936 // Replacing results may cause a different MERGE_VALUES to suddenly 937 // be CSE'd with N, and carry its uses with it. Iterate until no 938 // uses remain, to ensure that the node can be safely deleted. 939 do { 940 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 941 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i), 942 &DeadNodes); 943 } while (!N->use_empty()); 944 removeFromWorkList(N); 945 DAG.DeleteNode(N); 946 return SDValue(N, 0); // Return N so it doesn't get rechecked! 947} 948 949static 950SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1, 951 SelectionDAG &DAG) { 952 EVT VT = N0.getValueType(); 953 SDValue N00 = N0.getOperand(0); 954 SDValue N01 = N0.getOperand(1); 955 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 956 957 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && 958 isa<ConstantSDNode>(N00.getOperand(1))) { 959 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 960 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, 961 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT, 962 N00.getOperand(0), N01), 963 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT, 964 N00.getOperand(1), N01)); 965 return DAG.getNode(ISD::ADD, DL, VT, N0, N1); 966 } 967 968 return SDValue(); 969} 970 971SDValue DAGCombiner::visitADD(SDNode *N) { 972 SDValue N0 = N->getOperand(0); 973 SDValue N1 = N->getOperand(1); 974 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 975 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 976 EVT VT = N0.getValueType(); 977 978 // fold vector ops 979 if (VT.isVector()) { 980 SDValue FoldedVOp = SimplifyVBinOp(N); 981 if (FoldedVOp.getNode()) return FoldedVOp; 982 } 983 984 // fold (add x, undef) -> undef 985 if (N0.getOpcode() == ISD::UNDEF) 986 return N0; 987 if (N1.getOpcode() == ISD::UNDEF) 988 return N1; 989 // fold (add c1, c2) -> c1+c2 990 if (N0C && N1C) 991 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C); 992 // canonicalize constant to RHS 993 if (N0C && !N1C) 994 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0); 995 // fold (add x, 0) -> x 996 if (N1C && N1C->isNullValue()) 997 return N0; 998 // fold (add Sym, c) -> Sym+c 999 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1000 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C && 1001 GA->getOpcode() == ISD::GlobalAddress) 1002 return DAG.getGlobalAddress(GA->getGlobal(), VT, 1003 GA->getOffset() + 1004 (uint64_t)N1C->getSExtValue()); 1005 // fold ((c1-A)+c2) -> (c1+c2)-A 1006 if (N1C && N0.getOpcode() == ISD::SUB) 1007 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 1008 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1009 DAG.getConstant(N1C->getAPIntValue()+ 1010 N0C->getAPIntValue(), VT), 1011 N0.getOperand(1)); 1012 // reassociate add 1013 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1); 1014 if (RADD.getNode() != 0) 1015 return RADD; 1016 // fold ((0-A) + B) -> B-A 1017 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 1018 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 1019 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1)); 1020 // fold (A + (0-B)) -> A-B 1021 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1022 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 1023 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1)); 1024 // fold (A+(B-A)) -> B 1025 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 1026 return N1.getOperand(0); 1027 // fold ((B-A)+A) -> B 1028 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) 1029 return N0.getOperand(0); 1030 // fold (A+(B-(A+C))) to (B-C) 1031 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1032 N0 == N1.getOperand(1).getOperand(0)) 1033 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1034 N1.getOperand(1).getOperand(1)); 1035 // fold (A+(B-(C+A))) to (B-C) 1036 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1037 N0 == N1.getOperand(1).getOperand(1)) 1038 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1039 N1.getOperand(1).getOperand(0)); 1040 // fold (A+((B-A)+or-C)) to (B+or-C) 1041 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && 1042 N1.getOperand(0).getOpcode() == ISD::SUB && 1043 N0 == N1.getOperand(0).getOperand(1)) 1044 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT, 1045 N1.getOperand(0).getOperand(0), N1.getOperand(1)); 1046 1047 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant 1048 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) { 1049 SDValue N00 = N0.getOperand(0); 1050 SDValue N01 = N0.getOperand(1); 1051 SDValue N10 = N1.getOperand(0); 1052 SDValue N11 = N1.getOperand(1); 1053 1054 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10)) 1055 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1056 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10), 1057 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11)); 1058 } 1059 1060 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 1061 return SDValue(N, 0); 1062 1063 // fold (a+b) -> (a|b) iff a and b share no bits. 1064 if (VT.isInteger() && !VT.isVector()) { 1065 APInt LHSZero, LHSOne; 1066 APInt RHSZero, RHSOne; 1067 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 1068 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1069 1070 if (LHSZero.getBoolValue()) { 1071 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1072 1073 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1074 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1075 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1076 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1077 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1); 1078 } 1079 } 1080 1081 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1082 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1083 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG); 1084 if (Result.getNode()) return Result; 1085 } 1086 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1087 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG); 1088 if (Result.getNode()) return Result; 1089 } 1090 1091 return SDValue(); 1092} 1093 1094SDValue DAGCombiner::visitADDC(SDNode *N) { 1095 SDValue N0 = N->getOperand(0); 1096 SDValue N1 = N->getOperand(1); 1097 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1098 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1099 EVT VT = N0.getValueType(); 1100 1101 // If the flag result is dead, turn this into an ADD. 1102 if (N->hasNUsesOfValue(0, 1)) 1103 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0), 1104 DAG.getNode(ISD::CARRY_FALSE, 1105 N->getDebugLoc(), MVT::Flag)); 1106 1107 // canonicalize constant to RHS. 1108 if (N0C && !N1C) 1109 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1110 1111 // fold (addc x, 0) -> x + no carry out 1112 if (N1C && N1C->isNullValue()) 1113 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, 1114 N->getDebugLoc(), MVT::Flag)); 1115 1116 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1117 APInt LHSZero, LHSOne; 1118 APInt RHSZero, RHSOne; 1119 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 1120 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1121 1122 if (LHSZero.getBoolValue()) { 1123 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1124 1125 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1126 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1127 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1128 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1129 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1), 1130 DAG.getNode(ISD::CARRY_FALSE, 1131 N->getDebugLoc(), MVT::Flag)); 1132 } 1133 1134 return SDValue(); 1135} 1136 1137SDValue DAGCombiner::visitADDE(SDNode *N) { 1138 SDValue N0 = N->getOperand(0); 1139 SDValue N1 = N->getOperand(1); 1140 SDValue CarryIn = N->getOperand(2); 1141 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1142 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1143 1144 // canonicalize constant to RHS 1145 if (N0C && !N1C) 1146 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), 1147 N1, N0, CarryIn); 1148 1149 // fold (adde x, y, false) -> (addc x, y) 1150 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1151 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1152 1153 return SDValue(); 1154} 1155 1156SDValue DAGCombiner::visitSUB(SDNode *N) { 1157 SDValue N0 = N->getOperand(0); 1158 SDValue N1 = N->getOperand(1); 1159 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1160 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1161 EVT VT = N0.getValueType(); 1162 1163 // fold vector ops 1164 if (VT.isVector()) { 1165 SDValue FoldedVOp = SimplifyVBinOp(N); 1166 if (FoldedVOp.getNode()) return FoldedVOp; 1167 } 1168 1169 // fold (sub x, x) -> 0 1170 if (N0 == N1) 1171 return DAG.getConstant(0, N->getValueType(0)); 1172 // fold (sub c1, c2) -> c1-c2 1173 if (N0C && N1C) 1174 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C); 1175 // fold (sub x, c) -> (add x, -c) 1176 if (N1C) 1177 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, 1178 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1179 // fold (A+B)-A -> B 1180 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1181 return N0.getOperand(1); 1182 // fold (A+B)-B -> A 1183 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1184 return N0.getOperand(0); 1185 // fold ((A+(B+or-C))-B) -> A+or-C 1186 if (N0.getOpcode() == ISD::ADD && 1187 (N0.getOperand(1).getOpcode() == ISD::SUB || 1188 N0.getOperand(1).getOpcode() == ISD::ADD) && 1189 N0.getOperand(1).getOperand(0) == N1) 1190 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT, 1191 N0.getOperand(0), N0.getOperand(1).getOperand(1)); 1192 // fold ((A+(C+B))-B) -> A+C 1193 if (N0.getOpcode() == ISD::ADD && 1194 N0.getOperand(1).getOpcode() == ISD::ADD && 1195 N0.getOperand(1).getOperand(1) == N1) 1196 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1197 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1198 // fold ((A-(B-C))-C) -> A-B 1199 if (N0.getOpcode() == ISD::SUB && 1200 N0.getOperand(1).getOpcode() == ISD::SUB && 1201 N0.getOperand(1).getOperand(1) == N1) 1202 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1203 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1204 1205 // If either operand of a sub is undef, the result is undef 1206 if (N0.getOpcode() == ISD::UNDEF) 1207 return N0; 1208 if (N1.getOpcode() == ISD::UNDEF) 1209 return N1; 1210 1211 // If the relocation model supports it, consider symbol offsets. 1212 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1213 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) { 1214 // fold (sub Sym, c) -> Sym-c 1215 if (N1C && GA->getOpcode() == ISD::GlobalAddress) 1216 return DAG.getGlobalAddress(GA->getGlobal(), VT, 1217 GA->getOffset() - 1218 (uint64_t)N1C->getSExtValue()); 1219 // fold (sub Sym+c1, Sym+c2) -> c1-c2 1220 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1)) 1221 if (GA->getGlobal() == GB->getGlobal()) 1222 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(), 1223 VT); 1224 } 1225 1226 return SDValue(); 1227} 1228 1229SDValue DAGCombiner::visitMUL(SDNode *N) { 1230 SDValue N0 = N->getOperand(0); 1231 SDValue N1 = N->getOperand(1); 1232 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1233 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1234 EVT VT = N0.getValueType(); 1235 1236 // fold vector ops 1237 if (VT.isVector()) { 1238 SDValue FoldedVOp = SimplifyVBinOp(N); 1239 if (FoldedVOp.getNode()) return FoldedVOp; 1240 } 1241 1242 // fold (mul x, undef) -> 0 1243 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1244 return DAG.getConstant(0, VT); 1245 // fold (mul c1, c2) -> c1*c2 1246 if (N0C && N1C) 1247 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C); 1248 // canonicalize constant to RHS 1249 if (N0C && !N1C) 1250 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0); 1251 // fold (mul x, 0) -> 0 1252 if (N1C && N1C->isNullValue()) 1253 return N1; 1254 // fold (mul x, -1) -> 0-x 1255 if (N1C && N1C->isAllOnesValue()) 1256 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1257 DAG.getConstant(0, VT), N0); 1258 // fold (mul x, (1 << c)) -> x << c 1259 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1260 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1261 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1262 getShiftAmountTy())); 1263 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1264 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) { 1265 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2(); 1266 // FIXME: If the input is something that is easily negated (e.g. a 1267 // single-use add), we should put the negate there. 1268 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1269 DAG.getConstant(0, VT), 1270 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1271 DAG.getConstant(Log2Val, getShiftAmountTy()))); 1272 } 1273 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1274 if (N1C && N0.getOpcode() == ISD::SHL && 1275 isa<ConstantSDNode>(N0.getOperand(1))) { 1276 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1277 N1, N0.getOperand(1)); 1278 AddToWorkList(C3.getNode()); 1279 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1280 N0.getOperand(0), C3); 1281 } 1282 1283 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1284 // use. 1285 { 1286 SDValue Sh(0,0), Y(0,0); 1287 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1288 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1289 N0.getNode()->hasOneUse()) { 1290 Sh = N0; Y = N1; 1291 } else if (N1.getOpcode() == ISD::SHL && 1292 isa<ConstantSDNode>(N1.getOperand(1)) && 1293 N1.getNode()->hasOneUse()) { 1294 Sh = N1; Y = N0; 1295 } 1296 1297 if (Sh.getNode()) { 1298 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1299 Sh.getOperand(0), Y); 1300 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1301 Mul, Sh.getOperand(1)); 1302 } 1303 } 1304 1305 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1306 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 1307 isa<ConstantSDNode>(N0.getOperand(1))) 1308 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1309 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT, 1310 N0.getOperand(0), N1), 1311 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT, 1312 N0.getOperand(1), N1)); 1313 1314 // reassociate mul 1315 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1); 1316 if (RMUL.getNode() != 0) 1317 return RMUL; 1318 1319 return SDValue(); 1320} 1321 1322SDValue DAGCombiner::visitSDIV(SDNode *N) { 1323 SDValue N0 = N->getOperand(0); 1324 SDValue N1 = N->getOperand(1); 1325 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1326 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1327 EVT VT = N->getValueType(0); 1328 1329 // fold vector ops 1330 if (VT.isVector()) { 1331 SDValue FoldedVOp = SimplifyVBinOp(N); 1332 if (FoldedVOp.getNode()) return FoldedVOp; 1333 } 1334 1335 // fold (sdiv c1, c2) -> c1/c2 1336 if (N0C && N1C && !N1C->isNullValue()) 1337 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); 1338 // fold (sdiv X, 1) -> X 1339 if (N1C && N1C->getSExtValue() == 1LL) 1340 return N0; 1341 // fold (sdiv X, -1) -> 0-X 1342 if (N1C && N1C->isAllOnesValue()) 1343 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1344 DAG.getConstant(0, VT), N0); 1345 // If we know the sign bits of both operands are zero, strength reduce to a 1346 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1347 if (!VT.isVector()) { 1348 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1349 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(), 1350 N0, N1); 1351 } 1352 // fold (sdiv X, pow2) -> simple ops after legalize 1353 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() && 1354 (isPowerOf2_64(N1C->getSExtValue()) || 1355 isPowerOf2_64(-N1C->getSExtValue()))) { 1356 // If dividing by powers of two is cheap, then don't perform the following 1357 // fold. 1358 if (TLI.isPow2DivCheap()) 1359 return SDValue(); 1360 1361 int64_t pow2 = N1C->getSExtValue(); 1362 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1363 unsigned lg2 = Log2_64(abs2); 1364 1365 // Splat the sign bit into the register 1366 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 1367 DAG.getConstant(VT.getSizeInBits()-1, 1368 getShiftAmountTy())); 1369 AddToWorkList(SGN.getNode()); 1370 1371 // Add (N0 < 0) ? abs2 - 1 : 0; 1372 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN, 1373 DAG.getConstant(VT.getSizeInBits() - lg2, 1374 getShiftAmountTy())); 1375 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL); 1376 AddToWorkList(SRL.getNode()); 1377 AddToWorkList(ADD.getNode()); // Divide by pow2 1378 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD, 1379 DAG.getConstant(lg2, getShiftAmountTy())); 1380 1381 // If we're dividing by a positive value, we're done. Otherwise, we must 1382 // negate the result. 1383 if (pow2 > 0) 1384 return SRA; 1385 1386 AddToWorkList(SRA.getNode()); 1387 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1388 DAG.getConstant(0, VT), SRA); 1389 } 1390 1391 // if integer divide is expensive and we satisfy the requirements, emit an 1392 // alternate sequence. 1393 if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) && 1394 !TLI.isIntDivCheap()) { 1395 SDValue Op = BuildSDIV(N); 1396 if (Op.getNode()) return Op; 1397 } 1398 1399 // undef / X -> 0 1400 if (N0.getOpcode() == ISD::UNDEF) 1401 return DAG.getConstant(0, VT); 1402 // X / undef -> undef 1403 if (N1.getOpcode() == ISD::UNDEF) 1404 return N1; 1405 1406 return SDValue(); 1407} 1408 1409SDValue DAGCombiner::visitUDIV(SDNode *N) { 1410 SDValue N0 = N->getOperand(0); 1411 SDValue N1 = N->getOperand(1); 1412 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1413 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1414 EVT VT = N->getValueType(0); 1415 1416 // fold vector ops 1417 if (VT.isVector()) { 1418 SDValue FoldedVOp = SimplifyVBinOp(N); 1419 if (FoldedVOp.getNode()) return FoldedVOp; 1420 } 1421 1422 // fold (udiv c1, c2) -> c1/c2 1423 if (N0C && N1C && !N1C->isNullValue()) 1424 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); 1425 // fold (udiv x, (1 << c)) -> x >>u c 1426 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1427 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 1428 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1429 getShiftAmountTy())); 1430 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1431 if (N1.getOpcode() == ISD::SHL) { 1432 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1433 if (SHC->getAPIntValue().isPowerOf2()) { 1434 EVT ADDVT = N1.getOperand(1).getValueType(); 1435 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT, 1436 N1.getOperand(1), 1437 DAG.getConstant(SHC->getAPIntValue() 1438 .logBase2(), 1439 ADDVT)); 1440 AddToWorkList(Add.getNode()); 1441 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add); 1442 } 1443 } 1444 } 1445 // fold (udiv x, c) -> alternate 1446 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1447 SDValue Op = BuildUDIV(N); 1448 if (Op.getNode()) return Op; 1449 } 1450 1451 // undef / X -> 0 1452 if (N0.getOpcode() == ISD::UNDEF) 1453 return DAG.getConstant(0, VT); 1454 // X / undef -> undef 1455 if (N1.getOpcode() == ISD::UNDEF) 1456 return N1; 1457 1458 return SDValue(); 1459} 1460 1461SDValue DAGCombiner::visitSREM(SDNode *N) { 1462 SDValue N0 = N->getOperand(0); 1463 SDValue N1 = N->getOperand(1); 1464 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1465 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1466 EVT VT = N->getValueType(0); 1467 1468 // fold (srem c1, c2) -> c1%c2 1469 if (N0C && N1C && !N1C->isNullValue()) 1470 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); 1471 // If we know the sign bits of both operands are zero, strength reduce to a 1472 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1473 if (!VT.isVector()) { 1474 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1475 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1); 1476 } 1477 1478 // If X/C can be simplified by the division-by-constant logic, lower 1479 // X%C to the equivalent of X-X/C*C. 1480 if (N1C && !N1C->isNullValue()) { 1481 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1); 1482 AddToWorkList(Div.getNode()); 1483 SDValue OptimizedDiv = combine(Div.getNode()); 1484 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1485 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1486 OptimizedDiv, N1); 1487 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1488 AddToWorkList(Mul.getNode()); 1489 return Sub; 1490 } 1491 } 1492 1493 // undef % X -> 0 1494 if (N0.getOpcode() == ISD::UNDEF) 1495 return DAG.getConstant(0, VT); 1496 // X % undef -> undef 1497 if (N1.getOpcode() == ISD::UNDEF) 1498 return N1; 1499 1500 return SDValue(); 1501} 1502 1503SDValue DAGCombiner::visitUREM(SDNode *N) { 1504 SDValue N0 = N->getOperand(0); 1505 SDValue N1 = N->getOperand(1); 1506 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1507 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1508 EVT VT = N->getValueType(0); 1509 1510 // fold (urem c1, c2) -> c1%c2 1511 if (N0C && N1C && !N1C->isNullValue()) 1512 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C); 1513 // fold (urem x, pow2) -> (and x, pow2-1) 1514 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 1515 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, 1516 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 1517 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1518 if (N1.getOpcode() == ISD::SHL) { 1519 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1520 if (SHC->getAPIntValue().isPowerOf2()) { 1521 SDValue Add = 1522 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, 1523 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 1524 VT)); 1525 AddToWorkList(Add.getNode()); 1526 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add); 1527 } 1528 } 1529 } 1530 1531 // If X/C can be simplified by the division-by-constant logic, lower 1532 // X%C to the equivalent of X-X/C*C. 1533 if (N1C && !N1C->isNullValue()) { 1534 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1); 1535 AddToWorkList(Div.getNode()); 1536 SDValue OptimizedDiv = combine(Div.getNode()); 1537 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1538 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1539 OptimizedDiv, N1); 1540 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1541 AddToWorkList(Mul.getNode()); 1542 return Sub; 1543 } 1544 } 1545 1546 // undef % X -> 0 1547 if (N0.getOpcode() == ISD::UNDEF) 1548 return DAG.getConstant(0, VT); 1549 // X % undef -> undef 1550 if (N1.getOpcode() == ISD::UNDEF) 1551 return N1; 1552 1553 return SDValue(); 1554} 1555 1556SDValue DAGCombiner::visitMULHS(SDNode *N) { 1557 SDValue N0 = N->getOperand(0); 1558 SDValue N1 = N->getOperand(1); 1559 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1560 EVT VT = N->getValueType(0); 1561 1562 // fold (mulhs x, 0) -> 0 1563 if (N1C && N1C->isNullValue()) 1564 return N1; 1565 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1566 if (N1C && N1C->getAPIntValue() == 1) 1567 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0, 1568 DAG.getConstant(N0.getValueType().getSizeInBits() - 1, 1569 getShiftAmountTy())); 1570 // fold (mulhs x, undef) -> 0 1571 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1572 return DAG.getConstant(0, VT); 1573 1574 return SDValue(); 1575} 1576 1577SDValue DAGCombiner::visitMULHU(SDNode *N) { 1578 SDValue N0 = N->getOperand(0); 1579 SDValue N1 = N->getOperand(1); 1580 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1581 EVT VT = N->getValueType(0); 1582 1583 // fold (mulhu x, 0) -> 0 1584 if (N1C && N1C->isNullValue()) 1585 return N1; 1586 // fold (mulhu x, 1) -> 0 1587 if (N1C && N1C->getAPIntValue() == 1) 1588 return DAG.getConstant(0, N0.getValueType()); 1589 // fold (mulhu x, undef) -> 0 1590 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1591 return DAG.getConstant(0, VT); 1592 1593 return SDValue(); 1594} 1595 1596/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 1597/// compute two values. LoOp and HiOp give the opcodes for the two computations 1598/// that are being performed. Return true if a simplification was made. 1599/// 1600SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 1601 unsigned HiOp) { 1602 // If the high half is not needed, just compute the low half. 1603 bool HiExists = N->hasAnyUseOfValue(1); 1604 if (!HiExists && 1605 (!LegalOperations || 1606 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 1607 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 1608 N->op_begin(), N->getNumOperands()); 1609 return CombineTo(N, Res, Res); 1610 } 1611 1612 // If the low half is not needed, just compute the high half. 1613 bool LoExists = N->hasAnyUseOfValue(0); 1614 if (!LoExists && 1615 (!LegalOperations || 1616 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 1617 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 1618 N->op_begin(), N->getNumOperands()); 1619 return CombineTo(N, Res, Res); 1620 } 1621 1622 // If both halves are used, return as it is. 1623 if (LoExists && HiExists) 1624 return SDValue(); 1625 1626 // If the two computed results can be simplified separately, separate them. 1627 if (LoExists) { 1628 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 1629 N->op_begin(), N->getNumOperands()); 1630 AddToWorkList(Lo.getNode()); 1631 SDValue LoOpt = combine(Lo.getNode()); 1632 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && 1633 (!LegalOperations || 1634 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 1635 return CombineTo(N, LoOpt, LoOpt); 1636 } 1637 1638 if (HiExists) { 1639 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 1640 N->op_begin(), N->getNumOperands()); 1641 AddToWorkList(Hi.getNode()); 1642 SDValue HiOpt = combine(Hi.getNode()); 1643 if (HiOpt.getNode() && HiOpt != Hi && 1644 (!LegalOperations || 1645 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 1646 return CombineTo(N, HiOpt, HiOpt); 1647 } 1648 1649 return SDValue(); 1650} 1651 1652SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 1653 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 1654 if (Res.getNode()) return Res; 1655 1656 return SDValue(); 1657} 1658 1659SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 1660 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 1661 if (Res.getNode()) return Res; 1662 1663 return SDValue(); 1664} 1665 1666SDValue DAGCombiner::visitSDIVREM(SDNode *N) { 1667 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 1668 if (Res.getNode()) return Res; 1669 1670 return SDValue(); 1671} 1672 1673SDValue DAGCombiner::visitUDIVREM(SDNode *N) { 1674 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 1675 if (Res.getNode()) return Res; 1676 1677 return SDValue(); 1678} 1679 1680/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 1681/// two operands of the same opcode, try to simplify it. 1682SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 1683 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 1684 EVT VT = N0.getValueType(); 1685 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 1686 1687 // For each of OP in AND/OR/XOR: 1688 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 1689 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 1690 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 1691 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free) 1692 // 1693 // do not sink logical op inside of a vector extend, since it may combine 1694 // into a vsetcc. 1695 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND|| 1696 N0.getOpcode() == ISD::SIGN_EXTEND || 1697 (N0.getOpcode() == ISD::TRUNCATE && 1698 !TLI.isTruncateFree(N0.getOperand(0).getValueType(), VT))) && 1699 !VT.isVector() && 1700 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType() && 1701 (!LegalOperations || 1702 TLI.isOperationLegal(N->getOpcode(), N0.getOperand(0).getValueType()))) { 1703 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 1704 N0.getOperand(0).getValueType(), 1705 N0.getOperand(0), N1.getOperand(0)); 1706 AddToWorkList(ORNode.getNode()); 1707 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode); 1708 } 1709 1710 // For each of OP in SHL/SRL/SRA/AND... 1711 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 1712 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 1713 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 1714 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 1715 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 1716 N0.getOperand(1) == N1.getOperand(1)) { 1717 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 1718 N0.getOperand(0).getValueType(), 1719 N0.getOperand(0), N1.getOperand(0)); 1720 AddToWorkList(ORNode.getNode()); 1721 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 1722 ORNode, N0.getOperand(1)); 1723 } 1724 1725 return SDValue(); 1726} 1727 1728SDValue DAGCombiner::visitAND(SDNode *N) { 1729 SDValue N0 = N->getOperand(0); 1730 SDValue N1 = N->getOperand(1); 1731 SDValue LL, LR, RL, RR, CC0, CC1; 1732 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1733 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1734 EVT VT = N1.getValueType(); 1735 unsigned BitWidth = VT.getSizeInBits(); 1736 1737 // fold vector ops 1738 if (VT.isVector()) { 1739 SDValue FoldedVOp = SimplifyVBinOp(N); 1740 if (FoldedVOp.getNode()) return FoldedVOp; 1741 } 1742 1743 // fold (and x, undef) -> 0 1744 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1745 return DAG.getConstant(0, VT); 1746 // fold (and c1, c2) -> c1&c2 1747 if (N0C && N1C) 1748 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C); 1749 // canonicalize constant to RHS 1750 if (N0C && !N1C) 1751 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0); 1752 // fold (and x, -1) -> x 1753 if (N1C && N1C->isAllOnesValue()) 1754 return N0; 1755 // if (and x, c) is known to be zero, return 0 1756 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 1757 APInt::getAllOnesValue(BitWidth))) 1758 return DAG.getConstant(0, VT); 1759 // reassociate and 1760 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1); 1761 if (RAND.getNode() != 0) 1762 return RAND; 1763 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 1764 if (N1C && N0.getOpcode() == ISD::OR) 1765 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1766 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 1767 return N1; 1768 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 1769 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1770 SDValue N0Op0 = N0.getOperand(0); 1771 APInt Mask = ~N1C->getAPIntValue(); 1772 Mask.trunc(N0Op0.getValueSizeInBits()); 1773 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 1774 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), 1775 N0.getValueType(), N0Op0); 1776 1777 // Replace uses of the AND with uses of the Zero extend node. 1778 CombineTo(N, Zext); 1779 1780 // We actually want to replace all uses of the any_extend with the 1781 // zero_extend, to avoid duplicating things. This will later cause this 1782 // AND to be folded. 1783 CombineTo(N0.getNode(), Zext); 1784 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1785 } 1786 } 1787 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 1788 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1789 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1790 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1791 1792 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1793 LL.getValueType().isInteger()) { 1794 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0) 1795 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 1796 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 1797 LR.getValueType(), LL, RL); 1798 AddToWorkList(ORNode.getNode()); 1799 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 1800 } 1801 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1) 1802 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 1803 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(), 1804 LR.getValueType(), LL, RL); 1805 AddToWorkList(ANDNode.getNode()); 1806 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 1807 } 1808 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1) 1809 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1810 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 1811 LR.getValueType(), LL, RL); 1812 AddToWorkList(ORNode.getNode()); 1813 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 1814 } 1815 } 1816 // canonicalize equivalent to ll == rl 1817 if (LL == RR && LR == RL) { 1818 Op1 = ISD::getSetCCSwappedOperands(Op1); 1819 std::swap(RL, RR); 1820 } 1821 if (LL == RL && LR == RR) { 1822 bool isInteger = LL.getValueType().isInteger(); 1823 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1824 if (Result != ISD::SETCC_INVALID && 1825 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 1826 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 1827 LL, LR, Result); 1828 } 1829 } 1830 1831 // Simplify: (and (op x...), (op y...)) -> (op (and x, y)) 1832 if (N0.getOpcode() == N1.getOpcode()) { 1833 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1834 if (Tmp.getNode()) return Tmp; 1835 } 1836 1837 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1838 // fold (and (sra)) -> (and (srl)) when possible. 1839 if (!VT.isVector() && 1840 SimplifyDemandedBits(SDValue(N, 0))) 1841 return SDValue(N, 0); 1842 // fold (zext_inreg (extload x)) -> (zextload x) 1843 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { 1844 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1845 EVT MemVT = LN0->getMemoryVT(); 1846 // If we zero all the possible extended bits, then we can turn this into 1847 // a zextload if we are running before legalize or the operation is legal. 1848 unsigned BitWidth = N1.getValueSizeInBits(); 1849 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1850 BitWidth - MemVT.getSizeInBits())) && 1851 ((!LegalOperations && !LN0->isVolatile()) || 1852 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 1853 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 1854 LN0->getChain(), LN0->getBasePtr(), 1855 LN0->getSrcValue(), 1856 LN0->getSrcValueOffset(), MemVT, 1857 LN0->isVolatile(), LN0->getAlignment()); 1858 AddToWorkList(N); 1859 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 1860 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1861 } 1862 } 1863 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1864 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 1865 N0.hasOneUse()) { 1866 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1867 EVT MemVT = LN0->getMemoryVT(); 1868 // If we zero all the possible extended bits, then we can turn this into 1869 // a zextload if we are running before legalize or the operation is legal. 1870 unsigned BitWidth = N1.getValueSizeInBits(); 1871 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1872 BitWidth - MemVT.getSizeInBits())) && 1873 ((!LegalOperations && !LN0->isVolatile()) || 1874 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 1875 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 1876 LN0->getChain(), 1877 LN0->getBasePtr(), LN0->getSrcValue(), 1878 LN0->getSrcValueOffset(), MemVT, 1879 LN0->isVolatile(), LN0->getAlignment()); 1880 AddToWorkList(N); 1881 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 1882 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1883 } 1884 } 1885 1886 // fold (and (load x), 255) -> (zextload x, i8) 1887 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1888 if (N1C && N0.getOpcode() == ISD::LOAD) { 1889 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1890 if (LN0->getExtensionType() != ISD::SEXTLOAD && 1891 LN0->isUnindexed() && N0.hasOneUse() && 1892 // Do not change the width of a volatile load. 1893 !LN0->isVolatile()) { 1894 EVT ExtVT = MVT::Other; 1895 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 1896 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())) 1897 ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits); 1898 1899 EVT LoadedVT = LN0->getMemoryVT(); 1900 1901 // Do not generate loads of non-round integer types since these can 1902 // be expensive (and would be wrong if the type is not byte sized). 1903 if (ExtVT != MVT::Other && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() && 1904 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 1905 EVT PtrType = N0.getOperand(1).getValueType(); 1906 1907 // For big endian targets, we need to add an offset to the pointer to 1908 // load the correct bytes. For little endian systems, we merely need to 1909 // read fewer bytes from the same pointer. 1910 unsigned LVTStoreBytes = LoadedVT.getStoreSize(); 1911 unsigned EVTStoreBytes = ExtVT.getStoreSize(); 1912 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 1913 unsigned Alignment = LN0->getAlignment(); 1914 SDValue NewPtr = LN0->getBasePtr(); 1915 1916 if (TLI.isBigEndian()) { 1917 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType, 1918 NewPtr, DAG.getConstant(PtrOff, PtrType)); 1919 Alignment = MinAlign(Alignment, PtrOff); 1920 } 1921 1922 AddToWorkList(NewPtr.getNode()); 1923 SDValue Load = 1924 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), VT, LN0->getChain(), 1925 NewPtr, LN0->getSrcValue(), LN0->getSrcValueOffset(), 1926 ExtVT, LN0->isVolatile(), Alignment); 1927 AddToWorkList(N); 1928 CombineTo(N0.getNode(), Load, Load.getValue(1)); 1929 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1930 } 1931 } 1932 } 1933 1934 return SDValue(); 1935} 1936 1937SDValue DAGCombiner::visitOR(SDNode *N) { 1938 SDValue N0 = N->getOperand(0); 1939 SDValue N1 = N->getOperand(1); 1940 SDValue LL, LR, RL, RR, CC0, CC1; 1941 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1942 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1943 EVT VT = N1.getValueType(); 1944 1945 // fold vector ops 1946 if (VT.isVector()) { 1947 SDValue FoldedVOp = SimplifyVBinOp(N); 1948 if (FoldedVOp.getNode()) return FoldedVOp; 1949 } 1950 1951 // fold (or x, undef) -> -1 1952 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) { 1953 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 1954 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT); 1955 } 1956 // fold (or c1, c2) -> c1|c2 1957 if (N0C && N1C) 1958 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); 1959 // canonicalize constant to RHS 1960 if (N0C && !N1C) 1961 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0); 1962 // fold (or x, 0) -> x 1963 if (N1C && N1C->isNullValue()) 1964 return N0; 1965 // fold (or x, -1) -> -1 1966 if (N1C && N1C->isAllOnesValue()) 1967 return N1; 1968 // fold (or x, c) -> c iff (x & ~c) == 0 1969 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 1970 return N1; 1971 // reassociate or 1972 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1); 1973 if (ROR.getNode() != 0) 1974 return ROR; 1975 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 1976 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 1977 isa<ConstantSDNode>(N0.getOperand(1))) { 1978 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 1979 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 1980 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 1981 N0.getOperand(0), N1), 1982 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1)); 1983 } 1984 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 1985 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1986 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1987 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1988 1989 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1990 LL.getValueType().isInteger()) { 1991 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0) 1992 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0) 1993 if (cast<ConstantSDNode>(LR)->isNullValue() && 1994 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 1995 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(), 1996 LR.getValueType(), LL, RL); 1997 AddToWorkList(ORNode.getNode()); 1998 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 1999 } 2000 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1) 2001 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1) 2002 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 2003 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 2004 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(), 2005 LR.getValueType(), LL, RL); 2006 AddToWorkList(ANDNode.getNode()); 2007 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 2008 } 2009 } 2010 // canonicalize equivalent to ll == rl 2011 if (LL == RR && LR == RL) { 2012 Op1 = ISD::getSetCCSwappedOperands(Op1); 2013 std::swap(RL, RR); 2014 } 2015 if (LL == RL && LR == RR) { 2016 bool isInteger = LL.getValueType().isInteger(); 2017 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 2018 if (Result != ISD::SETCC_INVALID && 2019 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 2020 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 2021 LL, LR, Result); 2022 } 2023 } 2024 2025 // Simplify: (or (op x...), (op y...)) -> (op (or x, y)) 2026 if (N0.getOpcode() == N1.getOpcode()) { 2027 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2028 if (Tmp.getNode()) return Tmp; 2029 } 2030 2031 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible. 2032 if (N0.getOpcode() == ISD::AND && 2033 N1.getOpcode() == ISD::AND && 2034 N0.getOperand(1).getOpcode() == ISD::Constant && 2035 N1.getOperand(1).getOpcode() == ISD::Constant && 2036 // Don't increase # computations. 2037 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) { 2038 // We can only do this xform if we know that bits from X that are set in C2 2039 // but not in C1 are already zero. Likewise for Y. 2040 const APInt &LHSMask = 2041 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 2042 const APInt &RHSMask = 2043 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 2044 2045 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 2046 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 2047 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 2048 N0.getOperand(0), N1.getOperand(0)); 2049 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X, 2050 DAG.getConstant(LHSMask | RHSMask, VT)); 2051 } 2052 } 2053 2054 // See if this is some rotate idiom. 2055 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc())) 2056 return SDValue(Rot, 0); 2057 2058 return SDValue(); 2059} 2060 2061/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 2062static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 2063 if (Op.getOpcode() == ISD::AND) { 2064 if (isa<ConstantSDNode>(Op.getOperand(1))) { 2065 Mask = Op.getOperand(1); 2066 Op = Op.getOperand(0); 2067 } else { 2068 return false; 2069 } 2070 } 2071 2072 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 2073 Shift = Op; 2074 return true; 2075 } 2076 2077 return false; 2078} 2079 2080// MatchRotate - Handle an 'or' of two operands. If this is one of the many 2081// idioms for rotate, and if the target supports rotation instructions, generate 2082// a rot[lr]. 2083SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) { 2084 // Must be a legal type. Expanded 'n promoted things won't work with rotates. 2085 EVT VT = LHS.getValueType(); 2086 if (!TLI.isTypeLegal(VT)) return 0; 2087 2088 // The target must have at least one rotate flavor. 2089 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT); 2090 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT); 2091 if (!HasROTL && !HasROTR) return 0; 2092 2093 // Match "(X shl/srl V1) & V2" where V2 may not be present. 2094 SDValue LHSShift; // The shift. 2095 SDValue LHSMask; // AND value if any. 2096 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 2097 return 0; // Not part of a rotate. 2098 2099 SDValue RHSShift; // The shift. 2100 SDValue RHSMask; // AND value if any. 2101 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 2102 return 0; // Not part of a rotate. 2103 2104 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 2105 return 0; // Not shifting the same value. 2106 2107 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 2108 return 0; // Shifts must disagree. 2109 2110 // Canonicalize shl to left side in a shl/srl pair. 2111 if (RHSShift.getOpcode() == ISD::SHL) { 2112 std::swap(LHS, RHS); 2113 std::swap(LHSShift, RHSShift); 2114 std::swap(LHSMask , RHSMask ); 2115 } 2116 2117 unsigned OpSizeInBits = VT.getSizeInBits(); 2118 SDValue LHSShiftArg = LHSShift.getOperand(0); 2119 SDValue LHSShiftAmt = LHSShift.getOperand(1); 2120 SDValue RHSShiftAmt = RHSShift.getOperand(1); 2121 2122 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 2123 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 2124 if (LHSShiftAmt.getOpcode() == ISD::Constant && 2125 RHSShiftAmt.getOpcode() == ISD::Constant) { 2126 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue(); 2127 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue(); 2128 if ((LShVal + RShVal) != OpSizeInBits) 2129 return 0; 2130 2131 SDValue Rot; 2132 if (HasROTL) 2133 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt); 2134 else 2135 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt); 2136 2137 // If there is an AND of either shifted operand, apply it to the result. 2138 if (LHSMask.getNode() || RHSMask.getNode()) { 2139 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 2140 2141 if (LHSMask.getNode()) { 2142 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 2143 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 2144 } 2145 if (RHSMask.getNode()) { 2146 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 2147 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 2148 } 2149 2150 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT)); 2151 } 2152 2153 return Rot.getNode(); 2154 } 2155 2156 // If there is a mask here, and we have a variable shift, we can't be sure 2157 // that we're masking out the right stuff. 2158 if (LHSMask.getNode() || RHSMask.getNode()) 2159 return 0; 2160 2161 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 2162 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 2163 if (RHSShiftAmt.getOpcode() == ISD::SUB && 2164 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 2165 if (ConstantSDNode *SUBC = 2166 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 2167 if (SUBC->getAPIntValue() == OpSizeInBits) { 2168 if (HasROTL) 2169 return DAG.getNode(ISD::ROTL, DL, VT, 2170 LHSShiftArg, LHSShiftAmt).getNode(); 2171 else 2172 return DAG.getNode(ISD::ROTR, DL, VT, 2173 LHSShiftArg, RHSShiftAmt).getNode(); 2174 } 2175 } 2176 } 2177 2178 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 2179 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 2180 if (LHSShiftAmt.getOpcode() == ISD::SUB && 2181 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 2182 if (ConstantSDNode *SUBC = 2183 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 2184 if (SUBC->getAPIntValue() == OpSizeInBits) { 2185 if (HasROTR) 2186 return DAG.getNode(ISD::ROTR, DL, VT, 2187 LHSShiftArg, RHSShiftAmt).getNode(); 2188 else 2189 return DAG.getNode(ISD::ROTL, DL, VT, 2190 LHSShiftArg, LHSShiftAmt).getNode(); 2191 } 2192 } 2193 } 2194 2195 // Look for sign/zext/any-extended or truncate cases: 2196 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2197 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2198 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2199 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && 2200 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2201 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2202 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2203 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { 2204 SDValue LExtOp0 = LHSShiftAmt.getOperand(0); 2205 SDValue RExtOp0 = RHSShiftAmt.getOperand(0); 2206 if (RExtOp0.getOpcode() == ISD::SUB && 2207 RExtOp0.getOperand(1) == LExtOp0) { 2208 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2209 // (rotl x, y) 2210 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2211 // (rotr x, (sub 32, y)) 2212 if (ConstantSDNode *SUBC = 2213 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 2214 if (SUBC->getAPIntValue() == OpSizeInBits) { 2215 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 2216 LHSShiftArg, 2217 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 2218 } 2219 } 2220 } else if (LExtOp0.getOpcode() == ISD::SUB && 2221 RExtOp0 == LExtOp0.getOperand(1)) { 2222 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2223 // (rotr x, y) 2224 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2225 // (rotl x, (sub 32, y)) 2226 if (ConstantSDNode *SUBC = 2227 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 2228 if (SUBC->getAPIntValue() == OpSizeInBits) { 2229 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, 2230 LHSShiftArg, 2231 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 2232 } 2233 } 2234 } 2235 } 2236 2237 return 0; 2238} 2239 2240SDValue DAGCombiner::visitXOR(SDNode *N) { 2241 SDValue N0 = N->getOperand(0); 2242 SDValue N1 = N->getOperand(1); 2243 SDValue LHS, RHS, CC; 2244 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2245 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2246 EVT VT = N0.getValueType(); 2247 2248 // fold vector ops 2249 if (VT.isVector()) { 2250 SDValue FoldedVOp = SimplifyVBinOp(N); 2251 if (FoldedVOp.getNode()) return FoldedVOp; 2252 } 2253 2254 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 2255 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 2256 return DAG.getConstant(0, VT); 2257 // fold (xor x, undef) -> undef 2258 if (N0.getOpcode() == ISD::UNDEF) 2259 return N0; 2260 if (N1.getOpcode() == ISD::UNDEF) 2261 return N1; 2262 // fold (xor c1, c2) -> c1^c2 2263 if (N0C && N1C) 2264 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); 2265 // canonicalize constant to RHS 2266 if (N0C && !N1C) 2267 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 2268 // fold (xor x, 0) -> x 2269 if (N1C && N1C->isNullValue()) 2270 return N0; 2271 // reassociate xor 2272 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1); 2273 if (RXOR.getNode() != 0) 2274 return RXOR; 2275 2276 // fold !(x cc y) -> (x !cc y) 2277 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 2278 bool isInt = LHS.getValueType().isInteger(); 2279 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 2280 isInt); 2281 2282 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) { 2283 switch (N0.getOpcode()) { 2284 default: 2285 llvm_unreachable("Unhandled SetCC Equivalent!"); 2286 case ISD::SETCC: 2287 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC); 2288 case ISD::SELECT_CC: 2289 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2), 2290 N0.getOperand(3), NotCC); 2291 } 2292 } 2293 } 2294 2295 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 2296 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 2297 N0.getNode()->hasOneUse() && 2298 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 2299 SDValue V = N0.getOperand(0); 2300 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V, 2301 DAG.getConstant(1, V.getValueType())); 2302 AddToWorkList(V.getNode()); 2303 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V); 2304 } 2305 2306 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc 2307 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 2308 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2309 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2310 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 2311 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2312 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2313 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2314 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2315 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2316 } 2317 } 2318 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants 2319 if (N1C && N1C->isAllOnesValue() && 2320 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2321 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2322 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 2323 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2324 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2325 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2326 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2327 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2328 } 2329 } 2330 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2)) 2331 if (N1C && N0.getOpcode() == ISD::XOR) { 2332 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 2333 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2334 if (N00C) 2335 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1), 2336 DAG.getConstant(N1C->getAPIntValue() ^ 2337 N00C->getAPIntValue(), VT)); 2338 if (N01C) 2339 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0), 2340 DAG.getConstant(N1C->getAPIntValue() ^ 2341 N01C->getAPIntValue(), VT)); 2342 } 2343 // fold (xor x, x) -> 0 2344 if (N0 == N1) { 2345 if (!VT.isVector()) { 2346 return DAG.getConstant(0, VT); 2347 } else if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)){ 2348 // Produce a vector of zeros. 2349 SDValue El = DAG.getConstant(0, VT.getVectorElementType()); 2350 std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 2351 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 2352 &Ops[0], Ops.size()); 2353 } 2354 } 2355 2356 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 2357 if (N0.getOpcode() == N1.getOpcode()) { 2358 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2359 if (Tmp.getNode()) return Tmp; 2360 } 2361 2362 // Simplify the expression using non-local knowledge. 2363 if (!VT.isVector() && 2364 SimplifyDemandedBits(SDValue(N, 0))) 2365 return SDValue(N, 0); 2366 2367 return SDValue(); 2368} 2369 2370/// visitShiftByConstant - Handle transforms common to the three shifts, when 2371/// the shift amount is a constant. 2372SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 2373 SDNode *LHS = N->getOperand(0).getNode(); 2374 if (!LHS->hasOneUse()) return SDValue(); 2375 2376 // We want to pull some binops through shifts, so that we have (and (shift)) 2377 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 2378 // thing happens with address calculations, so it's important to canonicalize 2379 // it. 2380 bool HighBitSet = false; // Can we transform this if the high bit is set? 2381 2382 switch (LHS->getOpcode()) { 2383 default: return SDValue(); 2384 case ISD::OR: 2385 case ISD::XOR: 2386 HighBitSet = false; // We can only transform sra if the high bit is clear. 2387 break; 2388 case ISD::AND: 2389 HighBitSet = true; // We can only transform sra if the high bit is set. 2390 break; 2391 case ISD::ADD: 2392 if (N->getOpcode() != ISD::SHL) 2393 return SDValue(); // only shl(add) not sr[al](add). 2394 HighBitSet = false; // We can only transform sra if the high bit is clear. 2395 break; 2396 } 2397 2398 // We require the RHS of the binop to be a constant as well. 2399 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 2400 if (!BinOpCst) return SDValue(); 2401 2402 // FIXME: disable this unless the input to the binop is a shift by a constant. 2403 // If it is not a shift, it pessimizes some common cases like: 2404 // 2405 // void foo(int *X, int i) { X[i & 1235] = 1; } 2406 // int bar(int *X, int i) { return X[i & 255]; } 2407 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); 2408 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 2409 BinOpLHSVal->getOpcode() != ISD::SRA && 2410 BinOpLHSVal->getOpcode() != ISD::SRL) || 2411 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 2412 return SDValue(); 2413 2414 EVT VT = N->getValueType(0); 2415 2416 // If this is a signed shift right, and the high bit is modified by the 2417 // logical operation, do not perform the transformation. The highBitSet 2418 // boolean indicates the value of the high bit of the constant which would 2419 // cause it to be modified for this operation. 2420 if (N->getOpcode() == ISD::SRA) { 2421 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 2422 if (BinOpRHSSignSet != HighBitSet) 2423 return SDValue(); 2424 } 2425 2426 // Fold the constants, shifting the binop RHS by the shift amount. 2427 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(), 2428 N->getValueType(0), 2429 LHS->getOperand(1), N->getOperand(1)); 2430 2431 // Create the new shift. 2432 SDValue NewShift = DAG.getNode(N->getOpcode(), LHS->getOperand(0).getDebugLoc(), 2433 VT, LHS->getOperand(0), N->getOperand(1)); 2434 2435 // Create the new binop. 2436 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS); 2437} 2438 2439SDValue DAGCombiner::visitSHL(SDNode *N) { 2440 SDValue N0 = N->getOperand(0); 2441 SDValue N1 = N->getOperand(1); 2442 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2443 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2444 EVT VT = N0.getValueType(); 2445 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 2446 2447 // fold (shl c1, c2) -> c1<<c2 2448 if (N0C && N1C) 2449 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C); 2450 // fold (shl 0, x) -> 0 2451 if (N0C && N0C->isNullValue()) 2452 return N0; 2453 // fold (shl x, c >= size(x)) -> undef 2454 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2455 return DAG.getUNDEF(VT); 2456 // fold (shl x, 0) -> x 2457 if (N1C && N1C->isNullValue()) 2458 return N0; 2459 // if (shl x, c) is known to be zero, return 0 2460 if (DAG.MaskedValueIsZero(SDValue(N, 0), 2461 APInt::getAllOnesValue(OpSizeInBits))) 2462 return DAG.getConstant(0, VT); 2463 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))). 2464 if (N1.getOpcode() == ISD::TRUNCATE && 2465 N1.getOperand(0).getOpcode() == ISD::AND && 2466 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2467 SDValue N101 = N1.getOperand(0).getOperand(1); 2468 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2469 EVT TruncVT = N1.getValueType(); 2470 SDValue N100 = N1.getOperand(0).getOperand(0); 2471 APInt TruncC = N101C->getAPIntValue(); 2472 TruncC.trunc(TruncVT.getSizeInBits()); 2473 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 2474 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT, 2475 DAG.getNode(ISD::TRUNCATE, 2476 N->getDebugLoc(), 2477 TruncVT, N100), 2478 DAG.getConstant(TruncC, TruncVT))); 2479 } 2480 } 2481 2482 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2483 return SDValue(N, 0); 2484 2485 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2)) 2486 if (N1C && N0.getOpcode() == ISD::SHL && 2487 N0.getOperand(1).getOpcode() == ISD::Constant) { 2488 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2489 uint64_t c2 = N1C->getZExtValue(); 2490 if (c1 + c2 > OpSizeInBits) 2491 return DAG.getConstant(0, VT); 2492 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 2493 DAG.getConstant(c1 + c2, N1.getValueType())); 2494 } 2495 // fold (shl (srl x, c1), c2) -> (shl (and x, (shl -1, c1)), (sub c2, c1)) or 2496 // (srl (and x, (shl -1, c1)), (sub c1, c2)) 2497 if (N1C && N0.getOpcode() == ISD::SRL && 2498 N0.getOperand(1).getOpcode() == ISD::Constant) { 2499 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2500 if (c1 < VT.getSizeInBits()) { 2501 uint64_t c2 = N1C->getZExtValue(); 2502 SDValue HiBitsMask = 2503 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 2504 VT.getSizeInBits() - c1), 2505 VT); 2506 SDValue Mask = DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, 2507 N0.getOperand(0), 2508 HiBitsMask); 2509 if (c2 > c1) 2510 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, Mask, 2511 DAG.getConstant(c2-c1, N1.getValueType())); 2512 else 2513 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Mask, 2514 DAG.getConstant(c1-c2, N1.getValueType())); 2515 } 2516 } 2517 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1)) 2518 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) { 2519 SDValue HiBitsMask = 2520 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 2521 VT.getSizeInBits() - 2522 N1C->getZExtValue()), 2523 VT); 2524 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 2525 HiBitsMask); 2526 } 2527 2528 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2529} 2530 2531SDValue DAGCombiner::visitSRA(SDNode *N) { 2532 SDValue N0 = N->getOperand(0); 2533 SDValue N1 = N->getOperand(1); 2534 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2535 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2536 EVT VT = N0.getValueType(); 2537 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 2538 2539 // fold (sra c1, c2) -> (sra c1, c2) 2540 if (N0C && N1C) 2541 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); 2542 // fold (sra 0, x) -> 0 2543 if (N0C && N0C->isNullValue()) 2544 return N0; 2545 // fold (sra -1, x) -> -1 2546 if (N0C && N0C->isAllOnesValue()) 2547 return N0; 2548 // fold (sra x, (setge c, size(x))) -> undef 2549 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2550 return DAG.getUNDEF(VT); 2551 // fold (sra x, 0) -> x 2552 if (N1C && N1C->isNullValue()) 2553 return N0; 2554 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 2555 // sext_inreg. 2556 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 2557 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue(); 2558 EVT EVT = EVT::getIntegerVT(*DAG.getContext(), LowBits); 2559 if ((!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))) 2560 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 2561 N0.getOperand(0), DAG.getValueType(EVT)); 2562 } 2563 2564 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) 2565 if (N1C && N0.getOpcode() == ISD::SRA) { 2566 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2567 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); 2568 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1; 2569 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0), 2570 DAG.getConstant(Sum, N1C->getValueType(0))); 2571 } 2572 } 2573 2574 // fold (sra (shl X, m), (sub result_size, n)) 2575 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for 2576 // result_size - n != m. 2577 // If truncate is free for the target sext(shl) is likely to result in better 2578 // code. 2579 if (N0.getOpcode() == ISD::SHL) { 2580 // Get the two constanst of the shifts, CN0 = m, CN = n. 2581 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2582 if (N01C && N1C) { 2583 // Determine what the truncate's result bitsize and type would be. 2584 EVT TruncVT = 2585 EVT::getIntegerVT(*DAG.getContext(), OpSizeInBits - N1C->getZExtValue()); 2586 // Determine the residual right-shift amount. 2587 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); 2588 2589 // If the shift is not a no-op (in which case this should be just a sign 2590 // extend already), the truncated to type is legal, sign_extend is legal 2591 // on that type, and the the truncate to that type is both legal and free, 2592 // perform the transform. 2593 if ((ShiftAmt > 0) && 2594 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) && 2595 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) && 2596 TLI.isTruncateFree(VT, TruncVT)) { 2597 2598 SDValue Amt = DAG.getConstant(ShiftAmt, getShiftAmountTy()); 2599 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, 2600 N0.getOperand(0), Amt); 2601 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT, 2602 Shift); 2603 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), 2604 N->getValueType(0), Trunc); 2605 } 2606 } 2607 } 2608 2609 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))). 2610 if (N1.getOpcode() == ISD::TRUNCATE && 2611 N1.getOperand(0).getOpcode() == ISD::AND && 2612 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2613 SDValue N101 = N1.getOperand(0).getOperand(1); 2614 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2615 EVT TruncVT = N1.getValueType(); 2616 SDValue N100 = N1.getOperand(0).getOperand(0); 2617 APInt TruncC = N101C->getAPIntValue(); 2618 TruncC.trunc(TruncVT.getScalarType().getSizeInBits()); 2619 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 2620 DAG.getNode(ISD::AND, N->getDebugLoc(), 2621 TruncVT, 2622 DAG.getNode(ISD::TRUNCATE, 2623 N->getDebugLoc(), 2624 TruncVT, N100), 2625 DAG.getConstant(TruncC, TruncVT))); 2626 } 2627 } 2628 2629 // Simplify, based on bits shifted out of the LHS. 2630 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2631 return SDValue(N, 0); 2632 2633 2634 // If the sign bit is known to be zero, switch this to a SRL. 2635 if (DAG.SignBitIsZero(N0)) 2636 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1); 2637 2638 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2639} 2640 2641SDValue DAGCombiner::visitSRL(SDNode *N) { 2642 SDValue N0 = N->getOperand(0); 2643 SDValue N1 = N->getOperand(1); 2644 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2645 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2646 EVT VT = N0.getValueType(); 2647 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 2648 2649 // fold (srl c1, c2) -> c1 >>u c2 2650 if (N0C && N1C) 2651 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); 2652 // fold (srl 0, x) -> 0 2653 if (N0C && N0C->isNullValue()) 2654 return N0; 2655 // fold (srl x, c >= size(x)) -> undef 2656 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2657 return DAG.getUNDEF(VT); 2658 // fold (srl x, 0) -> x 2659 if (N1C && N1C->isNullValue()) 2660 return N0; 2661 // if (srl x, c) is known to be zero, return 0 2662 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2663 APInt::getAllOnesValue(OpSizeInBits))) 2664 return DAG.getConstant(0, VT); 2665 2666 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2)) 2667 if (N1C && N0.getOpcode() == ISD::SRL && 2668 N0.getOperand(1).getOpcode() == ISD::Constant) { 2669 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2670 uint64_t c2 = N1C->getZExtValue(); 2671 if (c1 + c2 > OpSizeInBits) 2672 return DAG.getConstant(0, VT); 2673 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 2674 DAG.getConstant(c1 + c2, N1.getValueType())); 2675 } 2676 2677 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 2678 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2679 // Shifting in all undef bits? 2680 EVT SmallVT = N0.getOperand(0).getValueType(); 2681 if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) 2682 return DAG.getUNDEF(VT); 2683 2684 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT, 2685 N0.getOperand(0), N1); 2686 AddToWorkList(SmallShift.getNode()); 2687 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift); 2688 } 2689 2690 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 2691 // bit, which is unmodified by sra. 2692 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) { 2693 if (N0.getOpcode() == ISD::SRA) 2694 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1); 2695 } 2696 2697 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 2698 if (N1C && N0.getOpcode() == ISD::CTLZ && 2699 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 2700 APInt KnownZero, KnownOne; 2701 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 2702 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 2703 2704 // If any of the input bits are KnownOne, then the input couldn't be all 2705 // zeros, thus the result of the srl will always be zero. 2706 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 2707 2708 // If all of the bits input the to ctlz node are known to be zero, then 2709 // the result of the ctlz is "32" and the result of the shift is one. 2710 APInt UnknownBits = ~KnownZero & Mask; 2711 if (UnknownBits == 0) return DAG.getConstant(1, VT); 2712 2713 // Otherwise, check to see if there is exactly one bit input to the ctlz. 2714 if ((UnknownBits & (UnknownBits - 1)) == 0) { 2715 // Okay, we know that only that the single bit specified by UnknownBits 2716 // could be set on input to the CTLZ node. If this bit is set, the SRL 2717 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 2718 // to an SRL/XOR pair, which is likely to simplify more. 2719 unsigned ShAmt = UnknownBits.countTrailingZeros(); 2720 SDValue Op = N0.getOperand(0); 2721 2722 if (ShAmt) { 2723 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op, 2724 DAG.getConstant(ShAmt, getShiftAmountTy())); 2725 AddToWorkList(Op.getNode()); 2726 } 2727 2728 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 2729 Op, DAG.getConstant(1, VT)); 2730 } 2731 } 2732 2733 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))). 2734 if (N1.getOpcode() == ISD::TRUNCATE && 2735 N1.getOperand(0).getOpcode() == ISD::AND && 2736 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2737 SDValue N101 = N1.getOperand(0).getOperand(1); 2738 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2739 EVT TruncVT = N1.getValueType(); 2740 SDValue N100 = N1.getOperand(0).getOperand(0); 2741 APInt TruncC = N101C->getAPIntValue(); 2742 TruncC.trunc(TruncVT.getSizeInBits()); 2743 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 2744 DAG.getNode(ISD::AND, N->getDebugLoc(), 2745 TruncVT, 2746 DAG.getNode(ISD::TRUNCATE, 2747 N->getDebugLoc(), 2748 TruncVT, N100), 2749 DAG.getConstant(TruncC, TruncVT))); 2750 } 2751 } 2752 2753 // fold operands of srl based on knowledge that the low bits are not 2754 // demanded. 2755 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2756 return SDValue(N, 0); 2757 2758 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2759} 2760 2761SDValue DAGCombiner::visitCTLZ(SDNode *N) { 2762 SDValue N0 = N->getOperand(0); 2763 EVT VT = N->getValueType(0); 2764 2765 // fold (ctlz c1) -> c2 2766 if (isa<ConstantSDNode>(N0)) 2767 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0); 2768 return SDValue(); 2769} 2770 2771SDValue DAGCombiner::visitCTTZ(SDNode *N) { 2772 SDValue N0 = N->getOperand(0); 2773 EVT VT = N->getValueType(0); 2774 2775 // fold (cttz c1) -> c2 2776 if (isa<ConstantSDNode>(N0)) 2777 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0); 2778 return SDValue(); 2779} 2780 2781SDValue DAGCombiner::visitCTPOP(SDNode *N) { 2782 SDValue N0 = N->getOperand(0); 2783 EVT VT = N->getValueType(0); 2784 2785 // fold (ctpop c1) -> c2 2786 if (isa<ConstantSDNode>(N0)) 2787 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0); 2788 return SDValue(); 2789} 2790 2791SDValue DAGCombiner::visitSELECT(SDNode *N) { 2792 SDValue N0 = N->getOperand(0); 2793 SDValue N1 = N->getOperand(1); 2794 SDValue N2 = N->getOperand(2); 2795 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2796 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2797 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 2798 EVT VT = N->getValueType(0); 2799 EVT VT0 = N0.getValueType(); 2800 2801 // fold (select C, X, X) -> X 2802 if (N1 == N2) 2803 return N1; 2804 // fold (select true, X, Y) -> X 2805 if (N0C && !N0C->isNullValue()) 2806 return N1; 2807 // fold (select false, X, Y) -> Y 2808 if (N0C && N0C->isNullValue()) 2809 return N2; 2810 // fold (select C, 1, X) -> (or C, X) 2811 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 2812 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 2813 // fold (select C, 0, 1) -> (xor C, 1) 2814 if (VT.isInteger() && 2815 (VT0 == MVT::i1 || 2816 (VT0.isInteger() && 2817 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) && 2818 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 2819 SDValue XORNode; 2820 if (VT == VT0) 2821 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0, 2822 N0, DAG.getConstant(1, VT0)); 2823 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0, 2824 N0, DAG.getConstant(1, VT0)); 2825 AddToWorkList(XORNode.getNode()); 2826 if (VT.bitsGT(VT0)) 2827 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode); 2828 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode); 2829 } 2830 // fold (select C, 0, X) -> (and (not C), X) 2831 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 2832 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 2833 AddToWorkList(NOTNode.getNode()); 2834 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2); 2835 } 2836 // fold (select C, X, 1) -> (or (not C), X) 2837 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 2838 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 2839 AddToWorkList(NOTNode.getNode()); 2840 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1); 2841 } 2842 // fold (select C, X, 0) -> (and C, X) 2843 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 2844 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 2845 // fold (select X, X, Y) -> (or X, Y) 2846 // fold (select X, 1, Y) -> (or X, Y) 2847 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1))) 2848 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 2849 // fold (select X, Y, X) -> (and X, Y) 2850 // fold (select X, Y, 0) -> (and X, Y) 2851 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0))) 2852 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 2853 2854 // If we can fold this based on the true/false value, do so. 2855 if (SimplifySelectOps(N, N1, N2)) 2856 return SDValue(N, 0); // Don't revisit N. 2857 2858 // fold selects based on a setcc into other things, such as min/max/abs 2859 if (N0.getOpcode() == ISD::SETCC) { 2860 // FIXME: 2861 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 2862 // having to say they don't support SELECT_CC on every type the DAG knows 2863 // about, since there is no way to mark an opcode illegal at all value types 2864 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) && 2865 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT)) 2866 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, 2867 N0.getOperand(0), N0.getOperand(1), 2868 N1, N2, N0.getOperand(2)); 2869 return SimplifySelect(N->getDebugLoc(), N0, N1, N2); 2870 } 2871 2872 return SDValue(); 2873} 2874 2875SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 2876 SDValue N0 = N->getOperand(0); 2877 SDValue N1 = N->getOperand(1); 2878 SDValue N2 = N->getOperand(2); 2879 SDValue N3 = N->getOperand(3); 2880 SDValue N4 = N->getOperand(4); 2881 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 2882 2883 // fold select_cc lhs, rhs, x, x, cc -> x 2884 if (N2 == N3) 2885 return N2; 2886 2887 // Determine if the condition we're dealing with is constant 2888 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 2889 N0, N1, CC, N->getDebugLoc(), false); 2890 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 2891 2892 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) { 2893 if (!SCCC->isNullValue()) 2894 return N2; // cond always true -> true val 2895 else 2896 return N3; // cond always false -> false val 2897 } 2898 2899 // Fold to a simpler select_cc 2900 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) 2901 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(), 2902 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 2903 SCC.getOperand(2)); 2904 2905 // If we can fold this based on the true/false value, do so. 2906 if (SimplifySelectOps(N, N2, N3)) 2907 return SDValue(N, 0); // Don't revisit N. 2908 2909 // fold select_cc into other things, such as min/max/abs 2910 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC); 2911} 2912 2913SDValue DAGCombiner::visitSETCC(SDNode *N) { 2914 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 2915 cast<CondCodeSDNode>(N->getOperand(2))->get(), 2916 N->getDebugLoc()); 2917} 2918 2919// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 2920// "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))" 2921// transformation. Returns true if extension are possible and the above 2922// mentioned transformation is profitable. 2923static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 2924 unsigned ExtOpc, 2925 SmallVector<SDNode*, 4> &ExtendNodes, 2926 const TargetLowering &TLI) { 2927 bool HasCopyToRegUses = false; 2928 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 2929 for (SDNode::use_iterator UI = N0.getNode()->use_begin(), 2930 UE = N0.getNode()->use_end(); 2931 UI != UE; ++UI) { 2932 SDNode *User = *UI; 2933 if (User == N) 2934 continue; 2935 if (UI.getUse().getResNo() != N0.getResNo()) 2936 continue; 2937 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 2938 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { 2939 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 2940 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 2941 // Sign bits will be lost after a zext. 2942 return false; 2943 bool Add = false; 2944 for (unsigned i = 0; i != 2; ++i) { 2945 SDValue UseOp = User->getOperand(i); 2946 if (UseOp == N0) 2947 continue; 2948 if (!isa<ConstantSDNode>(UseOp)) 2949 return false; 2950 Add = true; 2951 } 2952 if (Add) 2953 ExtendNodes.push_back(User); 2954 continue; 2955 } 2956 // If truncates aren't free and there are users we can't 2957 // extend, it isn't worthwhile. 2958 if (!isTruncFree) 2959 return false; 2960 // Remember if this value is live-out. 2961 if (User->getOpcode() == ISD::CopyToReg) 2962 HasCopyToRegUses = true; 2963 } 2964 2965 if (HasCopyToRegUses) { 2966 bool BothLiveOut = false; 2967 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 2968 UI != UE; ++UI) { 2969 SDUse &Use = UI.getUse(); 2970 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) { 2971 BothLiveOut = true; 2972 break; 2973 } 2974 } 2975 if (BothLiveOut) 2976 // Both unextended and extended values are live out. There had better be 2977 // good a reason for the transformation. 2978 return ExtendNodes.size(); 2979 } 2980 return true; 2981} 2982 2983SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 2984 SDValue N0 = N->getOperand(0); 2985 EVT VT = N->getValueType(0); 2986 2987 // fold (sext c1) -> c1 2988 if (isa<ConstantSDNode>(N0)) 2989 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0); 2990 2991 // fold (sext (sext x)) -> (sext x) 2992 // fold (sext (aext x)) -> (sext x) 2993 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2994 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, 2995 N0.getOperand(0)); 2996 2997 if (N0.getOpcode() == ISD::TRUNCATE) { 2998 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 2999 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 3000 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3001 if (NarrowLoad.getNode()) { 3002 if (NarrowLoad.getNode() != N0.getNode()) 3003 CombineTo(N0.getNode(), NarrowLoad); 3004 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3005 } 3006 3007 // See if the value being truncated is already sign extended. If so, just 3008 // eliminate the trunc/sext pair. 3009 SDValue Op = N0.getOperand(0); 3010 unsigned OpBits = Op.getValueType().getSizeInBits(); 3011 unsigned MidBits = N0.getValueType().getSizeInBits(); 3012 unsigned DestBits = VT.getSizeInBits(); 3013 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 3014 3015 if (OpBits == DestBits) { 3016 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 3017 // bits, it is already ready. 3018 if (NumSignBits > DestBits-MidBits) 3019 return Op; 3020 } else if (OpBits < DestBits) { 3021 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 3022 // bits, just sext from i32. 3023 if (NumSignBits > OpBits-MidBits) 3024 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op); 3025 } else { 3026 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 3027 // bits, just truncate to i32. 3028 if (NumSignBits > OpBits-MidBits) 3029 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 3030 } 3031 3032 // fold (sext (truncate x)) -> (sextinreg x). 3033 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 3034 N0.getValueType())) { 3035 if (Op.getValueType().bitsLT(VT)) 3036 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op); 3037 else if (Op.getValueType().bitsGT(VT)) 3038 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op); 3039 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op, 3040 DAG.getValueType(N0.getValueType().getScalarType())); 3041 } 3042 } 3043 3044 // fold (sext (load x)) -> (sext (truncate (sextload x))) 3045 if (ISD::isNON_EXTLoad(N0.getNode()) && 3046 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3047 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { 3048 bool DoXform = true; 3049 SmallVector<SDNode*, 4> SetCCs; 3050 if (!N0.hasOneUse()) 3051 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 3052 if (DoXform) { 3053 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3054 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3055 LN0->getChain(), 3056 LN0->getBasePtr(), LN0->getSrcValue(), 3057 LN0->getSrcValueOffset(), 3058 N0.getValueType(), 3059 LN0->isVolatile(), LN0->getAlignment()); 3060 CombineTo(N, ExtLoad); 3061 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3062 N0.getValueType(), ExtLoad); 3063 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3064 3065 // Extend SetCC uses if necessary. 3066 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3067 SDNode *SetCC = SetCCs[i]; 3068 SmallVector<SDValue, 4> Ops; 3069 3070 for (unsigned j = 0; j != 2; ++j) { 3071 SDValue SOp = SetCC->getOperand(j); 3072 if (SOp == Trunc) 3073 Ops.push_back(ExtLoad); 3074 else 3075 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, 3076 N->getDebugLoc(), VT, SOp)); 3077 } 3078 3079 Ops.push_back(SetCC->getOperand(2)); 3080 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3081 SetCC->getValueType(0), 3082 &Ops[0], Ops.size())); 3083 } 3084 3085 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3086 } 3087 } 3088 3089 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 3090 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 3091 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3092 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3093 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3094 EVT MemVT = LN0->getMemoryVT(); 3095 if ((!LegalOperations && !LN0->isVolatile()) || 3096 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) { 3097 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3098 LN0->getChain(), 3099 LN0->getBasePtr(), LN0->getSrcValue(), 3100 LN0->getSrcValueOffset(), MemVT, 3101 LN0->isVolatile(), LN0->getAlignment()); 3102 CombineTo(N, ExtLoad); 3103 CombineTo(N0.getNode(), 3104 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3105 N0.getValueType(), ExtLoad), 3106 ExtLoad.getValue(1)); 3107 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3108 } 3109 } 3110 3111 if (N0.getOpcode() == ISD::SETCC) { 3112 // sext(setcc) -> sext_in_reg(vsetcc) for vectors. 3113 if (VT.isVector() && 3114 // We know that the # elements of the results is the same as the 3115 // # elements of the compare (and the # elements of the compare result 3116 // for that matter). Check to see that they are the same size. If so, 3117 // we know that the element size of the sext'd result matches the 3118 // element size of the compare operands. 3119 VT.getSizeInBits() == N0.getOperand(0).getValueType().getSizeInBits() && 3120 3121 // Only do this before legalize for now. 3122 !LegalOperations) { 3123 return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 3124 N0.getOperand(1), 3125 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 3126 } 3127 3128 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc) 3129 SDValue NegOne = 3130 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT); 3131 SDValue SCC = 3132 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3133 NegOne, DAG.getConstant(0, VT), 3134 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3135 if (SCC.getNode()) return SCC; 3136 } 3137 3138 3139 3140 // fold (sext x) -> (zext x) if the sign bit is known zero. 3141 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 3142 DAG.SignBitIsZero(N0)) 3143 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3144 3145 return SDValue(); 3146} 3147 3148SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 3149 SDValue N0 = N->getOperand(0); 3150 EVT VT = N->getValueType(0); 3151 3152 // fold (zext c1) -> c1 3153 if (isa<ConstantSDNode>(N0)) 3154 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3155 // fold (zext (zext x)) -> (zext x) 3156 // fold (zext (aext x)) -> (zext x) 3157 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 3158 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, 3159 N0.getOperand(0)); 3160 3161 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 3162 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 3163 if (N0.getOpcode() == ISD::TRUNCATE) { 3164 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3165 if (NarrowLoad.getNode()) { 3166 if (NarrowLoad.getNode() != N0.getNode()) 3167 CombineTo(N0.getNode(), NarrowLoad); 3168 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 3169 } 3170 } 3171 3172 // fold (zext (truncate x)) -> (and x, mask) 3173 if (N0.getOpcode() == ISD::TRUNCATE && 3174 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) { 3175 SDValue Op = N0.getOperand(0); 3176 if (Op.getValueType().bitsLT(VT)) { 3177 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op); 3178 } else if (Op.getValueType().bitsGT(VT)) { 3179 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 3180 } 3181 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), 3182 N0.getValueType().getScalarType()); 3183 } 3184 3185 // Fold (zext (and (trunc x), cst)) -> (and x, cst), 3186 // if either of the casts is not free. 3187 if (N0.getOpcode() == ISD::AND && 3188 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3189 N0.getOperand(1).getOpcode() == ISD::Constant && 3190 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 3191 N0.getValueType()) || 3192 !TLI.isZExtFree(N0.getValueType(), VT))) { 3193 SDValue X = N0.getOperand(0).getOperand(0); 3194 if (X.getValueType().bitsLT(VT)) { 3195 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X); 3196 } else if (X.getValueType().bitsGT(VT)) { 3197 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 3198 } 3199 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3200 Mask.zext(VT.getSizeInBits()); 3201 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3202 X, DAG.getConstant(Mask, VT)); 3203 } 3204 3205 // Fold (zext (and x, cst)) -> (and (zext x), cst) 3206 if (N0.getOpcode() == ISD::AND && 3207 N0.getOperand(1).getOpcode() == ISD::Constant && 3208 N0.getOperand(0).getOpcode() != ISD::TRUNCATE && 3209 N0.getOperand(0).hasOneUse()) { 3210 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3211 Mask.zext(VT.getSizeInBits()); 3212 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3213 DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, 3214 N0.getOperand(0)), 3215 DAG.getConstant(Mask, VT)); 3216 } 3217 3218 // fold (zext (load x)) -> (zext (truncate (zextload x))) 3219 if (ISD::isNON_EXTLoad(N0.getNode()) && 3220 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3221 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 3222 bool DoXform = true; 3223 SmallVector<SDNode*, 4> SetCCs; 3224 if (!N0.hasOneUse()) 3225 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 3226 if (DoXform) { 3227 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3228 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 3229 LN0->getChain(), 3230 LN0->getBasePtr(), LN0->getSrcValue(), 3231 LN0->getSrcValueOffset(), 3232 N0.getValueType(), 3233 LN0->isVolatile(), LN0->getAlignment()); 3234 CombineTo(N, ExtLoad); 3235 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3236 N0.getValueType(), ExtLoad); 3237 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3238 3239 // Extend SetCC uses if necessary. 3240 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3241 SDNode *SetCC = SetCCs[i]; 3242 SmallVector<SDValue, 4> Ops; 3243 3244 for (unsigned j = 0; j != 2; ++j) { 3245 SDValue SOp = SetCC->getOperand(j); 3246 if (SOp == Trunc) 3247 Ops.push_back(ExtLoad); 3248 else 3249 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, 3250 N->getDebugLoc(), VT, SOp)); 3251 } 3252 3253 Ops.push_back(SetCC->getOperand(2)); 3254 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3255 SetCC->getValueType(0), 3256 &Ops[0], Ops.size())); 3257 } 3258 3259 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3260 } 3261 } 3262 3263 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 3264 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 3265 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3266 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3267 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3268 EVT MemVT = LN0->getMemoryVT(); 3269 if ((!LegalOperations && !LN0->isVolatile()) || 3270 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) { 3271 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 3272 LN0->getChain(), 3273 LN0->getBasePtr(), LN0->getSrcValue(), 3274 LN0->getSrcValueOffset(), MemVT, 3275 LN0->isVolatile(), LN0->getAlignment()); 3276 CombineTo(N, ExtLoad); 3277 CombineTo(N0.getNode(), 3278 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(), 3279 ExtLoad), 3280 ExtLoad.getValue(1)); 3281 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3282 } 3283 } 3284 3285 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3286 if (N0.getOpcode() == ISD::SETCC) { 3287 SDValue SCC = 3288 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3289 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3290 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3291 if (SCC.getNode()) return SCC; 3292 } 3293 3294 // (zext (shl (zext x), cst)) -> (shl (zext x), cst) 3295 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && 3296 isa<ConstantSDNode>(N0.getOperand(1)) && 3297 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && 3298 N0.hasOneUse()) { 3299 if (N0.getOpcode() == ISD::SHL) { 3300 // If the original shl may be shifting out bits, do not perform this 3301 // transformation. 3302 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3303 unsigned KnownZeroBits = N0.getOperand(0).getValueType().getSizeInBits() - 3304 N0.getOperand(0).getOperand(0).getValueType().getSizeInBits(); 3305 if (ShAmt > KnownZeroBits) 3306 return SDValue(); 3307 } 3308 DebugLoc dl = N->getDebugLoc(); 3309 return DAG.getNode(N0.getOpcode(), dl, VT, 3310 DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0.getOperand(0)), 3311 DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0.getOperand(1))); 3312 } 3313 3314 return SDValue(); 3315} 3316 3317SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 3318 SDValue N0 = N->getOperand(0); 3319 EVT VT = N->getValueType(0); 3320 3321 // fold (aext c1) -> c1 3322 if (isa<ConstantSDNode>(N0)) 3323 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0); 3324 // fold (aext (aext x)) -> (aext x) 3325 // fold (aext (zext x)) -> (zext x) 3326 // fold (aext (sext x)) -> (sext x) 3327 if (N0.getOpcode() == ISD::ANY_EXTEND || 3328 N0.getOpcode() == ISD::ZERO_EXTEND || 3329 N0.getOpcode() == ISD::SIGN_EXTEND) 3330 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0)); 3331 3332 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 3333 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 3334 if (N0.getOpcode() == ISD::TRUNCATE) { 3335 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3336 if (NarrowLoad.getNode()) { 3337 if (NarrowLoad.getNode() != N0.getNode()) 3338 CombineTo(N0.getNode(), NarrowLoad); 3339 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 3340 } 3341 } 3342 3343 // fold (aext (truncate x)) 3344 if (N0.getOpcode() == ISD::TRUNCATE) { 3345 SDValue TruncOp = N0.getOperand(0); 3346 if (TruncOp.getValueType() == VT) 3347 return TruncOp; // x iff x size == zext size. 3348 if (TruncOp.getValueType().bitsGT(VT)) 3349 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp); 3350 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp); 3351 } 3352 3353 // Fold (aext (and (trunc x), cst)) -> (and x, cst) 3354 // if the trunc is not free. 3355 if (N0.getOpcode() == ISD::AND && 3356 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3357 N0.getOperand(1).getOpcode() == ISD::Constant && 3358 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 3359 N0.getValueType())) { 3360 SDValue X = N0.getOperand(0).getOperand(0); 3361 if (X.getValueType().bitsLT(VT)) { 3362 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X); 3363 } else if (X.getValueType().bitsGT(VT)) { 3364 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X); 3365 } 3366 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3367 Mask.zext(VT.getSizeInBits()); 3368 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3369 X, DAG.getConstant(Mask, VT)); 3370 } 3371 3372 // fold (aext (load x)) -> (aext (truncate (extload x))) 3373 if (ISD::isNON_EXTLoad(N0.getNode()) && 3374 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3375 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 3376 bool DoXform = true; 3377 SmallVector<SDNode*, 4> SetCCs; 3378 if (!N0.hasOneUse()) 3379 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI); 3380 if (DoXform) { 3381 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3382 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 3383 LN0->getChain(), 3384 LN0->getBasePtr(), LN0->getSrcValue(), 3385 LN0->getSrcValueOffset(), 3386 N0.getValueType(), 3387 LN0->isVolatile(), LN0->getAlignment()); 3388 CombineTo(N, ExtLoad); 3389 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3390 N0.getValueType(), ExtLoad); 3391 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3392 3393 // Extend SetCC uses if necessary. 3394 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3395 SDNode *SetCC = SetCCs[i]; 3396 SmallVector<SDValue, 4> Ops; 3397 3398 for (unsigned j = 0; j != 2; ++j) { 3399 SDValue SOp = SetCC->getOperand(j); 3400 if (SOp == Trunc) 3401 Ops.push_back(ExtLoad); 3402 else 3403 Ops.push_back(DAG.getNode(ISD::ANY_EXTEND, 3404 N->getDebugLoc(), VT, SOp)); 3405 } 3406 3407 Ops.push_back(SetCC->getOperand(2)); 3408 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3409 SetCC->getValueType(0), 3410 &Ops[0], Ops.size())); 3411 } 3412 3413 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3414 } 3415 } 3416 3417 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 3418 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 3419 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 3420 if (N0.getOpcode() == ISD::LOAD && 3421 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3422 N0.hasOneUse()) { 3423 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3424 EVT MemVT = LN0->getMemoryVT(); 3425 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(), 3426 VT, LN0->getChain(), LN0->getBasePtr(), 3427 LN0->getSrcValue(), 3428 LN0->getSrcValueOffset(), MemVT, 3429 LN0->isVolatile(), LN0->getAlignment()); 3430 CombineTo(N, ExtLoad); 3431 CombineTo(N0.getNode(), 3432 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3433 N0.getValueType(), ExtLoad), 3434 ExtLoad.getValue(1)); 3435 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3436 } 3437 3438 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3439 if (N0.getOpcode() == ISD::SETCC) { 3440 SDValue SCC = 3441 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3442 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3443 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3444 if (SCC.getNode()) 3445 return SCC; 3446 } 3447 3448 return SDValue(); 3449} 3450 3451/// GetDemandedBits - See if the specified operand can be simplified with the 3452/// knowledge that only the bits specified by Mask are used. If so, return the 3453/// simpler operand, otherwise return a null SDValue. 3454SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 3455 switch (V.getOpcode()) { 3456 default: break; 3457 case ISD::OR: 3458 case ISD::XOR: 3459 // If the LHS or RHS don't contribute bits to the or, drop them. 3460 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 3461 return V.getOperand(1); 3462 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 3463 return V.getOperand(0); 3464 break; 3465 case ISD::SRL: 3466 // Only look at single-use SRLs. 3467 if (!V.getNode()->hasOneUse()) 3468 break; 3469 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 3470 // See if we can recursively simplify the LHS. 3471 unsigned Amt = RHSC->getZExtValue(); 3472 3473 // Watch out for shift count overflow though. 3474 if (Amt >= Mask.getBitWidth()) break; 3475 APInt NewMask = Mask << Amt; 3476 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 3477 if (SimplifyLHS.getNode()) 3478 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(), 3479 SimplifyLHS, V.getOperand(1)); 3480 } 3481 } 3482 return SDValue(); 3483} 3484 3485/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 3486/// bits and then truncated to a narrower type and where N is a multiple 3487/// of number of bits of the narrower type, transform it to a narrower load 3488/// from address + N / num of bits of new type. If the result is to be 3489/// extended, also fold the extension to form a extending load. 3490SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 3491 unsigned Opc = N->getOpcode(); 3492 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 3493 SDValue N0 = N->getOperand(0); 3494 EVT VT = N->getValueType(0); 3495 EVT ExtVT = VT; 3496 3497 // This transformation isn't valid for vector loads. 3498 if (VT.isVector()) 3499 return SDValue(); 3500 3501 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then 3502 // extended to VT. 3503 if (Opc == ISD::SIGN_EXTEND_INREG) { 3504 ExtType = ISD::SEXTLOAD; 3505 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3506 if (LegalOperations && !TLI.isLoadExtLegal(ISD::SEXTLOAD, ExtVT)) 3507 return SDValue(); 3508 } 3509 3510 unsigned EVTBits = ExtVT.getSizeInBits(); 3511 unsigned ShAmt = 0; 3512 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse() && ExtVT.isRound()) { 3513 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3514 ShAmt = N01->getZExtValue(); 3515 // Is the shift amount a multiple of size of VT? 3516 if ((ShAmt & (EVTBits-1)) == 0) { 3517 N0 = N0.getOperand(0); 3518 // Is the load width a multiple of size of VT? 3519 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0) 3520 return SDValue(); 3521 } 3522 } 3523 } 3524 3525 // Do not generate loads of non-round integer types since these can 3526 // be expensive (and would be wrong if the type is not byte sized). 3527 if (isa<LoadSDNode>(N0) && N0.hasOneUse() && ExtVT.isRound() && 3528 cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() > EVTBits && 3529 // Do not change the width of a volatile load. 3530 !cast<LoadSDNode>(N0)->isVolatile()) { 3531 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3532 EVT PtrType = N0.getOperand(1).getValueType(); 3533 3534 // For big endian targets, we need to adjust the offset to the pointer to 3535 // load the correct bytes. 3536 if (TLI.isBigEndian()) { 3537 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 3538 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits(); 3539 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 3540 } 3541 3542 uint64_t PtrOff = ShAmt / 8; 3543 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 3544 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), 3545 PtrType, LN0->getBasePtr(), 3546 DAG.getConstant(PtrOff, PtrType)); 3547 AddToWorkList(NewPtr.getNode()); 3548 3549 SDValue Load = (ExtType == ISD::NON_EXTLOAD) 3550 ? DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr, 3551 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3552 LN0->isVolatile(), NewAlign) 3553 : DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(), NewPtr, 3554 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3555 ExtVT, LN0->isVolatile(), NewAlign); 3556 3557 // Replace the old load's chain with the new load's chain. 3558 WorkListRemover DeadNodes(*this); 3559 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), 3560 &DeadNodes); 3561 3562 // Return the new loaded value. 3563 return Load; 3564 } 3565 3566 return SDValue(); 3567} 3568 3569SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 3570 SDValue N0 = N->getOperand(0); 3571 SDValue N1 = N->getOperand(1); 3572 EVT VT = N->getValueType(0); 3573 EVT EVT = cast<VTSDNode>(N1)->getVT(); 3574 unsigned VTBits = VT.getScalarType().getSizeInBits(); 3575 unsigned EVTBits = EVT.getSizeInBits(); 3576 3577 // fold (sext_in_reg c1) -> c1 3578 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 3579 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1); 3580 3581 // If the input is already sign extended, just drop the extension. 3582 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1) 3583 return N0; 3584 3585 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 3586 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 3587 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 3588 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 3589 N0.getOperand(0), N1); 3590 } 3591 3592 // fold (sext_in_reg (sext x)) -> (sext x) 3593 // fold (sext_in_reg (aext x)) -> (sext x) 3594 // if x is small enough. 3595 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 3596 SDValue N00 = N0.getOperand(0); 3597 if (N00.getValueType().getScalarType().getSizeInBits() < EVTBits) 3598 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1); 3599 } 3600 3601 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 3602 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 3603 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT); 3604 3605 // fold operands of sext_in_reg based on knowledge that the top bits are not 3606 // demanded. 3607 if (SimplifyDemandedBits(SDValue(N, 0))) 3608 return SDValue(N, 0); 3609 3610 // fold (sext_in_reg (load x)) -> (smaller sextload x) 3611 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 3612 SDValue NarrowLoad = ReduceLoadWidth(N); 3613 if (NarrowLoad.getNode()) 3614 return NarrowLoad; 3615 3616 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24) 3617 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible. 3618 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 3619 if (N0.getOpcode() == ISD::SRL) { 3620 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 3621 if (ShAmt->getZExtValue()+EVTBits <= VTBits) { 3622 // We can turn this into an SRA iff the input to the SRL is already sign 3623 // extended enough. 3624 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 3625 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits) 3626 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, 3627 N0.getOperand(0), N0.getOperand(1)); 3628 } 3629 } 3630 3631 // fold (sext_inreg (extload x)) -> (sextload x) 3632 if (ISD::isEXTLoad(N0.getNode()) && 3633 ISD::isUNINDEXEDLoad(N0.getNode()) && 3634 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3635 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3636 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 3637 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3638 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3639 LN0->getChain(), 3640 LN0->getBasePtr(), LN0->getSrcValue(), 3641 LN0->getSrcValueOffset(), EVT, 3642 LN0->isVolatile(), LN0->getAlignment()); 3643 CombineTo(N, ExtLoad); 3644 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 3645 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3646 } 3647 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 3648 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3649 N0.hasOneUse() && 3650 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3651 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3652 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 3653 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3654 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3655 LN0->getChain(), 3656 LN0->getBasePtr(), LN0->getSrcValue(), 3657 LN0->getSrcValueOffset(), EVT, 3658 LN0->isVolatile(), LN0->getAlignment()); 3659 CombineTo(N, ExtLoad); 3660 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 3661 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3662 } 3663 return SDValue(); 3664} 3665 3666SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 3667 SDValue N0 = N->getOperand(0); 3668 EVT VT = N->getValueType(0); 3669 3670 // noop truncate 3671 if (N0.getValueType() == N->getValueType(0)) 3672 return N0; 3673 // fold (truncate c1) -> c1 3674 if (isa<ConstantSDNode>(N0)) 3675 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0); 3676 // fold (truncate (truncate x)) -> (truncate x) 3677 if (N0.getOpcode() == ISD::TRUNCATE) 3678 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 3679 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 3680 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| 3681 N0.getOpcode() == ISD::ANY_EXTEND) { 3682 if (N0.getOperand(0).getValueType().bitsLT(VT)) 3683 // if the source is smaller than the dest, we still need an extend 3684 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 3685 N0.getOperand(0)); 3686 else if (N0.getOperand(0).getValueType().bitsGT(VT)) 3687 // if the source is larger than the dest, than we just need the truncate 3688 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 3689 else 3690 // if the source and dest are the same type, we can drop both the extend 3691 // and the truncate 3692 return N0.getOperand(0); 3693 } 3694 3695 // See if we can simplify the input to this truncate through knowledge that 3696 // only the low bits are being used. For example "trunc (or (shl x, 8), y)" 3697 // -> trunc y 3698 SDValue Shorter = 3699 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 3700 VT.getSizeInBits())); 3701 if (Shorter.getNode()) 3702 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter); 3703 3704 // fold (truncate (load x)) -> (smaller load x) 3705 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 3706 return ReduceLoadWidth(N); 3707} 3708 3709static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 3710 SDValue Elt = N->getOperand(i); 3711 if (Elt.getOpcode() != ISD::MERGE_VALUES) 3712 return Elt.getNode(); 3713 return Elt.getOperand(Elt.getResNo()).getNode(); 3714} 3715 3716/// CombineConsecutiveLoads - build_pair (load, load) -> load 3717/// if load locations are consecutive. 3718SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) { 3719 assert(N->getOpcode() == ISD::BUILD_PAIR); 3720 3721 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0)); 3722 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1)); 3723 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse()) 3724 return SDValue(); 3725 EVT LD1VT = LD1->getValueType(0); 3726 3727 if (ISD::isNON_EXTLoad(LD2) && 3728 LD2->hasOneUse() && 3729 // If both are volatile this would reduce the number of volatile loads. 3730 // If one is volatile it might be ok, but play conservative and bail out. 3731 !LD1->isVolatile() && 3732 !LD2->isVolatile() && 3733 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) { 3734 unsigned Align = LD1->getAlignment(); 3735 unsigned NewAlign = TLI.getTargetData()-> 3736 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 3737 3738 if (NewAlign <= Align && 3739 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) 3740 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(), 3741 LD1->getBasePtr(), LD1->getSrcValue(), 3742 LD1->getSrcValueOffset(), false, Align); 3743 } 3744 3745 return SDValue(); 3746} 3747 3748SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) { 3749 SDValue N0 = N->getOperand(0); 3750 EVT VT = N->getValueType(0); 3751 3752 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 3753 // Only do this before legalize, since afterward the target may be depending 3754 // on the bitconvert. 3755 // First check to see if this is all constant. 3756 if (!LegalTypes && 3757 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 3758 VT.isVector()) { 3759 bool isSimple = true; 3760 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 3761 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 3762 N0.getOperand(i).getOpcode() != ISD::Constant && 3763 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 3764 isSimple = false; 3765 break; 3766 } 3767 3768 EVT DestEltVT = N->getValueType(0).getVectorElementType(); 3769 assert(!DestEltVT.isVector() && 3770 "Element type of vector ValueType must not be vector!"); 3771 if (isSimple) 3772 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.getNode(), DestEltVT); 3773 } 3774 3775 // If the input is a constant, let getNode fold it. 3776 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 3777 SDValue Res = DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, N0); 3778 if (Res.getNode() != N) { 3779 if (!LegalOperations || 3780 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT)) 3781 return Res; 3782 3783 // Folding it resulted in an illegal node, and it's too late to 3784 // do that. Clean up the old node and forego the transformation. 3785 // Ideally this won't happen very often, because instcombine 3786 // and the earlier dagcombine runs (where illegal nodes are 3787 // permitted) should have folded most of them already. 3788 DAG.DeleteNode(Res.getNode()); 3789 } 3790 } 3791 3792 // (conv (conv x, t1), t2) -> (conv x, t2) 3793 if (N0.getOpcode() == ISD::BIT_CONVERT) 3794 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, 3795 N0.getOperand(0)); 3796 3797 // fold (conv (load x)) -> (load (conv*)x) 3798 // If the resultant load doesn't need a higher alignment than the original! 3799 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 3800 // Do not change the width of a volatile load. 3801 !cast<LoadSDNode>(N0)->isVolatile() && 3802 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) { 3803 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3804 unsigned Align = TLI.getTargetData()-> 3805 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 3806 unsigned OrigAlign = LN0->getAlignment(); 3807 3808 if (Align <= OrigAlign) { 3809 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(), 3810 LN0->getBasePtr(), 3811 LN0->getSrcValue(), LN0->getSrcValueOffset(), 3812 LN0->isVolatile(), OrigAlign); 3813 AddToWorkList(N); 3814 CombineTo(N0.getNode(), 3815 DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 3816 N0.getValueType(), Load), 3817 Load.getValue(1)); 3818 return Load; 3819 } 3820 } 3821 3822 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit) 3823 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit)) 3824 // This often reduces constant pool loads. 3825 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && 3826 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) { 3827 SDValue NewConv = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), VT, 3828 N0.getOperand(0)); 3829 AddToWorkList(NewConv.getNode()); 3830 3831 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3832 if (N0.getOpcode() == ISD::FNEG) 3833 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 3834 NewConv, DAG.getConstant(SignBit, VT)); 3835 assert(N0.getOpcode() == ISD::FABS); 3836 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3837 NewConv, DAG.getConstant(~SignBit, VT)); 3838 } 3839 3840 // fold (bitconvert (fcopysign cst, x)) -> 3841 // (or (and (bitconvert x), sign), (and cst, (not sign))) 3842 // Note that we don't handle (copysign x, cst) because this can always be 3843 // folded to an fneg or fabs. 3844 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 3845 isa<ConstantFPSDNode>(N0.getOperand(0)) && 3846 VT.isInteger() && !VT.isVector()) { 3847 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 3848 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth); 3849 if (TLI.isTypeLegal(IntXVT) || !LegalTypes) { 3850 SDValue X = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 3851 IntXVT, N0.getOperand(1)); 3852 AddToWorkList(X.getNode()); 3853 3854 // If X has a different width than the result/lhs, sext it or truncate it. 3855 unsigned VTWidth = VT.getSizeInBits(); 3856 if (OrigXWidth < VTWidth) { 3857 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X); 3858 AddToWorkList(X.getNode()); 3859 } else if (OrigXWidth > VTWidth) { 3860 // To get the sign bit in the right place, we have to shift it right 3861 // before truncating. 3862 X = DAG.getNode(ISD::SRL, X.getDebugLoc(), 3863 X.getValueType(), X, 3864 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 3865 AddToWorkList(X.getNode()); 3866 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 3867 AddToWorkList(X.getNode()); 3868 } 3869 3870 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3871 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT, 3872 X, DAG.getConstant(SignBit, VT)); 3873 AddToWorkList(X.getNode()); 3874 3875 SDValue Cst = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 3876 VT, N0.getOperand(0)); 3877 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT, 3878 Cst, DAG.getConstant(~SignBit, VT)); 3879 AddToWorkList(Cst.getNode()); 3880 3881 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst); 3882 } 3883 } 3884 3885 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 3886 if (N0.getOpcode() == ISD::BUILD_PAIR) { 3887 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT); 3888 if (CombineLD.getNode()) 3889 return CombineLD; 3890 } 3891 3892 return SDValue(); 3893} 3894 3895SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 3896 EVT VT = N->getValueType(0); 3897 return CombineConsecutiveLoads(N, VT); 3898} 3899 3900/// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector 3901/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 3902/// destination element value type. 3903SDValue DAGCombiner:: 3904ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) { 3905 EVT SrcEltVT = BV->getValueType(0).getVectorElementType(); 3906 3907 // If this is already the right type, we're done. 3908 if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 3909 3910 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 3911 unsigned DstBitSize = DstEltVT.getSizeInBits(); 3912 3913 // If this is a conversion of N elements of one type to N elements of another 3914 // type, convert each element. This handles FP<->INT cases. 3915 if (SrcBitSize == DstBitSize) { 3916 SmallVector<SDValue, 8> Ops; 3917 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3918 SDValue Op = BV->getOperand(i); 3919 // If the vector element type is not legal, the BUILD_VECTOR operands 3920 // are promoted and implicitly truncated. Make that explicit here. 3921 if (Op.getValueType() != SrcEltVT) 3922 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op); 3923 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, BV->getDebugLoc(), 3924 DstEltVT, Op)); 3925 AddToWorkList(Ops.back().getNode()); 3926 } 3927 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 3928 BV->getValueType(0).getVectorNumElements()); 3929 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 3930 &Ops[0], Ops.size()); 3931 } 3932 3933 // Otherwise, we're growing or shrinking the elements. To avoid having to 3934 // handle annoying details of growing/shrinking FP values, we convert them to 3935 // int first. 3936 if (SrcEltVT.isFloatingPoint()) { 3937 // Convert the input float vector to a int vector where the elements are the 3938 // same sizes. 3939 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 3940 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits()); 3941 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode(); 3942 SrcEltVT = IntVT; 3943 } 3944 3945 // Now we know the input is an integer vector. If the output is a FP type, 3946 // convert to integer first, then to FP of the right size. 3947 if (DstEltVT.isFloatingPoint()) { 3948 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 3949 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits()); 3950 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).getNode(); 3951 3952 // Next, convert to FP elements of the same size. 3953 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT); 3954 } 3955 3956 // Okay, we know the src/dst types are both integers of differing types. 3957 // Handling growing first. 3958 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 3959 if (SrcBitSize < DstBitSize) { 3960 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 3961 3962 SmallVector<SDValue, 8> Ops; 3963 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 3964 i += NumInputsPerOutput) { 3965 bool isLE = TLI.isLittleEndian(); 3966 APInt NewBits = APInt(DstBitSize, 0); 3967 bool EltIsUndef = true; 3968 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 3969 // Shift the previously computed bits over. 3970 NewBits <<= SrcBitSize; 3971 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 3972 if (Op.getOpcode() == ISD::UNDEF) continue; 3973 EltIsUndef = false; 3974 3975 NewBits |= (APInt(cast<ConstantSDNode>(Op)->getAPIntValue()). 3976 zextOrTrunc(SrcBitSize).zext(DstBitSize)); 3977 } 3978 3979 if (EltIsUndef) 3980 Ops.push_back(DAG.getUNDEF(DstEltVT)); 3981 else 3982 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 3983 } 3984 3985 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size()); 3986 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 3987 &Ops[0], Ops.size()); 3988 } 3989 3990 // Finally, this must be the case where we are shrinking elements: each input 3991 // turns into multiple outputs. 3992 bool isS2V = ISD::isScalarToVector(BV); 3993 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 3994 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 3995 NumOutputsPerInput*BV->getNumOperands()); 3996 SmallVector<SDValue, 8> Ops; 3997 3998 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3999 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 4000 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 4001 Ops.push_back(DAG.getUNDEF(DstEltVT)); 4002 continue; 4003 } 4004 4005 APInt OpVal = APInt(cast<ConstantSDNode>(BV->getOperand(i))-> 4006 getAPIntValue()).zextOrTrunc(SrcBitSize); 4007 4008 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 4009 APInt ThisVal = APInt(OpVal).trunc(DstBitSize); 4010 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 4011 if (isS2V && i == 0 && j == 0 && APInt(ThisVal).zext(SrcBitSize) == OpVal) 4012 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 4013 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 4014 Ops[0]); 4015 OpVal = OpVal.lshr(DstBitSize); 4016 } 4017 4018 // For big endian targets, swap the order of the pieces of each element. 4019 if (TLI.isBigEndian()) 4020 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 4021 } 4022 4023 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 4024 &Ops[0], Ops.size()); 4025} 4026 4027SDValue DAGCombiner::visitFADD(SDNode *N) { 4028 SDValue N0 = N->getOperand(0); 4029 SDValue N1 = N->getOperand(1); 4030 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4031 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4032 EVT VT = N->getValueType(0); 4033 4034 // fold vector ops 4035 if (VT.isVector()) { 4036 SDValue FoldedVOp = SimplifyVBinOp(N); 4037 if (FoldedVOp.getNode()) return FoldedVOp; 4038 } 4039 4040 // fold (fadd c1, c2) -> (fadd c1, c2) 4041 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4042 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1); 4043 // canonicalize constant to RHS 4044 if (N0CFP && !N1CFP) 4045 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0); 4046 // fold (fadd A, 0) -> A 4047 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4048 return N0; 4049 // fold (fadd A, (fneg B)) -> (fsub A, B) 4050 if (isNegatibleForFree(N1, LegalOperations) == 2) 4051 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, 4052 GetNegatedExpression(N1, DAG, LegalOperations)); 4053 // fold (fadd (fneg A), B) -> (fsub B, A) 4054 if (isNegatibleForFree(N0, LegalOperations) == 2) 4055 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1, 4056 GetNegatedExpression(N0, DAG, LegalOperations)); 4057 4058 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 4059 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 4060 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 4061 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0), 4062 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 4063 N0.getOperand(1), N1)); 4064 4065 return SDValue(); 4066} 4067 4068SDValue DAGCombiner::visitFSUB(SDNode *N) { 4069 SDValue N0 = N->getOperand(0); 4070 SDValue N1 = N->getOperand(1); 4071 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4072 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4073 EVT VT = N->getValueType(0); 4074 4075 // fold vector ops 4076 if (VT.isVector()) { 4077 SDValue FoldedVOp = SimplifyVBinOp(N); 4078 if (FoldedVOp.getNode()) return FoldedVOp; 4079 } 4080 4081 // fold (fsub c1, c2) -> c1-c2 4082 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4083 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1); 4084 // fold (fsub A, 0) -> A 4085 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4086 return N0; 4087 // fold (fsub 0, B) -> -B 4088 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { 4089 if (isNegatibleForFree(N1, LegalOperations)) 4090 return GetNegatedExpression(N1, DAG, LegalOperations); 4091 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4092 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1); 4093 } 4094 // fold (fsub A, (fneg B)) -> (fadd A, B) 4095 if (isNegatibleForFree(N1, LegalOperations)) 4096 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, 4097 GetNegatedExpression(N1, DAG, LegalOperations)); 4098 4099 return SDValue(); 4100} 4101 4102SDValue DAGCombiner::visitFMUL(SDNode *N) { 4103 SDValue N0 = N->getOperand(0); 4104 SDValue N1 = N->getOperand(1); 4105 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4106 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4107 EVT VT = N->getValueType(0); 4108 4109 // fold vector ops 4110 if (VT.isVector()) { 4111 SDValue FoldedVOp = SimplifyVBinOp(N); 4112 if (FoldedVOp.getNode()) return FoldedVOp; 4113 } 4114 4115 // fold (fmul c1, c2) -> c1*c2 4116 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4117 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1); 4118 // canonicalize constant to RHS 4119 if (N0CFP && !N1CFP) 4120 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0); 4121 // fold (fmul A, 0) -> 0 4122 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4123 return N1; 4124 // fold (fmul A, 0) -> 0, vector edition. 4125 if (UnsafeFPMath && ISD::isBuildVectorAllZeros(N1.getNode())) 4126 return N1; 4127 // fold (fmul X, 2.0) -> (fadd X, X) 4128 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 4129 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0); 4130 // fold (fmul X, -1.0) -> (fneg X) 4131 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 4132 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4133 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0); 4134 4135 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y) 4136 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 4137 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 4138 // Both can be negated for free, check to see if at least one is cheaper 4139 // negated. 4140 if (LHSNeg == 2 || RHSNeg == 2) 4141 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 4142 GetNegatedExpression(N0, DAG, LegalOperations), 4143 GetNegatedExpression(N1, DAG, LegalOperations)); 4144 } 4145 } 4146 4147 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 4148 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 4149 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 4150 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0), 4151 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 4152 N0.getOperand(1), N1)); 4153 4154 return SDValue(); 4155} 4156 4157SDValue DAGCombiner::visitFDIV(SDNode *N) { 4158 SDValue N0 = N->getOperand(0); 4159 SDValue N1 = N->getOperand(1); 4160 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4161 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4162 EVT VT = N->getValueType(0); 4163 4164 // fold vector ops 4165 if (VT.isVector()) { 4166 SDValue FoldedVOp = SimplifyVBinOp(N); 4167 if (FoldedVOp.getNode()) return FoldedVOp; 4168 } 4169 4170 // fold (fdiv c1, c2) -> c1/c2 4171 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4172 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1); 4173 4174 4175 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y) 4176 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 4177 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 4178 // Both can be negated for free, check to see if at least one is cheaper 4179 // negated. 4180 if (LHSNeg == 2 || RHSNeg == 2) 4181 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, 4182 GetNegatedExpression(N0, DAG, LegalOperations), 4183 GetNegatedExpression(N1, DAG, LegalOperations)); 4184 } 4185 } 4186 4187 return SDValue(); 4188} 4189 4190SDValue DAGCombiner::visitFREM(SDNode *N) { 4191 SDValue N0 = N->getOperand(0); 4192 SDValue N1 = N->getOperand(1); 4193 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4194 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4195 EVT VT = N->getValueType(0); 4196 4197 // fold (frem c1, c2) -> fmod(c1,c2) 4198 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4199 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1); 4200 4201 return SDValue(); 4202} 4203 4204SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 4205 SDValue N0 = N->getOperand(0); 4206 SDValue N1 = N->getOperand(1); 4207 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4208 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4209 EVT VT = N->getValueType(0); 4210 4211 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 4212 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1); 4213 4214 if (N1CFP) { 4215 const APFloat& V = N1CFP->getValueAPF(); 4216 // copysign(x, c1) -> fabs(x) iff ispos(c1) 4217 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 4218 if (!V.isNegative()) { 4219 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) 4220 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4221 } else { 4222 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4223 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, 4224 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0)); 4225 } 4226 } 4227 4228 // copysign(fabs(x), y) -> copysign(x, y) 4229 // copysign(fneg(x), y) -> copysign(x, y) 4230 // copysign(copysign(x,z), y) -> copysign(x, y) 4231 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 4232 N0.getOpcode() == ISD::FCOPYSIGN) 4233 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4234 N0.getOperand(0), N1); 4235 4236 // copysign(x, abs(y)) -> abs(x) 4237 if (N1.getOpcode() == ISD::FABS) 4238 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4239 4240 // copysign(x, copysign(y,z)) -> copysign(x, z) 4241 if (N1.getOpcode() == ISD::FCOPYSIGN) 4242 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4243 N0, N1.getOperand(1)); 4244 4245 // copysign(x, fp_extend(y)) -> copysign(x, y) 4246 // copysign(x, fp_round(y)) -> copysign(x, y) 4247 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 4248 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4249 N0, N1.getOperand(0)); 4250 4251 return SDValue(); 4252} 4253 4254SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 4255 SDValue N0 = N->getOperand(0); 4256 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4257 EVT VT = N->getValueType(0); 4258 EVT OpVT = N0.getValueType(); 4259 4260 // fold (sint_to_fp c1) -> c1fp 4261 if (N0C && OpVT != MVT::ppcf128) 4262 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 4263 4264 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 4265 // but UINT_TO_FP is legal on this target, try to convert. 4266 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && 4267 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { 4268 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 4269 if (DAG.SignBitIsZero(N0)) 4270 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 4271 } 4272 4273 return SDValue(); 4274} 4275 4276SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 4277 SDValue N0 = N->getOperand(0); 4278 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4279 EVT VT = N->getValueType(0); 4280 EVT OpVT = N0.getValueType(); 4281 4282 // fold (uint_to_fp c1) -> c1fp 4283 if (N0C && OpVT != MVT::ppcf128) 4284 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 4285 4286 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 4287 // but SINT_TO_FP is legal on this target, try to convert. 4288 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && 4289 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { 4290 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 4291 if (DAG.SignBitIsZero(N0)) 4292 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 4293 } 4294 4295 return SDValue(); 4296} 4297 4298SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 4299 SDValue N0 = N->getOperand(0); 4300 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4301 EVT VT = N->getValueType(0); 4302 4303 // fold (fp_to_sint c1fp) -> c1 4304 if (N0CFP) 4305 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0); 4306 4307 return SDValue(); 4308} 4309 4310SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 4311 SDValue N0 = N->getOperand(0); 4312 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4313 EVT VT = N->getValueType(0); 4314 4315 // fold (fp_to_uint c1fp) -> c1 4316 if (N0CFP && VT != MVT::ppcf128) 4317 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0); 4318 4319 return SDValue(); 4320} 4321 4322SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 4323 SDValue N0 = N->getOperand(0); 4324 SDValue N1 = N->getOperand(1); 4325 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4326 EVT VT = N->getValueType(0); 4327 4328 // fold (fp_round c1fp) -> c1fp 4329 if (N0CFP && N0.getValueType() != MVT::ppcf128) 4330 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1); 4331 4332 // fold (fp_round (fp_extend x)) -> x 4333 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 4334 return N0.getOperand(0); 4335 4336 // fold (fp_round (fp_round x)) -> (fp_round x) 4337 if (N0.getOpcode() == ISD::FP_ROUND) { 4338 // This is a value preserving truncation if both round's are. 4339 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 4340 N0.getNode()->getConstantOperandVal(1) == 1; 4341 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0), 4342 DAG.getIntPtrConstant(IsTrunc)); 4343 } 4344 4345 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 4346 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { 4347 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT, 4348 N0.getOperand(0), N1); 4349 AddToWorkList(Tmp.getNode()); 4350 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4351 Tmp, N0.getOperand(1)); 4352 } 4353 4354 return SDValue(); 4355} 4356 4357SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 4358 SDValue N0 = N->getOperand(0); 4359 EVT VT = N->getValueType(0); 4360 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 4361 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4362 4363 // fold (fp_round_inreg c1fp) -> c1fp 4364 if (N0CFP && (TLI.isTypeLegal(EVT) || !LegalTypes)) { 4365 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT); 4366 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round); 4367 } 4368 4369 return SDValue(); 4370} 4371 4372SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 4373 SDValue N0 = N->getOperand(0); 4374 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4375 EVT VT = N->getValueType(0); 4376 4377 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 4378 if (N->hasOneUse() && 4379 N->use_begin()->getOpcode() == ISD::FP_ROUND) 4380 return SDValue(); 4381 4382 // fold (fp_extend c1fp) -> c1fp 4383 if (N0CFP && VT != MVT::ppcf128) 4384 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0); 4385 4386 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 4387 // value of X. 4388 if (N0.getOpcode() == ISD::FP_ROUND 4389 && N0.getNode()->getConstantOperandVal(1) == 1) { 4390 SDValue In = N0.getOperand(0); 4391 if (In.getValueType() == VT) return In; 4392 if (VT.bitsLT(In.getValueType())) 4393 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, 4394 In, N0.getOperand(1)); 4395 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In); 4396 } 4397 4398 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 4399 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 4400 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4401 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 4402 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4403 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 4404 LN0->getChain(), 4405 LN0->getBasePtr(), LN0->getSrcValue(), 4406 LN0->getSrcValueOffset(), 4407 N0.getValueType(), 4408 LN0->isVolatile(), LN0->getAlignment()); 4409 CombineTo(N, ExtLoad); 4410 CombineTo(N0.getNode(), 4411 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), 4412 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)), 4413 ExtLoad.getValue(1)); 4414 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4415 } 4416 4417 return SDValue(); 4418} 4419 4420SDValue DAGCombiner::visitFNEG(SDNode *N) { 4421 SDValue N0 = N->getOperand(0); 4422 EVT VT = N->getValueType(0); 4423 4424 if (isNegatibleForFree(N0, LegalOperations)) 4425 return GetNegatedExpression(N0, DAG, LegalOperations); 4426 4427 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 4428 // constant pool values. 4429 if (N0.getOpcode() == ISD::BIT_CONVERT && 4430 !VT.isVector() && 4431 N0.getNode()->hasOneUse() && 4432 N0.getOperand(0).getValueType().isInteger()) { 4433 SDValue Int = N0.getOperand(0); 4434 EVT IntVT = Int.getValueType(); 4435 if (IntVT.isInteger() && !IntVT.isVector()) { 4436 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int, 4437 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 4438 AddToWorkList(Int.getNode()); 4439 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), 4440 VT, Int); 4441 } 4442 } 4443 4444 return SDValue(); 4445} 4446 4447SDValue DAGCombiner::visitFABS(SDNode *N) { 4448 SDValue N0 = N->getOperand(0); 4449 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4450 EVT VT = N->getValueType(0); 4451 4452 // fold (fabs c1) -> fabs(c1) 4453 if (N0CFP && VT != MVT::ppcf128) 4454 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4455 // fold (fabs (fabs x)) -> (fabs x) 4456 if (N0.getOpcode() == ISD::FABS) 4457 return N->getOperand(0); 4458 // fold (fabs (fneg x)) -> (fabs x) 4459 // fold (fabs (fcopysign x, y)) -> (fabs x) 4460 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 4461 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0)); 4462 4463 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 4464 // constant pool values. 4465 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() && 4466 N0.getOperand(0).getValueType().isInteger() && 4467 !N0.getOperand(0).getValueType().isVector()) { 4468 SDValue Int = N0.getOperand(0); 4469 EVT IntVT = Int.getValueType(); 4470 if (IntVT.isInteger() && !IntVT.isVector()) { 4471 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int, 4472 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 4473 AddToWorkList(Int.getNode()); 4474 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), 4475 N->getValueType(0), Int); 4476 } 4477 } 4478 4479 return SDValue(); 4480} 4481 4482SDValue DAGCombiner::visitBRCOND(SDNode *N) { 4483 SDValue Chain = N->getOperand(0); 4484 SDValue N1 = N->getOperand(1); 4485 SDValue N2 = N->getOperand(2); 4486 4487 // If N is a constant we could fold this into a fallthrough or unconditional 4488 // branch. However that doesn't happen very often in normal code, because 4489 // Instcombine/SimplifyCFG should have handled the available opportunities. 4490 // If we did this folding here, it would be necessary to update the 4491 // MachineBasicBlock CFG, which is awkward. 4492 4493 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 4494 // on the target. 4495 if (N1.getOpcode() == ISD::SETCC && 4496 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) { 4497 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 4498 Chain, N1.getOperand(2), 4499 N1.getOperand(0), N1.getOperand(1), N2); 4500 } 4501 4502 if (N1.hasOneUse() && N1.getOpcode() == ISD::SRL) { 4503 // Match this pattern so that we can generate simpler code: 4504 // 4505 // %a = ... 4506 // %b = and i32 %a, 2 4507 // %c = srl i32 %b, 1 4508 // brcond i32 %c ... 4509 // 4510 // into 4511 // 4512 // %a = ... 4513 // %b = and %a, 2 4514 // %c = setcc eq %b, 0 4515 // brcond %c ... 4516 // 4517 // This applies only when the AND constant value has one bit set and the 4518 // SRL constant is equal to the log2 of the AND constant. The back-end is 4519 // smart enough to convert the result into a TEST/JMP sequence. 4520 SDValue Op0 = N1.getOperand(0); 4521 SDValue Op1 = N1.getOperand(1); 4522 4523 if (Op0.getOpcode() == ISD::AND && 4524 Op0.hasOneUse() && 4525 Op1.getOpcode() == ISD::Constant) { 4526 SDValue AndOp1 = Op0.getOperand(1); 4527 4528 if (AndOp1.getOpcode() == ISD::Constant) { 4529 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue(); 4530 4531 if (AndConst.isPowerOf2() && 4532 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) { 4533 SDValue SetCC = 4534 DAG.getSetCC(N->getDebugLoc(), 4535 TLI.getSetCCResultType(Op0.getValueType()), 4536 Op0, DAG.getConstant(0, Op0.getValueType()), 4537 ISD::SETNE); 4538 4539 // Replace the uses of SRL with SETCC 4540 DAG.ReplaceAllUsesOfValueWith(N1, SetCC); 4541 removeFromWorkList(N1.getNode()); 4542 DAG.DeleteNode(N1.getNode()); 4543 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 4544 MVT::Other, Chain, SetCC, N2); 4545 } 4546 } 4547 } 4548 } 4549 4550 return SDValue(); 4551} 4552 4553// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 4554// 4555SDValue DAGCombiner::visitBR_CC(SDNode *N) { 4556 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 4557 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 4558 4559 // If N is a constant we could fold this into a fallthrough or unconditional 4560 // branch. However that doesn't happen very often in normal code, because 4561 // Instcombine/SimplifyCFG should have handled the available opportunities. 4562 // If we did this folding here, it would be necessary to update the 4563 // MachineBasicBlock CFG, which is awkward. 4564 4565 // Use SimplifySetCC to simplify SETCC's. 4566 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()), 4567 CondLHS, CondRHS, CC->get(), N->getDebugLoc(), 4568 false); 4569 if (Simp.getNode()) AddToWorkList(Simp.getNode()); 4570 4571 // fold to a simpler setcc 4572 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) 4573 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 4574 N->getOperand(0), Simp.getOperand(2), 4575 Simp.getOperand(0), Simp.getOperand(1), 4576 N->getOperand(4)); 4577 4578 return SDValue(); 4579} 4580 4581/// CombineToPreIndexedLoadStore - Try turning a load / store into a 4582/// pre-indexed load / store when the base pointer is an add or subtract 4583/// and it has other uses besides the load / store. After the 4584/// transformation, the new indexed load / store has effectively folded 4585/// the add / subtract in and all of its other uses are redirected to the 4586/// new load / store. 4587bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 4588 if (!LegalOperations) 4589 return false; 4590 4591 bool isLoad = true; 4592 SDValue Ptr; 4593 EVT VT; 4594 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4595 if (LD->isIndexed()) 4596 return false; 4597 VT = LD->getMemoryVT(); 4598 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 4599 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 4600 return false; 4601 Ptr = LD->getBasePtr(); 4602 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4603 if (ST->isIndexed()) 4604 return false; 4605 VT = ST->getMemoryVT(); 4606 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 4607 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 4608 return false; 4609 Ptr = ST->getBasePtr(); 4610 isLoad = false; 4611 } else { 4612 return false; 4613 } 4614 4615 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 4616 // out. There is no reason to make this a preinc/predec. 4617 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 4618 Ptr.getNode()->hasOneUse()) 4619 return false; 4620 4621 // Ask the target to do addressing mode selection. 4622 SDValue BasePtr; 4623 SDValue Offset; 4624 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4625 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 4626 return false; 4627 // Don't create a indexed load / store with zero offset. 4628 if (isa<ConstantSDNode>(Offset) && 4629 cast<ConstantSDNode>(Offset)->isNullValue()) 4630 return false; 4631 4632 // Try turning it into a pre-indexed load / store except when: 4633 // 1) The new base ptr is a frame index. 4634 // 2) If N is a store and the new base ptr is either the same as or is a 4635 // predecessor of the value being stored. 4636 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 4637 // that would create a cycle. 4638 // 4) All uses are load / store ops that use it as old base ptr. 4639 4640 // Check #1. Preinc'ing a frame index would require copying the stack pointer 4641 // (plus the implicit offset) to a register to preinc anyway. 4642 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 4643 return false; 4644 4645 // Check #2. 4646 if (!isLoad) { 4647 SDValue Val = cast<StoreSDNode>(N)->getValue(); 4648 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode())) 4649 return false; 4650 } 4651 4652 // Now check for #3 and #4. 4653 bool RealUse = false; 4654 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 4655 E = Ptr.getNode()->use_end(); I != E; ++I) { 4656 SDNode *Use = *I; 4657 if (Use == N) 4658 continue; 4659 if (Use->isPredecessorOf(N)) 4660 return false; 4661 4662 if (!((Use->getOpcode() == ISD::LOAD && 4663 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 4664 (Use->getOpcode() == ISD::STORE && 4665 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))) 4666 RealUse = true; 4667 } 4668 4669 if (!RealUse) 4670 return false; 4671 4672 SDValue Result; 4673 if (isLoad) 4674 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 4675 BasePtr, Offset, AM); 4676 else 4677 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 4678 BasePtr, Offset, AM); 4679 ++PreIndexedNodes; 4680 ++NodesCombined; 4681 DEBUG(errs() << "\nReplacing.4 "; 4682 N->dump(&DAG); 4683 errs() << "\nWith: "; 4684 Result.getNode()->dump(&DAG); 4685 errs() << '\n'); 4686 WorkListRemover DeadNodes(*this); 4687 if (isLoad) { 4688 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 4689 &DeadNodes); 4690 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 4691 &DeadNodes); 4692 } else { 4693 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 4694 &DeadNodes); 4695 } 4696 4697 // Finally, since the node is now dead, remove it from the graph. 4698 DAG.DeleteNode(N); 4699 4700 // Replace the uses of Ptr with uses of the updated base value. 4701 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 4702 &DeadNodes); 4703 removeFromWorkList(Ptr.getNode()); 4704 DAG.DeleteNode(Ptr.getNode()); 4705 4706 return true; 4707} 4708 4709/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 4710/// add / sub of the base pointer node into a post-indexed load / store. 4711/// The transformation folded the add / subtract into the new indexed 4712/// load / store effectively and all of its uses are redirected to the 4713/// new load / store. 4714bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 4715 if (!LegalOperations) 4716 return false; 4717 4718 bool isLoad = true; 4719 SDValue Ptr; 4720 EVT VT; 4721 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4722 if (LD->isIndexed()) 4723 return false; 4724 VT = LD->getMemoryVT(); 4725 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 4726 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 4727 return false; 4728 Ptr = LD->getBasePtr(); 4729 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4730 if (ST->isIndexed()) 4731 return false; 4732 VT = ST->getMemoryVT(); 4733 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 4734 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 4735 return false; 4736 Ptr = ST->getBasePtr(); 4737 isLoad = false; 4738 } else { 4739 return false; 4740 } 4741 4742 if (Ptr.getNode()->hasOneUse()) 4743 return false; 4744 4745 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 4746 E = Ptr.getNode()->use_end(); I != E; ++I) { 4747 SDNode *Op = *I; 4748 if (Op == N || 4749 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 4750 continue; 4751 4752 SDValue BasePtr; 4753 SDValue Offset; 4754 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4755 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 4756 if (Ptr == Offset && Op->getOpcode() == ISD::ADD) 4757 std::swap(BasePtr, Offset); 4758 if (Ptr != BasePtr) 4759 continue; 4760 // Don't create a indexed load / store with zero offset. 4761 if (isa<ConstantSDNode>(Offset) && 4762 cast<ConstantSDNode>(Offset)->isNullValue()) 4763 continue; 4764 4765 // Try turning it into a post-indexed load / store except when 4766 // 1) All uses are load / store ops that use it as base ptr. 4767 // 2) Op must be independent of N, i.e. Op is neither a predecessor 4768 // nor a successor of N. Otherwise, if Op is folded that would 4769 // create a cycle. 4770 4771 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 4772 continue; 4773 4774 // Check for #1. 4775 bool TryNext = false; 4776 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), 4777 EE = BasePtr.getNode()->use_end(); II != EE; ++II) { 4778 SDNode *Use = *II; 4779 if (Use == Ptr.getNode()) 4780 continue; 4781 4782 // If all the uses are load / store addresses, then don't do the 4783 // transformation. 4784 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 4785 bool RealUse = false; 4786 for (SDNode::use_iterator III = Use->use_begin(), 4787 EEE = Use->use_end(); III != EEE; ++III) { 4788 SDNode *UseUse = *III; 4789 if (!((UseUse->getOpcode() == ISD::LOAD && 4790 cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) || 4791 (UseUse->getOpcode() == ISD::STORE && 4792 cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use))) 4793 RealUse = true; 4794 } 4795 4796 if (!RealUse) { 4797 TryNext = true; 4798 break; 4799 } 4800 } 4801 } 4802 4803 if (TryNext) 4804 continue; 4805 4806 // Check for #2 4807 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 4808 SDValue Result = isLoad 4809 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 4810 BasePtr, Offset, AM) 4811 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 4812 BasePtr, Offset, AM); 4813 ++PostIndexedNodes; 4814 ++NodesCombined; 4815 DEBUG(errs() << "\nReplacing.5 "; 4816 N->dump(&DAG); 4817 errs() << "\nWith: "; 4818 Result.getNode()->dump(&DAG); 4819 errs() << '\n'); 4820 WorkListRemover DeadNodes(*this); 4821 if (isLoad) { 4822 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 4823 &DeadNodes); 4824 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 4825 &DeadNodes); 4826 } else { 4827 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 4828 &DeadNodes); 4829 } 4830 4831 // Finally, since the node is now dead, remove it from the graph. 4832 DAG.DeleteNode(N); 4833 4834 // Replace the uses of Use with uses of the updated base value. 4835 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 4836 Result.getValue(isLoad ? 1 : 0), 4837 &DeadNodes); 4838 removeFromWorkList(Op); 4839 DAG.DeleteNode(Op); 4840 return true; 4841 } 4842 } 4843 } 4844 4845 return false; 4846} 4847 4848SDValue DAGCombiner::visitLOAD(SDNode *N) { 4849 LoadSDNode *LD = cast<LoadSDNode>(N); 4850 SDValue Chain = LD->getChain(); 4851 SDValue Ptr = LD->getBasePtr(); 4852 4853 // Try to infer better alignment information than the load already has. 4854 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) { 4855 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 4856 if (Align > LD->getAlignment()) 4857 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(), 4858 LD->getValueType(0), 4859 Chain, Ptr, LD->getSrcValue(), 4860 LD->getSrcValueOffset(), LD->getMemoryVT(), 4861 LD->isVolatile(), Align); 4862 } 4863 } 4864 4865 // If load is not volatile and there are no uses of the loaded value (and 4866 // the updated indexed value in case of indexed loads), change uses of the 4867 // chain value into uses of the chain input (i.e. delete the dead load). 4868 if (!LD->isVolatile()) { 4869 if (N->getValueType(1) == MVT::Other) { 4870 // Unindexed loads. 4871 if (N->hasNUsesOfValue(0, 0)) { 4872 // It's not safe to use the two value CombineTo variant here. e.g. 4873 // v1, chain2 = load chain1, loc 4874 // v2, chain3 = load chain2, loc 4875 // v3 = add v2, c 4876 // Now we replace use of chain2 with chain1. This makes the second load 4877 // isomorphic to the one we are deleting, and thus makes this load live. 4878 DEBUG(errs() << "\nReplacing.6 "; 4879 N->dump(&DAG); 4880 errs() << "\nWith chain: "; 4881 Chain.getNode()->dump(&DAG); 4882 errs() << "\n"); 4883 WorkListRemover DeadNodes(*this); 4884 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes); 4885 4886 if (N->use_empty()) { 4887 removeFromWorkList(N); 4888 DAG.DeleteNode(N); 4889 } 4890 4891 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4892 } 4893 } else { 4894 // Indexed loads. 4895 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 4896 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 4897 SDValue Undef = DAG.getUNDEF(N->getValueType(0)); 4898 DEBUG(errs() << "\nReplacing.6 "; 4899 N->dump(&DAG); 4900 errs() << "\nWith: "; 4901 Undef.getNode()->dump(&DAG); 4902 errs() << " and 2 other values\n"); 4903 WorkListRemover DeadNodes(*this); 4904 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes); 4905 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 4906 DAG.getUNDEF(N->getValueType(1)), 4907 &DeadNodes); 4908 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes); 4909 removeFromWorkList(N); 4910 DAG.DeleteNode(N); 4911 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4912 } 4913 } 4914 } 4915 4916 // If this load is directly stored, replace the load value with the stored 4917 // value. 4918 // TODO: Handle store large -> read small portion. 4919 // TODO: Handle TRUNCSTORE/LOADEXT 4920 if (LD->getExtensionType() == ISD::NON_EXTLOAD && 4921 !LD->isVolatile()) { 4922 if (ISD::isNON_TRUNCStore(Chain.getNode())) { 4923 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 4924 if (PrevST->getBasePtr() == Ptr && 4925 PrevST->getValue().getValueType() == N->getValueType(0)) 4926 return CombineTo(N, Chain.getOperand(1), Chain); 4927 } 4928 } 4929 4930 if (CombinerAA) { 4931 // Walk up chain skipping non-aliasing memory nodes. 4932 SDValue BetterChain = FindBetterChain(N, Chain); 4933 4934 // If there is a better chain. 4935 if (Chain != BetterChain) { 4936 SDValue ReplLoad; 4937 4938 // Replace the chain to void dependency. 4939 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 4940 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(), 4941 BetterChain, Ptr, 4942 LD->getSrcValue(), LD->getSrcValueOffset(), 4943 LD->isVolatile(), LD->getAlignment()); 4944 } else { 4945 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(), 4946 LD->getValueType(0), 4947 BetterChain, Ptr, LD->getSrcValue(), 4948 LD->getSrcValueOffset(), 4949 LD->getMemoryVT(), 4950 LD->isVolatile(), 4951 LD->getAlignment()); 4952 } 4953 4954 // Create token factor to keep old chain connected. 4955 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 4956 MVT::Other, Chain, ReplLoad.getValue(1)); 4957 4958 // Make sure the new and old chains are cleaned up. 4959 AddToWorkList(Token.getNode()); 4960 4961 // Replace uses with load result and token factor. Don't add users 4962 // to work list. 4963 return CombineTo(N, ReplLoad.getValue(0), Token, false); 4964 } 4965 } 4966 4967 // Try transforming N to an indexed load. 4968 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4969 return SDValue(N, 0); 4970 4971 return SDValue(); 4972} 4973 4974 4975/// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is 4976/// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some 4977/// of the loaded bits, try narrowing the load and store if it would end up 4978/// being a win for performance or code size. 4979SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) { 4980 StoreSDNode *ST = cast<StoreSDNode>(N); 4981 if (ST->isVolatile()) 4982 return SDValue(); 4983 4984 SDValue Chain = ST->getChain(); 4985 SDValue Value = ST->getValue(); 4986 SDValue Ptr = ST->getBasePtr(); 4987 EVT VT = Value.getValueType(); 4988 4989 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse()) 4990 return SDValue(); 4991 4992 unsigned Opc = Value.getOpcode(); 4993 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) || 4994 Value.getOperand(1).getOpcode() != ISD::Constant) 4995 return SDValue(); 4996 4997 SDValue N0 = Value.getOperand(0); 4998 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse()) { 4999 LoadSDNode *LD = cast<LoadSDNode>(N0); 5000 if (LD->getBasePtr() != Ptr) 5001 return SDValue(); 5002 5003 // Find the type to narrow it the load / op / store to. 5004 SDValue N1 = Value.getOperand(1); 5005 unsigned BitWidth = N1.getValueSizeInBits(); 5006 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue(); 5007 if (Opc == ISD::AND) 5008 Imm ^= APInt::getAllOnesValue(BitWidth); 5009 if (Imm == 0 || Imm.isAllOnesValue()) 5010 return SDValue(); 5011 unsigned ShAmt = Imm.countTrailingZeros(); 5012 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1; 5013 unsigned NewBW = NextPowerOf2(MSB - ShAmt); 5014 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 5015 while (NewBW < BitWidth && 5016 !(TLI.isOperationLegalOrCustom(Opc, NewVT) && 5017 TLI.isNarrowingProfitable(VT, NewVT))) { 5018 NewBW = NextPowerOf2(NewBW); 5019 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 5020 } 5021 if (NewBW >= BitWidth) 5022 return SDValue(); 5023 5024 // If the lsb changed does not start at the type bitwidth boundary, 5025 // start at the previous one. 5026 if (ShAmt % NewBW) 5027 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW; 5028 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW); 5029 if ((Imm & Mask) == Imm) { 5030 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW); 5031 if (Opc == ISD::AND) 5032 NewImm ^= APInt::getAllOnesValue(NewBW); 5033 uint64_t PtrOff = ShAmt / 8; 5034 // For big endian targets, we need to adjust the offset to the pointer to 5035 // load the correct bytes. 5036 if (TLI.isBigEndian()) 5037 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff; 5038 5039 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff); 5040 if (NewAlign < 5041 TLI.getTargetData()->getABITypeAlignment(NewVT.getTypeForEVT(*DAG.getContext()))) 5042 return SDValue(); 5043 5044 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(), 5045 Ptr.getValueType(), Ptr, 5046 DAG.getConstant(PtrOff, Ptr.getValueType())); 5047 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(), 5048 LD->getChain(), NewPtr, 5049 LD->getSrcValue(), LD->getSrcValueOffset(), 5050 LD->isVolatile(), NewAlign); 5051 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD, 5052 DAG.getConstant(NewImm, NewVT)); 5053 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(), 5054 NewVal, NewPtr, 5055 ST->getSrcValue(), ST->getSrcValueOffset(), 5056 false, NewAlign); 5057 5058 AddToWorkList(NewPtr.getNode()); 5059 AddToWorkList(NewLD.getNode()); 5060 AddToWorkList(NewVal.getNode()); 5061 WorkListRemover DeadNodes(*this); 5062 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1), 5063 &DeadNodes); 5064 ++OpsNarrowed; 5065 return NewST; 5066 } 5067 } 5068 5069 return SDValue(); 5070} 5071 5072SDValue DAGCombiner::visitSTORE(SDNode *N) { 5073 StoreSDNode *ST = cast<StoreSDNode>(N); 5074 SDValue Chain = ST->getChain(); 5075 SDValue Value = ST->getValue(); 5076 SDValue Ptr = ST->getBasePtr(); 5077 5078 // Try to infer better alignment information than the store already has. 5079 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) { 5080 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 5081 if (Align > ST->getAlignment()) 5082 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value, 5083 Ptr, ST->getSrcValue(), 5084 ST->getSrcValueOffset(), ST->getMemoryVT(), 5085 ST->isVolatile(), Align); 5086 } 5087 } 5088 5089 // If this is a store of a bit convert, store the input value if the 5090 // resultant store does not need a higher alignment than the original. 5091 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() && 5092 ST->isUnindexed()) { 5093 unsigned OrigAlign = ST->getAlignment(); 5094 EVT SVT = Value.getOperand(0).getValueType(); 5095 unsigned Align = TLI.getTargetData()-> 5096 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext())); 5097 if (Align <= OrigAlign && 5098 ((!LegalOperations && !ST->isVolatile()) || 5099 TLI.isOperationLegalOrCustom(ISD::STORE, SVT))) 5100 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0), 5101 Ptr, ST->getSrcValue(), 5102 ST->getSrcValueOffset(), ST->isVolatile(), OrigAlign); 5103 } 5104 5105 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 5106 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 5107 // NOTE: If the original store is volatile, this transform must not increase 5108 // the number of stores. For example, on x86-32 an f64 can be stored in one 5109 // processor operation but an i64 (which is not legal) requires two. So the 5110 // transform should not be done in this case. 5111 if (Value.getOpcode() != ISD::TargetConstantFP) { 5112 SDValue Tmp; 5113 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) { 5114 default: llvm_unreachable("Unknown FP type"); 5115 case MVT::f80: // We don't do this for these yet. 5116 case MVT::f128: 5117 case MVT::ppcf128: 5118 break; 5119 case MVT::f32: 5120 if (((TLI.isTypeLegal(MVT::i32) || !LegalTypes) && !LegalOperations && 5121 !ST->isVolatile()) || 5122 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 5123 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 5124 bitcastToAPInt().getZExtValue(), MVT::i32); 5125 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 5126 Ptr, ST->getSrcValue(), 5127 ST->getSrcValueOffset(), ST->isVolatile(), 5128 ST->getAlignment()); 5129 } 5130 break; 5131 case MVT::f64: 5132 if (((TLI.isTypeLegal(MVT::i64) || !LegalTypes) && !LegalOperations && 5133 !ST->isVolatile()) || 5134 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) { 5135 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 5136 getZExtValue(), MVT::i64); 5137 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 5138 Ptr, ST->getSrcValue(), 5139 ST->getSrcValueOffset(), ST->isVolatile(), 5140 ST->getAlignment()); 5141 } else if (!ST->isVolatile() && 5142 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 5143 // Many FP stores are not made apparent until after legalize, e.g. for 5144 // argument passing. Since this is so common, custom legalize the 5145 // 64-bit integer store into two 32-bit stores. 5146 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); 5147 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 5148 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 5149 if (TLI.isBigEndian()) std::swap(Lo, Hi); 5150 5151 int SVOffset = ST->getSrcValueOffset(); 5152 unsigned Alignment = ST->getAlignment(); 5153 bool isVolatile = ST->isVolatile(); 5154 5155 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo, 5156 Ptr, ST->getSrcValue(), 5157 ST->getSrcValueOffset(), 5158 isVolatile, ST->getAlignment()); 5159 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr, 5160 DAG.getConstant(4, Ptr.getValueType())); 5161 SVOffset += 4; 5162 Alignment = MinAlign(Alignment, 4U); 5163 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi, 5164 Ptr, ST->getSrcValue(), 5165 SVOffset, isVolatile, Alignment); 5166 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 5167 St0, St1); 5168 } 5169 5170 break; 5171 } 5172 } 5173 } 5174 5175 if (CombinerAA) { 5176 // Walk up chain skipping non-aliasing memory nodes. 5177 SDValue BetterChain = FindBetterChain(N, Chain); 5178 5179 // If there is a better chain. 5180 if (Chain != BetterChain) { 5181 SDValue ReplStore; 5182 5183 // Replace the chain to avoid dependency. 5184 if (ST->isTruncatingStore()) { 5185 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr, 5186 ST->getSrcValue(),ST->getSrcValueOffset(), 5187 ST->getMemoryVT(), 5188 ST->isVolatile(), ST->getAlignment()); 5189 } else { 5190 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr, 5191 ST->getSrcValue(), ST->getSrcValueOffset(), 5192 ST->isVolatile(), ST->getAlignment()); 5193 } 5194 5195 // Create token to keep both nodes around. 5196 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 5197 MVT::Other, Chain, ReplStore); 5198 5199 // Make sure the new and old chains are cleaned up. 5200 AddToWorkList(Token.getNode()); 5201 5202 // Don't add users to work list. 5203 return CombineTo(N, Token, false); 5204 } 5205 } 5206 5207 // Try transforming N to an indexed store. 5208 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 5209 return SDValue(N, 0); 5210 5211 // FIXME: is there such a thing as a truncating indexed store? 5212 if (ST->isTruncatingStore() && ST->isUnindexed() && 5213 Value.getValueType().isInteger()) { 5214 // See if we can simplify the input to this truncstore with knowledge that 5215 // only the low bits are being used. For example: 5216 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 5217 SDValue Shorter = 5218 GetDemandedBits(Value, 5219 APInt::getLowBitsSet(Value.getValueSizeInBits(), 5220 ST->getMemoryVT().getSizeInBits())); 5221 AddToWorkList(Value.getNode()); 5222 if (Shorter.getNode()) 5223 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter, 5224 Ptr, ST->getSrcValue(), 5225 ST->getSrcValueOffset(), ST->getMemoryVT(), 5226 ST->isVolatile(), ST->getAlignment()); 5227 5228 // Otherwise, see if we can simplify the operation with 5229 // SimplifyDemandedBits, which only works if the value has a single use. 5230 if (SimplifyDemandedBits(Value, 5231 APInt::getLowBitsSet( 5232 Value.getValueType().getScalarType().getSizeInBits(), 5233 ST->getMemoryVT().getSizeInBits()))) 5234 return SDValue(N, 0); 5235 } 5236 5237 // If this is a load followed by a store to the same location, then the store 5238 // is dead/noop. 5239 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 5240 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 5241 ST->isUnindexed() && !ST->isVolatile() && 5242 // There can't be any side effects between the load and store, such as 5243 // a call or store. 5244 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 5245 // The store is dead, remove it. 5246 return Chain; 5247 } 5248 } 5249 5250 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 5251 // truncating store. We can do this even if this is already a truncstore. 5252 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 5253 && Value.getNode()->hasOneUse() && ST->isUnindexed() && 5254 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 5255 ST->getMemoryVT())) { 5256 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0), 5257 Ptr, ST->getSrcValue(), 5258 ST->getSrcValueOffset(), ST->getMemoryVT(), 5259 ST->isVolatile(), ST->getAlignment()); 5260 } 5261 5262 return ReduceLoadOpStoreWidth(N); 5263} 5264 5265SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 5266 SDValue InVec = N->getOperand(0); 5267 SDValue InVal = N->getOperand(1); 5268 SDValue EltNo = N->getOperand(2); 5269 5270 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 5271 // vector with the inserted element. 5272 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 5273 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5274 SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(), 5275 InVec.getNode()->op_end()); 5276 if (Elt < Ops.size()) 5277 Ops[Elt] = InVal; 5278 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5279 InVec.getValueType(), &Ops[0], Ops.size()); 5280 } 5281 // If the invec is an UNDEF and if EltNo is a constant, create a new 5282 // BUILD_VECTOR with undef elements and the inserted element. 5283 if (!LegalOperations && InVec.getOpcode() == ISD::UNDEF && 5284 isa<ConstantSDNode>(EltNo)) { 5285 EVT VT = InVec.getValueType(); 5286 EVT EltVT = VT.getVectorElementType(); 5287 unsigned NElts = VT.getVectorNumElements(); 5288 SmallVector<SDValue, 8> Ops(NElts, DAG.getUNDEF(EltVT)); 5289 5290 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5291 if (Elt < Ops.size()) 5292 Ops[Elt] = InVal; 5293 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5294 InVec.getValueType(), &Ops[0], Ops.size()); 5295 } 5296 return SDValue(); 5297} 5298 5299SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 5300 // (vextract (scalar_to_vector val, 0) -> val 5301 SDValue InVec = N->getOperand(0); 5302 5303 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 5304 // If the operand is wider than the vector element type then it is implicitly 5305 // truncated. Make that explicit here. 5306 EVT EltVT = InVec.getValueType().getVectorElementType(); 5307 SDValue InOp = InVec.getOperand(0); 5308 if (InOp.getValueType() != EltVT) 5309 return DAG.getNode(ISD::TRUNCATE, InVec.getDebugLoc(), EltVT, InOp); 5310 return InOp; 5311 } 5312 5313 // Perform only after legalization to ensure build_vector / vector_shuffle 5314 // optimizations have already been done. 5315 if (!LegalOperations) return SDValue(); 5316 5317 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 5318 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 5319 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 5320 SDValue EltNo = N->getOperand(1); 5321 5322 if (isa<ConstantSDNode>(EltNo)) { 5323 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5324 bool NewLoad = false; 5325 bool BCNumEltsChanged = false; 5326 EVT VT = InVec.getValueType(); 5327 EVT ExtVT = VT.getVectorElementType(); 5328 EVT LVT = ExtVT; 5329 5330 if (InVec.getOpcode() == ISD::BIT_CONVERT) { 5331 EVT BCVT = InVec.getOperand(0).getValueType(); 5332 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType())) 5333 return SDValue(); 5334 if (VT.getVectorNumElements() != BCVT.getVectorNumElements()) 5335 BCNumEltsChanged = true; 5336 InVec = InVec.getOperand(0); 5337 ExtVT = BCVT.getVectorElementType(); 5338 NewLoad = true; 5339 } 5340 5341 LoadSDNode *LN0 = NULL; 5342 const ShuffleVectorSDNode *SVN = NULL; 5343 if (ISD::isNormalLoad(InVec.getNode())) { 5344 LN0 = cast<LoadSDNode>(InVec); 5345 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 5346 InVec.getOperand(0).getValueType() == ExtVT && 5347 ISD::isNormalLoad(InVec.getOperand(0).getNode())) { 5348 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 5349 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) { 5350 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 5351 // => 5352 // (load $addr+1*size) 5353 5354 // If the bit convert changed the number of elements, it is unsafe 5355 // to examine the mask. 5356 if (BCNumEltsChanged) 5357 return SDValue(); 5358 5359 // Select the input vector, guarding against out of range extract vector. 5360 unsigned NumElems = VT.getVectorNumElements(); 5361 int Idx = (Elt > NumElems) ? -1 : SVN->getMaskElt(Elt); 5362 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 5363 5364 if (InVec.getOpcode() == ISD::BIT_CONVERT) 5365 InVec = InVec.getOperand(0); 5366 if (ISD::isNormalLoad(InVec.getNode())) { 5367 LN0 = cast<LoadSDNode>(InVec); 5368 Elt = (Idx < (int)NumElems) ? Idx : Idx - NumElems; 5369 } 5370 } 5371 5372 if (!LN0 || !LN0->hasOneUse() || LN0->isVolatile()) 5373 return SDValue(); 5374 5375 unsigned Align = LN0->getAlignment(); 5376 if (NewLoad) { 5377 // Check the resultant load doesn't need a higher alignment than the 5378 // original load. 5379 unsigned NewAlign = 5380 TLI.getTargetData()->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext())); 5381 5382 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT)) 5383 return SDValue(); 5384 5385 Align = NewAlign; 5386 } 5387 5388 SDValue NewPtr = LN0->getBasePtr(); 5389 if (Elt) { 5390 unsigned PtrOff = LVT.getSizeInBits() * Elt / 8; 5391 EVT PtrType = NewPtr.getValueType(); 5392 if (TLI.isBigEndian()) 5393 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 5394 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr, 5395 DAG.getConstant(PtrOff, PtrType)); 5396 } 5397 5398 return DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr, 5399 LN0->getSrcValue(), LN0->getSrcValueOffset(), 5400 LN0->isVolatile(), Align); 5401 } 5402 5403 return SDValue(); 5404} 5405 5406SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 5407 unsigned NumInScalars = N->getNumOperands(); 5408 EVT VT = N->getValueType(0); 5409 5410 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 5411 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 5412 // at most two distinct vectors, turn this into a shuffle node. 5413 SDValue VecIn1, VecIn2; 5414 for (unsigned i = 0; i != NumInScalars; ++i) { 5415 // Ignore undef inputs. 5416 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 5417 5418 // If this input is something other than a EXTRACT_VECTOR_ELT with a 5419 // constant index, bail out. 5420 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 5421 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 5422 VecIn1 = VecIn2 = SDValue(0, 0); 5423 break; 5424 } 5425 5426 // If the input vector type disagrees with the result of the build_vector, 5427 // we can't make a shuffle. 5428 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 5429 if (ExtractedFromVec.getValueType() != VT) { 5430 VecIn1 = VecIn2 = SDValue(0, 0); 5431 break; 5432 } 5433 5434 // Otherwise, remember this. We allow up to two distinct input vectors. 5435 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 5436 continue; 5437 5438 if (VecIn1.getNode() == 0) { 5439 VecIn1 = ExtractedFromVec; 5440 } else if (VecIn2.getNode() == 0) { 5441 VecIn2 = ExtractedFromVec; 5442 } else { 5443 // Too many inputs. 5444 VecIn1 = VecIn2 = SDValue(0, 0); 5445 break; 5446 } 5447 } 5448 5449 // If everything is good, we can make a shuffle operation. 5450 if (VecIn1.getNode()) { 5451 SmallVector<int, 8> Mask; 5452 for (unsigned i = 0; i != NumInScalars; ++i) { 5453 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 5454 Mask.push_back(-1); 5455 continue; 5456 } 5457 5458 // If extracting from the first vector, just use the index directly. 5459 SDValue Extract = N->getOperand(i); 5460 SDValue ExtVal = Extract.getOperand(1); 5461 if (Extract.getOperand(0) == VecIn1) { 5462 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 5463 if (ExtIndex > VT.getVectorNumElements()) 5464 return SDValue(); 5465 5466 Mask.push_back(ExtIndex); 5467 continue; 5468 } 5469 5470 // Otherwise, use InIdx + VecSize 5471 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 5472 Mask.push_back(Idx+NumInScalars); 5473 } 5474 5475 // Add count and size info. 5476 if (!TLI.isTypeLegal(VT) && LegalTypes) 5477 return SDValue(); 5478 5479 // Return the new VECTOR_SHUFFLE node. 5480 SDValue Ops[2]; 5481 Ops[0] = VecIn1; 5482 Ops[1] = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT); 5483 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]); 5484 } 5485 5486 return SDValue(); 5487} 5488 5489SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 5490 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 5491 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 5492 // inputs come from at most two distinct vectors, turn this into a shuffle 5493 // node. 5494 5495 // If we only have one input vector, we don't need to do any concatenation. 5496 if (N->getNumOperands() == 1) 5497 return N->getOperand(0); 5498 5499 return SDValue(); 5500} 5501 5502SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 5503 return SDValue(); 5504 5505 EVT VT = N->getValueType(0); 5506 unsigned NumElts = VT.getVectorNumElements(); 5507 5508 SDValue N0 = N->getOperand(0); 5509 5510 assert(N0.getValueType().getVectorNumElements() == NumElts && 5511 "Vector shuffle must be normalized in DAG"); 5512 5513 // FIXME: implement canonicalizations from DAG.getVectorShuffle() 5514 5515 // If it is a splat, check if the argument vector is a build_vector with 5516 // all scalar elements the same. 5517 if (cast<ShuffleVectorSDNode>(N)->isSplat()) { 5518 SDNode *V = N0.getNode(); 5519 5520 5521 // If this is a bit convert that changes the element type of the vector but 5522 // not the number of vector elements, look through it. Be careful not to 5523 // look though conversions that change things like v4f32 to v2f64. 5524 if (V->getOpcode() == ISD::BIT_CONVERT) { 5525 SDValue ConvInput = V->getOperand(0); 5526 if (ConvInput.getValueType().isVector() && 5527 ConvInput.getValueType().getVectorNumElements() == NumElts) 5528 V = ConvInput.getNode(); 5529 } 5530 5531 if (V->getOpcode() == ISD::BUILD_VECTOR) { 5532 unsigned NumElems = V->getNumOperands(); 5533 unsigned BaseIdx = cast<ShuffleVectorSDNode>(N)->getSplatIndex(); 5534 if (NumElems > BaseIdx) { 5535 SDValue Base; 5536 bool AllSame = true; 5537 for (unsigned i = 0; i != NumElems; ++i) { 5538 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 5539 Base = V->getOperand(i); 5540 break; 5541 } 5542 } 5543 // Splat of <u, u, u, u>, return <u, u, u, u> 5544 if (!Base.getNode()) 5545 return N0; 5546 for (unsigned i = 0; i != NumElems; ++i) { 5547 if (V->getOperand(i) != Base) { 5548 AllSame = false; 5549 break; 5550 } 5551 } 5552 // Splat of <x, x, x, x>, return <x, x, x, x> 5553 if (AllSame) 5554 return N0; 5555 } 5556 } 5557 } 5558 return SDValue(); 5559} 5560 5561/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 5562/// an AND to a vector_shuffle with the destination vector and a zero vector. 5563/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 5564/// vector_shuffle V, Zero, <0, 4, 2, 4> 5565SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 5566 EVT VT = N->getValueType(0); 5567 DebugLoc dl = N->getDebugLoc(); 5568 SDValue LHS = N->getOperand(0); 5569 SDValue RHS = N->getOperand(1); 5570 if (N->getOpcode() == ISD::AND) { 5571 if (RHS.getOpcode() == ISD::BIT_CONVERT) 5572 RHS = RHS.getOperand(0); 5573 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 5574 SmallVector<int, 8> Indices; 5575 unsigned NumElts = RHS.getNumOperands(); 5576 for (unsigned i = 0; i != NumElts; ++i) { 5577 SDValue Elt = RHS.getOperand(i); 5578 if (!isa<ConstantSDNode>(Elt)) 5579 return SDValue(); 5580 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 5581 Indices.push_back(i); 5582 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 5583 Indices.push_back(NumElts); 5584 else 5585 return SDValue(); 5586 } 5587 5588 // Let's see if the target supports this vector_shuffle. 5589 EVT RVT = RHS.getValueType(); 5590 if (!TLI.isVectorClearMaskLegal(Indices, RVT)) 5591 return SDValue(); 5592 5593 // Return the new VECTOR_SHUFFLE node. 5594 EVT EltVT = RVT.getVectorElementType(); 5595 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(), 5596 DAG.getConstant(0, EltVT)); 5597 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5598 RVT, &ZeroOps[0], ZeroOps.size()); 5599 LHS = DAG.getNode(ISD::BIT_CONVERT, dl, RVT, LHS); 5600 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]); 5601 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Shuf); 5602 } 5603 } 5604 5605 return SDValue(); 5606} 5607 5608/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 5609SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 5610 // After legalize, the target may be depending on adds and other 5611 // binary ops to provide legal ways to construct constants or other 5612 // things. Simplifying them may result in a loss of legality. 5613 if (LegalOperations) return SDValue(); 5614 5615 EVT VT = N->getValueType(0); 5616 assert(VT.isVector() && "SimplifyVBinOp only works on vectors!"); 5617 5618 EVT EltType = VT.getVectorElementType(); 5619 SDValue LHS = N->getOperand(0); 5620 SDValue RHS = N->getOperand(1); 5621 SDValue Shuffle = XformToShuffleWithZero(N); 5622 if (Shuffle.getNode()) return Shuffle; 5623 5624 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 5625 // this operation. 5626 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 5627 RHS.getOpcode() == ISD::BUILD_VECTOR) { 5628 SmallVector<SDValue, 8> Ops; 5629 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 5630 SDValue LHSOp = LHS.getOperand(i); 5631 SDValue RHSOp = RHS.getOperand(i); 5632 // If these two elements can't be folded, bail out. 5633 if ((LHSOp.getOpcode() != ISD::UNDEF && 5634 LHSOp.getOpcode() != ISD::Constant && 5635 LHSOp.getOpcode() != ISD::ConstantFP) || 5636 (RHSOp.getOpcode() != ISD::UNDEF && 5637 RHSOp.getOpcode() != ISD::Constant && 5638 RHSOp.getOpcode() != ISD::ConstantFP)) 5639 break; 5640 5641 // Can't fold divide by zero. 5642 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 5643 N->getOpcode() == ISD::FDIV) { 5644 if ((RHSOp.getOpcode() == ISD::Constant && 5645 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) || 5646 (RHSOp.getOpcode() == ISD::ConstantFP && 5647 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero())) 5648 break; 5649 } 5650 5651 Ops.push_back(DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), 5652 EltType, LHSOp, RHSOp)); 5653 AddToWorkList(Ops.back().getNode()); 5654 assert((Ops.back().getOpcode() == ISD::UNDEF || 5655 Ops.back().getOpcode() == ISD::Constant || 5656 Ops.back().getOpcode() == ISD::ConstantFP) && 5657 "Scalar binop didn't fold!"); 5658 } 5659 5660 if (Ops.size() == LHS.getNumOperands()) { 5661 EVT VT = LHS.getValueType(); 5662 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 5663 &Ops[0], Ops.size()); 5664 } 5665 } 5666 5667 return SDValue(); 5668} 5669 5670SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0, 5671 SDValue N1, SDValue N2){ 5672 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 5673 5674 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2, 5675 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 5676 5677 // If we got a simplified select_cc node back from SimplifySelectCC, then 5678 // break it down into a new SETCC node, and a new SELECT node, and then return 5679 // the SELECT node, since we were called with a SELECT node. 5680 if (SCC.getNode()) { 5681 // Check to see if we got a select_cc back (to turn into setcc/select). 5682 // Otherwise, just return whatever node we got back, like fabs. 5683 if (SCC.getOpcode() == ISD::SELECT_CC) { 5684 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(), 5685 N0.getValueType(), 5686 SCC.getOperand(0), SCC.getOperand(1), 5687 SCC.getOperand(4)); 5688 AddToWorkList(SETCC.getNode()); 5689 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(), 5690 SCC.getOperand(2), SCC.getOperand(3), SETCC); 5691 } 5692 5693 return SCC; 5694 } 5695 return SDValue(); 5696} 5697 5698/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 5699/// are the two values being selected between, see if we can simplify the 5700/// select. Callers of this should assume that TheSelect is deleted if this 5701/// returns true. As such, they should return the appropriate thing (e.g. the 5702/// node) back to the top-level of the DAG combiner loop to avoid it being 5703/// looked at. 5704bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 5705 SDValue RHS) { 5706 5707 // If this is a select from two identical things, try to pull the operation 5708 // through the select. 5709 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 5710 // If this is a load and the token chain is identical, replace the select 5711 // of two loads with a load through a select of the address to load from. 5712 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 5713 // constants have been dropped into the constant pool. 5714 if (LHS.getOpcode() == ISD::LOAD && 5715 // Do not let this transformation reduce the number of volatile loads. 5716 !cast<LoadSDNode>(LHS)->isVolatile() && 5717 !cast<LoadSDNode>(RHS)->isVolatile() && 5718 // Token chains must be identical. 5719 LHS.getOperand(0) == RHS.getOperand(0)) { 5720 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 5721 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 5722 5723 // If this is an EXTLOAD, the VT's must match. 5724 if (LLD->getMemoryVT() == RLD->getMemoryVT()) { 5725 // FIXME: this discards src value information. This is 5726 // over-conservative. It would be beneficial to be able to remember 5727 // both potential memory locations. 5728 SDValue Addr; 5729 if (TheSelect->getOpcode() == ISD::SELECT) { 5730 // Check that the condition doesn't reach either load. If so, folding 5731 // this will induce a cycle into the DAG. 5732 if ((!LLD->hasAnyUseOfValue(1) || 5733 !LLD->isPredecessorOf(TheSelect->getOperand(0).getNode())) && 5734 (!RLD->hasAnyUseOfValue(1) || 5735 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()))) { 5736 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(), 5737 LLD->getBasePtr().getValueType(), 5738 TheSelect->getOperand(0), LLD->getBasePtr(), 5739 RLD->getBasePtr()); 5740 } 5741 } else { 5742 // Check that the condition doesn't reach either load. If so, folding 5743 // this will induce a cycle into the DAG. 5744 if ((!LLD->hasAnyUseOfValue(1) || 5745 (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5746 !LLD->isPredecessorOf(TheSelect->getOperand(1).getNode()))) && 5747 (!RLD->hasAnyUseOfValue(1) || 5748 (!RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5749 !RLD->isPredecessorOf(TheSelect->getOperand(1).getNode())))) { 5750 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(), 5751 LLD->getBasePtr().getValueType(), 5752 TheSelect->getOperand(0), 5753 TheSelect->getOperand(1), 5754 LLD->getBasePtr(), RLD->getBasePtr(), 5755 TheSelect->getOperand(4)); 5756 } 5757 } 5758 5759 if (Addr.getNode()) { 5760 SDValue Load; 5761 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) { 5762 Load = DAG.getLoad(TheSelect->getValueType(0), 5763 TheSelect->getDebugLoc(), 5764 LLD->getChain(), 5765 Addr, 0, 0, 5766 LLD->isVolatile(), 5767 LLD->getAlignment()); 5768 } else { 5769 Load = DAG.getExtLoad(LLD->getExtensionType(), 5770 TheSelect->getDebugLoc(), 5771 TheSelect->getValueType(0), 5772 LLD->getChain(), Addr, 0, 0, 5773 LLD->getMemoryVT(), 5774 LLD->isVolatile(), 5775 LLD->getAlignment()); 5776 } 5777 5778 // Users of the select now use the result of the load. 5779 CombineTo(TheSelect, Load); 5780 5781 // Users of the old loads now use the new load's chain. We know the 5782 // old-load value is dead now. 5783 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); 5784 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); 5785 return true; 5786 } 5787 } 5788 } 5789 } 5790 5791 return false; 5792} 5793 5794/// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3 5795/// where 'cond' is the comparison specified by CC. 5796SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, 5797 SDValue N2, SDValue N3, 5798 ISD::CondCode CC, bool NotExtCompare) { 5799 // (x ? y : y) -> y. 5800 if (N2 == N3) return N2; 5801 5802 EVT VT = N2.getValueType(); 5803 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 5804 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 5805 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); 5806 5807 // Determine if the condition we're dealing with is constant 5808 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 5809 N0, N1, CC, DL, false); 5810 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 5811 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode()); 5812 5813 // fold select_cc true, x, y -> x 5814 if (SCCC && !SCCC->isNullValue()) 5815 return N2; 5816 // fold select_cc false, x, y -> y 5817 if (SCCC && SCCC->isNullValue()) 5818 return N3; 5819 5820 // Check to see if we can simplify the select into an fabs node 5821 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 5822 // Allow either -0.0 or 0.0 5823 if (CFP->getValueAPF().isZero()) { 5824 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 5825 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 5826 N0 == N2 && N3.getOpcode() == ISD::FNEG && 5827 N2 == N3.getOperand(0)) 5828 return DAG.getNode(ISD::FABS, DL, VT, N0); 5829 5830 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 5831 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 5832 N0 == N3 && N2.getOpcode() == ISD::FNEG && 5833 N2.getOperand(0) == N3) 5834 return DAG.getNode(ISD::FABS, DL, VT, N3); 5835 } 5836 } 5837 5838 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)" 5839 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0 5840 // in it. This is a win when the constant is not otherwise available because 5841 // it replaces two constant pool loads with one. We only do this if the FP 5842 // type is known to be legal, because if it isn't, then we are before legalize 5843 // types an we want the other legalization to happen first (e.g. to avoid 5844 // messing with soft float) and if the ConstantFP is not legal, because if 5845 // it is legal, we may not need to store the FP constant in a constant pool. 5846 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2)) 5847 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) { 5848 if (TLI.isTypeLegal(N2.getValueType()) && 5849 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) != 5850 TargetLowering::Legal) && 5851 // If both constants have multiple uses, then we won't need to do an 5852 // extra load, they are likely around in registers for other users. 5853 (TV->hasOneUse() || FV->hasOneUse())) { 5854 Constant *Elts[] = { 5855 const_cast<ConstantFP*>(FV->getConstantFPValue()), 5856 const_cast<ConstantFP*>(TV->getConstantFPValue()) 5857 }; 5858 const Type *FPTy = Elts[0]->getType(); 5859 const TargetData &TD = *TLI.getTargetData(); 5860 5861 // Create a ConstantArray of the two constants. 5862 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts, 2); 5863 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(), 5864 TD.getPrefTypeAlignment(FPTy)); 5865 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 5866 5867 // Get the offsets to the 0 and 1 element of the array so that we can 5868 // select between them. 5869 SDValue Zero = DAG.getIntPtrConstant(0); 5870 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType()); 5871 SDValue One = DAG.getIntPtrConstant(EltSize); 5872 5873 SDValue Cond = DAG.getSetCC(DL, 5874 TLI.getSetCCResultType(N0.getValueType()), 5875 N0, N1, CC); 5876 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(), 5877 Cond, One, Zero); 5878 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx, 5879 CstOffset); 5880 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx, 5881 PseudoSourceValue::getConstantPool(), 0, false, 5882 Alignment); 5883 5884 } 5885 } 5886 5887 // Check to see if we can perform the "gzip trick", transforming 5888 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A) 5889 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 5890 N0.getValueType().isInteger() && 5891 N2.getValueType().isInteger() && 5892 (N1C->isNullValue() || // (a < 0) ? b : 0 5893 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 5894 EVT XType = N0.getValueType(); 5895 EVT AType = N2.getValueType(); 5896 if (XType.bitsGE(AType)) { 5897 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 5898 // single-bit constant. 5899 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 5900 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 5901 ShCtV = XType.getSizeInBits()-ShCtV-1; 5902 SDValue ShCt = DAG.getConstant(ShCtV, getShiftAmountTy()); 5903 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), 5904 XType, N0, ShCt); 5905 AddToWorkList(Shift.getNode()); 5906 5907 if (XType.bitsGT(AType)) { 5908 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 5909 AddToWorkList(Shift.getNode()); 5910 } 5911 5912 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 5913 } 5914 5915 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), 5916 XType, N0, 5917 DAG.getConstant(XType.getSizeInBits()-1, 5918 getShiftAmountTy())); 5919 AddToWorkList(Shift.getNode()); 5920 5921 if (XType.bitsGT(AType)) { 5922 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 5923 AddToWorkList(Shift.getNode()); 5924 } 5925 5926 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 5927 } 5928 } 5929 5930 // fold select C, 16, 0 -> shl C, 4 5931 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 5932 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) { 5933 5934 // If the caller doesn't want us to simplify this into a zext of a compare, 5935 // don't do it. 5936 if (NotExtCompare && N2C->getAPIntValue() == 1) 5937 return SDValue(); 5938 5939 // Get a SetCC of the condition 5940 // FIXME: Should probably make sure that setcc is legal if we ever have a 5941 // target where it isn't. 5942 SDValue Temp, SCC; 5943 // cast from setcc result type to select result type 5944 if (LegalTypes) { 5945 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()), 5946 N0, N1, CC); 5947 if (N2.getValueType().bitsLT(SCC.getValueType())) 5948 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType()); 5949 else 5950 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 5951 N2.getValueType(), SCC); 5952 } else { 5953 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC); 5954 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 5955 N2.getValueType(), SCC); 5956 } 5957 5958 AddToWorkList(SCC.getNode()); 5959 AddToWorkList(Temp.getNode()); 5960 5961 if (N2C->getAPIntValue() == 1) 5962 return Temp; 5963 5964 // shl setcc result by log2 n2c 5965 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp, 5966 DAG.getConstant(N2C->getAPIntValue().logBase2(), 5967 getShiftAmountTy())); 5968 } 5969 5970 // Check to see if this is the equivalent of setcc 5971 // FIXME: Turn all of these into setcc if setcc if setcc is legal 5972 // otherwise, go ahead with the folds. 5973 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 5974 EVT XType = N0.getValueType(); 5975 if (!LegalOperations || 5976 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) { 5977 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC); 5978 if (Res.getValueType() != VT) 5979 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res); 5980 return Res; 5981 } 5982 5983 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X)))) 5984 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 5985 (!LegalOperations || 5986 TLI.isOperationLegal(ISD::CTLZ, XType))) { 5987 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0); 5988 return DAG.getNode(ISD::SRL, DL, XType, Ctlz, 5989 DAG.getConstant(Log2_32(XType.getSizeInBits()), 5990 getShiftAmountTy())); 5991 } 5992 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1)) 5993 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 5994 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(), 5995 XType, DAG.getConstant(0, XType), N0); 5996 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType); 5997 return DAG.getNode(ISD::SRL, DL, XType, 5998 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0), 5999 DAG.getConstant(XType.getSizeInBits()-1, 6000 getShiftAmountTy())); 6001 } 6002 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1)) 6003 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 6004 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0, 6005 DAG.getConstant(XType.getSizeInBits()-1, 6006 getShiftAmountTy())); 6007 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType)); 6008 } 6009 } 6010 6011 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 6012 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 6013 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 6014 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) && 6015 N2.getOperand(0) == N1 && N0.getValueType().isInteger()) { 6016 EVT XType = N0.getValueType(); 6017 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, N0, 6018 DAG.getConstant(XType.getSizeInBits()-1, 6019 getShiftAmountTy())); 6020 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), XType, 6021 N0, Shift); 6022 AddToWorkList(Shift.getNode()); 6023 AddToWorkList(Add.getNode()); 6024 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 6025 } 6026 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X -> 6027 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 6028 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT && 6029 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) { 6030 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 6031 EVT XType = N0.getValueType(); 6032 if (SubC->isNullValue() && XType.isInteger()) { 6033 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, 6034 N0, 6035 DAG.getConstant(XType.getSizeInBits()-1, 6036 getShiftAmountTy())); 6037 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), 6038 XType, N0, Shift); 6039 AddToWorkList(Shift.getNode()); 6040 AddToWorkList(Add.getNode()); 6041 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 6042 } 6043 } 6044 } 6045 6046 return SDValue(); 6047} 6048 6049/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 6050SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0, 6051 SDValue N1, ISD::CondCode Cond, 6052 DebugLoc DL, bool foldBooleans) { 6053 TargetLowering::DAGCombinerInfo 6054 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 6055 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL); 6056} 6057 6058/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 6059/// return a DAG expression to select that will generate the same value by 6060/// multiplying by a magic number. See: 6061/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 6062SDValue DAGCombiner::BuildSDIV(SDNode *N) { 6063 std::vector<SDNode*> Built; 6064 SDValue S = TLI.BuildSDIV(N, DAG, &Built); 6065 6066 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 6067 ii != ee; ++ii) 6068 AddToWorkList(*ii); 6069 return S; 6070} 6071 6072/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 6073/// return a DAG expression to select that will generate the same value by 6074/// multiplying by a magic number. See: 6075/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 6076SDValue DAGCombiner::BuildUDIV(SDNode *N) { 6077 std::vector<SDNode*> Built; 6078 SDValue S = TLI.BuildUDIV(N, DAG, &Built); 6079 6080 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 6081 ii != ee; ++ii) 6082 AddToWorkList(*ii); 6083 return S; 6084} 6085 6086/// FindBaseOffset - Return true if base is a frame index, which is known not 6087// to alias with anything but itself. Provides base object and offset as results. 6088static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset, 6089 GlobalValue *&GV, void *&CV) { 6090 // Assume it is a primitive operation. 6091 Base = Ptr; Offset = 0; GV = 0; CV = 0; 6092 6093 // If it's an adding a simple constant then integrate the offset. 6094 if (Base.getOpcode() == ISD::ADD) { 6095 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 6096 Base = Base.getOperand(0); 6097 Offset += C->getZExtValue(); 6098 } 6099 } 6100 6101 // Return the underlying GlobalValue, and update the Offset. Return false 6102 // for GlobalAddressSDNode since the same GlobalAddress may be represented 6103 // by multiple nodes with different offsets. 6104 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) { 6105 GV = G->getGlobal(); 6106 Offset += G->getOffset(); 6107 return false; 6108 } 6109 6110 // Return the underlying Constant value, and update the Offset. Return false 6111 // for ConstantSDNodes since the same constant pool entry may be represented 6112 // by multiple nodes with different offsets. 6113 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) { 6114 CV = C->isMachineConstantPoolEntry() ? (void *)C->getMachineCPVal() 6115 : (void *)C->getConstVal(); 6116 Offset += C->getOffset(); 6117 return false; 6118 } 6119 // If it's any of the following then it can't alias with anything but itself. 6120 return isa<FrameIndexSDNode>(Base); 6121} 6122 6123/// isAlias - Return true if there is any possibility that the two addresses 6124/// overlap. 6125bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, 6126 const Value *SrcValue1, int SrcValueOffset1, 6127 unsigned SrcValueAlign1, 6128 SDValue Ptr2, int64_t Size2, 6129 const Value *SrcValue2, int SrcValueOffset2, 6130 unsigned SrcValueAlign2) const { 6131 // If they are the same then they must be aliases. 6132 if (Ptr1 == Ptr2) return true; 6133 6134 // Gather base node and offset information. 6135 SDValue Base1, Base2; 6136 int64_t Offset1, Offset2; 6137 GlobalValue *GV1, *GV2; 6138 void *CV1, *CV2; 6139 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1); 6140 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2); 6141 6142 // If they have a same base address then check to see if they overlap. 6143 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2))) 6144 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 6145 6146 // If we know what the bases are, and they aren't identical, then we know they 6147 // cannot alias. 6148 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2)) 6149 return false; 6150 6151 // If we know required SrcValue1 and SrcValue2 have relatively large alignment 6152 // compared to the size and offset of the access, we may be able to prove they 6153 // do not alias. This check is conservative for now to catch cases created by 6154 // splitting vector types. 6155 if ((SrcValueAlign1 == SrcValueAlign2) && 6156 (SrcValueOffset1 != SrcValueOffset2) && 6157 (Size1 == Size2) && (SrcValueAlign1 > Size1)) { 6158 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1; 6159 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1; 6160 6161 // There is no overlap between these relatively aligned accesses of similar 6162 // size, return no alias. 6163 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1) 6164 return false; 6165 } 6166 6167 if (CombinerGlobalAA) { 6168 // Use alias analysis information. 6169 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 6170 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 6171 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 6172 AliasAnalysis::AliasResult AAResult = 6173 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2); 6174 if (AAResult == AliasAnalysis::NoAlias) 6175 return false; 6176 } 6177 6178 // Otherwise we have to assume they alias. 6179 return true; 6180} 6181 6182/// FindAliasInfo - Extracts the relevant alias information from the memory 6183/// node. Returns true if the operand was a load. 6184bool DAGCombiner::FindAliasInfo(SDNode *N, 6185 SDValue &Ptr, int64_t &Size, 6186 const Value *&SrcValue, 6187 int &SrcValueOffset, 6188 unsigned &SrcValueAlign) const { 6189 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 6190 Ptr = LD->getBasePtr(); 6191 Size = LD->getMemoryVT().getSizeInBits() >> 3; 6192 SrcValue = LD->getSrcValue(); 6193 SrcValueOffset = LD->getSrcValueOffset(); 6194 SrcValueAlign = LD->getOriginalAlignment(); 6195 return true; 6196 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 6197 Ptr = ST->getBasePtr(); 6198 Size = ST->getMemoryVT().getSizeInBits() >> 3; 6199 SrcValue = ST->getSrcValue(); 6200 SrcValueOffset = ST->getSrcValueOffset(); 6201 SrcValueAlign = ST->getOriginalAlignment(); 6202 } else { 6203 llvm_unreachable("FindAliasInfo expected a memory operand"); 6204 } 6205 6206 return false; 6207} 6208 6209/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 6210/// looking for aliasing nodes and adding them to the Aliases vector. 6211void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 6212 SmallVector<SDValue, 8> &Aliases) { 6213 SmallVector<SDValue, 8> Chains; // List of chains to visit. 6214 SmallPtrSet<SDNode *, 16> Visited; // Visited node set. 6215 6216 // Get alias information for node. 6217 SDValue Ptr; 6218 int64_t Size; 6219 const Value *SrcValue; 6220 int SrcValueOffset; 6221 unsigned SrcValueAlign; 6222 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset, 6223 SrcValueAlign); 6224 6225 // Starting off. 6226 Chains.push_back(OriginalChain); 6227 unsigned Depth = 0; 6228 6229 // Look at each chain and determine if it is an alias. If so, add it to the 6230 // aliases list. If not, then continue up the chain looking for the next 6231 // candidate. 6232 while (!Chains.empty()) { 6233 SDValue Chain = Chains.back(); 6234 Chains.pop_back(); 6235 6236 // For TokenFactor nodes, look at each operand and only continue up the 6237 // chain until we find two aliases. If we've seen two aliases, assume we'll 6238 // find more and revert to original chain since the xform is unlikely to be 6239 // profitable. 6240 // 6241 // FIXME: The depth check could be made to return the last non-aliasing 6242 // chain we found before we hit a tokenfactor rather than the original 6243 // chain. 6244 if (Depth > 6 || Aliases.size() == 2) { 6245 Aliases.clear(); 6246 Aliases.push_back(OriginalChain); 6247 break; 6248 } 6249 6250 // Don't bother if we've been before. 6251 if (!Visited.insert(Chain.getNode())) 6252 continue; 6253 6254 switch (Chain.getOpcode()) { 6255 case ISD::EntryToken: 6256 // Entry token is ideal chain operand, but handled in FindBetterChain. 6257 break; 6258 6259 case ISD::LOAD: 6260 case ISD::STORE: { 6261 // Get alias information for Chain. 6262 SDValue OpPtr; 6263 int64_t OpSize; 6264 const Value *OpSrcValue; 6265 int OpSrcValueOffset; 6266 unsigned OpSrcValueAlign; 6267 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, 6268 OpSrcValue, OpSrcValueOffset, 6269 OpSrcValueAlign); 6270 6271 // If chain is alias then stop here. 6272 if (!(IsLoad && IsOpLoad) && 6273 isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign, 6274 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset, 6275 OpSrcValueAlign)) { 6276 Aliases.push_back(Chain); 6277 } else { 6278 // Look further up the chain. 6279 Chains.push_back(Chain.getOperand(0)); 6280 ++Depth; 6281 } 6282 break; 6283 } 6284 6285 case ISD::TokenFactor: 6286 // We have to check each of the operands of the token factor for "small" 6287 // token factors, so we queue them up. Adding the operands to the queue 6288 // (stack) in reverse order maintains the original order and increases the 6289 // likelihood that getNode will find a matching token factor (CSE.) 6290 if (Chain.getNumOperands() > 16) { 6291 Aliases.push_back(Chain); 6292 break; 6293 } 6294 for (unsigned n = Chain.getNumOperands(); n;) 6295 Chains.push_back(Chain.getOperand(--n)); 6296 ++Depth; 6297 break; 6298 6299 default: 6300 // For all other instructions we will just have to take what we can get. 6301 Aliases.push_back(Chain); 6302 break; 6303 } 6304 } 6305} 6306 6307/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 6308/// for a better chain (aliasing node.) 6309SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 6310 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 6311 6312 // Accumulate all the aliases to this node. 6313 GatherAllAliases(N, OldChain, Aliases); 6314 6315 if (Aliases.size() == 0) { 6316 // If no operands then chain to entry token. 6317 return DAG.getEntryNode(); 6318 } else if (Aliases.size() == 1) { 6319 // If a single operand then chain to it. We don't need to revisit it. 6320 return Aliases[0]; 6321 } 6322 6323 // Construct a custom tailored token factor. 6324 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 6325 &Aliases[0], Aliases.size()); 6326} 6327 6328// SelectionDAG::Combine - This is the entry point for the file. 6329// 6330void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, 6331 CodeGenOpt::Level OptLevel) { 6332 /// run - This is the main entry point to this class. 6333 /// 6334 DAGCombiner(*this, AA, OptLevel).Run(Level); 6335} 6336