DAGCombiner.cpp revision dd75196ded16ee38a03ad2b04e5d1e0d0849bce9
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// This pass is not a substitute for the LLVM IR instcombine pass. This pass is 14// primarily intended to handle simplification opportunities that are implicit 15// in the LLVM IR and exposed by the various codegen lowering phases. 16// 17//===----------------------------------------------------------------------===// 18 19#define DEBUG_TYPE "dagcombine" 20#include "llvm/CodeGen/SelectionDAG.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/LLVMContext.h" 23#include "llvm/CodeGen/MachineFunction.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/PseudoSourceValue.h" 26#include "llvm/Analysis/AliasAnalysis.h" 27#include "llvm/Target/TargetData.h" 28#include "llvm/Target/TargetFrameInfo.h" 29#include "llvm/Target/TargetLowering.h" 30#include "llvm/Target/TargetMachine.h" 31#include "llvm/Target/TargetOptions.h" 32#include "llvm/ADT/SmallPtrSet.h" 33#include "llvm/ADT/Statistic.h" 34#include "llvm/Support/CommandLine.h" 35#include "llvm/Support/Debug.h" 36#include "llvm/Support/ErrorHandling.h" 37#include "llvm/Support/MathExtras.h" 38#include "llvm/Support/raw_ostream.h" 39#include <algorithm> 40using namespace llvm; 41 42STATISTIC(NodesCombined , "Number of dag nodes combined"); 43STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 44STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 45STATISTIC(OpsNarrowed , "Number of load/op/store narrowed"); 46 47namespace { 48 static cl::opt<bool> 49 CombinerAA("combiner-alias-analysis", cl::Hidden, 50 cl::desc("Turn on alias analysis during testing")); 51 52 static cl::opt<bool> 53 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 54 cl::desc("Include global information in alias analysis")); 55 56//------------------------------ DAGCombiner ---------------------------------// 57 58 class DAGCombiner { 59 SelectionDAG &DAG; 60 const TargetLowering &TLI; 61 CombineLevel Level; 62 CodeGenOpt::Level OptLevel; 63 bool LegalOperations; 64 bool LegalTypes; 65 66 // Worklist of all of the nodes that need to be simplified. 67 std::vector<SDNode*> WorkList; 68 69 // AA - Used for DAG load/store alias analysis. 70 AliasAnalysis &AA; 71 72 /// AddUsersToWorkList - When an instruction is simplified, add all users of 73 /// the instruction to the work lists because they might get more simplified 74 /// now. 75 /// 76 void AddUsersToWorkList(SDNode *N) { 77 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 78 UI != UE; ++UI) 79 AddToWorkList(*UI); 80 } 81 82 /// visit - call the node-specific routine that knows how to fold each 83 /// particular type of node. 84 SDValue visit(SDNode *N); 85 86 public: 87 /// AddToWorkList - Add to the work list making sure it's instance is at the 88 /// the back (next to be processed.) 89 void AddToWorkList(SDNode *N) { 90 removeFromWorkList(N); 91 WorkList.push_back(N); 92 } 93 94 /// removeFromWorkList - remove all instances of N from the worklist. 95 /// 96 void removeFromWorkList(SDNode *N) { 97 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 98 WorkList.end()); 99 } 100 101 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 102 bool AddTo = true); 103 104 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 105 return CombineTo(N, &Res, 1, AddTo); 106 } 107 108 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 109 bool AddTo = true) { 110 SDValue To[] = { Res0, Res1 }; 111 return CombineTo(N, To, 2, AddTo); 112 } 113 114 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO); 115 116 private: 117 118 /// SimplifyDemandedBits - Check the specified integer node value to see if 119 /// it can be simplified or if things it uses can be simplified by bit 120 /// propagation. If so, return true. 121 bool SimplifyDemandedBits(SDValue Op) { 122 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits(); 123 APInt Demanded = APInt::getAllOnesValue(BitWidth); 124 return SimplifyDemandedBits(Op, Demanded); 125 } 126 127 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 128 129 bool CombineToPreIndexedLoadStore(SDNode *N); 130 bool CombineToPostIndexedLoadStore(SDNode *N); 131 132 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad); 133 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace); 134 SDValue SExtPromoteOperand(SDValue Op, EVT PVT); 135 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT); 136 SDValue PromoteIntBinOp(SDValue Op); 137 SDValue PromoteIntShiftOp(SDValue Op); 138 SDValue PromoteExtend(SDValue Op); 139 bool PromoteLoad(SDValue Op); 140 141 /// combine - call the node-specific routine that knows how to fold each 142 /// particular type of node. If that doesn't do anything, try the 143 /// target-specific DAG combines. 144 SDValue combine(SDNode *N); 145 146 // Visitation implementation - Implement dag node combining for different 147 // node types. The semantics are as follows: 148 // Return Value: 149 // SDValue.getNode() == 0 - No change was made 150 // SDValue.getNode() == N - N was replaced, is dead and has been handled. 151 // otherwise - N should be replaced by the returned Operand. 152 // 153 SDValue visitTokenFactor(SDNode *N); 154 SDValue visitMERGE_VALUES(SDNode *N); 155 SDValue visitADD(SDNode *N); 156 SDValue visitSUB(SDNode *N); 157 SDValue visitADDC(SDNode *N); 158 SDValue visitADDE(SDNode *N); 159 SDValue visitMUL(SDNode *N); 160 SDValue visitSDIV(SDNode *N); 161 SDValue visitUDIV(SDNode *N); 162 SDValue visitSREM(SDNode *N); 163 SDValue visitUREM(SDNode *N); 164 SDValue visitMULHU(SDNode *N); 165 SDValue visitMULHS(SDNode *N); 166 SDValue visitSMUL_LOHI(SDNode *N); 167 SDValue visitUMUL_LOHI(SDNode *N); 168 SDValue visitSDIVREM(SDNode *N); 169 SDValue visitUDIVREM(SDNode *N); 170 SDValue visitAND(SDNode *N); 171 SDValue visitOR(SDNode *N); 172 SDValue visitXOR(SDNode *N); 173 SDValue SimplifyVBinOp(SDNode *N); 174 SDValue visitSHL(SDNode *N); 175 SDValue visitSRA(SDNode *N); 176 SDValue visitSRL(SDNode *N); 177 SDValue visitCTLZ(SDNode *N); 178 SDValue visitCTTZ(SDNode *N); 179 SDValue visitCTPOP(SDNode *N); 180 SDValue visitSELECT(SDNode *N); 181 SDValue visitSELECT_CC(SDNode *N); 182 SDValue visitSETCC(SDNode *N); 183 SDValue visitSIGN_EXTEND(SDNode *N); 184 SDValue visitZERO_EXTEND(SDNode *N); 185 SDValue visitANY_EXTEND(SDNode *N); 186 SDValue visitSIGN_EXTEND_INREG(SDNode *N); 187 SDValue visitTRUNCATE(SDNode *N); 188 SDValue visitBIT_CONVERT(SDNode *N); 189 SDValue visitBUILD_PAIR(SDNode *N); 190 SDValue visitFADD(SDNode *N); 191 SDValue visitFSUB(SDNode *N); 192 SDValue visitFMUL(SDNode *N); 193 SDValue visitFDIV(SDNode *N); 194 SDValue visitFREM(SDNode *N); 195 SDValue visitFCOPYSIGN(SDNode *N); 196 SDValue visitSINT_TO_FP(SDNode *N); 197 SDValue visitUINT_TO_FP(SDNode *N); 198 SDValue visitFP_TO_SINT(SDNode *N); 199 SDValue visitFP_TO_UINT(SDNode *N); 200 SDValue visitFP_ROUND(SDNode *N); 201 SDValue visitFP_ROUND_INREG(SDNode *N); 202 SDValue visitFP_EXTEND(SDNode *N); 203 SDValue visitFNEG(SDNode *N); 204 SDValue visitFABS(SDNode *N); 205 SDValue visitBRCOND(SDNode *N); 206 SDValue visitBR_CC(SDNode *N); 207 SDValue visitLOAD(SDNode *N); 208 SDValue visitSTORE(SDNode *N); 209 SDValue visitINSERT_VECTOR_ELT(SDNode *N); 210 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 211 SDValue visitBUILD_VECTOR(SDNode *N); 212 SDValue visitCONCAT_VECTORS(SDNode *N); 213 SDValue visitVECTOR_SHUFFLE(SDNode *N); 214 SDValue visitMEMBARRIER(SDNode *N); 215 216 SDValue XformToShuffleWithZero(SDNode *N); 217 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS); 218 219 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 220 221 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 222 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 223 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2); 224 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2, 225 SDValue N3, ISD::CondCode CC, 226 bool NotExtCompare = false); 227 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 228 DebugLoc DL, bool foldBooleans = true); 229 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 230 unsigned HiOp); 231 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT); 232 SDValue ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, EVT); 233 SDValue BuildSDIV(SDNode *N); 234 SDValue BuildUDIV(SDNode *N); 235 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL); 236 SDValue ReduceLoadWidth(SDNode *N); 237 SDValue ReduceLoadOpStoreWidth(SDNode *N); 238 239 SDValue GetDemandedBits(SDValue V, const APInt &Mask); 240 241 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 242 /// looking for aliasing nodes and adding them to the Aliases vector. 243 void GatherAllAliases(SDNode *N, SDValue OriginalChain, 244 SmallVector<SDValue, 8> &Aliases); 245 246 /// isAlias - Return true if there is any possibility that the two addresses 247 /// overlap. 248 bool isAlias(SDValue Ptr1, int64_t Size1, 249 const Value *SrcValue1, int SrcValueOffset1, 250 unsigned SrcValueAlign1, 251 SDValue Ptr2, int64_t Size2, 252 const Value *SrcValue2, int SrcValueOffset2, 253 unsigned SrcValueAlign2) const; 254 255 /// FindAliasInfo - Extracts the relevant alias information from the memory 256 /// node. Returns true if the operand was a load. 257 bool FindAliasInfo(SDNode *N, 258 SDValue &Ptr, int64_t &Size, 259 const Value *&SrcValue, int &SrcValueOffset, 260 unsigned &SrcValueAlignment) const; 261 262 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 263 /// looking for a better chain (aliasing node.) 264 SDValue FindBetterChain(SDNode *N, SDValue Chain); 265 266 public: 267 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL) 268 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(Unrestricted), 269 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {} 270 271 /// Run - runs the dag combiner on all nodes in the work list 272 void Run(CombineLevel AtLevel); 273 274 SelectionDAG &getDAG() const { return DAG; } 275 276 /// getShiftAmountTy - Returns a type large enough to hold any valid 277 /// shift amount - before type legalization these can be huge. 278 EVT getShiftAmountTy() { 279 return LegalTypes ? TLI.getShiftAmountTy() : TLI.getPointerTy(); 280 } 281 282 /// isTypeLegal - This method returns true if we are running before type 283 /// legalization or if the specified VT is legal. 284 bool isTypeLegal(const EVT &VT) { 285 if (!LegalTypes) return true; 286 return TLI.isTypeLegal(VT); 287 } 288 }; 289} 290 291 292namespace { 293/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 294/// nodes from the worklist. 295class WorkListRemover : public SelectionDAG::DAGUpdateListener { 296 DAGCombiner &DC; 297public: 298 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {} 299 300 virtual void NodeDeleted(SDNode *N, SDNode *E) { 301 DC.removeFromWorkList(N); 302 } 303 304 virtual void NodeUpdated(SDNode *N) { 305 // Ignore updates. 306 } 307}; 308} 309 310//===----------------------------------------------------------------------===// 311// TargetLowering::DAGCombinerInfo implementation 312//===----------------------------------------------------------------------===// 313 314void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 315 ((DAGCombiner*)DC)->AddToWorkList(N); 316} 317 318SDValue TargetLowering::DAGCombinerInfo:: 319CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) { 320 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo); 321} 322 323SDValue TargetLowering::DAGCombinerInfo:: 324CombineTo(SDNode *N, SDValue Res, bool AddTo) { 325 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo); 326} 327 328 329SDValue TargetLowering::DAGCombinerInfo:: 330CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) { 331 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo); 332} 333 334void TargetLowering::DAGCombinerInfo:: 335CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 336 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO); 337} 338 339//===----------------------------------------------------------------------===// 340// Helper Functions 341//===----------------------------------------------------------------------===// 342 343/// isNegatibleForFree - Return 1 if we can compute the negated form of the 344/// specified expression for the same cost as the expression itself, or 2 if we 345/// can compute the negated form more cheaply than the expression itself. 346static char isNegatibleForFree(SDValue Op, bool LegalOperations, 347 unsigned Depth = 0) { 348 // No compile time optimizations on this type. 349 if (Op.getValueType() == MVT::ppcf128) 350 return 0; 351 352 // fneg is removable even if it has multiple uses. 353 if (Op.getOpcode() == ISD::FNEG) return 2; 354 355 // Don't allow anything with multiple uses. 356 if (!Op.hasOneUse()) return 0; 357 358 // Don't recurse exponentially. 359 if (Depth > 6) return 0; 360 361 switch (Op.getOpcode()) { 362 default: return false; 363 case ISD::ConstantFP: 364 // Don't invert constant FP values after legalize. The negated constant 365 // isn't necessarily legal. 366 return LegalOperations ? 0 : 1; 367 case ISD::FADD: 368 // FIXME: determine better conditions for this xform. 369 if (!UnsafeFPMath) return 0; 370 371 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B) 372 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 373 return V; 374 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 375 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 376 case ISD::FSUB: 377 // We can't turn -(A-B) into B-A when we honor signed zeros. 378 if (!UnsafeFPMath) return 0; 379 380 // fold (fneg (fsub A, B)) -> (fsub B, A) 381 return 1; 382 383 case ISD::FMUL: 384 case ISD::FDIV: 385 if (HonorSignDependentRoundingFPMath()) return 0; 386 387 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y)) 388 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 389 return V; 390 391 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 392 393 case ISD::FP_EXTEND: 394 case ISD::FP_ROUND: 395 case ISD::FSIN: 396 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1); 397 } 398} 399 400/// GetNegatedExpression - If isNegatibleForFree returns true, this function 401/// returns the newly negated expression. 402static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 403 bool LegalOperations, unsigned Depth = 0) { 404 // fneg is removable even if it has multiple uses. 405 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 406 407 // Don't allow anything with multiple uses. 408 assert(Op.hasOneUse() && "Unknown reuse!"); 409 410 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 411 switch (Op.getOpcode()) { 412 default: llvm_unreachable("Unknown code"); 413 case ISD::ConstantFP: { 414 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 415 V.changeSign(); 416 return DAG.getConstantFP(V, Op.getValueType()); 417 } 418 case ISD::FADD: 419 // FIXME: determine better conditions for this xform. 420 assert(UnsafeFPMath); 421 422 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 423 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 424 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 425 GetNegatedExpression(Op.getOperand(0), DAG, 426 LegalOperations, Depth+1), 427 Op.getOperand(1)); 428 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 429 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 430 GetNegatedExpression(Op.getOperand(1), DAG, 431 LegalOperations, Depth+1), 432 Op.getOperand(0)); 433 case ISD::FSUB: 434 // We can't turn -(A-B) into B-A when we honor signed zeros. 435 assert(UnsafeFPMath); 436 437 // fold (fneg (fsub 0, B)) -> B 438 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 439 if (N0CFP->getValueAPF().isZero()) 440 return Op.getOperand(1); 441 442 // fold (fneg (fsub A, B)) -> (fsub B, A) 443 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 444 Op.getOperand(1), Op.getOperand(0)); 445 446 case ISD::FMUL: 447 case ISD::FDIV: 448 assert(!HonorSignDependentRoundingFPMath()); 449 450 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) 451 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 452 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 453 GetNegatedExpression(Op.getOperand(0), DAG, 454 LegalOperations, Depth+1), 455 Op.getOperand(1)); 456 457 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y)) 458 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 459 Op.getOperand(0), 460 GetNegatedExpression(Op.getOperand(1), DAG, 461 LegalOperations, Depth+1)); 462 463 case ISD::FP_EXTEND: 464 case ISD::FSIN: 465 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 466 GetNegatedExpression(Op.getOperand(0), DAG, 467 LegalOperations, Depth+1)); 468 case ISD::FP_ROUND: 469 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(), 470 GetNegatedExpression(Op.getOperand(0), DAG, 471 LegalOperations, Depth+1), 472 Op.getOperand(1)); 473 } 474} 475 476 477// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 478// that selects between the values 1 and 0, making it equivalent to a setcc. 479// Also, set the incoming LHS, RHS, and CC references to the appropriate 480// nodes based on the type of node we are checking. This simplifies life a 481// bit for the callers. 482static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 483 SDValue &CC) { 484 if (N.getOpcode() == ISD::SETCC) { 485 LHS = N.getOperand(0); 486 RHS = N.getOperand(1); 487 CC = N.getOperand(2); 488 return true; 489 } 490 if (N.getOpcode() == ISD::SELECT_CC && 491 N.getOperand(2).getOpcode() == ISD::Constant && 492 N.getOperand(3).getOpcode() == ISD::Constant && 493 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 494 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 495 LHS = N.getOperand(0); 496 RHS = N.getOperand(1); 497 CC = N.getOperand(4); 498 return true; 499 } 500 return false; 501} 502 503// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 504// one use. If this is true, it allows the users to invert the operation for 505// free when it is profitable to do so. 506static bool isOneUseSetCC(SDValue N) { 507 SDValue N0, N1, N2; 508 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 509 return true; 510 return false; 511} 512 513SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL, 514 SDValue N0, SDValue N1) { 515 EVT VT = N0.getValueType(); 516 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 517 if (isa<ConstantSDNode>(N1)) { 518 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 519 SDValue OpNode = 520 DAG.FoldConstantArithmetic(Opc, VT, 521 cast<ConstantSDNode>(N0.getOperand(1)), 522 cast<ConstantSDNode>(N1)); 523 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode); 524 } else if (N0.hasOneUse()) { 525 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 526 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 527 N0.getOperand(0), N1); 528 AddToWorkList(OpNode.getNode()); 529 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1)); 530 } 531 } 532 533 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 534 if (isa<ConstantSDNode>(N0)) { 535 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 536 SDValue OpNode = 537 DAG.FoldConstantArithmetic(Opc, VT, 538 cast<ConstantSDNode>(N1.getOperand(1)), 539 cast<ConstantSDNode>(N0)); 540 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode); 541 } else if (N1.hasOneUse()) { 542 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 543 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 544 N1.getOperand(0), N0); 545 AddToWorkList(OpNode.getNode()); 546 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1)); 547 } 548 } 549 550 return SDValue(); 551} 552 553SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 554 bool AddTo) { 555 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 556 ++NodesCombined; 557 DEBUG(dbgs() << "\nReplacing.1 "; 558 N->dump(&DAG); 559 dbgs() << "\nWith: "; 560 To[0].getNode()->dump(&DAG); 561 dbgs() << " and " << NumTo-1 << " other values\n"; 562 for (unsigned i = 0, e = NumTo; i != e; ++i) 563 assert((!To[i].getNode() || 564 N->getValueType(i) == To[i].getValueType()) && 565 "Cannot combine value to value of different type!")); 566 WorkListRemover DeadNodes(*this); 567 DAG.ReplaceAllUsesWith(N, To, &DeadNodes); 568 569 if (AddTo) { 570 // Push the new nodes and any users onto the worklist 571 for (unsigned i = 0, e = NumTo; i != e; ++i) { 572 if (To[i].getNode()) { 573 AddToWorkList(To[i].getNode()); 574 AddUsersToWorkList(To[i].getNode()); 575 } 576 } 577 } 578 579 // Finally, if the node is now dead, remove it from the graph. The node 580 // may not be dead if the replacement process recursively simplified to 581 // something else needing this node. 582 if (N->use_empty()) { 583 // Nodes can be reintroduced into the worklist. Make sure we do not 584 // process a node that has been replaced. 585 removeFromWorkList(N); 586 587 // Finally, since the node is now dead, remove it from the graph. 588 DAG.DeleteNode(N); 589 } 590 return SDValue(N, 0); 591} 592 593void DAGCombiner:: 594CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 595 // Replace all uses. If any nodes become isomorphic to other nodes and 596 // are deleted, make sure to remove them from our worklist. 597 WorkListRemover DeadNodes(*this); 598 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 599 600 // Push the new node and any (possibly new) users onto the worklist. 601 AddToWorkList(TLO.New.getNode()); 602 AddUsersToWorkList(TLO.New.getNode()); 603 604 // Finally, if the node is now dead, remove it from the graph. The node 605 // may not be dead if the replacement process recursively simplified to 606 // something else needing this node. 607 if (TLO.Old.getNode()->use_empty()) { 608 removeFromWorkList(TLO.Old.getNode()); 609 610 // If the operands of this node are only used by the node, they will now 611 // be dead. Make sure to visit them first to delete dead nodes early. 612 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i) 613 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse()) 614 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode()); 615 616 DAG.DeleteNode(TLO.Old.getNode()); 617 } 618} 619 620/// SimplifyDemandedBits - Check the specified integer node value to see if 621/// it can be simplified or if things it uses can be simplified by bit 622/// propagation. If so, return true. 623bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 624 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations); 625 APInt KnownZero, KnownOne; 626 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 627 return false; 628 629 // Revisit the node. 630 AddToWorkList(Op.getNode()); 631 632 // Replace the old value with the new one. 633 ++NodesCombined; 634 DEBUG(dbgs() << "\nReplacing.2 "; 635 TLO.Old.getNode()->dump(&DAG); 636 dbgs() << "\nWith: "; 637 TLO.New.getNode()->dump(&DAG); 638 dbgs() << '\n'); 639 640 CommitTargetLoweringOpt(TLO); 641 return true; 642} 643 644void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) { 645 DebugLoc dl = Load->getDebugLoc(); 646 EVT VT = Load->getValueType(0); 647 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0)); 648 649 DEBUG(dbgs() << "\nReplacing.9 "; 650 Load->dump(&DAG); 651 dbgs() << "\nWith: "; 652 Trunc.getNode()->dump(&DAG); 653 dbgs() << '\n'); 654 WorkListRemover DeadNodes(*this); 655 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc, &DeadNodes); 656 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1), 657 &DeadNodes); 658 removeFromWorkList(Load); 659 DAG.DeleteNode(Load); 660 AddToWorkList(Trunc.getNode()); 661} 662 663SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) { 664 Replace = false; 665 DebugLoc dl = Op.getDebugLoc(); 666 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) { 667 EVT MemVT = LD->getMemoryVT(); 668 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 669 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD : ISD::EXTLOAD) 670 : LD->getExtensionType(); 671 Replace = true; 672 return DAG.getExtLoad(ExtType, PVT, dl, 673 LD->getChain(), LD->getBasePtr(), 674 LD->getPointerInfo(), 675 MemVT, LD->isVolatile(), 676 LD->isNonTemporal(), LD->getAlignment()); 677 } 678 679 unsigned Opc = Op.getOpcode(); 680 switch (Opc) { 681 default: break; 682 case ISD::AssertSext: 683 return DAG.getNode(ISD::AssertSext, dl, PVT, 684 SExtPromoteOperand(Op.getOperand(0), PVT), 685 Op.getOperand(1)); 686 case ISD::AssertZext: 687 return DAG.getNode(ISD::AssertZext, dl, PVT, 688 ZExtPromoteOperand(Op.getOperand(0), PVT), 689 Op.getOperand(1)); 690 case ISD::Constant: { 691 unsigned ExtOpc = 692 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 693 return DAG.getNode(ExtOpc, dl, PVT, Op); 694 } 695 } 696 697 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT)) 698 return SDValue(); 699 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op); 700} 701 702SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) { 703 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT)) 704 return SDValue(); 705 EVT OldVT = Op.getValueType(); 706 DebugLoc dl = Op.getDebugLoc(); 707 bool Replace = false; 708 SDValue NewOp = PromoteOperand(Op, PVT, Replace); 709 if (NewOp.getNode() == 0) 710 return SDValue(); 711 AddToWorkList(NewOp.getNode()); 712 713 if (Replace) 714 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 715 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp, 716 DAG.getValueType(OldVT)); 717} 718 719SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) { 720 EVT OldVT = Op.getValueType(); 721 DebugLoc dl = Op.getDebugLoc(); 722 bool Replace = false; 723 SDValue NewOp = PromoteOperand(Op, PVT, Replace); 724 if (NewOp.getNode() == 0) 725 return SDValue(); 726 AddToWorkList(NewOp.getNode()); 727 728 if (Replace) 729 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 730 return DAG.getZeroExtendInReg(NewOp, dl, OldVT); 731} 732 733/// PromoteIntBinOp - Promote the specified integer binary operation if the 734/// target indicates it is beneficial. e.g. On x86, it's usually better to 735/// promote i16 operations to i32 since i16 instructions are longer. 736SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) { 737 if (!LegalOperations) 738 return SDValue(); 739 740 EVT VT = Op.getValueType(); 741 if (VT.isVector() || !VT.isInteger()) 742 return SDValue(); 743 744 // If operation type is 'undesirable', e.g. i16 on x86, consider 745 // promoting it. 746 unsigned Opc = Op.getOpcode(); 747 if (TLI.isTypeDesirableForOp(Opc, VT)) 748 return SDValue(); 749 750 EVT PVT = VT; 751 // Consult target whether it is a good idea to promote this operation and 752 // what's the right type to promote it to. 753 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 754 assert(PVT != VT && "Don't know what type to promote to!"); 755 756 bool Replace0 = false; 757 SDValue N0 = Op.getOperand(0); 758 SDValue NN0 = PromoteOperand(N0, PVT, Replace0); 759 if (NN0.getNode() == 0) 760 return SDValue(); 761 762 bool Replace1 = false; 763 SDValue N1 = Op.getOperand(1); 764 SDValue NN1; 765 if (N0 == N1) 766 NN1 = NN0; 767 else { 768 NN1 = PromoteOperand(N1, PVT, Replace1); 769 if (NN1.getNode() == 0) 770 return SDValue(); 771 } 772 773 AddToWorkList(NN0.getNode()); 774 if (NN1.getNode()) 775 AddToWorkList(NN1.getNode()); 776 777 if (Replace0) 778 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode()); 779 if (Replace1) 780 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode()); 781 782 DEBUG(dbgs() << "\nPromoting "; 783 Op.getNode()->dump(&DAG)); 784 DebugLoc dl = Op.getDebugLoc(); 785 return DAG.getNode(ISD::TRUNCATE, dl, VT, 786 DAG.getNode(Opc, dl, PVT, NN0, NN1)); 787 } 788 return SDValue(); 789} 790 791/// PromoteIntShiftOp - Promote the specified integer shift operation if the 792/// target indicates it is beneficial. e.g. On x86, it's usually better to 793/// promote i16 operations to i32 since i16 instructions are longer. 794SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) { 795 if (!LegalOperations) 796 return SDValue(); 797 798 EVT VT = Op.getValueType(); 799 if (VT.isVector() || !VT.isInteger()) 800 return SDValue(); 801 802 // If operation type is 'undesirable', e.g. i16 on x86, consider 803 // promoting it. 804 unsigned Opc = Op.getOpcode(); 805 if (TLI.isTypeDesirableForOp(Opc, VT)) 806 return SDValue(); 807 808 EVT PVT = VT; 809 // Consult target whether it is a good idea to promote this operation and 810 // what's the right type to promote it to. 811 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 812 assert(PVT != VT && "Don't know what type to promote to!"); 813 814 bool Replace = false; 815 SDValue N0 = Op.getOperand(0); 816 if (Opc == ISD::SRA) 817 N0 = SExtPromoteOperand(Op.getOperand(0), PVT); 818 else if (Opc == ISD::SRL) 819 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT); 820 else 821 N0 = PromoteOperand(N0, PVT, Replace); 822 if (N0.getNode() == 0) 823 return SDValue(); 824 825 AddToWorkList(N0.getNode()); 826 if (Replace) 827 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode()); 828 829 DEBUG(dbgs() << "\nPromoting "; 830 Op.getNode()->dump(&DAG)); 831 DebugLoc dl = Op.getDebugLoc(); 832 return DAG.getNode(ISD::TRUNCATE, dl, VT, 833 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1))); 834 } 835 return SDValue(); 836} 837 838SDValue DAGCombiner::PromoteExtend(SDValue Op) { 839 if (!LegalOperations) 840 return SDValue(); 841 842 EVT VT = Op.getValueType(); 843 if (VT.isVector() || !VT.isInteger()) 844 return SDValue(); 845 846 // If operation type is 'undesirable', e.g. i16 on x86, consider 847 // promoting it. 848 unsigned Opc = Op.getOpcode(); 849 if (TLI.isTypeDesirableForOp(Opc, VT)) 850 return SDValue(); 851 852 EVT PVT = VT; 853 // Consult target whether it is a good idea to promote this operation and 854 // what's the right type to promote it to. 855 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 856 assert(PVT != VT && "Don't know what type to promote to!"); 857 // fold (aext (aext x)) -> (aext x) 858 // fold (aext (zext x)) -> (zext x) 859 // fold (aext (sext x)) -> (sext x) 860 DEBUG(dbgs() << "\nPromoting "; 861 Op.getNode()->dump(&DAG)); 862 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), VT, Op.getOperand(0)); 863 } 864 return SDValue(); 865} 866 867bool DAGCombiner::PromoteLoad(SDValue Op) { 868 if (!LegalOperations) 869 return false; 870 871 EVT VT = Op.getValueType(); 872 if (VT.isVector() || !VT.isInteger()) 873 return false; 874 875 // If operation type is 'undesirable', e.g. i16 on x86, consider 876 // promoting it. 877 unsigned Opc = Op.getOpcode(); 878 if (TLI.isTypeDesirableForOp(Opc, VT)) 879 return false; 880 881 EVT PVT = VT; 882 // Consult target whether it is a good idea to promote this operation and 883 // what's the right type to promote it to. 884 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 885 assert(PVT != VT && "Don't know what type to promote to!"); 886 887 DebugLoc dl = Op.getDebugLoc(); 888 SDNode *N = Op.getNode(); 889 LoadSDNode *LD = cast<LoadSDNode>(N); 890 EVT MemVT = LD->getMemoryVT(); 891 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 892 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD : ISD::EXTLOAD) 893 : LD->getExtensionType(); 894 SDValue NewLD = DAG.getExtLoad(ExtType, PVT, dl, 895 LD->getChain(), LD->getBasePtr(), 896 LD->getPointerInfo(), 897 MemVT, LD->isVolatile(), 898 LD->isNonTemporal(), LD->getAlignment()); 899 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD); 900 901 DEBUG(dbgs() << "\nPromoting "; 902 N->dump(&DAG); 903 dbgs() << "\nTo: "; 904 Result.getNode()->dump(&DAG); 905 dbgs() << '\n'); 906 WorkListRemover DeadNodes(*this); 907 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result, &DeadNodes); 908 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1), &DeadNodes); 909 removeFromWorkList(N); 910 DAG.DeleteNode(N); 911 AddToWorkList(Result.getNode()); 912 return true; 913 } 914 return false; 915} 916 917 918//===----------------------------------------------------------------------===// 919// Main DAG Combiner implementation 920//===----------------------------------------------------------------------===// 921 922void DAGCombiner::Run(CombineLevel AtLevel) { 923 // set the instance variables, so that the various visit routines may use it. 924 Level = AtLevel; 925 LegalOperations = Level >= NoIllegalOperations; 926 LegalTypes = Level >= NoIllegalTypes; 927 928 // Add all the dag nodes to the worklist. 929 WorkList.reserve(DAG.allnodes_size()); 930 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 931 E = DAG.allnodes_end(); I != E; ++I) 932 WorkList.push_back(I); 933 934 // Create a dummy node (which is not added to allnodes), that adds a reference 935 // to the root node, preventing it from being deleted, and tracking any 936 // changes of the root. 937 HandleSDNode Dummy(DAG.getRoot()); 938 939 // The root of the dag may dangle to deleted nodes until the dag combiner is 940 // done. Set it to null to avoid confusion. 941 DAG.setRoot(SDValue()); 942 943 // while the worklist isn't empty, inspect the node on the end of it and 944 // try and combine it. 945 while (!WorkList.empty()) { 946 SDNode *N = WorkList.back(); 947 WorkList.pop_back(); 948 949 // If N has no uses, it is dead. Make sure to revisit all N's operands once 950 // N is deleted from the DAG, since they too may now be dead or may have a 951 // reduced number of uses, allowing other xforms. 952 if (N->use_empty() && N != &Dummy) { 953 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 954 AddToWorkList(N->getOperand(i).getNode()); 955 956 DAG.DeleteNode(N); 957 continue; 958 } 959 960 SDValue RV = combine(N); 961 962 if (RV.getNode() == 0) 963 continue; 964 965 ++NodesCombined; 966 967 // If we get back the same node we passed in, rather than a new node or 968 // zero, we know that the node must have defined multiple values and 969 // CombineTo was used. Since CombineTo takes care of the worklist 970 // mechanics for us, we have no work to do in this case. 971 if (RV.getNode() == N) 972 continue; 973 974 assert(N->getOpcode() != ISD::DELETED_NODE && 975 RV.getNode()->getOpcode() != ISD::DELETED_NODE && 976 "Node was deleted but visit returned new node!"); 977 978 DEBUG(dbgs() << "\nReplacing.3 "; 979 N->dump(&DAG); 980 dbgs() << "\nWith: "; 981 RV.getNode()->dump(&DAG); 982 dbgs() << '\n'); 983 WorkListRemover DeadNodes(*this); 984 if (N->getNumValues() == RV.getNode()->getNumValues()) 985 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes); 986 else { 987 assert(N->getValueType(0) == RV.getValueType() && 988 N->getNumValues() == 1 && "Type mismatch"); 989 SDValue OpV = RV; 990 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes); 991 } 992 993 // Push the new node and any users onto the worklist 994 AddToWorkList(RV.getNode()); 995 AddUsersToWorkList(RV.getNode()); 996 997 // Add any uses of the old node to the worklist in case this node is the 998 // last one that uses them. They may become dead after this node is 999 // deleted. 1000 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1001 AddToWorkList(N->getOperand(i).getNode()); 1002 1003 // Finally, if the node is now dead, remove it from the graph. The node 1004 // may not be dead if the replacement process recursively simplified to 1005 // something else needing this node. 1006 if (N->use_empty()) { 1007 // Nodes can be reintroduced into the worklist. Make sure we do not 1008 // process a node that has been replaced. 1009 removeFromWorkList(N); 1010 1011 // Finally, since the node is now dead, remove it from the graph. 1012 DAG.DeleteNode(N); 1013 } 1014 } 1015 1016 // If the root changed (e.g. it was a dead load, update the root). 1017 DAG.setRoot(Dummy.getValue()); 1018} 1019 1020SDValue DAGCombiner::visit(SDNode *N) { 1021 switch (N->getOpcode()) { 1022 default: break; 1023 case ISD::TokenFactor: return visitTokenFactor(N); 1024 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 1025 case ISD::ADD: return visitADD(N); 1026 case ISD::SUB: return visitSUB(N); 1027 case ISD::ADDC: return visitADDC(N); 1028 case ISD::ADDE: return visitADDE(N); 1029 case ISD::MUL: return visitMUL(N); 1030 case ISD::SDIV: return visitSDIV(N); 1031 case ISD::UDIV: return visitUDIV(N); 1032 case ISD::SREM: return visitSREM(N); 1033 case ISD::UREM: return visitUREM(N); 1034 case ISD::MULHU: return visitMULHU(N); 1035 case ISD::MULHS: return visitMULHS(N); 1036 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 1037 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 1038 case ISD::SDIVREM: return visitSDIVREM(N); 1039 case ISD::UDIVREM: return visitUDIVREM(N); 1040 case ISD::AND: return visitAND(N); 1041 case ISD::OR: return visitOR(N); 1042 case ISD::XOR: return visitXOR(N); 1043 case ISD::SHL: return visitSHL(N); 1044 case ISD::SRA: return visitSRA(N); 1045 case ISD::SRL: return visitSRL(N); 1046 case ISD::CTLZ: return visitCTLZ(N); 1047 case ISD::CTTZ: return visitCTTZ(N); 1048 case ISD::CTPOP: return visitCTPOP(N); 1049 case ISD::SELECT: return visitSELECT(N); 1050 case ISD::SELECT_CC: return visitSELECT_CC(N); 1051 case ISD::SETCC: return visitSETCC(N); 1052 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 1053 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 1054 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 1055 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 1056 case ISD::TRUNCATE: return visitTRUNCATE(N); 1057 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 1058 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 1059 case ISD::FADD: return visitFADD(N); 1060 case ISD::FSUB: return visitFSUB(N); 1061 case ISD::FMUL: return visitFMUL(N); 1062 case ISD::FDIV: return visitFDIV(N); 1063 case ISD::FREM: return visitFREM(N); 1064 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 1065 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 1066 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 1067 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 1068 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 1069 case ISD::FP_ROUND: return visitFP_ROUND(N); 1070 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 1071 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 1072 case ISD::FNEG: return visitFNEG(N); 1073 case ISD::FABS: return visitFABS(N); 1074 case ISD::BRCOND: return visitBRCOND(N); 1075 case ISD::BR_CC: return visitBR_CC(N); 1076 case ISD::LOAD: return visitLOAD(N); 1077 case ISD::STORE: return visitSTORE(N); 1078 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 1079 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 1080 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 1081 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 1082 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 1083 case ISD::MEMBARRIER: return visitMEMBARRIER(N); 1084 } 1085 return SDValue(); 1086} 1087 1088SDValue DAGCombiner::combine(SDNode *N) { 1089 SDValue RV = visit(N); 1090 1091 // If nothing happened, try a target-specific DAG combine. 1092 if (RV.getNode() == 0) { 1093 assert(N->getOpcode() != ISD::DELETED_NODE && 1094 "Node was deleted but visit returned NULL!"); 1095 1096 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 1097 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 1098 1099 // Expose the DAG combiner to the target combiner impls. 1100 TargetLowering::DAGCombinerInfo 1101 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 1102 1103 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 1104 } 1105 } 1106 1107 // If nothing happened still, try promoting the operation. 1108 if (RV.getNode() == 0) { 1109 switch (N->getOpcode()) { 1110 default: break; 1111 case ISD::ADD: 1112 case ISD::SUB: 1113 case ISD::MUL: 1114 case ISD::AND: 1115 case ISD::OR: 1116 case ISD::XOR: 1117 RV = PromoteIntBinOp(SDValue(N, 0)); 1118 break; 1119 case ISD::SHL: 1120 case ISD::SRA: 1121 case ISD::SRL: 1122 RV = PromoteIntShiftOp(SDValue(N, 0)); 1123 break; 1124 case ISD::SIGN_EXTEND: 1125 case ISD::ZERO_EXTEND: 1126 case ISD::ANY_EXTEND: 1127 RV = PromoteExtend(SDValue(N, 0)); 1128 break; 1129 case ISD::LOAD: 1130 if (PromoteLoad(SDValue(N, 0))) 1131 RV = SDValue(N, 0); 1132 break; 1133 } 1134 } 1135 1136 // If N is a commutative binary node, try commuting it to enable more 1137 // sdisel CSE. 1138 if (RV.getNode() == 0 && 1139 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 1140 N->getNumValues() == 1) { 1141 SDValue N0 = N->getOperand(0); 1142 SDValue N1 = N->getOperand(1); 1143 1144 // Constant operands are canonicalized to RHS. 1145 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 1146 SDValue Ops[] = { N1, N0 }; 1147 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 1148 Ops, 2); 1149 if (CSENode) 1150 return SDValue(CSENode, 0); 1151 } 1152 } 1153 1154 return RV; 1155} 1156 1157/// getInputChainForNode - Given a node, return its input chain if it has one, 1158/// otherwise return a null sd operand. 1159static SDValue getInputChainForNode(SDNode *N) { 1160 if (unsigned NumOps = N->getNumOperands()) { 1161 if (N->getOperand(0).getValueType() == MVT::Other) 1162 return N->getOperand(0); 1163 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 1164 return N->getOperand(NumOps-1); 1165 for (unsigned i = 1; i < NumOps-1; ++i) 1166 if (N->getOperand(i).getValueType() == MVT::Other) 1167 return N->getOperand(i); 1168 } 1169 return SDValue(); 1170} 1171 1172SDValue DAGCombiner::visitTokenFactor(SDNode *N) { 1173 // If N has two operands, where one has an input chain equal to the other, 1174 // the 'other' chain is redundant. 1175 if (N->getNumOperands() == 2) { 1176 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) 1177 return N->getOperand(0); 1178 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) 1179 return N->getOperand(1); 1180 } 1181 1182 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 1183 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 1184 SmallPtrSet<SDNode*, 16> SeenOps; 1185 bool Changed = false; // If we should replace this token factor. 1186 1187 // Start out with this token factor. 1188 TFs.push_back(N); 1189 1190 // Iterate through token factors. The TFs grows when new token factors are 1191 // encountered. 1192 for (unsigned i = 0; i < TFs.size(); ++i) { 1193 SDNode *TF = TFs[i]; 1194 1195 // Check each of the operands. 1196 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 1197 SDValue Op = TF->getOperand(i); 1198 1199 switch (Op.getOpcode()) { 1200 case ISD::EntryToken: 1201 // Entry tokens don't need to be added to the list. They are 1202 // rededundant. 1203 Changed = true; 1204 break; 1205 1206 case ISD::TokenFactor: 1207 if (Op.hasOneUse() && 1208 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { 1209 // Queue up for processing. 1210 TFs.push_back(Op.getNode()); 1211 // Clean up in case the token factor is removed. 1212 AddToWorkList(Op.getNode()); 1213 Changed = true; 1214 break; 1215 } 1216 // Fall thru 1217 1218 default: 1219 // Only add if it isn't already in the list. 1220 if (SeenOps.insert(Op.getNode())) 1221 Ops.push_back(Op); 1222 else 1223 Changed = true; 1224 break; 1225 } 1226 } 1227 } 1228 1229 SDValue Result; 1230 1231 // If we've change things around then replace token factor. 1232 if (Changed) { 1233 if (Ops.empty()) { 1234 // The entry token is the only possible outcome. 1235 Result = DAG.getEntryNode(); 1236 } else { 1237 // New and improved token factor. 1238 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 1239 MVT::Other, &Ops[0], Ops.size()); 1240 } 1241 1242 // Don't add users to work list. 1243 return CombineTo(N, Result, false); 1244 } 1245 1246 return Result; 1247} 1248 1249/// MERGE_VALUES can always be eliminated. 1250SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 1251 WorkListRemover DeadNodes(*this); 1252 // Replacing results may cause a different MERGE_VALUES to suddenly 1253 // be CSE'd with N, and carry its uses with it. Iterate until no 1254 // uses remain, to ensure that the node can be safely deleted. 1255 do { 1256 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1257 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i), 1258 &DeadNodes); 1259 } while (!N->use_empty()); 1260 removeFromWorkList(N); 1261 DAG.DeleteNode(N); 1262 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1263} 1264 1265static 1266SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1, 1267 SelectionDAG &DAG) { 1268 EVT VT = N0.getValueType(); 1269 SDValue N00 = N0.getOperand(0); 1270 SDValue N01 = N0.getOperand(1); 1271 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 1272 1273 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && 1274 isa<ConstantSDNode>(N00.getOperand(1))) { 1275 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1276 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, 1277 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT, 1278 N00.getOperand(0), N01), 1279 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT, 1280 N00.getOperand(1), N01)); 1281 return DAG.getNode(ISD::ADD, DL, VT, N0, N1); 1282 } 1283 1284 return SDValue(); 1285} 1286 1287SDValue DAGCombiner::visitADD(SDNode *N) { 1288 SDValue N0 = N->getOperand(0); 1289 SDValue N1 = N->getOperand(1); 1290 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1291 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1292 EVT VT = N0.getValueType(); 1293 1294 // fold vector ops 1295 if (VT.isVector()) { 1296 SDValue FoldedVOp = SimplifyVBinOp(N); 1297 if (FoldedVOp.getNode()) return FoldedVOp; 1298 } 1299 1300 // fold (add x, undef) -> undef 1301 if (N0.getOpcode() == ISD::UNDEF) 1302 return N0; 1303 if (N1.getOpcode() == ISD::UNDEF) 1304 return N1; 1305 // fold (add c1, c2) -> c1+c2 1306 if (N0C && N1C) 1307 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C); 1308 // canonicalize constant to RHS 1309 if (N0C && !N1C) 1310 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0); 1311 // fold (add x, 0) -> x 1312 if (N1C && N1C->isNullValue()) 1313 return N0; 1314 // fold (add Sym, c) -> Sym+c 1315 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1316 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C && 1317 GA->getOpcode() == ISD::GlobalAddress) 1318 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT, 1319 GA->getOffset() + 1320 (uint64_t)N1C->getSExtValue()); 1321 // fold ((c1-A)+c2) -> (c1+c2)-A 1322 if (N1C && N0.getOpcode() == ISD::SUB) 1323 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 1324 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1325 DAG.getConstant(N1C->getAPIntValue()+ 1326 N0C->getAPIntValue(), VT), 1327 N0.getOperand(1)); 1328 // reassociate add 1329 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1); 1330 if (RADD.getNode() != 0) 1331 return RADD; 1332 // fold ((0-A) + B) -> B-A 1333 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 1334 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 1335 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1)); 1336 // fold (A + (0-B)) -> A-B 1337 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1338 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 1339 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1)); 1340 // fold (A+(B-A)) -> B 1341 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 1342 return N1.getOperand(0); 1343 // fold ((B-A)+A) -> B 1344 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) 1345 return N0.getOperand(0); 1346 // fold (A+(B-(A+C))) to (B-C) 1347 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1348 N0 == N1.getOperand(1).getOperand(0)) 1349 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1350 N1.getOperand(1).getOperand(1)); 1351 // fold (A+(B-(C+A))) to (B-C) 1352 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1353 N0 == N1.getOperand(1).getOperand(1)) 1354 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1355 N1.getOperand(1).getOperand(0)); 1356 // fold (A+((B-A)+or-C)) to (B+or-C) 1357 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && 1358 N1.getOperand(0).getOpcode() == ISD::SUB && 1359 N0 == N1.getOperand(0).getOperand(1)) 1360 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT, 1361 N1.getOperand(0).getOperand(0), N1.getOperand(1)); 1362 1363 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant 1364 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) { 1365 SDValue N00 = N0.getOperand(0); 1366 SDValue N01 = N0.getOperand(1); 1367 SDValue N10 = N1.getOperand(0); 1368 SDValue N11 = N1.getOperand(1); 1369 1370 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10)) 1371 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1372 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10), 1373 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11)); 1374 } 1375 1376 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 1377 return SDValue(N, 0); 1378 1379 // fold (a+b) -> (a|b) iff a and b share no bits. 1380 if (VT.isInteger() && !VT.isVector()) { 1381 APInt LHSZero, LHSOne; 1382 APInt RHSZero, RHSOne; 1383 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 1384 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1385 1386 if (LHSZero.getBoolValue()) { 1387 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1388 1389 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1390 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1391 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1392 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1393 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1); 1394 } 1395 } 1396 1397 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1398 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1399 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG); 1400 if (Result.getNode()) return Result; 1401 } 1402 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1403 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG); 1404 if (Result.getNode()) return Result; 1405 } 1406 1407 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n)) 1408 if (N1.getOpcode() == ISD::SHL && 1409 N1.getOperand(0).getOpcode() == ISD::SUB) 1410 if (ConstantSDNode *C = 1411 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0))) 1412 if (C->getAPIntValue() == 0) 1413 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, 1414 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1415 N1.getOperand(0).getOperand(1), 1416 N1.getOperand(1))); 1417 if (N0.getOpcode() == ISD::SHL && 1418 N0.getOperand(0).getOpcode() == ISD::SUB) 1419 if (ConstantSDNode *C = 1420 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0))) 1421 if (C->getAPIntValue() == 0) 1422 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, 1423 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1424 N0.getOperand(0).getOperand(1), 1425 N0.getOperand(1))); 1426 1427 if (N1.getOpcode() == ISD::AND) { 1428 SDValue AndOp0 = N1.getOperand(0); 1429 ConstantSDNode *AndOp1 = dyn_cast<ConstantSDNode>(N1->getOperand(1)); 1430 unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0); 1431 unsigned DestBits = VT.getScalarType().getSizeInBits(); 1432 1433 // (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x)) 1434 // and similar xforms where the inner op is either ~0 or 0. 1435 if (NumSignBits == DestBits && AndOp1 && AndOp1->isOne()) { 1436 DebugLoc DL = N->getDebugLoc(); 1437 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0); 1438 } 1439 } 1440 1441 return SDValue(); 1442} 1443 1444SDValue DAGCombiner::visitADDC(SDNode *N) { 1445 SDValue N0 = N->getOperand(0); 1446 SDValue N1 = N->getOperand(1); 1447 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1448 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1449 EVT VT = N0.getValueType(); 1450 1451 // If the flag result is dead, turn this into an ADD. 1452 if (N->hasNUsesOfValue(0, 1)) 1453 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0), 1454 DAG.getNode(ISD::CARRY_FALSE, 1455 N->getDebugLoc(), MVT::Flag)); 1456 1457 // canonicalize constant to RHS. 1458 if (N0C && !N1C) 1459 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1460 1461 // fold (addc x, 0) -> x + no carry out 1462 if (N1C && N1C->isNullValue()) 1463 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, 1464 N->getDebugLoc(), MVT::Flag)); 1465 1466 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1467 APInt LHSZero, LHSOne; 1468 APInt RHSZero, RHSOne; 1469 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 1470 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1471 1472 if (LHSZero.getBoolValue()) { 1473 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1474 1475 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1476 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1477 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1478 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1479 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1), 1480 DAG.getNode(ISD::CARRY_FALSE, 1481 N->getDebugLoc(), MVT::Flag)); 1482 } 1483 1484 return SDValue(); 1485} 1486 1487SDValue DAGCombiner::visitADDE(SDNode *N) { 1488 SDValue N0 = N->getOperand(0); 1489 SDValue N1 = N->getOperand(1); 1490 SDValue CarryIn = N->getOperand(2); 1491 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1492 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1493 1494 // canonicalize constant to RHS 1495 if (N0C && !N1C) 1496 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), 1497 N1, N0, CarryIn); 1498 1499 // fold (adde x, y, false) -> (addc x, y) 1500 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1501 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1502 1503 return SDValue(); 1504} 1505 1506SDValue DAGCombiner::visitSUB(SDNode *N) { 1507 SDValue N0 = N->getOperand(0); 1508 SDValue N1 = N->getOperand(1); 1509 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1510 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1511 EVT VT = N0.getValueType(); 1512 1513 // fold vector ops 1514 if (VT.isVector()) { 1515 SDValue FoldedVOp = SimplifyVBinOp(N); 1516 if (FoldedVOp.getNode()) return FoldedVOp; 1517 } 1518 1519 // fold (sub x, x) -> 0 1520 if (N0 == N1) 1521 return DAG.getConstant(0, N->getValueType(0)); 1522 // fold (sub c1, c2) -> c1-c2 1523 if (N0C && N1C) 1524 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C); 1525 // fold (sub x, c) -> (add x, -c) 1526 if (N1C) 1527 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, 1528 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1529 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) 1530 if (N0C && N0C->isAllOnesValue()) 1531 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 1532 // fold (A+B)-A -> B 1533 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1534 return N0.getOperand(1); 1535 // fold (A+B)-B -> A 1536 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1537 return N0.getOperand(0); 1538 // fold ((A+(B+or-C))-B) -> A+or-C 1539 if (N0.getOpcode() == ISD::ADD && 1540 (N0.getOperand(1).getOpcode() == ISD::SUB || 1541 N0.getOperand(1).getOpcode() == ISD::ADD) && 1542 N0.getOperand(1).getOperand(0) == N1) 1543 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT, 1544 N0.getOperand(0), N0.getOperand(1).getOperand(1)); 1545 // fold ((A+(C+B))-B) -> A+C 1546 if (N0.getOpcode() == ISD::ADD && 1547 N0.getOperand(1).getOpcode() == ISD::ADD && 1548 N0.getOperand(1).getOperand(1) == N1) 1549 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1550 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1551 // fold ((A-(B-C))-C) -> A-B 1552 if (N0.getOpcode() == ISD::SUB && 1553 N0.getOperand(1).getOpcode() == ISD::SUB && 1554 N0.getOperand(1).getOperand(1) == N1) 1555 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1556 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1557 1558 // If either operand of a sub is undef, the result is undef 1559 if (N0.getOpcode() == ISD::UNDEF) 1560 return N0; 1561 if (N1.getOpcode() == ISD::UNDEF) 1562 return N1; 1563 1564 // If the relocation model supports it, consider symbol offsets. 1565 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1566 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) { 1567 // fold (sub Sym, c) -> Sym-c 1568 if (N1C && GA->getOpcode() == ISD::GlobalAddress) 1569 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT, 1570 GA->getOffset() - 1571 (uint64_t)N1C->getSExtValue()); 1572 // fold (sub Sym+c1, Sym+c2) -> c1-c2 1573 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1)) 1574 if (GA->getGlobal() == GB->getGlobal()) 1575 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(), 1576 VT); 1577 } 1578 1579 return SDValue(); 1580} 1581 1582SDValue DAGCombiner::visitMUL(SDNode *N) { 1583 SDValue N0 = N->getOperand(0); 1584 SDValue N1 = N->getOperand(1); 1585 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1586 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1587 EVT VT = N0.getValueType(); 1588 1589 // fold vector ops 1590 if (VT.isVector()) { 1591 SDValue FoldedVOp = SimplifyVBinOp(N); 1592 if (FoldedVOp.getNode()) return FoldedVOp; 1593 } 1594 1595 // fold (mul x, undef) -> 0 1596 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1597 return DAG.getConstant(0, VT); 1598 // fold (mul c1, c2) -> c1*c2 1599 if (N0C && N1C) 1600 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C); 1601 // canonicalize constant to RHS 1602 if (N0C && !N1C) 1603 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0); 1604 // fold (mul x, 0) -> 0 1605 if (N1C && N1C->isNullValue()) 1606 return N1; 1607 // fold (mul x, -1) -> 0-x 1608 if (N1C && N1C->isAllOnesValue()) 1609 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1610 DAG.getConstant(0, VT), N0); 1611 // fold (mul x, (1 << c)) -> x << c 1612 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1613 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1614 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1615 getShiftAmountTy())); 1616 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1617 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) { 1618 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2(); 1619 // FIXME: If the input is something that is easily negated (e.g. a 1620 // single-use add), we should put the negate there. 1621 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1622 DAG.getConstant(0, VT), 1623 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1624 DAG.getConstant(Log2Val, getShiftAmountTy()))); 1625 } 1626 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1627 if (N1C && N0.getOpcode() == ISD::SHL && 1628 isa<ConstantSDNode>(N0.getOperand(1))) { 1629 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1630 N1, N0.getOperand(1)); 1631 AddToWorkList(C3.getNode()); 1632 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1633 N0.getOperand(0), C3); 1634 } 1635 1636 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1637 // use. 1638 { 1639 SDValue Sh(0,0), Y(0,0); 1640 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1641 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1642 N0.getNode()->hasOneUse()) { 1643 Sh = N0; Y = N1; 1644 } else if (N1.getOpcode() == ISD::SHL && 1645 isa<ConstantSDNode>(N1.getOperand(1)) && 1646 N1.getNode()->hasOneUse()) { 1647 Sh = N1; Y = N0; 1648 } 1649 1650 if (Sh.getNode()) { 1651 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1652 Sh.getOperand(0), Y); 1653 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1654 Mul, Sh.getOperand(1)); 1655 } 1656 } 1657 1658 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1659 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 1660 isa<ConstantSDNode>(N0.getOperand(1))) 1661 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1662 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT, 1663 N0.getOperand(0), N1), 1664 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT, 1665 N0.getOperand(1), N1)); 1666 1667 // reassociate mul 1668 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1); 1669 if (RMUL.getNode() != 0) 1670 return RMUL; 1671 1672 return SDValue(); 1673} 1674 1675SDValue DAGCombiner::visitSDIV(SDNode *N) { 1676 SDValue N0 = N->getOperand(0); 1677 SDValue N1 = N->getOperand(1); 1678 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1679 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1680 EVT VT = N->getValueType(0); 1681 1682 // fold vector ops 1683 if (VT.isVector()) { 1684 SDValue FoldedVOp = SimplifyVBinOp(N); 1685 if (FoldedVOp.getNode()) return FoldedVOp; 1686 } 1687 1688 // fold (sdiv c1, c2) -> c1/c2 1689 if (N0C && N1C && !N1C->isNullValue()) 1690 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); 1691 // fold (sdiv X, 1) -> X 1692 if (N1C && N1C->getSExtValue() == 1LL) 1693 return N0; 1694 // fold (sdiv X, -1) -> 0-X 1695 if (N1C && N1C->isAllOnesValue()) 1696 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1697 DAG.getConstant(0, VT), N0); 1698 // If we know the sign bits of both operands are zero, strength reduce to a 1699 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1700 if (!VT.isVector()) { 1701 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1702 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(), 1703 N0, N1); 1704 } 1705 // fold (sdiv X, pow2) -> simple ops after legalize 1706 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() && 1707 (isPowerOf2_64(N1C->getSExtValue()) || 1708 isPowerOf2_64(-N1C->getSExtValue()))) { 1709 // If dividing by powers of two is cheap, then don't perform the following 1710 // fold. 1711 if (TLI.isPow2DivCheap()) 1712 return SDValue(); 1713 1714 int64_t pow2 = N1C->getSExtValue(); 1715 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1716 unsigned lg2 = Log2_64(abs2); 1717 1718 // Splat the sign bit into the register 1719 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 1720 DAG.getConstant(VT.getSizeInBits()-1, 1721 getShiftAmountTy())); 1722 AddToWorkList(SGN.getNode()); 1723 1724 // Add (N0 < 0) ? abs2 - 1 : 0; 1725 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN, 1726 DAG.getConstant(VT.getSizeInBits() - lg2, 1727 getShiftAmountTy())); 1728 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL); 1729 AddToWorkList(SRL.getNode()); 1730 AddToWorkList(ADD.getNode()); // Divide by pow2 1731 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD, 1732 DAG.getConstant(lg2, getShiftAmountTy())); 1733 1734 // If we're dividing by a positive value, we're done. Otherwise, we must 1735 // negate the result. 1736 if (pow2 > 0) 1737 return SRA; 1738 1739 AddToWorkList(SRA.getNode()); 1740 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1741 DAG.getConstant(0, VT), SRA); 1742 } 1743 1744 // if integer divide is expensive and we satisfy the requirements, emit an 1745 // alternate sequence. 1746 if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) && 1747 !TLI.isIntDivCheap()) { 1748 SDValue Op = BuildSDIV(N); 1749 if (Op.getNode()) return Op; 1750 } 1751 1752 // undef / X -> 0 1753 if (N0.getOpcode() == ISD::UNDEF) 1754 return DAG.getConstant(0, VT); 1755 // X / undef -> undef 1756 if (N1.getOpcode() == ISD::UNDEF) 1757 return N1; 1758 1759 return SDValue(); 1760} 1761 1762SDValue DAGCombiner::visitUDIV(SDNode *N) { 1763 SDValue N0 = N->getOperand(0); 1764 SDValue N1 = N->getOperand(1); 1765 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1766 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1767 EVT VT = N->getValueType(0); 1768 1769 // fold vector ops 1770 if (VT.isVector()) { 1771 SDValue FoldedVOp = SimplifyVBinOp(N); 1772 if (FoldedVOp.getNode()) return FoldedVOp; 1773 } 1774 1775 // fold (udiv c1, c2) -> c1/c2 1776 if (N0C && N1C && !N1C->isNullValue()) 1777 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); 1778 // fold (udiv x, (1 << c)) -> x >>u c 1779 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1780 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 1781 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1782 getShiftAmountTy())); 1783 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1784 if (N1.getOpcode() == ISD::SHL) { 1785 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1786 if (SHC->getAPIntValue().isPowerOf2()) { 1787 EVT ADDVT = N1.getOperand(1).getValueType(); 1788 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT, 1789 N1.getOperand(1), 1790 DAG.getConstant(SHC->getAPIntValue() 1791 .logBase2(), 1792 ADDVT)); 1793 AddToWorkList(Add.getNode()); 1794 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add); 1795 } 1796 } 1797 } 1798 // fold (udiv x, c) -> alternate 1799 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1800 SDValue Op = BuildUDIV(N); 1801 if (Op.getNode()) return Op; 1802 } 1803 1804 // undef / X -> 0 1805 if (N0.getOpcode() == ISD::UNDEF) 1806 return DAG.getConstant(0, VT); 1807 // X / undef -> undef 1808 if (N1.getOpcode() == ISD::UNDEF) 1809 return N1; 1810 1811 return SDValue(); 1812} 1813 1814SDValue DAGCombiner::visitSREM(SDNode *N) { 1815 SDValue N0 = N->getOperand(0); 1816 SDValue N1 = N->getOperand(1); 1817 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1818 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1819 EVT VT = N->getValueType(0); 1820 1821 // fold (srem c1, c2) -> c1%c2 1822 if (N0C && N1C && !N1C->isNullValue()) 1823 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); 1824 // If we know the sign bits of both operands are zero, strength reduce to a 1825 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1826 if (!VT.isVector()) { 1827 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1828 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1); 1829 } 1830 1831 // If X/C can be simplified by the division-by-constant logic, lower 1832 // X%C to the equivalent of X-X/C*C. 1833 if (N1C && !N1C->isNullValue()) { 1834 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1); 1835 AddToWorkList(Div.getNode()); 1836 SDValue OptimizedDiv = combine(Div.getNode()); 1837 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1838 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1839 OptimizedDiv, N1); 1840 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1841 AddToWorkList(Mul.getNode()); 1842 return Sub; 1843 } 1844 } 1845 1846 // undef % X -> 0 1847 if (N0.getOpcode() == ISD::UNDEF) 1848 return DAG.getConstant(0, VT); 1849 // X % undef -> undef 1850 if (N1.getOpcode() == ISD::UNDEF) 1851 return N1; 1852 1853 return SDValue(); 1854} 1855 1856SDValue DAGCombiner::visitUREM(SDNode *N) { 1857 SDValue N0 = N->getOperand(0); 1858 SDValue N1 = N->getOperand(1); 1859 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1860 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1861 EVT VT = N->getValueType(0); 1862 1863 // fold (urem c1, c2) -> c1%c2 1864 if (N0C && N1C && !N1C->isNullValue()) 1865 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C); 1866 // fold (urem x, pow2) -> (and x, pow2-1) 1867 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 1868 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, 1869 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 1870 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1871 if (N1.getOpcode() == ISD::SHL) { 1872 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1873 if (SHC->getAPIntValue().isPowerOf2()) { 1874 SDValue Add = 1875 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, 1876 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 1877 VT)); 1878 AddToWorkList(Add.getNode()); 1879 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add); 1880 } 1881 } 1882 } 1883 1884 // If X/C can be simplified by the division-by-constant logic, lower 1885 // X%C to the equivalent of X-X/C*C. 1886 if (N1C && !N1C->isNullValue()) { 1887 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1); 1888 AddToWorkList(Div.getNode()); 1889 SDValue OptimizedDiv = combine(Div.getNode()); 1890 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1891 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1892 OptimizedDiv, N1); 1893 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1894 AddToWorkList(Mul.getNode()); 1895 return Sub; 1896 } 1897 } 1898 1899 // undef % X -> 0 1900 if (N0.getOpcode() == ISD::UNDEF) 1901 return DAG.getConstant(0, VT); 1902 // X % undef -> undef 1903 if (N1.getOpcode() == ISD::UNDEF) 1904 return N1; 1905 1906 return SDValue(); 1907} 1908 1909SDValue DAGCombiner::visitMULHS(SDNode *N) { 1910 SDValue N0 = N->getOperand(0); 1911 SDValue N1 = N->getOperand(1); 1912 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1913 EVT VT = N->getValueType(0); 1914 1915 // fold (mulhs x, 0) -> 0 1916 if (N1C && N1C->isNullValue()) 1917 return N1; 1918 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1919 if (N1C && N1C->getAPIntValue() == 1) 1920 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0, 1921 DAG.getConstant(N0.getValueType().getSizeInBits() - 1, 1922 getShiftAmountTy())); 1923 // fold (mulhs x, undef) -> 0 1924 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1925 return DAG.getConstant(0, VT); 1926 1927 return SDValue(); 1928} 1929 1930SDValue DAGCombiner::visitMULHU(SDNode *N) { 1931 SDValue N0 = N->getOperand(0); 1932 SDValue N1 = N->getOperand(1); 1933 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1934 EVT VT = N->getValueType(0); 1935 1936 // fold (mulhu x, 0) -> 0 1937 if (N1C && N1C->isNullValue()) 1938 return N1; 1939 // fold (mulhu x, 1) -> 0 1940 if (N1C && N1C->getAPIntValue() == 1) 1941 return DAG.getConstant(0, N0.getValueType()); 1942 // fold (mulhu x, undef) -> 0 1943 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1944 return DAG.getConstant(0, VT); 1945 1946 return SDValue(); 1947} 1948 1949/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 1950/// compute two values. LoOp and HiOp give the opcodes for the two computations 1951/// that are being performed. Return true if a simplification was made. 1952/// 1953SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 1954 unsigned HiOp) { 1955 // If the high half is not needed, just compute the low half. 1956 bool HiExists = N->hasAnyUseOfValue(1); 1957 if (!HiExists && 1958 (!LegalOperations || 1959 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 1960 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 1961 N->op_begin(), N->getNumOperands()); 1962 return CombineTo(N, Res, Res); 1963 } 1964 1965 // If the low half is not needed, just compute the high half. 1966 bool LoExists = N->hasAnyUseOfValue(0); 1967 if (!LoExists && 1968 (!LegalOperations || 1969 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 1970 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 1971 N->op_begin(), N->getNumOperands()); 1972 return CombineTo(N, Res, Res); 1973 } 1974 1975 // If both halves are used, return as it is. 1976 if (LoExists && HiExists) 1977 return SDValue(); 1978 1979 // If the two computed results can be simplified separately, separate them. 1980 if (LoExists) { 1981 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 1982 N->op_begin(), N->getNumOperands()); 1983 AddToWorkList(Lo.getNode()); 1984 SDValue LoOpt = combine(Lo.getNode()); 1985 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && 1986 (!LegalOperations || 1987 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 1988 return CombineTo(N, LoOpt, LoOpt); 1989 } 1990 1991 if (HiExists) { 1992 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 1993 N->op_begin(), N->getNumOperands()); 1994 AddToWorkList(Hi.getNode()); 1995 SDValue HiOpt = combine(Hi.getNode()); 1996 if (HiOpt.getNode() && HiOpt != Hi && 1997 (!LegalOperations || 1998 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 1999 return CombineTo(N, HiOpt, HiOpt); 2000 } 2001 2002 return SDValue(); 2003} 2004 2005SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 2006 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 2007 if (Res.getNode()) return Res; 2008 2009 return SDValue(); 2010} 2011 2012SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 2013 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 2014 if (Res.getNode()) return Res; 2015 2016 return SDValue(); 2017} 2018 2019SDValue DAGCombiner::visitSDIVREM(SDNode *N) { 2020 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 2021 if (Res.getNode()) return Res; 2022 2023 return SDValue(); 2024} 2025 2026SDValue DAGCombiner::visitUDIVREM(SDNode *N) { 2027 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 2028 if (Res.getNode()) return Res; 2029 2030 return SDValue(); 2031} 2032 2033/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 2034/// two operands of the same opcode, try to simplify it. 2035SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 2036 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 2037 EVT VT = N0.getValueType(); 2038 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 2039 2040 // Bail early if none of these transforms apply. 2041 if (N0.getNode()->getNumOperands() == 0) return SDValue(); 2042 2043 // For each of OP in AND/OR/XOR: 2044 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 2045 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 2046 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 2047 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free) 2048 // 2049 // do not sink logical op inside of a vector extend, since it may combine 2050 // into a vsetcc. 2051 EVT Op0VT = N0.getOperand(0).getValueType(); 2052 if ((N0.getOpcode() == ISD::ZERO_EXTEND || 2053 N0.getOpcode() == ISD::SIGN_EXTEND || 2054 // Avoid infinite looping with PromoteIntBinOp. 2055 (N0.getOpcode() == ISD::ANY_EXTEND && 2056 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) || 2057 (N0.getOpcode() == ISD::TRUNCATE && 2058 (!TLI.isZExtFree(VT, Op0VT) || 2059 !TLI.isTruncateFree(Op0VT, VT)) && 2060 TLI.isTypeLegal(Op0VT))) && 2061 !VT.isVector() && 2062 Op0VT == N1.getOperand(0).getValueType() && 2063 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) { 2064 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 2065 N0.getOperand(0).getValueType(), 2066 N0.getOperand(0), N1.getOperand(0)); 2067 AddToWorkList(ORNode.getNode()); 2068 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode); 2069 } 2070 2071 // For each of OP in SHL/SRL/SRA/AND... 2072 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 2073 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 2074 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 2075 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 2076 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 2077 N0.getOperand(1) == N1.getOperand(1)) { 2078 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 2079 N0.getOperand(0).getValueType(), 2080 N0.getOperand(0), N1.getOperand(0)); 2081 AddToWorkList(ORNode.getNode()); 2082 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 2083 ORNode, N0.getOperand(1)); 2084 } 2085 2086 return SDValue(); 2087} 2088 2089SDValue DAGCombiner::visitAND(SDNode *N) { 2090 SDValue N0 = N->getOperand(0); 2091 SDValue N1 = N->getOperand(1); 2092 SDValue LL, LR, RL, RR, CC0, CC1; 2093 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2094 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2095 EVT VT = N1.getValueType(); 2096 unsigned BitWidth = VT.getScalarType().getSizeInBits(); 2097 2098 // fold vector ops 2099 if (VT.isVector()) { 2100 SDValue FoldedVOp = SimplifyVBinOp(N); 2101 if (FoldedVOp.getNode()) return FoldedVOp; 2102 } 2103 2104 // fold (and x, undef) -> 0 2105 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2106 return DAG.getConstant(0, VT); 2107 // fold (and c1, c2) -> c1&c2 2108 if (N0C && N1C) 2109 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C); 2110 // canonicalize constant to RHS 2111 if (N0C && !N1C) 2112 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0); 2113 // fold (and x, -1) -> x 2114 if (N1C && N1C->isAllOnesValue()) 2115 return N0; 2116 // if (and x, c) is known to be zero, return 0 2117 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2118 APInt::getAllOnesValue(BitWidth))) 2119 return DAG.getConstant(0, VT); 2120 // reassociate and 2121 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1); 2122 if (RAND.getNode() != 0) 2123 return RAND; 2124 // fold (and (or x, C), D) -> D if (C & D) == D 2125 if (N1C && N0.getOpcode() == ISD::OR) 2126 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 2127 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 2128 return N1; 2129 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 2130 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2131 SDValue N0Op0 = N0.getOperand(0); 2132 APInt Mask = ~N1C->getAPIntValue(); 2133 Mask.trunc(N0Op0.getValueSizeInBits()); 2134 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 2135 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), 2136 N0.getValueType(), N0Op0); 2137 2138 // Replace uses of the AND with uses of the Zero extend node. 2139 CombineTo(N, Zext); 2140 2141 // We actually want to replace all uses of the any_extend with the 2142 // zero_extend, to avoid duplicating things. This will later cause this 2143 // AND to be folded. 2144 CombineTo(N0.getNode(), Zext); 2145 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2146 } 2147 } 2148 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 2149 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 2150 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 2151 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 2152 2153 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 2154 LL.getValueType().isInteger()) { 2155 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0) 2156 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 2157 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 2158 LR.getValueType(), LL, RL); 2159 AddToWorkList(ORNode.getNode()); 2160 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2161 } 2162 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1) 2163 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 2164 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(), 2165 LR.getValueType(), LL, RL); 2166 AddToWorkList(ANDNode.getNode()); 2167 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 2168 } 2169 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1) 2170 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 2171 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 2172 LR.getValueType(), LL, RL); 2173 AddToWorkList(ORNode.getNode()); 2174 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2175 } 2176 } 2177 // canonicalize equivalent to ll == rl 2178 if (LL == RR && LR == RL) { 2179 Op1 = ISD::getSetCCSwappedOperands(Op1); 2180 std::swap(RL, RR); 2181 } 2182 if (LL == RL && LR == RR) { 2183 bool isInteger = LL.getValueType().isInteger(); 2184 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 2185 if (Result != ISD::SETCC_INVALID && 2186 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 2187 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 2188 LL, LR, Result); 2189 } 2190 } 2191 2192 // Simplify: (and (op x...), (op y...)) -> (op (and x, y)) 2193 if (N0.getOpcode() == N1.getOpcode()) { 2194 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2195 if (Tmp.getNode()) return Tmp; 2196 } 2197 2198 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 2199 // fold (and (sra)) -> (and (srl)) when possible. 2200 if (!VT.isVector() && 2201 SimplifyDemandedBits(SDValue(N, 0))) 2202 return SDValue(N, 0); 2203 2204 // fold (zext_inreg (extload x)) -> (zextload x) 2205 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { 2206 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2207 EVT MemVT = LN0->getMemoryVT(); 2208 // If we zero all the possible extended bits, then we can turn this into 2209 // a zextload if we are running before legalize or the operation is legal. 2210 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2211 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2212 BitWidth - MemVT.getScalarType().getSizeInBits())) && 2213 ((!LegalOperations && !LN0->isVolatile()) || 2214 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2215 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getDebugLoc(), 2216 LN0->getChain(), LN0->getBasePtr(), 2217 LN0->getPointerInfo(), MemVT, 2218 LN0->isVolatile(), LN0->isNonTemporal(), 2219 LN0->getAlignment()); 2220 AddToWorkList(N); 2221 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2222 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2223 } 2224 } 2225 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 2226 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 2227 N0.hasOneUse()) { 2228 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2229 EVT MemVT = LN0->getMemoryVT(); 2230 // If we zero all the possible extended bits, then we can turn this into 2231 // a zextload if we are running before legalize or the operation is legal. 2232 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2233 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2234 BitWidth - MemVT.getScalarType().getSizeInBits())) && 2235 ((!LegalOperations && !LN0->isVolatile()) || 2236 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2237 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getDebugLoc(), 2238 LN0->getChain(), 2239 LN0->getBasePtr(), LN0->getPointerInfo(), 2240 MemVT, 2241 LN0->isVolatile(), LN0->isNonTemporal(), 2242 LN0->getAlignment()); 2243 AddToWorkList(N); 2244 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2245 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2246 } 2247 } 2248 2249 // fold (and (load x), 255) -> (zextload x, i8) 2250 // fold (and (extload x, i16), 255) -> (zextload x, i8) 2251 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8) 2252 if (N1C && (N0.getOpcode() == ISD::LOAD || 2253 (N0.getOpcode() == ISD::ANY_EXTEND && 2254 N0.getOperand(0).getOpcode() == ISD::LOAD))) { 2255 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND; 2256 LoadSDNode *LN0 = HasAnyExt 2257 ? cast<LoadSDNode>(N0.getOperand(0)) 2258 : cast<LoadSDNode>(N0); 2259 if (LN0->getExtensionType() != ISD::SEXTLOAD && 2260 LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) { 2261 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 2262 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){ 2263 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits); 2264 EVT LoadedVT = LN0->getMemoryVT(); 2265 2266 if (ExtVT == LoadedVT && 2267 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2268 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2269 2270 SDValue NewLoad = 2271 DAG.getExtLoad(ISD::ZEXTLOAD, LoadResultTy, LN0->getDebugLoc(), 2272 LN0->getChain(), LN0->getBasePtr(), 2273 LN0->getPointerInfo(), 2274 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 2275 LN0->getAlignment()); 2276 AddToWorkList(N); 2277 CombineTo(LN0, NewLoad, NewLoad.getValue(1)); 2278 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2279 } 2280 2281 // Do not change the width of a volatile load. 2282 // Do not generate loads of non-round integer types since these can 2283 // be expensive (and would be wrong if the type is not byte sized). 2284 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() && 2285 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2286 EVT PtrType = LN0->getOperand(1).getValueType(); 2287 2288 unsigned Alignment = LN0->getAlignment(); 2289 SDValue NewPtr = LN0->getBasePtr(); 2290 2291 // For big endian targets, we need to add an offset to the pointer 2292 // to load the correct bytes. For little endian systems, we merely 2293 // need to read fewer bytes from the same pointer. 2294 if (TLI.isBigEndian()) { 2295 unsigned LVTStoreBytes = LoadedVT.getStoreSize(); 2296 unsigned EVTStoreBytes = ExtVT.getStoreSize(); 2297 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 2298 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType, 2299 NewPtr, DAG.getConstant(PtrOff, PtrType)); 2300 Alignment = MinAlign(Alignment, PtrOff); 2301 } 2302 2303 AddToWorkList(NewPtr.getNode()); 2304 2305 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2306 SDValue Load = 2307 DAG.getExtLoad(ISD::ZEXTLOAD, LoadResultTy, LN0->getDebugLoc(), 2308 LN0->getChain(), NewPtr, 2309 LN0->getPointerInfo(), 2310 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 2311 Alignment); 2312 AddToWorkList(N); 2313 CombineTo(LN0, Load, Load.getValue(1)); 2314 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2315 } 2316 } 2317 } 2318 } 2319 2320 return SDValue(); 2321} 2322 2323SDValue DAGCombiner::visitOR(SDNode *N) { 2324 SDValue N0 = N->getOperand(0); 2325 SDValue N1 = N->getOperand(1); 2326 SDValue LL, LR, RL, RR, CC0, CC1; 2327 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2328 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2329 EVT VT = N1.getValueType(); 2330 2331 // fold vector ops 2332 if (VT.isVector()) { 2333 SDValue FoldedVOp = SimplifyVBinOp(N); 2334 if (FoldedVOp.getNode()) return FoldedVOp; 2335 } 2336 2337 // fold (or x, undef) -> -1 2338 if (!LegalOperations && 2339 (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) { 2340 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 2341 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT); 2342 } 2343 // fold (or c1, c2) -> c1|c2 2344 if (N0C && N1C) 2345 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); 2346 // canonicalize constant to RHS 2347 if (N0C && !N1C) 2348 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0); 2349 // fold (or x, 0) -> x 2350 if (N1C && N1C->isNullValue()) 2351 return N0; 2352 // fold (or x, -1) -> -1 2353 if (N1C && N1C->isAllOnesValue()) 2354 return N1; 2355 // fold (or x, c) -> c iff (x & ~c) == 0 2356 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 2357 return N1; 2358 // reassociate or 2359 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1); 2360 if (ROR.getNode() != 0) 2361 return ROR; 2362 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 2363 // iff (c1 & c2) == 0. 2364 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 2365 isa<ConstantSDNode>(N0.getOperand(1))) { 2366 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 2367 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0) 2368 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 2369 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 2370 N0.getOperand(0), N1), 2371 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1)); 2372 } 2373 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 2374 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 2375 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 2376 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 2377 2378 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 2379 LL.getValueType().isInteger()) { 2380 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0) 2381 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0) 2382 if (cast<ConstantSDNode>(LR)->isNullValue() && 2383 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 2384 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(), 2385 LR.getValueType(), LL, RL); 2386 AddToWorkList(ORNode.getNode()); 2387 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2388 } 2389 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1) 2390 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1) 2391 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 2392 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 2393 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(), 2394 LR.getValueType(), LL, RL); 2395 AddToWorkList(ANDNode.getNode()); 2396 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 2397 } 2398 } 2399 // canonicalize equivalent to ll == rl 2400 if (LL == RR && LR == RL) { 2401 Op1 = ISD::getSetCCSwappedOperands(Op1); 2402 std::swap(RL, RR); 2403 } 2404 if (LL == RL && LR == RR) { 2405 bool isInteger = LL.getValueType().isInteger(); 2406 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 2407 if (Result != ISD::SETCC_INVALID && 2408 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 2409 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 2410 LL, LR, Result); 2411 } 2412 } 2413 2414 // Simplify: (or (op x...), (op y...)) -> (op (or x, y)) 2415 if (N0.getOpcode() == N1.getOpcode()) { 2416 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2417 if (Tmp.getNode()) return Tmp; 2418 } 2419 2420 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible. 2421 if (N0.getOpcode() == ISD::AND && 2422 N1.getOpcode() == ISD::AND && 2423 N0.getOperand(1).getOpcode() == ISD::Constant && 2424 N1.getOperand(1).getOpcode() == ISD::Constant && 2425 // Don't increase # computations. 2426 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) { 2427 // We can only do this xform if we know that bits from X that are set in C2 2428 // but not in C1 are already zero. Likewise for Y. 2429 const APInt &LHSMask = 2430 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 2431 const APInt &RHSMask = 2432 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 2433 2434 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 2435 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 2436 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 2437 N0.getOperand(0), N1.getOperand(0)); 2438 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X, 2439 DAG.getConstant(LHSMask | RHSMask, VT)); 2440 } 2441 } 2442 2443 // See if this is some rotate idiom. 2444 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc())) 2445 return SDValue(Rot, 0); 2446 2447 // Simplify the operands using demanded-bits information. 2448 if (!VT.isVector() && 2449 SimplifyDemandedBits(SDValue(N, 0))) 2450 return SDValue(N, 0); 2451 2452 return SDValue(); 2453} 2454 2455/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 2456static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 2457 if (Op.getOpcode() == ISD::AND) { 2458 if (isa<ConstantSDNode>(Op.getOperand(1))) { 2459 Mask = Op.getOperand(1); 2460 Op = Op.getOperand(0); 2461 } else { 2462 return false; 2463 } 2464 } 2465 2466 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 2467 Shift = Op; 2468 return true; 2469 } 2470 2471 return false; 2472} 2473 2474// MatchRotate - Handle an 'or' of two operands. If this is one of the many 2475// idioms for rotate, and if the target supports rotation instructions, generate 2476// a rot[lr]. 2477SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) { 2478 // Must be a legal type. Expanded 'n promoted things won't work with rotates. 2479 EVT VT = LHS.getValueType(); 2480 if (!TLI.isTypeLegal(VT)) return 0; 2481 2482 // The target must have at least one rotate flavor. 2483 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT); 2484 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT); 2485 if (!HasROTL && !HasROTR) return 0; 2486 2487 // Match "(X shl/srl V1) & V2" where V2 may not be present. 2488 SDValue LHSShift; // The shift. 2489 SDValue LHSMask; // AND value if any. 2490 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 2491 return 0; // Not part of a rotate. 2492 2493 SDValue RHSShift; // The shift. 2494 SDValue RHSMask; // AND value if any. 2495 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 2496 return 0; // Not part of a rotate. 2497 2498 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 2499 return 0; // Not shifting the same value. 2500 2501 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 2502 return 0; // Shifts must disagree. 2503 2504 // Canonicalize shl to left side in a shl/srl pair. 2505 if (RHSShift.getOpcode() == ISD::SHL) { 2506 std::swap(LHS, RHS); 2507 std::swap(LHSShift, RHSShift); 2508 std::swap(LHSMask , RHSMask ); 2509 } 2510 2511 unsigned OpSizeInBits = VT.getSizeInBits(); 2512 SDValue LHSShiftArg = LHSShift.getOperand(0); 2513 SDValue LHSShiftAmt = LHSShift.getOperand(1); 2514 SDValue RHSShiftAmt = RHSShift.getOperand(1); 2515 2516 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 2517 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 2518 if (LHSShiftAmt.getOpcode() == ISD::Constant && 2519 RHSShiftAmt.getOpcode() == ISD::Constant) { 2520 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue(); 2521 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue(); 2522 if ((LShVal + RShVal) != OpSizeInBits) 2523 return 0; 2524 2525 SDValue Rot; 2526 if (HasROTL) 2527 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt); 2528 else 2529 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt); 2530 2531 // If there is an AND of either shifted operand, apply it to the result. 2532 if (LHSMask.getNode() || RHSMask.getNode()) { 2533 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 2534 2535 if (LHSMask.getNode()) { 2536 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 2537 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 2538 } 2539 if (RHSMask.getNode()) { 2540 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 2541 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 2542 } 2543 2544 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT)); 2545 } 2546 2547 return Rot.getNode(); 2548 } 2549 2550 // If there is a mask here, and we have a variable shift, we can't be sure 2551 // that we're masking out the right stuff. 2552 if (LHSMask.getNode() || RHSMask.getNode()) 2553 return 0; 2554 2555 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 2556 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 2557 if (RHSShiftAmt.getOpcode() == ISD::SUB && 2558 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 2559 if (ConstantSDNode *SUBC = 2560 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 2561 if (SUBC->getAPIntValue() == OpSizeInBits) { 2562 if (HasROTL) 2563 return DAG.getNode(ISD::ROTL, DL, VT, 2564 LHSShiftArg, LHSShiftAmt).getNode(); 2565 else 2566 return DAG.getNode(ISD::ROTR, DL, VT, 2567 LHSShiftArg, RHSShiftAmt).getNode(); 2568 } 2569 } 2570 } 2571 2572 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 2573 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 2574 if (LHSShiftAmt.getOpcode() == ISD::SUB && 2575 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 2576 if (ConstantSDNode *SUBC = 2577 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 2578 if (SUBC->getAPIntValue() == OpSizeInBits) { 2579 if (HasROTR) 2580 return DAG.getNode(ISD::ROTR, DL, VT, 2581 LHSShiftArg, RHSShiftAmt).getNode(); 2582 else 2583 return DAG.getNode(ISD::ROTL, DL, VT, 2584 LHSShiftArg, LHSShiftAmt).getNode(); 2585 } 2586 } 2587 } 2588 2589 // Look for sign/zext/any-extended or truncate cases: 2590 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2591 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2592 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2593 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && 2594 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2595 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2596 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2597 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { 2598 SDValue LExtOp0 = LHSShiftAmt.getOperand(0); 2599 SDValue RExtOp0 = RHSShiftAmt.getOperand(0); 2600 if (RExtOp0.getOpcode() == ISD::SUB && 2601 RExtOp0.getOperand(1) == LExtOp0) { 2602 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2603 // (rotl x, y) 2604 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2605 // (rotr x, (sub 32, y)) 2606 if (ConstantSDNode *SUBC = 2607 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 2608 if (SUBC->getAPIntValue() == OpSizeInBits) { 2609 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 2610 LHSShiftArg, 2611 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 2612 } 2613 } 2614 } else if (LExtOp0.getOpcode() == ISD::SUB && 2615 RExtOp0 == LExtOp0.getOperand(1)) { 2616 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2617 // (rotr x, y) 2618 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2619 // (rotl x, (sub 32, y)) 2620 if (ConstantSDNode *SUBC = 2621 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 2622 if (SUBC->getAPIntValue() == OpSizeInBits) { 2623 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, 2624 LHSShiftArg, 2625 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 2626 } 2627 } 2628 } 2629 } 2630 2631 return 0; 2632} 2633 2634SDValue DAGCombiner::visitXOR(SDNode *N) { 2635 SDValue N0 = N->getOperand(0); 2636 SDValue N1 = N->getOperand(1); 2637 SDValue LHS, RHS, CC; 2638 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2639 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2640 EVT VT = N0.getValueType(); 2641 2642 // fold vector ops 2643 if (VT.isVector()) { 2644 SDValue FoldedVOp = SimplifyVBinOp(N); 2645 if (FoldedVOp.getNode()) return FoldedVOp; 2646 } 2647 2648 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 2649 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 2650 return DAG.getConstant(0, VT); 2651 // fold (xor x, undef) -> undef 2652 if (N0.getOpcode() == ISD::UNDEF) 2653 return N0; 2654 if (N1.getOpcode() == ISD::UNDEF) 2655 return N1; 2656 // fold (xor c1, c2) -> c1^c2 2657 if (N0C && N1C) 2658 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); 2659 // canonicalize constant to RHS 2660 if (N0C && !N1C) 2661 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 2662 // fold (xor x, 0) -> x 2663 if (N1C && N1C->isNullValue()) 2664 return N0; 2665 // reassociate xor 2666 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1); 2667 if (RXOR.getNode() != 0) 2668 return RXOR; 2669 2670 // fold !(x cc y) -> (x !cc y) 2671 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 2672 bool isInt = LHS.getValueType().isInteger(); 2673 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 2674 isInt); 2675 2676 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) { 2677 switch (N0.getOpcode()) { 2678 default: 2679 llvm_unreachable("Unhandled SetCC Equivalent!"); 2680 case ISD::SETCC: 2681 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC); 2682 case ISD::SELECT_CC: 2683 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2), 2684 N0.getOperand(3), NotCC); 2685 } 2686 } 2687 } 2688 2689 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 2690 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 2691 N0.getNode()->hasOneUse() && 2692 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 2693 SDValue V = N0.getOperand(0); 2694 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V, 2695 DAG.getConstant(1, V.getValueType())); 2696 AddToWorkList(V.getNode()); 2697 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V); 2698 } 2699 2700 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc 2701 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 2702 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2703 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2704 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 2705 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2706 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2707 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2708 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2709 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2710 } 2711 } 2712 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants 2713 if (N1C && N1C->isAllOnesValue() && 2714 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2715 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2716 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 2717 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2718 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2719 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2720 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2721 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2722 } 2723 } 2724 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2)) 2725 if (N1C && N0.getOpcode() == ISD::XOR) { 2726 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 2727 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2728 if (N00C) 2729 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1), 2730 DAG.getConstant(N1C->getAPIntValue() ^ 2731 N00C->getAPIntValue(), VT)); 2732 if (N01C) 2733 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0), 2734 DAG.getConstant(N1C->getAPIntValue() ^ 2735 N01C->getAPIntValue(), VT)); 2736 } 2737 // fold (xor x, x) -> 0 2738 if (N0 == N1) { 2739 if (!VT.isVector()) { 2740 return DAG.getConstant(0, VT); 2741 } else if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)){ 2742 // Produce a vector of zeros. 2743 SDValue El = DAG.getConstant(0, VT.getVectorElementType()); 2744 std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 2745 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 2746 &Ops[0], Ops.size()); 2747 } 2748 } 2749 2750 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 2751 if (N0.getOpcode() == N1.getOpcode()) { 2752 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2753 if (Tmp.getNode()) return Tmp; 2754 } 2755 2756 // Simplify the expression using non-local knowledge. 2757 if (!VT.isVector() && 2758 SimplifyDemandedBits(SDValue(N, 0))) 2759 return SDValue(N, 0); 2760 2761 return SDValue(); 2762} 2763 2764/// visitShiftByConstant - Handle transforms common to the three shifts, when 2765/// the shift amount is a constant. 2766SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 2767 SDNode *LHS = N->getOperand(0).getNode(); 2768 if (!LHS->hasOneUse()) return SDValue(); 2769 2770 // We want to pull some binops through shifts, so that we have (and (shift)) 2771 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 2772 // thing happens with address calculations, so it's important to canonicalize 2773 // it. 2774 bool HighBitSet = false; // Can we transform this if the high bit is set? 2775 2776 switch (LHS->getOpcode()) { 2777 default: return SDValue(); 2778 case ISD::OR: 2779 case ISD::XOR: 2780 HighBitSet = false; // We can only transform sra if the high bit is clear. 2781 break; 2782 case ISD::AND: 2783 HighBitSet = true; // We can only transform sra if the high bit is set. 2784 break; 2785 case ISD::ADD: 2786 if (N->getOpcode() != ISD::SHL) 2787 return SDValue(); // only shl(add) not sr[al](add). 2788 HighBitSet = false; // We can only transform sra if the high bit is clear. 2789 break; 2790 } 2791 2792 // We require the RHS of the binop to be a constant as well. 2793 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 2794 if (!BinOpCst) return SDValue(); 2795 2796 // FIXME: disable this unless the input to the binop is a shift by a constant. 2797 // If it is not a shift, it pessimizes some common cases like: 2798 // 2799 // void foo(int *X, int i) { X[i & 1235] = 1; } 2800 // int bar(int *X, int i) { return X[i & 255]; } 2801 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); 2802 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 2803 BinOpLHSVal->getOpcode() != ISD::SRA && 2804 BinOpLHSVal->getOpcode() != ISD::SRL) || 2805 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 2806 return SDValue(); 2807 2808 EVT VT = N->getValueType(0); 2809 2810 // If this is a signed shift right, and the high bit is modified by the 2811 // logical operation, do not perform the transformation. The highBitSet 2812 // boolean indicates the value of the high bit of the constant which would 2813 // cause it to be modified for this operation. 2814 if (N->getOpcode() == ISD::SRA) { 2815 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 2816 if (BinOpRHSSignSet != HighBitSet) 2817 return SDValue(); 2818 } 2819 2820 // Fold the constants, shifting the binop RHS by the shift amount. 2821 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(), 2822 N->getValueType(0), 2823 LHS->getOperand(1), N->getOperand(1)); 2824 2825 // Create the new shift. 2826 SDValue NewShift = DAG.getNode(N->getOpcode(), LHS->getOperand(0).getDebugLoc(), 2827 VT, LHS->getOperand(0), N->getOperand(1)); 2828 2829 // Create the new binop. 2830 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS); 2831} 2832 2833SDValue DAGCombiner::visitSHL(SDNode *N) { 2834 SDValue N0 = N->getOperand(0); 2835 SDValue N1 = N->getOperand(1); 2836 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2837 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2838 EVT VT = N0.getValueType(); 2839 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 2840 2841 // fold (shl c1, c2) -> c1<<c2 2842 if (N0C && N1C) 2843 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C); 2844 // fold (shl 0, x) -> 0 2845 if (N0C && N0C->isNullValue()) 2846 return N0; 2847 // fold (shl x, c >= size(x)) -> undef 2848 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2849 return DAG.getUNDEF(VT); 2850 // fold (shl x, 0) -> x 2851 if (N1C && N1C->isNullValue()) 2852 return N0; 2853 // if (shl x, c) is known to be zero, return 0 2854 if (DAG.MaskedValueIsZero(SDValue(N, 0), 2855 APInt::getAllOnesValue(OpSizeInBits))) 2856 return DAG.getConstant(0, VT); 2857 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))). 2858 if (N1.getOpcode() == ISD::TRUNCATE && 2859 N1.getOperand(0).getOpcode() == ISD::AND && 2860 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2861 SDValue N101 = N1.getOperand(0).getOperand(1); 2862 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2863 EVT TruncVT = N1.getValueType(); 2864 SDValue N100 = N1.getOperand(0).getOperand(0); 2865 APInt TruncC = N101C->getAPIntValue(); 2866 TruncC.trunc(TruncVT.getSizeInBits()); 2867 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 2868 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT, 2869 DAG.getNode(ISD::TRUNCATE, 2870 N->getDebugLoc(), 2871 TruncVT, N100), 2872 DAG.getConstant(TruncC, TruncVT))); 2873 } 2874 } 2875 2876 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2877 return SDValue(N, 0); 2878 2879 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2)) 2880 if (N1C && N0.getOpcode() == ISD::SHL && 2881 N0.getOperand(1).getOpcode() == ISD::Constant) { 2882 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2883 uint64_t c2 = N1C->getZExtValue(); 2884 if (c1 + c2 > OpSizeInBits) 2885 return DAG.getConstant(0, VT); 2886 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 2887 DAG.getConstant(c1 + c2, N1.getValueType())); 2888 } 2889 // fold (shl (srl x, c1), c2) -> (shl (and x, (shl -1, c1)), (sub c2, c1)) or 2890 // (srl (and x, (shl -1, c1)), (sub c1, c2)) 2891 if (N1C && N0.getOpcode() == ISD::SRL && 2892 N0.getOperand(1).getOpcode() == ISD::Constant) { 2893 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2894 if (c1 < VT.getSizeInBits()) { 2895 uint64_t c2 = N1C->getZExtValue(); 2896 SDValue HiBitsMask = 2897 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 2898 VT.getSizeInBits() - c1), 2899 VT); 2900 SDValue Mask = DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, 2901 N0.getOperand(0), 2902 HiBitsMask); 2903 if (c2 > c1) 2904 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, Mask, 2905 DAG.getConstant(c2-c1, N1.getValueType())); 2906 else 2907 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Mask, 2908 DAG.getConstant(c1-c2, N1.getValueType())); 2909 } 2910 } 2911 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1)) 2912 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) { 2913 SDValue HiBitsMask = 2914 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 2915 VT.getSizeInBits() - 2916 N1C->getZExtValue()), 2917 VT); 2918 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 2919 HiBitsMask); 2920 } 2921 2922 if (N1C) { 2923 SDValue NewSHL = visitShiftByConstant(N, N1C->getZExtValue()); 2924 if (NewSHL.getNode()) 2925 return NewSHL; 2926 } 2927 2928 return SDValue(); 2929} 2930 2931SDValue DAGCombiner::visitSRA(SDNode *N) { 2932 SDValue N0 = N->getOperand(0); 2933 SDValue N1 = N->getOperand(1); 2934 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2935 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2936 EVT VT = N0.getValueType(); 2937 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 2938 2939 // fold (sra c1, c2) -> (sra c1, c2) 2940 if (N0C && N1C) 2941 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); 2942 // fold (sra 0, x) -> 0 2943 if (N0C && N0C->isNullValue()) 2944 return N0; 2945 // fold (sra -1, x) -> -1 2946 if (N0C && N0C->isAllOnesValue()) 2947 return N0; 2948 // fold (sra x, (setge c, size(x))) -> undef 2949 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2950 return DAG.getUNDEF(VT); 2951 // fold (sra x, 0) -> x 2952 if (N1C && N1C->isNullValue()) 2953 return N0; 2954 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 2955 // sext_inreg. 2956 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 2957 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue(); 2958 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits); 2959 if (VT.isVector()) 2960 ExtVT = EVT::getVectorVT(*DAG.getContext(), 2961 ExtVT, VT.getVectorNumElements()); 2962 if ((!LegalOperations || 2963 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT))) 2964 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 2965 N0.getOperand(0), DAG.getValueType(ExtVT)); 2966 } 2967 2968 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) 2969 if (N1C && N0.getOpcode() == ISD::SRA) { 2970 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2971 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); 2972 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1; 2973 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0), 2974 DAG.getConstant(Sum, N1C->getValueType(0))); 2975 } 2976 } 2977 2978 // fold (sra (shl X, m), (sub result_size, n)) 2979 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for 2980 // result_size - n != m. 2981 // If truncate is free for the target sext(shl) is likely to result in better 2982 // code. 2983 if (N0.getOpcode() == ISD::SHL) { 2984 // Get the two constanst of the shifts, CN0 = m, CN = n. 2985 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2986 if (N01C && N1C) { 2987 // Determine what the truncate's result bitsize and type would be. 2988 EVT TruncVT = 2989 EVT::getIntegerVT(*DAG.getContext(), OpSizeInBits - N1C->getZExtValue()); 2990 // Determine the residual right-shift amount. 2991 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); 2992 2993 // If the shift is not a no-op (in which case this should be just a sign 2994 // extend already), the truncated to type is legal, sign_extend is legal 2995 // on that type, and the truncate to that type is both legal and free, 2996 // perform the transform. 2997 if ((ShiftAmt > 0) && 2998 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) && 2999 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) && 3000 TLI.isTruncateFree(VT, TruncVT)) { 3001 3002 SDValue Amt = DAG.getConstant(ShiftAmt, getShiftAmountTy()); 3003 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, 3004 N0.getOperand(0), Amt); 3005 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT, 3006 Shift); 3007 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), 3008 N->getValueType(0), Trunc); 3009 } 3010 } 3011 } 3012 3013 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))). 3014 if (N1.getOpcode() == ISD::TRUNCATE && 3015 N1.getOperand(0).getOpcode() == ISD::AND && 3016 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3017 SDValue N101 = N1.getOperand(0).getOperand(1); 3018 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3019 EVT TruncVT = N1.getValueType(); 3020 SDValue N100 = N1.getOperand(0).getOperand(0); 3021 APInt TruncC = N101C->getAPIntValue(); 3022 TruncC.trunc(TruncVT.getScalarType().getSizeInBits()); 3023 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 3024 DAG.getNode(ISD::AND, N->getDebugLoc(), 3025 TruncVT, 3026 DAG.getNode(ISD::TRUNCATE, 3027 N->getDebugLoc(), 3028 TruncVT, N100), 3029 DAG.getConstant(TruncC, TruncVT))); 3030 } 3031 } 3032 3033 // Simplify, based on bits shifted out of the LHS. 3034 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3035 return SDValue(N, 0); 3036 3037 3038 // If the sign bit is known to be zero, switch this to a SRL. 3039 if (DAG.SignBitIsZero(N0)) 3040 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1); 3041 3042 if (N1C) { 3043 SDValue NewSRA = visitShiftByConstant(N, N1C->getZExtValue()); 3044 if (NewSRA.getNode()) 3045 return NewSRA; 3046 } 3047 3048 return SDValue(); 3049} 3050 3051SDValue DAGCombiner::visitSRL(SDNode *N) { 3052 SDValue N0 = N->getOperand(0); 3053 SDValue N1 = N->getOperand(1); 3054 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3055 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3056 EVT VT = N0.getValueType(); 3057 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3058 3059 // fold (srl c1, c2) -> c1 >>u c2 3060 if (N0C && N1C) 3061 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); 3062 // fold (srl 0, x) -> 0 3063 if (N0C && N0C->isNullValue()) 3064 return N0; 3065 // fold (srl x, c >= size(x)) -> undef 3066 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3067 return DAG.getUNDEF(VT); 3068 // fold (srl x, 0) -> x 3069 if (N1C && N1C->isNullValue()) 3070 return N0; 3071 // if (srl x, c) is known to be zero, return 0 3072 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 3073 APInt::getAllOnesValue(OpSizeInBits))) 3074 return DAG.getConstant(0, VT); 3075 3076 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2)) 3077 if (N1C && N0.getOpcode() == ISD::SRL && 3078 N0.getOperand(1).getOpcode() == ISD::Constant) { 3079 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3080 uint64_t c2 = N1C->getZExtValue(); 3081 if (c1 + c2 > OpSizeInBits) 3082 return DAG.getConstant(0, VT); 3083 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 3084 DAG.getConstant(c1 + c2, N1.getValueType())); 3085 } 3086 3087 // fold (srl (shl x, c), c) -> (and x, cst2) 3088 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 && 3089 N0.getValueSizeInBits() <= 64) { 3090 uint64_t ShAmt = N1C->getZExtValue()+64-N0.getValueSizeInBits(); 3091 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 3092 DAG.getConstant(~0ULL >> ShAmt, VT)); 3093 } 3094 3095 3096 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 3097 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 3098 // Shifting in all undef bits? 3099 EVT SmallVT = N0.getOperand(0).getValueType(); 3100 if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) 3101 return DAG.getUNDEF(VT); 3102 3103 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) { 3104 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT, 3105 N0.getOperand(0), N1); 3106 AddToWorkList(SmallShift.getNode()); 3107 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift); 3108 } 3109 } 3110 3111 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 3112 // bit, which is unmodified by sra. 3113 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) { 3114 if (N0.getOpcode() == ISD::SRA) 3115 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1); 3116 } 3117 3118 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 3119 if (N1C && N0.getOpcode() == ISD::CTLZ && 3120 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 3121 APInt KnownZero, KnownOne; 3122 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 3123 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 3124 3125 // If any of the input bits are KnownOne, then the input couldn't be all 3126 // zeros, thus the result of the srl will always be zero. 3127 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 3128 3129 // If all of the bits input the to ctlz node are known to be zero, then 3130 // the result of the ctlz is "32" and the result of the shift is one. 3131 APInt UnknownBits = ~KnownZero & Mask; 3132 if (UnknownBits == 0) return DAG.getConstant(1, VT); 3133 3134 // Otherwise, check to see if there is exactly one bit input to the ctlz. 3135 if ((UnknownBits & (UnknownBits - 1)) == 0) { 3136 // Okay, we know that only that the single bit specified by UnknownBits 3137 // could be set on input to the CTLZ node. If this bit is set, the SRL 3138 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 3139 // to an SRL/XOR pair, which is likely to simplify more. 3140 unsigned ShAmt = UnknownBits.countTrailingZeros(); 3141 SDValue Op = N0.getOperand(0); 3142 3143 if (ShAmt) { 3144 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op, 3145 DAG.getConstant(ShAmt, getShiftAmountTy())); 3146 AddToWorkList(Op.getNode()); 3147 } 3148 3149 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 3150 Op, DAG.getConstant(1, VT)); 3151 } 3152 } 3153 3154 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))). 3155 if (N1.getOpcode() == ISD::TRUNCATE && 3156 N1.getOperand(0).getOpcode() == ISD::AND && 3157 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3158 SDValue N101 = N1.getOperand(0).getOperand(1); 3159 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3160 EVT TruncVT = N1.getValueType(); 3161 SDValue N100 = N1.getOperand(0).getOperand(0); 3162 APInt TruncC = N101C->getAPIntValue(); 3163 TruncC.trunc(TruncVT.getSizeInBits()); 3164 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 3165 DAG.getNode(ISD::AND, N->getDebugLoc(), 3166 TruncVT, 3167 DAG.getNode(ISD::TRUNCATE, 3168 N->getDebugLoc(), 3169 TruncVT, N100), 3170 DAG.getConstant(TruncC, TruncVT))); 3171 } 3172 } 3173 3174 // fold operands of srl based on knowledge that the low bits are not 3175 // demanded. 3176 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3177 return SDValue(N, 0); 3178 3179 if (N1C) { 3180 SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue()); 3181 if (NewSRL.getNode()) 3182 return NewSRL; 3183 } 3184 3185 // Attempt to convert a srl of a load into a narrower zero-extending load. 3186 SDValue NarrowLoad = ReduceLoadWidth(N); 3187 if (NarrowLoad.getNode()) 3188 return NarrowLoad; 3189 3190 // Here is a common situation. We want to optimize: 3191 // 3192 // %a = ... 3193 // %b = and i32 %a, 2 3194 // %c = srl i32 %b, 1 3195 // brcond i32 %c ... 3196 // 3197 // into 3198 // 3199 // %a = ... 3200 // %b = and %a, 2 3201 // %c = setcc eq %b, 0 3202 // brcond %c ... 3203 // 3204 // However when after the source operand of SRL is optimized into AND, the SRL 3205 // itself may not be optimized further. Look for it and add the BRCOND into 3206 // the worklist. 3207 if (N->hasOneUse()) { 3208 SDNode *Use = *N->use_begin(); 3209 if (Use->getOpcode() == ISD::BRCOND) 3210 AddToWorkList(Use); 3211 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) { 3212 // Also look pass the truncate. 3213 Use = *Use->use_begin(); 3214 if (Use->getOpcode() == ISD::BRCOND) 3215 AddToWorkList(Use); 3216 } 3217 } 3218 3219 return SDValue(); 3220} 3221 3222SDValue DAGCombiner::visitCTLZ(SDNode *N) { 3223 SDValue N0 = N->getOperand(0); 3224 EVT VT = N->getValueType(0); 3225 3226 // fold (ctlz c1) -> c2 3227 if (isa<ConstantSDNode>(N0)) 3228 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0); 3229 return SDValue(); 3230} 3231 3232SDValue DAGCombiner::visitCTTZ(SDNode *N) { 3233 SDValue N0 = N->getOperand(0); 3234 EVT VT = N->getValueType(0); 3235 3236 // fold (cttz c1) -> c2 3237 if (isa<ConstantSDNode>(N0)) 3238 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0); 3239 return SDValue(); 3240} 3241 3242SDValue DAGCombiner::visitCTPOP(SDNode *N) { 3243 SDValue N0 = N->getOperand(0); 3244 EVT VT = N->getValueType(0); 3245 3246 // fold (ctpop c1) -> c2 3247 if (isa<ConstantSDNode>(N0)) 3248 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0); 3249 return SDValue(); 3250} 3251 3252SDValue DAGCombiner::visitSELECT(SDNode *N) { 3253 SDValue N0 = N->getOperand(0); 3254 SDValue N1 = N->getOperand(1); 3255 SDValue N2 = N->getOperand(2); 3256 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3257 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3258 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 3259 EVT VT = N->getValueType(0); 3260 EVT VT0 = N0.getValueType(); 3261 3262 // fold (select C, X, X) -> X 3263 if (N1 == N2) 3264 return N1; 3265 // fold (select true, X, Y) -> X 3266 if (N0C && !N0C->isNullValue()) 3267 return N1; 3268 // fold (select false, X, Y) -> Y 3269 if (N0C && N0C->isNullValue()) 3270 return N2; 3271 // fold (select C, 1, X) -> (or C, X) 3272 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 3273 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 3274 // fold (select C, 0, 1) -> (xor C, 1) 3275 if (VT.isInteger() && 3276 (VT0 == MVT::i1 || 3277 (VT0.isInteger() && 3278 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) && 3279 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 3280 SDValue XORNode; 3281 if (VT == VT0) 3282 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0, 3283 N0, DAG.getConstant(1, VT0)); 3284 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0, 3285 N0, DAG.getConstant(1, VT0)); 3286 AddToWorkList(XORNode.getNode()); 3287 if (VT.bitsGT(VT0)) 3288 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode); 3289 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode); 3290 } 3291 // fold (select C, 0, X) -> (and (not C), X) 3292 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 3293 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 3294 AddToWorkList(NOTNode.getNode()); 3295 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2); 3296 } 3297 // fold (select C, X, 1) -> (or (not C), X) 3298 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 3299 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 3300 AddToWorkList(NOTNode.getNode()); 3301 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1); 3302 } 3303 // fold (select C, X, 0) -> (and C, X) 3304 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 3305 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 3306 // fold (select X, X, Y) -> (or X, Y) 3307 // fold (select X, 1, Y) -> (or X, Y) 3308 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1))) 3309 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 3310 // fold (select X, Y, X) -> (and X, Y) 3311 // fold (select X, Y, 0) -> (and X, Y) 3312 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0))) 3313 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 3314 3315 // If we can fold this based on the true/false value, do so. 3316 if (SimplifySelectOps(N, N1, N2)) 3317 return SDValue(N, 0); // Don't revisit N. 3318 3319 // fold selects based on a setcc into other things, such as min/max/abs 3320 if (N0.getOpcode() == ISD::SETCC) { 3321 // FIXME: 3322 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 3323 // having to say they don't support SELECT_CC on every type the DAG knows 3324 // about, since there is no way to mark an opcode illegal at all value types 3325 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) && 3326 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT)) 3327 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, 3328 N0.getOperand(0), N0.getOperand(1), 3329 N1, N2, N0.getOperand(2)); 3330 return SimplifySelect(N->getDebugLoc(), N0, N1, N2); 3331 } 3332 3333 return SDValue(); 3334} 3335 3336SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 3337 SDValue N0 = N->getOperand(0); 3338 SDValue N1 = N->getOperand(1); 3339 SDValue N2 = N->getOperand(2); 3340 SDValue N3 = N->getOperand(3); 3341 SDValue N4 = N->getOperand(4); 3342 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 3343 3344 // fold select_cc lhs, rhs, x, x, cc -> x 3345 if (N2 == N3) 3346 return N2; 3347 3348 // Determine if the condition we're dealing with is constant 3349 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 3350 N0, N1, CC, N->getDebugLoc(), false); 3351 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 3352 3353 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) { 3354 if (!SCCC->isNullValue()) 3355 return N2; // cond always true -> true val 3356 else 3357 return N3; // cond always false -> false val 3358 } 3359 3360 // Fold to a simpler select_cc 3361 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) 3362 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(), 3363 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 3364 SCC.getOperand(2)); 3365 3366 // If we can fold this based on the true/false value, do so. 3367 if (SimplifySelectOps(N, N2, N3)) 3368 return SDValue(N, 0); // Don't revisit N. 3369 3370 // fold select_cc into other things, such as min/max/abs 3371 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC); 3372} 3373 3374SDValue DAGCombiner::visitSETCC(SDNode *N) { 3375 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 3376 cast<CondCodeSDNode>(N->getOperand(2))->get(), 3377 N->getDebugLoc()); 3378} 3379 3380// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 3381// "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))" 3382// transformation. Returns true if extension are possible and the above 3383// mentioned transformation is profitable. 3384static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 3385 unsigned ExtOpc, 3386 SmallVector<SDNode*, 4> &ExtendNodes, 3387 const TargetLowering &TLI) { 3388 bool HasCopyToRegUses = false; 3389 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 3390 for (SDNode::use_iterator UI = N0.getNode()->use_begin(), 3391 UE = N0.getNode()->use_end(); 3392 UI != UE; ++UI) { 3393 SDNode *User = *UI; 3394 if (User == N) 3395 continue; 3396 if (UI.getUse().getResNo() != N0.getResNo()) 3397 continue; 3398 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 3399 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { 3400 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 3401 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 3402 // Sign bits will be lost after a zext. 3403 return false; 3404 bool Add = false; 3405 for (unsigned i = 0; i != 2; ++i) { 3406 SDValue UseOp = User->getOperand(i); 3407 if (UseOp == N0) 3408 continue; 3409 if (!isa<ConstantSDNode>(UseOp)) 3410 return false; 3411 Add = true; 3412 } 3413 if (Add) 3414 ExtendNodes.push_back(User); 3415 continue; 3416 } 3417 // If truncates aren't free and there are users we can't 3418 // extend, it isn't worthwhile. 3419 if (!isTruncFree) 3420 return false; 3421 // Remember if this value is live-out. 3422 if (User->getOpcode() == ISD::CopyToReg) 3423 HasCopyToRegUses = true; 3424 } 3425 3426 if (HasCopyToRegUses) { 3427 bool BothLiveOut = false; 3428 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 3429 UI != UE; ++UI) { 3430 SDUse &Use = UI.getUse(); 3431 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) { 3432 BothLiveOut = true; 3433 break; 3434 } 3435 } 3436 if (BothLiveOut) 3437 // Both unextended and extended values are live out. There had better be 3438 // good a reason for the transformation. 3439 return ExtendNodes.size(); 3440 } 3441 return true; 3442} 3443 3444SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 3445 SDValue N0 = N->getOperand(0); 3446 EVT VT = N->getValueType(0); 3447 3448 // fold (sext c1) -> c1 3449 if (isa<ConstantSDNode>(N0)) 3450 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0); 3451 3452 // fold (sext (sext x)) -> (sext x) 3453 // fold (sext (aext x)) -> (sext x) 3454 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 3455 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, 3456 N0.getOperand(0)); 3457 3458 if (N0.getOpcode() == ISD::TRUNCATE) { 3459 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 3460 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 3461 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3462 if (NarrowLoad.getNode()) { 3463 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 3464 if (NarrowLoad.getNode() != N0.getNode()) { 3465 CombineTo(N0.getNode(), NarrowLoad); 3466 // CombineTo deleted the truncate, if needed, but not what's under it. 3467 AddToWorkList(oye); 3468 } 3469 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3470 } 3471 3472 // See if the value being truncated is already sign extended. If so, just 3473 // eliminate the trunc/sext pair. 3474 SDValue Op = N0.getOperand(0); 3475 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits(); 3476 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits(); 3477 unsigned DestBits = VT.getScalarType().getSizeInBits(); 3478 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 3479 3480 if (OpBits == DestBits) { 3481 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 3482 // bits, it is already ready. 3483 if (NumSignBits > DestBits-MidBits) 3484 return Op; 3485 } else if (OpBits < DestBits) { 3486 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 3487 // bits, just sext from i32. 3488 if (NumSignBits > OpBits-MidBits) 3489 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op); 3490 } else { 3491 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 3492 // bits, just truncate to i32. 3493 if (NumSignBits > OpBits-MidBits) 3494 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 3495 } 3496 3497 // fold (sext (truncate x)) -> (sextinreg x). 3498 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 3499 N0.getValueType())) { 3500 if (OpBits < DestBits) 3501 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op); 3502 else if (OpBits > DestBits) 3503 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op); 3504 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op, 3505 DAG.getValueType(N0.getValueType())); 3506 } 3507 } 3508 3509 // fold (sext (load x)) -> (sext (truncate (sextload x))) 3510 if (ISD::isNON_EXTLoad(N0.getNode()) && 3511 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3512 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { 3513 bool DoXform = true; 3514 SmallVector<SDNode*, 4> SetCCs; 3515 if (!N0.hasOneUse()) 3516 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 3517 if (DoXform) { 3518 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3519 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N->getDebugLoc(), 3520 LN0->getChain(), 3521 LN0->getBasePtr(), LN0->getPointerInfo(), 3522 N0.getValueType(), 3523 LN0->isVolatile(), LN0->isNonTemporal(), 3524 LN0->getAlignment()); 3525 CombineTo(N, ExtLoad); 3526 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3527 N0.getValueType(), ExtLoad); 3528 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3529 3530 // Extend SetCC uses if necessary. 3531 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3532 SDNode *SetCC = SetCCs[i]; 3533 SmallVector<SDValue, 4> Ops; 3534 3535 for (unsigned j = 0; j != 2; ++j) { 3536 SDValue SOp = SetCC->getOperand(j); 3537 if (SOp == Trunc) 3538 Ops.push_back(ExtLoad); 3539 else 3540 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, 3541 N->getDebugLoc(), VT, SOp)); 3542 } 3543 3544 Ops.push_back(SetCC->getOperand(2)); 3545 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3546 SetCC->getValueType(0), 3547 &Ops[0], Ops.size())); 3548 } 3549 3550 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3551 } 3552 } 3553 3554 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 3555 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 3556 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3557 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3558 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3559 EVT MemVT = LN0->getMemoryVT(); 3560 if ((!LegalOperations && !LN0->isVolatile()) || 3561 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) { 3562 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N->getDebugLoc(), 3563 LN0->getChain(), 3564 LN0->getBasePtr(), LN0->getPointerInfo(), 3565 MemVT, 3566 LN0->isVolatile(), LN0->isNonTemporal(), 3567 LN0->getAlignment()); 3568 CombineTo(N, ExtLoad); 3569 CombineTo(N0.getNode(), 3570 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3571 N0.getValueType(), ExtLoad), 3572 ExtLoad.getValue(1)); 3573 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3574 } 3575 } 3576 3577 if (N0.getOpcode() == ISD::SETCC) { 3578 // sext(setcc) -> sext_in_reg(vsetcc) for vectors. 3579 // Only do this before legalize for now. 3580 if (VT.isVector() && !LegalOperations) { 3581 EVT N0VT = N0.getOperand(0).getValueType(); 3582 // We know that the # elements of the results is the same as the 3583 // # elements of the compare (and the # elements of the compare result 3584 // for that matter). Check to see that they are the same size. If so, 3585 // we know that the element size of the sext'd result matches the 3586 // element size of the compare operands. 3587 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 3588 return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 3589 N0.getOperand(1), 3590 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 3591 // If the desired elements are smaller or larger than the source 3592 // elements we can use a matching integer vector type and then 3593 // truncate/sign extend 3594 else { 3595 EVT MatchingElementType = 3596 EVT::getIntegerVT(*DAG.getContext(), 3597 N0VT.getScalarType().getSizeInBits()); 3598 EVT MatchingVectorType = 3599 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 3600 N0VT.getVectorNumElements()); 3601 SDValue VsetCC = 3602 DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 3603 N0.getOperand(1), 3604 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 3605 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); 3606 } 3607 } 3608 3609 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc) 3610 unsigned ElementWidth = VT.getScalarType().getSizeInBits(); 3611 SDValue NegOne = 3612 DAG.getConstant(APInt::getAllOnesValue(ElementWidth), VT); 3613 SDValue SCC = 3614 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3615 NegOne, DAG.getConstant(0, VT), 3616 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3617 if (SCC.getNode()) return SCC; 3618 if (!LegalOperations || 3619 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT))) 3620 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT, 3621 DAG.getSetCC(N->getDebugLoc(), 3622 TLI.getSetCCResultType(VT), 3623 N0.getOperand(0), N0.getOperand(1), 3624 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 3625 NegOne, DAG.getConstant(0, VT)); 3626 } 3627 3628 // fold (sext x) -> (zext x) if the sign bit is known zero. 3629 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 3630 DAG.SignBitIsZero(N0)) 3631 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3632 3633 return SDValue(); 3634} 3635 3636SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 3637 SDValue N0 = N->getOperand(0); 3638 EVT VT = N->getValueType(0); 3639 3640 // fold (zext c1) -> c1 3641 if (isa<ConstantSDNode>(N0)) 3642 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3643 // fold (zext (zext x)) -> (zext x) 3644 // fold (zext (aext x)) -> (zext x) 3645 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 3646 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, 3647 N0.getOperand(0)); 3648 3649 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 3650 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 3651 if (N0.getOpcode() == ISD::TRUNCATE) { 3652 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3653 if (NarrowLoad.getNode()) { 3654 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 3655 if (NarrowLoad.getNode() != N0.getNode()) { 3656 CombineTo(N0.getNode(), NarrowLoad); 3657 // CombineTo deleted the truncate, if needed, but not what's under it. 3658 AddToWorkList(oye); 3659 } 3660 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 3661 } 3662 } 3663 3664 // fold (zext (truncate x)) -> (and x, mask) 3665 if (N0.getOpcode() == ISD::TRUNCATE && 3666 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) { 3667 SDValue Op = N0.getOperand(0); 3668 if (Op.getValueType().bitsLT(VT)) { 3669 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op); 3670 } else if (Op.getValueType().bitsGT(VT)) { 3671 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 3672 } 3673 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), 3674 N0.getValueType().getScalarType()); 3675 } 3676 3677 // Fold (zext (and (trunc x), cst)) -> (and x, cst), 3678 // if either of the casts is not free. 3679 if (N0.getOpcode() == ISD::AND && 3680 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3681 N0.getOperand(1).getOpcode() == ISD::Constant && 3682 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 3683 N0.getValueType()) || 3684 !TLI.isZExtFree(N0.getValueType(), VT))) { 3685 SDValue X = N0.getOperand(0).getOperand(0); 3686 if (X.getValueType().bitsLT(VT)) { 3687 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X); 3688 } else if (X.getValueType().bitsGT(VT)) { 3689 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 3690 } 3691 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3692 Mask.zext(VT.getSizeInBits()); 3693 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3694 X, DAG.getConstant(Mask, VT)); 3695 } 3696 3697 // fold (zext (load x)) -> (zext (truncate (zextload x))) 3698 if (ISD::isNON_EXTLoad(N0.getNode()) && 3699 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3700 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 3701 bool DoXform = true; 3702 SmallVector<SDNode*, 4> SetCCs; 3703 if (!N0.hasOneUse()) 3704 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 3705 if (DoXform) { 3706 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3707 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N->getDebugLoc(), 3708 LN0->getChain(), 3709 LN0->getBasePtr(), LN0->getPointerInfo(), 3710 N0.getValueType(), 3711 LN0->isVolatile(), LN0->isNonTemporal(), 3712 LN0->getAlignment()); 3713 CombineTo(N, ExtLoad); 3714 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3715 N0.getValueType(), ExtLoad); 3716 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3717 3718 // Extend SetCC uses if necessary. 3719 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3720 SDNode *SetCC = SetCCs[i]; 3721 SmallVector<SDValue, 4> Ops; 3722 3723 for (unsigned j = 0; j != 2; ++j) { 3724 SDValue SOp = SetCC->getOperand(j); 3725 if (SOp == Trunc) 3726 Ops.push_back(ExtLoad); 3727 else 3728 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, 3729 N->getDebugLoc(), VT, SOp)); 3730 } 3731 3732 Ops.push_back(SetCC->getOperand(2)); 3733 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3734 SetCC->getValueType(0), 3735 &Ops[0], Ops.size())); 3736 } 3737 3738 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3739 } 3740 } 3741 3742 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 3743 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 3744 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3745 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3746 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3747 EVT MemVT = LN0->getMemoryVT(); 3748 if ((!LegalOperations && !LN0->isVolatile()) || 3749 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) { 3750 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N->getDebugLoc(), 3751 LN0->getChain(), 3752 LN0->getBasePtr(), LN0->getPointerInfo(), 3753 MemVT, 3754 LN0->isVolatile(), LN0->isNonTemporal(), 3755 LN0->getAlignment()); 3756 CombineTo(N, ExtLoad); 3757 CombineTo(N0.getNode(), 3758 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(), 3759 ExtLoad), 3760 ExtLoad.getValue(1)); 3761 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3762 } 3763 } 3764 3765 if (N0.getOpcode() == ISD::SETCC) { 3766 if (!LegalOperations && VT.isVector()) { 3767 // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors. 3768 // Only do this before legalize for now. 3769 EVT N0VT = N0.getOperand(0).getValueType(); 3770 EVT EltVT = VT.getVectorElementType(); 3771 SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(), 3772 DAG.getConstant(1, EltVT)); 3773 if (VT.getSizeInBits() == N0VT.getSizeInBits()) { 3774 // We know that the # elements of the results is the same as the 3775 // # elements of the compare (and the # elements of the compare result 3776 // for that matter). Check to see that they are the same size. If so, 3777 // we know that the element size of the sext'd result matches the 3778 // element size of the compare operands. 3779 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3780 DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 3781 N0.getOperand(1), 3782 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 3783 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 3784 &OneOps[0], OneOps.size())); 3785 } else { 3786 // If the desired elements are smaller or larger than the source 3787 // elements we can use a matching integer vector type and then 3788 // truncate/sign extend 3789 EVT MatchingElementType = 3790 EVT::getIntegerVT(*DAG.getContext(), 3791 N0VT.getScalarType().getSizeInBits()); 3792 EVT MatchingVectorType = 3793 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 3794 N0VT.getVectorNumElements()); 3795 SDValue VsetCC = 3796 DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 3797 N0.getOperand(1), 3798 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 3799 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3800 DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT), 3801 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 3802 &OneOps[0], OneOps.size())); 3803 } 3804 } 3805 3806 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3807 SDValue SCC = 3808 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3809 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3810 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3811 if (SCC.getNode()) return SCC; 3812 } 3813 3814 // (zext (shl (zext x), cst)) -> (shl (zext x), cst) 3815 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && 3816 isa<ConstantSDNode>(N0.getOperand(1)) && 3817 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && 3818 N0.hasOneUse()) { 3819 if (N0.getOpcode() == ISD::SHL) { 3820 // If the original shl may be shifting out bits, do not perform this 3821 // transformation. 3822 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3823 unsigned KnownZeroBits = N0.getOperand(0).getValueType().getSizeInBits() - 3824 N0.getOperand(0).getOperand(0).getValueType().getSizeInBits(); 3825 if (ShAmt > KnownZeroBits) 3826 return SDValue(); 3827 } 3828 DebugLoc dl = N->getDebugLoc(); 3829 return DAG.getNode(N0.getOpcode(), dl, VT, 3830 DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0.getOperand(0)), 3831 DAG.getNode(ISD::ZERO_EXTEND, dl, 3832 N0.getOperand(1).getValueType(), 3833 N0.getOperand(1))); 3834 } 3835 3836 return SDValue(); 3837} 3838 3839SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 3840 SDValue N0 = N->getOperand(0); 3841 EVT VT = N->getValueType(0); 3842 3843 // fold (aext c1) -> c1 3844 if (isa<ConstantSDNode>(N0)) 3845 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0); 3846 // fold (aext (aext x)) -> (aext x) 3847 // fold (aext (zext x)) -> (zext x) 3848 // fold (aext (sext x)) -> (sext x) 3849 if (N0.getOpcode() == ISD::ANY_EXTEND || 3850 N0.getOpcode() == ISD::ZERO_EXTEND || 3851 N0.getOpcode() == ISD::SIGN_EXTEND) 3852 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0)); 3853 3854 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 3855 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 3856 if (N0.getOpcode() == ISD::TRUNCATE) { 3857 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3858 if (NarrowLoad.getNode()) { 3859 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 3860 if (NarrowLoad.getNode() != N0.getNode()) { 3861 CombineTo(N0.getNode(), NarrowLoad); 3862 // CombineTo deleted the truncate, if needed, but not what's under it. 3863 AddToWorkList(oye); 3864 } 3865 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 3866 } 3867 } 3868 3869 // fold (aext (truncate x)) 3870 if (N0.getOpcode() == ISD::TRUNCATE) { 3871 SDValue TruncOp = N0.getOperand(0); 3872 if (TruncOp.getValueType() == VT) 3873 return TruncOp; // x iff x size == zext size. 3874 if (TruncOp.getValueType().bitsGT(VT)) 3875 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp); 3876 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp); 3877 } 3878 3879 // Fold (aext (and (trunc x), cst)) -> (and x, cst) 3880 // if the trunc is not free. 3881 if (N0.getOpcode() == ISD::AND && 3882 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3883 N0.getOperand(1).getOpcode() == ISD::Constant && 3884 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 3885 N0.getValueType())) { 3886 SDValue X = N0.getOperand(0).getOperand(0); 3887 if (X.getValueType().bitsLT(VT)) { 3888 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X); 3889 } else if (X.getValueType().bitsGT(VT)) { 3890 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X); 3891 } 3892 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3893 Mask.zext(VT.getSizeInBits()); 3894 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3895 X, DAG.getConstant(Mask, VT)); 3896 } 3897 3898 // fold (aext (load x)) -> (aext (truncate (extload x))) 3899 if (ISD::isNON_EXTLoad(N0.getNode()) && 3900 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3901 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 3902 bool DoXform = true; 3903 SmallVector<SDNode*, 4> SetCCs; 3904 if (!N0.hasOneUse()) 3905 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI); 3906 if (DoXform) { 3907 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3908 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, N->getDebugLoc(), 3909 LN0->getChain(), 3910 LN0->getBasePtr(), LN0->getPointerInfo(), 3911 N0.getValueType(), 3912 LN0->isVolatile(), LN0->isNonTemporal(), 3913 LN0->getAlignment()); 3914 CombineTo(N, ExtLoad); 3915 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3916 N0.getValueType(), ExtLoad); 3917 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3918 3919 // Extend SetCC uses if necessary. 3920 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3921 SDNode *SetCC = SetCCs[i]; 3922 SmallVector<SDValue, 4> Ops; 3923 3924 for (unsigned j = 0; j != 2; ++j) { 3925 SDValue SOp = SetCC->getOperand(j); 3926 if (SOp == Trunc) 3927 Ops.push_back(ExtLoad); 3928 else 3929 Ops.push_back(DAG.getNode(ISD::ANY_EXTEND, 3930 N->getDebugLoc(), VT, SOp)); 3931 } 3932 3933 Ops.push_back(SetCC->getOperand(2)); 3934 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3935 SetCC->getValueType(0), 3936 &Ops[0], Ops.size())); 3937 } 3938 3939 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3940 } 3941 } 3942 3943 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 3944 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 3945 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 3946 if (N0.getOpcode() == ISD::LOAD && 3947 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3948 N0.hasOneUse()) { 3949 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3950 EVT MemVT = LN0->getMemoryVT(); 3951 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT, 3952 N->getDebugLoc(), 3953 LN0->getChain(), LN0->getBasePtr(), 3954 LN0->getPointerInfo(), MemVT, 3955 LN0->isVolatile(), LN0->isNonTemporal(), 3956 LN0->getAlignment()); 3957 CombineTo(N, ExtLoad); 3958 CombineTo(N0.getNode(), 3959 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3960 N0.getValueType(), ExtLoad), 3961 ExtLoad.getValue(1)); 3962 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3963 } 3964 3965 if (N0.getOpcode() == ISD::SETCC) { 3966 // aext(setcc) -> sext_in_reg(vsetcc) for vectors. 3967 // Only do this before legalize for now. 3968 if (VT.isVector() && !LegalOperations) { 3969 EVT N0VT = N0.getOperand(0).getValueType(); 3970 // We know that the # elements of the results is the same as the 3971 // # elements of the compare (and the # elements of the compare result 3972 // for that matter). Check to see that they are the same size. If so, 3973 // we know that the element size of the sext'd result matches the 3974 // element size of the compare operands. 3975 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 3976 return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 3977 N0.getOperand(1), 3978 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 3979 // If the desired elements are smaller or larger than the source 3980 // elements we can use a matching integer vector type and then 3981 // truncate/sign extend 3982 else { 3983 EVT MatchingElementType = 3984 EVT::getIntegerVT(*DAG.getContext(), 3985 N0VT.getScalarType().getSizeInBits()); 3986 EVT MatchingVectorType = 3987 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 3988 N0VT.getVectorNumElements()); 3989 SDValue VsetCC = 3990 DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 3991 N0.getOperand(1), 3992 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 3993 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); 3994 } 3995 } 3996 3997 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3998 SDValue SCC = 3999 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4000 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 4001 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4002 if (SCC.getNode()) 4003 return SCC; 4004 } 4005 4006 return SDValue(); 4007} 4008 4009/// GetDemandedBits - See if the specified operand can be simplified with the 4010/// knowledge that only the bits specified by Mask are used. If so, return the 4011/// simpler operand, otherwise return a null SDValue. 4012SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 4013 switch (V.getOpcode()) { 4014 default: break; 4015 case ISD::OR: 4016 case ISD::XOR: 4017 // If the LHS or RHS don't contribute bits to the or, drop them. 4018 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 4019 return V.getOperand(1); 4020 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 4021 return V.getOperand(0); 4022 break; 4023 case ISD::SRL: 4024 // Only look at single-use SRLs. 4025 if (!V.getNode()->hasOneUse()) 4026 break; 4027 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 4028 // See if we can recursively simplify the LHS. 4029 unsigned Amt = RHSC->getZExtValue(); 4030 4031 // Watch out for shift count overflow though. 4032 if (Amt >= Mask.getBitWidth()) break; 4033 APInt NewMask = Mask << Amt; 4034 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 4035 if (SimplifyLHS.getNode()) 4036 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(), 4037 SimplifyLHS, V.getOperand(1)); 4038 } 4039 } 4040 return SDValue(); 4041} 4042 4043/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 4044/// bits and then truncated to a narrower type and where N is a multiple 4045/// of number of bits of the narrower type, transform it to a narrower load 4046/// from address + N / num of bits of new type. If the result is to be 4047/// extended, also fold the extension to form a extending load. 4048SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 4049 unsigned Opc = N->getOpcode(); 4050 4051 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 4052 SDValue N0 = N->getOperand(0); 4053 EVT VT = N->getValueType(0); 4054 EVT ExtVT = VT; 4055 4056 // This transformation isn't valid for vector loads. 4057 if (VT.isVector()) 4058 return SDValue(); 4059 4060 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then 4061 // extended to VT. 4062 if (Opc == ISD::SIGN_EXTEND_INREG) { 4063 ExtType = ISD::SEXTLOAD; 4064 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 4065 if (LegalOperations && !TLI.isLoadExtLegal(ISD::SEXTLOAD, ExtVT)) 4066 return SDValue(); 4067 } else if (Opc == ISD::SRL) { 4068 // Annother special-case: SRL is basically zero-extending a narrower 4069 // value. 4070 ExtType = ISD::ZEXTLOAD; 4071 N0 = SDValue(N, 0); 4072 ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 4073 if (!N01) return SDValue(); 4074 ExtVT = EVT::getIntegerVT(*DAG.getContext(), 4075 VT.getSizeInBits() - N01->getZExtValue()); 4076 } 4077 4078 unsigned EVTBits = ExtVT.getSizeInBits(); 4079 unsigned ShAmt = 0; 4080 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse() && ExtVT.isRound()) { 4081 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 4082 ShAmt = N01->getZExtValue(); 4083 // Is the shift amount a multiple of size of VT? 4084 if ((ShAmt & (EVTBits-1)) == 0) { 4085 N0 = N0.getOperand(0); 4086 // Is the load width a multiple of size of VT? 4087 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0) 4088 return SDValue(); 4089 } 4090 4091 // If the shift amount is larger than the input type then we're not 4092 // accessing any of the loaded bytes. If the load was a zextload/extload 4093 // then the result of the shift+trunc is zero/undef (handled elsewhere). 4094 // If the load was a sextload then the result is a splat of the sign bit 4095 // of the extended byte. This is not worth optimizing for. 4096 if (ShAmt >= VT.getSizeInBits()) 4097 return SDValue(); 4098 4099 } 4100 } 4101 4102 // Do not generate loads of non-round integer types since these can 4103 // be expensive (and would be wrong if the type is not byte sized). 4104 if (isa<LoadSDNode>(N0) && N0.hasOneUse() && ExtVT.isRound() && 4105 cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() >= EVTBits && 4106 // Do not change the width of a volatile load. 4107 !cast<LoadSDNode>(N0)->isVolatile()) { 4108 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4109 EVT PtrType = N0.getOperand(1).getValueType(); 4110 4111 // For big endian targets, we need to adjust the offset to the pointer to 4112 // load the correct bytes. 4113 if (TLI.isBigEndian()) { 4114 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 4115 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits(); 4116 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 4117 } 4118 4119 uint64_t PtrOff = ShAmt / 8; 4120 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 4121 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), 4122 PtrType, LN0->getBasePtr(), 4123 DAG.getConstant(PtrOff, PtrType)); 4124 AddToWorkList(NewPtr.getNode()); 4125 4126 SDValue Load = (ExtType == ISD::NON_EXTLOAD) 4127 ? DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr, 4128 LN0->getPointerInfo().getWithOffset(PtrOff), 4129 LN0->isVolatile(), LN0->isNonTemporal(), NewAlign) 4130 : DAG.getExtLoad(ExtType, VT, N0.getDebugLoc(), LN0->getChain(), NewPtr, 4131 LN0->getPointerInfo().getWithOffset(PtrOff), 4132 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 4133 NewAlign); 4134 4135 // Replace the old load's chain with the new load's chain. 4136 WorkListRemover DeadNodes(*this); 4137 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), 4138 &DeadNodes); 4139 4140 // Return the new loaded value. 4141 return Load; 4142 } 4143 4144 return SDValue(); 4145} 4146 4147SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 4148 SDValue N0 = N->getOperand(0); 4149 SDValue N1 = N->getOperand(1); 4150 EVT VT = N->getValueType(0); 4151 EVT EVT = cast<VTSDNode>(N1)->getVT(); 4152 unsigned VTBits = VT.getScalarType().getSizeInBits(); 4153 unsigned EVTBits = EVT.getScalarType().getSizeInBits(); 4154 4155 // fold (sext_in_reg c1) -> c1 4156 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 4157 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1); 4158 4159 // If the input is already sign extended, just drop the extension. 4160 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1) 4161 return N0; 4162 4163 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 4164 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 4165 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 4166 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 4167 N0.getOperand(0), N1); 4168 } 4169 4170 // fold (sext_in_reg (sext x)) -> (sext x) 4171 // fold (sext_in_reg (aext x)) -> (sext x) 4172 // if x is small enough. 4173 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 4174 SDValue N00 = N0.getOperand(0); 4175 if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits && 4176 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT))) 4177 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1); 4178 } 4179 4180 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 4181 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 4182 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT); 4183 4184 // fold operands of sext_in_reg based on knowledge that the top bits are not 4185 // demanded. 4186 if (SimplifyDemandedBits(SDValue(N, 0))) 4187 return SDValue(N, 0); 4188 4189 // fold (sext_in_reg (load x)) -> (smaller sextload x) 4190 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 4191 SDValue NarrowLoad = ReduceLoadWidth(N); 4192 if (NarrowLoad.getNode()) 4193 return NarrowLoad; 4194 4195 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24) 4196 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible. 4197 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 4198 if (N0.getOpcode() == ISD::SRL) { 4199 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 4200 if (ShAmt->getZExtValue()+EVTBits <= VTBits) { 4201 // We can turn this into an SRA iff the input to the SRL is already sign 4202 // extended enough. 4203 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 4204 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits) 4205 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, 4206 N0.getOperand(0), N0.getOperand(1)); 4207 } 4208 } 4209 4210 // fold (sext_inreg (extload x)) -> (sextload x) 4211 if (ISD::isEXTLoad(N0.getNode()) && 4212 ISD::isUNINDEXEDLoad(N0.getNode()) && 4213 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 4214 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4215 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 4216 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4217 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N->getDebugLoc(), 4218 LN0->getChain(), 4219 LN0->getBasePtr(), LN0->getPointerInfo(), 4220 EVT, 4221 LN0->isVolatile(), LN0->isNonTemporal(), 4222 LN0->getAlignment()); 4223 CombineTo(N, ExtLoad); 4224 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 4225 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4226 } 4227 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 4228 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 4229 N0.hasOneUse() && 4230 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 4231 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4232 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 4233 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4234 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N->getDebugLoc(), 4235 LN0->getChain(), 4236 LN0->getBasePtr(), LN0->getPointerInfo(), 4237 EVT, 4238 LN0->isVolatile(), LN0->isNonTemporal(), 4239 LN0->getAlignment()); 4240 CombineTo(N, ExtLoad); 4241 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 4242 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4243 } 4244 return SDValue(); 4245} 4246 4247SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 4248 SDValue N0 = N->getOperand(0); 4249 EVT VT = N->getValueType(0); 4250 4251 // noop truncate 4252 if (N0.getValueType() == N->getValueType(0)) 4253 return N0; 4254 // fold (truncate c1) -> c1 4255 if (isa<ConstantSDNode>(N0)) 4256 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0); 4257 // fold (truncate (truncate x)) -> (truncate x) 4258 if (N0.getOpcode() == ISD::TRUNCATE) 4259 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 4260 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 4261 if (N0.getOpcode() == ISD::ZERO_EXTEND || 4262 N0.getOpcode() == ISD::SIGN_EXTEND || 4263 N0.getOpcode() == ISD::ANY_EXTEND) { 4264 if (N0.getOperand(0).getValueType().bitsLT(VT)) 4265 // if the source is smaller than the dest, we still need an extend 4266 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 4267 N0.getOperand(0)); 4268 else if (N0.getOperand(0).getValueType().bitsGT(VT)) 4269 // if the source is larger than the dest, than we just need the truncate 4270 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 4271 else 4272 // if the source and dest are the same type, we can drop both the extend 4273 // and the truncate. 4274 return N0.getOperand(0); 4275 } 4276 4277 // See if we can simplify the input to this truncate through knowledge that 4278 // only the low bits are being used. For example "trunc (or (shl x, 8), y)" 4279 // -> trunc y 4280 SDValue Shorter = 4281 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 4282 VT.getSizeInBits())); 4283 if (Shorter.getNode()) 4284 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter); 4285 4286 // fold (truncate (load x)) -> (smaller load x) 4287 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 4288 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) { 4289 SDValue Reduced = ReduceLoadWidth(N); 4290 if (Reduced.getNode()) 4291 return Reduced; 4292 } 4293 4294 // Simplify the operands using demanded-bits information. 4295 if (!VT.isVector() && 4296 SimplifyDemandedBits(SDValue(N, 0))) 4297 return SDValue(N, 0); 4298 4299 return SDValue(); 4300} 4301 4302static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 4303 SDValue Elt = N->getOperand(i); 4304 if (Elt.getOpcode() != ISD::MERGE_VALUES) 4305 return Elt.getNode(); 4306 return Elt.getOperand(Elt.getResNo()).getNode(); 4307} 4308 4309/// CombineConsecutiveLoads - build_pair (load, load) -> load 4310/// if load locations are consecutive. 4311SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) { 4312 assert(N->getOpcode() == ISD::BUILD_PAIR); 4313 4314 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0)); 4315 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1)); 4316 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse() || 4317 LD1->getPointerInfo().getAddrSpace() != 4318 LD2->getPointerInfo().getAddrSpace()) 4319 return SDValue(); 4320 EVT LD1VT = LD1->getValueType(0); 4321 4322 if (ISD::isNON_EXTLoad(LD2) && 4323 LD2->hasOneUse() && 4324 // If both are volatile this would reduce the number of volatile loads. 4325 // If one is volatile it might be ok, but play conservative and bail out. 4326 !LD1->isVolatile() && 4327 !LD2->isVolatile() && 4328 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) { 4329 unsigned Align = LD1->getAlignment(); 4330 unsigned NewAlign = TLI.getTargetData()-> 4331 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 4332 4333 if (NewAlign <= Align && 4334 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) 4335 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(), 4336 LD1->getBasePtr(), LD1->getPointerInfo(), 4337 false, false, Align); 4338 } 4339 4340 return SDValue(); 4341} 4342 4343SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) { 4344 SDValue N0 = N->getOperand(0); 4345 EVT VT = N->getValueType(0); 4346 4347 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 4348 // Only do this before legalize, since afterward the target may be depending 4349 // on the bitconvert. 4350 // First check to see if this is all constant. 4351 if (!LegalTypes && 4352 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 4353 VT.isVector()) { 4354 bool isSimple = true; 4355 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 4356 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 4357 N0.getOperand(i).getOpcode() != ISD::Constant && 4358 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 4359 isSimple = false; 4360 break; 4361 } 4362 4363 EVT DestEltVT = N->getValueType(0).getVectorElementType(); 4364 assert(!DestEltVT.isVector() && 4365 "Element type of vector ValueType must not be vector!"); 4366 if (isSimple) 4367 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.getNode(), DestEltVT); 4368 } 4369 4370 // If the input is a constant, let getNode fold it. 4371 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 4372 SDValue Res = DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, N0); 4373 if (Res.getNode() != N) { 4374 if (!LegalOperations || 4375 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT)) 4376 return Res; 4377 4378 // Folding it resulted in an illegal node, and it's too late to 4379 // do that. Clean up the old node and forego the transformation. 4380 // Ideally this won't happen very often, because instcombine 4381 // and the earlier dagcombine runs (where illegal nodes are 4382 // permitted) should have folded most of them already. 4383 DAG.DeleteNode(Res.getNode()); 4384 } 4385 } 4386 4387 // (conv (conv x, t1), t2) -> (conv x, t2) 4388 if (N0.getOpcode() == ISD::BIT_CONVERT) 4389 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, 4390 N0.getOperand(0)); 4391 4392 // fold (conv (load x)) -> (load (conv*)x) 4393 // If the resultant load doesn't need a higher alignment than the original! 4394 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 4395 // Do not change the width of a volatile load. 4396 !cast<LoadSDNode>(N0)->isVolatile() && 4397 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) { 4398 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4399 unsigned Align = TLI.getTargetData()-> 4400 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 4401 unsigned OrigAlign = LN0->getAlignment(); 4402 4403 if (Align <= OrigAlign) { 4404 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(), 4405 LN0->getBasePtr(), LN0->getPointerInfo(), 4406 LN0->isVolatile(), LN0->isNonTemporal(), 4407 OrigAlign); 4408 AddToWorkList(N); 4409 CombineTo(N0.getNode(), 4410 DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 4411 N0.getValueType(), Load), 4412 Load.getValue(1)); 4413 return Load; 4414 } 4415 } 4416 4417 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit) 4418 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit)) 4419 // This often reduces constant pool loads. 4420 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && 4421 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) { 4422 SDValue NewConv = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), VT, 4423 N0.getOperand(0)); 4424 AddToWorkList(NewConv.getNode()); 4425 4426 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 4427 if (N0.getOpcode() == ISD::FNEG) 4428 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 4429 NewConv, DAG.getConstant(SignBit, VT)); 4430 assert(N0.getOpcode() == ISD::FABS); 4431 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4432 NewConv, DAG.getConstant(~SignBit, VT)); 4433 } 4434 4435 // fold (bitconvert (fcopysign cst, x)) -> 4436 // (or (and (bitconvert x), sign), (and cst, (not sign))) 4437 // Note that we don't handle (copysign x, cst) because this can always be 4438 // folded to an fneg or fabs. 4439 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 4440 isa<ConstantFPSDNode>(N0.getOperand(0)) && 4441 VT.isInteger() && !VT.isVector()) { 4442 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 4443 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth); 4444 if (isTypeLegal(IntXVT)) { 4445 SDValue X = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 4446 IntXVT, N0.getOperand(1)); 4447 AddToWorkList(X.getNode()); 4448 4449 // If X has a different width than the result/lhs, sext it or truncate it. 4450 unsigned VTWidth = VT.getSizeInBits(); 4451 if (OrigXWidth < VTWidth) { 4452 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X); 4453 AddToWorkList(X.getNode()); 4454 } else if (OrigXWidth > VTWidth) { 4455 // To get the sign bit in the right place, we have to shift it right 4456 // before truncating. 4457 X = DAG.getNode(ISD::SRL, X.getDebugLoc(), 4458 X.getValueType(), X, 4459 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 4460 AddToWorkList(X.getNode()); 4461 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 4462 AddToWorkList(X.getNode()); 4463 } 4464 4465 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 4466 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT, 4467 X, DAG.getConstant(SignBit, VT)); 4468 AddToWorkList(X.getNode()); 4469 4470 SDValue Cst = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 4471 VT, N0.getOperand(0)); 4472 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT, 4473 Cst, DAG.getConstant(~SignBit, VT)); 4474 AddToWorkList(Cst.getNode()); 4475 4476 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst); 4477 } 4478 } 4479 4480 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 4481 if (N0.getOpcode() == ISD::BUILD_PAIR) { 4482 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT); 4483 if (CombineLD.getNode()) 4484 return CombineLD; 4485 } 4486 4487 return SDValue(); 4488} 4489 4490SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 4491 EVT VT = N->getValueType(0); 4492 return CombineConsecutiveLoads(N, VT); 4493} 4494 4495/// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector 4496/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 4497/// destination element value type. 4498SDValue DAGCombiner:: 4499ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) { 4500 EVT SrcEltVT = BV->getValueType(0).getVectorElementType(); 4501 4502 // If this is already the right type, we're done. 4503 if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 4504 4505 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 4506 unsigned DstBitSize = DstEltVT.getSizeInBits(); 4507 4508 // If this is a conversion of N elements of one type to N elements of another 4509 // type, convert each element. This handles FP<->INT cases. 4510 if (SrcBitSize == DstBitSize) { 4511 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 4512 BV->getValueType(0).getVectorNumElements()); 4513 4514 // Due to the FP element handling below calling this routine recursively, 4515 // we can end up with a scalar-to-vector node here. 4516 if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR) 4517 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 4518 DAG.getNode(ISD::BIT_CONVERT, BV->getDebugLoc(), 4519 DstEltVT, BV->getOperand(0))); 4520 4521 SmallVector<SDValue, 8> Ops; 4522 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 4523 SDValue Op = BV->getOperand(i); 4524 // If the vector element type is not legal, the BUILD_VECTOR operands 4525 // are promoted and implicitly truncated. Make that explicit here. 4526 if (Op.getValueType() != SrcEltVT) 4527 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op); 4528 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, BV->getDebugLoc(), 4529 DstEltVT, Op)); 4530 AddToWorkList(Ops.back().getNode()); 4531 } 4532 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 4533 &Ops[0], Ops.size()); 4534 } 4535 4536 // Otherwise, we're growing or shrinking the elements. To avoid having to 4537 // handle annoying details of growing/shrinking FP values, we convert them to 4538 // int first. 4539 if (SrcEltVT.isFloatingPoint()) { 4540 // Convert the input float vector to a int vector where the elements are the 4541 // same sizes. 4542 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 4543 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits()); 4544 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode(); 4545 SrcEltVT = IntVT; 4546 } 4547 4548 // Now we know the input is an integer vector. If the output is a FP type, 4549 // convert to integer first, then to FP of the right size. 4550 if (DstEltVT.isFloatingPoint()) { 4551 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 4552 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits()); 4553 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).getNode(); 4554 4555 // Next, convert to FP elements of the same size. 4556 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT); 4557 } 4558 4559 // Okay, we know the src/dst types are both integers of differing types. 4560 // Handling growing first. 4561 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 4562 if (SrcBitSize < DstBitSize) { 4563 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 4564 4565 SmallVector<SDValue, 8> Ops; 4566 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 4567 i += NumInputsPerOutput) { 4568 bool isLE = TLI.isLittleEndian(); 4569 APInt NewBits = APInt(DstBitSize, 0); 4570 bool EltIsUndef = true; 4571 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 4572 // Shift the previously computed bits over. 4573 NewBits <<= SrcBitSize; 4574 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 4575 if (Op.getOpcode() == ISD::UNDEF) continue; 4576 EltIsUndef = false; 4577 4578 NewBits |= APInt(cast<ConstantSDNode>(Op)->getAPIntValue()). 4579 zextOrTrunc(SrcBitSize).zext(DstBitSize); 4580 } 4581 4582 if (EltIsUndef) 4583 Ops.push_back(DAG.getUNDEF(DstEltVT)); 4584 else 4585 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 4586 } 4587 4588 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size()); 4589 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 4590 &Ops[0], Ops.size()); 4591 } 4592 4593 // Finally, this must be the case where we are shrinking elements: each input 4594 // turns into multiple outputs. 4595 bool isS2V = ISD::isScalarToVector(BV); 4596 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 4597 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 4598 NumOutputsPerInput*BV->getNumOperands()); 4599 SmallVector<SDValue, 8> Ops; 4600 4601 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 4602 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 4603 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 4604 Ops.push_back(DAG.getUNDEF(DstEltVT)); 4605 continue; 4606 } 4607 4608 APInt OpVal = APInt(cast<ConstantSDNode>(BV->getOperand(i))-> 4609 getAPIntValue()).zextOrTrunc(SrcBitSize); 4610 4611 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 4612 APInt ThisVal = APInt(OpVal).trunc(DstBitSize); 4613 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 4614 if (isS2V && i == 0 && j == 0 && APInt(ThisVal).zext(SrcBitSize) == OpVal) 4615 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 4616 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 4617 Ops[0]); 4618 OpVal = OpVal.lshr(DstBitSize); 4619 } 4620 4621 // For big endian targets, swap the order of the pieces of each element. 4622 if (TLI.isBigEndian()) 4623 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 4624 } 4625 4626 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 4627 &Ops[0], Ops.size()); 4628} 4629 4630SDValue DAGCombiner::visitFADD(SDNode *N) { 4631 SDValue N0 = N->getOperand(0); 4632 SDValue N1 = N->getOperand(1); 4633 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4634 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4635 EVT VT = N->getValueType(0); 4636 4637 // fold vector ops 4638 if (VT.isVector()) { 4639 SDValue FoldedVOp = SimplifyVBinOp(N); 4640 if (FoldedVOp.getNode()) return FoldedVOp; 4641 } 4642 4643 // fold (fadd c1, c2) -> (fadd c1, c2) 4644 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4645 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1); 4646 // canonicalize constant to RHS 4647 if (N0CFP && !N1CFP) 4648 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0); 4649 // fold (fadd A, 0) -> A 4650 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4651 return N0; 4652 // fold (fadd A, (fneg B)) -> (fsub A, B) 4653 if (isNegatibleForFree(N1, LegalOperations) == 2) 4654 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, 4655 GetNegatedExpression(N1, DAG, LegalOperations)); 4656 // fold (fadd (fneg A), B) -> (fsub B, A) 4657 if (isNegatibleForFree(N0, LegalOperations) == 2) 4658 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1, 4659 GetNegatedExpression(N0, DAG, LegalOperations)); 4660 4661 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 4662 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 4663 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 4664 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0), 4665 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 4666 N0.getOperand(1), N1)); 4667 4668 return SDValue(); 4669} 4670 4671SDValue DAGCombiner::visitFSUB(SDNode *N) { 4672 SDValue N0 = N->getOperand(0); 4673 SDValue N1 = N->getOperand(1); 4674 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4675 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4676 EVT VT = N->getValueType(0); 4677 4678 // fold vector ops 4679 if (VT.isVector()) { 4680 SDValue FoldedVOp = SimplifyVBinOp(N); 4681 if (FoldedVOp.getNode()) return FoldedVOp; 4682 } 4683 4684 // fold (fsub c1, c2) -> c1-c2 4685 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4686 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1); 4687 // fold (fsub A, 0) -> A 4688 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4689 return N0; 4690 // fold (fsub 0, B) -> -B 4691 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { 4692 if (isNegatibleForFree(N1, LegalOperations)) 4693 return GetNegatedExpression(N1, DAG, LegalOperations); 4694 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4695 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1); 4696 } 4697 // fold (fsub A, (fneg B)) -> (fadd A, B) 4698 if (isNegatibleForFree(N1, LegalOperations)) 4699 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, 4700 GetNegatedExpression(N1, DAG, LegalOperations)); 4701 4702 return SDValue(); 4703} 4704 4705SDValue DAGCombiner::visitFMUL(SDNode *N) { 4706 SDValue N0 = N->getOperand(0); 4707 SDValue N1 = N->getOperand(1); 4708 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4709 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4710 EVT VT = N->getValueType(0); 4711 4712 // fold vector ops 4713 if (VT.isVector()) { 4714 SDValue FoldedVOp = SimplifyVBinOp(N); 4715 if (FoldedVOp.getNode()) return FoldedVOp; 4716 } 4717 4718 // fold (fmul c1, c2) -> c1*c2 4719 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4720 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1); 4721 // canonicalize constant to RHS 4722 if (N0CFP && !N1CFP) 4723 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0); 4724 // fold (fmul A, 0) -> 0 4725 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4726 return N1; 4727 // fold (fmul A, 0) -> 0, vector edition. 4728 if (UnsafeFPMath && ISD::isBuildVectorAllZeros(N1.getNode())) 4729 return N1; 4730 // fold (fmul X, 2.0) -> (fadd X, X) 4731 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 4732 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0); 4733 // fold (fmul X, -1.0) -> (fneg X) 4734 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 4735 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4736 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0); 4737 4738 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y) 4739 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 4740 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 4741 // Both can be negated for free, check to see if at least one is cheaper 4742 // negated. 4743 if (LHSNeg == 2 || RHSNeg == 2) 4744 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 4745 GetNegatedExpression(N0, DAG, LegalOperations), 4746 GetNegatedExpression(N1, DAG, LegalOperations)); 4747 } 4748 } 4749 4750 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 4751 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 4752 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 4753 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0), 4754 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 4755 N0.getOperand(1), N1)); 4756 4757 return SDValue(); 4758} 4759 4760SDValue DAGCombiner::visitFDIV(SDNode *N) { 4761 SDValue N0 = N->getOperand(0); 4762 SDValue N1 = N->getOperand(1); 4763 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4764 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4765 EVT VT = N->getValueType(0); 4766 4767 // fold vector ops 4768 if (VT.isVector()) { 4769 SDValue FoldedVOp = SimplifyVBinOp(N); 4770 if (FoldedVOp.getNode()) return FoldedVOp; 4771 } 4772 4773 // fold (fdiv c1, c2) -> c1/c2 4774 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4775 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1); 4776 4777 4778 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y) 4779 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 4780 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 4781 // Both can be negated for free, check to see if at least one is cheaper 4782 // negated. 4783 if (LHSNeg == 2 || RHSNeg == 2) 4784 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, 4785 GetNegatedExpression(N0, DAG, LegalOperations), 4786 GetNegatedExpression(N1, DAG, LegalOperations)); 4787 } 4788 } 4789 4790 return SDValue(); 4791} 4792 4793SDValue DAGCombiner::visitFREM(SDNode *N) { 4794 SDValue N0 = N->getOperand(0); 4795 SDValue N1 = N->getOperand(1); 4796 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4797 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4798 EVT VT = N->getValueType(0); 4799 4800 // fold (frem c1, c2) -> fmod(c1,c2) 4801 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4802 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1); 4803 4804 return SDValue(); 4805} 4806 4807SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 4808 SDValue N0 = N->getOperand(0); 4809 SDValue N1 = N->getOperand(1); 4810 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4811 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4812 EVT VT = N->getValueType(0); 4813 4814 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 4815 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1); 4816 4817 if (N1CFP) { 4818 const APFloat& V = N1CFP->getValueAPF(); 4819 // copysign(x, c1) -> fabs(x) iff ispos(c1) 4820 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 4821 if (!V.isNegative()) { 4822 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) 4823 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4824 } else { 4825 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4826 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, 4827 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0)); 4828 } 4829 } 4830 4831 // copysign(fabs(x), y) -> copysign(x, y) 4832 // copysign(fneg(x), y) -> copysign(x, y) 4833 // copysign(copysign(x,z), y) -> copysign(x, y) 4834 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 4835 N0.getOpcode() == ISD::FCOPYSIGN) 4836 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4837 N0.getOperand(0), N1); 4838 4839 // copysign(x, abs(y)) -> abs(x) 4840 if (N1.getOpcode() == ISD::FABS) 4841 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4842 4843 // copysign(x, copysign(y,z)) -> copysign(x, z) 4844 if (N1.getOpcode() == ISD::FCOPYSIGN) 4845 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4846 N0, N1.getOperand(1)); 4847 4848 // copysign(x, fp_extend(y)) -> copysign(x, y) 4849 // copysign(x, fp_round(y)) -> copysign(x, y) 4850 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 4851 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4852 N0, N1.getOperand(0)); 4853 4854 return SDValue(); 4855} 4856 4857SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 4858 SDValue N0 = N->getOperand(0); 4859 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4860 EVT VT = N->getValueType(0); 4861 EVT OpVT = N0.getValueType(); 4862 4863 // fold (sint_to_fp c1) -> c1fp 4864 if (N0C && OpVT != MVT::ppcf128) 4865 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 4866 4867 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 4868 // but UINT_TO_FP is legal on this target, try to convert. 4869 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && 4870 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { 4871 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 4872 if (DAG.SignBitIsZero(N0)) 4873 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 4874 } 4875 4876 return SDValue(); 4877} 4878 4879SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 4880 SDValue N0 = N->getOperand(0); 4881 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4882 EVT VT = N->getValueType(0); 4883 EVT OpVT = N0.getValueType(); 4884 4885 // fold (uint_to_fp c1) -> c1fp 4886 if (N0C && OpVT != MVT::ppcf128) 4887 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 4888 4889 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 4890 // but SINT_TO_FP is legal on this target, try to convert. 4891 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && 4892 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { 4893 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 4894 if (DAG.SignBitIsZero(N0)) 4895 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 4896 } 4897 4898 return SDValue(); 4899} 4900 4901SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 4902 SDValue N0 = N->getOperand(0); 4903 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4904 EVT VT = N->getValueType(0); 4905 4906 // fold (fp_to_sint c1fp) -> c1 4907 if (N0CFP) 4908 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0); 4909 4910 return SDValue(); 4911} 4912 4913SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 4914 SDValue N0 = N->getOperand(0); 4915 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4916 EVT VT = N->getValueType(0); 4917 4918 // fold (fp_to_uint c1fp) -> c1 4919 if (N0CFP && VT != MVT::ppcf128) 4920 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0); 4921 4922 return SDValue(); 4923} 4924 4925SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 4926 SDValue N0 = N->getOperand(0); 4927 SDValue N1 = N->getOperand(1); 4928 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4929 EVT VT = N->getValueType(0); 4930 4931 // fold (fp_round c1fp) -> c1fp 4932 if (N0CFP && N0.getValueType() != MVT::ppcf128) 4933 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1); 4934 4935 // fold (fp_round (fp_extend x)) -> x 4936 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 4937 return N0.getOperand(0); 4938 4939 // fold (fp_round (fp_round x)) -> (fp_round x) 4940 if (N0.getOpcode() == ISD::FP_ROUND) { 4941 // This is a value preserving truncation if both round's are. 4942 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 4943 N0.getNode()->getConstantOperandVal(1) == 1; 4944 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0), 4945 DAG.getIntPtrConstant(IsTrunc)); 4946 } 4947 4948 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 4949 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { 4950 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT, 4951 N0.getOperand(0), N1); 4952 AddToWorkList(Tmp.getNode()); 4953 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4954 Tmp, N0.getOperand(1)); 4955 } 4956 4957 return SDValue(); 4958} 4959 4960SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 4961 SDValue N0 = N->getOperand(0); 4962 EVT VT = N->getValueType(0); 4963 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 4964 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4965 4966 // fold (fp_round_inreg c1fp) -> c1fp 4967 if (N0CFP && isTypeLegal(EVT)) { 4968 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT); 4969 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round); 4970 } 4971 4972 return SDValue(); 4973} 4974 4975SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 4976 SDValue N0 = N->getOperand(0); 4977 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4978 EVT VT = N->getValueType(0); 4979 4980 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 4981 if (N->hasOneUse() && 4982 N->use_begin()->getOpcode() == ISD::FP_ROUND) 4983 return SDValue(); 4984 4985 // fold (fp_extend c1fp) -> c1fp 4986 if (N0CFP && VT != MVT::ppcf128) 4987 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0); 4988 4989 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 4990 // value of X. 4991 if (N0.getOpcode() == ISD::FP_ROUND 4992 && N0.getNode()->getConstantOperandVal(1) == 1) { 4993 SDValue In = N0.getOperand(0); 4994 if (In.getValueType() == VT) return In; 4995 if (VT.bitsLT(In.getValueType())) 4996 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, 4997 In, N0.getOperand(1)); 4998 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In); 4999 } 5000 5001 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 5002 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 5003 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 5004 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 5005 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5006 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, N->getDebugLoc(), 5007 LN0->getChain(), 5008 LN0->getBasePtr(), LN0->getPointerInfo(), 5009 N0.getValueType(), 5010 LN0->isVolatile(), LN0->isNonTemporal(), 5011 LN0->getAlignment()); 5012 CombineTo(N, ExtLoad); 5013 CombineTo(N0.getNode(), 5014 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), 5015 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)), 5016 ExtLoad.getValue(1)); 5017 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5018 } 5019 5020 return SDValue(); 5021} 5022 5023SDValue DAGCombiner::visitFNEG(SDNode *N) { 5024 SDValue N0 = N->getOperand(0); 5025 EVT VT = N->getValueType(0); 5026 5027 if (isNegatibleForFree(N0, LegalOperations)) 5028 return GetNegatedExpression(N0, DAG, LegalOperations); 5029 5030 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 5031 // constant pool values. 5032 if (N0.getOpcode() == ISD::BIT_CONVERT && 5033 !VT.isVector() && 5034 N0.getNode()->hasOneUse() && 5035 N0.getOperand(0).getValueType().isInteger()) { 5036 SDValue Int = N0.getOperand(0); 5037 EVT IntVT = Int.getValueType(); 5038 if (IntVT.isInteger() && !IntVT.isVector()) { 5039 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int, 5040 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 5041 AddToWorkList(Int.getNode()); 5042 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), 5043 VT, Int); 5044 } 5045 } 5046 5047 return SDValue(); 5048} 5049 5050SDValue DAGCombiner::visitFABS(SDNode *N) { 5051 SDValue N0 = N->getOperand(0); 5052 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5053 EVT VT = N->getValueType(0); 5054 5055 // fold (fabs c1) -> fabs(c1) 5056 if (N0CFP && VT != MVT::ppcf128) 5057 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 5058 // fold (fabs (fabs x)) -> (fabs x) 5059 if (N0.getOpcode() == ISD::FABS) 5060 return N->getOperand(0); 5061 // fold (fabs (fneg x)) -> (fabs x) 5062 // fold (fabs (fcopysign x, y)) -> (fabs x) 5063 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 5064 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0)); 5065 5066 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 5067 // constant pool values. 5068 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() && 5069 N0.getOperand(0).getValueType().isInteger() && 5070 !N0.getOperand(0).getValueType().isVector()) { 5071 SDValue Int = N0.getOperand(0); 5072 EVT IntVT = Int.getValueType(); 5073 if (IntVT.isInteger() && !IntVT.isVector()) { 5074 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int, 5075 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 5076 AddToWorkList(Int.getNode()); 5077 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), 5078 N->getValueType(0), Int); 5079 } 5080 } 5081 5082 return SDValue(); 5083} 5084 5085SDValue DAGCombiner::visitBRCOND(SDNode *N) { 5086 SDValue Chain = N->getOperand(0); 5087 SDValue N1 = N->getOperand(1); 5088 SDValue N2 = N->getOperand(2); 5089 5090 // If N is a constant we could fold this into a fallthrough or unconditional 5091 // branch. However that doesn't happen very often in normal code, because 5092 // Instcombine/SimplifyCFG should have handled the available opportunities. 5093 // If we did this folding here, it would be necessary to update the 5094 // MachineBasicBlock CFG, which is awkward. 5095 5096 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 5097 // on the target. 5098 if (N1.getOpcode() == ISD::SETCC && 5099 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) { 5100 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 5101 Chain, N1.getOperand(2), 5102 N1.getOperand(0), N1.getOperand(1), N2); 5103 } 5104 5105 SDNode *Trunc = 0; 5106 if (N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) { 5107 // Look past truncate. 5108 Trunc = N1.getNode(); 5109 N1 = N1.getOperand(0); 5110 } 5111 5112 if (N1.hasOneUse() && N1.getOpcode() == ISD::SRL) { 5113 // Match this pattern so that we can generate simpler code: 5114 // 5115 // %a = ... 5116 // %b = and i32 %a, 2 5117 // %c = srl i32 %b, 1 5118 // brcond i32 %c ... 5119 // 5120 // into 5121 // 5122 // %a = ... 5123 // %b = and i32 %a, 2 5124 // %c = setcc eq %b, 0 5125 // brcond %c ... 5126 // 5127 // This applies only when the AND constant value has one bit set and the 5128 // SRL constant is equal to the log2 of the AND constant. The back-end is 5129 // smart enough to convert the result into a TEST/JMP sequence. 5130 SDValue Op0 = N1.getOperand(0); 5131 SDValue Op1 = N1.getOperand(1); 5132 5133 if (Op0.getOpcode() == ISD::AND && 5134 Op1.getOpcode() == ISD::Constant) { 5135 SDValue AndOp1 = Op0.getOperand(1); 5136 5137 if (AndOp1.getOpcode() == ISD::Constant) { 5138 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue(); 5139 5140 if (AndConst.isPowerOf2() && 5141 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) { 5142 SDValue SetCC = 5143 DAG.getSetCC(N->getDebugLoc(), 5144 TLI.getSetCCResultType(Op0.getValueType()), 5145 Op0, DAG.getConstant(0, Op0.getValueType()), 5146 ISD::SETNE); 5147 5148 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 5149 MVT::Other, Chain, SetCC, N2); 5150 // Don't add the new BRCond into the worklist or else SimplifySelectCC 5151 // will convert it back to (X & C1) >> C2. 5152 CombineTo(N, NewBRCond, false); 5153 // Truncate is dead. 5154 if (Trunc) { 5155 removeFromWorkList(Trunc); 5156 DAG.DeleteNode(Trunc); 5157 } 5158 // Replace the uses of SRL with SETCC 5159 WorkListRemover DeadNodes(*this); 5160 DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes); 5161 removeFromWorkList(N1.getNode()); 5162 DAG.DeleteNode(N1.getNode()); 5163 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5164 } 5165 } 5166 } 5167 } 5168 5169 // Transform br(xor(x, y)) -> br(x != y) 5170 // Transform br(xor(xor(x,y), 1)) -> br (x == y) 5171 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) { 5172 SDNode *TheXor = N1.getNode(); 5173 SDValue Op0 = TheXor->getOperand(0); 5174 SDValue Op1 = TheXor->getOperand(1); 5175 if (Op0.getOpcode() == Op1.getOpcode()) { 5176 // Avoid missing important xor optimizations. 5177 SDValue Tmp = visitXOR(TheXor); 5178 if (Tmp.getNode() && Tmp.getNode() != TheXor) { 5179 DEBUG(dbgs() << "\nReplacing.8 "; 5180 TheXor->dump(&DAG); 5181 dbgs() << "\nWith: "; 5182 Tmp.getNode()->dump(&DAG); 5183 dbgs() << '\n'); 5184 WorkListRemover DeadNodes(*this); 5185 DAG.ReplaceAllUsesOfValueWith(N1, Tmp, &DeadNodes); 5186 removeFromWorkList(TheXor); 5187 DAG.DeleteNode(TheXor); 5188 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 5189 MVT::Other, Chain, Tmp, N2); 5190 } 5191 } 5192 5193 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) { 5194 bool Equal = false; 5195 if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0)) 5196 if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() && 5197 Op0.getOpcode() == ISD::XOR) { 5198 TheXor = Op0.getNode(); 5199 Equal = true; 5200 } 5201 5202 SDValue NodeToReplace = Trunc ? SDValue(Trunc, 0) : N1; 5203 5204 EVT SetCCVT = NodeToReplace.getValueType(); 5205 if (LegalTypes) 5206 SetCCVT = TLI.getSetCCResultType(SetCCVT); 5207 SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(), 5208 SetCCVT, 5209 Op0, Op1, 5210 Equal ? ISD::SETEQ : ISD::SETNE); 5211 // Replace the uses of XOR with SETCC 5212 WorkListRemover DeadNodes(*this); 5213 DAG.ReplaceAllUsesOfValueWith(NodeToReplace, SetCC, &DeadNodes); 5214 removeFromWorkList(NodeToReplace.getNode()); 5215 DAG.DeleteNode(NodeToReplace.getNode()); 5216 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 5217 MVT::Other, Chain, SetCC, N2); 5218 } 5219 } 5220 5221 return SDValue(); 5222} 5223 5224// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 5225// 5226SDValue DAGCombiner::visitBR_CC(SDNode *N) { 5227 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 5228 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 5229 5230 // If N is a constant we could fold this into a fallthrough or unconditional 5231 // branch. However that doesn't happen very often in normal code, because 5232 // Instcombine/SimplifyCFG should have handled the available opportunities. 5233 // If we did this folding here, it would be necessary to update the 5234 // MachineBasicBlock CFG, which is awkward. 5235 5236 // Use SimplifySetCC to simplify SETCC's. 5237 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()), 5238 CondLHS, CondRHS, CC->get(), N->getDebugLoc(), 5239 false); 5240 if (Simp.getNode()) AddToWorkList(Simp.getNode()); 5241 5242 // fold to a simpler setcc 5243 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) 5244 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 5245 N->getOperand(0), Simp.getOperand(2), 5246 Simp.getOperand(0), Simp.getOperand(1), 5247 N->getOperand(4)); 5248 5249 return SDValue(); 5250} 5251 5252/// CombineToPreIndexedLoadStore - Try turning a load / store into a 5253/// pre-indexed load / store when the base pointer is an add or subtract 5254/// and it has other uses besides the load / store. After the 5255/// transformation, the new indexed load / store has effectively folded 5256/// the add / subtract in and all of its other uses are redirected to the 5257/// new load / store. 5258bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 5259 if (!LegalOperations) 5260 return false; 5261 5262 bool isLoad = true; 5263 SDValue Ptr; 5264 EVT VT; 5265 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 5266 if (LD->isIndexed()) 5267 return false; 5268 VT = LD->getMemoryVT(); 5269 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 5270 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 5271 return false; 5272 Ptr = LD->getBasePtr(); 5273 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 5274 if (ST->isIndexed()) 5275 return false; 5276 VT = ST->getMemoryVT(); 5277 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 5278 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 5279 return false; 5280 Ptr = ST->getBasePtr(); 5281 isLoad = false; 5282 } else { 5283 return false; 5284 } 5285 5286 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 5287 // out. There is no reason to make this a preinc/predec. 5288 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 5289 Ptr.getNode()->hasOneUse()) 5290 return false; 5291 5292 // Ask the target to do addressing mode selection. 5293 SDValue BasePtr; 5294 SDValue Offset; 5295 ISD::MemIndexedMode AM = ISD::UNINDEXED; 5296 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 5297 return false; 5298 // Don't create a indexed load / store with zero offset. 5299 if (isa<ConstantSDNode>(Offset) && 5300 cast<ConstantSDNode>(Offset)->isNullValue()) 5301 return false; 5302 5303 // Try turning it into a pre-indexed load / store except when: 5304 // 1) The new base ptr is a frame index. 5305 // 2) If N is a store and the new base ptr is either the same as or is a 5306 // predecessor of the value being stored. 5307 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 5308 // that would create a cycle. 5309 // 4) All uses are load / store ops that use it as old base ptr. 5310 5311 // Check #1. Preinc'ing a frame index would require copying the stack pointer 5312 // (plus the implicit offset) to a register to preinc anyway. 5313 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 5314 return false; 5315 5316 // Check #2. 5317 if (!isLoad) { 5318 SDValue Val = cast<StoreSDNode>(N)->getValue(); 5319 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode())) 5320 return false; 5321 } 5322 5323 // Now check for #3 and #4. 5324 bool RealUse = false; 5325 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 5326 E = Ptr.getNode()->use_end(); I != E; ++I) { 5327 SDNode *Use = *I; 5328 if (Use == N) 5329 continue; 5330 if (Use->isPredecessorOf(N)) 5331 return false; 5332 5333 if (!((Use->getOpcode() == ISD::LOAD && 5334 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 5335 (Use->getOpcode() == ISD::STORE && 5336 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))) 5337 RealUse = true; 5338 } 5339 5340 if (!RealUse) 5341 return false; 5342 5343 SDValue Result; 5344 if (isLoad) 5345 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 5346 BasePtr, Offset, AM); 5347 else 5348 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 5349 BasePtr, Offset, AM); 5350 ++PreIndexedNodes; 5351 ++NodesCombined; 5352 DEBUG(dbgs() << "\nReplacing.4 "; 5353 N->dump(&DAG); 5354 dbgs() << "\nWith: "; 5355 Result.getNode()->dump(&DAG); 5356 dbgs() << '\n'); 5357 WorkListRemover DeadNodes(*this); 5358 if (isLoad) { 5359 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 5360 &DeadNodes); 5361 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 5362 &DeadNodes); 5363 } else { 5364 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 5365 &DeadNodes); 5366 } 5367 5368 // Finally, since the node is now dead, remove it from the graph. 5369 DAG.DeleteNode(N); 5370 5371 // Replace the uses of Ptr with uses of the updated base value. 5372 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 5373 &DeadNodes); 5374 removeFromWorkList(Ptr.getNode()); 5375 DAG.DeleteNode(Ptr.getNode()); 5376 5377 return true; 5378} 5379 5380/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 5381/// add / sub of the base pointer node into a post-indexed load / store. 5382/// The transformation folded the add / subtract into the new indexed 5383/// load / store effectively and all of its uses are redirected to the 5384/// new load / store. 5385bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 5386 if (!LegalOperations) 5387 return false; 5388 5389 bool isLoad = true; 5390 SDValue Ptr; 5391 EVT VT; 5392 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 5393 if (LD->isIndexed()) 5394 return false; 5395 VT = LD->getMemoryVT(); 5396 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 5397 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 5398 return false; 5399 Ptr = LD->getBasePtr(); 5400 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 5401 if (ST->isIndexed()) 5402 return false; 5403 VT = ST->getMemoryVT(); 5404 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 5405 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 5406 return false; 5407 Ptr = ST->getBasePtr(); 5408 isLoad = false; 5409 } else { 5410 return false; 5411 } 5412 5413 if (Ptr.getNode()->hasOneUse()) 5414 return false; 5415 5416 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 5417 E = Ptr.getNode()->use_end(); I != E; ++I) { 5418 SDNode *Op = *I; 5419 if (Op == N || 5420 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 5421 continue; 5422 5423 SDValue BasePtr; 5424 SDValue Offset; 5425 ISD::MemIndexedMode AM = ISD::UNINDEXED; 5426 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 5427 // Don't create a indexed load / store with zero offset. 5428 if (isa<ConstantSDNode>(Offset) && 5429 cast<ConstantSDNode>(Offset)->isNullValue()) 5430 continue; 5431 5432 // Try turning it into a post-indexed load / store except when 5433 // 1) All uses are load / store ops that use it as base ptr. 5434 // 2) Op must be independent of N, i.e. Op is neither a predecessor 5435 // nor a successor of N. Otherwise, if Op is folded that would 5436 // create a cycle. 5437 5438 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 5439 continue; 5440 5441 // Check for #1. 5442 bool TryNext = false; 5443 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), 5444 EE = BasePtr.getNode()->use_end(); II != EE; ++II) { 5445 SDNode *Use = *II; 5446 if (Use == Ptr.getNode()) 5447 continue; 5448 5449 // If all the uses are load / store addresses, then don't do the 5450 // transformation. 5451 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 5452 bool RealUse = false; 5453 for (SDNode::use_iterator III = Use->use_begin(), 5454 EEE = Use->use_end(); III != EEE; ++III) { 5455 SDNode *UseUse = *III; 5456 if (!((UseUse->getOpcode() == ISD::LOAD && 5457 cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) || 5458 (UseUse->getOpcode() == ISD::STORE && 5459 cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use))) 5460 RealUse = true; 5461 } 5462 5463 if (!RealUse) { 5464 TryNext = true; 5465 break; 5466 } 5467 } 5468 } 5469 5470 if (TryNext) 5471 continue; 5472 5473 // Check for #2 5474 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 5475 SDValue Result = isLoad 5476 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 5477 BasePtr, Offset, AM) 5478 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 5479 BasePtr, Offset, AM); 5480 ++PostIndexedNodes; 5481 ++NodesCombined; 5482 DEBUG(dbgs() << "\nReplacing.5 "; 5483 N->dump(&DAG); 5484 dbgs() << "\nWith: "; 5485 Result.getNode()->dump(&DAG); 5486 dbgs() << '\n'); 5487 WorkListRemover DeadNodes(*this); 5488 if (isLoad) { 5489 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 5490 &DeadNodes); 5491 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 5492 &DeadNodes); 5493 } else { 5494 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 5495 &DeadNodes); 5496 } 5497 5498 // Finally, since the node is now dead, remove it from the graph. 5499 DAG.DeleteNode(N); 5500 5501 // Replace the uses of Use with uses of the updated base value. 5502 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 5503 Result.getValue(isLoad ? 1 : 0), 5504 &DeadNodes); 5505 removeFromWorkList(Op); 5506 DAG.DeleteNode(Op); 5507 return true; 5508 } 5509 } 5510 } 5511 5512 return false; 5513} 5514 5515SDValue DAGCombiner::visitLOAD(SDNode *N) { 5516 LoadSDNode *LD = cast<LoadSDNode>(N); 5517 SDValue Chain = LD->getChain(); 5518 SDValue Ptr = LD->getBasePtr(); 5519 5520 // If load is not volatile and there are no uses of the loaded value (and 5521 // the updated indexed value in case of indexed loads), change uses of the 5522 // chain value into uses of the chain input (i.e. delete the dead load). 5523 if (!LD->isVolatile()) { 5524 if (N->getValueType(1) == MVT::Other) { 5525 // Unindexed loads. 5526 if (N->hasNUsesOfValue(0, 0)) { 5527 // It's not safe to use the two value CombineTo variant here. e.g. 5528 // v1, chain2 = load chain1, loc 5529 // v2, chain3 = load chain2, loc 5530 // v3 = add v2, c 5531 // Now we replace use of chain2 with chain1. This makes the second load 5532 // isomorphic to the one we are deleting, and thus makes this load live. 5533 DEBUG(dbgs() << "\nReplacing.6 "; 5534 N->dump(&DAG); 5535 dbgs() << "\nWith chain: "; 5536 Chain.getNode()->dump(&DAG); 5537 dbgs() << "\n"); 5538 WorkListRemover DeadNodes(*this); 5539 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes); 5540 5541 if (N->use_empty()) { 5542 removeFromWorkList(N); 5543 DAG.DeleteNode(N); 5544 } 5545 5546 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5547 } 5548 } else { 5549 // Indexed loads. 5550 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 5551 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 5552 SDValue Undef = DAG.getUNDEF(N->getValueType(0)); 5553 DEBUG(dbgs() << "\nReplacing.7 "; 5554 N->dump(&DAG); 5555 dbgs() << "\nWith: "; 5556 Undef.getNode()->dump(&DAG); 5557 dbgs() << " and 2 other values\n"); 5558 WorkListRemover DeadNodes(*this); 5559 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes); 5560 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 5561 DAG.getUNDEF(N->getValueType(1)), 5562 &DeadNodes); 5563 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes); 5564 removeFromWorkList(N); 5565 DAG.DeleteNode(N); 5566 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5567 } 5568 } 5569 } 5570 5571 // If this load is directly stored, replace the load value with the stored 5572 // value. 5573 // TODO: Handle store large -> read small portion. 5574 // TODO: Handle TRUNCSTORE/LOADEXT 5575 if (LD->getExtensionType() == ISD::NON_EXTLOAD && 5576 !LD->isVolatile()) { 5577 if (ISD::isNON_TRUNCStore(Chain.getNode())) { 5578 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 5579 if (PrevST->getBasePtr() == Ptr && 5580 PrevST->getValue().getValueType() == N->getValueType(0)) 5581 return CombineTo(N, Chain.getOperand(1), Chain); 5582 } 5583 } 5584 5585 // Try to infer better alignment information than the load already has. 5586 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) { 5587 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 5588 if (Align > LD->getAlignment()) 5589 return DAG.getExtLoad(LD->getExtensionType(), LD->getValueType(0), 5590 N->getDebugLoc(), 5591 Chain, Ptr, LD->getPointerInfo(), 5592 LD->getMemoryVT(), 5593 LD->isVolatile(), LD->isNonTemporal(), Align); 5594 } 5595 } 5596 5597 if (CombinerAA) { 5598 // Walk up chain skipping non-aliasing memory nodes. 5599 SDValue BetterChain = FindBetterChain(N, Chain); 5600 5601 // If there is a better chain. 5602 if (Chain != BetterChain) { 5603 SDValue ReplLoad; 5604 5605 // Replace the chain to void dependency. 5606 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 5607 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(), 5608 BetterChain, Ptr, LD->getPointerInfo(), 5609 LD->isVolatile(), LD->isNonTemporal(), 5610 LD->getAlignment()); 5611 } else { 5612 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getValueType(0), 5613 LD->getDebugLoc(), 5614 BetterChain, Ptr, LD->getPointerInfo(), 5615 LD->getMemoryVT(), 5616 LD->isVolatile(), 5617 LD->isNonTemporal(), 5618 LD->getAlignment()); 5619 } 5620 5621 // Create token factor to keep old chain connected. 5622 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 5623 MVT::Other, Chain, ReplLoad.getValue(1)); 5624 5625 // Make sure the new and old chains are cleaned up. 5626 AddToWorkList(Token.getNode()); 5627 5628 // Replace uses with load result and token factor. Don't add users 5629 // to work list. 5630 return CombineTo(N, ReplLoad.getValue(0), Token, false); 5631 } 5632 } 5633 5634 // Try transforming N to an indexed load. 5635 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 5636 return SDValue(N, 0); 5637 5638 return SDValue(); 5639} 5640 5641/// CheckForMaskedLoad - Check to see if V is (and load (ptr), imm), where the 5642/// load is having specific bytes cleared out. If so, return the byte size 5643/// being masked out and the shift amount. 5644static std::pair<unsigned, unsigned> 5645CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) { 5646 std::pair<unsigned, unsigned> Result(0, 0); 5647 5648 // Check for the structure we're looking for. 5649 if (V->getOpcode() != ISD::AND || 5650 !isa<ConstantSDNode>(V->getOperand(1)) || 5651 !ISD::isNormalLoad(V->getOperand(0).getNode())) 5652 return Result; 5653 5654 // Check the chain and pointer. 5655 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0)); 5656 if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer. 5657 5658 // The store should be chained directly to the load or be an operand of a 5659 // tokenfactor. 5660 if (LD == Chain.getNode()) 5661 ; // ok. 5662 else if (Chain->getOpcode() != ISD::TokenFactor) 5663 return Result; // Fail. 5664 else { 5665 bool isOk = false; 5666 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i) 5667 if (Chain->getOperand(i).getNode() == LD) { 5668 isOk = true; 5669 break; 5670 } 5671 if (!isOk) return Result; 5672 } 5673 5674 // This only handles simple types. 5675 if (V.getValueType() != MVT::i16 && 5676 V.getValueType() != MVT::i32 && 5677 V.getValueType() != MVT::i64) 5678 return Result; 5679 5680 // Check the constant mask. Invert it so that the bits being masked out are 5681 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits 5682 // follow the sign bit for uniformity. 5683 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue(); 5684 unsigned NotMaskLZ = CountLeadingZeros_64(NotMask); 5685 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte. 5686 unsigned NotMaskTZ = CountTrailingZeros_64(NotMask); 5687 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte. 5688 if (NotMaskLZ == 64) return Result; // All zero mask. 5689 5690 // See if we have a continuous run of bits. If so, we have 0*1+0* 5691 if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64) 5692 return Result; 5693 5694 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64. 5695 if (V.getValueType() != MVT::i64 && NotMaskLZ) 5696 NotMaskLZ -= 64-V.getValueSizeInBits(); 5697 5698 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8; 5699 switch (MaskedBytes) { 5700 case 1: 5701 case 2: 5702 case 4: break; 5703 default: return Result; // All one mask, or 5-byte mask. 5704 } 5705 5706 // Verify that the first bit starts at a multiple of mask so that the access 5707 // is aligned the same as the access width. 5708 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result; 5709 5710 Result.first = MaskedBytes; 5711 Result.second = NotMaskTZ/8; 5712 return Result; 5713} 5714 5715 5716/// ShrinkLoadReplaceStoreWithStore - Check to see if IVal is something that 5717/// provides a value as specified by MaskInfo. If so, replace the specified 5718/// store with a narrower store of truncated IVal. 5719static SDNode * 5720ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo, 5721 SDValue IVal, StoreSDNode *St, 5722 DAGCombiner *DC) { 5723 unsigned NumBytes = MaskInfo.first; 5724 unsigned ByteShift = MaskInfo.second; 5725 SelectionDAG &DAG = DC->getDAG(); 5726 5727 // Check to see if IVal is all zeros in the part being masked in by the 'or' 5728 // that uses this. If not, this is not a replacement. 5729 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(), 5730 ByteShift*8, (ByteShift+NumBytes)*8); 5731 if (!DAG.MaskedValueIsZero(IVal, Mask)) return 0; 5732 5733 // Check that it is legal on the target to do this. It is legal if the new 5734 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type 5735 // legalization. 5736 MVT VT = MVT::getIntegerVT(NumBytes*8); 5737 if (!DC->isTypeLegal(VT)) 5738 return 0; 5739 5740 // Okay, we can do this! Replace the 'St' store with a store of IVal that is 5741 // shifted by ByteShift and truncated down to NumBytes. 5742 if (ByteShift) 5743 IVal = DAG.getNode(ISD::SRL, IVal->getDebugLoc(), IVal.getValueType(), IVal, 5744 DAG.getConstant(ByteShift*8, DC->getShiftAmountTy())); 5745 5746 // Figure out the offset for the store and the alignment of the access. 5747 unsigned StOffset; 5748 unsigned NewAlign = St->getAlignment(); 5749 5750 if (DAG.getTargetLoweringInfo().isLittleEndian()) 5751 StOffset = ByteShift; 5752 else 5753 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes; 5754 5755 SDValue Ptr = St->getBasePtr(); 5756 if (StOffset) { 5757 Ptr = DAG.getNode(ISD::ADD, IVal->getDebugLoc(), Ptr.getValueType(), 5758 Ptr, DAG.getConstant(StOffset, Ptr.getValueType())); 5759 NewAlign = MinAlign(NewAlign, StOffset); 5760 } 5761 5762 // Truncate down to the new size. 5763 IVal = DAG.getNode(ISD::TRUNCATE, IVal->getDebugLoc(), VT, IVal); 5764 5765 ++OpsNarrowed; 5766 return DAG.getStore(St->getChain(), St->getDebugLoc(), IVal, Ptr, 5767 St->getPointerInfo().getWithOffset(StOffset), 5768 false, false, NewAlign).getNode(); 5769} 5770 5771 5772/// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is 5773/// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some 5774/// of the loaded bits, try narrowing the load and store if it would end up 5775/// being a win for performance or code size. 5776SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) { 5777 StoreSDNode *ST = cast<StoreSDNode>(N); 5778 if (ST->isVolatile()) 5779 return SDValue(); 5780 5781 SDValue Chain = ST->getChain(); 5782 SDValue Value = ST->getValue(); 5783 SDValue Ptr = ST->getBasePtr(); 5784 EVT VT = Value.getValueType(); 5785 5786 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse()) 5787 return SDValue(); 5788 5789 unsigned Opc = Value.getOpcode(); 5790 5791 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst 5792 // is a byte mask indicating a consecutive number of bytes, check to see if 5793 // Y is known to provide just those bytes. If so, we try to replace the 5794 // load + replace + store sequence with a single (narrower) store, which makes 5795 // the load dead. 5796 if (Opc == ISD::OR) { 5797 std::pair<unsigned, unsigned> MaskedLoad; 5798 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain); 5799 if (MaskedLoad.first) 5800 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 5801 Value.getOperand(1), ST,this)) 5802 return SDValue(NewST, 0); 5803 5804 // Or is commutative, so try swapping X and Y. 5805 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain); 5806 if (MaskedLoad.first) 5807 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 5808 Value.getOperand(0), ST,this)) 5809 return SDValue(NewST, 0); 5810 } 5811 5812 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) || 5813 Value.getOperand(1).getOpcode() != ISD::Constant) 5814 return SDValue(); 5815 5816 SDValue N0 = Value.getOperand(0); 5817 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 5818 Chain == SDValue(N0.getNode(), 1)) { 5819 LoadSDNode *LD = cast<LoadSDNode>(N0); 5820 if (LD->getBasePtr() != Ptr || 5821 LD->getPointerInfo().getAddrSpace() != 5822 ST->getPointerInfo().getAddrSpace()) 5823 return SDValue(); 5824 5825 // Find the type to narrow it the load / op / store to. 5826 SDValue N1 = Value.getOperand(1); 5827 unsigned BitWidth = N1.getValueSizeInBits(); 5828 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue(); 5829 if (Opc == ISD::AND) 5830 Imm ^= APInt::getAllOnesValue(BitWidth); 5831 if (Imm == 0 || Imm.isAllOnesValue()) 5832 return SDValue(); 5833 unsigned ShAmt = Imm.countTrailingZeros(); 5834 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1; 5835 unsigned NewBW = NextPowerOf2(MSB - ShAmt); 5836 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 5837 while (NewBW < BitWidth && 5838 !(TLI.isOperationLegalOrCustom(Opc, NewVT) && 5839 TLI.isNarrowingProfitable(VT, NewVT))) { 5840 NewBW = NextPowerOf2(NewBW); 5841 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 5842 } 5843 if (NewBW >= BitWidth) 5844 return SDValue(); 5845 5846 // If the lsb changed does not start at the type bitwidth boundary, 5847 // start at the previous one. 5848 if (ShAmt % NewBW) 5849 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW; 5850 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW); 5851 if ((Imm & Mask) == Imm) { 5852 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW); 5853 if (Opc == ISD::AND) 5854 NewImm ^= APInt::getAllOnesValue(NewBW); 5855 uint64_t PtrOff = ShAmt / 8; 5856 // For big endian targets, we need to adjust the offset to the pointer to 5857 // load the correct bytes. 5858 if (TLI.isBigEndian()) 5859 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff; 5860 5861 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff); 5862 const Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext()); 5863 if (NewAlign < TLI.getTargetData()->getABITypeAlignment(NewVTTy)) 5864 return SDValue(); 5865 5866 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(), 5867 Ptr.getValueType(), Ptr, 5868 DAG.getConstant(PtrOff, Ptr.getValueType())); 5869 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(), 5870 LD->getChain(), NewPtr, 5871 LD->getPointerInfo().getWithOffset(PtrOff), 5872 LD->isVolatile(), LD->isNonTemporal(), 5873 NewAlign); 5874 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD, 5875 DAG.getConstant(NewImm, NewVT)); 5876 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(), 5877 NewVal, NewPtr, 5878 ST->getPointerInfo().getWithOffset(PtrOff), 5879 false, false, NewAlign); 5880 5881 AddToWorkList(NewPtr.getNode()); 5882 AddToWorkList(NewLD.getNode()); 5883 AddToWorkList(NewVal.getNode()); 5884 WorkListRemover DeadNodes(*this); 5885 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1), 5886 &DeadNodes); 5887 ++OpsNarrowed; 5888 return NewST; 5889 } 5890 } 5891 5892 return SDValue(); 5893} 5894 5895SDValue DAGCombiner::visitSTORE(SDNode *N) { 5896 StoreSDNode *ST = cast<StoreSDNode>(N); 5897 SDValue Chain = ST->getChain(); 5898 SDValue Value = ST->getValue(); 5899 SDValue Ptr = ST->getBasePtr(); 5900 5901 // If this is a store of a bit convert, store the input value if the 5902 // resultant store does not need a higher alignment than the original. 5903 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() && 5904 ST->isUnindexed()) { 5905 unsigned OrigAlign = ST->getAlignment(); 5906 EVT SVT = Value.getOperand(0).getValueType(); 5907 unsigned Align = TLI.getTargetData()-> 5908 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext())); 5909 if (Align <= OrigAlign && 5910 ((!LegalOperations && !ST->isVolatile()) || 5911 TLI.isOperationLegalOrCustom(ISD::STORE, SVT))) 5912 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0), 5913 Ptr, ST->getPointerInfo(), ST->isVolatile(), 5914 ST->isNonTemporal(), OrigAlign); 5915 } 5916 5917 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 5918 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 5919 // NOTE: If the original store is volatile, this transform must not increase 5920 // the number of stores. For example, on x86-32 an f64 can be stored in one 5921 // processor operation but an i64 (which is not legal) requires two. So the 5922 // transform should not be done in this case. 5923 if (Value.getOpcode() != ISD::TargetConstantFP) { 5924 SDValue Tmp; 5925 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) { 5926 default: llvm_unreachable("Unknown FP type"); 5927 case MVT::f80: // We don't do this for these yet. 5928 case MVT::f128: 5929 case MVT::ppcf128: 5930 break; 5931 case MVT::f32: 5932 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) || 5933 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 5934 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 5935 bitcastToAPInt().getZExtValue(), MVT::i32); 5936 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 5937 Ptr, ST->getPointerInfo(), ST->isVolatile(), 5938 ST->isNonTemporal(), ST->getAlignment()); 5939 } 5940 break; 5941 case MVT::f64: 5942 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations && 5943 !ST->isVolatile()) || 5944 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) { 5945 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 5946 getZExtValue(), MVT::i64); 5947 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 5948 Ptr, ST->getPointerInfo(), ST->isVolatile(), 5949 ST->isNonTemporal(), ST->getAlignment()); 5950 } else if (!ST->isVolatile() && 5951 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 5952 // Many FP stores are not made apparent until after legalize, e.g. for 5953 // argument passing. Since this is so common, custom legalize the 5954 // 64-bit integer store into two 32-bit stores. 5955 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); 5956 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 5957 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 5958 if (TLI.isBigEndian()) std::swap(Lo, Hi); 5959 5960 unsigned Alignment = ST->getAlignment(); 5961 bool isVolatile = ST->isVolatile(); 5962 bool isNonTemporal = ST->isNonTemporal(); 5963 5964 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo, 5965 Ptr, ST->getPointerInfo(), 5966 isVolatile, isNonTemporal, 5967 ST->getAlignment()); 5968 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr, 5969 DAG.getConstant(4, Ptr.getValueType())); 5970 Alignment = MinAlign(Alignment, 4U); 5971 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi, 5972 Ptr, ST->getPointerInfo().getWithOffset(4), 5973 isVolatile, isNonTemporal, 5974 Alignment); 5975 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 5976 St0, St1); 5977 } 5978 5979 break; 5980 } 5981 } 5982 } 5983 5984 // Try to infer better alignment information than the store already has. 5985 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) { 5986 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 5987 if (Align > ST->getAlignment()) 5988 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value, 5989 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 5990 ST->isVolatile(), ST->isNonTemporal(), Align); 5991 } 5992 } 5993 5994 if (CombinerAA) { 5995 // Walk up chain skipping non-aliasing memory nodes. 5996 SDValue BetterChain = FindBetterChain(N, Chain); 5997 5998 // If there is a better chain. 5999 if (Chain != BetterChain) { 6000 SDValue ReplStore; 6001 6002 // Replace the chain to avoid dependency. 6003 if (ST->isTruncatingStore()) { 6004 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr, 6005 ST->getPointerInfo(), 6006 ST->getMemoryVT(), ST->isVolatile(), 6007 ST->isNonTemporal(), ST->getAlignment()); 6008 } else { 6009 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr, 6010 ST->getPointerInfo(), 6011 ST->isVolatile(), ST->isNonTemporal(), 6012 ST->getAlignment()); 6013 } 6014 6015 // Create token to keep both nodes around. 6016 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 6017 MVT::Other, Chain, ReplStore); 6018 6019 // Make sure the new and old chains are cleaned up. 6020 AddToWorkList(Token.getNode()); 6021 6022 // Don't add users to work list. 6023 return CombineTo(N, Token, false); 6024 } 6025 } 6026 6027 // Try transforming N to an indexed store. 6028 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 6029 return SDValue(N, 0); 6030 6031 // FIXME: is there such a thing as a truncating indexed store? 6032 if (ST->isTruncatingStore() && ST->isUnindexed() && 6033 Value.getValueType().isInteger()) { 6034 // See if we can simplify the input to this truncstore with knowledge that 6035 // only the low bits are being used. For example: 6036 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 6037 SDValue Shorter = 6038 GetDemandedBits(Value, 6039 APInt::getLowBitsSet(Value.getValueSizeInBits(), 6040 ST->getMemoryVT().getSizeInBits())); 6041 AddToWorkList(Value.getNode()); 6042 if (Shorter.getNode()) 6043 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter, 6044 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 6045 ST->isVolatile(), ST->isNonTemporal(), 6046 ST->getAlignment()); 6047 6048 // Otherwise, see if we can simplify the operation with 6049 // SimplifyDemandedBits, which only works if the value has a single use. 6050 if (SimplifyDemandedBits(Value, 6051 APInt::getLowBitsSet( 6052 Value.getValueType().getScalarType().getSizeInBits(), 6053 ST->getMemoryVT().getScalarType().getSizeInBits()))) 6054 return SDValue(N, 0); 6055 } 6056 6057 // If this is a load followed by a store to the same location, then the store 6058 // is dead/noop. 6059 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 6060 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 6061 ST->isUnindexed() && !ST->isVolatile() && 6062 // There can't be any side effects between the load and store, such as 6063 // a call or store. 6064 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 6065 // The store is dead, remove it. 6066 return Chain; 6067 } 6068 } 6069 6070 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 6071 // truncating store. We can do this even if this is already a truncstore. 6072 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 6073 && Value.getNode()->hasOneUse() && ST->isUnindexed() && 6074 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 6075 ST->getMemoryVT())) { 6076 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0), 6077 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 6078 ST->isVolatile(), ST->isNonTemporal(), 6079 ST->getAlignment()); 6080 } 6081 6082 return ReduceLoadOpStoreWidth(N); 6083} 6084 6085SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 6086 SDValue InVec = N->getOperand(0); 6087 SDValue InVal = N->getOperand(1); 6088 SDValue EltNo = N->getOperand(2); 6089 6090 // If the inserted element is an UNDEF, just use the input vector. 6091 if (InVal.getOpcode() == ISD::UNDEF) 6092 return InVec; 6093 6094 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 6095 // vector with the inserted element. 6096 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 6097 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 6098 SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(), 6099 InVec.getNode()->op_end()); 6100 if (Elt < Ops.size()) 6101 Ops[Elt] = InVal; 6102 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 6103 InVec.getValueType(), &Ops[0], Ops.size()); 6104 } 6105 // If the invec is an UNDEF and if EltNo is a constant, create a new 6106 // BUILD_VECTOR with undef elements and the inserted element. 6107 if (!LegalOperations && InVec.getOpcode() == ISD::UNDEF && 6108 isa<ConstantSDNode>(EltNo)) { 6109 EVT VT = InVec.getValueType(); 6110 EVT EltVT = VT.getVectorElementType(); 6111 unsigned NElts = VT.getVectorNumElements(); 6112 SmallVector<SDValue, 8> Ops(NElts, DAG.getUNDEF(EltVT)); 6113 6114 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 6115 if (Elt < Ops.size()) 6116 Ops[Elt] = InVal; 6117 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 6118 InVec.getValueType(), &Ops[0], Ops.size()); 6119 } 6120 return SDValue(); 6121} 6122 6123SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 6124 // (vextract (scalar_to_vector val, 0) -> val 6125 SDValue InVec = N->getOperand(0); 6126 6127 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 6128 // Check if the result type doesn't match the inserted element type. A 6129 // SCALAR_TO_VECTOR may truncate the inserted element and the 6130 // EXTRACT_VECTOR_ELT may widen the extracted vector. 6131 SDValue InOp = InVec.getOperand(0); 6132 EVT NVT = N->getValueType(0); 6133 if (InOp.getValueType() != NVT) { 6134 assert(InOp.getValueType().isInteger() && NVT.isInteger()); 6135 return DAG.getSExtOrTrunc(InOp, InVec.getDebugLoc(), NVT); 6136 } 6137 return InOp; 6138 } 6139 6140 // Perform only after legalization to ensure build_vector / vector_shuffle 6141 // optimizations have already been done. 6142 if (!LegalOperations) return SDValue(); 6143 6144 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 6145 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 6146 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 6147 SDValue EltNo = N->getOperand(1); 6148 6149 if (isa<ConstantSDNode>(EltNo)) { 6150 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 6151 bool NewLoad = false; 6152 bool BCNumEltsChanged = false; 6153 EVT VT = InVec.getValueType(); 6154 EVT ExtVT = VT.getVectorElementType(); 6155 EVT LVT = ExtVT; 6156 6157 if (InVec.getOpcode() == ISD::BIT_CONVERT) { 6158 EVT BCVT = InVec.getOperand(0).getValueType(); 6159 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType())) 6160 return SDValue(); 6161 if (VT.getVectorNumElements() != BCVT.getVectorNumElements()) 6162 BCNumEltsChanged = true; 6163 InVec = InVec.getOperand(0); 6164 ExtVT = BCVT.getVectorElementType(); 6165 NewLoad = true; 6166 } 6167 6168 LoadSDNode *LN0 = NULL; 6169 const ShuffleVectorSDNode *SVN = NULL; 6170 if (ISD::isNormalLoad(InVec.getNode())) { 6171 LN0 = cast<LoadSDNode>(InVec); 6172 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 6173 InVec.getOperand(0).getValueType() == ExtVT && 6174 ISD::isNormalLoad(InVec.getOperand(0).getNode())) { 6175 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 6176 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) { 6177 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 6178 // => 6179 // (load $addr+1*size) 6180 6181 // If the bit convert changed the number of elements, it is unsafe 6182 // to examine the mask. 6183 if (BCNumEltsChanged) 6184 return SDValue(); 6185 6186 // Select the input vector, guarding against out of range extract vector. 6187 unsigned NumElems = VT.getVectorNumElements(); 6188 int Idx = (Elt > NumElems) ? -1 : SVN->getMaskElt(Elt); 6189 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 6190 6191 if (InVec.getOpcode() == ISD::BIT_CONVERT) 6192 InVec = InVec.getOperand(0); 6193 if (ISD::isNormalLoad(InVec.getNode())) { 6194 LN0 = cast<LoadSDNode>(InVec); 6195 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems; 6196 } 6197 } 6198 6199 if (!LN0 || !LN0->hasOneUse() || LN0->isVolatile()) 6200 return SDValue(); 6201 6202 unsigned Align = LN0->getAlignment(); 6203 if (NewLoad) { 6204 // Check the resultant load doesn't need a higher alignment than the 6205 // original load. 6206 unsigned NewAlign = 6207 TLI.getTargetData()->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext())); 6208 6209 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT)) 6210 return SDValue(); 6211 6212 Align = NewAlign; 6213 } 6214 6215 SDValue NewPtr = LN0->getBasePtr(); 6216 unsigned PtrOff = 0; 6217 if (Elt) { 6218 PtrOff = LVT.getSizeInBits() * Elt / 8; 6219 EVT PtrType = NewPtr.getValueType(); 6220 if (TLI.isBigEndian()) 6221 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 6222 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr, 6223 DAG.getConstant(PtrOff, PtrType)); 6224 } 6225 6226 return DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr, 6227 LN0->getPointerInfo().getWithOffset(PtrOff), 6228 LN0->isVolatile(), LN0->isNonTemporal(), Align); 6229 } 6230 6231 return SDValue(); 6232} 6233 6234SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 6235 unsigned NumInScalars = N->getNumOperands(); 6236 EVT VT = N->getValueType(0); 6237 6238 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 6239 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 6240 // at most two distinct vectors, turn this into a shuffle node. 6241 SDValue VecIn1, VecIn2; 6242 for (unsigned i = 0; i != NumInScalars; ++i) { 6243 // Ignore undef inputs. 6244 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 6245 6246 // If this input is something other than a EXTRACT_VECTOR_ELT with a 6247 // constant index, bail out. 6248 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 6249 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 6250 VecIn1 = VecIn2 = SDValue(0, 0); 6251 break; 6252 } 6253 6254 // If the input vector type disagrees with the result of the build_vector, 6255 // we can't make a shuffle. 6256 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 6257 if (ExtractedFromVec.getValueType() != VT) { 6258 VecIn1 = VecIn2 = SDValue(0, 0); 6259 break; 6260 } 6261 6262 // Otherwise, remember this. We allow up to two distinct input vectors. 6263 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 6264 continue; 6265 6266 if (VecIn1.getNode() == 0) { 6267 VecIn1 = ExtractedFromVec; 6268 } else if (VecIn2.getNode() == 0) { 6269 VecIn2 = ExtractedFromVec; 6270 } else { 6271 // Too many inputs. 6272 VecIn1 = VecIn2 = SDValue(0, 0); 6273 break; 6274 } 6275 } 6276 6277 // If everything is good, we can make a shuffle operation. 6278 if (VecIn1.getNode()) { 6279 SmallVector<int, 8> Mask; 6280 for (unsigned i = 0; i != NumInScalars; ++i) { 6281 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 6282 Mask.push_back(-1); 6283 continue; 6284 } 6285 6286 // If extracting from the first vector, just use the index directly. 6287 SDValue Extract = N->getOperand(i); 6288 SDValue ExtVal = Extract.getOperand(1); 6289 if (Extract.getOperand(0) == VecIn1) { 6290 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 6291 if (ExtIndex > VT.getVectorNumElements()) 6292 return SDValue(); 6293 6294 Mask.push_back(ExtIndex); 6295 continue; 6296 } 6297 6298 // Otherwise, use InIdx + VecSize 6299 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 6300 Mask.push_back(Idx+NumInScalars); 6301 } 6302 6303 // Add count and size info. 6304 if (!isTypeLegal(VT)) 6305 return SDValue(); 6306 6307 // Return the new VECTOR_SHUFFLE node. 6308 SDValue Ops[2]; 6309 Ops[0] = VecIn1; 6310 Ops[1] = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT); 6311 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]); 6312 } 6313 6314 return SDValue(); 6315} 6316 6317SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 6318 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 6319 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 6320 // inputs come from at most two distinct vectors, turn this into a shuffle 6321 // node. 6322 6323 // If we only have one input vector, we don't need to do any concatenation. 6324 if (N->getNumOperands() == 1) 6325 return N->getOperand(0); 6326 6327 return SDValue(); 6328} 6329 6330SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 6331 EVT VT = N->getValueType(0); 6332 unsigned NumElts = VT.getVectorNumElements(); 6333 6334 SDValue N0 = N->getOperand(0); 6335 6336 assert(N0.getValueType().getVectorNumElements() == NumElts && 6337 "Vector shuffle must be normalized in DAG"); 6338 6339 // FIXME: implement canonicalizations from DAG.getVectorShuffle() 6340 6341 // If it is a splat, check if the argument vector is a build_vector with 6342 // all scalar elements the same. 6343 if (cast<ShuffleVectorSDNode>(N)->isSplat()) { 6344 SDNode *V = N0.getNode(); 6345 6346 // If this is a bit convert that changes the element type of the vector but 6347 // not the number of vector elements, look through it. Be careful not to 6348 // look though conversions that change things like v4f32 to v2f64. 6349 if (V->getOpcode() == ISD::BIT_CONVERT) { 6350 SDValue ConvInput = V->getOperand(0); 6351 if (ConvInput.getValueType().isVector() && 6352 ConvInput.getValueType().getVectorNumElements() == NumElts) 6353 V = ConvInput.getNode(); 6354 } 6355 6356 if (V->getOpcode() == ISD::BUILD_VECTOR) { 6357 unsigned NumElems = V->getNumOperands(); 6358 unsigned BaseIdx = cast<ShuffleVectorSDNode>(N)->getSplatIndex(); 6359 if (NumElems > BaseIdx) { 6360 SDValue Base; 6361 bool AllSame = true; 6362 for (unsigned i = 0; i != NumElems; ++i) { 6363 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 6364 Base = V->getOperand(i); 6365 break; 6366 } 6367 } 6368 // Splat of <u, u, u, u>, return <u, u, u, u> 6369 if (!Base.getNode()) 6370 return N0; 6371 for (unsigned i = 0; i != NumElems; ++i) { 6372 if (V->getOperand(i) != Base) { 6373 AllSame = false; 6374 break; 6375 } 6376 } 6377 // Splat of <x, x, x, x>, return <x, x, x, x> 6378 if (AllSame) 6379 return N0; 6380 } 6381 } 6382 } 6383 return SDValue(); 6384} 6385 6386SDValue DAGCombiner::visitMEMBARRIER(SDNode* N) { 6387 if (!TLI.getShouldFoldAtomicFences()) 6388 return SDValue(); 6389 6390 SDValue atomic = N->getOperand(0); 6391 switch (atomic.getOpcode()) { 6392 case ISD::ATOMIC_CMP_SWAP: 6393 case ISD::ATOMIC_SWAP: 6394 case ISD::ATOMIC_LOAD_ADD: 6395 case ISD::ATOMIC_LOAD_SUB: 6396 case ISD::ATOMIC_LOAD_AND: 6397 case ISD::ATOMIC_LOAD_OR: 6398 case ISD::ATOMIC_LOAD_XOR: 6399 case ISD::ATOMIC_LOAD_NAND: 6400 case ISD::ATOMIC_LOAD_MIN: 6401 case ISD::ATOMIC_LOAD_MAX: 6402 case ISD::ATOMIC_LOAD_UMIN: 6403 case ISD::ATOMIC_LOAD_UMAX: 6404 break; 6405 default: 6406 return SDValue(); 6407 } 6408 6409 SDValue fence = atomic.getOperand(0); 6410 if (fence.getOpcode() != ISD::MEMBARRIER) 6411 return SDValue(); 6412 6413 switch (atomic.getOpcode()) { 6414 case ISD::ATOMIC_CMP_SWAP: 6415 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(), 6416 fence.getOperand(0), 6417 atomic.getOperand(1), atomic.getOperand(2), 6418 atomic.getOperand(3)), atomic.getResNo()); 6419 case ISD::ATOMIC_SWAP: 6420 case ISD::ATOMIC_LOAD_ADD: 6421 case ISD::ATOMIC_LOAD_SUB: 6422 case ISD::ATOMIC_LOAD_AND: 6423 case ISD::ATOMIC_LOAD_OR: 6424 case ISD::ATOMIC_LOAD_XOR: 6425 case ISD::ATOMIC_LOAD_NAND: 6426 case ISD::ATOMIC_LOAD_MIN: 6427 case ISD::ATOMIC_LOAD_MAX: 6428 case ISD::ATOMIC_LOAD_UMIN: 6429 case ISD::ATOMIC_LOAD_UMAX: 6430 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(), 6431 fence.getOperand(0), 6432 atomic.getOperand(1), atomic.getOperand(2)), 6433 atomic.getResNo()); 6434 default: 6435 return SDValue(); 6436 } 6437} 6438 6439/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 6440/// an AND to a vector_shuffle with the destination vector and a zero vector. 6441/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 6442/// vector_shuffle V, Zero, <0, 4, 2, 4> 6443SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 6444 EVT VT = N->getValueType(0); 6445 DebugLoc dl = N->getDebugLoc(); 6446 SDValue LHS = N->getOperand(0); 6447 SDValue RHS = N->getOperand(1); 6448 if (N->getOpcode() == ISD::AND) { 6449 if (RHS.getOpcode() == ISD::BIT_CONVERT) 6450 RHS = RHS.getOperand(0); 6451 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 6452 SmallVector<int, 8> Indices; 6453 unsigned NumElts = RHS.getNumOperands(); 6454 for (unsigned i = 0; i != NumElts; ++i) { 6455 SDValue Elt = RHS.getOperand(i); 6456 if (!isa<ConstantSDNode>(Elt)) 6457 return SDValue(); 6458 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 6459 Indices.push_back(i); 6460 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 6461 Indices.push_back(NumElts); 6462 else 6463 return SDValue(); 6464 } 6465 6466 // Let's see if the target supports this vector_shuffle. 6467 EVT RVT = RHS.getValueType(); 6468 if (!TLI.isVectorClearMaskLegal(Indices, RVT)) 6469 return SDValue(); 6470 6471 // Return the new VECTOR_SHUFFLE node. 6472 EVT EltVT = RVT.getVectorElementType(); 6473 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(), 6474 DAG.getConstant(0, EltVT)); 6475 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 6476 RVT, &ZeroOps[0], ZeroOps.size()); 6477 LHS = DAG.getNode(ISD::BIT_CONVERT, dl, RVT, LHS); 6478 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]); 6479 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Shuf); 6480 } 6481 } 6482 6483 return SDValue(); 6484} 6485 6486/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 6487SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 6488 // After legalize, the target may be depending on adds and other 6489 // binary ops to provide legal ways to construct constants or other 6490 // things. Simplifying them may result in a loss of legality. 6491 if (LegalOperations) return SDValue(); 6492 6493 EVT VT = N->getValueType(0); 6494 assert(VT.isVector() && "SimplifyVBinOp only works on vectors!"); 6495 6496 EVT EltType = VT.getVectorElementType(); 6497 SDValue LHS = N->getOperand(0); 6498 SDValue RHS = N->getOperand(1); 6499 SDValue Shuffle = XformToShuffleWithZero(N); 6500 if (Shuffle.getNode()) return Shuffle; 6501 6502 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 6503 // this operation. 6504 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 6505 RHS.getOpcode() == ISD::BUILD_VECTOR) { 6506 SmallVector<SDValue, 8> Ops; 6507 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 6508 SDValue LHSOp = LHS.getOperand(i); 6509 SDValue RHSOp = RHS.getOperand(i); 6510 // If these two elements can't be folded, bail out. 6511 if ((LHSOp.getOpcode() != ISD::UNDEF && 6512 LHSOp.getOpcode() != ISD::Constant && 6513 LHSOp.getOpcode() != ISD::ConstantFP) || 6514 (RHSOp.getOpcode() != ISD::UNDEF && 6515 RHSOp.getOpcode() != ISD::Constant && 6516 RHSOp.getOpcode() != ISD::ConstantFP)) 6517 break; 6518 6519 // Can't fold divide by zero. 6520 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 6521 N->getOpcode() == ISD::FDIV) { 6522 if ((RHSOp.getOpcode() == ISD::Constant && 6523 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) || 6524 (RHSOp.getOpcode() == ISD::ConstantFP && 6525 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero())) 6526 break; 6527 } 6528 6529 // If the vector element type is not legal, the BUILD_VECTOR operands 6530 // are promoted and implicitly truncated. Make that explicit here. 6531 if (LHSOp.getValueType() != EltType) 6532 LHSOp = DAG.getNode(ISD::TRUNCATE, LHS.getDebugLoc(), EltType, LHSOp); 6533 if (RHSOp.getValueType() != EltType) 6534 RHSOp = DAG.getNode(ISD::TRUNCATE, RHS.getDebugLoc(), EltType, RHSOp); 6535 6536 SDValue FoldOp = DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), EltType, 6537 LHSOp, RHSOp); 6538 if (FoldOp.getOpcode() != ISD::UNDEF && 6539 FoldOp.getOpcode() != ISD::Constant && 6540 FoldOp.getOpcode() != ISD::ConstantFP) 6541 break; 6542 Ops.push_back(FoldOp); 6543 AddToWorkList(FoldOp.getNode()); 6544 } 6545 6546 if (Ops.size() == LHS.getNumOperands()) { 6547 EVT VT = LHS.getValueType(); 6548 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 6549 &Ops[0], Ops.size()); 6550 } 6551 } 6552 6553 return SDValue(); 6554} 6555 6556SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0, 6557 SDValue N1, SDValue N2){ 6558 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 6559 6560 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2, 6561 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 6562 6563 // If we got a simplified select_cc node back from SimplifySelectCC, then 6564 // break it down into a new SETCC node, and a new SELECT node, and then return 6565 // the SELECT node, since we were called with a SELECT node. 6566 if (SCC.getNode()) { 6567 // Check to see if we got a select_cc back (to turn into setcc/select). 6568 // Otherwise, just return whatever node we got back, like fabs. 6569 if (SCC.getOpcode() == ISD::SELECT_CC) { 6570 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(), 6571 N0.getValueType(), 6572 SCC.getOperand(0), SCC.getOperand(1), 6573 SCC.getOperand(4)); 6574 AddToWorkList(SETCC.getNode()); 6575 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(), 6576 SCC.getOperand(2), SCC.getOperand(3), SETCC); 6577 } 6578 6579 return SCC; 6580 } 6581 return SDValue(); 6582} 6583 6584/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 6585/// are the two values being selected between, see if we can simplify the 6586/// select. Callers of this should assume that TheSelect is deleted if this 6587/// returns true. As such, they should return the appropriate thing (e.g. the 6588/// node) back to the top-level of the DAG combiner loop to avoid it being 6589/// looked at. 6590bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 6591 SDValue RHS) { 6592 6593 // If this is a select from two identical things, try to pull the operation 6594 // through the select. 6595 if (LHS.getOpcode() != RHS.getOpcode() || 6596 !LHS.hasOneUse() || !RHS.hasOneUse()) 6597 return false; 6598 6599 // If this is a load and the token chain is identical, replace the select 6600 // of two loads with a load through a select of the address to load from. 6601 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 6602 // constants have been dropped into the constant pool. 6603 if (LHS.getOpcode() == ISD::LOAD) { 6604 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 6605 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 6606 6607 // Token chains must be identical. 6608 if (LHS.getOperand(0) != RHS.getOperand(0) || 6609 // Do not let this transformation reduce the number of volatile loads. 6610 LLD->isVolatile() || RLD->isVolatile() || 6611 // If this is an EXTLOAD, the VT's must match. 6612 LLD->getMemoryVT() != RLD->getMemoryVT() || 6613 // FIXME: this discards src value information. This is 6614 // over-conservative. It would be beneficial to be able to remember 6615 // both potential memory locations. Since we are discarding 6616 // src value info, don't do the transformation if the memory 6617 // locations are not in the default address space. 6618 LLD->getPointerInfo().getAddrSpace() != 0 || 6619 RLD->getPointerInfo().getAddrSpace() != 0) 6620 return false; 6621 6622 // Check that the select condition doesn't reach either load. If so, 6623 // folding this will induce a cycle into the DAG. If not, this is safe to 6624 // xform, so create a select of the addresses. 6625 SDValue Addr; 6626 if (TheSelect->getOpcode() == ISD::SELECT) { 6627 SDNode *CondNode = TheSelect->getOperand(0).getNode(); 6628 if ((LLD->hasAnyUseOfValue(1) && LLD->isPredecessorOf(CondNode)) || 6629 (RLD->hasAnyUseOfValue(1) && RLD->isPredecessorOf(CondNode))) 6630 return false; 6631 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(), 6632 LLD->getBasePtr().getValueType(), 6633 TheSelect->getOperand(0), LLD->getBasePtr(), 6634 RLD->getBasePtr()); 6635 } else { // Otherwise SELECT_CC 6636 SDNode *CondLHS = TheSelect->getOperand(0).getNode(); 6637 SDNode *CondRHS = TheSelect->getOperand(1).getNode(); 6638 6639 if ((LLD->hasAnyUseOfValue(1) && 6640 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))) || 6641 (LLD->hasAnyUseOfValue(1) && 6642 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS)))) 6643 return false; 6644 6645 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(), 6646 LLD->getBasePtr().getValueType(), 6647 TheSelect->getOperand(0), 6648 TheSelect->getOperand(1), 6649 LLD->getBasePtr(), RLD->getBasePtr(), 6650 TheSelect->getOperand(4)); 6651 } 6652 6653 SDValue Load; 6654 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) { 6655 Load = DAG.getLoad(TheSelect->getValueType(0), 6656 TheSelect->getDebugLoc(), 6657 // FIXME: Discards pointer info. 6658 LLD->getChain(), Addr, MachinePointerInfo(), 6659 LLD->isVolatile(), LLD->isNonTemporal(), 6660 LLD->getAlignment()); 6661 } else { 6662 Load = DAG.getExtLoad(LLD->getExtensionType(), 6663 TheSelect->getValueType(0), 6664 TheSelect->getDebugLoc(), 6665 // FIXME: Discards pointer info. 6666 LLD->getChain(), Addr, MachinePointerInfo(), 6667 LLD->getMemoryVT(), LLD->isVolatile(), 6668 LLD->isNonTemporal(), LLD->getAlignment()); 6669 } 6670 6671 // Users of the select now use the result of the load. 6672 CombineTo(TheSelect, Load); 6673 6674 // Users of the old loads now use the new load's chain. We know the 6675 // old-load value is dead now. 6676 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); 6677 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); 6678 return true; 6679 } 6680 6681 return false; 6682} 6683 6684/// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3 6685/// where 'cond' is the comparison specified by CC. 6686SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, 6687 SDValue N2, SDValue N3, 6688 ISD::CondCode CC, bool NotExtCompare) { 6689 // (x ? y : y) -> y. 6690 if (N2 == N3) return N2; 6691 6692 EVT VT = N2.getValueType(); 6693 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 6694 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 6695 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); 6696 6697 // Determine if the condition we're dealing with is constant 6698 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 6699 N0, N1, CC, DL, false); 6700 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 6701 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode()); 6702 6703 // fold select_cc true, x, y -> x 6704 if (SCCC && !SCCC->isNullValue()) 6705 return N2; 6706 // fold select_cc false, x, y -> y 6707 if (SCCC && SCCC->isNullValue()) 6708 return N3; 6709 6710 // Check to see if we can simplify the select into an fabs node 6711 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 6712 // Allow either -0.0 or 0.0 6713 if (CFP->getValueAPF().isZero()) { 6714 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 6715 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 6716 N0 == N2 && N3.getOpcode() == ISD::FNEG && 6717 N2 == N3.getOperand(0)) 6718 return DAG.getNode(ISD::FABS, DL, VT, N0); 6719 6720 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 6721 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 6722 N0 == N3 && N2.getOpcode() == ISD::FNEG && 6723 N2.getOperand(0) == N3) 6724 return DAG.getNode(ISD::FABS, DL, VT, N3); 6725 } 6726 } 6727 6728 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)" 6729 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0 6730 // in it. This is a win when the constant is not otherwise available because 6731 // it replaces two constant pool loads with one. We only do this if the FP 6732 // type is known to be legal, because if it isn't, then we are before legalize 6733 // types an we want the other legalization to happen first (e.g. to avoid 6734 // messing with soft float) and if the ConstantFP is not legal, because if 6735 // it is legal, we may not need to store the FP constant in a constant pool. 6736 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2)) 6737 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) { 6738 if (TLI.isTypeLegal(N2.getValueType()) && 6739 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) != 6740 TargetLowering::Legal) && 6741 // If both constants have multiple uses, then we won't need to do an 6742 // extra load, they are likely around in registers for other users. 6743 (TV->hasOneUse() || FV->hasOneUse())) { 6744 Constant *Elts[] = { 6745 const_cast<ConstantFP*>(FV->getConstantFPValue()), 6746 const_cast<ConstantFP*>(TV->getConstantFPValue()) 6747 }; 6748 const Type *FPTy = Elts[0]->getType(); 6749 const TargetData &TD = *TLI.getTargetData(); 6750 6751 // Create a ConstantArray of the two constants. 6752 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts, 2); 6753 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(), 6754 TD.getPrefTypeAlignment(FPTy)); 6755 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 6756 6757 // Get the offsets to the 0 and 1 element of the array so that we can 6758 // select between them. 6759 SDValue Zero = DAG.getIntPtrConstant(0); 6760 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType()); 6761 SDValue One = DAG.getIntPtrConstant(EltSize); 6762 6763 SDValue Cond = DAG.getSetCC(DL, 6764 TLI.getSetCCResultType(N0.getValueType()), 6765 N0, N1, CC); 6766 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(), 6767 Cond, One, Zero); 6768 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx, 6769 CstOffset); 6770 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx, 6771 MachinePointerInfo::getConstantPool(), false, 6772 false, Alignment); 6773 6774 } 6775 } 6776 6777 // Check to see if we can perform the "gzip trick", transforming 6778 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A) 6779 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 6780 N0.getValueType().isInteger() && 6781 N2.getValueType().isInteger() && 6782 (N1C->isNullValue() || // (a < 0) ? b : 0 6783 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 6784 EVT XType = N0.getValueType(); 6785 EVT AType = N2.getValueType(); 6786 if (XType.bitsGE(AType)) { 6787 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 6788 // single-bit constant. 6789 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 6790 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 6791 ShCtV = XType.getSizeInBits()-ShCtV-1; 6792 SDValue ShCt = DAG.getConstant(ShCtV, getShiftAmountTy()); 6793 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), 6794 XType, N0, ShCt); 6795 AddToWorkList(Shift.getNode()); 6796 6797 if (XType.bitsGT(AType)) { 6798 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 6799 AddToWorkList(Shift.getNode()); 6800 } 6801 6802 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 6803 } 6804 6805 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), 6806 XType, N0, 6807 DAG.getConstant(XType.getSizeInBits()-1, 6808 getShiftAmountTy())); 6809 AddToWorkList(Shift.getNode()); 6810 6811 if (XType.bitsGT(AType)) { 6812 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 6813 AddToWorkList(Shift.getNode()); 6814 } 6815 6816 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 6817 } 6818 } 6819 6820 // fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A) 6821 // where y is has a single bit set. 6822 // A plaintext description would be, we can turn the SELECT_CC into an AND 6823 // when the condition can be materialized as an all-ones register. Any 6824 // single bit-test can be materialized as an all-ones register with 6825 // shift-left and shift-right-arith. 6826 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND && 6827 N0->getValueType(0) == VT && 6828 N1C && N1C->isNullValue() && 6829 N2C && N2C->isNullValue()) { 6830 SDValue AndLHS = N0->getOperand(0); 6831 ConstantSDNode *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1)); 6832 if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) { 6833 // Shift the tested bit over the sign bit. 6834 APInt AndMask = ConstAndRHS->getAPIntValue(); 6835 SDValue ShlAmt = 6836 DAG.getConstant(AndMask.countLeadingZeros(), getShiftAmountTy()); 6837 SDValue Shl = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, AndLHS, ShlAmt); 6838 6839 // Now arithmetic right shift it all the way over, so the result is either 6840 // all-ones, or zero. 6841 SDValue ShrAmt = 6842 DAG.getConstant(AndMask.getBitWidth()-1, getShiftAmountTy()); 6843 SDValue Shr = DAG.getNode(ISD::SRA, N0.getDebugLoc(), VT, Shl, ShrAmt); 6844 6845 return DAG.getNode(ISD::AND, DL, VT, Shr, N3); 6846 } 6847 } 6848 6849 // fold select C, 16, 0 -> shl C, 4 6850 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 6851 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) { 6852 6853 // If the caller doesn't want us to simplify this into a zext of a compare, 6854 // don't do it. 6855 if (NotExtCompare && N2C->getAPIntValue() == 1) 6856 return SDValue(); 6857 6858 // Get a SetCC of the condition 6859 // FIXME: Should probably make sure that setcc is legal if we ever have a 6860 // target where it isn't. 6861 SDValue Temp, SCC; 6862 // cast from setcc result type to select result type 6863 if (LegalTypes) { 6864 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()), 6865 N0, N1, CC); 6866 if (N2.getValueType().bitsLT(SCC.getValueType())) 6867 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType()); 6868 else 6869 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 6870 N2.getValueType(), SCC); 6871 } else { 6872 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC); 6873 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 6874 N2.getValueType(), SCC); 6875 } 6876 6877 AddToWorkList(SCC.getNode()); 6878 AddToWorkList(Temp.getNode()); 6879 6880 if (N2C->getAPIntValue() == 1) 6881 return Temp; 6882 6883 // shl setcc result by log2 n2c 6884 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp, 6885 DAG.getConstant(N2C->getAPIntValue().logBase2(), 6886 getShiftAmountTy())); 6887 } 6888 6889 // Check to see if this is the equivalent of setcc 6890 // FIXME: Turn all of these into setcc if setcc if setcc is legal 6891 // otherwise, go ahead with the folds. 6892 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 6893 EVT XType = N0.getValueType(); 6894 if (!LegalOperations || 6895 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) { 6896 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC); 6897 if (Res.getValueType() != VT) 6898 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res); 6899 return Res; 6900 } 6901 6902 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X)))) 6903 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 6904 (!LegalOperations || 6905 TLI.isOperationLegal(ISD::CTLZ, XType))) { 6906 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0); 6907 return DAG.getNode(ISD::SRL, DL, XType, Ctlz, 6908 DAG.getConstant(Log2_32(XType.getSizeInBits()), 6909 getShiftAmountTy())); 6910 } 6911 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1)) 6912 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 6913 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(), 6914 XType, DAG.getConstant(0, XType), N0); 6915 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType); 6916 return DAG.getNode(ISD::SRL, DL, XType, 6917 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0), 6918 DAG.getConstant(XType.getSizeInBits()-1, 6919 getShiftAmountTy())); 6920 } 6921 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1)) 6922 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 6923 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0, 6924 DAG.getConstant(XType.getSizeInBits()-1, 6925 getShiftAmountTy())); 6926 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType)); 6927 } 6928 } 6929 6930 // Check to see if this is an integer abs. 6931 // select_cc setg[te] X, 0, X, -X -> 6932 // select_cc setgt X, -1, X, -X -> 6933 // select_cc setl[te] X, 0, -X, X -> 6934 // select_cc setlt X, 1, -X, X -> 6935 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 6936 if (N1C) { 6937 ConstantSDNode *SubC = NULL; 6938 if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) || 6939 (N1C->isAllOnesValue() && CC == ISD::SETGT)) && 6940 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) 6941 SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0)); 6942 else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) || 6943 (N1C->isOne() && CC == ISD::SETLT)) && 6944 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) 6945 SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0)); 6946 6947 EVT XType = N0.getValueType(); 6948 if (SubC && SubC->isNullValue() && XType.isInteger()) { 6949 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, 6950 N0, 6951 DAG.getConstant(XType.getSizeInBits()-1, 6952 getShiftAmountTy())); 6953 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), 6954 XType, N0, Shift); 6955 AddToWorkList(Shift.getNode()); 6956 AddToWorkList(Add.getNode()); 6957 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 6958 } 6959 } 6960 6961 return SDValue(); 6962} 6963 6964/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 6965SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0, 6966 SDValue N1, ISD::CondCode Cond, 6967 DebugLoc DL, bool foldBooleans) { 6968 TargetLowering::DAGCombinerInfo 6969 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 6970 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL); 6971} 6972 6973/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 6974/// return a DAG expression to select that will generate the same value by 6975/// multiplying by a magic number. See: 6976/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 6977SDValue DAGCombiner::BuildSDIV(SDNode *N) { 6978 std::vector<SDNode*> Built; 6979 SDValue S = TLI.BuildSDIV(N, DAG, &Built); 6980 6981 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 6982 ii != ee; ++ii) 6983 AddToWorkList(*ii); 6984 return S; 6985} 6986 6987/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 6988/// return a DAG expression to select that will generate the same value by 6989/// multiplying by a magic number. See: 6990/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 6991SDValue DAGCombiner::BuildUDIV(SDNode *N) { 6992 std::vector<SDNode*> Built; 6993 SDValue S = TLI.BuildUDIV(N, DAG, &Built); 6994 6995 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 6996 ii != ee; ++ii) 6997 AddToWorkList(*ii); 6998 return S; 6999} 7000 7001/// FindBaseOffset - Return true if base is a frame index, which is known not 7002// to alias with anything but itself. Provides base object and offset as results. 7003static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset, 7004 const GlobalValue *&GV, void *&CV) { 7005 // Assume it is a primitive operation. 7006 Base = Ptr; Offset = 0; GV = 0; CV = 0; 7007 7008 // If it's an adding a simple constant then integrate the offset. 7009 if (Base.getOpcode() == ISD::ADD) { 7010 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 7011 Base = Base.getOperand(0); 7012 Offset += C->getZExtValue(); 7013 } 7014 } 7015 7016 // Return the underlying GlobalValue, and update the Offset. Return false 7017 // for GlobalAddressSDNode since the same GlobalAddress may be represented 7018 // by multiple nodes with different offsets. 7019 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) { 7020 GV = G->getGlobal(); 7021 Offset += G->getOffset(); 7022 return false; 7023 } 7024 7025 // Return the underlying Constant value, and update the Offset. Return false 7026 // for ConstantSDNodes since the same constant pool entry may be represented 7027 // by multiple nodes with different offsets. 7028 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) { 7029 CV = C->isMachineConstantPoolEntry() ? (void *)C->getMachineCPVal() 7030 : (void *)C->getConstVal(); 7031 Offset += C->getOffset(); 7032 return false; 7033 } 7034 // If it's any of the following then it can't alias with anything but itself. 7035 return isa<FrameIndexSDNode>(Base); 7036} 7037 7038/// isAlias - Return true if there is any possibility that the two addresses 7039/// overlap. 7040bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, 7041 const Value *SrcValue1, int SrcValueOffset1, 7042 unsigned SrcValueAlign1, 7043 SDValue Ptr2, int64_t Size2, 7044 const Value *SrcValue2, int SrcValueOffset2, 7045 unsigned SrcValueAlign2) const { 7046 // If they are the same then they must be aliases. 7047 if (Ptr1 == Ptr2) return true; 7048 7049 // Gather base node and offset information. 7050 SDValue Base1, Base2; 7051 int64_t Offset1, Offset2; 7052 const GlobalValue *GV1, *GV2; 7053 void *CV1, *CV2; 7054 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1); 7055 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2); 7056 7057 // If they have a same base address then check to see if they overlap. 7058 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2))) 7059 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 7060 7061 // It is possible for different frame indices to alias each other, mostly 7062 // when tail call optimization reuses return address slots for arguments. 7063 // To catch this case, look up the actual index of frame indices to compute 7064 // the real alias relationship. 7065 if (isFrameIndex1 && isFrameIndex2) { 7066 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7067 Offset1 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base1)->getIndex()); 7068 Offset2 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base2)->getIndex()); 7069 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 7070 } 7071 7072 // Otherwise, if we know what the bases are, and they aren't identical, then 7073 // we know they cannot alias. 7074 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2)) 7075 return false; 7076 7077 // If we know required SrcValue1 and SrcValue2 have relatively large alignment 7078 // compared to the size and offset of the access, we may be able to prove they 7079 // do not alias. This check is conservative for now to catch cases created by 7080 // splitting vector types. 7081 if ((SrcValueAlign1 == SrcValueAlign2) && 7082 (SrcValueOffset1 != SrcValueOffset2) && 7083 (Size1 == Size2) && (SrcValueAlign1 > Size1)) { 7084 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1; 7085 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1; 7086 7087 // There is no overlap between these relatively aligned accesses of similar 7088 // size, return no alias. 7089 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1) 7090 return false; 7091 } 7092 7093 if (CombinerGlobalAA) { 7094 // Use alias analysis information. 7095 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 7096 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 7097 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 7098 AliasAnalysis::AliasResult AAResult = 7099 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2); 7100 if (AAResult == AliasAnalysis::NoAlias) 7101 return false; 7102 } 7103 7104 // Otherwise we have to assume they alias. 7105 return true; 7106} 7107 7108/// FindAliasInfo - Extracts the relevant alias information from the memory 7109/// node. Returns true if the operand was a load. 7110bool DAGCombiner::FindAliasInfo(SDNode *N, 7111 SDValue &Ptr, int64_t &Size, 7112 const Value *&SrcValue, 7113 int &SrcValueOffset, 7114 unsigned &SrcValueAlign) const { 7115 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 7116 Ptr = LD->getBasePtr(); 7117 Size = LD->getMemoryVT().getSizeInBits() >> 3; 7118 SrcValue = LD->getSrcValue(); 7119 SrcValueOffset = LD->getSrcValueOffset(); 7120 SrcValueAlign = LD->getOriginalAlignment(); 7121 return true; 7122 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 7123 Ptr = ST->getBasePtr(); 7124 Size = ST->getMemoryVT().getSizeInBits() >> 3; 7125 SrcValue = ST->getSrcValue(); 7126 SrcValueOffset = ST->getSrcValueOffset(); 7127 SrcValueAlign = ST->getOriginalAlignment(); 7128 } else { 7129 llvm_unreachable("FindAliasInfo expected a memory operand"); 7130 } 7131 7132 return false; 7133} 7134 7135/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 7136/// looking for aliasing nodes and adding them to the Aliases vector. 7137void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 7138 SmallVector<SDValue, 8> &Aliases) { 7139 SmallVector<SDValue, 8> Chains; // List of chains to visit. 7140 SmallPtrSet<SDNode *, 16> Visited; // Visited node set. 7141 7142 // Get alias information for node. 7143 SDValue Ptr; 7144 int64_t Size; 7145 const Value *SrcValue; 7146 int SrcValueOffset; 7147 unsigned SrcValueAlign; 7148 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset, 7149 SrcValueAlign); 7150 7151 // Starting off. 7152 Chains.push_back(OriginalChain); 7153 unsigned Depth = 0; 7154 7155 // Look at each chain and determine if it is an alias. If so, add it to the 7156 // aliases list. If not, then continue up the chain looking for the next 7157 // candidate. 7158 while (!Chains.empty()) { 7159 SDValue Chain = Chains.back(); 7160 Chains.pop_back(); 7161 7162 // For TokenFactor nodes, look at each operand and only continue up the 7163 // chain until we find two aliases. If we've seen two aliases, assume we'll 7164 // find more and revert to original chain since the xform is unlikely to be 7165 // profitable. 7166 // 7167 // FIXME: The depth check could be made to return the last non-aliasing 7168 // chain we found before we hit a tokenfactor rather than the original 7169 // chain. 7170 if (Depth > 6 || Aliases.size() == 2) { 7171 Aliases.clear(); 7172 Aliases.push_back(OriginalChain); 7173 break; 7174 } 7175 7176 // Don't bother if we've been before. 7177 if (!Visited.insert(Chain.getNode())) 7178 continue; 7179 7180 switch (Chain.getOpcode()) { 7181 case ISD::EntryToken: 7182 // Entry token is ideal chain operand, but handled in FindBetterChain. 7183 break; 7184 7185 case ISD::LOAD: 7186 case ISD::STORE: { 7187 // Get alias information for Chain. 7188 SDValue OpPtr; 7189 int64_t OpSize; 7190 const Value *OpSrcValue; 7191 int OpSrcValueOffset; 7192 unsigned OpSrcValueAlign; 7193 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, 7194 OpSrcValue, OpSrcValueOffset, 7195 OpSrcValueAlign); 7196 7197 // If chain is alias then stop here. 7198 if (!(IsLoad && IsOpLoad) && 7199 isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign, 7200 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset, 7201 OpSrcValueAlign)) { 7202 Aliases.push_back(Chain); 7203 } else { 7204 // Look further up the chain. 7205 Chains.push_back(Chain.getOperand(0)); 7206 ++Depth; 7207 } 7208 break; 7209 } 7210 7211 case ISD::TokenFactor: 7212 // We have to check each of the operands of the token factor for "small" 7213 // token factors, so we queue them up. Adding the operands to the queue 7214 // (stack) in reverse order maintains the original order and increases the 7215 // likelihood that getNode will find a matching token factor (CSE.) 7216 if (Chain.getNumOperands() > 16) { 7217 Aliases.push_back(Chain); 7218 break; 7219 } 7220 for (unsigned n = Chain.getNumOperands(); n;) 7221 Chains.push_back(Chain.getOperand(--n)); 7222 ++Depth; 7223 break; 7224 7225 default: 7226 // For all other instructions we will just have to take what we can get. 7227 Aliases.push_back(Chain); 7228 break; 7229 } 7230 } 7231} 7232 7233/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 7234/// for a better chain (aliasing node.) 7235SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 7236 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 7237 7238 // Accumulate all the aliases to this node. 7239 GatherAllAliases(N, OldChain, Aliases); 7240 7241 if (Aliases.size() == 0) { 7242 // If no operands then chain to entry token. 7243 return DAG.getEntryNode(); 7244 } else if (Aliases.size() == 1) { 7245 // If a single operand then chain to it. We don't need to revisit it. 7246 return Aliases[0]; 7247 } 7248 7249 // Construct a custom tailored token factor. 7250 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 7251 &Aliases[0], Aliases.size()); 7252} 7253 7254// SelectionDAG::Combine - This is the entry point for the file. 7255// 7256void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, 7257 CodeGenOpt::Level OptLevel) { 7258 /// run - This is the main entry point to this class. 7259 /// 7260 DAGCombiner(*this, AA, OptLevel).Run(Level); 7261} 7262