DAGCombiner.cpp revision e8b886aa842369e1e1d5ab25c16e05690adbaa33
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "dagcombine" 16#include "llvm/CodeGen/SelectionDAG.h" 17#include "llvm/Analysis/AliasAnalysis.h" 18#include "llvm/Target/TargetData.h" 19#include "llvm/Target/TargetLowering.h" 20#include "llvm/Target/TargetMachine.h" 21#include "llvm/Target/TargetOptions.h" 22#include "llvm/ADT/SmallPtrSet.h" 23#include "llvm/ADT/Statistic.h" 24#include "llvm/Support/Compiler.h" 25#include "llvm/Support/CommandLine.h" 26#include "llvm/Support/Debug.h" 27#include "llvm/Support/MathExtras.h" 28#include <algorithm> 29using namespace llvm; 30 31STATISTIC(NodesCombined , "Number of dag nodes combined"); 32STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 33STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 34 35namespace { 36#ifndef NDEBUG 37 static cl::opt<bool> 38 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 39 cl::desc("Pop up a window to show dags before the first " 40 "dag combine pass")); 41 static cl::opt<bool> 42 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 43 cl::desc("Pop up a window to show dags before the second " 44 "dag combine pass")); 45#else 46 static const bool ViewDAGCombine1 = false; 47 static const bool ViewDAGCombine2 = false; 48#endif 49 50 static cl::opt<bool> 51 CombinerAA("combiner-alias-analysis", cl::Hidden, 52 cl::desc("Turn on alias analysis during testing")); 53 54 static cl::opt<bool> 55 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 56 cl::desc("Include global information in alias analysis")); 57 58//------------------------------ DAGCombiner ---------------------------------// 59 60 class VISIBILITY_HIDDEN DAGCombiner { 61 SelectionDAG &DAG; 62 TargetLowering &TLI; 63 bool AfterLegalize; 64 65 // Worklist of all of the nodes that need to be simplified. 66 std::vector<SDNode*> WorkList; 67 68 // AA - Used for DAG load/store alias analysis. 69 AliasAnalysis &AA; 70 71 /// AddUsersToWorkList - When an instruction is simplified, add all users of 72 /// the instruction to the work lists because they might get more simplified 73 /// now. 74 /// 75 void AddUsersToWorkList(SDNode *N) { 76 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 77 UI != UE; ++UI) 78 AddToWorkList(*UI); 79 } 80 81 /// removeFromWorkList - remove all instances of N from the worklist. 82 /// 83 void removeFromWorkList(SDNode *N) { 84 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 85 WorkList.end()); 86 } 87 88 /// visit - call the node-specific routine that knows how to fold each 89 /// particular type of node. 90 SDOperand visit(SDNode *N); 91 92 public: 93 /// AddToWorkList - Add to the work list making sure it's instance is at the 94 /// the back (next to be processed.) 95 void AddToWorkList(SDNode *N) { 96 removeFromWorkList(N); 97 WorkList.push_back(N); 98 } 99 100 SDOperand CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo, 101 bool AddTo = true) { 102 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 103 ++NodesCombined; 104 DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG)); 105 DOUT << "\nWith: "; DEBUG(To[0].Val->dump(&DAG)); 106 DOUT << " and " << NumTo-1 << " other values\n"; 107 std::vector<SDNode*> NowDead; 108 DAG.ReplaceAllUsesWith(N, To, &NowDead); 109 110 if (AddTo) { 111 // Push the new nodes and any users onto the worklist 112 for (unsigned i = 0, e = NumTo; i != e; ++i) { 113 AddToWorkList(To[i].Val); 114 AddUsersToWorkList(To[i].Val); 115 } 116 } 117 118 // Nodes can be reintroduced into the worklist. Make sure we do not 119 // process a node that has been replaced. 120 removeFromWorkList(N); 121 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 122 removeFromWorkList(NowDead[i]); 123 124 // Finally, since the node is now dead, remove it from the graph. 125 DAG.DeleteNode(N); 126 return SDOperand(N, 0); 127 } 128 129 SDOperand CombineTo(SDNode *N, SDOperand Res, bool AddTo = true) { 130 return CombineTo(N, &Res, 1, AddTo); 131 } 132 133 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1, 134 bool AddTo = true) { 135 SDOperand To[] = { Res0, Res1 }; 136 return CombineTo(N, To, 2, AddTo); 137 } 138 private: 139 140 /// SimplifyDemandedBits - Check the specified integer node value to see if 141 /// it can be simplified or if things it uses can be simplified by bit 142 /// propagation. If so, return true. 143 bool SimplifyDemandedBits(SDOperand Op, uint64_t Demanded = ~0ULL) { 144 TargetLowering::TargetLoweringOpt TLO(DAG, AfterLegalize); 145 uint64_t KnownZero, KnownOne; 146 Demanded &= MVT::getIntVTBitMask(Op.getValueType()); 147 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 148 return false; 149 150 // Revisit the node. 151 AddToWorkList(Op.Val); 152 153 // Replace the old value with the new one. 154 ++NodesCombined; 155 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.Val->dump(&DAG)); 156 DOUT << "\nWith: "; DEBUG(TLO.New.Val->dump(&DAG)); 157 DOUT << '\n'; 158 159 std::vector<SDNode*> NowDead; 160 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &NowDead); 161 162 // Push the new node and any (possibly new) users onto the worklist. 163 AddToWorkList(TLO.New.Val); 164 AddUsersToWorkList(TLO.New.Val); 165 166 // Nodes can end up on the worklist more than once. Make sure we do 167 // not process a node that has been replaced. 168 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 169 removeFromWorkList(NowDead[i]); 170 171 // Finally, if the node is now dead, remove it from the graph. The node 172 // may not be dead if the replacement process recursively simplified to 173 // something else needing this node. 174 if (TLO.Old.Val->use_empty()) { 175 removeFromWorkList(TLO.Old.Val); 176 177 // If the operands of this node are only used by the node, they will now 178 // be dead. Make sure to visit them first to delete dead nodes early. 179 for (unsigned i = 0, e = TLO.Old.Val->getNumOperands(); i != e; ++i) 180 if (TLO.Old.Val->getOperand(i).Val->hasOneUse()) 181 AddToWorkList(TLO.Old.Val->getOperand(i).Val); 182 183 DAG.DeleteNode(TLO.Old.Val); 184 } 185 return true; 186 } 187 188 bool CombineToPreIndexedLoadStore(SDNode *N); 189 bool CombineToPostIndexedLoadStore(SDNode *N); 190 191 192 /// combine - call the node-specific routine that knows how to fold each 193 /// particular type of node. If that doesn't do anything, try the 194 /// target-specific DAG combines. 195 SDOperand combine(SDNode *N); 196 197 // Visitation implementation - Implement dag node combining for different 198 // node types. The semantics are as follows: 199 // Return Value: 200 // SDOperand.Val == 0 - No change was made 201 // SDOperand.Val == N - N was replaced, is dead, and is already handled. 202 // otherwise - N should be replaced by the returned Operand. 203 // 204 SDOperand visitTokenFactor(SDNode *N); 205 SDOperand visitADD(SDNode *N); 206 SDOperand visitSUB(SDNode *N); 207 SDOperand visitADDC(SDNode *N); 208 SDOperand visitADDE(SDNode *N); 209 SDOperand visitMUL(SDNode *N); 210 SDOperand visitSDIV(SDNode *N); 211 SDOperand visitUDIV(SDNode *N); 212 SDOperand visitSREM(SDNode *N); 213 SDOperand visitUREM(SDNode *N); 214 SDOperand visitMULHU(SDNode *N); 215 SDOperand visitMULHS(SDNode *N); 216 SDOperand visitSMUL_LOHI(SDNode *N); 217 SDOperand visitUMUL_LOHI(SDNode *N); 218 SDOperand visitSDIVREM(SDNode *N); 219 SDOperand visitUDIVREM(SDNode *N); 220 SDOperand visitAND(SDNode *N); 221 SDOperand visitOR(SDNode *N); 222 SDOperand visitXOR(SDNode *N); 223 SDOperand SimplifyVBinOp(SDNode *N); 224 SDOperand visitSHL(SDNode *N); 225 SDOperand visitSRA(SDNode *N); 226 SDOperand visitSRL(SDNode *N); 227 SDOperand visitCTLZ(SDNode *N); 228 SDOperand visitCTTZ(SDNode *N); 229 SDOperand visitCTPOP(SDNode *N); 230 SDOperand visitSELECT(SDNode *N); 231 SDOperand visitSELECT_CC(SDNode *N); 232 SDOperand visitSETCC(SDNode *N); 233 SDOperand visitSIGN_EXTEND(SDNode *N); 234 SDOperand visitZERO_EXTEND(SDNode *N); 235 SDOperand visitANY_EXTEND(SDNode *N); 236 SDOperand visitSIGN_EXTEND_INREG(SDNode *N); 237 SDOperand visitTRUNCATE(SDNode *N); 238 SDOperand visitBIT_CONVERT(SDNode *N); 239 SDOperand visitFADD(SDNode *N); 240 SDOperand visitFSUB(SDNode *N); 241 SDOperand visitFMUL(SDNode *N); 242 SDOperand visitFDIV(SDNode *N); 243 SDOperand visitFREM(SDNode *N); 244 SDOperand visitFCOPYSIGN(SDNode *N); 245 SDOperand visitSINT_TO_FP(SDNode *N); 246 SDOperand visitUINT_TO_FP(SDNode *N); 247 SDOperand visitFP_TO_SINT(SDNode *N); 248 SDOperand visitFP_TO_UINT(SDNode *N); 249 SDOperand visitFP_ROUND(SDNode *N); 250 SDOperand visitFP_ROUND_INREG(SDNode *N); 251 SDOperand visitFP_EXTEND(SDNode *N); 252 SDOperand visitFNEG(SDNode *N); 253 SDOperand visitFABS(SDNode *N); 254 SDOperand visitBRCOND(SDNode *N); 255 SDOperand visitBR_CC(SDNode *N); 256 SDOperand visitLOAD(SDNode *N); 257 SDOperand visitSTORE(SDNode *N); 258 SDOperand visitINSERT_VECTOR_ELT(SDNode *N); 259 SDOperand visitEXTRACT_VECTOR_ELT(SDNode *N); 260 SDOperand visitBUILD_VECTOR(SDNode *N); 261 SDOperand visitCONCAT_VECTORS(SDNode *N); 262 SDOperand visitVECTOR_SHUFFLE(SDNode *N); 263 264 SDOperand XformToShuffleWithZero(SDNode *N); 265 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS); 266 267 SDOperand visitShiftByConstant(SDNode *N, unsigned Amt); 268 269 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS); 270 SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N); 271 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2); 272 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2, 273 SDOperand N3, ISD::CondCode CC, 274 bool NotExtCompare = false); 275 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, 276 ISD::CondCode Cond, bool foldBooleans = true); 277 bool SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, unsigned HiOp); 278 SDOperand ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT::ValueType); 279 SDOperand BuildSDIV(SDNode *N); 280 SDOperand BuildUDIV(SDNode *N); 281 SDNode *MatchRotate(SDOperand LHS, SDOperand RHS); 282 SDOperand ReduceLoadWidth(SDNode *N); 283 284 SDOperand GetDemandedBits(SDOperand V, uint64_t Mask); 285 286 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 287 /// looking for aliasing nodes and adding them to the Aliases vector. 288 void GatherAllAliases(SDNode *N, SDOperand OriginalChain, 289 SmallVector<SDOperand, 8> &Aliases); 290 291 /// isAlias - Return true if there is any possibility that the two addresses 292 /// overlap. 293 bool isAlias(SDOperand Ptr1, int64_t Size1, 294 const Value *SrcValue1, int SrcValueOffset1, 295 SDOperand Ptr2, int64_t Size2, 296 const Value *SrcValue2, int SrcValueOffset2); 297 298 /// FindAliasInfo - Extracts the relevant alias information from the memory 299 /// node. Returns true if the operand was a load. 300 bool FindAliasInfo(SDNode *N, 301 SDOperand &Ptr, int64_t &Size, 302 const Value *&SrcValue, int &SrcValueOffset); 303 304 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 305 /// looking for a better chain (aliasing node.) 306 SDOperand FindBetterChain(SDNode *N, SDOperand Chain); 307 308public: 309 DAGCombiner(SelectionDAG &D, AliasAnalysis &A) 310 : DAG(D), 311 TLI(D.getTargetLoweringInfo()), 312 AfterLegalize(false), 313 AA(A) {} 314 315 /// Run - runs the dag combiner on all nodes in the work list 316 void Run(bool RunningAfterLegalize); 317 }; 318} 319 320//===----------------------------------------------------------------------===// 321// TargetLowering::DAGCombinerInfo implementation 322//===----------------------------------------------------------------------===// 323 324void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 325 ((DAGCombiner*)DC)->AddToWorkList(N); 326} 327 328SDOperand TargetLowering::DAGCombinerInfo:: 329CombineTo(SDNode *N, const std::vector<SDOperand> &To) { 330 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size()); 331} 332 333SDOperand TargetLowering::DAGCombinerInfo:: 334CombineTo(SDNode *N, SDOperand Res) { 335 return ((DAGCombiner*)DC)->CombineTo(N, Res); 336} 337 338 339SDOperand TargetLowering::DAGCombinerInfo:: 340CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) { 341 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1); 342} 343 344 345//===----------------------------------------------------------------------===// 346// Helper Functions 347//===----------------------------------------------------------------------===// 348 349/// isNegatibleForFree - Return 1 if we can compute the negated form of the 350/// specified expression for the same cost as the expression itself, or 2 if we 351/// can compute the negated form more cheaply than the expression itself. 352static char isNegatibleForFree(SDOperand Op, unsigned Depth = 0) { 353 // No compile time optimizations on this type. 354 if (Op.getValueType() == MVT::ppcf128) 355 return 0; 356 357 // fneg is removable even if it has multiple uses. 358 if (Op.getOpcode() == ISD::FNEG) return 2; 359 360 // Don't allow anything with multiple uses. 361 if (!Op.hasOneUse()) return 0; 362 363 // Don't recurse exponentially. 364 if (Depth > 6) return 0; 365 366 switch (Op.getOpcode()) { 367 default: return false; 368 case ISD::ConstantFP: 369 return 1; 370 case ISD::FADD: 371 // FIXME: determine better conditions for this xform. 372 if (!UnsafeFPMath) return 0; 373 374 // -(A+B) -> -A - B 375 if (char V = isNegatibleForFree(Op.getOperand(0), Depth+1)) 376 return V; 377 // -(A+B) -> -B - A 378 return isNegatibleForFree(Op.getOperand(1), Depth+1); 379 case ISD::FSUB: 380 // We can't turn -(A-B) into B-A when we honor signed zeros. 381 if (!UnsafeFPMath) return 0; 382 383 // -(A-B) -> B-A 384 return 1; 385 386 case ISD::FMUL: 387 case ISD::FDIV: 388 if (HonorSignDependentRoundingFPMath()) return 0; 389 390 // -(X*Y) -> (-X * Y) or (X*-Y) 391 if (char V = isNegatibleForFree(Op.getOperand(0), Depth+1)) 392 return V; 393 394 return isNegatibleForFree(Op.getOperand(1), Depth+1); 395 396 case ISD::FP_EXTEND: 397 case ISD::FP_ROUND: 398 case ISD::FSIN: 399 return isNegatibleForFree(Op.getOperand(0), Depth+1); 400 } 401} 402 403/// GetNegatedExpression - If isNegatibleForFree returns true, this function 404/// returns the newly negated expression. 405static SDOperand GetNegatedExpression(SDOperand Op, SelectionDAG &DAG, 406 unsigned Depth = 0) { 407 // fneg is removable even if it has multiple uses. 408 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 409 410 // Don't allow anything with multiple uses. 411 assert(Op.hasOneUse() && "Unknown reuse!"); 412 413 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 414 switch (Op.getOpcode()) { 415 default: assert(0 && "Unknown code"); 416 case ISD::ConstantFP: { 417 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 418 V.changeSign(); 419 return DAG.getConstantFP(V, Op.getValueType()); 420 } 421 case ISD::FADD: 422 // FIXME: determine better conditions for this xform. 423 assert(UnsafeFPMath); 424 425 // -(A+B) -> -A - B 426 if (isNegatibleForFree(Op.getOperand(0), Depth+1)) 427 return DAG.getNode(ISD::FSUB, Op.getValueType(), 428 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1), 429 Op.getOperand(1)); 430 // -(A+B) -> -B - A 431 return DAG.getNode(ISD::FSUB, Op.getValueType(), 432 GetNegatedExpression(Op.getOperand(1), DAG, Depth+1), 433 Op.getOperand(0)); 434 case ISD::FSUB: 435 // We can't turn -(A-B) into B-A when we honor signed zeros. 436 assert(UnsafeFPMath); 437 438 // -(0-B) -> B 439 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 440 if (N0CFP->getValueAPF().isZero()) 441 return Op.getOperand(1); 442 443 // -(A-B) -> B-A 444 return DAG.getNode(ISD::FSUB, Op.getValueType(), Op.getOperand(1), 445 Op.getOperand(0)); 446 447 case ISD::FMUL: 448 case ISD::FDIV: 449 assert(!HonorSignDependentRoundingFPMath()); 450 451 // -(X*Y) -> -X * Y 452 if (isNegatibleForFree(Op.getOperand(0), Depth+1)) 453 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 454 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1), 455 Op.getOperand(1)); 456 457 // -(X*Y) -> X * -Y 458 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 459 Op.getOperand(0), 460 GetNegatedExpression(Op.getOperand(1), DAG, Depth+1)); 461 462 case ISD::FP_EXTEND: 463 case ISD::FP_ROUND: 464 case ISD::FSIN: 465 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 466 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1)); 467 } 468} 469 470 471// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 472// that selects between the values 1 and 0, making it equivalent to a setcc. 473// Also, set the incoming LHS, RHS, and CC references to the appropriate 474// nodes based on the type of node we are checking. This simplifies life a 475// bit for the callers. 476static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS, 477 SDOperand &CC) { 478 if (N.getOpcode() == ISD::SETCC) { 479 LHS = N.getOperand(0); 480 RHS = N.getOperand(1); 481 CC = N.getOperand(2); 482 return true; 483 } 484 if (N.getOpcode() == ISD::SELECT_CC && 485 N.getOperand(2).getOpcode() == ISD::Constant && 486 N.getOperand(3).getOpcode() == ISD::Constant && 487 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 && 488 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 489 LHS = N.getOperand(0); 490 RHS = N.getOperand(1); 491 CC = N.getOperand(4); 492 return true; 493 } 494 return false; 495} 496 497// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 498// one use. If this is true, it allows the users to invert the operation for 499// free when it is profitable to do so. 500static bool isOneUseSetCC(SDOperand N) { 501 SDOperand N0, N1, N2; 502 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse()) 503 return true; 504 return false; 505} 506 507SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){ 508 MVT::ValueType VT = N0.getValueType(); 509 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 510 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 511 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 512 if (isa<ConstantSDNode>(N1)) { 513 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1); 514 AddToWorkList(OpNode.Val); 515 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0)); 516 } else if (N0.hasOneUse()) { 517 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1); 518 AddToWorkList(OpNode.Val); 519 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1)); 520 } 521 } 522 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 523 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 524 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 525 if (isa<ConstantSDNode>(N0)) { 526 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0); 527 AddToWorkList(OpNode.Val); 528 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0)); 529 } else if (N1.hasOneUse()) { 530 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0); 531 AddToWorkList(OpNode.Val); 532 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1)); 533 } 534 } 535 return SDOperand(); 536} 537 538//===----------------------------------------------------------------------===// 539// Main DAG Combiner implementation 540//===----------------------------------------------------------------------===// 541 542void DAGCombiner::Run(bool RunningAfterLegalize) { 543 // set the instance variable, so that the various visit routines may use it. 544 AfterLegalize = RunningAfterLegalize; 545 546 // Add all the dag nodes to the worklist. 547 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 548 E = DAG.allnodes_end(); I != E; ++I) 549 WorkList.push_back(I); 550 551 // Create a dummy node (which is not added to allnodes), that adds a reference 552 // to the root node, preventing it from being deleted, and tracking any 553 // changes of the root. 554 HandleSDNode Dummy(DAG.getRoot()); 555 556 // The root of the dag may dangle to deleted nodes until the dag combiner is 557 // done. Set it to null to avoid confusion. 558 DAG.setRoot(SDOperand()); 559 560 // while the worklist isn't empty, inspect the node on the end of it and 561 // try and combine it. 562 while (!WorkList.empty()) { 563 SDNode *N = WorkList.back(); 564 WorkList.pop_back(); 565 566 // If N has no uses, it is dead. Make sure to revisit all N's operands once 567 // N is deleted from the DAG, since they too may now be dead or may have a 568 // reduced number of uses, allowing other xforms. 569 if (N->use_empty() && N != &Dummy) { 570 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 571 AddToWorkList(N->getOperand(i).Val); 572 573 DAG.DeleteNode(N); 574 continue; 575 } 576 577 SDOperand RV = combine(N); 578 579 if (RV.Val) { 580 ++NodesCombined; 581 // If we get back the same node we passed in, rather than a new node or 582 // zero, we know that the node must have defined multiple values and 583 // CombineTo was used. Since CombineTo takes care of the worklist 584 // mechanics for us, we have no work to do in this case. 585 if (RV.Val != N) { 586 assert(N->getOpcode() != ISD::DELETED_NODE && 587 RV.Val->getOpcode() != ISD::DELETED_NODE && 588 "Node was deleted but visit returned new node!"); 589 590 DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG)); 591 DOUT << "\nWith: "; DEBUG(RV.Val->dump(&DAG)); 592 DOUT << '\n'; 593 std::vector<SDNode*> NowDead; 594 if (N->getNumValues() == RV.Val->getNumValues()) 595 DAG.ReplaceAllUsesWith(N, RV.Val, &NowDead); 596 else { 597 assert(N->getValueType(0) == RV.getValueType() && "Type mismatch"); 598 SDOperand OpV = RV; 599 DAG.ReplaceAllUsesWith(N, &OpV, &NowDead); 600 } 601 602 // Push the new node and any users onto the worklist 603 AddToWorkList(RV.Val); 604 AddUsersToWorkList(RV.Val); 605 606 // Nodes can be reintroduced into the worklist. Make sure we do not 607 // process a node that has been replaced. 608 removeFromWorkList(N); 609 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 610 removeFromWorkList(NowDead[i]); 611 612 // Finally, since the node is now dead, remove it from the graph. 613 DAG.DeleteNode(N); 614 } 615 } 616 } 617 618 // If the root changed (e.g. it was a dead load, update the root). 619 DAG.setRoot(Dummy.getValue()); 620} 621 622SDOperand DAGCombiner::visit(SDNode *N) { 623 switch(N->getOpcode()) { 624 default: break; 625 case ISD::TokenFactor: return visitTokenFactor(N); 626 case ISD::ADD: return visitADD(N); 627 case ISD::SUB: return visitSUB(N); 628 case ISD::ADDC: return visitADDC(N); 629 case ISD::ADDE: return visitADDE(N); 630 case ISD::MUL: return visitMUL(N); 631 case ISD::SDIV: return visitSDIV(N); 632 case ISD::UDIV: return visitUDIV(N); 633 case ISD::SREM: return visitSREM(N); 634 case ISD::UREM: return visitUREM(N); 635 case ISD::MULHU: return visitMULHU(N); 636 case ISD::MULHS: return visitMULHS(N); 637 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 638 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 639 case ISD::SDIVREM: return visitSDIVREM(N); 640 case ISD::UDIVREM: return visitUDIVREM(N); 641 case ISD::AND: return visitAND(N); 642 case ISD::OR: return visitOR(N); 643 case ISD::XOR: return visitXOR(N); 644 case ISD::SHL: return visitSHL(N); 645 case ISD::SRA: return visitSRA(N); 646 case ISD::SRL: return visitSRL(N); 647 case ISD::CTLZ: return visitCTLZ(N); 648 case ISD::CTTZ: return visitCTTZ(N); 649 case ISD::CTPOP: return visitCTPOP(N); 650 case ISD::SELECT: return visitSELECT(N); 651 case ISD::SELECT_CC: return visitSELECT_CC(N); 652 case ISD::SETCC: return visitSETCC(N); 653 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 654 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 655 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 656 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 657 case ISD::TRUNCATE: return visitTRUNCATE(N); 658 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 659 case ISD::FADD: return visitFADD(N); 660 case ISD::FSUB: return visitFSUB(N); 661 case ISD::FMUL: return visitFMUL(N); 662 case ISD::FDIV: return visitFDIV(N); 663 case ISD::FREM: return visitFREM(N); 664 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 665 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 666 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 667 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 668 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 669 case ISD::FP_ROUND: return visitFP_ROUND(N); 670 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 671 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 672 case ISD::FNEG: return visitFNEG(N); 673 case ISD::FABS: return visitFABS(N); 674 case ISD::BRCOND: return visitBRCOND(N); 675 case ISD::BR_CC: return visitBR_CC(N); 676 case ISD::LOAD: return visitLOAD(N); 677 case ISD::STORE: return visitSTORE(N); 678 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 679 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 680 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 681 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 682 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 683 } 684 return SDOperand(); 685} 686 687SDOperand DAGCombiner::combine(SDNode *N) { 688 689 SDOperand RV = visit(N); 690 691 // If nothing happened, try a target-specific DAG combine. 692 if (RV.Val == 0) { 693 assert(N->getOpcode() != ISD::DELETED_NODE && 694 "Node was deleted but visit returned NULL!"); 695 696 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 697 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 698 699 // Expose the DAG combiner to the target combiner impls. 700 TargetLowering::DAGCombinerInfo 701 DagCombineInfo(DAG, !AfterLegalize, false, this); 702 703 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 704 } 705 } 706 707 return RV; 708} 709 710/// getInputChainForNode - Given a node, return its input chain if it has one, 711/// otherwise return a null sd operand. 712static SDOperand getInputChainForNode(SDNode *N) { 713 if (unsigned NumOps = N->getNumOperands()) { 714 if (N->getOperand(0).getValueType() == MVT::Other) 715 return N->getOperand(0); 716 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 717 return N->getOperand(NumOps-1); 718 for (unsigned i = 1; i < NumOps-1; ++i) 719 if (N->getOperand(i).getValueType() == MVT::Other) 720 return N->getOperand(i); 721 } 722 return SDOperand(0, 0); 723} 724 725SDOperand DAGCombiner::visitTokenFactor(SDNode *N) { 726 // If N has two operands, where one has an input chain equal to the other, 727 // the 'other' chain is redundant. 728 if (N->getNumOperands() == 2) { 729 if (getInputChainForNode(N->getOperand(0).Val) == N->getOperand(1)) 730 return N->getOperand(0); 731 if (getInputChainForNode(N->getOperand(1).Val) == N->getOperand(0)) 732 return N->getOperand(1); 733 } 734 735 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 736 SmallVector<SDOperand, 8> Ops; // Ops for replacing token factor. 737 SmallPtrSet<SDNode*, 16> SeenOps; 738 bool Changed = false; // If we should replace this token factor. 739 740 // Start out with this token factor. 741 TFs.push_back(N); 742 743 // Iterate through token factors. The TFs grows when new token factors are 744 // encountered. 745 for (unsigned i = 0; i < TFs.size(); ++i) { 746 SDNode *TF = TFs[i]; 747 748 // Check each of the operands. 749 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 750 SDOperand Op = TF->getOperand(i); 751 752 switch (Op.getOpcode()) { 753 case ISD::EntryToken: 754 // Entry tokens don't need to be added to the list. They are 755 // rededundant. 756 Changed = true; 757 break; 758 759 case ISD::TokenFactor: 760 if ((CombinerAA || Op.hasOneUse()) && 761 std::find(TFs.begin(), TFs.end(), Op.Val) == TFs.end()) { 762 // Queue up for processing. 763 TFs.push_back(Op.Val); 764 // Clean up in case the token factor is removed. 765 AddToWorkList(Op.Val); 766 Changed = true; 767 break; 768 } 769 // Fall thru 770 771 default: 772 // Only add if it isn't already in the list. 773 if (SeenOps.insert(Op.Val)) 774 Ops.push_back(Op); 775 else 776 Changed = true; 777 break; 778 } 779 } 780 } 781 782 SDOperand Result; 783 784 // If we've change things around then replace token factor. 785 if (Changed) { 786 if (Ops.size() == 0) { 787 // The entry token is the only possible outcome. 788 Result = DAG.getEntryNode(); 789 } else { 790 // New and improved token factor. 791 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size()); 792 } 793 794 // Don't add users to work list. 795 return CombineTo(N, Result, false); 796 } 797 798 return Result; 799} 800 801static 802SDOperand combineShlAddConstant(SDOperand N0, SDOperand N1, SelectionDAG &DAG) { 803 MVT::ValueType VT = N0.getValueType(); 804 SDOperand N00 = N0.getOperand(0); 805 SDOperand N01 = N0.getOperand(1); 806 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 807 if (N01C && N00.getOpcode() == ISD::ADD && N00.Val->hasOneUse() && 808 isa<ConstantSDNode>(N00.getOperand(1))) { 809 N0 = DAG.getNode(ISD::ADD, VT, 810 DAG.getNode(ISD::SHL, VT, N00.getOperand(0), N01), 811 DAG.getNode(ISD::SHL, VT, N00.getOperand(1), N01)); 812 return DAG.getNode(ISD::ADD, VT, N0, N1); 813 } 814 return SDOperand(); 815} 816 817static 818SDOperand combineSelectAndUse(SDNode *N, SDOperand Slct, SDOperand OtherOp, 819 SelectionDAG &DAG) { 820 MVT::ValueType VT = N->getValueType(0); 821 unsigned Opc = N->getOpcode(); 822 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC; 823 SDOperand LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1); 824 SDOperand RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2); 825 ISD::CondCode CC = ISD::SETCC_INVALID; 826 if (isSlctCC) 827 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get(); 828 else { 829 SDOperand CCOp = Slct.getOperand(0); 830 if (CCOp.getOpcode() == ISD::SETCC) 831 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get(); 832 } 833 834 bool DoXform = false; 835 bool InvCC = false; 836 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) && 837 "Bad input!"); 838 if (LHS.getOpcode() == ISD::Constant && 839 cast<ConstantSDNode>(LHS)->isNullValue()) 840 DoXform = true; 841 else if (CC != ISD::SETCC_INVALID && 842 RHS.getOpcode() == ISD::Constant && 843 cast<ConstantSDNode>(RHS)->isNullValue()) { 844 std::swap(LHS, RHS); 845 bool isInt = MVT::isInteger(isSlctCC ? Slct.getOperand(0).getValueType() 846 : Slct.getOperand(0).getOperand(0).getValueType()); 847 CC = ISD::getSetCCInverse(CC, isInt); 848 DoXform = true; 849 InvCC = true; 850 } 851 852 if (DoXform) { 853 SDOperand Result = DAG.getNode(Opc, VT, OtherOp, RHS); 854 if (isSlctCC) 855 return DAG.getSelectCC(OtherOp, Result, 856 Slct.getOperand(0), Slct.getOperand(1), CC); 857 SDOperand CCOp = Slct.getOperand(0); 858 if (InvCC) 859 CCOp = DAG.getSetCC(CCOp.getValueType(), CCOp.getOperand(0), 860 CCOp.getOperand(1), CC); 861 return DAG.getNode(ISD::SELECT, VT, CCOp, OtherOp, Result); 862 } 863 return SDOperand(); 864} 865 866SDOperand DAGCombiner::visitADD(SDNode *N) { 867 SDOperand N0 = N->getOperand(0); 868 SDOperand N1 = N->getOperand(1); 869 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 870 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 871 MVT::ValueType VT = N0.getValueType(); 872 873 // fold vector ops 874 if (MVT::isVector(VT)) { 875 SDOperand FoldedVOp = SimplifyVBinOp(N); 876 if (FoldedVOp.Val) return FoldedVOp; 877 } 878 879 // fold (add x, undef) -> undef 880 if (N0.getOpcode() == ISD::UNDEF) 881 return N0; 882 if (N1.getOpcode() == ISD::UNDEF) 883 return N1; 884 // fold (add c1, c2) -> c1+c2 885 if (N0C && N1C) 886 return DAG.getNode(ISD::ADD, VT, N0, N1); 887 // canonicalize constant to RHS 888 if (N0C && !N1C) 889 return DAG.getNode(ISD::ADD, VT, N1, N0); 890 // fold (add x, 0) -> x 891 if (N1C && N1C->isNullValue()) 892 return N0; 893 // fold ((c1-A)+c2) -> (c1+c2)-A 894 if (N1C && N0.getOpcode() == ISD::SUB) 895 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 896 return DAG.getNode(ISD::SUB, VT, 897 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT), 898 N0.getOperand(1)); 899 // reassociate add 900 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1); 901 if (RADD.Val != 0) 902 return RADD; 903 // fold ((0-A) + B) -> B-A 904 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 905 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 906 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1)); 907 // fold (A + (0-B)) -> A-B 908 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 909 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 910 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1)); 911 // fold (A+(B-A)) -> B 912 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 913 return N1.getOperand(0); 914 915 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0))) 916 return SDOperand(N, 0); 917 918 // fold (a+b) -> (a|b) iff a and b share no bits. 919 if (MVT::isInteger(VT) && !MVT::isVector(VT)) { 920 uint64_t LHSZero, LHSOne; 921 uint64_t RHSZero, RHSOne; 922 uint64_t Mask = MVT::getIntVTBitMask(VT); 923 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 924 if (LHSZero) { 925 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 926 927 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 928 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 929 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 930 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 931 return DAG.getNode(ISD::OR, VT, N0, N1); 932 } 933 } 934 935 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 936 if (N0.getOpcode() == ISD::SHL && N0.Val->hasOneUse()) { 937 SDOperand Result = combineShlAddConstant(N0, N1, DAG); 938 if (Result.Val) return Result; 939 } 940 if (N1.getOpcode() == ISD::SHL && N1.Val->hasOneUse()) { 941 SDOperand Result = combineShlAddConstant(N1, N0, DAG); 942 if (Result.Val) return Result; 943 } 944 945 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c)) 946 if (N0.getOpcode() == ISD::SELECT && N0.Val->hasOneUse()) { 947 SDOperand Result = combineSelectAndUse(N, N0, N1, DAG); 948 if (Result.Val) return Result; 949 } 950 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) { 951 SDOperand Result = combineSelectAndUse(N, N1, N0, DAG); 952 if (Result.Val) return Result; 953 } 954 955 return SDOperand(); 956} 957 958SDOperand DAGCombiner::visitADDC(SDNode *N) { 959 SDOperand N0 = N->getOperand(0); 960 SDOperand N1 = N->getOperand(1); 961 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 962 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 963 MVT::ValueType VT = N0.getValueType(); 964 965 // If the flag result is dead, turn this into an ADD. 966 if (N->hasNUsesOfValue(0, 1)) 967 return CombineTo(N, DAG.getNode(ISD::ADD, VT, N1, N0), 968 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 969 970 // canonicalize constant to RHS. 971 if (N0C && !N1C) { 972 SDOperand Ops[] = { N1, N0 }; 973 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2); 974 } 975 976 // fold (addc x, 0) -> x + no carry out 977 if (N1C && N1C->isNullValue()) 978 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 979 980 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 981 uint64_t LHSZero, LHSOne; 982 uint64_t RHSZero, RHSOne; 983 uint64_t Mask = MVT::getIntVTBitMask(VT); 984 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 985 if (LHSZero) { 986 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 987 988 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 989 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 990 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 991 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 992 return CombineTo(N, DAG.getNode(ISD::OR, VT, N0, N1), 993 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 994 } 995 996 return SDOperand(); 997} 998 999SDOperand DAGCombiner::visitADDE(SDNode *N) { 1000 SDOperand N0 = N->getOperand(0); 1001 SDOperand N1 = N->getOperand(1); 1002 SDOperand CarryIn = N->getOperand(2); 1003 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1004 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1005 //MVT::ValueType VT = N0.getValueType(); 1006 1007 // canonicalize constant to RHS 1008 if (N0C && !N1C) { 1009 SDOperand Ops[] = { N1, N0, CarryIn }; 1010 return DAG.getNode(ISD::ADDE, N->getVTList(), Ops, 3); 1011 } 1012 1013 // fold (adde x, y, false) -> (addc x, y) 1014 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) { 1015 SDOperand Ops[] = { N1, N0 }; 1016 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2); 1017 } 1018 1019 return SDOperand(); 1020} 1021 1022 1023 1024SDOperand DAGCombiner::visitSUB(SDNode *N) { 1025 SDOperand N0 = N->getOperand(0); 1026 SDOperand N1 = N->getOperand(1); 1027 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1028 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1029 MVT::ValueType VT = N0.getValueType(); 1030 1031 // fold vector ops 1032 if (MVT::isVector(VT)) { 1033 SDOperand FoldedVOp = SimplifyVBinOp(N); 1034 if (FoldedVOp.Val) return FoldedVOp; 1035 } 1036 1037 // fold (sub x, x) -> 0 1038 if (N0 == N1) 1039 return DAG.getConstant(0, N->getValueType(0)); 1040 // fold (sub c1, c2) -> c1-c2 1041 if (N0C && N1C) 1042 return DAG.getNode(ISD::SUB, VT, N0, N1); 1043 // fold (sub x, c) -> (add x, -c) 1044 if (N1C) 1045 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT)); 1046 // fold (A+B)-A -> B 1047 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1048 return N0.getOperand(1); 1049 // fold (A+B)-B -> A 1050 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1051 return N0.getOperand(0); 1052 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c)) 1053 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) { 1054 SDOperand Result = combineSelectAndUse(N, N1, N0, DAG); 1055 if (Result.Val) return Result; 1056 } 1057 // If either operand of a sub is undef, the result is undef 1058 if (N0.getOpcode() == ISD::UNDEF) 1059 return N0; 1060 if (N1.getOpcode() == ISD::UNDEF) 1061 return N1; 1062 1063 return SDOperand(); 1064} 1065 1066SDOperand DAGCombiner::visitMUL(SDNode *N) { 1067 SDOperand N0 = N->getOperand(0); 1068 SDOperand N1 = N->getOperand(1); 1069 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1070 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1071 MVT::ValueType VT = N0.getValueType(); 1072 1073 // fold vector ops 1074 if (MVT::isVector(VT)) { 1075 SDOperand FoldedVOp = SimplifyVBinOp(N); 1076 if (FoldedVOp.Val) return FoldedVOp; 1077 } 1078 1079 // fold (mul x, undef) -> 0 1080 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1081 return DAG.getConstant(0, VT); 1082 // fold (mul c1, c2) -> c1*c2 1083 if (N0C && N1C) 1084 return DAG.getNode(ISD::MUL, VT, N0, N1); 1085 // canonicalize constant to RHS 1086 if (N0C && !N1C) 1087 return DAG.getNode(ISD::MUL, VT, N1, N0); 1088 // fold (mul x, 0) -> 0 1089 if (N1C && N1C->isNullValue()) 1090 return N1; 1091 // fold (mul x, -1) -> 0-x 1092 if (N1C && N1C->isAllOnesValue()) 1093 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 1094 // fold (mul x, (1 << c)) -> x << c 1095 if (N1C && isPowerOf2_64(N1C->getValue())) 1096 return DAG.getNode(ISD::SHL, VT, N0, 1097 DAG.getConstant(Log2_64(N1C->getValue()), 1098 TLI.getShiftAmountTy())); 1099 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1100 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) { 1101 // FIXME: If the input is something that is easily negated (e.g. a 1102 // single-use add), we should put the negate there. 1103 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), 1104 DAG.getNode(ISD::SHL, VT, N0, 1105 DAG.getConstant(Log2_64(-N1C->getSignExtended()), 1106 TLI.getShiftAmountTy()))); 1107 } 1108 1109 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1110 if (N1C && N0.getOpcode() == ISD::SHL && 1111 isa<ConstantSDNode>(N0.getOperand(1))) { 1112 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1)); 1113 AddToWorkList(C3.Val); 1114 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3); 1115 } 1116 1117 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1118 // use. 1119 { 1120 SDOperand Sh(0,0), Y(0,0); 1121 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1122 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1123 N0.Val->hasOneUse()) { 1124 Sh = N0; Y = N1; 1125 } else if (N1.getOpcode() == ISD::SHL && 1126 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) { 1127 Sh = N1; Y = N0; 1128 } 1129 if (Sh.Val) { 1130 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y); 1131 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1)); 1132 } 1133 } 1134 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1135 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() && 1136 isa<ConstantSDNode>(N0.getOperand(1))) { 1137 return DAG.getNode(ISD::ADD, VT, 1138 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1), 1139 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1)); 1140 } 1141 1142 // reassociate mul 1143 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1); 1144 if (RMUL.Val != 0) 1145 return RMUL; 1146 1147 return SDOperand(); 1148} 1149 1150SDOperand DAGCombiner::visitSDIV(SDNode *N) { 1151 SDOperand N0 = N->getOperand(0); 1152 SDOperand N1 = N->getOperand(1); 1153 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1154 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1155 MVT::ValueType VT = N->getValueType(0); 1156 1157 // fold vector ops 1158 if (MVT::isVector(VT)) { 1159 SDOperand FoldedVOp = SimplifyVBinOp(N); 1160 if (FoldedVOp.Val) return FoldedVOp; 1161 } 1162 1163 // fold (sdiv c1, c2) -> c1/c2 1164 if (N0C && N1C && !N1C->isNullValue()) 1165 return DAG.getNode(ISD::SDIV, VT, N0, N1); 1166 // fold (sdiv X, 1) -> X 1167 if (N1C && N1C->getSignExtended() == 1LL) 1168 return N0; 1169 // fold (sdiv X, -1) -> 0-X 1170 if (N1C && N1C->isAllOnesValue()) 1171 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 1172 // If we know the sign bits of both operands are zero, strength reduce to a 1173 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1174 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 1175 if (DAG.MaskedValueIsZero(N1, SignBit) && 1176 DAG.MaskedValueIsZero(N0, SignBit)) 1177 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1); 1178 // fold (sdiv X, pow2) -> simple ops after legalize 1179 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() && 1180 (isPowerOf2_64(N1C->getSignExtended()) || 1181 isPowerOf2_64(-N1C->getSignExtended()))) { 1182 // If dividing by powers of two is cheap, then don't perform the following 1183 // fold. 1184 if (TLI.isPow2DivCheap()) 1185 return SDOperand(); 1186 int64_t pow2 = N1C->getSignExtended(); 1187 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1188 unsigned lg2 = Log2_64(abs2); 1189 // Splat the sign bit into the register 1190 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0, 1191 DAG.getConstant(MVT::getSizeInBits(VT)-1, 1192 TLI.getShiftAmountTy())); 1193 AddToWorkList(SGN.Val); 1194 // Add (N0 < 0) ? abs2 - 1 : 0; 1195 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN, 1196 DAG.getConstant(MVT::getSizeInBits(VT)-lg2, 1197 TLI.getShiftAmountTy())); 1198 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL); 1199 AddToWorkList(SRL.Val); 1200 AddToWorkList(ADD.Val); // Divide by pow2 1201 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD, 1202 DAG.getConstant(lg2, TLI.getShiftAmountTy())); 1203 // If we're dividing by a positive value, we're done. Otherwise, we must 1204 // negate the result. 1205 if (pow2 > 0) 1206 return SRA; 1207 AddToWorkList(SRA.Val); 1208 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA); 1209 } 1210 // if integer divide is expensive and we satisfy the requirements, emit an 1211 // alternate sequence. 1212 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) && 1213 !TLI.isIntDivCheap()) { 1214 SDOperand Op = BuildSDIV(N); 1215 if (Op.Val) return Op; 1216 } 1217 1218 // undef / X -> 0 1219 if (N0.getOpcode() == ISD::UNDEF) 1220 return DAG.getConstant(0, VT); 1221 // X / undef -> undef 1222 if (N1.getOpcode() == ISD::UNDEF) 1223 return N1; 1224 1225 return SDOperand(); 1226} 1227 1228SDOperand DAGCombiner::visitUDIV(SDNode *N) { 1229 SDOperand N0 = N->getOperand(0); 1230 SDOperand N1 = N->getOperand(1); 1231 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1232 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1233 MVT::ValueType VT = N->getValueType(0); 1234 1235 // fold vector ops 1236 if (MVT::isVector(VT)) { 1237 SDOperand FoldedVOp = SimplifyVBinOp(N); 1238 if (FoldedVOp.Val) return FoldedVOp; 1239 } 1240 1241 // fold (udiv c1, c2) -> c1/c2 1242 if (N0C && N1C && !N1C->isNullValue()) 1243 return DAG.getNode(ISD::UDIV, VT, N0, N1); 1244 // fold (udiv x, (1 << c)) -> x >>u c 1245 if (N1C && isPowerOf2_64(N1C->getValue())) 1246 return DAG.getNode(ISD::SRL, VT, N0, 1247 DAG.getConstant(Log2_64(N1C->getValue()), 1248 TLI.getShiftAmountTy())); 1249 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1250 if (N1.getOpcode() == ISD::SHL) { 1251 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1252 if (isPowerOf2_64(SHC->getValue())) { 1253 MVT::ValueType ADDVT = N1.getOperand(1).getValueType(); 1254 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1), 1255 DAG.getConstant(Log2_64(SHC->getValue()), 1256 ADDVT)); 1257 AddToWorkList(Add.Val); 1258 return DAG.getNode(ISD::SRL, VT, N0, Add); 1259 } 1260 } 1261 } 1262 // fold (udiv x, c) -> alternate 1263 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) { 1264 SDOperand Op = BuildUDIV(N); 1265 if (Op.Val) return Op; 1266 } 1267 1268 // undef / X -> 0 1269 if (N0.getOpcode() == ISD::UNDEF) 1270 return DAG.getConstant(0, VT); 1271 // X / undef -> undef 1272 if (N1.getOpcode() == ISD::UNDEF) 1273 return N1; 1274 1275 return SDOperand(); 1276} 1277 1278SDOperand DAGCombiner::visitSREM(SDNode *N) { 1279 SDOperand N0 = N->getOperand(0); 1280 SDOperand N1 = N->getOperand(1); 1281 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1282 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1283 MVT::ValueType VT = N->getValueType(0); 1284 1285 // fold (srem c1, c2) -> c1%c2 1286 if (N0C && N1C && !N1C->isNullValue()) 1287 return DAG.getNode(ISD::SREM, VT, N0, N1); 1288 // If we know the sign bits of both operands are zero, strength reduce to a 1289 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1290 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 1291 if (DAG.MaskedValueIsZero(N1, SignBit) && 1292 DAG.MaskedValueIsZero(N0, SignBit)) 1293 return DAG.getNode(ISD::UREM, VT, N0, N1); 1294 1295 // If X/C can be simplified by the division-by-constant logic, lower 1296 // X%C to the equivalent of X-X/C*C. 1297 if (N1C && !N1C->isNullValue()) { 1298 SDOperand Div = DAG.getNode(ISD::SDIV, VT, N0, N1); 1299 SDOperand OptimizedDiv = combine(Div.Val); 1300 if (OptimizedDiv.Val && OptimizedDiv.Val != Div.Val) { 1301 SDOperand Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1); 1302 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1303 AddToWorkList(Mul.Val); 1304 return Sub; 1305 } 1306 } 1307 1308 // undef % X -> 0 1309 if (N0.getOpcode() == ISD::UNDEF) 1310 return DAG.getConstant(0, VT); 1311 // X % undef -> undef 1312 if (N1.getOpcode() == ISD::UNDEF) 1313 return N1; 1314 1315 return SDOperand(); 1316} 1317 1318SDOperand DAGCombiner::visitUREM(SDNode *N) { 1319 SDOperand N0 = N->getOperand(0); 1320 SDOperand N1 = N->getOperand(1); 1321 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1322 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1323 MVT::ValueType VT = N->getValueType(0); 1324 1325 // fold (urem c1, c2) -> c1%c2 1326 if (N0C && N1C && !N1C->isNullValue()) 1327 return DAG.getNode(ISD::UREM, VT, N0, N1); 1328 // fold (urem x, pow2) -> (and x, pow2-1) 1329 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue())) 1330 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT)); 1331 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1332 if (N1.getOpcode() == ISD::SHL) { 1333 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1334 if (isPowerOf2_64(SHC->getValue())) { 1335 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT)); 1336 AddToWorkList(Add.Val); 1337 return DAG.getNode(ISD::AND, VT, N0, Add); 1338 } 1339 } 1340 } 1341 1342 // If X/C can be simplified by the division-by-constant logic, lower 1343 // X%C to the equivalent of X-X/C*C. 1344 if (N1C && !N1C->isNullValue()) { 1345 SDOperand Div = DAG.getNode(ISD::UDIV, VT, N0, N1); 1346 SDOperand OptimizedDiv = combine(Div.Val); 1347 if (OptimizedDiv.Val && OptimizedDiv.Val != Div.Val) { 1348 SDOperand Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1); 1349 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1350 AddToWorkList(Mul.Val); 1351 return Sub; 1352 } 1353 } 1354 1355 // undef % X -> 0 1356 if (N0.getOpcode() == ISD::UNDEF) 1357 return DAG.getConstant(0, VT); 1358 // X % undef -> undef 1359 if (N1.getOpcode() == ISD::UNDEF) 1360 return N1; 1361 1362 return SDOperand(); 1363} 1364 1365SDOperand DAGCombiner::visitMULHS(SDNode *N) { 1366 SDOperand N0 = N->getOperand(0); 1367 SDOperand N1 = N->getOperand(1); 1368 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1369 MVT::ValueType VT = N->getValueType(0); 1370 1371 // fold (mulhs x, 0) -> 0 1372 if (N1C && N1C->isNullValue()) 1373 return N1; 1374 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1375 if (N1C && N1C->getValue() == 1) 1376 return DAG.getNode(ISD::SRA, N0.getValueType(), N0, 1377 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1, 1378 TLI.getShiftAmountTy())); 1379 // fold (mulhs x, undef) -> 0 1380 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1381 return DAG.getConstant(0, VT); 1382 1383 return SDOperand(); 1384} 1385 1386SDOperand DAGCombiner::visitMULHU(SDNode *N) { 1387 SDOperand N0 = N->getOperand(0); 1388 SDOperand N1 = N->getOperand(1); 1389 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1390 MVT::ValueType VT = N->getValueType(0); 1391 1392 // fold (mulhu x, 0) -> 0 1393 if (N1C && N1C->isNullValue()) 1394 return N1; 1395 // fold (mulhu x, 1) -> 0 1396 if (N1C && N1C->getValue() == 1) 1397 return DAG.getConstant(0, N0.getValueType()); 1398 // fold (mulhu x, undef) -> 0 1399 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1400 return DAG.getConstant(0, VT); 1401 1402 return SDOperand(); 1403} 1404 1405/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 1406/// compute two values. LoOp and HiOp give the opcodes for the two computations 1407/// that are being performed. Return true if a simplification was made. 1408/// 1409bool DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, 1410 unsigned LoOp, unsigned HiOp) { 1411 // If the high half is not needed, just compute the low half. 1412 bool HiExists = N->hasAnyUseOfValue(1); 1413 if (!HiExists && 1414 (!AfterLegalize || 1415 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 1416 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), 1417 DAG.getNode(LoOp, N->getValueType(0), 1418 N->op_begin(), 1419 N->getNumOperands())); 1420 return true; 1421 } 1422 1423 // If the low half is not needed, just compute the high half. 1424 bool LoExists = N->hasAnyUseOfValue(0); 1425 if (!LoExists && 1426 (!AfterLegalize || 1427 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 1428 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), 1429 DAG.getNode(HiOp, N->getValueType(1), 1430 N->op_begin(), 1431 N->getNumOperands())); 1432 return true; 1433 } 1434 1435 // If both halves are used, return as it is. 1436 if (LoExists && HiExists) 1437 return false; 1438 1439 // If the two computed results can be simplified separately, separate them. 1440 bool RetVal = false; 1441 if (LoExists) { 1442 SDOperand Lo = DAG.getNode(LoOp, N->getValueType(0), 1443 N->op_begin(), N->getNumOperands()); 1444 SDOperand LoOpt = combine(Lo.Val); 1445 if (LoOpt.Val && LoOpt != Lo && 1446 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())) { 1447 RetVal = true; 1448 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), LoOpt); 1449 } else 1450 DAG.DeleteNode(Lo.Val); 1451 } 1452 1453 if (HiExists) { 1454 SDOperand Hi = DAG.getNode(HiOp, N->getValueType(1), 1455 N->op_begin(), N->getNumOperands()); 1456 SDOperand HiOpt = combine(Hi.Val); 1457 if (HiOpt.Val && HiOpt != Hi && 1458 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())) { 1459 RetVal = true; 1460 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), HiOpt); 1461 } else 1462 DAG.DeleteNode(Hi.Val); 1463 } 1464 1465 return RetVal; 1466} 1467 1468SDOperand DAGCombiner::visitSMUL_LOHI(SDNode *N) { 1469 1470 if (SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS)) 1471 return SDOperand(); 1472 1473 return SDOperand(); 1474} 1475 1476SDOperand DAGCombiner::visitUMUL_LOHI(SDNode *N) { 1477 1478 if (SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU)) 1479 return SDOperand(); 1480 1481 return SDOperand(); 1482} 1483 1484SDOperand DAGCombiner::visitSDIVREM(SDNode *N) { 1485 1486 if (SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM)) 1487 return SDOperand(); 1488 1489 return SDOperand(); 1490} 1491 1492SDOperand DAGCombiner::visitUDIVREM(SDNode *N) { 1493 1494 if (SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM)) 1495 return SDOperand(); 1496 1497 return SDOperand(); 1498} 1499 1500/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 1501/// two operands of the same opcode, try to simplify it. 1502SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 1503 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1); 1504 MVT::ValueType VT = N0.getValueType(); 1505 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 1506 1507 // For each of OP in AND/OR/XOR: 1508 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 1509 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 1510 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 1511 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) 1512 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND|| 1513 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) && 1514 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1515 SDOperand ORNode = DAG.getNode(N->getOpcode(), 1516 N0.getOperand(0).getValueType(), 1517 N0.getOperand(0), N1.getOperand(0)); 1518 AddToWorkList(ORNode.Val); 1519 return DAG.getNode(N0.getOpcode(), VT, ORNode); 1520 } 1521 1522 // For each of OP in SHL/SRL/SRA/AND... 1523 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 1524 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 1525 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 1526 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 1527 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 1528 N0.getOperand(1) == N1.getOperand(1)) { 1529 SDOperand ORNode = DAG.getNode(N->getOpcode(), 1530 N0.getOperand(0).getValueType(), 1531 N0.getOperand(0), N1.getOperand(0)); 1532 AddToWorkList(ORNode.Val); 1533 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1)); 1534 } 1535 1536 return SDOperand(); 1537} 1538 1539SDOperand DAGCombiner::visitAND(SDNode *N) { 1540 SDOperand N0 = N->getOperand(0); 1541 SDOperand N1 = N->getOperand(1); 1542 SDOperand LL, LR, RL, RR, CC0, CC1; 1543 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1544 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1545 MVT::ValueType VT = N1.getValueType(); 1546 1547 // fold vector ops 1548 if (MVT::isVector(VT)) { 1549 SDOperand FoldedVOp = SimplifyVBinOp(N); 1550 if (FoldedVOp.Val) return FoldedVOp; 1551 } 1552 1553 // fold (and x, undef) -> 0 1554 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1555 return DAG.getConstant(0, VT); 1556 // fold (and c1, c2) -> c1&c2 1557 if (N0C && N1C) 1558 return DAG.getNode(ISD::AND, VT, N0, N1); 1559 // canonicalize constant to RHS 1560 if (N0C && !N1C) 1561 return DAG.getNode(ISD::AND, VT, N1, N0); 1562 // fold (and x, -1) -> x 1563 if (N1C && N1C->isAllOnesValue()) 1564 return N0; 1565 // if (and x, c) is known to be zero, return 0 1566 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) 1567 return DAG.getConstant(0, VT); 1568 // reassociate and 1569 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1); 1570 if (RAND.Val != 0) 1571 return RAND; 1572 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 1573 if (N1C && N0.getOpcode() == ISD::OR) 1574 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1575 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue()) 1576 return N1; 1577 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 1578 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1579 unsigned InMask = MVT::getIntVTBitMask(N0.getOperand(0).getValueType()); 1580 if (DAG.MaskedValueIsZero(N0.getOperand(0), 1581 ~N1C->getValue() & InMask)) { 1582 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(), 1583 N0.getOperand(0)); 1584 1585 // Replace uses of the AND with uses of the Zero extend node. 1586 CombineTo(N, Zext); 1587 1588 // We actually want to replace all uses of the any_extend with the 1589 // zero_extend, to avoid duplicating things. This will later cause this 1590 // AND to be folded. 1591 CombineTo(N0.Val, Zext); 1592 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1593 } 1594 } 1595 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 1596 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1597 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1598 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1599 1600 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1601 MVT::isInteger(LL.getValueType())) { 1602 // fold (X == 0) & (Y == 0) -> (X|Y == 0) 1603 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) { 1604 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1605 AddToWorkList(ORNode.Val); 1606 return DAG.getSetCC(VT, ORNode, LR, Op1); 1607 } 1608 // fold (X == -1) & (Y == -1) -> (X&Y == -1) 1609 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 1610 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1611 AddToWorkList(ANDNode.Val); 1612 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1613 } 1614 // fold (X > -1) & (Y > -1) -> (X|Y > -1) 1615 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1616 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1617 AddToWorkList(ORNode.Val); 1618 return DAG.getSetCC(VT, ORNode, LR, Op1); 1619 } 1620 } 1621 // canonicalize equivalent to ll == rl 1622 if (LL == RR && LR == RL) { 1623 Op1 = ISD::getSetCCSwappedOperands(Op1); 1624 std::swap(RL, RR); 1625 } 1626 if (LL == RL && LR == RR) { 1627 bool isInteger = MVT::isInteger(LL.getValueType()); 1628 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1629 if (Result != ISD::SETCC_INVALID) 1630 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1631 } 1632 } 1633 1634 // Simplify: and (op x...), (op y...) -> (op (and x, y)) 1635 if (N0.getOpcode() == N1.getOpcode()) { 1636 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1637 if (Tmp.Val) return Tmp; 1638 } 1639 1640 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1641 // fold (and (sra)) -> (and (srl)) when possible. 1642 if (!MVT::isVector(VT) && 1643 SimplifyDemandedBits(SDOperand(N, 0))) 1644 return SDOperand(N, 0); 1645 // fold (zext_inreg (extload x)) -> (zextload x) 1646 if (ISD::isEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val)) { 1647 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1648 MVT::ValueType EVT = LN0->getLoadedVT(); 1649 // If we zero all the possible extended bits, then we can turn this into 1650 // a zextload if we are running before legalize or the operation is legal. 1651 if (DAG.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && 1652 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1653 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1654 LN0->getBasePtr(), LN0->getSrcValue(), 1655 LN0->getSrcValueOffset(), EVT, 1656 LN0->isVolatile(), 1657 LN0->getAlignment()); 1658 AddToWorkList(N); 1659 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1660 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1661 } 1662 } 1663 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1664 if (ISD::isSEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 1665 N0.hasOneUse()) { 1666 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1667 MVT::ValueType EVT = LN0->getLoadedVT(); 1668 // If we zero all the possible extended bits, then we can turn this into 1669 // a zextload if we are running before legalize or the operation is legal. 1670 if (DAG.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && 1671 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1672 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1673 LN0->getBasePtr(), LN0->getSrcValue(), 1674 LN0->getSrcValueOffset(), EVT, 1675 LN0->isVolatile(), 1676 LN0->getAlignment()); 1677 AddToWorkList(N); 1678 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1679 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1680 } 1681 } 1682 1683 // fold (and (load x), 255) -> (zextload x, i8) 1684 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1685 if (N1C && N0.getOpcode() == ISD::LOAD) { 1686 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1687 if (LN0->getExtensionType() != ISD::SEXTLOAD && 1688 LN0->getAddressingMode() == ISD::UNINDEXED && 1689 N0.hasOneUse()) { 1690 MVT::ValueType EVT, LoadedVT; 1691 if (N1C->getValue() == 255) 1692 EVT = MVT::i8; 1693 else if (N1C->getValue() == 65535) 1694 EVT = MVT::i16; 1695 else if (N1C->getValue() == ~0U) 1696 EVT = MVT::i32; 1697 else 1698 EVT = MVT::Other; 1699 1700 LoadedVT = LN0->getLoadedVT(); 1701 if (EVT != MVT::Other && LoadedVT > EVT && 1702 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1703 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 1704 // For big endian targets, we need to add an offset to the pointer to 1705 // load the correct bytes. For little endian systems, we merely need to 1706 // read fewer bytes from the same pointer. 1707 unsigned LVTStoreBytes = MVT::getStoreSizeInBits(LoadedVT)/8; 1708 unsigned EVTStoreBytes = MVT::getStoreSizeInBits(EVT)/8; 1709 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 1710 unsigned Alignment = LN0->getAlignment(); 1711 SDOperand NewPtr = LN0->getBasePtr(); 1712 if (!TLI.isLittleEndian()) { 1713 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, 1714 DAG.getConstant(PtrOff, PtrType)); 1715 Alignment = MinAlign(Alignment, PtrOff); 1716 } 1717 AddToWorkList(NewPtr.Val); 1718 SDOperand Load = 1719 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr, 1720 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT, 1721 LN0->isVolatile(), Alignment); 1722 AddToWorkList(N); 1723 CombineTo(N0.Val, Load, Load.getValue(1)); 1724 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1725 } 1726 } 1727 } 1728 1729 return SDOperand(); 1730} 1731 1732SDOperand DAGCombiner::visitOR(SDNode *N) { 1733 SDOperand N0 = N->getOperand(0); 1734 SDOperand N1 = N->getOperand(1); 1735 SDOperand LL, LR, RL, RR, CC0, CC1; 1736 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1737 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1738 MVT::ValueType VT = N1.getValueType(); 1739 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1740 1741 // fold vector ops 1742 if (MVT::isVector(VT)) { 1743 SDOperand FoldedVOp = SimplifyVBinOp(N); 1744 if (FoldedVOp.Val) return FoldedVOp; 1745 } 1746 1747 // fold (or x, undef) -> -1 1748 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1749 return DAG.getConstant(~0ULL, VT); 1750 // fold (or c1, c2) -> c1|c2 1751 if (N0C && N1C) 1752 return DAG.getNode(ISD::OR, VT, N0, N1); 1753 // canonicalize constant to RHS 1754 if (N0C && !N1C) 1755 return DAG.getNode(ISD::OR, VT, N1, N0); 1756 // fold (or x, 0) -> x 1757 if (N1C && N1C->isNullValue()) 1758 return N0; 1759 // fold (or x, -1) -> -1 1760 if (N1C && N1C->isAllOnesValue()) 1761 return N1; 1762 // fold (or x, c) -> c iff (x & ~c) == 0 1763 if (N1C && 1764 DAG.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)))) 1765 return N1; 1766 // reassociate or 1767 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1); 1768 if (ROR.Val != 0) 1769 return ROR; 1770 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 1771 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() && 1772 isa<ConstantSDNode>(N0.getOperand(1))) { 1773 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 1774 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0), 1775 N1), 1776 DAG.getConstant(N1C->getValue() | C1->getValue(), VT)); 1777 } 1778 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 1779 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1780 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1781 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1782 1783 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1784 MVT::isInteger(LL.getValueType())) { 1785 // fold (X != 0) | (Y != 0) -> (X|Y != 0) 1786 // fold (X < 0) | (Y < 0) -> (X|Y < 0) 1787 if (cast<ConstantSDNode>(LR)->getValue() == 0 && 1788 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 1789 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1790 AddToWorkList(ORNode.Val); 1791 return DAG.getSetCC(VT, ORNode, LR, Op1); 1792 } 1793 // fold (X != -1) | (Y != -1) -> (X&Y != -1) 1794 // fold (X > -1) | (Y > -1) -> (X&Y > -1) 1795 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 1796 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 1797 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1798 AddToWorkList(ANDNode.Val); 1799 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1800 } 1801 } 1802 // canonicalize equivalent to ll == rl 1803 if (LL == RR && LR == RL) { 1804 Op1 = ISD::getSetCCSwappedOperands(Op1); 1805 std::swap(RL, RR); 1806 } 1807 if (LL == RL && LR == RR) { 1808 bool isInteger = MVT::isInteger(LL.getValueType()); 1809 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 1810 if (Result != ISD::SETCC_INVALID) 1811 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1812 } 1813 } 1814 1815 // Simplify: or (op x...), (op y...) -> (op (or x, y)) 1816 if (N0.getOpcode() == N1.getOpcode()) { 1817 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1818 if (Tmp.Val) return Tmp; 1819 } 1820 1821 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible. 1822 if (N0.getOpcode() == ISD::AND && 1823 N1.getOpcode() == ISD::AND && 1824 N0.getOperand(1).getOpcode() == ISD::Constant && 1825 N1.getOperand(1).getOpcode() == ISD::Constant && 1826 // Don't increase # computations. 1827 (N0.Val->hasOneUse() || N1.Val->hasOneUse())) { 1828 // We can only do this xform if we know that bits from X that are set in C2 1829 // but not in C1 are already zero. Likewise for Y. 1830 uint64_t LHSMask = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1831 uint64_t RHSMask = cast<ConstantSDNode>(N1.getOperand(1))->getValue(); 1832 1833 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 1834 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 1835 SDOperand X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0)); 1836 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT)); 1837 } 1838 } 1839 1840 1841 // See if this is some rotate idiom. 1842 if (SDNode *Rot = MatchRotate(N0, N1)) 1843 return SDOperand(Rot, 0); 1844 1845 return SDOperand(); 1846} 1847 1848 1849/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 1850static bool MatchRotateHalf(SDOperand Op, SDOperand &Shift, SDOperand &Mask) { 1851 if (Op.getOpcode() == ISD::AND) { 1852 if (isa<ConstantSDNode>(Op.getOperand(1))) { 1853 Mask = Op.getOperand(1); 1854 Op = Op.getOperand(0); 1855 } else { 1856 return false; 1857 } 1858 } 1859 1860 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 1861 Shift = Op; 1862 return true; 1863 } 1864 return false; 1865} 1866 1867 1868// MatchRotate - Handle an 'or' of two operands. If this is one of the many 1869// idioms for rotate, and if the target supports rotation instructions, generate 1870// a rot[lr]. 1871SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) { 1872 // Must be a legal type. Expanded an promoted things won't work with rotates. 1873 MVT::ValueType VT = LHS.getValueType(); 1874 if (!TLI.isTypeLegal(VT)) return 0; 1875 1876 // The target must have at least one rotate flavor. 1877 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT); 1878 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT); 1879 if (!HasROTL && !HasROTR) return 0; 1880 1881 // Match "(X shl/srl V1) & V2" where V2 may not be present. 1882 SDOperand LHSShift; // The shift. 1883 SDOperand LHSMask; // AND value if any. 1884 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 1885 return 0; // Not part of a rotate. 1886 1887 SDOperand RHSShift; // The shift. 1888 SDOperand RHSMask; // AND value if any. 1889 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 1890 return 0; // Not part of a rotate. 1891 1892 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 1893 return 0; // Not shifting the same value. 1894 1895 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 1896 return 0; // Shifts must disagree. 1897 1898 // Canonicalize shl to left side in a shl/srl pair. 1899 if (RHSShift.getOpcode() == ISD::SHL) { 1900 std::swap(LHS, RHS); 1901 std::swap(LHSShift, RHSShift); 1902 std::swap(LHSMask , RHSMask ); 1903 } 1904 1905 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1906 SDOperand LHSShiftArg = LHSShift.getOperand(0); 1907 SDOperand LHSShiftAmt = LHSShift.getOperand(1); 1908 SDOperand RHSShiftAmt = RHSShift.getOperand(1); 1909 1910 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 1911 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 1912 if (LHSShiftAmt.getOpcode() == ISD::Constant && 1913 RHSShiftAmt.getOpcode() == ISD::Constant) { 1914 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getValue(); 1915 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getValue(); 1916 if ((LShVal + RShVal) != OpSizeInBits) 1917 return 0; 1918 1919 SDOperand Rot; 1920 if (HasROTL) 1921 Rot = DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt); 1922 else 1923 Rot = DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt); 1924 1925 // If there is an AND of either shifted operand, apply it to the result. 1926 if (LHSMask.Val || RHSMask.Val) { 1927 uint64_t Mask = MVT::getIntVTBitMask(VT); 1928 1929 if (LHSMask.Val) { 1930 uint64_t RHSBits = (1ULL << LShVal)-1; 1931 Mask &= cast<ConstantSDNode>(LHSMask)->getValue() | RHSBits; 1932 } 1933 if (RHSMask.Val) { 1934 uint64_t LHSBits = ~((1ULL << (OpSizeInBits-RShVal))-1); 1935 Mask &= cast<ConstantSDNode>(RHSMask)->getValue() | LHSBits; 1936 } 1937 1938 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT)); 1939 } 1940 1941 return Rot.Val; 1942 } 1943 1944 // If there is a mask here, and we have a variable shift, we can't be sure 1945 // that we're masking out the right stuff. 1946 if (LHSMask.Val || RHSMask.Val) 1947 return 0; 1948 1949 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 1950 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 1951 if (RHSShiftAmt.getOpcode() == ISD::SUB && 1952 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 1953 if (ConstantSDNode *SUBC = 1954 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 1955 if (SUBC->getValue() == OpSizeInBits) 1956 if (HasROTL) 1957 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 1958 else 1959 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 1960 } 1961 } 1962 1963 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 1964 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 1965 if (LHSShiftAmt.getOpcode() == ISD::SUB && 1966 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 1967 if (ConstantSDNode *SUBC = 1968 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 1969 if (SUBC->getValue() == OpSizeInBits) 1970 if (HasROTL) 1971 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 1972 else 1973 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 1974 } 1975 } 1976 1977 // Look for sign/zext/any-extended cases: 1978 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 1979 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 1980 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND) && 1981 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 1982 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 1983 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND)) { 1984 SDOperand LExtOp0 = LHSShiftAmt.getOperand(0); 1985 SDOperand RExtOp0 = RHSShiftAmt.getOperand(0); 1986 if (RExtOp0.getOpcode() == ISD::SUB && 1987 RExtOp0.getOperand(1) == LExtOp0) { 1988 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 1989 // (rotr x, y) 1990 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 1991 // (rotl x, (sub 32, y)) 1992 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 1993 if (SUBC->getValue() == OpSizeInBits) { 1994 if (HasROTL) 1995 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 1996 else 1997 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 1998 } 1999 } 2000 } else if (LExtOp0.getOpcode() == ISD::SUB && 2001 RExtOp0 == LExtOp0.getOperand(1)) { 2002 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -> 2003 // (rotl x, y) 2004 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -> 2005 // (rotr x, (sub 32, y)) 2006 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 2007 if (SUBC->getValue() == OpSizeInBits) { 2008 if (HasROTL) 2009 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, RHSShiftAmt).Val; 2010 else 2011 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 2012 } 2013 } 2014 } 2015 } 2016 2017 return 0; 2018} 2019 2020 2021SDOperand DAGCombiner::visitXOR(SDNode *N) { 2022 SDOperand N0 = N->getOperand(0); 2023 SDOperand N1 = N->getOperand(1); 2024 SDOperand LHS, RHS, CC; 2025 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2026 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2027 MVT::ValueType VT = N0.getValueType(); 2028 2029 // fold vector ops 2030 if (MVT::isVector(VT)) { 2031 SDOperand FoldedVOp = SimplifyVBinOp(N); 2032 if (FoldedVOp.Val) return FoldedVOp; 2033 } 2034 2035 // fold (xor x, undef) -> undef 2036 if (N0.getOpcode() == ISD::UNDEF) 2037 return N0; 2038 if (N1.getOpcode() == ISD::UNDEF) 2039 return N1; 2040 // fold (xor c1, c2) -> c1^c2 2041 if (N0C && N1C) 2042 return DAG.getNode(ISD::XOR, VT, N0, N1); 2043 // canonicalize constant to RHS 2044 if (N0C && !N1C) 2045 return DAG.getNode(ISD::XOR, VT, N1, N0); 2046 // fold (xor x, 0) -> x 2047 if (N1C && N1C->isNullValue()) 2048 return N0; 2049 // reassociate xor 2050 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1); 2051 if (RXOR.Val != 0) 2052 return RXOR; 2053 // fold !(x cc y) -> (x !cc y) 2054 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 2055 bool isInt = MVT::isInteger(LHS.getValueType()); 2056 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 2057 isInt); 2058 if (N0.getOpcode() == ISD::SETCC) 2059 return DAG.getSetCC(VT, LHS, RHS, NotCC); 2060 if (N0.getOpcode() == ISD::SELECT_CC) 2061 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC); 2062 assert(0 && "Unhandled SetCC Equivalent!"); 2063 abort(); 2064 } 2065 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 2066 if (N1C && N1C->getValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 2067 N0.Val->hasOneUse() && isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 2068 SDOperand V = N0.getOperand(0); 2069 V = DAG.getNode(ISD::XOR, V.getValueType(), V, 2070 DAG.getConstant(1, V.getValueType())); 2071 AddToWorkList(V.Val); 2072 return DAG.getNode(ISD::ZERO_EXTEND, VT, V); 2073 } 2074 2075 // fold !(x or y) -> (!x and !y) iff x or y are setcc 2076 if (N1C && N1C->getValue() == 1 && VT == MVT::i1 && 2077 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2078 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2079 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 2080 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2081 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 2082 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 2083 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 2084 return DAG.getNode(NewOpcode, VT, LHS, RHS); 2085 } 2086 } 2087 // fold !(x or y) -> (!x and !y) iff x or y are constants 2088 if (N1C && N1C->isAllOnesValue() && 2089 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2090 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2091 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 2092 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2093 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 2094 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 2095 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 2096 return DAG.getNode(NewOpcode, VT, LHS, RHS); 2097 } 2098 } 2099 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2) 2100 if (N1C && N0.getOpcode() == ISD::XOR) { 2101 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 2102 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2103 if (N00C) 2104 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1), 2105 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT)); 2106 if (N01C) 2107 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0), 2108 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT)); 2109 } 2110 // fold (xor x, x) -> 0 2111 if (N0 == N1) { 2112 if (!MVT::isVector(VT)) { 2113 return DAG.getConstant(0, VT); 2114 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 2115 // Produce a vector of zeros. 2116 SDOperand El = DAG.getConstant(0, MVT::getVectorElementType(VT)); 2117 std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El); 2118 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 2119 } 2120 } 2121 2122 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 2123 if (N0.getOpcode() == N1.getOpcode()) { 2124 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2125 if (Tmp.Val) return Tmp; 2126 } 2127 2128 // Simplify the expression using non-local knowledge. 2129 if (!MVT::isVector(VT) && 2130 SimplifyDemandedBits(SDOperand(N, 0))) 2131 return SDOperand(N, 0); 2132 2133 return SDOperand(); 2134} 2135 2136/// visitShiftByConstant - Handle transforms common to the three shifts, when 2137/// the shift amount is a constant. 2138SDOperand DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 2139 SDNode *LHS = N->getOperand(0).Val; 2140 if (!LHS->hasOneUse()) return SDOperand(); 2141 2142 // We want to pull some binops through shifts, so that we have (and (shift)) 2143 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 2144 // thing happens with address calculations, so it's important to canonicalize 2145 // it. 2146 bool HighBitSet = false; // Can we transform this if the high bit is set? 2147 2148 switch (LHS->getOpcode()) { 2149 default: return SDOperand(); 2150 case ISD::OR: 2151 case ISD::XOR: 2152 HighBitSet = false; // We can only transform sra if the high bit is clear. 2153 break; 2154 case ISD::AND: 2155 HighBitSet = true; // We can only transform sra if the high bit is set. 2156 break; 2157 case ISD::ADD: 2158 if (N->getOpcode() != ISD::SHL) 2159 return SDOperand(); // only shl(add) not sr[al](add). 2160 HighBitSet = false; // We can only transform sra if the high bit is clear. 2161 break; 2162 } 2163 2164 // We require the RHS of the binop to be a constant as well. 2165 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 2166 if (!BinOpCst) return SDOperand(); 2167 2168 2169 // FIXME: disable this for unless the input to the binop is a shift by a 2170 // constant. If it is not a shift, it pessimizes some common cases like: 2171 // 2172 //void foo(int *X, int i) { X[i & 1235] = 1; } 2173 //int bar(int *X, int i) { return X[i & 255]; } 2174 SDNode *BinOpLHSVal = LHS->getOperand(0).Val; 2175 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 2176 BinOpLHSVal->getOpcode() != ISD::SRA && 2177 BinOpLHSVal->getOpcode() != ISD::SRL) || 2178 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 2179 return SDOperand(); 2180 2181 MVT::ValueType VT = N->getValueType(0); 2182 2183 // If this is a signed shift right, and the high bit is modified 2184 // by the logical operation, do not perform the transformation. 2185 // The highBitSet boolean indicates the value of the high bit of 2186 // the constant which would cause it to be modified for this 2187 // operation. 2188 if (N->getOpcode() == ISD::SRA) { 2189 uint64_t BinOpRHSSign = BinOpCst->getValue() >> MVT::getSizeInBits(VT)-1; 2190 if ((bool)BinOpRHSSign != HighBitSet) 2191 return SDOperand(); 2192 } 2193 2194 // Fold the constants, shifting the binop RHS by the shift amount. 2195 SDOperand NewRHS = DAG.getNode(N->getOpcode(), N->getValueType(0), 2196 LHS->getOperand(1), N->getOperand(1)); 2197 2198 // Create the new shift. 2199 SDOperand NewShift = DAG.getNode(N->getOpcode(), VT, LHS->getOperand(0), 2200 N->getOperand(1)); 2201 2202 // Create the new binop. 2203 return DAG.getNode(LHS->getOpcode(), VT, NewShift, NewRHS); 2204} 2205 2206 2207SDOperand DAGCombiner::visitSHL(SDNode *N) { 2208 SDOperand N0 = N->getOperand(0); 2209 SDOperand N1 = N->getOperand(1); 2210 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2211 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2212 MVT::ValueType VT = N0.getValueType(); 2213 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 2214 2215 // fold (shl c1, c2) -> c1<<c2 2216 if (N0C && N1C) 2217 return DAG.getNode(ISD::SHL, VT, N0, N1); 2218 // fold (shl 0, x) -> 0 2219 if (N0C && N0C->isNullValue()) 2220 return N0; 2221 // fold (shl x, c >= size(x)) -> undef 2222 if (N1C && N1C->getValue() >= OpSizeInBits) 2223 return DAG.getNode(ISD::UNDEF, VT); 2224 // fold (shl x, 0) -> x 2225 if (N1C && N1C->isNullValue()) 2226 return N0; 2227 // if (shl x, c) is known to be zero, return 0 2228 if (DAG.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) 2229 return DAG.getConstant(0, VT); 2230 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 2231 return SDOperand(N, 0); 2232 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2) 2233 if (N1C && N0.getOpcode() == ISD::SHL && 2234 N0.getOperand(1).getOpcode() == ISD::Constant) { 2235 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2236 uint64_t c2 = N1C->getValue(); 2237 if (c1 + c2 > OpSizeInBits) 2238 return DAG.getConstant(0, VT); 2239 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0), 2240 DAG.getConstant(c1 + c2, N1.getValueType())); 2241 } 2242 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or 2243 // (srl (and x, -1 << c1), c1-c2) 2244 if (N1C && N0.getOpcode() == ISD::SRL && 2245 N0.getOperand(1).getOpcode() == ISD::Constant) { 2246 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2247 uint64_t c2 = N1C->getValue(); 2248 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0), 2249 DAG.getConstant(~0ULL << c1, VT)); 2250 if (c2 > c1) 2251 return DAG.getNode(ISD::SHL, VT, Mask, 2252 DAG.getConstant(c2-c1, N1.getValueType())); 2253 else 2254 return DAG.getNode(ISD::SRL, VT, Mask, 2255 DAG.getConstant(c1-c2, N1.getValueType())); 2256 } 2257 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1) 2258 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 2259 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 2260 DAG.getConstant(~0ULL << N1C->getValue(), VT)); 2261 2262 return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDOperand(); 2263} 2264 2265SDOperand DAGCombiner::visitSRA(SDNode *N) { 2266 SDOperand N0 = N->getOperand(0); 2267 SDOperand N1 = N->getOperand(1); 2268 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2269 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2270 MVT::ValueType VT = N0.getValueType(); 2271 2272 // fold (sra c1, c2) -> c1>>c2 2273 if (N0C && N1C) 2274 return DAG.getNode(ISD::SRA, VT, N0, N1); 2275 // fold (sra 0, x) -> 0 2276 if (N0C && N0C->isNullValue()) 2277 return N0; 2278 // fold (sra -1, x) -> -1 2279 if (N0C && N0C->isAllOnesValue()) 2280 return N0; 2281 // fold (sra x, c >= size(x)) -> undef 2282 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT)) 2283 return DAG.getNode(ISD::UNDEF, VT); 2284 // fold (sra x, 0) -> x 2285 if (N1C && N1C->isNullValue()) 2286 return N0; 2287 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 2288 // sext_inreg. 2289 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 2290 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue(); 2291 MVT::ValueType EVT; 2292 switch (LowBits) { 2293 default: EVT = MVT::Other; break; 2294 case 1: EVT = MVT::i1; break; 2295 case 8: EVT = MVT::i8; break; 2296 case 16: EVT = MVT::i16; break; 2297 case 32: EVT = MVT::i32; break; 2298 } 2299 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT)) 2300 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), 2301 DAG.getValueType(EVT)); 2302 } 2303 2304 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2) 2305 if (N1C && N0.getOpcode() == ISD::SRA) { 2306 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2307 unsigned Sum = N1C->getValue() + C1->getValue(); 2308 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1; 2309 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), 2310 DAG.getConstant(Sum, N1C->getValueType(0))); 2311 } 2312 } 2313 2314 // Simplify, based on bits shifted out of the LHS. 2315 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 2316 return SDOperand(N, 0); 2317 2318 2319 // If the sign bit is known to be zero, switch this to a SRL. 2320 if (DAG.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT))) 2321 return DAG.getNode(ISD::SRL, VT, N0, N1); 2322 2323 return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDOperand(); 2324} 2325 2326SDOperand DAGCombiner::visitSRL(SDNode *N) { 2327 SDOperand N0 = N->getOperand(0); 2328 SDOperand N1 = N->getOperand(1); 2329 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2330 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2331 MVT::ValueType VT = N0.getValueType(); 2332 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 2333 2334 // fold (srl c1, c2) -> c1 >>u c2 2335 if (N0C && N1C) 2336 return DAG.getNode(ISD::SRL, VT, N0, N1); 2337 // fold (srl 0, x) -> 0 2338 if (N0C && N0C->isNullValue()) 2339 return N0; 2340 // fold (srl x, c >= size(x)) -> undef 2341 if (N1C && N1C->getValue() >= OpSizeInBits) 2342 return DAG.getNode(ISD::UNDEF, VT); 2343 // fold (srl x, 0) -> x 2344 if (N1C && N1C->isNullValue()) 2345 return N0; 2346 // if (srl x, c) is known to be zero, return 0 2347 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits))) 2348 return DAG.getConstant(0, VT); 2349 2350 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2) 2351 if (N1C && N0.getOpcode() == ISD::SRL && 2352 N0.getOperand(1).getOpcode() == ISD::Constant) { 2353 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2354 uint64_t c2 = N1C->getValue(); 2355 if (c1 + c2 > OpSizeInBits) 2356 return DAG.getConstant(0, VT); 2357 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 2358 DAG.getConstant(c1 + c2, N1.getValueType())); 2359 } 2360 2361 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 2362 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2363 // Shifting in all undef bits? 2364 MVT::ValueType SmallVT = N0.getOperand(0).getValueType(); 2365 if (N1C->getValue() >= MVT::getSizeInBits(SmallVT)) 2366 return DAG.getNode(ISD::UNDEF, VT); 2367 2368 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1); 2369 AddToWorkList(SmallShift.Val); 2370 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift); 2371 } 2372 2373 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 2374 // bit, which is unmodified by sra. 2375 if (N1C && N1C->getValue()+1 == MVT::getSizeInBits(VT)) { 2376 if (N0.getOpcode() == ISD::SRA) 2377 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1); 2378 } 2379 2380 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 2381 if (N1C && N0.getOpcode() == ISD::CTLZ && 2382 N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) { 2383 uint64_t KnownZero, KnownOne, Mask = MVT::getIntVTBitMask(VT); 2384 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 2385 2386 // If any of the input bits are KnownOne, then the input couldn't be all 2387 // zeros, thus the result of the srl will always be zero. 2388 if (KnownOne) return DAG.getConstant(0, VT); 2389 2390 // If all of the bits input the to ctlz node are known to be zero, then 2391 // the result of the ctlz is "32" and the result of the shift is one. 2392 uint64_t UnknownBits = ~KnownZero & Mask; 2393 if (UnknownBits == 0) return DAG.getConstant(1, VT); 2394 2395 // Otherwise, check to see if there is exactly one bit input to the ctlz. 2396 if ((UnknownBits & (UnknownBits-1)) == 0) { 2397 // Okay, we know that only that the single bit specified by UnknownBits 2398 // could be set on input to the CTLZ node. If this bit is set, the SRL 2399 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 2400 // to an SRL,XOR pair, which is likely to simplify more. 2401 unsigned ShAmt = CountTrailingZeros_64(UnknownBits); 2402 SDOperand Op = N0.getOperand(0); 2403 if (ShAmt) { 2404 Op = DAG.getNode(ISD::SRL, VT, Op, 2405 DAG.getConstant(ShAmt, TLI.getShiftAmountTy())); 2406 AddToWorkList(Op.Val); 2407 } 2408 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT)); 2409 } 2410 } 2411 2412 // fold operands of srl based on knowledge that the low bits are not 2413 // demanded. 2414 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 2415 return SDOperand(N, 0); 2416 2417 return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDOperand(); 2418} 2419 2420SDOperand DAGCombiner::visitCTLZ(SDNode *N) { 2421 SDOperand N0 = N->getOperand(0); 2422 MVT::ValueType VT = N->getValueType(0); 2423 2424 // fold (ctlz c1) -> c2 2425 if (isa<ConstantSDNode>(N0)) 2426 return DAG.getNode(ISD::CTLZ, VT, N0); 2427 return SDOperand(); 2428} 2429 2430SDOperand DAGCombiner::visitCTTZ(SDNode *N) { 2431 SDOperand N0 = N->getOperand(0); 2432 MVT::ValueType VT = N->getValueType(0); 2433 2434 // fold (cttz c1) -> c2 2435 if (isa<ConstantSDNode>(N0)) 2436 return DAG.getNode(ISD::CTTZ, VT, N0); 2437 return SDOperand(); 2438} 2439 2440SDOperand DAGCombiner::visitCTPOP(SDNode *N) { 2441 SDOperand N0 = N->getOperand(0); 2442 MVT::ValueType VT = N->getValueType(0); 2443 2444 // fold (ctpop c1) -> c2 2445 if (isa<ConstantSDNode>(N0)) 2446 return DAG.getNode(ISD::CTPOP, VT, N0); 2447 return SDOperand(); 2448} 2449 2450SDOperand DAGCombiner::visitSELECT(SDNode *N) { 2451 SDOperand N0 = N->getOperand(0); 2452 SDOperand N1 = N->getOperand(1); 2453 SDOperand N2 = N->getOperand(2); 2454 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2455 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2456 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 2457 MVT::ValueType VT = N->getValueType(0); 2458 MVT::ValueType VT0 = N0.getValueType(); 2459 2460 // fold select C, X, X -> X 2461 if (N1 == N2) 2462 return N1; 2463 // fold select true, X, Y -> X 2464 if (N0C && !N0C->isNullValue()) 2465 return N1; 2466 // fold select false, X, Y -> Y 2467 if (N0C && N0C->isNullValue()) 2468 return N2; 2469 // fold select C, 1, X -> C | X 2470 if (MVT::i1 == VT && N1C && N1C->getValue() == 1) 2471 return DAG.getNode(ISD::OR, VT, N0, N2); 2472 // fold select C, 0, 1 -> ~C 2473 if (MVT::isInteger(VT) && MVT::isInteger(VT0) && 2474 N1C && N2C && N1C->isNullValue() && N2C->getValue() == 1) { 2475 SDOperand XORNode = DAG.getNode(ISD::XOR, VT0, N0, DAG.getConstant(1, VT0)); 2476 if (VT == VT0) 2477 return XORNode; 2478 AddToWorkList(XORNode.Val); 2479 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(VT0)) 2480 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode); 2481 return DAG.getNode(ISD::TRUNCATE, VT, XORNode); 2482 } 2483 // fold select C, 0, X -> ~C & X 2484 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 2485 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 2486 AddToWorkList(XORNode.Val); 2487 return DAG.getNode(ISD::AND, VT, XORNode, N2); 2488 } 2489 // fold select C, X, 1 -> ~C | X 2490 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getValue() == 1) { 2491 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 2492 AddToWorkList(XORNode.Val); 2493 return DAG.getNode(ISD::OR, VT, XORNode, N1); 2494 } 2495 // fold select C, X, 0 -> C & X 2496 // FIXME: this should check for C type == X type, not i1? 2497 if (MVT::i1 == VT && N2C && N2C->isNullValue()) 2498 return DAG.getNode(ISD::AND, VT, N0, N1); 2499 // fold X ? X : Y --> X ? 1 : Y --> X | Y 2500 if (MVT::i1 == VT && N0 == N1) 2501 return DAG.getNode(ISD::OR, VT, N0, N2); 2502 // fold X ? Y : X --> X ? Y : 0 --> X & Y 2503 if (MVT::i1 == VT && N0 == N2) 2504 return DAG.getNode(ISD::AND, VT, N0, N1); 2505 2506 // If we can fold this based on the true/false value, do so. 2507 if (SimplifySelectOps(N, N1, N2)) 2508 return SDOperand(N, 0); // Don't revisit N. 2509 2510 // fold selects based on a setcc into other things, such as min/max/abs 2511 if (N0.getOpcode() == ISD::SETCC) 2512 // FIXME: 2513 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 2514 // having to say they don't support SELECT_CC on every type the DAG knows 2515 // about, since there is no way to mark an opcode illegal at all value types 2516 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other)) 2517 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1), 2518 N1, N2, N0.getOperand(2)); 2519 else 2520 return SimplifySelect(N0, N1, N2); 2521 return SDOperand(); 2522} 2523 2524SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) { 2525 SDOperand N0 = N->getOperand(0); 2526 SDOperand N1 = N->getOperand(1); 2527 SDOperand N2 = N->getOperand(2); 2528 SDOperand N3 = N->getOperand(3); 2529 SDOperand N4 = N->getOperand(4); 2530 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 2531 2532 // fold select_cc lhs, rhs, x, x, cc -> x 2533 if (N2 == N3) 2534 return N2; 2535 2536 // Determine if the condition we're dealing with is constant 2537 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 2538 if (SCC.Val) AddToWorkList(SCC.Val); 2539 2540 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) { 2541 if (SCCC->getValue()) 2542 return N2; // cond always true -> true val 2543 else 2544 return N3; // cond always false -> false val 2545 } 2546 2547 // Fold to a simpler select_cc 2548 if (SCC.Val && SCC.getOpcode() == ISD::SETCC) 2549 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(), 2550 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 2551 SCC.getOperand(2)); 2552 2553 // If we can fold this based on the true/false value, do so. 2554 if (SimplifySelectOps(N, N2, N3)) 2555 return SDOperand(N, 0); // Don't revisit N. 2556 2557 // fold select_cc into other things, such as min/max/abs 2558 return SimplifySelectCC(N0, N1, N2, N3, CC); 2559} 2560 2561SDOperand DAGCombiner::visitSETCC(SDNode *N) { 2562 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 2563 cast<CondCodeSDNode>(N->getOperand(2))->get()); 2564} 2565 2566// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 2567// "fold ({s|z}ext (load x)) -> ({s|z}ext (truncate ({s|z}extload x)))" 2568// transformation. Returns true if extension are possible and the above 2569// mentioned transformation is profitable. 2570static bool ExtendUsesToFormExtLoad(SDNode *N, SDOperand N0, 2571 unsigned ExtOpc, 2572 SmallVector<SDNode*, 4> &ExtendNodes, 2573 TargetLowering &TLI) { 2574 bool HasCopyToRegUses = false; 2575 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 2576 for (SDNode::use_iterator UI = N0.Val->use_begin(), UE = N0.Val->use_end(); 2577 UI != UE; ++UI) { 2578 SDNode *User = *UI; 2579 if (User == N) 2580 continue; 2581 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 2582 if (User->getOpcode() == ISD::SETCC) { 2583 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 2584 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 2585 // Sign bits will be lost after a zext. 2586 return false; 2587 bool Add = false; 2588 for (unsigned i = 0; i != 2; ++i) { 2589 SDOperand UseOp = User->getOperand(i); 2590 if (UseOp == N0) 2591 continue; 2592 if (!isa<ConstantSDNode>(UseOp)) 2593 return false; 2594 Add = true; 2595 } 2596 if (Add) 2597 ExtendNodes.push_back(User); 2598 } else { 2599 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2600 SDOperand UseOp = User->getOperand(i); 2601 if (UseOp == N0) { 2602 // If truncate from extended type to original load type is free 2603 // on this target, then it's ok to extend a CopyToReg. 2604 if (isTruncFree && User->getOpcode() == ISD::CopyToReg) 2605 HasCopyToRegUses = true; 2606 else 2607 return false; 2608 } 2609 } 2610 } 2611 } 2612 2613 if (HasCopyToRegUses) { 2614 bool BothLiveOut = false; 2615 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 2616 UI != UE; ++UI) { 2617 SDNode *User = *UI; 2618 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2619 SDOperand UseOp = User->getOperand(i); 2620 if (UseOp.Val == N && UseOp.ResNo == 0) { 2621 BothLiveOut = true; 2622 break; 2623 } 2624 } 2625 } 2626 if (BothLiveOut) 2627 // Both unextended and extended values are live out. There had better be 2628 // good a reason for the transformation. 2629 return ExtendNodes.size(); 2630 } 2631 return true; 2632} 2633 2634SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 2635 SDOperand N0 = N->getOperand(0); 2636 MVT::ValueType VT = N->getValueType(0); 2637 2638 // fold (sext c1) -> c1 2639 if (isa<ConstantSDNode>(N0)) 2640 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0); 2641 2642 // fold (sext (sext x)) -> (sext x) 2643 // fold (sext (aext x)) -> (sext x) 2644 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2645 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0)); 2646 2647 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 2648 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 2649 if (N0.getOpcode() == ISD::TRUNCATE) { 2650 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2651 if (NarrowLoad.Val) { 2652 if (NarrowLoad.Val != N0.Val) 2653 CombineTo(N0.Val, NarrowLoad); 2654 return DAG.getNode(ISD::SIGN_EXTEND, VT, NarrowLoad); 2655 } 2656 } 2657 2658 // See if the value being truncated is already sign extended. If so, just 2659 // eliminate the trunc/sext pair. 2660 if (N0.getOpcode() == ISD::TRUNCATE) { 2661 SDOperand Op = N0.getOperand(0); 2662 unsigned OpBits = MVT::getSizeInBits(Op.getValueType()); 2663 unsigned MidBits = MVT::getSizeInBits(N0.getValueType()); 2664 unsigned DestBits = MVT::getSizeInBits(VT); 2665 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 2666 2667 if (OpBits == DestBits) { 2668 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 2669 // bits, it is already ready. 2670 if (NumSignBits > DestBits-MidBits) 2671 return Op; 2672 } else if (OpBits < DestBits) { 2673 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 2674 // bits, just sext from i32. 2675 if (NumSignBits > OpBits-MidBits) 2676 return DAG.getNode(ISD::SIGN_EXTEND, VT, Op); 2677 } else { 2678 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 2679 // bits, just truncate to i32. 2680 if (NumSignBits > OpBits-MidBits) 2681 return DAG.getNode(ISD::TRUNCATE, VT, Op); 2682 } 2683 2684 // fold (sext (truncate x)) -> (sextinreg x). 2685 if (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 2686 N0.getValueType())) { 2687 if (Op.getValueType() < VT) 2688 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2689 else if (Op.getValueType() > VT) 2690 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2691 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op, 2692 DAG.getValueType(N0.getValueType())); 2693 } 2694 } 2695 2696 // fold (sext (load x)) -> (sext (truncate (sextload x))) 2697 if (ISD::isNON_EXTLoad(N0.Val) && 2698 (!AfterLegalize||TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType()))){ 2699 bool DoXform = true; 2700 SmallVector<SDNode*, 4> SetCCs; 2701 if (!N0.hasOneUse()) 2702 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 2703 if (DoXform) { 2704 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2705 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2706 LN0->getBasePtr(), LN0->getSrcValue(), 2707 LN0->getSrcValueOffset(), 2708 N0.getValueType(), 2709 LN0->isVolatile(), 2710 LN0->getAlignment()); 2711 CombineTo(N, ExtLoad); 2712 SDOperand Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad); 2713 CombineTo(N0.Val, Trunc, ExtLoad.getValue(1)); 2714 // Extend SetCC uses if necessary. 2715 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 2716 SDNode *SetCC = SetCCs[i]; 2717 SmallVector<SDOperand, 4> Ops; 2718 for (unsigned j = 0; j != 2; ++j) { 2719 SDOperand SOp = SetCC->getOperand(j); 2720 if (SOp == Trunc) 2721 Ops.push_back(ExtLoad); 2722 else 2723 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, VT, SOp)); 2724 } 2725 Ops.push_back(SetCC->getOperand(2)); 2726 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0), 2727 &Ops[0], Ops.size())); 2728 } 2729 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2730 } 2731 } 2732 2733 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 2734 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 2735 if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && 2736 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) { 2737 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2738 MVT::ValueType EVT = LN0->getLoadedVT(); 2739 if (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) { 2740 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2741 LN0->getBasePtr(), LN0->getSrcValue(), 2742 LN0->getSrcValueOffset(), EVT, 2743 LN0->isVolatile(), 2744 LN0->getAlignment()); 2745 CombineTo(N, ExtLoad); 2746 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2747 ExtLoad.getValue(1)); 2748 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2749 } 2750 } 2751 2752 // sext(setcc x,y,cc) -> select_cc x, y, -1, 0, cc 2753 if (N0.getOpcode() == ISD::SETCC) { 2754 SDOperand SCC = 2755 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 2756 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT), 2757 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 2758 if (SCC.Val) return SCC; 2759 } 2760 2761 return SDOperand(); 2762} 2763 2764SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) { 2765 SDOperand N0 = N->getOperand(0); 2766 MVT::ValueType VT = N->getValueType(0); 2767 2768 // fold (zext c1) -> c1 2769 if (isa<ConstantSDNode>(N0)) 2770 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 2771 // fold (zext (zext x)) -> (zext x) 2772 // fold (zext (aext x)) -> (zext x) 2773 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2774 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0)); 2775 2776 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 2777 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 2778 if (N0.getOpcode() == ISD::TRUNCATE) { 2779 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2780 if (NarrowLoad.Val) { 2781 if (NarrowLoad.Val != N0.Val) 2782 CombineTo(N0.Val, NarrowLoad); 2783 return DAG.getNode(ISD::ZERO_EXTEND, VT, NarrowLoad); 2784 } 2785 } 2786 2787 // fold (zext (truncate x)) -> (and x, mask) 2788 if (N0.getOpcode() == ISD::TRUNCATE && 2789 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) { 2790 SDOperand Op = N0.getOperand(0); 2791 if (Op.getValueType() < VT) { 2792 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2793 } else if (Op.getValueType() > VT) { 2794 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2795 } 2796 return DAG.getZeroExtendInReg(Op, N0.getValueType()); 2797 } 2798 2799 // fold (zext (and (trunc x), cst)) -> (and x, cst). 2800 if (N0.getOpcode() == ISD::AND && 2801 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 2802 N0.getOperand(1).getOpcode() == ISD::Constant) { 2803 SDOperand X = N0.getOperand(0).getOperand(0); 2804 if (X.getValueType() < VT) { 2805 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 2806 } else if (X.getValueType() > VT) { 2807 X = DAG.getNode(ISD::TRUNCATE, VT, X); 2808 } 2809 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2810 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 2811 } 2812 2813 // fold (zext (load x)) -> (zext (truncate (zextload x))) 2814 if (ISD::isNON_EXTLoad(N0.Val) && 2815 (!AfterLegalize||TLI.isLoadXLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 2816 bool DoXform = true; 2817 SmallVector<SDNode*, 4> SetCCs; 2818 if (!N0.hasOneUse()) 2819 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 2820 if (DoXform) { 2821 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2822 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 2823 LN0->getBasePtr(), LN0->getSrcValue(), 2824 LN0->getSrcValueOffset(), 2825 N0.getValueType(), 2826 LN0->isVolatile(), 2827 LN0->getAlignment()); 2828 CombineTo(N, ExtLoad); 2829 SDOperand Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad); 2830 CombineTo(N0.Val, Trunc, ExtLoad.getValue(1)); 2831 // Extend SetCC uses if necessary. 2832 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 2833 SDNode *SetCC = SetCCs[i]; 2834 SmallVector<SDOperand, 4> Ops; 2835 for (unsigned j = 0; j != 2; ++j) { 2836 SDOperand SOp = SetCC->getOperand(j); 2837 if (SOp == Trunc) 2838 Ops.push_back(ExtLoad); 2839 else 2840 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, VT, SOp)); 2841 } 2842 Ops.push_back(SetCC->getOperand(2)); 2843 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0), 2844 &Ops[0], Ops.size())); 2845 } 2846 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2847 } 2848 } 2849 2850 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 2851 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 2852 if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && 2853 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) { 2854 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2855 MVT::ValueType EVT = LN0->getLoadedVT(); 2856 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 2857 LN0->getBasePtr(), LN0->getSrcValue(), 2858 LN0->getSrcValueOffset(), EVT, 2859 LN0->isVolatile(), 2860 LN0->getAlignment()); 2861 CombineTo(N, ExtLoad); 2862 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2863 ExtLoad.getValue(1)); 2864 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2865 } 2866 2867 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 2868 if (N0.getOpcode() == ISD::SETCC) { 2869 SDOperand SCC = 2870 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 2871 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 2872 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 2873 if (SCC.Val) return SCC; 2874 } 2875 2876 return SDOperand(); 2877} 2878 2879SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) { 2880 SDOperand N0 = N->getOperand(0); 2881 MVT::ValueType VT = N->getValueType(0); 2882 2883 // fold (aext c1) -> c1 2884 if (isa<ConstantSDNode>(N0)) 2885 return DAG.getNode(ISD::ANY_EXTEND, VT, N0); 2886 // fold (aext (aext x)) -> (aext x) 2887 // fold (aext (zext x)) -> (zext x) 2888 // fold (aext (sext x)) -> (sext x) 2889 if (N0.getOpcode() == ISD::ANY_EXTEND || 2890 N0.getOpcode() == ISD::ZERO_EXTEND || 2891 N0.getOpcode() == ISD::SIGN_EXTEND) 2892 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 2893 2894 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 2895 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 2896 if (N0.getOpcode() == ISD::TRUNCATE) { 2897 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2898 if (NarrowLoad.Val) { 2899 if (NarrowLoad.Val != N0.Val) 2900 CombineTo(N0.Val, NarrowLoad); 2901 return DAG.getNode(ISD::ANY_EXTEND, VT, NarrowLoad); 2902 } 2903 } 2904 2905 // fold (aext (truncate x)) 2906 if (N0.getOpcode() == ISD::TRUNCATE) { 2907 SDOperand TruncOp = N0.getOperand(0); 2908 if (TruncOp.getValueType() == VT) 2909 return TruncOp; // x iff x size == zext size. 2910 if (TruncOp.getValueType() > VT) 2911 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp); 2912 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp); 2913 } 2914 2915 // fold (aext (and (trunc x), cst)) -> (and x, cst). 2916 if (N0.getOpcode() == ISD::AND && 2917 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 2918 N0.getOperand(1).getOpcode() == ISD::Constant) { 2919 SDOperand X = N0.getOperand(0).getOperand(0); 2920 if (X.getValueType() < VT) { 2921 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 2922 } else if (X.getValueType() > VT) { 2923 X = DAG.getNode(ISD::TRUNCATE, VT, X); 2924 } 2925 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2926 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 2927 } 2928 2929 // fold (aext (load x)) -> (aext (truncate (extload x))) 2930 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2931 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) { 2932 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2933 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 2934 LN0->getBasePtr(), LN0->getSrcValue(), 2935 LN0->getSrcValueOffset(), 2936 N0.getValueType(), 2937 LN0->isVolatile(), 2938 LN0->getAlignment()); 2939 CombineTo(N, ExtLoad); 2940 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2941 ExtLoad.getValue(1)); 2942 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2943 } 2944 2945 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 2946 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 2947 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 2948 if (N0.getOpcode() == ISD::LOAD && 2949 !ISD::isNON_EXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 2950 N0.hasOneUse()) { 2951 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2952 MVT::ValueType EVT = LN0->getLoadedVT(); 2953 SDOperand ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT, 2954 LN0->getChain(), LN0->getBasePtr(), 2955 LN0->getSrcValue(), 2956 LN0->getSrcValueOffset(), EVT, 2957 LN0->isVolatile(), 2958 LN0->getAlignment()); 2959 CombineTo(N, ExtLoad); 2960 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2961 ExtLoad.getValue(1)); 2962 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2963 } 2964 2965 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 2966 if (N0.getOpcode() == ISD::SETCC) { 2967 SDOperand SCC = 2968 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 2969 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 2970 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 2971 if (SCC.Val) 2972 return SCC; 2973 } 2974 2975 return SDOperand(); 2976} 2977 2978/// GetDemandedBits - See if the specified operand can be simplified with the 2979/// knowledge that only the bits specified by Mask are used. If so, return the 2980/// simpler operand, otherwise return a null SDOperand. 2981SDOperand DAGCombiner::GetDemandedBits(SDOperand V, uint64_t Mask) { 2982 switch (V.getOpcode()) { 2983 default: break; 2984 case ISD::OR: 2985 case ISD::XOR: 2986 // If the LHS or RHS don't contribute bits to the or, drop them. 2987 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 2988 return V.getOperand(1); 2989 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 2990 return V.getOperand(0); 2991 break; 2992 case ISD::SRL: 2993 // Only look at single-use SRLs. 2994 if (!V.Val->hasOneUse()) 2995 break; 2996 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 2997 // See if we can recursively simplify the LHS. 2998 unsigned Amt = RHSC->getValue(); 2999 Mask = (Mask << Amt) & MVT::getIntVTBitMask(V.getValueType()); 3000 SDOperand SimplifyLHS = GetDemandedBits(V.getOperand(0), Mask); 3001 if (SimplifyLHS.Val) { 3002 return DAG.getNode(ISD::SRL, V.getValueType(), 3003 SimplifyLHS, V.getOperand(1)); 3004 } 3005 } 3006 } 3007 return SDOperand(); 3008} 3009 3010/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 3011/// bits and then truncated to a narrower type and where N is a multiple 3012/// of number of bits of the narrower type, transform it to a narrower load 3013/// from address + N / num of bits of new type. If the result is to be 3014/// extended, also fold the extension to form a extending load. 3015SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) { 3016 unsigned Opc = N->getOpcode(); 3017 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 3018 SDOperand N0 = N->getOperand(0); 3019 MVT::ValueType VT = N->getValueType(0); 3020 MVT::ValueType EVT = N->getValueType(0); 3021 3022 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then 3023 // extended to VT. 3024 if (Opc == ISD::SIGN_EXTEND_INREG) { 3025 ExtType = ISD::SEXTLOAD; 3026 EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3027 if (AfterLegalize && !TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) 3028 return SDOperand(); 3029 } 3030 3031 unsigned EVTBits = MVT::getSizeInBits(EVT); 3032 unsigned ShAmt = 0; 3033 bool CombineSRL = false; 3034 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 3035 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3036 ShAmt = N01->getValue(); 3037 // Is the shift amount a multiple of size of VT? 3038 if ((ShAmt & (EVTBits-1)) == 0) { 3039 N0 = N0.getOperand(0); 3040 if (MVT::getSizeInBits(N0.getValueType()) <= EVTBits) 3041 return SDOperand(); 3042 CombineSRL = true; 3043 } 3044 } 3045 } 3046 3047 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 3048 // Do not allow folding to i1 here. i1 is implicitly stored in memory in 3049 // zero extended form: by shrinking the load, we lose track of the fact 3050 // that it is already zero extended. 3051 // FIXME: This should be reevaluated. 3052 VT != MVT::i1) { 3053 assert(MVT::getSizeInBits(N0.getValueType()) > EVTBits && 3054 "Cannot truncate to larger type!"); 3055 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3056 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 3057 // For big endian targets, we need to adjust the offset to the pointer to 3058 // load the correct bytes. 3059 if (!TLI.isLittleEndian()) { 3060 unsigned LVTStoreBits = MVT::getStoreSizeInBits(N0.getValueType()); 3061 unsigned EVTStoreBits = MVT::getStoreSizeInBits(EVT); 3062 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 3063 } 3064 uint64_t PtrOff = ShAmt / 8; 3065 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 3066 SDOperand NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(), 3067 DAG.getConstant(PtrOff, PtrType)); 3068 AddToWorkList(NewPtr.Val); 3069 SDOperand Load = (ExtType == ISD::NON_EXTLOAD) 3070 ? DAG.getLoad(VT, LN0->getChain(), NewPtr, 3071 LN0->getSrcValue(), LN0->getSrcValueOffset(), 3072 LN0->isVolatile(), NewAlign) 3073 : DAG.getExtLoad(ExtType, VT, LN0->getChain(), NewPtr, 3074 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT, 3075 LN0->isVolatile(), NewAlign); 3076 AddToWorkList(N); 3077 if (CombineSRL) { 3078 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1)); 3079 CombineTo(N->getOperand(0).Val, Load); 3080 } else 3081 CombineTo(N0.Val, Load, Load.getValue(1)); 3082 if (ShAmt) { 3083 if (Opc == ISD::SIGN_EXTEND_INREG) 3084 return DAG.getNode(Opc, VT, Load, N->getOperand(1)); 3085 else 3086 return DAG.getNode(Opc, VT, Load); 3087 } 3088 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3089 } 3090 3091 return SDOperand(); 3092} 3093 3094 3095SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 3096 SDOperand N0 = N->getOperand(0); 3097 SDOperand N1 = N->getOperand(1); 3098 MVT::ValueType VT = N->getValueType(0); 3099 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT(); 3100 unsigned EVTBits = MVT::getSizeInBits(EVT); 3101 3102 // fold (sext_in_reg c1) -> c1 3103 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 3104 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1); 3105 3106 // If the input is already sign extended, just drop the extension. 3107 if (DAG.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1) 3108 return N0; 3109 3110 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 3111 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 3112 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) { 3113 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); 3114 } 3115 3116 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 3117 if (DAG.MaskedValueIsZero(N0, 1ULL << (EVTBits-1))) 3118 return DAG.getZeroExtendInReg(N0, EVT); 3119 3120 // fold operands of sext_in_reg based on knowledge that the top bits are not 3121 // demanded. 3122 if (SimplifyDemandedBits(SDOperand(N, 0))) 3123 return SDOperand(N, 0); 3124 3125 // fold (sext_in_reg (load x)) -> (smaller sextload x) 3126 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 3127 SDOperand NarrowLoad = ReduceLoadWidth(N); 3128 if (NarrowLoad.Val) 3129 return NarrowLoad; 3130 3131 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24 3132 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible. 3133 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 3134 if (N0.getOpcode() == ISD::SRL) { 3135 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 3136 if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) { 3137 // We can turn this into an SRA iff the input to the SRL is already sign 3138 // extended enough. 3139 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 3140 if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits) 3141 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1)); 3142 } 3143 } 3144 3145 // fold (sext_inreg (extload x)) -> (sextload x) 3146 if (ISD::isEXTLoad(N0.Val) && 3147 ISD::isUNINDEXEDLoad(N0.Val) && 3148 EVT == cast<LoadSDNode>(N0)->getLoadedVT() && 3149 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) { 3150 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3151 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 3152 LN0->getBasePtr(), LN0->getSrcValue(), 3153 LN0->getSrcValueOffset(), EVT, 3154 LN0->isVolatile(), 3155 LN0->getAlignment()); 3156 CombineTo(N, ExtLoad); 3157 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 3158 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3159 } 3160 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 3161 if (ISD::isZEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 3162 N0.hasOneUse() && 3163 EVT == cast<LoadSDNode>(N0)->getLoadedVT() && 3164 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) { 3165 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3166 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 3167 LN0->getBasePtr(), LN0->getSrcValue(), 3168 LN0->getSrcValueOffset(), EVT, 3169 LN0->isVolatile(), 3170 LN0->getAlignment()); 3171 CombineTo(N, ExtLoad); 3172 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 3173 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3174 } 3175 return SDOperand(); 3176} 3177 3178SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) { 3179 SDOperand N0 = N->getOperand(0); 3180 MVT::ValueType VT = N->getValueType(0); 3181 3182 // noop truncate 3183 if (N0.getValueType() == N->getValueType(0)) 3184 return N0; 3185 // fold (truncate c1) -> c1 3186 if (isa<ConstantSDNode>(N0)) 3187 return DAG.getNode(ISD::TRUNCATE, VT, N0); 3188 // fold (truncate (truncate x)) -> (truncate x) 3189 if (N0.getOpcode() == ISD::TRUNCATE) 3190 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 3191 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 3192 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| 3193 N0.getOpcode() == ISD::ANY_EXTEND) { 3194 if (N0.getOperand(0).getValueType() < VT) 3195 // if the source is smaller than the dest, we still need an extend 3196 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 3197 else if (N0.getOperand(0).getValueType() > VT) 3198 // if the source is larger than the dest, than we just need the truncate 3199 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 3200 else 3201 // if the source and dest are the same type, we can drop both the extend 3202 // and the truncate 3203 return N0.getOperand(0); 3204 } 3205 3206 // See if we can simplify the input to this truncate through knowledge that 3207 // only the low bits are being used. For example "trunc (or (shl x, 8), y)" 3208 // -> trunc y 3209 SDOperand Shorter = GetDemandedBits(N0, MVT::getIntVTBitMask(VT)); 3210 if (Shorter.Val) 3211 return DAG.getNode(ISD::TRUNCATE, VT, Shorter); 3212 3213 // fold (truncate (load x)) -> (smaller load x) 3214 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 3215 return ReduceLoadWidth(N); 3216} 3217 3218SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) { 3219 SDOperand N0 = N->getOperand(0); 3220 MVT::ValueType VT = N->getValueType(0); 3221 3222 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 3223 // Only do this before legalize, since afterward the target may be depending 3224 // on the bitconvert. 3225 // First check to see if this is all constant. 3226 if (!AfterLegalize && 3227 N0.getOpcode() == ISD::BUILD_VECTOR && N0.Val->hasOneUse() && 3228 MVT::isVector(VT)) { 3229 bool isSimple = true; 3230 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 3231 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 3232 N0.getOperand(i).getOpcode() != ISD::Constant && 3233 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 3234 isSimple = false; 3235 break; 3236 } 3237 3238 MVT::ValueType DestEltVT = MVT::getVectorElementType(N->getValueType(0)); 3239 assert(!MVT::isVector(DestEltVT) && 3240 "Element type of vector ValueType must not be vector!"); 3241 if (isSimple) { 3242 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.Val, DestEltVT); 3243 } 3244 } 3245 3246 // If the input is a constant, let getNode() fold it. 3247 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 3248 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0); 3249 if (Res.Val != N) return Res; 3250 } 3251 3252 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2) 3253 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3254 3255 // fold (conv (load x)) -> (load (conv*)x) 3256 // If the resultant load doesn't need a higher alignment than the original! 3257 if (ISD::isNormalLoad(N0.Val) && N0.hasOneUse() && 3258 TLI.isOperationLegal(ISD::LOAD, VT)) { 3259 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3260 unsigned Align = TLI.getTargetMachine().getTargetData()-> 3261 getABITypeAlignment(MVT::getTypeForValueType(VT)); 3262 unsigned OrigAlign = LN0->getAlignment(); 3263 if (Align <= OrigAlign) { 3264 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(), 3265 LN0->getSrcValue(), LN0->getSrcValueOffset(), 3266 LN0->isVolatile(), Align); 3267 AddToWorkList(N); 3268 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load), 3269 Load.getValue(1)); 3270 return Load; 3271 } 3272 } 3273 3274 return SDOperand(); 3275} 3276 3277/// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector 3278/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 3279/// destination element value type. 3280SDOperand DAGCombiner:: 3281ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) { 3282 MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType(); 3283 3284 // If this is already the right type, we're done. 3285 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0); 3286 3287 unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT); 3288 unsigned DstBitSize = MVT::getSizeInBits(DstEltVT); 3289 3290 // If this is a conversion of N elements of one type to N elements of another 3291 // type, convert each element. This handles FP<->INT cases. 3292 if (SrcBitSize == DstBitSize) { 3293 SmallVector<SDOperand, 8> Ops; 3294 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3295 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i))); 3296 AddToWorkList(Ops.back().Val); 3297 } 3298 MVT::ValueType VT = 3299 MVT::getVectorType(DstEltVT, 3300 MVT::getVectorNumElements(BV->getValueType(0))); 3301 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3302 } 3303 3304 // Otherwise, we're growing or shrinking the elements. To avoid having to 3305 // handle annoying details of growing/shrinking FP values, we convert them to 3306 // int first. 3307 if (MVT::isFloatingPoint(SrcEltVT)) { 3308 // Convert the input float vector to a int vector where the elements are the 3309 // same sizes. 3310 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 3311 MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 3312 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).Val; 3313 SrcEltVT = IntVT; 3314 } 3315 3316 // Now we know the input is an integer vector. If the output is a FP type, 3317 // convert to integer first, then to FP of the right size. 3318 if (MVT::isFloatingPoint(DstEltVT)) { 3319 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 3320 MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 3321 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).Val; 3322 3323 // Next, convert to FP elements of the same size. 3324 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT); 3325 } 3326 3327 // Okay, we know the src/dst types are both integers of differing types. 3328 // Handling growing first. 3329 assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT)); 3330 if (SrcBitSize < DstBitSize) { 3331 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 3332 3333 SmallVector<SDOperand, 8> Ops; 3334 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 3335 i += NumInputsPerOutput) { 3336 bool isLE = TLI.isLittleEndian(); 3337 uint64_t NewBits = 0; 3338 bool EltIsUndef = true; 3339 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 3340 // Shift the previously computed bits over. 3341 NewBits <<= SrcBitSize; 3342 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 3343 if (Op.getOpcode() == ISD::UNDEF) continue; 3344 EltIsUndef = false; 3345 3346 NewBits |= cast<ConstantSDNode>(Op)->getValue(); 3347 } 3348 3349 if (EltIsUndef) 3350 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 3351 else 3352 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 3353 } 3354 3355 MVT::ValueType VT = MVT::getVectorType(DstEltVT, 3356 Ops.size()); 3357 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3358 } 3359 3360 // Finally, this must be the case where we are shrinking elements: each input 3361 // turns into multiple outputs. 3362 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 3363 SmallVector<SDOperand, 8> Ops; 3364 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3365 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 3366 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 3367 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 3368 continue; 3369 } 3370 uint64_t OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getValue(); 3371 3372 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 3373 unsigned ThisVal = OpVal & ((1ULL << DstBitSize)-1); 3374 OpVal >>= DstBitSize; 3375 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 3376 } 3377 3378 // For big endian targets, swap the order of the pieces of each element. 3379 if (!TLI.isLittleEndian()) 3380 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 3381 } 3382 MVT::ValueType VT = MVT::getVectorType(DstEltVT, Ops.size()); 3383 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3384} 3385 3386 3387 3388SDOperand DAGCombiner::visitFADD(SDNode *N) { 3389 SDOperand N0 = N->getOperand(0); 3390 SDOperand N1 = N->getOperand(1); 3391 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3392 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3393 MVT::ValueType VT = N->getValueType(0); 3394 3395 // fold vector ops 3396 if (MVT::isVector(VT)) { 3397 SDOperand FoldedVOp = SimplifyVBinOp(N); 3398 if (FoldedVOp.Val) return FoldedVOp; 3399 } 3400 3401 // fold (fadd c1, c2) -> c1+c2 3402 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3403 return DAG.getNode(ISD::FADD, VT, N0, N1); 3404 // canonicalize constant to RHS 3405 if (N0CFP && !N1CFP) 3406 return DAG.getNode(ISD::FADD, VT, N1, N0); 3407 // fold (A + (-B)) -> A-B 3408 if (isNegatibleForFree(N1) == 2) 3409 return DAG.getNode(ISD::FSUB, VT, N0, GetNegatedExpression(N1, DAG)); 3410 // fold ((-A) + B) -> B-A 3411 if (isNegatibleForFree(N0) == 2) 3412 return DAG.getNode(ISD::FSUB, VT, N1, GetNegatedExpression(N0, DAG)); 3413 3414 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 3415 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 3416 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3417 return DAG.getNode(ISD::FADD, VT, N0.getOperand(0), 3418 DAG.getNode(ISD::FADD, VT, N0.getOperand(1), N1)); 3419 3420 return SDOperand(); 3421} 3422 3423SDOperand DAGCombiner::visitFSUB(SDNode *N) { 3424 SDOperand N0 = N->getOperand(0); 3425 SDOperand N1 = N->getOperand(1); 3426 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3427 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3428 MVT::ValueType VT = N->getValueType(0); 3429 3430 // fold vector ops 3431 if (MVT::isVector(VT)) { 3432 SDOperand FoldedVOp = SimplifyVBinOp(N); 3433 if (FoldedVOp.Val) return FoldedVOp; 3434 } 3435 3436 // fold (fsub c1, c2) -> c1-c2 3437 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3438 return DAG.getNode(ISD::FSUB, VT, N0, N1); 3439 // fold (0-B) -> -B 3440 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { 3441 if (isNegatibleForFree(N1)) 3442 return GetNegatedExpression(N1, DAG); 3443 return DAG.getNode(ISD::FNEG, VT, N1); 3444 } 3445 // fold (A-(-B)) -> A+B 3446 if (isNegatibleForFree(N1)) 3447 return DAG.getNode(ISD::FADD, VT, N0, GetNegatedExpression(N1, DAG)); 3448 3449 return SDOperand(); 3450} 3451 3452SDOperand DAGCombiner::visitFMUL(SDNode *N) { 3453 SDOperand N0 = N->getOperand(0); 3454 SDOperand N1 = N->getOperand(1); 3455 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3456 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3457 MVT::ValueType VT = N->getValueType(0); 3458 3459 // fold vector ops 3460 if (MVT::isVector(VT)) { 3461 SDOperand FoldedVOp = SimplifyVBinOp(N); 3462 if (FoldedVOp.Val) return FoldedVOp; 3463 } 3464 3465 // fold (fmul c1, c2) -> c1*c2 3466 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3467 return DAG.getNode(ISD::FMUL, VT, N0, N1); 3468 // canonicalize constant to RHS 3469 if (N0CFP && !N1CFP) 3470 return DAG.getNode(ISD::FMUL, VT, N1, N0); 3471 // fold (fmul X, 2.0) -> (fadd X, X) 3472 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 3473 return DAG.getNode(ISD::FADD, VT, N0, N0); 3474 // fold (fmul X, -1.0) -> (fneg X) 3475 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 3476 return DAG.getNode(ISD::FNEG, VT, N0); 3477 3478 // -X * -Y -> X*Y 3479 if (char LHSNeg = isNegatibleForFree(N0)) { 3480 if (char RHSNeg = isNegatibleForFree(N1)) { 3481 // Both can be negated for free, check to see if at least one is cheaper 3482 // negated. 3483 if (LHSNeg == 2 || RHSNeg == 2) 3484 return DAG.getNode(ISD::FMUL, VT, GetNegatedExpression(N0, DAG), 3485 GetNegatedExpression(N1, DAG)); 3486 } 3487 } 3488 3489 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 3490 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 3491 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3492 return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0), 3493 DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1)); 3494 3495 return SDOperand(); 3496} 3497 3498SDOperand DAGCombiner::visitFDIV(SDNode *N) { 3499 SDOperand N0 = N->getOperand(0); 3500 SDOperand N1 = N->getOperand(1); 3501 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3502 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3503 MVT::ValueType VT = N->getValueType(0); 3504 3505 // fold vector ops 3506 if (MVT::isVector(VT)) { 3507 SDOperand FoldedVOp = SimplifyVBinOp(N); 3508 if (FoldedVOp.Val) return FoldedVOp; 3509 } 3510 3511 // fold (fdiv c1, c2) -> c1/c2 3512 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3513 return DAG.getNode(ISD::FDIV, VT, N0, N1); 3514 3515 3516 // -X / -Y -> X*Y 3517 if (char LHSNeg = isNegatibleForFree(N0)) { 3518 if (char RHSNeg = isNegatibleForFree(N1)) { 3519 // Both can be negated for free, check to see if at least one is cheaper 3520 // negated. 3521 if (LHSNeg == 2 || RHSNeg == 2) 3522 return DAG.getNode(ISD::FDIV, VT, GetNegatedExpression(N0, DAG), 3523 GetNegatedExpression(N1, DAG)); 3524 } 3525 } 3526 3527 return SDOperand(); 3528} 3529 3530SDOperand DAGCombiner::visitFREM(SDNode *N) { 3531 SDOperand N0 = N->getOperand(0); 3532 SDOperand N1 = N->getOperand(1); 3533 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3534 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3535 MVT::ValueType VT = N->getValueType(0); 3536 3537 // fold (frem c1, c2) -> fmod(c1,c2) 3538 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3539 return DAG.getNode(ISD::FREM, VT, N0, N1); 3540 3541 return SDOperand(); 3542} 3543 3544SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) { 3545 SDOperand N0 = N->getOperand(0); 3546 SDOperand N1 = N->getOperand(1); 3547 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3548 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3549 MVT::ValueType VT = N->getValueType(0); 3550 3551 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 3552 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1); 3553 3554 if (N1CFP) { 3555 const APFloat& V = N1CFP->getValueAPF(); 3556 // copysign(x, c1) -> fabs(x) iff ispos(c1) 3557 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 3558 if (!V.isNegative()) 3559 return DAG.getNode(ISD::FABS, VT, N0); 3560 else 3561 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0)); 3562 } 3563 3564 // copysign(fabs(x), y) -> copysign(x, y) 3565 // copysign(fneg(x), y) -> copysign(x, y) 3566 // copysign(copysign(x,z), y) -> copysign(x, y) 3567 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 3568 N0.getOpcode() == ISD::FCOPYSIGN) 3569 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1); 3570 3571 // copysign(x, abs(y)) -> abs(x) 3572 if (N1.getOpcode() == ISD::FABS) 3573 return DAG.getNode(ISD::FABS, VT, N0); 3574 3575 // copysign(x, copysign(y,z)) -> copysign(x, z) 3576 if (N1.getOpcode() == ISD::FCOPYSIGN) 3577 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1)); 3578 3579 // copysign(x, fp_extend(y)) -> copysign(x, y) 3580 // copysign(x, fp_round(y)) -> copysign(x, y) 3581 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 3582 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0)); 3583 3584 return SDOperand(); 3585} 3586 3587 3588 3589SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) { 3590 SDOperand N0 = N->getOperand(0); 3591 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3592 MVT::ValueType VT = N->getValueType(0); 3593 3594 // fold (sint_to_fp c1) -> c1fp 3595 if (N0C && N0.getValueType() != MVT::ppcf128) 3596 return DAG.getNode(ISD::SINT_TO_FP, VT, N0); 3597 return SDOperand(); 3598} 3599 3600SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) { 3601 SDOperand N0 = N->getOperand(0); 3602 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3603 MVT::ValueType VT = N->getValueType(0); 3604 3605 // fold (uint_to_fp c1) -> c1fp 3606 if (N0C && N0.getValueType() != MVT::ppcf128) 3607 return DAG.getNode(ISD::UINT_TO_FP, VT, N0); 3608 return SDOperand(); 3609} 3610 3611SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) { 3612 SDOperand N0 = N->getOperand(0); 3613 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3614 MVT::ValueType VT = N->getValueType(0); 3615 3616 // fold (fp_to_sint c1fp) -> c1 3617 if (N0CFP) 3618 return DAG.getNode(ISD::FP_TO_SINT, VT, N0); 3619 return SDOperand(); 3620} 3621 3622SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) { 3623 SDOperand N0 = N->getOperand(0); 3624 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3625 MVT::ValueType VT = N->getValueType(0); 3626 3627 // fold (fp_to_uint c1fp) -> c1 3628 if (N0CFP && VT != MVT::ppcf128) 3629 return DAG.getNode(ISD::FP_TO_UINT, VT, N0); 3630 return SDOperand(); 3631} 3632 3633SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) { 3634 SDOperand N0 = N->getOperand(0); 3635 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3636 MVT::ValueType VT = N->getValueType(0); 3637 3638 // fold (fp_round c1fp) -> c1fp 3639 if (N0CFP && N0.getValueType() != MVT::ppcf128) 3640 return DAG.getNode(ISD::FP_ROUND, VT, N0); 3641 3642 // fold (fp_round (fp_extend x)) -> x 3643 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 3644 return N0.getOperand(0); 3645 3646 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 3647 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) { 3648 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0)); 3649 AddToWorkList(Tmp.Val); 3650 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1)); 3651 } 3652 3653 return SDOperand(); 3654} 3655 3656SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 3657 SDOperand N0 = N->getOperand(0); 3658 MVT::ValueType VT = N->getValueType(0); 3659 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3660 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3661 3662 // fold (fp_round_inreg c1fp) -> c1fp 3663 if (N0CFP) { 3664 SDOperand Round = DAG.getConstantFP(N0CFP->getValueAPF(), EVT); 3665 return DAG.getNode(ISD::FP_EXTEND, VT, Round); 3666 } 3667 return SDOperand(); 3668} 3669 3670SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) { 3671 SDOperand N0 = N->getOperand(0); 3672 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3673 MVT::ValueType VT = N->getValueType(0); 3674 3675 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 3676 if (N->hasOneUse() && (*N->use_begin())->getOpcode() == ISD::FP_ROUND) 3677 return SDOperand(); 3678 3679 // fold (fp_extend c1fp) -> c1fp 3680 if (N0CFP && VT != MVT::ppcf128) 3681 return DAG.getNode(ISD::FP_EXTEND, VT, N0); 3682 3683 // fold (fpext (load x)) -> (fpext (fpround (extload x))) 3684 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 3685 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) { 3686 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3687 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 3688 LN0->getBasePtr(), LN0->getSrcValue(), 3689 LN0->getSrcValueOffset(), 3690 N0.getValueType(), 3691 LN0->isVolatile(), 3692 LN0->getAlignment()); 3693 CombineTo(N, ExtLoad); 3694 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad), 3695 ExtLoad.getValue(1)); 3696 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3697 } 3698 3699 3700 return SDOperand(); 3701} 3702 3703SDOperand DAGCombiner::visitFNEG(SDNode *N) { 3704 SDOperand N0 = N->getOperand(0); 3705 3706 if (isNegatibleForFree(N0)) 3707 return GetNegatedExpression(N0, DAG); 3708 3709 return SDOperand(); 3710} 3711 3712SDOperand DAGCombiner::visitFABS(SDNode *N) { 3713 SDOperand N0 = N->getOperand(0); 3714 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3715 MVT::ValueType VT = N->getValueType(0); 3716 3717 // fold (fabs c1) -> fabs(c1) 3718 if (N0CFP && VT != MVT::ppcf128) 3719 return DAG.getNode(ISD::FABS, VT, N0); 3720 // fold (fabs (fabs x)) -> (fabs x) 3721 if (N0.getOpcode() == ISD::FABS) 3722 return N->getOperand(0); 3723 // fold (fabs (fneg x)) -> (fabs x) 3724 // fold (fabs (fcopysign x, y)) -> (fabs x) 3725 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 3726 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0)); 3727 3728 return SDOperand(); 3729} 3730 3731SDOperand DAGCombiner::visitBRCOND(SDNode *N) { 3732 SDOperand Chain = N->getOperand(0); 3733 SDOperand N1 = N->getOperand(1); 3734 SDOperand N2 = N->getOperand(2); 3735 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3736 3737 // never taken branch, fold to chain 3738 if (N1C && N1C->isNullValue()) 3739 return Chain; 3740 // unconditional branch 3741 if (N1C && N1C->getValue() == 1) 3742 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 3743 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 3744 // on the target. 3745 if (N1.getOpcode() == ISD::SETCC && 3746 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) { 3747 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2), 3748 N1.getOperand(0), N1.getOperand(1), N2); 3749 } 3750 return SDOperand(); 3751} 3752 3753// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 3754// 3755SDOperand DAGCombiner::visitBR_CC(SDNode *N) { 3756 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 3757 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 3758 3759 // Use SimplifySetCC to simplify SETCC's. 3760 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false); 3761 if (Simp.Val) AddToWorkList(Simp.Val); 3762 3763 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val); 3764 3765 // fold br_cc true, dest -> br dest (unconditional branch) 3766 if (SCCC && SCCC->getValue()) 3767 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0), 3768 N->getOperand(4)); 3769 // fold br_cc false, dest -> unconditional fall through 3770 if (SCCC && SCCC->isNullValue()) 3771 return N->getOperand(0); 3772 3773 // fold to a simpler setcc 3774 if (Simp.Val && Simp.getOpcode() == ISD::SETCC) 3775 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0), 3776 Simp.getOperand(2), Simp.getOperand(0), 3777 Simp.getOperand(1), N->getOperand(4)); 3778 return SDOperand(); 3779} 3780 3781 3782/// CombineToPreIndexedLoadStore - Try turning a load / store and a 3783/// pre-indexed load / store when the base pointer is a add or subtract 3784/// and it has other uses besides the load / store. After the 3785/// transformation, the new indexed load / store has effectively folded 3786/// the add / subtract in and all of its other uses are redirected to the 3787/// new load / store. 3788bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 3789 if (!AfterLegalize) 3790 return false; 3791 3792 bool isLoad = true; 3793 SDOperand Ptr; 3794 MVT::ValueType VT; 3795 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 3796 if (LD->getAddressingMode() != ISD::UNINDEXED) 3797 return false; 3798 VT = LD->getLoadedVT(); 3799 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 3800 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 3801 return false; 3802 Ptr = LD->getBasePtr(); 3803 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 3804 if (ST->getAddressingMode() != ISD::UNINDEXED) 3805 return false; 3806 VT = ST->getStoredVT(); 3807 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 3808 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 3809 return false; 3810 Ptr = ST->getBasePtr(); 3811 isLoad = false; 3812 } else 3813 return false; 3814 3815 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 3816 // out. There is no reason to make this a preinc/predec. 3817 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 3818 Ptr.Val->hasOneUse()) 3819 return false; 3820 3821 // Ask the target to do addressing mode selection. 3822 SDOperand BasePtr; 3823 SDOperand Offset; 3824 ISD::MemIndexedMode AM = ISD::UNINDEXED; 3825 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 3826 return false; 3827 // Don't create a indexed load / store with zero offset. 3828 if (isa<ConstantSDNode>(Offset) && 3829 cast<ConstantSDNode>(Offset)->getValue() == 0) 3830 return false; 3831 3832 // Try turning it into a pre-indexed load / store except when: 3833 // 1) The new base ptr is a frame index. 3834 // 2) If N is a store and the new base ptr is either the same as or is a 3835 // predecessor of the value being stored. 3836 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 3837 // that would create a cycle. 3838 // 4) All uses are load / store ops that use it as old base ptr. 3839 3840 // Check #1. Preinc'ing a frame index would require copying the stack pointer 3841 // (plus the implicit offset) to a register to preinc anyway. 3842 if (isa<FrameIndexSDNode>(BasePtr)) 3843 return false; 3844 3845 // Check #2. 3846 if (!isLoad) { 3847 SDOperand Val = cast<StoreSDNode>(N)->getValue(); 3848 if (Val == BasePtr || BasePtr.Val->isPredecessor(Val.Val)) 3849 return false; 3850 } 3851 3852 // Now check for #3 and #4. 3853 bool RealUse = false; 3854 for (SDNode::use_iterator I = Ptr.Val->use_begin(), 3855 E = Ptr.Val->use_end(); I != E; ++I) { 3856 SDNode *Use = *I; 3857 if (Use == N) 3858 continue; 3859 if (Use->isPredecessor(N)) 3860 return false; 3861 3862 if (!((Use->getOpcode() == ISD::LOAD && 3863 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 3864 (Use->getOpcode() == ISD::STORE) && 3865 cast<StoreSDNode>(Use)->getBasePtr() == Ptr)) 3866 RealUse = true; 3867 } 3868 if (!RealUse) 3869 return false; 3870 3871 SDOperand Result; 3872 if (isLoad) 3873 Result = DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM); 3874 else 3875 Result = DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM); 3876 ++PreIndexedNodes; 3877 ++NodesCombined; 3878 DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG)); 3879 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG)); 3880 DOUT << '\n'; 3881 std::vector<SDNode*> NowDead; 3882 if (isLoad) { 3883 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0), 3884 &NowDead); 3885 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2), 3886 &NowDead); 3887 } else { 3888 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1), 3889 &NowDead); 3890 } 3891 3892 // Nodes can end up on the worklist more than once. Make sure we do 3893 // not process a node that has been replaced. 3894 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 3895 removeFromWorkList(NowDead[i]); 3896 // Finally, since the node is now dead, remove it from the graph. 3897 DAG.DeleteNode(N); 3898 3899 // Replace the uses of Ptr with uses of the updated base value. 3900 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 3901 &NowDead); 3902 removeFromWorkList(Ptr.Val); 3903 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 3904 removeFromWorkList(NowDead[i]); 3905 DAG.DeleteNode(Ptr.Val); 3906 3907 return true; 3908} 3909 3910/// CombineToPostIndexedLoadStore - Try combine a load / store with a 3911/// add / sub of the base pointer node into a post-indexed load / store. 3912/// The transformation folded the add / subtract into the new indexed 3913/// load / store effectively and all of its uses are redirected to the 3914/// new load / store. 3915bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 3916 if (!AfterLegalize) 3917 return false; 3918 3919 bool isLoad = true; 3920 SDOperand Ptr; 3921 MVT::ValueType VT; 3922 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 3923 if (LD->getAddressingMode() != ISD::UNINDEXED) 3924 return false; 3925 VT = LD->getLoadedVT(); 3926 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 3927 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 3928 return false; 3929 Ptr = LD->getBasePtr(); 3930 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 3931 if (ST->getAddressingMode() != ISD::UNINDEXED) 3932 return false; 3933 VT = ST->getStoredVT(); 3934 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 3935 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 3936 return false; 3937 Ptr = ST->getBasePtr(); 3938 isLoad = false; 3939 } else 3940 return false; 3941 3942 if (Ptr.Val->hasOneUse()) 3943 return false; 3944 3945 for (SDNode::use_iterator I = Ptr.Val->use_begin(), 3946 E = Ptr.Val->use_end(); I != E; ++I) { 3947 SDNode *Op = *I; 3948 if (Op == N || 3949 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 3950 continue; 3951 3952 SDOperand BasePtr; 3953 SDOperand Offset; 3954 ISD::MemIndexedMode AM = ISD::UNINDEXED; 3955 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 3956 if (Ptr == Offset) 3957 std::swap(BasePtr, Offset); 3958 if (Ptr != BasePtr) 3959 continue; 3960 // Don't create a indexed load / store with zero offset. 3961 if (isa<ConstantSDNode>(Offset) && 3962 cast<ConstantSDNode>(Offset)->getValue() == 0) 3963 continue; 3964 3965 // Try turning it into a post-indexed load / store except when 3966 // 1) All uses are load / store ops that use it as base ptr. 3967 // 2) Op must be independent of N, i.e. Op is neither a predecessor 3968 // nor a successor of N. Otherwise, if Op is folded that would 3969 // create a cycle. 3970 3971 // Check for #1. 3972 bool TryNext = false; 3973 for (SDNode::use_iterator II = BasePtr.Val->use_begin(), 3974 EE = BasePtr.Val->use_end(); II != EE; ++II) { 3975 SDNode *Use = *II; 3976 if (Use == Ptr.Val) 3977 continue; 3978 3979 // If all the uses are load / store addresses, then don't do the 3980 // transformation. 3981 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 3982 bool RealUse = false; 3983 for (SDNode::use_iterator III = Use->use_begin(), 3984 EEE = Use->use_end(); III != EEE; ++III) { 3985 SDNode *UseUse = *III; 3986 if (!((UseUse->getOpcode() == ISD::LOAD && 3987 cast<LoadSDNode>(UseUse)->getBasePtr().Val == Use) || 3988 (UseUse->getOpcode() == ISD::STORE) && 3989 cast<StoreSDNode>(UseUse)->getBasePtr().Val == Use)) 3990 RealUse = true; 3991 } 3992 3993 if (!RealUse) { 3994 TryNext = true; 3995 break; 3996 } 3997 } 3998 } 3999 if (TryNext) 4000 continue; 4001 4002 // Check for #2 4003 if (!Op->isPredecessor(N) && !N->isPredecessor(Op)) { 4004 SDOperand Result = isLoad 4005 ? DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM) 4006 : DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM); 4007 ++PostIndexedNodes; 4008 ++NodesCombined; 4009 DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG)); 4010 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG)); 4011 DOUT << '\n'; 4012 std::vector<SDNode*> NowDead; 4013 if (isLoad) { 4014 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0), 4015 &NowDead); 4016 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2), 4017 &NowDead); 4018 } else { 4019 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1), 4020 &NowDead); 4021 } 4022 4023 // Nodes can end up on the worklist more than once. Make sure we do 4024 // not process a node that has been replaced. 4025 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 4026 removeFromWorkList(NowDead[i]); 4027 // Finally, since the node is now dead, remove it from the graph. 4028 DAG.DeleteNode(N); 4029 4030 // Replace the uses of Use with uses of the updated base value. 4031 DAG.ReplaceAllUsesOfValueWith(SDOperand(Op, 0), 4032 Result.getValue(isLoad ? 1 : 0), 4033 &NowDead); 4034 removeFromWorkList(Op); 4035 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 4036 removeFromWorkList(NowDead[i]); 4037 DAG.DeleteNode(Op); 4038 4039 return true; 4040 } 4041 } 4042 } 4043 return false; 4044} 4045 4046 4047SDOperand DAGCombiner::visitLOAD(SDNode *N) { 4048 LoadSDNode *LD = cast<LoadSDNode>(N); 4049 SDOperand Chain = LD->getChain(); 4050 SDOperand Ptr = LD->getBasePtr(); 4051 4052 // If load is not volatile and there are no uses of the loaded value (and 4053 // the updated indexed value in case of indexed loads), change uses of the 4054 // chain value into uses of the chain input (i.e. delete the dead load). 4055 if (!LD->isVolatile()) { 4056 if (N->getValueType(1) == MVT::Other) { 4057 // Unindexed loads. 4058 if (N->hasNUsesOfValue(0, 0)) { 4059 // It's not safe to use the two value CombineTo variant here. e.g. 4060 // v1, chain2 = load chain1, loc 4061 // v2, chain3 = load chain2, loc 4062 // v3 = add v2, c 4063 // Now we replace use of v1 with undef, use of chain2 with chain1. 4064 // ReplaceAllUsesWith() will iterate through uses of the first load and 4065 // update operands: 4066 // v1, chain2 = load chain1, loc 4067 // v2, chain3 = load chain1, loc 4068 // v3 = add v2, c 4069 // Now the second load is the same as the first load, SelectionDAG cse 4070 // will ensure the use of second load is replaced with the first load. 4071 // v1, chain2 = load chain1, loc 4072 // v3 = add v1, c 4073 // Then v1 is replaced with undef and bad things happen. 4074 std::vector<SDNode*> NowDead; 4075 SDOperand Undef = DAG.getNode(ISD::UNDEF, N->getValueType(0)); 4076 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4077 DOUT << "\nWith: "; DEBUG(Undef.Val->dump(&DAG)); 4078 DOUT << " and 1 other value\n"; 4079 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Undef, &NowDead); 4080 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Chain, &NowDead); 4081 removeFromWorkList(N); 4082 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 4083 removeFromWorkList(NowDead[i]); 4084 DAG.DeleteNode(N); 4085 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 4086 } 4087 } else { 4088 // Indexed loads. 4089 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 4090 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 4091 std::vector<SDNode*> NowDead; 4092 SDOperand Undef = DAG.getNode(ISD::UNDEF, N->getValueType(0)); 4093 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4094 DOUT << "\nWith: "; DEBUG(Undef.Val->dump(&DAG)); 4095 DOUT << " and 2 other values\n"; 4096 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Undef, &NowDead); 4097 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), 4098 DAG.getNode(ISD::UNDEF, N->getValueType(1)), 4099 &NowDead); 4100 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 2), Chain, &NowDead); 4101 removeFromWorkList(N); 4102 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 4103 removeFromWorkList(NowDead[i]); 4104 DAG.DeleteNode(N); 4105 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 4106 } 4107 } 4108 } 4109 4110 // If this load is directly stored, replace the load value with the stored 4111 // value. 4112 // TODO: Handle store large -> read small portion. 4113 // TODO: Handle TRUNCSTORE/LOADEXT 4114 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 4115 if (ISD::isNON_TRUNCStore(Chain.Val)) { 4116 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 4117 if (PrevST->getBasePtr() == Ptr && 4118 PrevST->getValue().getValueType() == N->getValueType(0)) 4119 return CombineTo(N, Chain.getOperand(1), Chain); 4120 } 4121 } 4122 4123 if (CombinerAA) { 4124 // Walk up chain skipping non-aliasing memory nodes. 4125 SDOperand BetterChain = FindBetterChain(N, Chain); 4126 4127 // If there is a better chain. 4128 if (Chain != BetterChain) { 4129 SDOperand ReplLoad; 4130 4131 // Replace the chain to void dependency. 4132 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 4133 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr, 4134 LD->getSrcValue(), LD->getSrcValueOffset(), 4135 LD->isVolatile(), LD->getAlignment()); 4136 } else { 4137 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), 4138 LD->getValueType(0), 4139 BetterChain, Ptr, LD->getSrcValue(), 4140 LD->getSrcValueOffset(), 4141 LD->getLoadedVT(), 4142 LD->isVolatile(), 4143 LD->getAlignment()); 4144 } 4145 4146 // Create token factor to keep old chain connected. 4147 SDOperand Token = DAG.getNode(ISD::TokenFactor, MVT::Other, 4148 Chain, ReplLoad.getValue(1)); 4149 4150 // Replace uses with load result and token factor. Don't add users 4151 // to work list. 4152 return CombineTo(N, ReplLoad.getValue(0), Token, false); 4153 } 4154 } 4155 4156 // Try transforming N to an indexed load. 4157 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4158 return SDOperand(N, 0); 4159 4160 return SDOperand(); 4161} 4162 4163 4164SDOperand DAGCombiner::visitSTORE(SDNode *N) { 4165 StoreSDNode *ST = cast<StoreSDNode>(N); 4166 SDOperand Chain = ST->getChain(); 4167 SDOperand Value = ST->getValue(); 4168 SDOperand Ptr = ST->getBasePtr(); 4169 4170 // If this is a store of a bit convert, store the input value if the 4171 // resultant store does not need a higher alignment than the original. 4172 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() && 4173 ST->getAddressingMode() == ISD::UNINDEXED) { 4174 unsigned Align = ST->getAlignment(); 4175 MVT::ValueType SVT = Value.getOperand(0).getValueType(); 4176 unsigned OrigAlign = TLI.getTargetMachine().getTargetData()-> 4177 getABITypeAlignment(MVT::getTypeForValueType(SVT)); 4178 if (Align <= OrigAlign && TLI.isOperationLegal(ISD::STORE, SVT)) 4179 return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), 4180 ST->getSrcValueOffset(), ST->isVolatile(), Align); 4181 } 4182 4183 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 4184 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 4185 if (Value.getOpcode() != ISD::TargetConstantFP) { 4186 SDOperand Tmp; 4187 switch (CFP->getValueType(0)) { 4188 default: assert(0 && "Unknown FP type"); 4189 case MVT::f80: // We don't do this for these yet. 4190 case MVT::f128: 4191 case MVT::ppcf128: 4192 break; 4193 case MVT::f32: 4194 if (!AfterLegalize || TLI.isTypeLegal(MVT::i32)) { 4195 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 4196 convertToAPInt().getZExtValue(), MVT::i32); 4197 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 4198 ST->getSrcValueOffset(), ST->isVolatile(), 4199 ST->getAlignment()); 4200 } 4201 break; 4202 case MVT::f64: 4203 if (!AfterLegalize || TLI.isTypeLegal(MVT::i64)) { 4204 Tmp = DAG.getConstant(CFP->getValueAPF().convertToAPInt(). 4205 getZExtValue(), MVT::i64); 4206 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 4207 ST->getSrcValueOffset(), ST->isVolatile(), 4208 ST->getAlignment()); 4209 } else if (TLI.isTypeLegal(MVT::i32)) { 4210 // Many FP stores are not made apparent until after legalize, e.g. for 4211 // argument passing. Since this is so common, custom legalize the 4212 // 64-bit integer store into two 32-bit stores. 4213 uint64_t Val = CFP->getValueAPF().convertToAPInt().getZExtValue(); 4214 SDOperand Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 4215 SDOperand Hi = DAG.getConstant(Val >> 32, MVT::i32); 4216 if (!TLI.isLittleEndian()) std::swap(Lo, Hi); 4217 4218 int SVOffset = ST->getSrcValueOffset(); 4219 unsigned Alignment = ST->getAlignment(); 4220 bool isVolatile = ST->isVolatile(); 4221 4222 SDOperand St0 = DAG.getStore(Chain, Lo, Ptr, ST->getSrcValue(), 4223 ST->getSrcValueOffset(), 4224 isVolatile, ST->getAlignment()); 4225 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 4226 DAG.getConstant(4, Ptr.getValueType())); 4227 SVOffset += 4; 4228 Alignment = MinAlign(Alignment, 4U); 4229 SDOperand St1 = DAG.getStore(Chain, Hi, Ptr, ST->getSrcValue(), 4230 SVOffset, isVolatile, Alignment); 4231 return DAG.getNode(ISD::TokenFactor, MVT::Other, St0, St1); 4232 } 4233 break; 4234 } 4235 } 4236 } 4237 4238 if (CombinerAA) { 4239 // Walk up chain skipping non-aliasing memory nodes. 4240 SDOperand BetterChain = FindBetterChain(N, Chain); 4241 4242 // If there is a better chain. 4243 if (Chain != BetterChain) { 4244 // Replace the chain to avoid dependency. 4245 SDOperand ReplStore; 4246 if (ST->isTruncatingStore()) { 4247 ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr, 4248 ST->getSrcValue(), ST->getSrcValueOffset(), ST->getStoredVT(), 4249 ST->isVolatile(), ST->getAlignment()); 4250 } else { 4251 ReplStore = DAG.getStore(BetterChain, Value, Ptr, 4252 ST->getSrcValue(), ST->getSrcValueOffset(), 4253 ST->isVolatile(), ST->getAlignment()); 4254 } 4255 4256 // Create token to keep both nodes around. 4257 SDOperand Token = 4258 DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore); 4259 4260 // Don't add users to work list. 4261 return CombineTo(N, Token, false); 4262 } 4263 } 4264 4265 // Try transforming N to an indexed store. 4266 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4267 return SDOperand(N, 0); 4268 4269 // FIXME: is there such a thing as a truncating indexed store? 4270 if (ST->isTruncatingStore() && ST->getAddressingMode() == ISD::UNINDEXED && 4271 MVT::isInteger(Value.getValueType())) { 4272 // See if we can simplify the input to this truncstore with knowledge that 4273 // only the low bits are being used. For example: 4274 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 4275 SDOperand Shorter = 4276 GetDemandedBits(Value, MVT::getIntVTBitMask(ST->getStoredVT())); 4277 AddToWorkList(Value.Val); 4278 if (Shorter.Val) 4279 return DAG.getTruncStore(Chain, Shorter, Ptr, ST->getSrcValue(), 4280 ST->getSrcValueOffset(), ST->getStoredVT(), 4281 ST->isVolatile(), ST->getAlignment()); 4282 4283 // Otherwise, see if we can simplify the operation with 4284 // SimplifyDemandedBits, which only works if the value has a single use. 4285 if (SimplifyDemandedBits(Value, MVT::getIntVTBitMask(ST->getStoredVT()))) 4286 return SDOperand(N, 0); 4287 } 4288 4289 // If this is a load followed by a store to the same location, then the store 4290 // is dead/noop. 4291 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 4292 if (Ld->getBasePtr() == Ptr && ST->getStoredVT() == Ld->getLoadedVT() && 4293 ST->getAddressingMode() == ISD::UNINDEXED && 4294 !ST->isVolatile() && 4295 // There can't be any side effects between the load and store, such as 4296 // a call or store. 4297 Chain.reachesChainWithoutSideEffects(SDOperand(Ld, 1))) { 4298 // The store is dead, remove it. 4299 return Chain; 4300 } 4301 } 4302 4303 return SDOperand(); 4304} 4305 4306SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 4307 SDOperand InVec = N->getOperand(0); 4308 SDOperand InVal = N->getOperand(1); 4309 SDOperand EltNo = N->getOperand(2); 4310 4311 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 4312 // vector with the inserted element. 4313 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 4314 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 4315 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end()); 4316 if (Elt < Ops.size()) 4317 Ops[Elt] = InVal; 4318 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(), 4319 &Ops[0], Ops.size()); 4320 } 4321 4322 return SDOperand(); 4323} 4324 4325SDOperand DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 4326 SDOperand InVec = N->getOperand(0); 4327 SDOperand EltNo = N->getOperand(1); 4328 4329 // (vextract (v4f32 s2v (f32 load $addr)), 0) -> (f32 load $addr) 4330 // (vextract (v4i32 bc (v4f32 s2v (f32 load $addr))), 0) -> (i32 load $addr) 4331 if (isa<ConstantSDNode>(EltNo)) { 4332 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 4333 bool NewLoad = false; 4334 if (Elt == 0) { 4335 MVT::ValueType VT = InVec.getValueType(); 4336 MVT::ValueType EVT = MVT::getVectorElementType(VT); 4337 MVT::ValueType LVT = EVT; 4338 unsigned NumElts = MVT::getVectorNumElements(VT); 4339 if (InVec.getOpcode() == ISD::BIT_CONVERT) { 4340 MVT::ValueType BCVT = InVec.getOperand(0).getValueType(); 4341 if (!MVT::isVector(BCVT) || 4342 NumElts != MVT::getVectorNumElements(BCVT)) 4343 return SDOperand(); 4344 InVec = InVec.getOperand(0); 4345 EVT = MVT::getVectorElementType(BCVT); 4346 NewLoad = true; 4347 } 4348 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 4349 InVec.getOperand(0).getValueType() == EVT && 4350 ISD::isNormalLoad(InVec.getOperand(0).Val) && 4351 InVec.getOperand(0).hasOneUse()) { 4352 LoadSDNode *LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 4353 unsigned Align = LN0->getAlignment(); 4354 if (NewLoad) { 4355 // Check the resultant load doesn't need a higher alignment than the 4356 // original load. 4357 unsigned NewAlign = TLI.getTargetMachine().getTargetData()-> 4358 getABITypeAlignment(MVT::getTypeForValueType(LVT)); 4359 if (!TLI.isOperationLegal(ISD::LOAD, LVT) || NewAlign > Align) 4360 return SDOperand(); 4361 Align = NewAlign; 4362 } 4363 4364 return DAG.getLoad(LVT, LN0->getChain(), LN0->getBasePtr(), 4365 LN0->getSrcValue(), LN0->getSrcValueOffset(), 4366 LN0->isVolatile(), Align); 4367 } 4368 } 4369 } 4370 return SDOperand(); 4371} 4372 4373 4374SDOperand DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 4375 unsigned NumInScalars = N->getNumOperands(); 4376 MVT::ValueType VT = N->getValueType(0); 4377 unsigned NumElts = MVT::getVectorNumElements(VT); 4378 MVT::ValueType EltType = MVT::getVectorElementType(VT); 4379 4380 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 4381 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 4382 // at most two distinct vectors, turn this into a shuffle node. 4383 SDOperand VecIn1, VecIn2; 4384 for (unsigned i = 0; i != NumInScalars; ++i) { 4385 // Ignore undef inputs. 4386 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 4387 4388 // If this input is something other than a EXTRACT_VECTOR_ELT with a 4389 // constant index, bail out. 4390 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 4391 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 4392 VecIn1 = VecIn2 = SDOperand(0, 0); 4393 break; 4394 } 4395 4396 // If the input vector type disagrees with the result of the build_vector, 4397 // we can't make a shuffle. 4398 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0); 4399 if (ExtractedFromVec.getValueType() != VT) { 4400 VecIn1 = VecIn2 = SDOperand(0, 0); 4401 break; 4402 } 4403 4404 // Otherwise, remember this. We allow up to two distinct input vectors. 4405 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 4406 continue; 4407 4408 if (VecIn1.Val == 0) { 4409 VecIn1 = ExtractedFromVec; 4410 } else if (VecIn2.Val == 0) { 4411 VecIn2 = ExtractedFromVec; 4412 } else { 4413 // Too many inputs. 4414 VecIn1 = VecIn2 = SDOperand(0, 0); 4415 break; 4416 } 4417 } 4418 4419 // If everything is good, we can make a shuffle operation. 4420 if (VecIn1.Val) { 4421 SmallVector<SDOperand, 8> BuildVecIndices; 4422 for (unsigned i = 0; i != NumInScalars; ++i) { 4423 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 4424 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, TLI.getPointerTy())); 4425 continue; 4426 } 4427 4428 SDOperand Extract = N->getOperand(i); 4429 4430 // If extracting from the first vector, just use the index directly. 4431 if (Extract.getOperand(0) == VecIn1) { 4432 BuildVecIndices.push_back(Extract.getOperand(1)); 4433 continue; 4434 } 4435 4436 // Otherwise, use InIdx + VecSize 4437 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue(); 4438 BuildVecIndices.push_back(DAG.getConstant(Idx+NumInScalars, 4439 TLI.getPointerTy())); 4440 } 4441 4442 // Add count and size info. 4443 MVT::ValueType BuildVecVT = 4444 MVT::getVectorType(TLI.getPointerTy(), NumElts); 4445 4446 // Return the new VECTOR_SHUFFLE node. 4447 SDOperand Ops[5]; 4448 Ops[0] = VecIn1; 4449 if (VecIn2.Val) { 4450 Ops[1] = VecIn2; 4451 } else { 4452 // Use an undef build_vector as input for the second operand. 4453 std::vector<SDOperand> UnOps(NumInScalars, 4454 DAG.getNode(ISD::UNDEF, 4455 EltType)); 4456 Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, VT, 4457 &UnOps[0], UnOps.size()); 4458 AddToWorkList(Ops[1].Val); 4459 } 4460 Ops[2] = DAG.getNode(ISD::BUILD_VECTOR, BuildVecVT, 4461 &BuildVecIndices[0], BuildVecIndices.size()); 4462 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Ops, 3); 4463 } 4464 4465 return SDOperand(); 4466} 4467 4468SDOperand DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 4469 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 4470 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 4471 // inputs come from at most two distinct vectors, turn this into a shuffle 4472 // node. 4473 4474 // If we only have one input vector, we don't need to do any concatenation. 4475 if (N->getNumOperands() == 1) { 4476 return N->getOperand(0); 4477 } 4478 4479 return SDOperand(); 4480} 4481 4482SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 4483 SDOperand ShufMask = N->getOperand(2); 4484 unsigned NumElts = ShufMask.getNumOperands(); 4485 4486 // If the shuffle mask is an identity operation on the LHS, return the LHS. 4487 bool isIdentity = true; 4488 for (unsigned i = 0; i != NumElts; ++i) { 4489 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 4490 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) { 4491 isIdentity = false; 4492 break; 4493 } 4494 } 4495 if (isIdentity) return N->getOperand(0); 4496 4497 // If the shuffle mask is an identity operation on the RHS, return the RHS. 4498 isIdentity = true; 4499 for (unsigned i = 0; i != NumElts; ++i) { 4500 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 4501 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) { 4502 isIdentity = false; 4503 break; 4504 } 4505 } 4506 if (isIdentity) return N->getOperand(1); 4507 4508 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not 4509 // needed at all. 4510 bool isUnary = true; 4511 bool isSplat = true; 4512 int VecNum = -1; 4513 unsigned BaseIdx = 0; 4514 for (unsigned i = 0; i != NumElts; ++i) 4515 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) { 4516 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue(); 4517 int V = (Idx < NumElts) ? 0 : 1; 4518 if (VecNum == -1) { 4519 VecNum = V; 4520 BaseIdx = Idx; 4521 } else { 4522 if (BaseIdx != Idx) 4523 isSplat = false; 4524 if (VecNum != V) { 4525 isUnary = false; 4526 break; 4527 } 4528 } 4529 } 4530 4531 SDOperand N0 = N->getOperand(0); 4532 SDOperand N1 = N->getOperand(1); 4533 // Normalize unary shuffle so the RHS is undef. 4534 if (isUnary && VecNum == 1) 4535 std::swap(N0, N1); 4536 4537 // If it is a splat, check if the argument vector is a build_vector with 4538 // all scalar elements the same. 4539 if (isSplat) { 4540 SDNode *V = N0.Val; 4541 4542 // If this is a bit convert that changes the element type of the vector but 4543 // not the number of vector elements, look through it. Be careful not to 4544 // look though conversions that change things like v4f32 to v2f64. 4545 if (V->getOpcode() == ISD::BIT_CONVERT) { 4546 SDOperand ConvInput = V->getOperand(0); 4547 if (MVT::getVectorNumElements(ConvInput.getValueType()) == NumElts) 4548 V = ConvInput.Val; 4549 } 4550 4551 if (V->getOpcode() == ISD::BUILD_VECTOR) { 4552 unsigned NumElems = V->getNumOperands(); 4553 if (NumElems > BaseIdx) { 4554 SDOperand Base; 4555 bool AllSame = true; 4556 for (unsigned i = 0; i != NumElems; ++i) { 4557 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 4558 Base = V->getOperand(i); 4559 break; 4560 } 4561 } 4562 // Splat of <u, u, u, u>, return <u, u, u, u> 4563 if (!Base.Val) 4564 return N0; 4565 for (unsigned i = 0; i != NumElems; ++i) { 4566 if (V->getOperand(i) != Base) { 4567 AllSame = false; 4568 break; 4569 } 4570 } 4571 // Splat of <x, x, x, x>, return <x, x, x, x> 4572 if (AllSame) 4573 return N0; 4574 } 4575 } 4576 } 4577 4578 // If it is a unary or the LHS and the RHS are the same node, turn the RHS 4579 // into an undef. 4580 if (isUnary || N0 == N1) { 4581 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the 4582 // first operand. 4583 SmallVector<SDOperand, 8> MappedOps; 4584 for (unsigned i = 0; i != NumElts; ++i) { 4585 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || 4586 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) { 4587 MappedOps.push_back(ShufMask.getOperand(i)); 4588 } else { 4589 unsigned NewIdx = 4590 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts; 4591 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32)); 4592 } 4593 } 4594 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(), 4595 &MappedOps[0], MappedOps.size()); 4596 AddToWorkList(ShufMask.Val); 4597 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0), 4598 N0, 4599 DAG.getNode(ISD::UNDEF, N->getValueType(0)), 4600 ShufMask); 4601 } 4602 4603 return SDOperand(); 4604} 4605 4606/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 4607/// an AND to a vector_shuffle with the destination vector and a zero vector. 4608/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 4609/// vector_shuffle V, Zero, <0, 4, 2, 4> 4610SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) { 4611 SDOperand LHS = N->getOperand(0); 4612 SDOperand RHS = N->getOperand(1); 4613 if (N->getOpcode() == ISD::AND) { 4614 if (RHS.getOpcode() == ISD::BIT_CONVERT) 4615 RHS = RHS.getOperand(0); 4616 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 4617 std::vector<SDOperand> IdxOps; 4618 unsigned NumOps = RHS.getNumOperands(); 4619 unsigned NumElts = NumOps; 4620 MVT::ValueType EVT = MVT::getVectorElementType(RHS.getValueType()); 4621 for (unsigned i = 0; i != NumElts; ++i) { 4622 SDOperand Elt = RHS.getOperand(i); 4623 if (!isa<ConstantSDNode>(Elt)) 4624 return SDOperand(); 4625 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 4626 IdxOps.push_back(DAG.getConstant(i, EVT)); 4627 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 4628 IdxOps.push_back(DAG.getConstant(NumElts, EVT)); 4629 else 4630 return SDOperand(); 4631 } 4632 4633 // Let's see if the target supports this vector_shuffle. 4634 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG)) 4635 return SDOperand(); 4636 4637 // Return the new VECTOR_SHUFFLE node. 4638 MVT::ValueType VT = MVT::getVectorType(EVT, NumElts); 4639 std::vector<SDOperand> Ops; 4640 LHS = DAG.getNode(ISD::BIT_CONVERT, VT, LHS); 4641 Ops.push_back(LHS); 4642 AddToWorkList(LHS.Val); 4643 std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT)); 4644 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT, 4645 &ZeroOps[0], ZeroOps.size())); 4646 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT, 4647 &IdxOps[0], IdxOps.size())); 4648 SDOperand Result = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, 4649 &Ops[0], Ops.size()); 4650 if (VT != LHS.getValueType()) { 4651 Result = DAG.getNode(ISD::BIT_CONVERT, LHS.getValueType(), Result); 4652 } 4653 return Result; 4654 } 4655 } 4656 return SDOperand(); 4657} 4658 4659/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 4660SDOperand DAGCombiner::SimplifyVBinOp(SDNode *N) { 4661 // After legalize, the target may be depending on adds and other 4662 // binary ops to provide legal ways to construct constants or other 4663 // things. Simplifying them may result in a loss of legality. 4664 if (AfterLegalize) return SDOperand(); 4665 4666 MVT::ValueType VT = N->getValueType(0); 4667 assert(MVT::isVector(VT) && "SimplifyVBinOp only works on vectors!"); 4668 4669 MVT::ValueType EltType = MVT::getVectorElementType(VT); 4670 SDOperand LHS = N->getOperand(0); 4671 SDOperand RHS = N->getOperand(1); 4672 SDOperand Shuffle = XformToShuffleWithZero(N); 4673 if (Shuffle.Val) return Shuffle; 4674 4675 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 4676 // this operation. 4677 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 4678 RHS.getOpcode() == ISD::BUILD_VECTOR) { 4679 SmallVector<SDOperand, 8> Ops; 4680 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 4681 SDOperand LHSOp = LHS.getOperand(i); 4682 SDOperand RHSOp = RHS.getOperand(i); 4683 // If these two elements can't be folded, bail out. 4684 if ((LHSOp.getOpcode() != ISD::UNDEF && 4685 LHSOp.getOpcode() != ISD::Constant && 4686 LHSOp.getOpcode() != ISD::ConstantFP) || 4687 (RHSOp.getOpcode() != ISD::UNDEF && 4688 RHSOp.getOpcode() != ISD::Constant && 4689 RHSOp.getOpcode() != ISD::ConstantFP)) 4690 break; 4691 // Can't fold divide by zero. 4692 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 4693 N->getOpcode() == ISD::FDIV) { 4694 if ((RHSOp.getOpcode() == ISD::Constant && 4695 cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) || 4696 (RHSOp.getOpcode() == ISD::ConstantFP && 4697 cast<ConstantFPSDNode>(RHSOp.Val)->getValueAPF().isZero())) 4698 break; 4699 } 4700 Ops.push_back(DAG.getNode(N->getOpcode(), EltType, LHSOp, RHSOp)); 4701 AddToWorkList(Ops.back().Val); 4702 assert((Ops.back().getOpcode() == ISD::UNDEF || 4703 Ops.back().getOpcode() == ISD::Constant || 4704 Ops.back().getOpcode() == ISD::ConstantFP) && 4705 "Scalar binop didn't fold!"); 4706 } 4707 4708 if (Ops.size() == LHS.getNumOperands()) { 4709 MVT::ValueType VT = LHS.getValueType(); 4710 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 4711 } 4712 } 4713 4714 return SDOperand(); 4715} 4716 4717SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){ 4718 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 4719 4720 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2, 4721 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4722 // If we got a simplified select_cc node back from SimplifySelectCC, then 4723 // break it down into a new SETCC node, and a new SELECT node, and then return 4724 // the SELECT node, since we were called with a SELECT node. 4725 if (SCC.Val) { 4726 // Check to see if we got a select_cc back (to turn into setcc/select). 4727 // Otherwise, just return whatever node we got back, like fabs. 4728 if (SCC.getOpcode() == ISD::SELECT_CC) { 4729 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(), 4730 SCC.getOperand(0), SCC.getOperand(1), 4731 SCC.getOperand(4)); 4732 AddToWorkList(SETCC.Val); 4733 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2), 4734 SCC.getOperand(3), SETCC); 4735 } 4736 return SCC; 4737 } 4738 return SDOperand(); 4739} 4740 4741/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 4742/// are the two values being selected between, see if we can simplify the 4743/// select. Callers of this should assume that TheSelect is deleted if this 4744/// returns true. As such, they should return the appropriate thing (e.g. the 4745/// node) back to the top-level of the DAG combiner loop to avoid it being 4746/// looked at. 4747/// 4748bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS, 4749 SDOperand RHS) { 4750 4751 // If this is a select from two identical things, try to pull the operation 4752 // through the select. 4753 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 4754 // If this is a load and the token chain is identical, replace the select 4755 // of two loads with a load through a select of the address to load from. 4756 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 4757 // constants have been dropped into the constant pool. 4758 if (LHS.getOpcode() == ISD::LOAD && 4759 // Token chains must be identical. 4760 LHS.getOperand(0) == RHS.getOperand(0)) { 4761 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 4762 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 4763 4764 // If this is an EXTLOAD, the VT's must match. 4765 if (LLD->getLoadedVT() == RLD->getLoadedVT()) { 4766 // FIXME: this conflates two src values, discarding one. This is not 4767 // the right thing to do, but nothing uses srcvalues now. When they do, 4768 // turn SrcValue into a list of locations. 4769 SDOperand Addr; 4770 if (TheSelect->getOpcode() == ISD::SELECT) { 4771 // Check that the condition doesn't reach either load. If so, folding 4772 // this will induce a cycle into the DAG. 4773 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) && 4774 !RLD->isPredecessor(TheSelect->getOperand(0).Val)) { 4775 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(), 4776 TheSelect->getOperand(0), LLD->getBasePtr(), 4777 RLD->getBasePtr()); 4778 } 4779 } else { 4780 // Check that the condition doesn't reach either load. If so, folding 4781 // this will induce a cycle into the DAG. 4782 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) && 4783 !RLD->isPredecessor(TheSelect->getOperand(0).Val) && 4784 !LLD->isPredecessor(TheSelect->getOperand(1).Val) && 4785 !RLD->isPredecessor(TheSelect->getOperand(1).Val)) { 4786 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(), 4787 TheSelect->getOperand(0), 4788 TheSelect->getOperand(1), 4789 LLD->getBasePtr(), RLD->getBasePtr(), 4790 TheSelect->getOperand(4)); 4791 } 4792 } 4793 4794 if (Addr.Val) { 4795 SDOperand Load; 4796 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) 4797 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(), 4798 Addr,LLD->getSrcValue(), 4799 LLD->getSrcValueOffset(), 4800 LLD->isVolatile(), 4801 LLD->getAlignment()); 4802 else { 4803 Load = DAG.getExtLoad(LLD->getExtensionType(), 4804 TheSelect->getValueType(0), 4805 LLD->getChain(), Addr, LLD->getSrcValue(), 4806 LLD->getSrcValueOffset(), 4807 LLD->getLoadedVT(), 4808 LLD->isVolatile(), 4809 LLD->getAlignment()); 4810 } 4811 // Users of the select now use the result of the load. 4812 CombineTo(TheSelect, Load); 4813 4814 // Users of the old loads now use the new load's chain. We know the 4815 // old-load value is dead now. 4816 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1)); 4817 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1)); 4818 return true; 4819 } 4820 } 4821 } 4822 } 4823 4824 return false; 4825} 4826 4827SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1, 4828 SDOperand N2, SDOperand N3, 4829 ISD::CondCode CC, bool NotExtCompare) { 4830 4831 MVT::ValueType VT = N2.getValueType(); 4832 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 4833 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 4834 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 4835 4836 // Determine if the condition we're dealing with is constant 4837 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 4838 if (SCC.Val) AddToWorkList(SCC.Val); 4839 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 4840 4841 // fold select_cc true, x, y -> x 4842 if (SCCC && SCCC->getValue()) 4843 return N2; 4844 // fold select_cc false, x, y -> y 4845 if (SCCC && SCCC->getValue() == 0) 4846 return N3; 4847 4848 // Check to see if we can simplify the select into an fabs node 4849 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 4850 // Allow either -0.0 or 0.0 4851 if (CFP->getValueAPF().isZero()) { 4852 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 4853 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 4854 N0 == N2 && N3.getOpcode() == ISD::FNEG && 4855 N2 == N3.getOperand(0)) 4856 return DAG.getNode(ISD::FABS, VT, N0); 4857 4858 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 4859 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 4860 N0 == N3 && N2.getOpcode() == ISD::FNEG && 4861 N2.getOperand(0) == N3) 4862 return DAG.getNode(ISD::FABS, VT, N3); 4863 } 4864 } 4865 4866 // Check to see if we can perform the "gzip trick", transforming 4867 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 4868 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 4869 MVT::isInteger(N0.getValueType()) && 4870 MVT::isInteger(N2.getValueType()) && 4871 (N1C->isNullValue() || // (a < 0) ? b : 0 4872 (N1C->getValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 4873 MVT::ValueType XType = N0.getValueType(); 4874 MVT::ValueType AType = N2.getValueType(); 4875 if (XType >= AType) { 4876 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 4877 // single-bit constant. 4878 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) { 4879 unsigned ShCtV = Log2_64(N2C->getValue()); 4880 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1; 4881 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy()); 4882 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt); 4883 AddToWorkList(Shift.Val); 4884 if (XType > AType) { 4885 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 4886 AddToWorkList(Shift.Val); 4887 } 4888 return DAG.getNode(ISD::AND, AType, Shift, N2); 4889 } 4890 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 4891 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4892 TLI.getShiftAmountTy())); 4893 AddToWorkList(Shift.Val); 4894 if (XType > AType) { 4895 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 4896 AddToWorkList(Shift.Val); 4897 } 4898 return DAG.getNode(ISD::AND, AType, Shift, N2); 4899 } 4900 } 4901 4902 // fold select C, 16, 0 -> shl C, 4 4903 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) && 4904 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) { 4905 4906 // If the caller doesn't want us to simplify this into a zext of a compare, 4907 // don't do it. 4908 if (NotExtCompare && N2C->getValue() == 1) 4909 return SDOperand(); 4910 4911 // Get a SetCC of the condition 4912 // FIXME: Should probably make sure that setcc is legal if we ever have a 4913 // target where it isn't. 4914 SDOperand Temp, SCC; 4915 // cast from setcc result type to select result type 4916 if (AfterLegalize) { 4917 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 4918 if (N2.getValueType() < SCC.getValueType()) 4919 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType()); 4920 else 4921 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 4922 } else { 4923 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC); 4924 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 4925 } 4926 AddToWorkList(SCC.Val); 4927 AddToWorkList(Temp.Val); 4928 4929 if (N2C->getValue() == 1) 4930 return Temp; 4931 // shl setcc result by log2 n2c 4932 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp, 4933 DAG.getConstant(Log2_64(N2C->getValue()), 4934 TLI.getShiftAmountTy())); 4935 } 4936 4937 // Check to see if this is the equivalent of setcc 4938 // FIXME: Turn all of these into setcc if setcc if setcc is legal 4939 // otherwise, go ahead with the folds. 4940 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) { 4941 MVT::ValueType XType = N0.getValueType(); 4942 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) { 4943 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 4944 if (Res.getValueType() != VT) 4945 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res); 4946 return Res; 4947 } 4948 4949 // seteq X, 0 -> srl (ctlz X, log2(size(X))) 4950 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 4951 TLI.isOperationLegal(ISD::CTLZ, XType)) { 4952 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0); 4953 return DAG.getNode(ISD::SRL, XType, Ctlz, 4954 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)), 4955 TLI.getShiftAmountTy())); 4956 } 4957 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) 4958 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 4959 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType), 4960 N0); 4961 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0, 4962 DAG.getConstant(~0ULL, XType)); 4963 return DAG.getNode(ISD::SRL, XType, 4964 DAG.getNode(ISD::AND, XType, NegN0, NotN0), 4965 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4966 TLI.getShiftAmountTy())); 4967 } 4968 // setgt X, -1 -> xor (srl (X, size(X)-1), 1) 4969 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 4970 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0, 4971 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4972 TLI.getShiftAmountTy())); 4973 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType)); 4974 } 4975 } 4976 4977 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 4978 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 4979 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 4980 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) && 4981 N2.getOperand(0) == N1 && MVT::isInteger(N0.getValueType())) { 4982 MVT::ValueType XType = N0.getValueType(); 4983 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 4984 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4985 TLI.getShiftAmountTy())); 4986 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 4987 AddToWorkList(Shift.Val); 4988 AddToWorkList(Add.Val); 4989 return DAG.getNode(ISD::XOR, XType, Add, Shift); 4990 } 4991 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X -> 4992 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 4993 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT && 4994 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) { 4995 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 4996 MVT::ValueType XType = N0.getValueType(); 4997 if (SubC->isNullValue() && MVT::isInteger(XType)) { 4998 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 4999 DAG.getConstant(MVT::getSizeInBits(XType)-1, 5000 TLI.getShiftAmountTy())); 5001 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 5002 AddToWorkList(Shift.Val); 5003 AddToWorkList(Add.Val); 5004 return DAG.getNode(ISD::XOR, XType, Add, Shift); 5005 } 5006 } 5007 } 5008 5009 return SDOperand(); 5010} 5011 5012/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 5013SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0, 5014 SDOperand N1, ISD::CondCode Cond, 5015 bool foldBooleans) { 5016 TargetLowering::DAGCombinerInfo 5017 DagCombineInfo(DAG, !AfterLegalize, false, this); 5018 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo); 5019} 5020 5021/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 5022/// return a DAG expression to select that will generate the same value by 5023/// multiplying by a magic number. See: 5024/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 5025SDOperand DAGCombiner::BuildSDIV(SDNode *N) { 5026 std::vector<SDNode*> Built; 5027 SDOperand S = TLI.BuildSDIV(N, DAG, &Built); 5028 5029 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 5030 ii != ee; ++ii) 5031 AddToWorkList(*ii); 5032 return S; 5033} 5034 5035/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 5036/// return a DAG expression to select that will generate the same value by 5037/// multiplying by a magic number. See: 5038/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 5039SDOperand DAGCombiner::BuildUDIV(SDNode *N) { 5040 std::vector<SDNode*> Built; 5041 SDOperand S = TLI.BuildUDIV(N, DAG, &Built); 5042 5043 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 5044 ii != ee; ++ii) 5045 AddToWorkList(*ii); 5046 return S; 5047} 5048 5049/// FindBaseOffset - Return true if base is known not to alias with anything 5050/// but itself. Provides base object and offset as results. 5051static bool FindBaseOffset(SDOperand Ptr, SDOperand &Base, int64_t &Offset) { 5052 // Assume it is a primitive operation. 5053 Base = Ptr; Offset = 0; 5054 5055 // If it's an adding a simple constant then integrate the offset. 5056 if (Base.getOpcode() == ISD::ADD) { 5057 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 5058 Base = Base.getOperand(0); 5059 Offset += C->getValue(); 5060 } 5061 } 5062 5063 // If it's any of the following then it can't alias with anything but itself. 5064 return isa<FrameIndexSDNode>(Base) || 5065 isa<ConstantPoolSDNode>(Base) || 5066 isa<GlobalAddressSDNode>(Base); 5067} 5068 5069/// isAlias - Return true if there is any possibility that the two addresses 5070/// overlap. 5071bool DAGCombiner::isAlias(SDOperand Ptr1, int64_t Size1, 5072 const Value *SrcValue1, int SrcValueOffset1, 5073 SDOperand Ptr2, int64_t Size2, 5074 const Value *SrcValue2, int SrcValueOffset2) 5075{ 5076 // If they are the same then they must be aliases. 5077 if (Ptr1 == Ptr2) return true; 5078 5079 // Gather base node and offset information. 5080 SDOperand Base1, Base2; 5081 int64_t Offset1, Offset2; 5082 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1); 5083 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2); 5084 5085 // If they have a same base address then... 5086 if (Base1 == Base2) { 5087 // Check to see if the addresses overlap. 5088 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 5089 } 5090 5091 // If we know both bases then they can't alias. 5092 if (KnownBase1 && KnownBase2) return false; 5093 5094 if (CombinerGlobalAA) { 5095 // Use alias analysis information. 5096 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 5097 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 5098 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 5099 AliasAnalysis::AliasResult AAResult = 5100 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2); 5101 if (AAResult == AliasAnalysis::NoAlias) 5102 return false; 5103 } 5104 5105 // Otherwise we have to assume they alias. 5106 return true; 5107} 5108 5109/// FindAliasInfo - Extracts the relevant alias information from the memory 5110/// node. Returns true if the operand was a load. 5111bool DAGCombiner::FindAliasInfo(SDNode *N, 5112 SDOperand &Ptr, int64_t &Size, 5113 const Value *&SrcValue, int &SrcValueOffset) { 5114 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 5115 Ptr = LD->getBasePtr(); 5116 Size = MVT::getSizeInBits(LD->getLoadedVT()) >> 3; 5117 SrcValue = LD->getSrcValue(); 5118 SrcValueOffset = LD->getSrcValueOffset(); 5119 return true; 5120 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 5121 Ptr = ST->getBasePtr(); 5122 Size = MVT::getSizeInBits(ST->getStoredVT()) >> 3; 5123 SrcValue = ST->getSrcValue(); 5124 SrcValueOffset = ST->getSrcValueOffset(); 5125 } else { 5126 assert(0 && "FindAliasInfo expected a memory operand"); 5127 } 5128 5129 return false; 5130} 5131 5132/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 5133/// looking for aliasing nodes and adding them to the Aliases vector. 5134void DAGCombiner::GatherAllAliases(SDNode *N, SDOperand OriginalChain, 5135 SmallVector<SDOperand, 8> &Aliases) { 5136 SmallVector<SDOperand, 8> Chains; // List of chains to visit. 5137 std::set<SDNode *> Visited; // Visited node set. 5138 5139 // Get alias information for node. 5140 SDOperand Ptr; 5141 int64_t Size; 5142 const Value *SrcValue; 5143 int SrcValueOffset; 5144 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset); 5145 5146 // Starting off. 5147 Chains.push_back(OriginalChain); 5148 5149 // Look at each chain and determine if it is an alias. If so, add it to the 5150 // aliases list. If not, then continue up the chain looking for the next 5151 // candidate. 5152 while (!Chains.empty()) { 5153 SDOperand Chain = Chains.back(); 5154 Chains.pop_back(); 5155 5156 // Don't bother if we've been before. 5157 if (Visited.find(Chain.Val) != Visited.end()) continue; 5158 Visited.insert(Chain.Val); 5159 5160 switch (Chain.getOpcode()) { 5161 case ISD::EntryToken: 5162 // Entry token is ideal chain operand, but handled in FindBetterChain. 5163 break; 5164 5165 case ISD::LOAD: 5166 case ISD::STORE: { 5167 // Get alias information for Chain. 5168 SDOperand OpPtr; 5169 int64_t OpSize; 5170 const Value *OpSrcValue; 5171 int OpSrcValueOffset; 5172 bool IsOpLoad = FindAliasInfo(Chain.Val, OpPtr, OpSize, 5173 OpSrcValue, OpSrcValueOffset); 5174 5175 // If chain is alias then stop here. 5176 if (!(IsLoad && IsOpLoad) && 5177 isAlias(Ptr, Size, SrcValue, SrcValueOffset, 5178 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) { 5179 Aliases.push_back(Chain); 5180 } else { 5181 // Look further up the chain. 5182 Chains.push_back(Chain.getOperand(0)); 5183 // Clean up old chain. 5184 AddToWorkList(Chain.Val); 5185 } 5186 break; 5187 } 5188 5189 case ISD::TokenFactor: 5190 // We have to check each of the operands of the token factor, so we queue 5191 // then up. Adding the operands to the queue (stack) in reverse order 5192 // maintains the original order and increases the likelihood that getNode 5193 // will find a matching token factor (CSE.) 5194 for (unsigned n = Chain.getNumOperands(); n;) 5195 Chains.push_back(Chain.getOperand(--n)); 5196 // Eliminate the token factor if we can. 5197 AddToWorkList(Chain.Val); 5198 break; 5199 5200 default: 5201 // For all other instructions we will just have to take what we can get. 5202 Aliases.push_back(Chain); 5203 break; 5204 } 5205 } 5206} 5207 5208/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 5209/// for a better chain (aliasing node.) 5210SDOperand DAGCombiner::FindBetterChain(SDNode *N, SDOperand OldChain) { 5211 SmallVector<SDOperand, 8> Aliases; // Ops for replacing token factor. 5212 5213 // Accumulate all the aliases to this node. 5214 GatherAllAliases(N, OldChain, Aliases); 5215 5216 if (Aliases.size() == 0) { 5217 // If no operands then chain to entry token. 5218 return DAG.getEntryNode(); 5219 } else if (Aliases.size() == 1) { 5220 // If a single operand then chain to it. We don't need to revisit it. 5221 return Aliases[0]; 5222 } 5223 5224 // Construct a custom tailored token factor. 5225 SDOperand NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 5226 &Aliases[0], Aliases.size()); 5227 5228 // Make sure the old chain gets cleaned up. 5229 if (NewChain != OldChain) AddToWorkList(OldChain.Val); 5230 5231 return NewChain; 5232} 5233 5234// SelectionDAG::Combine - This is the entry point for the file. 5235// 5236void SelectionDAG::Combine(bool RunningAfterLegalize, AliasAnalysis &AA) { 5237 if (!RunningAfterLegalize && ViewDAGCombine1) 5238 viewGraph(); 5239 if (RunningAfterLegalize && ViewDAGCombine2) 5240 viewGraph(); 5241 /// run - This is the main entry point to this class. 5242 /// 5243 DAGCombiner(*this, AA).Run(RunningAfterLegalize); 5244} 5245