DAGCombiner.cpp revision ec142ee0b2a63ede390353860e0f22201b850d8b
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "dagcombine" 16#include "llvm/CodeGen/SelectionDAG.h" 17#include "llvm/CodeGen/MachineFunction.h" 18#include "llvm/CodeGen/MachineFrameInfo.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Target/TargetData.h" 21#include "llvm/Target/TargetFrameInfo.h" 22#include "llvm/Target/TargetLowering.h" 23#include "llvm/Target/TargetMachine.h" 24#include "llvm/Target/TargetOptions.h" 25#include "llvm/ADT/SmallPtrSet.h" 26#include "llvm/ADT/Statistic.h" 27#include "llvm/Support/Compiler.h" 28#include "llvm/Support/CommandLine.h" 29#include "llvm/Support/Debug.h" 30#include "llvm/Support/MathExtras.h" 31#include <algorithm> 32#include <set> 33using namespace llvm; 34 35STATISTIC(NodesCombined , "Number of dag nodes combined"); 36STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 37STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 38 39namespace { 40#ifndef NDEBUG 41 static cl::opt<bool> 42 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 43 cl::desc("Pop up a window to show dags before the first " 44 "dag combine pass")); 45 static cl::opt<bool> 46 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 47 cl::desc("Pop up a window to show dags before the second " 48 "dag combine pass")); 49#else 50 static const bool ViewDAGCombine1 = false; 51 static const bool ViewDAGCombine2 = false; 52#endif 53 54 static cl::opt<bool> 55 CombinerAA("combiner-alias-analysis", cl::Hidden, 56 cl::desc("Turn on alias analysis during testing")); 57 58 static cl::opt<bool> 59 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 60 cl::desc("Include global information in alias analysis")); 61 62//------------------------------ DAGCombiner ---------------------------------// 63 64 class VISIBILITY_HIDDEN DAGCombiner { 65 SelectionDAG &DAG; 66 TargetLowering &TLI; 67 bool AfterLegalize; 68 69 // Worklist of all of the nodes that need to be simplified. 70 std::vector<SDNode*> WorkList; 71 72 // AA - Used for DAG load/store alias analysis. 73 AliasAnalysis &AA; 74 75 /// AddUsersToWorkList - When an instruction is simplified, add all users of 76 /// the instruction to the work lists because they might get more simplified 77 /// now. 78 /// 79 void AddUsersToWorkList(SDNode *N) { 80 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 81 UI != UE; ++UI) 82 AddToWorkList(UI->getUser()); 83 } 84 85 /// visit - call the node-specific routine that knows how to fold each 86 /// particular type of node. 87 SDOperand visit(SDNode *N); 88 89 public: 90 /// AddToWorkList - Add to the work list making sure it's instance is at the 91 /// the back (next to be processed.) 92 void AddToWorkList(SDNode *N) { 93 removeFromWorkList(N); 94 WorkList.push_back(N); 95 } 96 97 /// removeFromWorkList - remove all instances of N from the worklist. 98 /// 99 void removeFromWorkList(SDNode *N) { 100 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 101 WorkList.end()); 102 } 103 104 SDOperand CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo, 105 bool AddTo = true); 106 107 SDOperand CombineTo(SDNode *N, SDOperand Res, bool AddTo = true) { 108 return CombineTo(N, &Res, 1, AddTo); 109 } 110 111 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1, 112 bool AddTo = true) { 113 SDOperand To[] = { Res0, Res1 }; 114 return CombineTo(N, To, 2, AddTo); 115 } 116 117 private: 118 119 /// SimplifyDemandedBits - Check the specified integer node value to see if 120 /// it can be simplified or if things it uses can be simplified by bit 121 /// propagation. If so, return true. 122 bool SimplifyDemandedBits(SDOperand Op) { 123 APInt Demanded = APInt::getAllOnesValue(Op.getValueSizeInBits()); 124 return SimplifyDemandedBits(Op, Demanded); 125 } 126 127 bool SimplifyDemandedBits(SDOperand Op, const APInt &Demanded); 128 129 bool CombineToPreIndexedLoadStore(SDNode *N); 130 bool CombineToPostIndexedLoadStore(SDNode *N); 131 132 133 /// combine - call the node-specific routine that knows how to fold each 134 /// particular type of node. If that doesn't do anything, try the 135 /// target-specific DAG combines. 136 SDOperand combine(SDNode *N); 137 138 // Visitation implementation - Implement dag node combining for different 139 // node types. The semantics are as follows: 140 // Return Value: 141 // SDOperand.Val == 0 - No change was made 142 // SDOperand.Val == N - N was replaced, is dead, and is already handled. 143 // otherwise - N should be replaced by the returned Operand. 144 // 145 SDOperand visitTokenFactor(SDNode *N); 146 SDOperand visitMERGE_VALUES(SDNode *N); 147 SDOperand visitADD(SDNode *N); 148 SDOperand visitSUB(SDNode *N); 149 SDOperand visitADDC(SDNode *N); 150 SDOperand visitADDE(SDNode *N); 151 SDOperand visitMUL(SDNode *N); 152 SDOperand visitSDIV(SDNode *N); 153 SDOperand visitUDIV(SDNode *N); 154 SDOperand visitSREM(SDNode *N); 155 SDOperand visitUREM(SDNode *N); 156 SDOperand visitMULHU(SDNode *N); 157 SDOperand visitMULHS(SDNode *N); 158 SDOperand visitSMUL_LOHI(SDNode *N); 159 SDOperand visitUMUL_LOHI(SDNode *N); 160 SDOperand visitSDIVREM(SDNode *N); 161 SDOperand visitUDIVREM(SDNode *N); 162 SDOperand visitAND(SDNode *N); 163 SDOperand visitOR(SDNode *N); 164 SDOperand visitXOR(SDNode *N); 165 SDOperand SimplifyVBinOp(SDNode *N); 166 SDOperand visitSHL(SDNode *N); 167 SDOperand visitSRA(SDNode *N); 168 SDOperand visitSRL(SDNode *N); 169 SDOperand visitCTLZ(SDNode *N); 170 SDOperand visitCTTZ(SDNode *N); 171 SDOperand visitCTPOP(SDNode *N); 172 SDOperand visitSELECT(SDNode *N); 173 SDOperand visitSELECT_CC(SDNode *N); 174 SDOperand visitSETCC(SDNode *N); 175 SDOperand visitSIGN_EXTEND(SDNode *N); 176 SDOperand visitZERO_EXTEND(SDNode *N); 177 SDOperand visitANY_EXTEND(SDNode *N); 178 SDOperand visitSIGN_EXTEND_INREG(SDNode *N); 179 SDOperand visitTRUNCATE(SDNode *N); 180 SDOperand visitBIT_CONVERT(SDNode *N); 181 SDOperand visitBUILD_PAIR(SDNode *N); 182 SDOperand visitFADD(SDNode *N); 183 SDOperand visitFSUB(SDNode *N); 184 SDOperand visitFMUL(SDNode *N); 185 SDOperand visitFDIV(SDNode *N); 186 SDOperand visitFREM(SDNode *N); 187 SDOperand visitFCOPYSIGN(SDNode *N); 188 SDOperand visitSINT_TO_FP(SDNode *N); 189 SDOperand visitUINT_TO_FP(SDNode *N); 190 SDOperand visitFP_TO_SINT(SDNode *N); 191 SDOperand visitFP_TO_UINT(SDNode *N); 192 SDOperand visitFP_ROUND(SDNode *N); 193 SDOperand visitFP_ROUND_INREG(SDNode *N); 194 SDOperand visitFP_EXTEND(SDNode *N); 195 SDOperand visitFNEG(SDNode *N); 196 SDOperand visitFABS(SDNode *N); 197 SDOperand visitBRCOND(SDNode *N); 198 SDOperand visitBR_CC(SDNode *N); 199 SDOperand visitLOAD(SDNode *N); 200 SDOperand visitSTORE(SDNode *N); 201 SDOperand visitINSERT_VECTOR_ELT(SDNode *N); 202 SDOperand visitEXTRACT_VECTOR_ELT(SDNode *N); 203 SDOperand visitBUILD_VECTOR(SDNode *N); 204 SDOperand visitCONCAT_VECTORS(SDNode *N); 205 SDOperand visitVECTOR_SHUFFLE(SDNode *N); 206 207 SDOperand XformToShuffleWithZero(SDNode *N); 208 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS); 209 210 SDOperand visitShiftByConstant(SDNode *N, unsigned Amt); 211 212 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS); 213 SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N); 214 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2); 215 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2, 216 SDOperand N3, ISD::CondCode CC, 217 bool NotExtCompare = false); 218 SDOperand SimplifySetCC(MVT VT, SDOperand N0, SDOperand N1, 219 ISD::CondCode Cond, bool foldBooleans = true); 220 SDOperand SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 221 unsigned HiOp); 222 SDOperand CombineConsecutiveLoads(SDNode *N, MVT VT); 223 SDOperand ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT); 224 SDOperand BuildSDIV(SDNode *N); 225 SDOperand BuildUDIV(SDNode *N); 226 SDNode *MatchRotate(SDOperand LHS, SDOperand RHS); 227 SDOperand ReduceLoadWidth(SDNode *N); 228 229 SDOperand GetDemandedBits(SDOperand V, const APInt &Mask); 230 231 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 232 /// looking for aliasing nodes and adding them to the Aliases vector. 233 void GatherAllAliases(SDNode *N, SDOperand OriginalChain, 234 SmallVector<SDOperand, 8> &Aliases); 235 236 /// isAlias - Return true if there is any possibility that the two addresses 237 /// overlap. 238 bool isAlias(SDOperand Ptr1, int64_t Size1, 239 const Value *SrcValue1, int SrcValueOffset1, 240 SDOperand Ptr2, int64_t Size2, 241 const Value *SrcValue2, int SrcValueOffset2); 242 243 /// FindAliasInfo - Extracts the relevant alias information from the memory 244 /// node. Returns true if the operand was a load. 245 bool FindAliasInfo(SDNode *N, 246 SDOperand &Ptr, int64_t &Size, 247 const Value *&SrcValue, int &SrcValueOffset); 248 249 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 250 /// looking for a better chain (aliasing node.) 251 SDOperand FindBetterChain(SDNode *N, SDOperand Chain); 252 253public: 254 DAGCombiner(SelectionDAG &D, AliasAnalysis &A) 255 : DAG(D), 256 TLI(D.getTargetLoweringInfo()), 257 AfterLegalize(false), 258 AA(A) {} 259 260 /// Run - runs the dag combiner on all nodes in the work list 261 void Run(bool RunningAfterLegalize); 262 }; 263} 264 265 266namespace { 267/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 268/// nodes from the worklist. 269class VISIBILITY_HIDDEN WorkListRemover : 270 public SelectionDAG::DAGUpdateListener { 271 DAGCombiner &DC; 272public: 273 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {} 274 275 virtual void NodeDeleted(SDNode *N) { 276 DC.removeFromWorkList(N); 277 } 278 279 virtual void NodeUpdated(SDNode *N) { 280 // Ignore updates. 281 } 282}; 283} 284 285//===----------------------------------------------------------------------===// 286// TargetLowering::DAGCombinerInfo implementation 287//===----------------------------------------------------------------------===// 288 289void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 290 ((DAGCombiner*)DC)->AddToWorkList(N); 291} 292 293SDOperand TargetLowering::DAGCombinerInfo:: 294CombineTo(SDNode *N, const std::vector<SDOperand> &To) { 295 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size()); 296} 297 298SDOperand TargetLowering::DAGCombinerInfo:: 299CombineTo(SDNode *N, SDOperand Res) { 300 return ((DAGCombiner*)DC)->CombineTo(N, Res); 301} 302 303 304SDOperand TargetLowering::DAGCombinerInfo:: 305CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) { 306 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1); 307} 308 309 310//===----------------------------------------------------------------------===// 311// Helper Functions 312//===----------------------------------------------------------------------===// 313 314/// isNegatibleForFree - Return 1 if we can compute the negated form of the 315/// specified expression for the same cost as the expression itself, or 2 if we 316/// can compute the negated form more cheaply than the expression itself. 317static char isNegatibleForFree(SDOperand Op, bool AfterLegalize, 318 unsigned Depth = 0) { 319 // No compile time optimizations on this type. 320 if (Op.getValueType() == MVT::ppcf128) 321 return 0; 322 323 // fneg is removable even if it has multiple uses. 324 if (Op.getOpcode() == ISD::FNEG) return 2; 325 326 // Don't allow anything with multiple uses. 327 if (!Op.hasOneUse()) return 0; 328 329 // Don't recurse exponentially. 330 if (Depth > 6) return 0; 331 332 switch (Op.getOpcode()) { 333 default: return false; 334 case ISD::ConstantFP: 335 // Don't invert constant FP values after legalize. The negated constant 336 // isn't necessarily legal. 337 return AfterLegalize ? 0 : 1; 338 case ISD::FADD: 339 // FIXME: determine better conditions for this xform. 340 if (!UnsafeFPMath) return 0; 341 342 // -(A+B) -> -A - B 343 if (char V = isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1)) 344 return V; 345 // -(A+B) -> -B - A 346 return isNegatibleForFree(Op.getOperand(1), AfterLegalize, Depth+1); 347 case ISD::FSUB: 348 // We can't turn -(A-B) into B-A when we honor signed zeros. 349 if (!UnsafeFPMath) return 0; 350 351 // -(A-B) -> B-A 352 return 1; 353 354 case ISD::FMUL: 355 case ISD::FDIV: 356 if (HonorSignDependentRoundingFPMath()) return 0; 357 358 // -(X*Y) -> (-X * Y) or (X*-Y) 359 if (char V = isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1)) 360 return V; 361 362 return isNegatibleForFree(Op.getOperand(1), AfterLegalize, Depth+1); 363 364 case ISD::FP_EXTEND: 365 case ISD::FP_ROUND: 366 case ISD::FSIN: 367 return isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1); 368 } 369} 370 371/// GetNegatedExpression - If isNegatibleForFree returns true, this function 372/// returns the newly negated expression. 373static SDOperand GetNegatedExpression(SDOperand Op, SelectionDAG &DAG, 374 bool AfterLegalize, unsigned Depth = 0) { 375 // fneg is removable even if it has multiple uses. 376 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 377 378 // Don't allow anything with multiple uses. 379 assert(Op.hasOneUse() && "Unknown reuse!"); 380 381 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 382 switch (Op.getOpcode()) { 383 default: assert(0 && "Unknown code"); 384 case ISD::ConstantFP: { 385 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 386 V.changeSign(); 387 return DAG.getConstantFP(V, Op.getValueType()); 388 } 389 case ISD::FADD: 390 // FIXME: determine better conditions for this xform. 391 assert(UnsafeFPMath); 392 393 // -(A+B) -> -A - B 394 if (isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1)) 395 return DAG.getNode(ISD::FSUB, Op.getValueType(), 396 GetNegatedExpression(Op.getOperand(0), DAG, 397 AfterLegalize, Depth+1), 398 Op.getOperand(1)); 399 // -(A+B) -> -B - A 400 return DAG.getNode(ISD::FSUB, Op.getValueType(), 401 GetNegatedExpression(Op.getOperand(1), DAG, 402 AfterLegalize, Depth+1), 403 Op.getOperand(0)); 404 case ISD::FSUB: 405 // We can't turn -(A-B) into B-A when we honor signed zeros. 406 assert(UnsafeFPMath); 407 408 // -(0-B) -> B 409 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 410 if (N0CFP->getValueAPF().isZero()) 411 return Op.getOperand(1); 412 413 // -(A-B) -> B-A 414 return DAG.getNode(ISD::FSUB, Op.getValueType(), Op.getOperand(1), 415 Op.getOperand(0)); 416 417 case ISD::FMUL: 418 case ISD::FDIV: 419 assert(!HonorSignDependentRoundingFPMath()); 420 421 // -(X*Y) -> -X * Y 422 if (isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1)) 423 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 424 GetNegatedExpression(Op.getOperand(0), DAG, 425 AfterLegalize, Depth+1), 426 Op.getOperand(1)); 427 428 // -(X*Y) -> X * -Y 429 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 430 Op.getOperand(0), 431 GetNegatedExpression(Op.getOperand(1), DAG, 432 AfterLegalize, Depth+1)); 433 434 case ISD::FP_EXTEND: 435 case ISD::FSIN: 436 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 437 GetNegatedExpression(Op.getOperand(0), DAG, 438 AfterLegalize, Depth+1)); 439 case ISD::FP_ROUND: 440 return DAG.getNode(ISD::FP_ROUND, Op.getValueType(), 441 GetNegatedExpression(Op.getOperand(0), DAG, 442 AfterLegalize, Depth+1), 443 Op.getOperand(1)); 444 } 445} 446 447 448// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 449// that selects between the values 1 and 0, making it equivalent to a setcc. 450// Also, set the incoming LHS, RHS, and CC references to the appropriate 451// nodes based on the type of node we are checking. This simplifies life a 452// bit for the callers. 453static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS, 454 SDOperand &CC) { 455 if (N.getOpcode() == ISD::SETCC) { 456 LHS = N.getOperand(0); 457 RHS = N.getOperand(1); 458 CC = N.getOperand(2); 459 return true; 460 } 461 if (N.getOpcode() == ISD::SELECT_CC && 462 N.getOperand(2).getOpcode() == ISD::Constant && 463 N.getOperand(3).getOpcode() == ISD::Constant && 464 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 465 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 466 LHS = N.getOperand(0); 467 RHS = N.getOperand(1); 468 CC = N.getOperand(4); 469 return true; 470 } 471 return false; 472} 473 474// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 475// one use. If this is true, it allows the users to invert the operation for 476// free when it is profitable to do so. 477static bool isOneUseSetCC(SDOperand N) { 478 SDOperand N0, N1, N2; 479 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse()) 480 return true; 481 return false; 482} 483 484SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){ 485 MVT VT = N0.getValueType(); 486 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 487 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 488 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 489 if (isa<ConstantSDNode>(N1)) { 490 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1); 491 AddToWorkList(OpNode.Val); 492 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0)); 493 } else if (N0.hasOneUse()) { 494 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1); 495 AddToWorkList(OpNode.Val); 496 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1)); 497 } 498 } 499 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 500 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 501 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 502 if (isa<ConstantSDNode>(N0)) { 503 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0); 504 AddToWorkList(OpNode.Val); 505 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0)); 506 } else if (N1.hasOneUse()) { 507 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0); 508 AddToWorkList(OpNode.Val); 509 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1)); 510 } 511 } 512 return SDOperand(); 513} 514 515SDOperand DAGCombiner::CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo, 516 bool AddTo) { 517 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 518 ++NodesCombined; 519 DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG)); 520 DOUT << "\nWith: "; DEBUG(To[0].Val->dump(&DAG)); 521 DOUT << " and " << NumTo-1 << " other values\n"; 522 WorkListRemover DeadNodes(*this); 523 DAG.ReplaceAllUsesWith(N, To, &DeadNodes); 524 525 if (AddTo) { 526 // Push the new nodes and any users onto the worklist 527 for (unsigned i = 0, e = NumTo; i != e; ++i) { 528 AddToWorkList(To[i].Val); 529 AddUsersToWorkList(To[i].Val); 530 } 531 } 532 533 // Nodes can be reintroduced into the worklist. Make sure we do not 534 // process a node that has been replaced. 535 removeFromWorkList(N); 536 537 // Finally, since the node is now dead, remove it from the graph. 538 DAG.DeleteNode(N); 539 return SDOperand(N, 0); 540} 541 542/// SimplifyDemandedBits - Check the specified integer node value to see if 543/// it can be simplified or if things it uses can be simplified by bit 544/// propagation. If so, return true. 545bool DAGCombiner::SimplifyDemandedBits(SDOperand Op, const APInt &Demanded) { 546 TargetLowering::TargetLoweringOpt TLO(DAG, AfterLegalize); 547 APInt KnownZero, KnownOne; 548 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 549 return false; 550 551 // Revisit the node. 552 AddToWorkList(Op.Val); 553 554 // Replace the old value with the new one. 555 ++NodesCombined; 556 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.Val->dump(&DAG)); 557 DOUT << "\nWith: "; DEBUG(TLO.New.Val->dump(&DAG)); 558 DOUT << '\n'; 559 560 // Replace all uses. If any nodes become isomorphic to other nodes and 561 // are deleted, make sure to remove them from our worklist. 562 WorkListRemover DeadNodes(*this); 563 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 564 565 // Push the new node and any (possibly new) users onto the worklist. 566 AddToWorkList(TLO.New.Val); 567 AddUsersToWorkList(TLO.New.Val); 568 569 // Finally, if the node is now dead, remove it from the graph. The node 570 // may not be dead if the replacement process recursively simplified to 571 // something else needing this node. 572 if (TLO.Old.Val->use_empty()) { 573 removeFromWorkList(TLO.Old.Val); 574 575 // If the operands of this node are only used by the node, they will now 576 // be dead. Make sure to visit them first to delete dead nodes early. 577 for (unsigned i = 0, e = TLO.Old.Val->getNumOperands(); i != e; ++i) 578 if (TLO.Old.Val->getOperand(i).Val->hasOneUse()) 579 AddToWorkList(TLO.Old.Val->getOperand(i).Val); 580 581 DAG.DeleteNode(TLO.Old.Val); 582 } 583 return true; 584} 585 586//===----------------------------------------------------------------------===// 587// Main DAG Combiner implementation 588//===----------------------------------------------------------------------===// 589 590void DAGCombiner::Run(bool RunningAfterLegalize) { 591 // set the instance variable, so that the various visit routines may use it. 592 AfterLegalize = RunningAfterLegalize; 593 594 // Add all the dag nodes to the worklist. 595 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 596 E = DAG.allnodes_end(); I != E; ++I) 597 WorkList.push_back(I); 598 599 // Create a dummy node (which is not added to allnodes), that adds a reference 600 // to the root node, preventing it from being deleted, and tracking any 601 // changes of the root. 602 HandleSDNode Dummy(DAG.getRoot()); 603 604 // The root of the dag may dangle to deleted nodes until the dag combiner is 605 // done. Set it to null to avoid confusion. 606 DAG.setRoot(SDOperand()); 607 608 // while the worklist isn't empty, inspect the node on the end of it and 609 // try and combine it. 610 while (!WorkList.empty()) { 611 SDNode *N = WorkList.back(); 612 WorkList.pop_back(); 613 614 // If N has no uses, it is dead. Make sure to revisit all N's operands once 615 // N is deleted from the DAG, since they too may now be dead or may have a 616 // reduced number of uses, allowing other xforms. 617 if (N->use_empty() && N != &Dummy) { 618 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 619 AddToWorkList(N->getOperand(i).Val); 620 621 DAG.DeleteNode(N); 622 continue; 623 } 624 625 SDOperand RV = combine(N); 626 627 if (RV.Val == 0) 628 continue; 629 630 ++NodesCombined; 631 632 // If we get back the same node we passed in, rather than a new node or 633 // zero, we know that the node must have defined multiple values and 634 // CombineTo was used. Since CombineTo takes care of the worklist 635 // mechanics for us, we have no work to do in this case. 636 if (RV.Val == N) 637 continue; 638 639 assert(N->getOpcode() != ISD::DELETED_NODE && 640 RV.Val->getOpcode() != ISD::DELETED_NODE && 641 "Node was deleted but visit returned new node!"); 642 643 DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG)); 644 DOUT << "\nWith: "; DEBUG(RV.Val->dump(&DAG)); 645 DOUT << '\n'; 646 WorkListRemover DeadNodes(*this); 647 if (N->getNumValues() == RV.Val->getNumValues()) 648 DAG.ReplaceAllUsesWith(N, RV.Val, &DeadNodes); 649 else { 650 assert(N->getValueType(0) == RV.getValueType() && 651 N->getNumValues() == 1 && "Type mismatch"); 652 SDOperand OpV = RV; 653 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes); 654 } 655 656 // Push the new node and any users onto the worklist 657 AddToWorkList(RV.Val); 658 AddUsersToWorkList(RV.Val); 659 660 // Add any uses of the old node to the worklist in case this node is the 661 // last one that uses them. They may become dead after this node is 662 // deleted. 663 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 664 AddToWorkList(N->getOperand(i).Val); 665 666 // Nodes can be reintroduced into the worklist. Make sure we do not 667 // process a node that has been replaced. 668 removeFromWorkList(N); 669 670 // Finally, since the node is now dead, remove it from the graph. 671 DAG.DeleteNode(N); 672 } 673 674 // If the root changed (e.g. it was a dead load, update the root). 675 DAG.setRoot(Dummy.getValue()); 676} 677 678SDOperand DAGCombiner::visit(SDNode *N) { 679 switch(N->getOpcode()) { 680 default: break; 681 case ISD::TokenFactor: return visitTokenFactor(N); 682 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 683 case ISD::ADD: return visitADD(N); 684 case ISD::SUB: return visitSUB(N); 685 case ISD::ADDC: return visitADDC(N); 686 case ISD::ADDE: return visitADDE(N); 687 case ISD::MUL: return visitMUL(N); 688 case ISD::SDIV: return visitSDIV(N); 689 case ISD::UDIV: return visitUDIV(N); 690 case ISD::SREM: return visitSREM(N); 691 case ISD::UREM: return visitUREM(N); 692 case ISD::MULHU: return visitMULHU(N); 693 case ISD::MULHS: return visitMULHS(N); 694 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 695 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 696 case ISD::SDIVREM: return visitSDIVREM(N); 697 case ISD::UDIVREM: return visitUDIVREM(N); 698 case ISD::AND: return visitAND(N); 699 case ISD::OR: return visitOR(N); 700 case ISD::XOR: return visitXOR(N); 701 case ISD::SHL: return visitSHL(N); 702 case ISD::SRA: return visitSRA(N); 703 case ISD::SRL: return visitSRL(N); 704 case ISD::CTLZ: return visitCTLZ(N); 705 case ISD::CTTZ: return visitCTTZ(N); 706 case ISD::CTPOP: return visitCTPOP(N); 707 case ISD::SELECT: return visitSELECT(N); 708 case ISD::SELECT_CC: return visitSELECT_CC(N); 709 case ISD::SETCC: return visitSETCC(N); 710 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 711 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 712 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 713 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 714 case ISD::TRUNCATE: return visitTRUNCATE(N); 715 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 716 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 717 case ISD::FADD: return visitFADD(N); 718 case ISD::FSUB: return visitFSUB(N); 719 case ISD::FMUL: return visitFMUL(N); 720 case ISD::FDIV: return visitFDIV(N); 721 case ISD::FREM: return visitFREM(N); 722 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 723 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 724 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 725 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 726 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 727 case ISD::FP_ROUND: return visitFP_ROUND(N); 728 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 729 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 730 case ISD::FNEG: return visitFNEG(N); 731 case ISD::FABS: return visitFABS(N); 732 case ISD::BRCOND: return visitBRCOND(N); 733 case ISD::BR_CC: return visitBR_CC(N); 734 case ISD::LOAD: return visitLOAD(N); 735 case ISD::STORE: return visitSTORE(N); 736 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 737 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 738 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 739 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 740 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 741 } 742 return SDOperand(); 743} 744 745SDOperand DAGCombiner::combine(SDNode *N) { 746 747 SDOperand RV = visit(N); 748 749 // If nothing happened, try a target-specific DAG combine. 750 if (RV.Val == 0) { 751 assert(N->getOpcode() != ISD::DELETED_NODE && 752 "Node was deleted but visit returned NULL!"); 753 754 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 755 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 756 757 // Expose the DAG combiner to the target combiner impls. 758 TargetLowering::DAGCombinerInfo 759 DagCombineInfo(DAG, !AfterLegalize, false, this); 760 761 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 762 } 763 } 764 765 // If N is a commutative binary node, try commuting it to enable more 766 // sdisel CSE. 767 if (RV.Val == 0 && 768 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 769 N->getNumValues() == 1) { 770 SDOperand N0 = N->getOperand(0); 771 SDOperand N1 = N->getOperand(1); 772 // Constant operands are canonicalized to RHS. 773 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 774 SDOperand Ops[] = { N1, N0 }; 775 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 776 Ops, 2); 777 if (CSENode) 778 return SDOperand(CSENode, 0); 779 } 780 } 781 782 return RV; 783} 784 785/// getInputChainForNode - Given a node, return its input chain if it has one, 786/// otherwise return a null sd operand. 787static SDOperand getInputChainForNode(SDNode *N) { 788 if (unsigned NumOps = N->getNumOperands()) { 789 if (N->getOperand(0).getValueType() == MVT::Other) 790 return N->getOperand(0); 791 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 792 return N->getOperand(NumOps-1); 793 for (unsigned i = 1; i < NumOps-1; ++i) 794 if (N->getOperand(i).getValueType() == MVT::Other) 795 return N->getOperand(i); 796 } 797 return SDOperand(0, 0); 798} 799 800SDOperand DAGCombiner::visitTokenFactor(SDNode *N) { 801 // If N has two operands, where one has an input chain equal to the other, 802 // the 'other' chain is redundant. 803 if (N->getNumOperands() == 2) { 804 if (getInputChainForNode(N->getOperand(0).Val) == N->getOperand(1)) 805 return N->getOperand(0); 806 if (getInputChainForNode(N->getOperand(1).Val) == N->getOperand(0)) 807 return N->getOperand(1); 808 } 809 810 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 811 SmallVector<SDOperand, 8> Ops; // Ops for replacing token factor. 812 SmallPtrSet<SDNode*, 16> SeenOps; 813 bool Changed = false; // If we should replace this token factor. 814 815 // Start out with this token factor. 816 TFs.push_back(N); 817 818 // Iterate through token factors. The TFs grows when new token factors are 819 // encountered. 820 for (unsigned i = 0; i < TFs.size(); ++i) { 821 SDNode *TF = TFs[i]; 822 823 // Check each of the operands. 824 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 825 SDOperand Op = TF->getOperand(i); 826 827 switch (Op.getOpcode()) { 828 case ISD::EntryToken: 829 // Entry tokens don't need to be added to the list. They are 830 // rededundant. 831 Changed = true; 832 break; 833 834 case ISD::TokenFactor: 835 if ((CombinerAA || Op.hasOneUse()) && 836 std::find(TFs.begin(), TFs.end(), Op.Val) == TFs.end()) { 837 // Queue up for processing. 838 TFs.push_back(Op.Val); 839 // Clean up in case the token factor is removed. 840 AddToWorkList(Op.Val); 841 Changed = true; 842 break; 843 } 844 // Fall thru 845 846 default: 847 // Only add if it isn't already in the list. 848 if (SeenOps.insert(Op.Val)) 849 Ops.push_back(Op); 850 else 851 Changed = true; 852 break; 853 } 854 } 855 } 856 857 SDOperand Result; 858 859 // If we've change things around then replace token factor. 860 if (Changed) { 861 if (Ops.empty()) { 862 // The entry token is the only possible outcome. 863 Result = DAG.getEntryNode(); 864 } else { 865 // New and improved token factor. 866 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size()); 867 } 868 869 // Don't add users to work list. 870 return CombineTo(N, Result, false); 871 } 872 873 return Result; 874} 875 876/// MERGE_VALUES can always be eliminated. 877SDOperand DAGCombiner::visitMERGE_VALUES(SDNode *N) { 878 WorkListRemover DeadNodes(*this); 879 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 880 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, i), N->getOperand(i), 881 &DeadNodes); 882 removeFromWorkList(N); 883 DAG.DeleteNode(N); 884 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 885} 886 887 888static 889SDOperand combineShlAddConstant(SDOperand N0, SDOperand N1, SelectionDAG &DAG) { 890 MVT VT = N0.getValueType(); 891 SDOperand N00 = N0.getOperand(0); 892 SDOperand N01 = N0.getOperand(1); 893 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 894 if (N01C && N00.getOpcode() == ISD::ADD && N00.Val->hasOneUse() && 895 isa<ConstantSDNode>(N00.getOperand(1))) { 896 N0 = DAG.getNode(ISD::ADD, VT, 897 DAG.getNode(ISD::SHL, VT, N00.getOperand(0), N01), 898 DAG.getNode(ISD::SHL, VT, N00.getOperand(1), N01)); 899 return DAG.getNode(ISD::ADD, VT, N0, N1); 900 } 901 return SDOperand(); 902} 903 904static 905SDOperand combineSelectAndUse(SDNode *N, SDOperand Slct, SDOperand OtherOp, 906 SelectionDAG &DAG) { 907 MVT VT = N->getValueType(0); 908 unsigned Opc = N->getOpcode(); 909 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC; 910 SDOperand LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1); 911 SDOperand RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2); 912 ISD::CondCode CC = ISD::SETCC_INVALID; 913 if (isSlctCC) 914 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get(); 915 else { 916 SDOperand CCOp = Slct.getOperand(0); 917 if (CCOp.getOpcode() == ISD::SETCC) 918 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get(); 919 } 920 921 bool DoXform = false; 922 bool InvCC = false; 923 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) && 924 "Bad input!"); 925 if (LHS.getOpcode() == ISD::Constant && 926 cast<ConstantSDNode>(LHS)->isNullValue()) 927 DoXform = true; 928 else if (CC != ISD::SETCC_INVALID && 929 RHS.getOpcode() == ISD::Constant && 930 cast<ConstantSDNode>(RHS)->isNullValue()) { 931 std::swap(LHS, RHS); 932 SDOperand Op0 = Slct.getOperand(0); 933 bool isInt = (isSlctCC ? Op0.getValueType() : 934 Op0.getOperand(0).getValueType()).isInteger(); 935 CC = ISD::getSetCCInverse(CC, isInt); 936 DoXform = true; 937 InvCC = true; 938 } 939 940 if (DoXform) { 941 SDOperand Result = DAG.getNode(Opc, VT, OtherOp, RHS); 942 if (isSlctCC) 943 return DAG.getSelectCC(OtherOp, Result, 944 Slct.getOperand(0), Slct.getOperand(1), CC); 945 SDOperand CCOp = Slct.getOperand(0); 946 if (InvCC) 947 CCOp = DAG.getSetCC(CCOp.getValueType(), CCOp.getOperand(0), 948 CCOp.getOperand(1), CC); 949 return DAG.getNode(ISD::SELECT, VT, CCOp, OtherOp, Result); 950 } 951 return SDOperand(); 952} 953 954SDOperand DAGCombiner::visitADD(SDNode *N) { 955 SDOperand N0 = N->getOperand(0); 956 SDOperand N1 = N->getOperand(1); 957 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 958 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 959 MVT VT = N0.getValueType(); 960 961 // fold vector ops 962 if (VT.isVector()) { 963 SDOperand FoldedVOp = SimplifyVBinOp(N); 964 if (FoldedVOp.Val) return FoldedVOp; 965 } 966 967 // fold (add x, undef) -> undef 968 if (N0.getOpcode() == ISD::UNDEF) 969 return N0; 970 if (N1.getOpcode() == ISD::UNDEF) 971 return N1; 972 // fold (add c1, c2) -> c1+c2 973 if (N0C && N1C) 974 return DAG.getConstant(N0C->getAPIntValue() + N1C->getAPIntValue(), VT); 975 // canonicalize constant to RHS 976 if (N0C && !N1C) 977 return DAG.getNode(ISD::ADD, VT, N1, N0); 978 // fold (add x, 0) -> x 979 if (N1C && N1C->isNullValue()) 980 return N0; 981 // fold ((c1-A)+c2) -> (c1+c2)-A 982 if (N1C && N0.getOpcode() == ISD::SUB) 983 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 984 return DAG.getNode(ISD::SUB, VT, 985 DAG.getConstant(N1C->getAPIntValue()+ 986 N0C->getAPIntValue(), VT), 987 N0.getOperand(1)); 988 // reassociate add 989 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1); 990 if (RADD.Val != 0) 991 return RADD; 992 // fold ((0-A) + B) -> B-A 993 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 994 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 995 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1)); 996 // fold (A + (0-B)) -> A-B 997 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 998 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 999 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1)); 1000 // fold (A+(B-A)) -> B 1001 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 1002 return N1.getOperand(0); 1003 1004 if (!VT.isVector() && SimplifyDemandedBits(SDOperand(N, 0))) 1005 return SDOperand(N, 0); 1006 1007 // fold (a+b) -> (a|b) iff a and b share no bits. 1008 if (VT.isInteger() && !VT.isVector()) { 1009 APInt LHSZero, LHSOne; 1010 APInt RHSZero, RHSOne; 1011 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 1012 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1013 if (LHSZero.getBoolValue()) { 1014 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1015 1016 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1017 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1018 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1019 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1020 return DAG.getNode(ISD::OR, VT, N0, N1); 1021 } 1022 } 1023 1024 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1025 if (N0.getOpcode() == ISD::SHL && N0.Val->hasOneUse()) { 1026 SDOperand Result = combineShlAddConstant(N0, N1, DAG); 1027 if (Result.Val) return Result; 1028 } 1029 if (N1.getOpcode() == ISD::SHL && N1.Val->hasOneUse()) { 1030 SDOperand Result = combineShlAddConstant(N1, N0, DAG); 1031 if (Result.Val) return Result; 1032 } 1033 1034 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c)) 1035 if (N0.getOpcode() == ISD::SELECT && N0.Val->hasOneUse()) { 1036 SDOperand Result = combineSelectAndUse(N, N0, N1, DAG); 1037 if (Result.Val) return Result; 1038 } 1039 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) { 1040 SDOperand Result = combineSelectAndUse(N, N1, N0, DAG); 1041 if (Result.Val) return Result; 1042 } 1043 1044 return SDOperand(); 1045} 1046 1047SDOperand DAGCombiner::visitADDC(SDNode *N) { 1048 SDOperand N0 = N->getOperand(0); 1049 SDOperand N1 = N->getOperand(1); 1050 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1051 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1052 MVT VT = N0.getValueType(); 1053 1054 // If the flag result is dead, turn this into an ADD. 1055 if (N->hasNUsesOfValue(0, 1)) 1056 return CombineTo(N, DAG.getNode(ISD::ADD, VT, N1, N0), 1057 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 1058 1059 // canonicalize constant to RHS. 1060 if (N0C && !N1C) { 1061 SDOperand Ops[] = { N1, N0 }; 1062 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2); 1063 } 1064 1065 // fold (addc x, 0) -> x + no carry out 1066 if (N1C && N1C->isNullValue()) 1067 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 1068 1069 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1070 APInt LHSZero, LHSOne; 1071 APInt RHSZero, RHSOne; 1072 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 1073 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1074 if (LHSZero.getBoolValue()) { 1075 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1076 1077 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1078 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1079 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1080 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1081 return CombineTo(N, DAG.getNode(ISD::OR, VT, N0, N1), 1082 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 1083 } 1084 1085 return SDOperand(); 1086} 1087 1088SDOperand DAGCombiner::visitADDE(SDNode *N) { 1089 SDOperand N0 = N->getOperand(0); 1090 SDOperand N1 = N->getOperand(1); 1091 SDOperand CarryIn = N->getOperand(2); 1092 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1093 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1094 //MVT VT = N0.getValueType(); 1095 1096 // canonicalize constant to RHS 1097 if (N0C && !N1C) { 1098 SDOperand Ops[] = { N1, N0, CarryIn }; 1099 return DAG.getNode(ISD::ADDE, N->getVTList(), Ops, 3); 1100 } 1101 1102 // fold (adde x, y, false) -> (addc x, y) 1103 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) { 1104 SDOperand Ops[] = { N1, N0 }; 1105 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2); 1106 } 1107 1108 return SDOperand(); 1109} 1110 1111 1112 1113SDOperand DAGCombiner::visitSUB(SDNode *N) { 1114 SDOperand N0 = N->getOperand(0); 1115 SDOperand N1 = N->getOperand(1); 1116 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1117 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1118 MVT VT = N0.getValueType(); 1119 1120 // fold vector ops 1121 if (VT.isVector()) { 1122 SDOperand FoldedVOp = SimplifyVBinOp(N); 1123 if (FoldedVOp.Val) return FoldedVOp; 1124 } 1125 1126 // fold (sub x, x) -> 0 1127 if (N0 == N1) 1128 return DAG.getConstant(0, N->getValueType(0)); 1129 // fold (sub c1, c2) -> c1-c2 1130 if (N0C && N1C) 1131 return DAG.getNode(ISD::SUB, VT, N0, N1); 1132 // fold (sub x, c) -> (add x, -c) 1133 if (N1C) 1134 return DAG.getNode(ISD::ADD, VT, N0, 1135 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1136 // fold (A+B)-A -> B 1137 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1138 return N0.getOperand(1); 1139 // fold (A+B)-B -> A 1140 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1141 return N0.getOperand(0); 1142 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c)) 1143 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) { 1144 SDOperand Result = combineSelectAndUse(N, N1, N0, DAG); 1145 if (Result.Val) return Result; 1146 } 1147 // If either operand of a sub is undef, the result is undef 1148 if (N0.getOpcode() == ISD::UNDEF) 1149 return N0; 1150 if (N1.getOpcode() == ISD::UNDEF) 1151 return N1; 1152 1153 return SDOperand(); 1154} 1155 1156SDOperand DAGCombiner::visitMUL(SDNode *N) { 1157 SDOperand N0 = N->getOperand(0); 1158 SDOperand N1 = N->getOperand(1); 1159 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1160 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1161 MVT VT = N0.getValueType(); 1162 1163 // fold vector ops 1164 if (VT.isVector()) { 1165 SDOperand FoldedVOp = SimplifyVBinOp(N); 1166 if (FoldedVOp.Val) return FoldedVOp; 1167 } 1168 1169 // fold (mul x, undef) -> 0 1170 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1171 return DAG.getConstant(0, VT); 1172 // fold (mul c1, c2) -> c1*c2 1173 if (N0C && N1C) 1174 return DAG.getNode(ISD::MUL, VT, N0, N1); 1175 // canonicalize constant to RHS 1176 if (N0C && !N1C) 1177 return DAG.getNode(ISD::MUL, VT, N1, N0); 1178 // fold (mul x, 0) -> 0 1179 if (N1C && N1C->isNullValue()) 1180 return N1; 1181 // fold (mul x, -1) -> 0-x 1182 if (N1C && N1C->isAllOnesValue()) 1183 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 1184 // fold (mul x, (1 << c)) -> x << c 1185 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1186 return DAG.getNode(ISD::SHL, VT, N0, 1187 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1188 TLI.getShiftAmountTy())); 1189 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1190 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) { 1191 // FIXME: If the input is something that is easily negated (e.g. a 1192 // single-use add), we should put the negate there. 1193 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), 1194 DAG.getNode(ISD::SHL, VT, N0, 1195 DAG.getConstant(Log2_64(-N1C->getSignExtended()), 1196 TLI.getShiftAmountTy()))); 1197 } 1198 1199 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1200 if (N1C && N0.getOpcode() == ISD::SHL && 1201 isa<ConstantSDNode>(N0.getOperand(1))) { 1202 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1)); 1203 AddToWorkList(C3.Val); 1204 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3); 1205 } 1206 1207 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1208 // use. 1209 { 1210 SDOperand Sh(0,0), Y(0,0); 1211 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1212 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1213 N0.Val->hasOneUse()) { 1214 Sh = N0; Y = N1; 1215 } else if (N1.getOpcode() == ISD::SHL && 1216 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) { 1217 Sh = N1; Y = N0; 1218 } 1219 if (Sh.Val) { 1220 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y); 1221 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1)); 1222 } 1223 } 1224 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1225 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() && 1226 isa<ConstantSDNode>(N0.getOperand(1))) { 1227 return DAG.getNode(ISD::ADD, VT, 1228 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1), 1229 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1)); 1230 } 1231 1232 // reassociate mul 1233 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1); 1234 if (RMUL.Val != 0) 1235 return RMUL; 1236 1237 return SDOperand(); 1238} 1239 1240SDOperand DAGCombiner::visitSDIV(SDNode *N) { 1241 SDOperand N0 = N->getOperand(0); 1242 SDOperand N1 = N->getOperand(1); 1243 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1244 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1245 MVT VT = N->getValueType(0); 1246 1247 // fold vector ops 1248 if (VT.isVector()) { 1249 SDOperand FoldedVOp = SimplifyVBinOp(N); 1250 if (FoldedVOp.Val) return FoldedVOp; 1251 } 1252 1253 // fold (sdiv c1, c2) -> c1/c2 1254 if (N0C && N1C && !N1C->isNullValue()) 1255 return DAG.getNode(ISD::SDIV, VT, N0, N1); 1256 // fold (sdiv X, 1) -> X 1257 if (N1C && N1C->getSignExtended() == 1LL) 1258 return N0; 1259 // fold (sdiv X, -1) -> 0-X 1260 if (N1C && N1C->isAllOnesValue()) 1261 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 1262 // If we know the sign bits of both operands are zero, strength reduce to a 1263 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1264 if (!VT.isVector()) { 1265 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1266 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1); 1267 } 1268 // fold (sdiv X, pow2) -> simple ops after legalize 1269 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() && 1270 (isPowerOf2_64(N1C->getSignExtended()) || 1271 isPowerOf2_64(-N1C->getSignExtended()))) { 1272 // If dividing by powers of two is cheap, then don't perform the following 1273 // fold. 1274 if (TLI.isPow2DivCheap()) 1275 return SDOperand(); 1276 int64_t pow2 = N1C->getSignExtended(); 1277 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1278 unsigned lg2 = Log2_64(abs2); 1279 // Splat the sign bit into the register 1280 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0, 1281 DAG.getConstant(VT.getSizeInBits()-1, 1282 TLI.getShiftAmountTy())); 1283 AddToWorkList(SGN.Val); 1284 // Add (N0 < 0) ? abs2 - 1 : 0; 1285 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN, 1286 DAG.getConstant(VT.getSizeInBits()-lg2, 1287 TLI.getShiftAmountTy())); 1288 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL); 1289 AddToWorkList(SRL.Val); 1290 AddToWorkList(ADD.Val); // Divide by pow2 1291 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD, 1292 DAG.getConstant(lg2, TLI.getShiftAmountTy())); 1293 // If we're dividing by a positive value, we're done. Otherwise, we must 1294 // negate the result. 1295 if (pow2 > 0) 1296 return SRA; 1297 AddToWorkList(SRA.Val); 1298 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA); 1299 } 1300 // if integer divide is expensive and we satisfy the requirements, emit an 1301 // alternate sequence. 1302 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) && 1303 !TLI.isIntDivCheap()) { 1304 SDOperand Op = BuildSDIV(N); 1305 if (Op.Val) return Op; 1306 } 1307 1308 // undef / X -> 0 1309 if (N0.getOpcode() == ISD::UNDEF) 1310 return DAG.getConstant(0, VT); 1311 // X / undef -> undef 1312 if (N1.getOpcode() == ISD::UNDEF) 1313 return N1; 1314 1315 return SDOperand(); 1316} 1317 1318SDOperand DAGCombiner::visitUDIV(SDNode *N) { 1319 SDOperand N0 = N->getOperand(0); 1320 SDOperand N1 = N->getOperand(1); 1321 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1322 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1323 MVT VT = N->getValueType(0); 1324 1325 // fold vector ops 1326 if (VT.isVector()) { 1327 SDOperand FoldedVOp = SimplifyVBinOp(N); 1328 if (FoldedVOp.Val) return FoldedVOp; 1329 } 1330 1331 // fold (udiv c1, c2) -> c1/c2 1332 if (N0C && N1C && !N1C->isNullValue()) 1333 return DAG.getNode(ISD::UDIV, VT, N0, N1); 1334 // fold (udiv x, (1 << c)) -> x >>u c 1335 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1336 return DAG.getNode(ISD::SRL, VT, N0, 1337 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1338 TLI.getShiftAmountTy())); 1339 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1340 if (N1.getOpcode() == ISD::SHL) { 1341 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1342 if (SHC->getAPIntValue().isPowerOf2()) { 1343 MVT ADDVT = N1.getOperand(1).getValueType(); 1344 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1), 1345 DAG.getConstant(SHC->getAPIntValue() 1346 .logBase2(), 1347 ADDVT)); 1348 AddToWorkList(Add.Val); 1349 return DAG.getNode(ISD::SRL, VT, N0, Add); 1350 } 1351 } 1352 } 1353 // fold (udiv x, c) -> alternate 1354 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1355 SDOperand Op = BuildUDIV(N); 1356 if (Op.Val) return Op; 1357 } 1358 1359 // undef / X -> 0 1360 if (N0.getOpcode() == ISD::UNDEF) 1361 return DAG.getConstant(0, VT); 1362 // X / undef -> undef 1363 if (N1.getOpcode() == ISD::UNDEF) 1364 return N1; 1365 1366 return SDOperand(); 1367} 1368 1369SDOperand DAGCombiner::visitSREM(SDNode *N) { 1370 SDOperand N0 = N->getOperand(0); 1371 SDOperand N1 = N->getOperand(1); 1372 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1373 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1374 MVT VT = N->getValueType(0); 1375 1376 // fold (srem c1, c2) -> c1%c2 1377 if (N0C && N1C && !N1C->isNullValue()) 1378 return DAG.getNode(ISD::SREM, VT, N0, N1); 1379 // If we know the sign bits of both operands are zero, strength reduce to a 1380 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1381 if (!VT.isVector()) { 1382 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1383 return DAG.getNode(ISD::UREM, VT, N0, N1); 1384 } 1385 1386 // If X/C can be simplified by the division-by-constant logic, lower 1387 // X%C to the equivalent of X-X/C*C. 1388 if (N1C && !N1C->isNullValue()) { 1389 SDOperand Div = DAG.getNode(ISD::SDIV, VT, N0, N1); 1390 AddToWorkList(Div.Val); 1391 SDOperand OptimizedDiv = combine(Div.Val); 1392 if (OptimizedDiv.Val && OptimizedDiv.Val != Div.Val) { 1393 SDOperand Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1); 1394 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1395 AddToWorkList(Mul.Val); 1396 return Sub; 1397 } 1398 } 1399 1400 // undef % X -> 0 1401 if (N0.getOpcode() == ISD::UNDEF) 1402 return DAG.getConstant(0, VT); 1403 // X % undef -> undef 1404 if (N1.getOpcode() == ISD::UNDEF) 1405 return N1; 1406 1407 return SDOperand(); 1408} 1409 1410SDOperand DAGCombiner::visitUREM(SDNode *N) { 1411 SDOperand N0 = N->getOperand(0); 1412 SDOperand N1 = N->getOperand(1); 1413 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1414 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1415 MVT VT = N->getValueType(0); 1416 1417 // fold (urem c1, c2) -> c1%c2 1418 if (N0C && N1C && !N1C->isNullValue()) 1419 return DAG.getNode(ISD::UREM, VT, N0, N1); 1420 // fold (urem x, pow2) -> (and x, pow2-1) 1421 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 1422 return DAG.getNode(ISD::AND, VT, N0, 1423 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 1424 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1425 if (N1.getOpcode() == ISD::SHL) { 1426 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1427 if (SHC->getAPIntValue().isPowerOf2()) { 1428 SDOperand Add = 1429 DAG.getNode(ISD::ADD, VT, N1, 1430 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 1431 VT)); 1432 AddToWorkList(Add.Val); 1433 return DAG.getNode(ISD::AND, VT, N0, Add); 1434 } 1435 } 1436 } 1437 1438 // If X/C can be simplified by the division-by-constant logic, lower 1439 // X%C to the equivalent of X-X/C*C. 1440 if (N1C && !N1C->isNullValue()) { 1441 SDOperand Div = DAG.getNode(ISD::UDIV, VT, N0, N1); 1442 SDOperand OptimizedDiv = combine(Div.Val); 1443 if (OptimizedDiv.Val && OptimizedDiv.Val != Div.Val) { 1444 SDOperand Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1); 1445 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1446 AddToWorkList(Mul.Val); 1447 return Sub; 1448 } 1449 } 1450 1451 // undef % X -> 0 1452 if (N0.getOpcode() == ISD::UNDEF) 1453 return DAG.getConstant(0, VT); 1454 // X % undef -> undef 1455 if (N1.getOpcode() == ISD::UNDEF) 1456 return N1; 1457 1458 return SDOperand(); 1459} 1460 1461SDOperand DAGCombiner::visitMULHS(SDNode *N) { 1462 SDOperand N0 = N->getOperand(0); 1463 SDOperand N1 = N->getOperand(1); 1464 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1465 MVT VT = N->getValueType(0); 1466 1467 // fold (mulhs x, 0) -> 0 1468 if (N1C && N1C->isNullValue()) 1469 return N1; 1470 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1471 if (N1C && N1C->getAPIntValue() == 1) 1472 return DAG.getNode(ISD::SRA, N0.getValueType(), N0, 1473 DAG.getConstant(N0.getValueType().getSizeInBits()-1, 1474 TLI.getShiftAmountTy())); 1475 // fold (mulhs x, undef) -> 0 1476 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1477 return DAG.getConstant(0, VT); 1478 1479 return SDOperand(); 1480} 1481 1482SDOperand DAGCombiner::visitMULHU(SDNode *N) { 1483 SDOperand N0 = N->getOperand(0); 1484 SDOperand N1 = N->getOperand(1); 1485 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1486 MVT VT = N->getValueType(0); 1487 1488 // fold (mulhu x, 0) -> 0 1489 if (N1C && N1C->isNullValue()) 1490 return N1; 1491 // fold (mulhu x, 1) -> 0 1492 if (N1C && N1C->getAPIntValue() == 1) 1493 return DAG.getConstant(0, N0.getValueType()); 1494 // fold (mulhu x, undef) -> 0 1495 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1496 return DAG.getConstant(0, VT); 1497 1498 return SDOperand(); 1499} 1500 1501/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 1502/// compute two values. LoOp and HiOp give the opcodes for the two computations 1503/// that are being performed. Return true if a simplification was made. 1504/// 1505SDOperand DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 1506 unsigned HiOp) { 1507 // If the high half is not needed, just compute the low half. 1508 bool HiExists = N->hasAnyUseOfValue(1); 1509 if (!HiExists && 1510 (!AfterLegalize || 1511 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 1512 SDOperand Res = DAG.getNode(LoOp, N->getValueType(0), N->op_begin(), 1513 N->getNumOperands()); 1514 return CombineTo(N, Res, Res); 1515 } 1516 1517 // If the low half is not needed, just compute the high half. 1518 bool LoExists = N->hasAnyUseOfValue(0); 1519 if (!LoExists && 1520 (!AfterLegalize || 1521 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 1522 SDOperand Res = DAG.getNode(HiOp, N->getValueType(1), N->op_begin(), 1523 N->getNumOperands()); 1524 return CombineTo(N, Res, Res); 1525 } 1526 1527 // If both halves are used, return as it is. 1528 if (LoExists && HiExists) 1529 return SDOperand(); 1530 1531 // If the two computed results can be simplified separately, separate them. 1532 if (LoExists) { 1533 SDOperand Lo = DAG.getNode(LoOp, N->getValueType(0), 1534 N->op_begin(), N->getNumOperands()); 1535 AddToWorkList(Lo.Val); 1536 SDOperand LoOpt = combine(Lo.Val); 1537 if (LoOpt.Val && LoOpt.Val != Lo.Val && 1538 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())) 1539 return CombineTo(N, LoOpt, LoOpt); 1540 } 1541 1542 if (HiExists) { 1543 SDOperand Hi = DAG.getNode(HiOp, N->getValueType(1), 1544 N->op_begin(), N->getNumOperands()); 1545 AddToWorkList(Hi.Val); 1546 SDOperand HiOpt = combine(Hi.Val); 1547 if (HiOpt.Val && HiOpt != Hi && 1548 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())) 1549 return CombineTo(N, HiOpt, HiOpt); 1550 } 1551 return SDOperand(); 1552} 1553 1554SDOperand DAGCombiner::visitSMUL_LOHI(SDNode *N) { 1555 SDOperand Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 1556 if (Res.Val) return Res; 1557 1558 return SDOperand(); 1559} 1560 1561SDOperand DAGCombiner::visitUMUL_LOHI(SDNode *N) { 1562 SDOperand Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 1563 if (Res.Val) return Res; 1564 1565 return SDOperand(); 1566} 1567 1568SDOperand DAGCombiner::visitSDIVREM(SDNode *N) { 1569 SDOperand Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 1570 if (Res.Val) return Res; 1571 1572 return SDOperand(); 1573} 1574 1575SDOperand DAGCombiner::visitUDIVREM(SDNode *N) { 1576 SDOperand Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 1577 if (Res.Val) return Res; 1578 1579 return SDOperand(); 1580} 1581 1582/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 1583/// two operands of the same opcode, try to simplify it. 1584SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 1585 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1); 1586 MVT VT = N0.getValueType(); 1587 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 1588 1589 // For each of OP in AND/OR/XOR: 1590 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 1591 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 1592 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 1593 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) 1594 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND|| 1595 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) && 1596 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1597 SDOperand ORNode = DAG.getNode(N->getOpcode(), 1598 N0.getOperand(0).getValueType(), 1599 N0.getOperand(0), N1.getOperand(0)); 1600 AddToWorkList(ORNode.Val); 1601 return DAG.getNode(N0.getOpcode(), VT, ORNode); 1602 } 1603 1604 // For each of OP in SHL/SRL/SRA/AND... 1605 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 1606 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 1607 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 1608 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 1609 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 1610 N0.getOperand(1) == N1.getOperand(1)) { 1611 SDOperand ORNode = DAG.getNode(N->getOpcode(), 1612 N0.getOperand(0).getValueType(), 1613 N0.getOperand(0), N1.getOperand(0)); 1614 AddToWorkList(ORNode.Val); 1615 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1)); 1616 } 1617 1618 return SDOperand(); 1619} 1620 1621SDOperand DAGCombiner::visitAND(SDNode *N) { 1622 SDOperand N0 = N->getOperand(0); 1623 SDOperand N1 = N->getOperand(1); 1624 SDOperand LL, LR, RL, RR, CC0, CC1; 1625 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1626 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1627 MVT VT = N1.getValueType(); 1628 unsigned BitWidth = VT.getSizeInBits(); 1629 1630 // fold vector ops 1631 if (VT.isVector()) { 1632 SDOperand FoldedVOp = SimplifyVBinOp(N); 1633 if (FoldedVOp.Val) return FoldedVOp; 1634 } 1635 1636 // fold (and x, undef) -> 0 1637 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1638 return DAG.getConstant(0, VT); 1639 // fold (and c1, c2) -> c1&c2 1640 if (N0C && N1C) 1641 return DAG.getNode(ISD::AND, VT, N0, N1); 1642 // canonicalize constant to RHS 1643 if (N0C && !N1C) 1644 return DAG.getNode(ISD::AND, VT, N1, N0); 1645 // fold (and x, -1) -> x 1646 if (N1C && N1C->isAllOnesValue()) 1647 return N0; 1648 // if (and x, c) is known to be zero, return 0 1649 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), 1650 APInt::getAllOnesValue(BitWidth))) 1651 return DAG.getConstant(0, VT); 1652 // reassociate and 1653 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1); 1654 if (RAND.Val != 0) 1655 return RAND; 1656 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 1657 if (N1C && N0.getOpcode() == ISD::OR) 1658 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1659 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 1660 return N1; 1661 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 1662 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1663 SDOperand N0Op0 = N0.getOperand(0); 1664 APInt Mask = ~N1C->getAPIntValue(); 1665 Mask.trunc(N0Op0.getValueSizeInBits()); 1666 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 1667 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(), 1668 N0Op0); 1669 1670 // Replace uses of the AND with uses of the Zero extend node. 1671 CombineTo(N, Zext); 1672 1673 // We actually want to replace all uses of the any_extend with the 1674 // zero_extend, to avoid duplicating things. This will later cause this 1675 // AND to be folded. 1676 CombineTo(N0.Val, Zext); 1677 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1678 } 1679 } 1680 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 1681 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1682 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1683 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1684 1685 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1686 LL.getValueType().isInteger()) { 1687 // fold (X == 0) & (Y == 0) -> (X|Y == 0) 1688 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 1689 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1690 AddToWorkList(ORNode.Val); 1691 return DAG.getSetCC(VT, ORNode, LR, Op1); 1692 } 1693 // fold (X == -1) & (Y == -1) -> (X&Y == -1) 1694 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 1695 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1696 AddToWorkList(ANDNode.Val); 1697 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1698 } 1699 // fold (X > -1) & (Y > -1) -> (X|Y > -1) 1700 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1701 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1702 AddToWorkList(ORNode.Val); 1703 return DAG.getSetCC(VT, ORNode, LR, Op1); 1704 } 1705 } 1706 // canonicalize equivalent to ll == rl 1707 if (LL == RR && LR == RL) { 1708 Op1 = ISD::getSetCCSwappedOperands(Op1); 1709 std::swap(RL, RR); 1710 } 1711 if (LL == RL && LR == RR) { 1712 bool isInteger = LL.getValueType().isInteger(); 1713 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1714 if (Result != ISD::SETCC_INVALID) 1715 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1716 } 1717 } 1718 1719 // Simplify: and (op x...), (op y...) -> (op (and x, y)) 1720 if (N0.getOpcode() == N1.getOpcode()) { 1721 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1722 if (Tmp.Val) return Tmp; 1723 } 1724 1725 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1726 // fold (and (sra)) -> (and (srl)) when possible. 1727 if (!VT.isVector() && 1728 SimplifyDemandedBits(SDOperand(N, 0))) 1729 return SDOperand(N, 0); 1730 // fold (zext_inreg (extload x)) -> (zextload x) 1731 if (ISD::isEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val)) { 1732 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1733 MVT EVT = LN0->getMemoryVT(); 1734 // If we zero all the possible extended bits, then we can turn this into 1735 // a zextload if we are running before legalize or the operation is legal. 1736 unsigned BitWidth = N1.getValueSizeInBits(); 1737 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1738 BitWidth - EVT.getSizeInBits())) && 1739 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1740 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1741 LN0->getBasePtr(), LN0->getSrcValue(), 1742 LN0->getSrcValueOffset(), EVT, 1743 LN0->isVolatile(), 1744 LN0->getAlignment()); 1745 AddToWorkList(N); 1746 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1747 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1748 } 1749 } 1750 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1751 if (ISD::isSEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 1752 N0.hasOneUse()) { 1753 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1754 MVT EVT = LN0->getMemoryVT(); 1755 // If we zero all the possible extended bits, then we can turn this into 1756 // a zextload if we are running before legalize or the operation is legal. 1757 unsigned BitWidth = N1.getValueSizeInBits(); 1758 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1759 BitWidth - EVT.getSizeInBits())) && 1760 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1761 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1762 LN0->getBasePtr(), LN0->getSrcValue(), 1763 LN0->getSrcValueOffset(), EVT, 1764 LN0->isVolatile(), 1765 LN0->getAlignment()); 1766 AddToWorkList(N); 1767 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1768 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1769 } 1770 } 1771 1772 // fold (and (load x), 255) -> (zextload x, i8) 1773 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1774 if (N1C && N0.getOpcode() == ISD::LOAD) { 1775 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1776 if (LN0->getExtensionType() != ISD::SEXTLOAD && 1777 LN0->isUnindexed() && N0.hasOneUse()) { 1778 MVT EVT, LoadedVT; 1779 if (N1C->getAPIntValue() == 255) 1780 EVT = MVT::i8; 1781 else if (N1C->getAPIntValue() == 65535) 1782 EVT = MVT::i16; 1783 else if (N1C->getAPIntValue() == ~0U) 1784 EVT = MVT::i32; 1785 else 1786 EVT = MVT::Other; 1787 1788 LoadedVT = LN0->getMemoryVT(); 1789 if (EVT != MVT::Other && LoadedVT.bitsGT(EVT) && 1790 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1791 MVT PtrType = N0.getOperand(1).getValueType(); 1792 // For big endian targets, we need to add an offset to the pointer to 1793 // load the correct bytes. For little endian systems, we merely need to 1794 // read fewer bytes from the same pointer. 1795 unsigned LVTStoreBytes = LoadedVT.getStoreSizeInBits()/8; 1796 unsigned EVTStoreBytes = EVT.getStoreSizeInBits()/8; 1797 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 1798 unsigned Alignment = LN0->getAlignment(); 1799 SDOperand NewPtr = LN0->getBasePtr(); 1800 if (TLI.isBigEndian()) { 1801 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, 1802 DAG.getConstant(PtrOff, PtrType)); 1803 Alignment = MinAlign(Alignment, PtrOff); 1804 } 1805 AddToWorkList(NewPtr.Val); 1806 SDOperand Load = 1807 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr, 1808 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT, 1809 LN0->isVolatile(), Alignment); 1810 AddToWorkList(N); 1811 CombineTo(N0.Val, Load, Load.getValue(1)); 1812 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1813 } 1814 } 1815 } 1816 1817 return SDOperand(); 1818} 1819 1820SDOperand DAGCombiner::visitOR(SDNode *N) { 1821 SDOperand N0 = N->getOperand(0); 1822 SDOperand N1 = N->getOperand(1); 1823 SDOperand LL, LR, RL, RR, CC0, CC1; 1824 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1825 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1826 MVT VT = N1.getValueType(); 1827 1828 // fold vector ops 1829 if (VT.isVector()) { 1830 SDOperand FoldedVOp = SimplifyVBinOp(N); 1831 if (FoldedVOp.Val) return FoldedVOp; 1832 } 1833 1834 // fold (or x, undef) -> -1 1835 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1836 return DAG.getConstant(~0ULL, VT); 1837 // fold (or c1, c2) -> c1|c2 1838 if (N0C && N1C) 1839 return DAG.getNode(ISD::OR, VT, N0, N1); 1840 // canonicalize constant to RHS 1841 if (N0C && !N1C) 1842 return DAG.getNode(ISD::OR, VT, N1, N0); 1843 // fold (or x, 0) -> x 1844 if (N1C && N1C->isNullValue()) 1845 return N0; 1846 // fold (or x, -1) -> -1 1847 if (N1C && N1C->isAllOnesValue()) 1848 return N1; 1849 // fold (or x, c) -> c iff (x & ~c) == 0 1850 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 1851 return N1; 1852 // reassociate or 1853 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1); 1854 if (ROR.Val != 0) 1855 return ROR; 1856 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 1857 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() && 1858 isa<ConstantSDNode>(N0.getOperand(1))) { 1859 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 1860 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0), 1861 N1), 1862 DAG.getConstant(N1C->getAPIntValue() | 1863 C1->getAPIntValue(), VT)); 1864 } 1865 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 1866 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1867 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1868 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1869 1870 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1871 LL.getValueType().isInteger()) { 1872 // fold (X != 0) | (Y != 0) -> (X|Y != 0) 1873 // fold (X < 0) | (Y < 0) -> (X|Y < 0) 1874 if (cast<ConstantSDNode>(LR)->isNullValue() && 1875 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 1876 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1877 AddToWorkList(ORNode.Val); 1878 return DAG.getSetCC(VT, ORNode, LR, Op1); 1879 } 1880 // fold (X != -1) | (Y != -1) -> (X&Y != -1) 1881 // fold (X > -1) | (Y > -1) -> (X&Y > -1) 1882 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 1883 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 1884 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1885 AddToWorkList(ANDNode.Val); 1886 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1887 } 1888 } 1889 // canonicalize equivalent to ll == rl 1890 if (LL == RR && LR == RL) { 1891 Op1 = ISD::getSetCCSwappedOperands(Op1); 1892 std::swap(RL, RR); 1893 } 1894 if (LL == RL && LR == RR) { 1895 bool isInteger = LL.getValueType().isInteger(); 1896 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 1897 if (Result != ISD::SETCC_INVALID) 1898 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1899 } 1900 } 1901 1902 // Simplify: or (op x...), (op y...) -> (op (or x, y)) 1903 if (N0.getOpcode() == N1.getOpcode()) { 1904 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1905 if (Tmp.Val) return Tmp; 1906 } 1907 1908 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible. 1909 if (N0.getOpcode() == ISD::AND && 1910 N1.getOpcode() == ISD::AND && 1911 N0.getOperand(1).getOpcode() == ISD::Constant && 1912 N1.getOperand(1).getOpcode() == ISD::Constant && 1913 // Don't increase # computations. 1914 (N0.Val->hasOneUse() || N1.Val->hasOneUse())) { 1915 // We can only do this xform if we know that bits from X that are set in C2 1916 // but not in C1 are already zero. Likewise for Y. 1917 const APInt &LHSMask = 1918 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 1919 const APInt &RHSMask = 1920 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 1921 1922 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 1923 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 1924 SDOperand X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0)); 1925 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT)); 1926 } 1927 } 1928 1929 1930 // See if this is some rotate idiom. 1931 if (SDNode *Rot = MatchRotate(N0, N1)) 1932 return SDOperand(Rot, 0); 1933 1934 return SDOperand(); 1935} 1936 1937 1938/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 1939static bool MatchRotateHalf(SDOperand Op, SDOperand &Shift, SDOperand &Mask) { 1940 if (Op.getOpcode() == ISD::AND) { 1941 if (isa<ConstantSDNode>(Op.getOperand(1))) { 1942 Mask = Op.getOperand(1); 1943 Op = Op.getOperand(0); 1944 } else { 1945 return false; 1946 } 1947 } 1948 1949 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 1950 Shift = Op; 1951 return true; 1952 } 1953 return false; 1954} 1955 1956 1957// MatchRotate - Handle an 'or' of two operands. If this is one of the many 1958// idioms for rotate, and if the target supports rotation instructions, generate 1959// a rot[lr]. 1960SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) { 1961 // Must be a legal type. Expanded an promoted things won't work with rotates. 1962 MVT VT = LHS.getValueType(); 1963 if (!TLI.isTypeLegal(VT)) return 0; 1964 1965 // The target must have at least one rotate flavor. 1966 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT); 1967 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT); 1968 if (!HasROTL && !HasROTR) return 0; 1969 1970 // Match "(X shl/srl V1) & V2" where V2 may not be present. 1971 SDOperand LHSShift; // The shift. 1972 SDOperand LHSMask; // AND value if any. 1973 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 1974 return 0; // Not part of a rotate. 1975 1976 SDOperand RHSShift; // The shift. 1977 SDOperand RHSMask; // AND value if any. 1978 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 1979 return 0; // Not part of a rotate. 1980 1981 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 1982 return 0; // Not shifting the same value. 1983 1984 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 1985 return 0; // Shifts must disagree. 1986 1987 // Canonicalize shl to left side in a shl/srl pair. 1988 if (RHSShift.getOpcode() == ISD::SHL) { 1989 std::swap(LHS, RHS); 1990 std::swap(LHSShift, RHSShift); 1991 std::swap(LHSMask , RHSMask ); 1992 } 1993 1994 unsigned OpSizeInBits = VT.getSizeInBits(); 1995 SDOperand LHSShiftArg = LHSShift.getOperand(0); 1996 SDOperand LHSShiftAmt = LHSShift.getOperand(1); 1997 SDOperand RHSShiftAmt = RHSShift.getOperand(1); 1998 1999 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 2000 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 2001 if (LHSShiftAmt.getOpcode() == ISD::Constant && 2002 RHSShiftAmt.getOpcode() == ISD::Constant) { 2003 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getValue(); 2004 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getValue(); 2005 if ((LShVal + RShVal) != OpSizeInBits) 2006 return 0; 2007 2008 SDOperand Rot; 2009 if (HasROTL) 2010 Rot = DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt); 2011 else 2012 Rot = DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt); 2013 2014 // If there is an AND of either shifted operand, apply it to the result. 2015 if (LHSMask.Val || RHSMask.Val) { 2016 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 2017 2018 if (LHSMask.Val) { 2019 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 2020 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 2021 } 2022 if (RHSMask.Val) { 2023 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 2024 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 2025 } 2026 2027 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT)); 2028 } 2029 2030 return Rot.Val; 2031 } 2032 2033 // If there is a mask here, and we have a variable shift, we can't be sure 2034 // that we're masking out the right stuff. 2035 if (LHSMask.Val || RHSMask.Val) 2036 return 0; 2037 2038 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 2039 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 2040 if (RHSShiftAmt.getOpcode() == ISD::SUB && 2041 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 2042 if (ConstantSDNode *SUBC = 2043 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 2044 if (SUBC->getAPIntValue() == OpSizeInBits) { 2045 if (HasROTL) 2046 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 2047 else 2048 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 2049 } 2050 } 2051 } 2052 2053 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 2054 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 2055 if (LHSShiftAmt.getOpcode() == ISD::SUB && 2056 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 2057 if (ConstantSDNode *SUBC = 2058 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 2059 if (SUBC->getAPIntValue() == OpSizeInBits) { 2060 if (HasROTL) 2061 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 2062 else 2063 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 2064 } 2065 } 2066 } 2067 2068 // Look for sign/zext/any-extended cases: 2069 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2070 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2071 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND) && 2072 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2073 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2074 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND)) { 2075 SDOperand LExtOp0 = LHSShiftAmt.getOperand(0); 2076 SDOperand RExtOp0 = RHSShiftAmt.getOperand(0); 2077 if (RExtOp0.getOpcode() == ISD::SUB && 2078 RExtOp0.getOperand(1) == LExtOp0) { 2079 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2080 // (rotr x, y) 2081 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2082 // (rotl x, (sub 32, y)) 2083 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 2084 if (SUBC->getAPIntValue() == OpSizeInBits) { 2085 if (HasROTL) 2086 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 2087 else 2088 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 2089 } 2090 } 2091 } else if (LExtOp0.getOpcode() == ISD::SUB && 2092 RExtOp0 == LExtOp0.getOperand(1)) { 2093 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -> 2094 // (rotl x, y) 2095 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -> 2096 // (rotr x, (sub 32, y)) 2097 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 2098 if (SUBC->getAPIntValue() == OpSizeInBits) { 2099 if (HasROTL) 2100 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, RHSShiftAmt).Val; 2101 else 2102 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 2103 } 2104 } 2105 } 2106 } 2107 2108 return 0; 2109} 2110 2111 2112SDOperand DAGCombiner::visitXOR(SDNode *N) { 2113 SDOperand N0 = N->getOperand(0); 2114 SDOperand N1 = N->getOperand(1); 2115 SDOperand LHS, RHS, CC; 2116 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2117 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2118 MVT VT = N0.getValueType(); 2119 2120 // fold vector ops 2121 if (VT.isVector()) { 2122 SDOperand FoldedVOp = SimplifyVBinOp(N); 2123 if (FoldedVOp.Val) return FoldedVOp; 2124 } 2125 2126 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 2127 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 2128 return DAG.getConstant(0, VT); 2129 // fold (xor x, undef) -> undef 2130 if (N0.getOpcode() == ISD::UNDEF) 2131 return N0; 2132 if (N1.getOpcode() == ISD::UNDEF) 2133 return N1; 2134 // fold (xor c1, c2) -> c1^c2 2135 if (N0C && N1C) 2136 return DAG.getNode(ISD::XOR, VT, N0, N1); 2137 // canonicalize constant to RHS 2138 if (N0C && !N1C) 2139 return DAG.getNode(ISD::XOR, VT, N1, N0); 2140 // fold (xor x, 0) -> x 2141 if (N1C && N1C->isNullValue()) 2142 return N0; 2143 // reassociate xor 2144 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1); 2145 if (RXOR.Val != 0) 2146 return RXOR; 2147 // fold !(x cc y) -> (x !cc y) 2148 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 2149 bool isInt = LHS.getValueType().isInteger(); 2150 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 2151 isInt); 2152 if (N0.getOpcode() == ISD::SETCC) 2153 return DAG.getSetCC(VT, LHS, RHS, NotCC); 2154 if (N0.getOpcode() == ISD::SELECT_CC) 2155 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC); 2156 assert(0 && "Unhandled SetCC Equivalent!"); 2157 abort(); 2158 } 2159 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 2160 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 2161 N0.Val->hasOneUse() && isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 2162 SDOperand V = N0.getOperand(0); 2163 V = DAG.getNode(ISD::XOR, V.getValueType(), V, 2164 DAG.getConstant(1, V.getValueType())); 2165 AddToWorkList(V.Val); 2166 return DAG.getNode(ISD::ZERO_EXTEND, VT, V); 2167 } 2168 2169 // fold !(x or y) -> (!x and !y) iff x or y are setcc 2170 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 2171 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2172 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2173 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 2174 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2175 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 2176 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 2177 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 2178 return DAG.getNode(NewOpcode, VT, LHS, RHS); 2179 } 2180 } 2181 // fold !(x or y) -> (!x and !y) iff x or y are constants 2182 if (N1C && N1C->isAllOnesValue() && 2183 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2184 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2185 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 2186 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2187 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 2188 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 2189 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 2190 return DAG.getNode(NewOpcode, VT, LHS, RHS); 2191 } 2192 } 2193 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2) 2194 if (N1C && N0.getOpcode() == ISD::XOR) { 2195 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 2196 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2197 if (N00C) 2198 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1), 2199 DAG.getConstant(N1C->getAPIntValue()^ 2200 N00C->getAPIntValue(), VT)); 2201 if (N01C) 2202 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0), 2203 DAG.getConstant(N1C->getAPIntValue()^ 2204 N01C->getAPIntValue(), VT)); 2205 } 2206 // fold (xor x, x) -> 0 2207 if (N0 == N1) { 2208 if (!VT.isVector()) { 2209 return DAG.getConstant(0, VT); 2210 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 2211 // Produce a vector of zeros. 2212 SDOperand El = DAG.getConstant(0, VT.getVectorElementType()); 2213 std::vector<SDOperand> Ops(VT.getVectorNumElements(), El); 2214 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 2215 } 2216 } 2217 2218 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 2219 if (N0.getOpcode() == N1.getOpcode()) { 2220 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2221 if (Tmp.Val) return Tmp; 2222 } 2223 2224 // Simplify the expression using non-local knowledge. 2225 if (!VT.isVector() && 2226 SimplifyDemandedBits(SDOperand(N, 0))) 2227 return SDOperand(N, 0); 2228 2229 return SDOperand(); 2230} 2231 2232/// visitShiftByConstant - Handle transforms common to the three shifts, when 2233/// the shift amount is a constant. 2234SDOperand DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 2235 SDNode *LHS = N->getOperand(0).Val; 2236 if (!LHS->hasOneUse()) return SDOperand(); 2237 2238 // We want to pull some binops through shifts, so that we have (and (shift)) 2239 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 2240 // thing happens with address calculations, so it's important to canonicalize 2241 // it. 2242 bool HighBitSet = false; // Can we transform this if the high bit is set? 2243 2244 switch (LHS->getOpcode()) { 2245 default: return SDOperand(); 2246 case ISD::OR: 2247 case ISD::XOR: 2248 HighBitSet = false; // We can only transform sra if the high bit is clear. 2249 break; 2250 case ISD::AND: 2251 HighBitSet = true; // We can only transform sra if the high bit is set. 2252 break; 2253 case ISD::ADD: 2254 if (N->getOpcode() != ISD::SHL) 2255 return SDOperand(); // only shl(add) not sr[al](add). 2256 HighBitSet = false; // We can only transform sra if the high bit is clear. 2257 break; 2258 } 2259 2260 // We require the RHS of the binop to be a constant as well. 2261 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 2262 if (!BinOpCst) return SDOperand(); 2263 2264 2265 // FIXME: disable this for unless the input to the binop is a shift by a 2266 // constant. If it is not a shift, it pessimizes some common cases like: 2267 // 2268 //void foo(int *X, int i) { X[i & 1235] = 1; } 2269 //int bar(int *X, int i) { return X[i & 255]; } 2270 SDNode *BinOpLHSVal = LHS->getOperand(0).Val; 2271 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 2272 BinOpLHSVal->getOpcode() != ISD::SRA && 2273 BinOpLHSVal->getOpcode() != ISD::SRL) || 2274 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 2275 return SDOperand(); 2276 2277 MVT VT = N->getValueType(0); 2278 2279 // If this is a signed shift right, and the high bit is modified 2280 // by the logical operation, do not perform the transformation. 2281 // The highBitSet boolean indicates the value of the high bit of 2282 // the constant which would cause it to be modified for this 2283 // operation. 2284 if (N->getOpcode() == ISD::SRA) { 2285 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 2286 if (BinOpRHSSignSet != HighBitSet) 2287 return SDOperand(); 2288 } 2289 2290 // Fold the constants, shifting the binop RHS by the shift amount. 2291 SDOperand NewRHS = DAG.getNode(N->getOpcode(), N->getValueType(0), 2292 LHS->getOperand(1), N->getOperand(1)); 2293 2294 // Create the new shift. 2295 SDOperand NewShift = DAG.getNode(N->getOpcode(), VT, LHS->getOperand(0), 2296 N->getOperand(1)); 2297 2298 // Create the new binop. 2299 return DAG.getNode(LHS->getOpcode(), VT, NewShift, NewRHS); 2300} 2301 2302 2303SDOperand DAGCombiner::visitSHL(SDNode *N) { 2304 SDOperand N0 = N->getOperand(0); 2305 SDOperand N1 = N->getOperand(1); 2306 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2307 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2308 MVT VT = N0.getValueType(); 2309 unsigned OpSizeInBits = VT.getSizeInBits(); 2310 2311 // fold (shl c1, c2) -> c1<<c2 2312 if (N0C && N1C) 2313 return DAG.getNode(ISD::SHL, VT, N0, N1); 2314 // fold (shl 0, x) -> 0 2315 if (N0C && N0C->isNullValue()) 2316 return N0; 2317 // fold (shl x, c >= size(x)) -> undef 2318 if (N1C && N1C->getValue() >= OpSizeInBits) 2319 return DAG.getNode(ISD::UNDEF, VT); 2320 // fold (shl x, 0) -> x 2321 if (N1C && N1C->isNullValue()) 2322 return N0; 2323 // if (shl x, c) is known to be zero, return 0 2324 if (DAG.MaskedValueIsZero(SDOperand(N, 0), 2325 APInt::getAllOnesValue(VT.getSizeInBits()))) 2326 return DAG.getConstant(0, VT); 2327 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 2328 return SDOperand(N, 0); 2329 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2) 2330 if (N1C && N0.getOpcode() == ISD::SHL && 2331 N0.getOperand(1).getOpcode() == ISD::Constant) { 2332 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2333 uint64_t c2 = N1C->getValue(); 2334 if (c1 + c2 > OpSizeInBits) 2335 return DAG.getConstant(0, VT); 2336 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0), 2337 DAG.getConstant(c1 + c2, N1.getValueType())); 2338 } 2339 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or 2340 // (srl (and x, -1 << c1), c1-c2) 2341 if (N1C && N0.getOpcode() == ISD::SRL && 2342 N0.getOperand(1).getOpcode() == ISD::Constant) { 2343 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2344 uint64_t c2 = N1C->getValue(); 2345 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0), 2346 DAG.getConstant(~0ULL << c1, VT)); 2347 if (c2 > c1) 2348 return DAG.getNode(ISD::SHL, VT, Mask, 2349 DAG.getConstant(c2-c1, N1.getValueType())); 2350 else 2351 return DAG.getNode(ISD::SRL, VT, Mask, 2352 DAG.getConstant(c1-c2, N1.getValueType())); 2353 } 2354 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1) 2355 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 2356 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 2357 DAG.getConstant(~0ULL << N1C->getValue(), VT)); 2358 2359 return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDOperand(); 2360} 2361 2362SDOperand DAGCombiner::visitSRA(SDNode *N) { 2363 SDOperand N0 = N->getOperand(0); 2364 SDOperand N1 = N->getOperand(1); 2365 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2366 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2367 MVT VT = N0.getValueType(); 2368 2369 // fold (sra c1, c2) -> c1>>c2 2370 if (N0C && N1C) 2371 return DAG.getNode(ISD::SRA, VT, N0, N1); 2372 // fold (sra 0, x) -> 0 2373 if (N0C && N0C->isNullValue()) 2374 return N0; 2375 // fold (sra -1, x) -> -1 2376 if (N0C && N0C->isAllOnesValue()) 2377 return N0; 2378 // fold (sra x, c >= size(x)) -> undef 2379 if (N1C && N1C->getValue() >= VT.getSizeInBits()) 2380 return DAG.getNode(ISD::UNDEF, VT); 2381 // fold (sra x, 0) -> x 2382 if (N1C && N1C->isNullValue()) 2383 return N0; 2384 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 2385 // sext_inreg. 2386 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 2387 unsigned LowBits = VT.getSizeInBits() - (unsigned)N1C->getValue(); 2388 MVT EVT; 2389 switch (LowBits) { 2390 default: EVT = MVT::Other; break; 2391 case 1: EVT = MVT::i1; break; 2392 case 8: EVT = MVT::i8; break; 2393 case 16: EVT = MVT::i16; break; 2394 case 32: EVT = MVT::i32; break; 2395 } 2396 if (EVT != MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT)) 2397 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), 2398 DAG.getValueType(EVT)); 2399 } 2400 2401 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2) 2402 if (N1C && N0.getOpcode() == ISD::SRA) { 2403 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2404 unsigned Sum = N1C->getValue() + C1->getValue(); 2405 if (Sum >= VT.getSizeInBits()) Sum = VT.getSizeInBits()-1; 2406 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), 2407 DAG.getConstant(Sum, N1C->getValueType(0))); 2408 } 2409 } 2410 2411 // fold sra (shl X, m), result_size - n 2412 // -> (sign_extend (trunc (shl X, result_size - n - m))) for 2413 // result_size - n != m. 2414 // If truncate is free for the target sext(shl) is likely to result in better 2415 // code. 2416 if (N0.getOpcode() == ISD::SHL) { 2417 // Get the two constanst of the shifts, CN0 = m, CN = n. 2418 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2419 if (N01C && N1C) { 2420 // Determine what the truncate's result bitsize and type would be. 2421 unsigned VTValSize = VT.getSizeInBits(); 2422 MVT TruncVT = 2423 MVT::getIntegerVT(VTValSize - N1C->getValue()); 2424 // Determine the residual right-shift amount. 2425 unsigned ShiftAmt = N1C->getValue() - N01C->getValue(); 2426 2427 // If the shift is not a no-op (in which case this should be just a sign 2428 // extend already), the truncated to type is legal, sign_extend is legal 2429 // on that type, and the the truncate to that type is both legal and free, 2430 // perform the transform. 2431 if (ShiftAmt && 2432 TLI.isTypeLegal(TruncVT) && 2433 TLI.isOperationLegal(ISD::SIGN_EXTEND, TruncVT) && 2434 TLI.isOperationLegal(ISD::TRUNCATE, VT) && 2435 TLI.isTruncateFree(VT, TruncVT)) { 2436 2437 SDOperand Amt = DAG.getConstant(ShiftAmt, TLI.getShiftAmountTy()); 2438 SDOperand Shift = DAG.getNode(ISD::SRL, VT, N0.getOperand(0), Amt); 2439 SDOperand Trunc = DAG.getNode(ISD::TRUNCATE, TruncVT, Shift); 2440 return DAG.getNode(ISD::SIGN_EXTEND, N->getValueType(0), Trunc); 2441 } 2442 } 2443 } 2444 2445 // Simplify, based on bits shifted out of the LHS. 2446 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 2447 return SDOperand(N, 0); 2448 2449 2450 // If the sign bit is known to be zero, switch this to a SRL. 2451 if (DAG.SignBitIsZero(N0)) 2452 return DAG.getNode(ISD::SRL, VT, N0, N1); 2453 2454 return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDOperand(); 2455} 2456 2457SDOperand DAGCombiner::visitSRL(SDNode *N) { 2458 SDOperand N0 = N->getOperand(0); 2459 SDOperand N1 = N->getOperand(1); 2460 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2461 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2462 MVT VT = N0.getValueType(); 2463 unsigned OpSizeInBits = VT.getSizeInBits(); 2464 2465 // fold (srl c1, c2) -> c1 >>u c2 2466 if (N0C && N1C) 2467 return DAG.getNode(ISD::SRL, VT, N0, N1); 2468 // fold (srl 0, x) -> 0 2469 if (N0C && N0C->isNullValue()) 2470 return N0; 2471 // fold (srl x, c >= size(x)) -> undef 2472 if (N1C && N1C->getValue() >= OpSizeInBits) 2473 return DAG.getNode(ISD::UNDEF, VT); 2474 // fold (srl x, 0) -> x 2475 if (N1C && N1C->isNullValue()) 2476 return N0; 2477 // if (srl x, c) is known to be zero, return 0 2478 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), 2479 APInt::getAllOnesValue(OpSizeInBits))) 2480 return DAG.getConstant(0, VT); 2481 2482 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2) 2483 if (N1C && N0.getOpcode() == ISD::SRL && 2484 N0.getOperand(1).getOpcode() == ISD::Constant) { 2485 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2486 uint64_t c2 = N1C->getValue(); 2487 if (c1 + c2 > OpSizeInBits) 2488 return DAG.getConstant(0, VT); 2489 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 2490 DAG.getConstant(c1 + c2, N1.getValueType())); 2491 } 2492 2493 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 2494 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2495 // Shifting in all undef bits? 2496 MVT SmallVT = N0.getOperand(0).getValueType(); 2497 if (N1C->getValue() >= SmallVT.getSizeInBits()) 2498 return DAG.getNode(ISD::UNDEF, VT); 2499 2500 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1); 2501 AddToWorkList(SmallShift.Val); 2502 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift); 2503 } 2504 2505 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 2506 // bit, which is unmodified by sra. 2507 if (N1C && N1C->getValue()+1 == VT.getSizeInBits()) { 2508 if (N0.getOpcode() == ISD::SRA) 2509 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1); 2510 } 2511 2512 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 2513 if (N1C && N0.getOpcode() == ISD::CTLZ && 2514 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 2515 APInt KnownZero, KnownOne; 2516 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 2517 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 2518 2519 // If any of the input bits are KnownOne, then the input couldn't be all 2520 // zeros, thus the result of the srl will always be zero. 2521 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 2522 2523 // If all of the bits input the to ctlz node are known to be zero, then 2524 // the result of the ctlz is "32" and the result of the shift is one. 2525 APInt UnknownBits = ~KnownZero & Mask; 2526 if (UnknownBits == 0) return DAG.getConstant(1, VT); 2527 2528 // Otherwise, check to see if there is exactly one bit input to the ctlz. 2529 if ((UnknownBits & (UnknownBits-1)) == 0) { 2530 // Okay, we know that only that the single bit specified by UnknownBits 2531 // could be set on input to the CTLZ node. If this bit is set, the SRL 2532 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 2533 // to an SRL,XOR pair, which is likely to simplify more. 2534 unsigned ShAmt = UnknownBits.countTrailingZeros(); 2535 SDOperand Op = N0.getOperand(0); 2536 if (ShAmt) { 2537 Op = DAG.getNode(ISD::SRL, VT, Op, 2538 DAG.getConstant(ShAmt, TLI.getShiftAmountTy())); 2539 AddToWorkList(Op.Val); 2540 } 2541 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT)); 2542 } 2543 } 2544 2545 // fold operands of srl based on knowledge that the low bits are not 2546 // demanded. 2547 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 2548 return SDOperand(N, 0); 2549 2550 return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDOperand(); 2551} 2552 2553SDOperand DAGCombiner::visitCTLZ(SDNode *N) { 2554 SDOperand N0 = N->getOperand(0); 2555 MVT VT = N->getValueType(0); 2556 2557 // fold (ctlz c1) -> c2 2558 if (isa<ConstantSDNode>(N0)) 2559 return DAG.getNode(ISD::CTLZ, VT, N0); 2560 return SDOperand(); 2561} 2562 2563SDOperand DAGCombiner::visitCTTZ(SDNode *N) { 2564 SDOperand N0 = N->getOperand(0); 2565 MVT VT = N->getValueType(0); 2566 2567 // fold (cttz c1) -> c2 2568 if (isa<ConstantSDNode>(N0)) 2569 return DAG.getNode(ISD::CTTZ, VT, N0); 2570 return SDOperand(); 2571} 2572 2573SDOperand DAGCombiner::visitCTPOP(SDNode *N) { 2574 SDOperand N0 = N->getOperand(0); 2575 MVT VT = N->getValueType(0); 2576 2577 // fold (ctpop c1) -> c2 2578 if (isa<ConstantSDNode>(N0)) 2579 return DAG.getNode(ISD::CTPOP, VT, N0); 2580 return SDOperand(); 2581} 2582 2583SDOperand DAGCombiner::visitSELECT(SDNode *N) { 2584 SDOperand N0 = N->getOperand(0); 2585 SDOperand N1 = N->getOperand(1); 2586 SDOperand N2 = N->getOperand(2); 2587 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2588 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2589 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 2590 MVT VT = N->getValueType(0); 2591 MVT VT0 = N0.getValueType(); 2592 2593 // fold select C, X, X -> X 2594 if (N1 == N2) 2595 return N1; 2596 // fold select true, X, Y -> X 2597 if (N0C && !N0C->isNullValue()) 2598 return N1; 2599 // fold select false, X, Y -> Y 2600 if (N0C && N0C->isNullValue()) 2601 return N2; 2602 // fold select C, 1, X -> C | X 2603 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 2604 return DAG.getNode(ISD::OR, VT, N0, N2); 2605 // fold select C, 0, 1 -> ~C 2606 if (VT.isInteger() && VT0.isInteger() && 2607 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 2608 SDOperand XORNode = DAG.getNode(ISD::XOR, VT0, N0, DAG.getConstant(1, VT0)); 2609 if (VT == VT0) 2610 return XORNode; 2611 AddToWorkList(XORNode.Val); 2612 if (VT.bitsGT(VT0)) 2613 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode); 2614 return DAG.getNode(ISD::TRUNCATE, VT, XORNode); 2615 } 2616 // fold select C, 0, X -> ~C & X 2617 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 2618 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 2619 AddToWorkList(XORNode.Val); 2620 return DAG.getNode(ISD::AND, VT, XORNode, N2); 2621 } 2622 // fold select C, X, 1 -> ~C | X 2623 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 2624 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 2625 AddToWorkList(XORNode.Val); 2626 return DAG.getNode(ISD::OR, VT, XORNode, N1); 2627 } 2628 // fold select C, X, 0 -> C & X 2629 // FIXME: this should check for C type == X type, not i1? 2630 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 2631 return DAG.getNode(ISD::AND, VT, N0, N1); 2632 // fold X ? X : Y --> X ? 1 : Y --> X | Y 2633 if (VT == MVT::i1 && N0 == N1) 2634 return DAG.getNode(ISD::OR, VT, N0, N2); 2635 // fold X ? Y : X --> X ? Y : 0 --> X & Y 2636 if (VT == MVT::i1 && N0 == N2) 2637 return DAG.getNode(ISD::AND, VT, N0, N1); 2638 2639 // If we can fold this based on the true/false value, do so. 2640 if (SimplifySelectOps(N, N1, N2)) 2641 return SDOperand(N, 0); // Don't revisit N. 2642 2643 // fold selects based on a setcc into other things, such as min/max/abs 2644 if (N0.getOpcode() == ISD::SETCC) { 2645 // FIXME: 2646 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 2647 // having to say they don't support SELECT_CC on every type the DAG knows 2648 // about, since there is no way to mark an opcode illegal at all value types 2649 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other)) 2650 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1), 2651 N1, N2, N0.getOperand(2)); 2652 else 2653 return SimplifySelect(N0, N1, N2); 2654 } 2655 return SDOperand(); 2656} 2657 2658SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) { 2659 SDOperand N0 = N->getOperand(0); 2660 SDOperand N1 = N->getOperand(1); 2661 SDOperand N2 = N->getOperand(2); 2662 SDOperand N3 = N->getOperand(3); 2663 SDOperand N4 = N->getOperand(4); 2664 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 2665 2666 // fold select_cc lhs, rhs, x, x, cc -> x 2667 if (N2 == N3) 2668 return N2; 2669 2670 // Determine if the condition we're dealing with is constant 2671 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultType(N0), N0, N1, CC, false); 2672 if (SCC.Val) AddToWorkList(SCC.Val); 2673 2674 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) { 2675 if (!SCCC->isNullValue()) 2676 return N2; // cond always true -> true val 2677 else 2678 return N3; // cond always false -> false val 2679 } 2680 2681 // Fold to a simpler select_cc 2682 if (SCC.Val && SCC.getOpcode() == ISD::SETCC) 2683 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(), 2684 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 2685 SCC.getOperand(2)); 2686 2687 // If we can fold this based on the true/false value, do so. 2688 if (SimplifySelectOps(N, N2, N3)) 2689 return SDOperand(N, 0); // Don't revisit N. 2690 2691 // fold select_cc into other things, such as min/max/abs 2692 return SimplifySelectCC(N0, N1, N2, N3, CC); 2693} 2694 2695SDOperand DAGCombiner::visitSETCC(SDNode *N) { 2696 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 2697 cast<CondCodeSDNode>(N->getOperand(2))->get()); 2698} 2699 2700// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 2701// "fold ({s|z}ext (load x)) -> ({s|z}ext (truncate ({s|z}extload x)))" 2702// transformation. Returns true if extension are possible and the above 2703// mentioned transformation is profitable. 2704static bool ExtendUsesToFormExtLoad(SDNode *N, SDOperand N0, 2705 unsigned ExtOpc, 2706 SmallVector<SDNode*, 4> &ExtendNodes, 2707 TargetLowering &TLI) { 2708 bool HasCopyToRegUses = false; 2709 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 2710 for (SDNode::use_iterator UI = N0.Val->use_begin(), UE = N0.Val->use_end(); 2711 UI != UE; ++UI) { 2712 SDNode *User = UI->getUser(); 2713 if (User == N) 2714 continue; 2715 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 2716 if (User->getOpcode() == ISD::SETCC) { 2717 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 2718 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 2719 // Sign bits will be lost after a zext. 2720 return false; 2721 bool Add = false; 2722 for (unsigned i = 0; i != 2; ++i) { 2723 SDOperand UseOp = User->getOperand(i); 2724 if (UseOp == N0) 2725 continue; 2726 if (!isa<ConstantSDNode>(UseOp)) 2727 return false; 2728 Add = true; 2729 } 2730 if (Add) 2731 ExtendNodes.push_back(User); 2732 } else { 2733 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2734 SDOperand UseOp = User->getOperand(i); 2735 if (UseOp == N0) { 2736 // If truncate from extended type to original load type is free 2737 // on this target, then it's ok to extend a CopyToReg. 2738 if (isTruncFree && User->getOpcode() == ISD::CopyToReg) 2739 HasCopyToRegUses = true; 2740 else 2741 return false; 2742 } 2743 } 2744 } 2745 } 2746 2747 if (HasCopyToRegUses) { 2748 bool BothLiveOut = false; 2749 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 2750 UI != UE; ++UI) { 2751 SDNode *User = UI->getUser(); 2752 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2753 SDOperand UseOp = User->getOperand(i); 2754 if (UseOp.Val == N && UseOp.ResNo == 0) { 2755 BothLiveOut = true; 2756 break; 2757 } 2758 } 2759 } 2760 if (BothLiveOut) 2761 // Both unextended and extended values are live out. There had better be 2762 // good a reason for the transformation. 2763 return ExtendNodes.size(); 2764 } 2765 return true; 2766} 2767 2768SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 2769 SDOperand N0 = N->getOperand(0); 2770 MVT VT = N->getValueType(0); 2771 2772 // fold (sext c1) -> c1 2773 if (isa<ConstantSDNode>(N0)) 2774 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0); 2775 2776 // fold (sext (sext x)) -> (sext x) 2777 // fold (sext (aext x)) -> (sext x) 2778 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2779 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0)); 2780 2781 if (N0.getOpcode() == ISD::TRUNCATE) { 2782 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 2783 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 2784 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2785 if (NarrowLoad.Val) { 2786 if (NarrowLoad.Val != N0.Val) 2787 CombineTo(N0.Val, NarrowLoad); 2788 return DAG.getNode(ISD::SIGN_EXTEND, VT, NarrowLoad); 2789 } 2790 2791 // See if the value being truncated is already sign extended. If so, just 2792 // eliminate the trunc/sext pair. 2793 SDOperand Op = N0.getOperand(0); 2794 unsigned OpBits = Op.getValueType().getSizeInBits(); 2795 unsigned MidBits = N0.getValueType().getSizeInBits(); 2796 unsigned DestBits = VT.getSizeInBits(); 2797 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 2798 2799 if (OpBits == DestBits) { 2800 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 2801 // bits, it is already ready. 2802 if (NumSignBits > DestBits-MidBits) 2803 return Op; 2804 } else if (OpBits < DestBits) { 2805 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 2806 // bits, just sext from i32. 2807 if (NumSignBits > OpBits-MidBits) 2808 return DAG.getNode(ISD::SIGN_EXTEND, VT, Op); 2809 } else { 2810 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 2811 // bits, just truncate to i32. 2812 if (NumSignBits > OpBits-MidBits) 2813 return DAG.getNode(ISD::TRUNCATE, VT, Op); 2814 } 2815 2816 // fold (sext (truncate x)) -> (sextinreg x). 2817 if (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 2818 N0.getValueType())) { 2819 if (Op.getValueType().bitsLT(VT)) 2820 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2821 else if (Op.getValueType().bitsGT(VT)) 2822 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2823 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op, 2824 DAG.getValueType(N0.getValueType())); 2825 } 2826 } 2827 2828 // fold (sext (load x)) -> (sext (truncate (sextload x))) 2829 if (ISD::isNON_EXTLoad(N0.Val) && 2830 (!AfterLegalize||TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType()))){ 2831 bool DoXform = true; 2832 SmallVector<SDNode*, 4> SetCCs; 2833 if (!N0.hasOneUse()) 2834 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 2835 if (DoXform) { 2836 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2837 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2838 LN0->getBasePtr(), LN0->getSrcValue(), 2839 LN0->getSrcValueOffset(), 2840 N0.getValueType(), 2841 LN0->isVolatile(), 2842 LN0->getAlignment()); 2843 CombineTo(N, ExtLoad); 2844 SDOperand Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad); 2845 CombineTo(N0.Val, Trunc, ExtLoad.getValue(1)); 2846 // Extend SetCC uses if necessary. 2847 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 2848 SDNode *SetCC = SetCCs[i]; 2849 SmallVector<SDOperand, 4> Ops; 2850 for (unsigned j = 0; j != 2; ++j) { 2851 SDOperand SOp = SetCC->getOperand(j); 2852 if (SOp == Trunc) 2853 Ops.push_back(ExtLoad); 2854 else 2855 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, VT, SOp)); 2856 } 2857 Ops.push_back(SetCC->getOperand(2)); 2858 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0), 2859 &Ops[0], Ops.size())); 2860 } 2861 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2862 } 2863 } 2864 2865 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 2866 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 2867 if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && 2868 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) { 2869 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2870 MVT EVT = LN0->getMemoryVT(); 2871 if (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) { 2872 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2873 LN0->getBasePtr(), LN0->getSrcValue(), 2874 LN0->getSrcValueOffset(), EVT, 2875 LN0->isVolatile(), 2876 LN0->getAlignment()); 2877 CombineTo(N, ExtLoad); 2878 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2879 ExtLoad.getValue(1)); 2880 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2881 } 2882 } 2883 2884 // sext(setcc x,y,cc) -> select_cc x, y, -1, 0, cc 2885 if (N0.getOpcode() == ISD::SETCC) { 2886 SDOperand SCC = 2887 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 2888 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT), 2889 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 2890 if (SCC.Val) return SCC; 2891 } 2892 2893 // fold (sext x) -> (zext x) if the sign bit is known zero. 2894 if ((!AfterLegalize || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 2895 DAG.SignBitIsZero(N0)) 2896 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 2897 2898 return SDOperand(); 2899} 2900 2901SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) { 2902 SDOperand N0 = N->getOperand(0); 2903 MVT VT = N->getValueType(0); 2904 2905 // fold (zext c1) -> c1 2906 if (isa<ConstantSDNode>(N0)) 2907 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 2908 // fold (zext (zext x)) -> (zext x) 2909 // fold (zext (aext x)) -> (zext x) 2910 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2911 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0)); 2912 2913 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 2914 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 2915 if (N0.getOpcode() == ISD::TRUNCATE) { 2916 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2917 if (NarrowLoad.Val) { 2918 if (NarrowLoad.Val != N0.Val) 2919 CombineTo(N0.Val, NarrowLoad); 2920 return DAG.getNode(ISD::ZERO_EXTEND, VT, NarrowLoad); 2921 } 2922 } 2923 2924 // fold (zext (truncate x)) -> (and x, mask) 2925 if (N0.getOpcode() == ISD::TRUNCATE && 2926 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) { 2927 SDOperand Op = N0.getOperand(0); 2928 if (Op.getValueType().bitsLT(VT)) { 2929 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2930 } else if (Op.getValueType().bitsGT(VT)) { 2931 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2932 } 2933 return DAG.getZeroExtendInReg(Op, N0.getValueType()); 2934 } 2935 2936 // fold (zext (and (trunc x), cst)) -> (and x, cst). 2937 if (N0.getOpcode() == ISD::AND && 2938 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 2939 N0.getOperand(1).getOpcode() == ISD::Constant) { 2940 SDOperand X = N0.getOperand(0).getOperand(0); 2941 if (X.getValueType().bitsLT(VT)) { 2942 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 2943 } else if (X.getValueType().bitsGT(VT)) { 2944 X = DAG.getNode(ISD::TRUNCATE, VT, X); 2945 } 2946 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 2947 Mask.zext(VT.getSizeInBits()); 2948 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 2949 } 2950 2951 // fold (zext (load x)) -> (zext (truncate (zextload x))) 2952 if (ISD::isNON_EXTLoad(N0.Val) && 2953 (!AfterLegalize||TLI.isLoadXLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 2954 bool DoXform = true; 2955 SmallVector<SDNode*, 4> SetCCs; 2956 if (!N0.hasOneUse()) 2957 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 2958 if (DoXform) { 2959 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2960 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 2961 LN0->getBasePtr(), LN0->getSrcValue(), 2962 LN0->getSrcValueOffset(), 2963 N0.getValueType(), 2964 LN0->isVolatile(), 2965 LN0->getAlignment()); 2966 CombineTo(N, ExtLoad); 2967 SDOperand Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad); 2968 CombineTo(N0.Val, Trunc, ExtLoad.getValue(1)); 2969 // Extend SetCC uses if necessary. 2970 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 2971 SDNode *SetCC = SetCCs[i]; 2972 SmallVector<SDOperand, 4> Ops; 2973 for (unsigned j = 0; j != 2; ++j) { 2974 SDOperand SOp = SetCC->getOperand(j); 2975 if (SOp == Trunc) 2976 Ops.push_back(ExtLoad); 2977 else 2978 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, VT, SOp)); 2979 } 2980 Ops.push_back(SetCC->getOperand(2)); 2981 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0), 2982 &Ops[0], Ops.size())); 2983 } 2984 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2985 } 2986 } 2987 2988 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 2989 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 2990 if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && 2991 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) { 2992 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2993 MVT EVT = LN0->getMemoryVT(); 2994 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 2995 LN0->getBasePtr(), LN0->getSrcValue(), 2996 LN0->getSrcValueOffset(), EVT, 2997 LN0->isVolatile(), 2998 LN0->getAlignment()); 2999 CombineTo(N, ExtLoad); 3000 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 3001 ExtLoad.getValue(1)); 3002 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3003 } 3004 3005 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3006 if (N0.getOpcode() == ISD::SETCC) { 3007 SDOperand SCC = 3008 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 3009 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3010 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3011 if (SCC.Val) return SCC; 3012 } 3013 3014 return SDOperand(); 3015} 3016 3017SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) { 3018 SDOperand N0 = N->getOperand(0); 3019 MVT VT = N->getValueType(0); 3020 3021 // fold (aext c1) -> c1 3022 if (isa<ConstantSDNode>(N0)) 3023 return DAG.getNode(ISD::ANY_EXTEND, VT, N0); 3024 // fold (aext (aext x)) -> (aext x) 3025 // fold (aext (zext x)) -> (zext x) 3026 // fold (aext (sext x)) -> (sext x) 3027 if (N0.getOpcode() == ISD::ANY_EXTEND || 3028 N0.getOpcode() == ISD::ZERO_EXTEND || 3029 N0.getOpcode() == ISD::SIGN_EXTEND) 3030 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 3031 3032 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 3033 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 3034 if (N0.getOpcode() == ISD::TRUNCATE) { 3035 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 3036 if (NarrowLoad.Val) { 3037 if (NarrowLoad.Val != N0.Val) 3038 CombineTo(N0.Val, NarrowLoad); 3039 return DAG.getNode(ISD::ANY_EXTEND, VT, NarrowLoad); 3040 } 3041 } 3042 3043 // fold (aext (truncate x)) 3044 if (N0.getOpcode() == ISD::TRUNCATE) { 3045 SDOperand TruncOp = N0.getOperand(0); 3046 if (TruncOp.getValueType() == VT) 3047 return TruncOp; // x iff x size == zext size. 3048 if (TruncOp.getValueType().bitsGT(VT)) 3049 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp); 3050 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp); 3051 } 3052 3053 // fold (aext (and (trunc x), cst)) -> (and x, cst). 3054 if (N0.getOpcode() == ISD::AND && 3055 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3056 N0.getOperand(1).getOpcode() == ISD::Constant) { 3057 SDOperand X = N0.getOperand(0).getOperand(0); 3058 if (X.getValueType().bitsLT(VT)) { 3059 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 3060 } else if (X.getValueType().bitsGT(VT)) { 3061 X = DAG.getNode(ISD::TRUNCATE, VT, X); 3062 } 3063 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3064 Mask.zext(VT.getSizeInBits()); 3065 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 3066 } 3067 3068 // fold (aext (load x)) -> (aext (truncate (extload x))) 3069 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 3070 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) { 3071 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3072 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 3073 LN0->getBasePtr(), LN0->getSrcValue(), 3074 LN0->getSrcValueOffset(), 3075 N0.getValueType(), 3076 LN0->isVolatile(), 3077 LN0->getAlignment()); 3078 CombineTo(N, ExtLoad); 3079 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 3080 ExtLoad.getValue(1)); 3081 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3082 } 3083 3084 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 3085 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 3086 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 3087 if (N0.getOpcode() == ISD::LOAD && 3088 !ISD::isNON_EXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 3089 N0.hasOneUse()) { 3090 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3091 MVT EVT = LN0->getMemoryVT(); 3092 SDOperand ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT, 3093 LN0->getChain(), LN0->getBasePtr(), 3094 LN0->getSrcValue(), 3095 LN0->getSrcValueOffset(), EVT, 3096 LN0->isVolatile(), 3097 LN0->getAlignment()); 3098 CombineTo(N, ExtLoad); 3099 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 3100 ExtLoad.getValue(1)); 3101 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3102 } 3103 3104 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3105 if (N0.getOpcode() == ISD::SETCC) { 3106 SDOperand SCC = 3107 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 3108 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3109 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3110 if (SCC.Val) 3111 return SCC; 3112 } 3113 3114 return SDOperand(); 3115} 3116 3117/// GetDemandedBits - See if the specified operand can be simplified with the 3118/// knowledge that only the bits specified by Mask are used. If so, return the 3119/// simpler operand, otherwise return a null SDOperand. 3120SDOperand DAGCombiner::GetDemandedBits(SDOperand V, const APInt &Mask) { 3121 switch (V.getOpcode()) { 3122 default: break; 3123 case ISD::OR: 3124 case ISD::XOR: 3125 // If the LHS or RHS don't contribute bits to the or, drop them. 3126 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 3127 return V.getOperand(1); 3128 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 3129 return V.getOperand(0); 3130 break; 3131 case ISD::SRL: 3132 // Only look at single-use SRLs. 3133 if (!V.Val->hasOneUse()) 3134 break; 3135 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 3136 // See if we can recursively simplify the LHS. 3137 unsigned Amt = RHSC->getValue(); 3138 APInt NewMask = Mask << Amt; 3139 SDOperand SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 3140 if (SimplifyLHS.Val) { 3141 return DAG.getNode(ISD::SRL, V.getValueType(), 3142 SimplifyLHS, V.getOperand(1)); 3143 } 3144 } 3145 } 3146 return SDOperand(); 3147} 3148 3149/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 3150/// bits and then truncated to a narrower type and where N is a multiple 3151/// of number of bits of the narrower type, transform it to a narrower load 3152/// from address + N / num of bits of new type. If the result is to be 3153/// extended, also fold the extension to form a extending load. 3154SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) { 3155 unsigned Opc = N->getOpcode(); 3156 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 3157 SDOperand N0 = N->getOperand(0); 3158 MVT VT = N->getValueType(0); 3159 MVT EVT = N->getValueType(0); 3160 3161 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then 3162 // extended to VT. 3163 if (Opc == ISD::SIGN_EXTEND_INREG) { 3164 ExtType = ISD::SEXTLOAD; 3165 EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3166 if (AfterLegalize && !TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) 3167 return SDOperand(); 3168 } 3169 3170 unsigned EVTBits = EVT.getSizeInBits(); 3171 unsigned ShAmt = 0; 3172 bool CombineSRL = false; 3173 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 3174 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3175 ShAmt = N01->getValue(); 3176 // Is the shift amount a multiple of size of VT? 3177 if ((ShAmt & (EVTBits-1)) == 0) { 3178 N0 = N0.getOperand(0); 3179 if (N0.getValueType().getSizeInBits() <= EVTBits) 3180 return SDOperand(); 3181 CombineSRL = true; 3182 } 3183 } 3184 } 3185 3186 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 3187 // Do not allow folding to i1 here. i1 is implicitly stored in memory in 3188 // zero extended form: by shrinking the load, we lose track of the fact 3189 // that it is already zero extended. 3190 // FIXME: This should be reevaluated. 3191 VT != MVT::i1) { 3192 assert(N0.getValueType().getSizeInBits() > EVTBits && 3193 "Cannot truncate to larger type!"); 3194 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3195 MVT PtrType = N0.getOperand(1).getValueType(); 3196 // For big endian targets, we need to adjust the offset to the pointer to 3197 // load the correct bytes. 3198 if (TLI.isBigEndian()) { 3199 unsigned LVTStoreBits = N0.getValueType().getStoreSizeInBits(); 3200 unsigned EVTStoreBits = EVT.getStoreSizeInBits(); 3201 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 3202 } 3203 uint64_t PtrOff = ShAmt / 8; 3204 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 3205 SDOperand NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(), 3206 DAG.getConstant(PtrOff, PtrType)); 3207 AddToWorkList(NewPtr.Val); 3208 SDOperand Load = (ExtType == ISD::NON_EXTLOAD) 3209 ? DAG.getLoad(VT, LN0->getChain(), NewPtr, 3210 LN0->getSrcValue(), LN0->getSrcValueOffset(), 3211 LN0->isVolatile(), NewAlign) 3212 : DAG.getExtLoad(ExtType, VT, LN0->getChain(), NewPtr, 3213 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT, 3214 LN0->isVolatile(), NewAlign); 3215 AddToWorkList(N); 3216 if (CombineSRL) { 3217 WorkListRemover DeadNodes(*this); 3218 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), 3219 &DeadNodes); 3220 CombineTo(N->getOperand(0).Val, Load); 3221 } else 3222 CombineTo(N0.Val, Load, Load.getValue(1)); 3223 if (ShAmt) { 3224 if (Opc == ISD::SIGN_EXTEND_INREG) 3225 return DAG.getNode(Opc, VT, Load, N->getOperand(1)); 3226 else 3227 return DAG.getNode(Opc, VT, Load); 3228 } 3229 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3230 } 3231 3232 return SDOperand(); 3233} 3234 3235 3236SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 3237 SDOperand N0 = N->getOperand(0); 3238 SDOperand N1 = N->getOperand(1); 3239 MVT VT = N->getValueType(0); 3240 MVT EVT = cast<VTSDNode>(N1)->getVT(); 3241 unsigned VTBits = VT.getSizeInBits(); 3242 unsigned EVTBits = EVT.getSizeInBits(); 3243 3244 // fold (sext_in_reg c1) -> c1 3245 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 3246 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1); 3247 3248 // If the input is already sign extended, just drop the extension. 3249 if (DAG.ComputeNumSignBits(N0) >= VT.getSizeInBits()-EVTBits+1) 3250 return N0; 3251 3252 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 3253 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 3254 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 3255 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); 3256 } 3257 3258 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 3259 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 3260 return DAG.getZeroExtendInReg(N0, EVT); 3261 3262 // fold operands of sext_in_reg based on knowledge that the top bits are not 3263 // demanded. 3264 if (SimplifyDemandedBits(SDOperand(N, 0))) 3265 return SDOperand(N, 0); 3266 3267 // fold (sext_in_reg (load x)) -> (smaller sextload x) 3268 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 3269 SDOperand NarrowLoad = ReduceLoadWidth(N); 3270 if (NarrowLoad.Val) 3271 return NarrowLoad; 3272 3273 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24 3274 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible. 3275 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 3276 if (N0.getOpcode() == ISD::SRL) { 3277 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 3278 if (ShAmt->getValue()+EVTBits <= VT.getSizeInBits()) { 3279 // We can turn this into an SRA iff the input to the SRL is already sign 3280 // extended enough. 3281 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 3282 if (VT.getSizeInBits()-(ShAmt->getValue()+EVTBits) < InSignBits) 3283 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1)); 3284 } 3285 } 3286 3287 // fold (sext_inreg (extload x)) -> (sextload x) 3288 if (ISD::isEXTLoad(N0.Val) && 3289 ISD::isUNINDEXEDLoad(N0.Val) && 3290 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3291 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) { 3292 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3293 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 3294 LN0->getBasePtr(), LN0->getSrcValue(), 3295 LN0->getSrcValueOffset(), EVT, 3296 LN0->isVolatile(), 3297 LN0->getAlignment()); 3298 CombineTo(N, ExtLoad); 3299 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 3300 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3301 } 3302 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 3303 if (ISD::isZEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 3304 N0.hasOneUse() && 3305 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3306 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) { 3307 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3308 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 3309 LN0->getBasePtr(), LN0->getSrcValue(), 3310 LN0->getSrcValueOffset(), EVT, 3311 LN0->isVolatile(), 3312 LN0->getAlignment()); 3313 CombineTo(N, ExtLoad); 3314 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 3315 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3316 } 3317 return SDOperand(); 3318} 3319 3320SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) { 3321 SDOperand N0 = N->getOperand(0); 3322 MVT VT = N->getValueType(0); 3323 3324 // noop truncate 3325 if (N0.getValueType() == N->getValueType(0)) 3326 return N0; 3327 // fold (truncate c1) -> c1 3328 if (isa<ConstantSDNode>(N0)) 3329 return DAG.getNode(ISD::TRUNCATE, VT, N0); 3330 // fold (truncate (truncate x)) -> (truncate x) 3331 if (N0.getOpcode() == ISD::TRUNCATE) 3332 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 3333 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 3334 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| 3335 N0.getOpcode() == ISD::ANY_EXTEND) { 3336 if (N0.getOperand(0).getValueType().bitsLT(VT)) 3337 // if the source is smaller than the dest, we still need an extend 3338 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 3339 else if (N0.getOperand(0).getValueType().bitsGT(VT)) 3340 // if the source is larger than the dest, than we just need the truncate 3341 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 3342 else 3343 // if the source and dest are the same type, we can drop both the extend 3344 // and the truncate 3345 return N0.getOperand(0); 3346 } 3347 3348 // See if we can simplify the input to this truncate through knowledge that 3349 // only the low bits are being used. For example "trunc (or (shl x, 8), y)" 3350 // -> trunc y 3351 SDOperand Shorter = 3352 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 3353 VT.getSizeInBits())); 3354 if (Shorter.Val) 3355 return DAG.getNode(ISD::TRUNCATE, VT, Shorter); 3356 3357 // fold (truncate (load x)) -> (smaller load x) 3358 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 3359 return ReduceLoadWidth(N); 3360} 3361 3362static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 3363 SDOperand Elt = N->getOperand(i); 3364 if (Elt.getOpcode() != ISD::MERGE_VALUES) 3365 return Elt.Val; 3366 return Elt.getOperand(Elt.ResNo).Val; 3367} 3368 3369/// CombineConsecutiveLoads - build_pair (load, load) -> load 3370/// if load locations are consecutive. 3371SDOperand DAGCombiner::CombineConsecutiveLoads(SDNode *N, MVT VT) { 3372 assert(N->getOpcode() == ISD::BUILD_PAIR); 3373 3374 SDNode *LD1 = getBuildPairElt(N, 0); 3375 if (!ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse()) 3376 return SDOperand(); 3377 MVT LD1VT = LD1->getValueType(0); 3378 SDNode *LD2 = getBuildPairElt(N, 1); 3379 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 3380 if (ISD::isNON_EXTLoad(LD2) && 3381 LD2->hasOneUse() && 3382 TLI.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1, MFI)) { 3383 LoadSDNode *LD = cast<LoadSDNode>(LD1); 3384 unsigned Align = LD->getAlignment(); 3385 unsigned NewAlign = TLI.getTargetMachine().getTargetData()-> 3386 getABITypeAlignment(VT.getTypeForMVT()); 3387 if ((!AfterLegalize || TLI.isTypeLegal(VT)) && 3388 TLI.isOperationLegal(ISD::LOAD, VT) && NewAlign <= Align) 3389 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), 3390 LD->getSrcValue(), LD->getSrcValueOffset(), 3391 LD->isVolatile(), Align); 3392 } 3393 return SDOperand(); 3394} 3395 3396SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) { 3397 SDOperand N0 = N->getOperand(0); 3398 MVT VT = N->getValueType(0); 3399 3400 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 3401 // Only do this before legalize, since afterward the target may be depending 3402 // on the bitconvert. 3403 // First check to see if this is all constant. 3404 if (!AfterLegalize && 3405 N0.getOpcode() == ISD::BUILD_VECTOR && N0.Val->hasOneUse() && 3406 VT.isVector()) { 3407 bool isSimple = true; 3408 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 3409 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 3410 N0.getOperand(i).getOpcode() != ISD::Constant && 3411 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 3412 isSimple = false; 3413 break; 3414 } 3415 3416 MVT DestEltVT = N->getValueType(0).getVectorElementType(); 3417 assert(!DestEltVT.isVector() && 3418 "Element type of vector ValueType must not be vector!"); 3419 if (isSimple) { 3420 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.Val, DestEltVT); 3421 } 3422 } 3423 3424 // If the input is a constant, let getNode() fold it. 3425 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 3426 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0); 3427 if (Res.Val != N) return Res; 3428 } 3429 3430 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2) 3431 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3432 3433 // fold (conv (load x)) -> (load (conv*)x) 3434 // If the resultant load doesn't need a higher alignment than the original! 3435 if (ISD::isNormalLoad(N0.Val) && N0.hasOneUse() && 3436 TLI.isOperationLegal(ISD::LOAD, VT)) { 3437 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3438 unsigned Align = TLI.getTargetMachine().getTargetData()-> 3439 getABITypeAlignment(VT.getTypeForMVT()); 3440 unsigned OrigAlign = LN0->getAlignment(); 3441 if (Align <= OrigAlign) { 3442 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(), 3443 LN0->getSrcValue(), LN0->getSrcValueOffset(), 3444 LN0->isVolatile(), Align); 3445 AddToWorkList(N); 3446 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load), 3447 Load.getValue(1)); 3448 return Load; 3449 } 3450 } 3451 3452 // Fold bitconvert(fneg(x)) -> xor(bitconvert(x), signbit) 3453 // Fold bitconvert(fabs(x)) -> and(bitconvert(x), ~signbit) 3454 // This often reduces constant pool loads. 3455 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && 3456 N0.Val->hasOneUse() && VT.isInteger() && !VT.isVector()) { 3457 SDOperand NewConv = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3458 AddToWorkList(NewConv.Val); 3459 3460 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3461 if (N0.getOpcode() == ISD::FNEG) 3462 return DAG.getNode(ISD::XOR, VT, NewConv, DAG.getConstant(SignBit, VT)); 3463 assert(N0.getOpcode() == ISD::FABS); 3464 return DAG.getNode(ISD::AND, VT, NewConv, DAG.getConstant(~SignBit, VT)); 3465 } 3466 3467 // Fold bitconvert(fcopysign(cst, x)) -> bitconvert(x)&sign | cst&~sign' 3468 // Note that we don't handle copysign(x,cst) because this can always be folded 3469 // to an fneg or fabs. 3470 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse() && 3471 isa<ConstantFPSDNode>(N0.getOperand(0)) && 3472 VT.isInteger() && !VT.isVector()) { 3473 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 3474 SDOperand X = DAG.getNode(ISD::BIT_CONVERT, 3475 MVT::getIntegerVT(OrigXWidth), 3476 N0.getOperand(1)); 3477 AddToWorkList(X.Val); 3478 3479 // If X has a different width than the result/lhs, sext it or truncate it. 3480 unsigned VTWidth = VT.getSizeInBits(); 3481 if (OrigXWidth < VTWidth) { 3482 X = DAG.getNode(ISD::SIGN_EXTEND, VT, X); 3483 AddToWorkList(X.Val); 3484 } else if (OrigXWidth > VTWidth) { 3485 // To get the sign bit in the right place, we have to shift it right 3486 // before truncating. 3487 X = DAG.getNode(ISD::SRL, X.getValueType(), X, 3488 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 3489 AddToWorkList(X.Val); 3490 X = DAG.getNode(ISD::TRUNCATE, VT, X); 3491 AddToWorkList(X.Val); 3492 } 3493 3494 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3495 X = DAG.getNode(ISD::AND, VT, X, DAG.getConstant(SignBit, VT)); 3496 AddToWorkList(X.Val); 3497 3498 SDOperand Cst = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3499 Cst = DAG.getNode(ISD::AND, VT, Cst, DAG.getConstant(~SignBit, VT)); 3500 AddToWorkList(Cst.Val); 3501 3502 return DAG.getNode(ISD::OR, VT, X, Cst); 3503 } 3504 3505 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 3506 if (N0.getOpcode() == ISD::BUILD_PAIR) { 3507 SDOperand CombineLD = CombineConsecutiveLoads(N0.Val, VT); 3508 if (CombineLD.Val) 3509 return CombineLD; 3510 } 3511 3512 return SDOperand(); 3513} 3514 3515SDOperand DAGCombiner::visitBUILD_PAIR(SDNode *N) { 3516 MVT VT = N->getValueType(0); 3517 return CombineConsecutiveLoads(N, VT); 3518} 3519 3520/// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector 3521/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 3522/// destination element value type. 3523SDOperand DAGCombiner:: 3524ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT DstEltVT) { 3525 MVT SrcEltVT = BV->getOperand(0).getValueType(); 3526 3527 // If this is already the right type, we're done. 3528 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0); 3529 3530 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 3531 unsigned DstBitSize = DstEltVT.getSizeInBits(); 3532 3533 // If this is a conversion of N elements of one type to N elements of another 3534 // type, convert each element. This handles FP<->INT cases. 3535 if (SrcBitSize == DstBitSize) { 3536 SmallVector<SDOperand, 8> Ops; 3537 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3538 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i))); 3539 AddToWorkList(Ops.back().Val); 3540 } 3541 MVT VT = MVT::getVectorVT(DstEltVT, 3542 BV->getValueType(0).getVectorNumElements()); 3543 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3544 } 3545 3546 // Otherwise, we're growing or shrinking the elements. To avoid having to 3547 // handle annoying details of growing/shrinking FP values, we convert them to 3548 // int first. 3549 if (SrcEltVT.isFloatingPoint()) { 3550 // Convert the input float vector to a int vector where the elements are the 3551 // same sizes. 3552 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 3553 MVT IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 3554 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).Val; 3555 SrcEltVT = IntVT; 3556 } 3557 3558 // Now we know the input is an integer vector. If the output is a FP type, 3559 // convert to integer first, then to FP of the right size. 3560 if (DstEltVT.isFloatingPoint()) { 3561 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 3562 MVT TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 3563 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).Val; 3564 3565 // Next, convert to FP elements of the same size. 3566 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT); 3567 } 3568 3569 // Okay, we know the src/dst types are both integers of differing types. 3570 // Handling growing first. 3571 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 3572 if (SrcBitSize < DstBitSize) { 3573 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 3574 3575 SmallVector<SDOperand, 8> Ops; 3576 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 3577 i += NumInputsPerOutput) { 3578 bool isLE = TLI.isLittleEndian(); 3579 APInt NewBits = APInt(DstBitSize, 0); 3580 bool EltIsUndef = true; 3581 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 3582 // Shift the previously computed bits over. 3583 NewBits <<= SrcBitSize; 3584 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 3585 if (Op.getOpcode() == ISD::UNDEF) continue; 3586 EltIsUndef = false; 3587 3588 NewBits |= 3589 APInt(cast<ConstantSDNode>(Op)->getAPIntValue()).zext(DstBitSize); 3590 } 3591 3592 if (EltIsUndef) 3593 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 3594 else 3595 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 3596 } 3597 3598 MVT VT = MVT::getVectorVT(DstEltVT, Ops.size()); 3599 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3600 } 3601 3602 // Finally, this must be the case where we are shrinking elements: each input 3603 // turns into multiple outputs. 3604 bool isS2V = ISD::isScalarToVector(BV); 3605 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 3606 MVT VT = MVT::getVectorVT(DstEltVT, NumOutputsPerInput*BV->getNumOperands()); 3607 SmallVector<SDOperand, 8> Ops; 3608 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3609 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 3610 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 3611 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 3612 continue; 3613 } 3614 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getAPIntValue(); 3615 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 3616 APInt ThisVal = APInt(OpVal).trunc(DstBitSize); 3617 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 3618 if (isS2V && i == 0 && j == 0 && APInt(ThisVal).zext(SrcBitSize) == OpVal) 3619 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 3620 return DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Ops[0]); 3621 OpVal = OpVal.lshr(DstBitSize); 3622 } 3623 3624 // For big endian targets, swap the order of the pieces of each element. 3625 if (TLI.isBigEndian()) 3626 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 3627 } 3628 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3629} 3630 3631 3632 3633SDOperand DAGCombiner::visitFADD(SDNode *N) { 3634 SDOperand N0 = N->getOperand(0); 3635 SDOperand N1 = N->getOperand(1); 3636 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3637 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3638 MVT VT = N->getValueType(0); 3639 3640 // fold vector ops 3641 if (VT.isVector()) { 3642 SDOperand FoldedVOp = SimplifyVBinOp(N); 3643 if (FoldedVOp.Val) return FoldedVOp; 3644 } 3645 3646 // fold (fadd c1, c2) -> c1+c2 3647 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3648 return DAG.getNode(ISD::FADD, VT, N0, N1); 3649 // canonicalize constant to RHS 3650 if (N0CFP && !N1CFP) 3651 return DAG.getNode(ISD::FADD, VT, N1, N0); 3652 // fold (A + (-B)) -> A-B 3653 if (isNegatibleForFree(N1, AfterLegalize) == 2) 3654 return DAG.getNode(ISD::FSUB, VT, N0, 3655 GetNegatedExpression(N1, DAG, AfterLegalize)); 3656 // fold ((-A) + B) -> B-A 3657 if (isNegatibleForFree(N0, AfterLegalize) == 2) 3658 return DAG.getNode(ISD::FSUB, VT, N1, 3659 GetNegatedExpression(N0, DAG, AfterLegalize)); 3660 3661 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 3662 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 3663 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3664 return DAG.getNode(ISD::FADD, VT, N0.getOperand(0), 3665 DAG.getNode(ISD::FADD, VT, N0.getOperand(1), N1)); 3666 3667 return SDOperand(); 3668} 3669 3670SDOperand DAGCombiner::visitFSUB(SDNode *N) { 3671 SDOperand N0 = N->getOperand(0); 3672 SDOperand N1 = N->getOperand(1); 3673 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3674 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3675 MVT VT = N->getValueType(0); 3676 3677 // fold vector ops 3678 if (VT.isVector()) { 3679 SDOperand FoldedVOp = SimplifyVBinOp(N); 3680 if (FoldedVOp.Val) return FoldedVOp; 3681 } 3682 3683 // fold (fsub c1, c2) -> c1-c2 3684 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3685 return DAG.getNode(ISD::FSUB, VT, N0, N1); 3686 // fold (0-B) -> -B 3687 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { 3688 if (isNegatibleForFree(N1, AfterLegalize)) 3689 return GetNegatedExpression(N1, DAG, AfterLegalize); 3690 return DAG.getNode(ISD::FNEG, VT, N1); 3691 } 3692 // fold (A-(-B)) -> A+B 3693 if (isNegatibleForFree(N1, AfterLegalize)) 3694 return DAG.getNode(ISD::FADD, VT, N0, 3695 GetNegatedExpression(N1, DAG, AfterLegalize)); 3696 3697 return SDOperand(); 3698} 3699 3700SDOperand DAGCombiner::visitFMUL(SDNode *N) { 3701 SDOperand N0 = N->getOperand(0); 3702 SDOperand N1 = N->getOperand(1); 3703 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3704 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3705 MVT VT = N->getValueType(0); 3706 3707 // fold vector ops 3708 if (VT.isVector()) { 3709 SDOperand FoldedVOp = SimplifyVBinOp(N); 3710 if (FoldedVOp.Val) return FoldedVOp; 3711 } 3712 3713 // fold (fmul c1, c2) -> c1*c2 3714 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3715 return DAG.getNode(ISD::FMUL, VT, N0, N1); 3716 // canonicalize constant to RHS 3717 if (N0CFP && !N1CFP) 3718 return DAG.getNode(ISD::FMUL, VT, N1, N0); 3719 // fold (fmul X, 2.0) -> (fadd X, X) 3720 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 3721 return DAG.getNode(ISD::FADD, VT, N0, N0); 3722 // fold (fmul X, -1.0) -> (fneg X) 3723 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 3724 return DAG.getNode(ISD::FNEG, VT, N0); 3725 3726 // -X * -Y -> X*Y 3727 if (char LHSNeg = isNegatibleForFree(N0, AfterLegalize)) { 3728 if (char RHSNeg = isNegatibleForFree(N1, AfterLegalize)) { 3729 // Both can be negated for free, check to see if at least one is cheaper 3730 // negated. 3731 if (LHSNeg == 2 || RHSNeg == 2) 3732 return DAG.getNode(ISD::FMUL, VT, 3733 GetNegatedExpression(N0, DAG, AfterLegalize), 3734 GetNegatedExpression(N1, DAG, AfterLegalize)); 3735 } 3736 } 3737 3738 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 3739 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 3740 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3741 return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0), 3742 DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1)); 3743 3744 return SDOperand(); 3745} 3746 3747SDOperand DAGCombiner::visitFDIV(SDNode *N) { 3748 SDOperand N0 = N->getOperand(0); 3749 SDOperand N1 = N->getOperand(1); 3750 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3751 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3752 MVT VT = N->getValueType(0); 3753 3754 // fold vector ops 3755 if (VT.isVector()) { 3756 SDOperand FoldedVOp = SimplifyVBinOp(N); 3757 if (FoldedVOp.Val) return FoldedVOp; 3758 } 3759 3760 // fold (fdiv c1, c2) -> c1/c2 3761 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3762 return DAG.getNode(ISD::FDIV, VT, N0, N1); 3763 3764 3765 // -X / -Y -> X*Y 3766 if (char LHSNeg = isNegatibleForFree(N0, AfterLegalize)) { 3767 if (char RHSNeg = isNegatibleForFree(N1, AfterLegalize)) { 3768 // Both can be negated for free, check to see if at least one is cheaper 3769 // negated. 3770 if (LHSNeg == 2 || RHSNeg == 2) 3771 return DAG.getNode(ISD::FDIV, VT, 3772 GetNegatedExpression(N0, DAG, AfterLegalize), 3773 GetNegatedExpression(N1, DAG, AfterLegalize)); 3774 } 3775 } 3776 3777 return SDOperand(); 3778} 3779 3780SDOperand DAGCombiner::visitFREM(SDNode *N) { 3781 SDOperand N0 = N->getOperand(0); 3782 SDOperand N1 = N->getOperand(1); 3783 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3784 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3785 MVT VT = N->getValueType(0); 3786 3787 // fold (frem c1, c2) -> fmod(c1,c2) 3788 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3789 return DAG.getNode(ISD::FREM, VT, N0, N1); 3790 3791 return SDOperand(); 3792} 3793 3794SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) { 3795 SDOperand N0 = N->getOperand(0); 3796 SDOperand N1 = N->getOperand(1); 3797 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3798 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3799 MVT VT = N->getValueType(0); 3800 3801 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 3802 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1); 3803 3804 if (N1CFP) { 3805 const APFloat& V = N1CFP->getValueAPF(); 3806 // copysign(x, c1) -> fabs(x) iff ispos(c1) 3807 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 3808 if (!V.isNegative()) 3809 return DAG.getNode(ISD::FABS, VT, N0); 3810 else 3811 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0)); 3812 } 3813 3814 // copysign(fabs(x), y) -> copysign(x, y) 3815 // copysign(fneg(x), y) -> copysign(x, y) 3816 // copysign(copysign(x,z), y) -> copysign(x, y) 3817 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 3818 N0.getOpcode() == ISD::FCOPYSIGN) 3819 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1); 3820 3821 // copysign(x, abs(y)) -> abs(x) 3822 if (N1.getOpcode() == ISD::FABS) 3823 return DAG.getNode(ISD::FABS, VT, N0); 3824 3825 // copysign(x, copysign(y,z)) -> copysign(x, z) 3826 if (N1.getOpcode() == ISD::FCOPYSIGN) 3827 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1)); 3828 3829 // copysign(x, fp_extend(y)) -> copysign(x, y) 3830 // copysign(x, fp_round(y)) -> copysign(x, y) 3831 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 3832 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0)); 3833 3834 return SDOperand(); 3835} 3836 3837 3838 3839SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) { 3840 SDOperand N0 = N->getOperand(0); 3841 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3842 MVT VT = N->getValueType(0); 3843 3844 // fold (sint_to_fp c1) -> c1fp 3845 if (N0C && N0.getValueType() != MVT::ppcf128) 3846 return DAG.getNode(ISD::SINT_TO_FP, VT, N0); 3847 return SDOperand(); 3848} 3849 3850SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) { 3851 SDOperand N0 = N->getOperand(0); 3852 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3853 MVT VT = N->getValueType(0); 3854 3855 // fold (uint_to_fp c1) -> c1fp 3856 if (N0C && N0.getValueType() != MVT::ppcf128) 3857 return DAG.getNode(ISD::UINT_TO_FP, VT, N0); 3858 return SDOperand(); 3859} 3860 3861SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) { 3862 SDOperand N0 = N->getOperand(0); 3863 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3864 MVT VT = N->getValueType(0); 3865 3866 // fold (fp_to_sint c1fp) -> c1 3867 if (N0CFP) 3868 return DAG.getNode(ISD::FP_TO_SINT, VT, N0); 3869 return SDOperand(); 3870} 3871 3872SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) { 3873 SDOperand N0 = N->getOperand(0); 3874 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3875 MVT VT = N->getValueType(0); 3876 3877 // fold (fp_to_uint c1fp) -> c1 3878 if (N0CFP && VT != MVT::ppcf128) 3879 return DAG.getNode(ISD::FP_TO_UINT, VT, N0); 3880 return SDOperand(); 3881} 3882 3883SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) { 3884 SDOperand N0 = N->getOperand(0); 3885 SDOperand N1 = N->getOperand(1); 3886 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3887 MVT VT = N->getValueType(0); 3888 3889 // fold (fp_round c1fp) -> c1fp 3890 if (N0CFP && N0.getValueType() != MVT::ppcf128) 3891 return DAG.getNode(ISD::FP_ROUND, VT, N0, N1); 3892 3893 // fold (fp_round (fp_extend x)) -> x 3894 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 3895 return N0.getOperand(0); 3896 3897 // fold (fp_round (fp_round x)) -> (fp_round x) 3898 if (N0.getOpcode() == ISD::FP_ROUND) { 3899 // This is a value preserving truncation if both round's are. 3900 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 3901 N0.Val->getConstantOperandVal(1) == 1; 3902 return DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0), 3903 DAG.getIntPtrConstant(IsTrunc)); 3904 } 3905 3906 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 3907 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) { 3908 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0), N1); 3909 AddToWorkList(Tmp.Val); 3910 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1)); 3911 } 3912 3913 return SDOperand(); 3914} 3915 3916SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 3917 SDOperand N0 = N->getOperand(0); 3918 MVT VT = N->getValueType(0); 3919 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3920 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3921 3922 // fold (fp_round_inreg c1fp) -> c1fp 3923 if (N0CFP) { 3924 SDOperand Round = DAG.getConstantFP(N0CFP->getValueAPF(), EVT); 3925 return DAG.getNode(ISD::FP_EXTEND, VT, Round); 3926 } 3927 return SDOperand(); 3928} 3929 3930SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) { 3931 SDOperand N0 = N->getOperand(0); 3932 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3933 MVT VT = N->getValueType(0); 3934 3935 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 3936 if (N->hasOneUse() && 3937 N->use_begin()->getSDOperand().getOpcode() == ISD::FP_ROUND) 3938 return SDOperand(); 3939 3940 // fold (fp_extend c1fp) -> c1fp 3941 if (N0CFP && VT != MVT::ppcf128) 3942 return DAG.getNode(ISD::FP_EXTEND, VT, N0); 3943 3944 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 3945 // value of X. 3946 if (N0.getOpcode() == ISD::FP_ROUND && N0.Val->getConstantOperandVal(1) == 1){ 3947 SDOperand In = N0.getOperand(0); 3948 if (In.getValueType() == VT) return In; 3949 if (VT.bitsLT(In.getValueType())) 3950 return DAG.getNode(ISD::FP_ROUND, VT, In, N0.getOperand(1)); 3951 return DAG.getNode(ISD::FP_EXTEND, VT, In); 3952 } 3953 3954 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 3955 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 3956 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) { 3957 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3958 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 3959 LN0->getBasePtr(), LN0->getSrcValue(), 3960 LN0->getSrcValueOffset(), 3961 N0.getValueType(), 3962 LN0->isVolatile(), 3963 LN0->getAlignment()); 3964 CombineTo(N, ExtLoad); 3965 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad, 3966 DAG.getIntPtrConstant(1)), 3967 ExtLoad.getValue(1)); 3968 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3969 } 3970 3971 3972 return SDOperand(); 3973} 3974 3975SDOperand DAGCombiner::visitFNEG(SDNode *N) { 3976 SDOperand N0 = N->getOperand(0); 3977 3978 if (isNegatibleForFree(N0, AfterLegalize)) 3979 return GetNegatedExpression(N0, DAG, AfterLegalize); 3980 3981 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 3982 // constant pool values. 3983 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.Val->hasOneUse() && 3984 N0.getOperand(0).getValueType().isInteger() && 3985 !N0.getOperand(0).getValueType().isVector()) { 3986 SDOperand Int = N0.getOperand(0); 3987 MVT IntVT = Int.getValueType(); 3988 if (IntVT.isInteger() && !IntVT.isVector()) { 3989 Int = DAG.getNode(ISD::XOR, IntVT, Int, 3990 DAG.getConstant(IntVT.getIntegerVTSignBit(), IntVT)); 3991 AddToWorkList(Int.Val); 3992 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int); 3993 } 3994 } 3995 3996 return SDOperand(); 3997} 3998 3999SDOperand DAGCombiner::visitFABS(SDNode *N) { 4000 SDOperand N0 = N->getOperand(0); 4001 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4002 MVT VT = N->getValueType(0); 4003 4004 // fold (fabs c1) -> fabs(c1) 4005 if (N0CFP && VT != MVT::ppcf128) 4006 return DAG.getNode(ISD::FABS, VT, N0); 4007 // fold (fabs (fabs x)) -> (fabs x) 4008 if (N0.getOpcode() == ISD::FABS) 4009 return N->getOperand(0); 4010 // fold (fabs (fneg x)) -> (fabs x) 4011 // fold (fabs (fcopysign x, y)) -> (fabs x) 4012 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 4013 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0)); 4014 4015 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 4016 // constant pool values. 4017 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.Val->hasOneUse() && 4018 N0.getOperand(0).getValueType().isInteger() && 4019 !N0.getOperand(0).getValueType().isVector()) { 4020 SDOperand Int = N0.getOperand(0); 4021 MVT IntVT = Int.getValueType(); 4022 if (IntVT.isInteger() && !IntVT.isVector()) { 4023 Int = DAG.getNode(ISD::AND, IntVT, Int, 4024 DAG.getConstant(~IntVT.getIntegerVTSignBit(), IntVT)); 4025 AddToWorkList(Int.Val); 4026 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int); 4027 } 4028 } 4029 4030 return SDOperand(); 4031} 4032 4033SDOperand DAGCombiner::visitBRCOND(SDNode *N) { 4034 SDOperand Chain = N->getOperand(0); 4035 SDOperand N1 = N->getOperand(1); 4036 SDOperand N2 = N->getOperand(2); 4037 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 4038 4039 // never taken branch, fold to chain 4040 if (N1C && N1C->isNullValue()) 4041 return Chain; 4042 // unconditional branch 4043 if (N1C && N1C->getAPIntValue() == 1) 4044 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 4045 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 4046 // on the target. 4047 if (N1.getOpcode() == ISD::SETCC && 4048 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) { 4049 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2), 4050 N1.getOperand(0), N1.getOperand(1), N2); 4051 } 4052 return SDOperand(); 4053} 4054 4055// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 4056// 4057SDOperand DAGCombiner::visitBR_CC(SDNode *N) { 4058 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 4059 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 4060 4061 // Use SimplifySetCC to simplify SETCC's. 4062 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false); 4063 if (Simp.Val) AddToWorkList(Simp.Val); 4064 4065 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val); 4066 4067 // fold br_cc true, dest -> br dest (unconditional branch) 4068 if (SCCC && !SCCC->isNullValue()) 4069 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0), 4070 N->getOperand(4)); 4071 // fold br_cc false, dest -> unconditional fall through 4072 if (SCCC && SCCC->isNullValue()) 4073 return N->getOperand(0); 4074 4075 // fold to a simpler setcc 4076 if (Simp.Val && Simp.getOpcode() == ISD::SETCC) 4077 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0), 4078 Simp.getOperand(2), Simp.getOperand(0), 4079 Simp.getOperand(1), N->getOperand(4)); 4080 return SDOperand(); 4081} 4082 4083 4084/// CombineToPreIndexedLoadStore - Try turning a load / store and a 4085/// pre-indexed load / store when the base pointer is a add or subtract 4086/// and it has other uses besides the load / store. After the 4087/// transformation, the new indexed load / store has effectively folded 4088/// the add / subtract in and all of its other uses are redirected to the 4089/// new load / store. 4090bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 4091 if (!AfterLegalize) 4092 return false; 4093 4094 bool isLoad = true; 4095 SDOperand Ptr; 4096 MVT VT; 4097 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4098 if (LD->isIndexed()) 4099 return false; 4100 VT = LD->getMemoryVT(); 4101 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 4102 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 4103 return false; 4104 Ptr = LD->getBasePtr(); 4105 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4106 if (ST->isIndexed()) 4107 return false; 4108 VT = ST->getMemoryVT(); 4109 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 4110 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 4111 return false; 4112 Ptr = ST->getBasePtr(); 4113 isLoad = false; 4114 } else 4115 return false; 4116 4117 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 4118 // out. There is no reason to make this a preinc/predec. 4119 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 4120 Ptr.Val->hasOneUse()) 4121 return false; 4122 4123 // Ask the target to do addressing mode selection. 4124 SDOperand BasePtr; 4125 SDOperand Offset; 4126 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4127 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 4128 return false; 4129 // Don't create a indexed load / store with zero offset. 4130 if (isa<ConstantSDNode>(Offset) && 4131 cast<ConstantSDNode>(Offset)->isNullValue()) 4132 return false; 4133 4134 // Try turning it into a pre-indexed load / store except when: 4135 // 1) The new base ptr is a frame index. 4136 // 2) If N is a store and the new base ptr is either the same as or is a 4137 // predecessor of the value being stored. 4138 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 4139 // that would create a cycle. 4140 // 4) All uses are load / store ops that use it as old base ptr. 4141 4142 // Check #1. Preinc'ing a frame index would require copying the stack pointer 4143 // (plus the implicit offset) to a register to preinc anyway. 4144 if (isa<FrameIndexSDNode>(BasePtr)) 4145 return false; 4146 4147 // Check #2. 4148 if (!isLoad) { 4149 SDOperand Val = cast<StoreSDNode>(N)->getValue(); 4150 if (Val == BasePtr || BasePtr.Val->isPredecessorOf(Val.Val)) 4151 return false; 4152 } 4153 4154 // Now check for #3 and #4. 4155 bool RealUse = false; 4156 for (SDNode::use_iterator I = Ptr.Val->use_begin(), 4157 E = Ptr.Val->use_end(); I != E; ++I) { 4158 SDNode *Use = I->getUser(); 4159 if (Use == N) 4160 continue; 4161 if (Use->isPredecessorOf(N)) 4162 return false; 4163 4164 if (!((Use->getOpcode() == ISD::LOAD && 4165 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 4166 (Use->getOpcode() == ISD::STORE && 4167 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))) 4168 RealUse = true; 4169 } 4170 if (!RealUse) 4171 return false; 4172 4173 SDOperand Result; 4174 if (isLoad) 4175 Result = DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM); 4176 else 4177 Result = DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM); 4178 ++PreIndexedNodes; 4179 ++NodesCombined; 4180 DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG)); 4181 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG)); 4182 DOUT << '\n'; 4183 WorkListRemover DeadNodes(*this); 4184 if (isLoad) { 4185 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0), 4186 &DeadNodes); 4187 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2), 4188 &DeadNodes); 4189 } else { 4190 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1), 4191 &DeadNodes); 4192 } 4193 4194 // Finally, since the node is now dead, remove it from the graph. 4195 DAG.DeleteNode(N); 4196 4197 // Replace the uses of Ptr with uses of the updated base value. 4198 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 4199 &DeadNodes); 4200 removeFromWorkList(Ptr.Val); 4201 DAG.DeleteNode(Ptr.Val); 4202 4203 return true; 4204} 4205 4206/// CombineToPostIndexedLoadStore - Try combine a load / store with a 4207/// add / sub of the base pointer node into a post-indexed load / store. 4208/// The transformation folded the add / subtract into the new indexed 4209/// load / store effectively and all of its uses are redirected to the 4210/// new load / store. 4211bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 4212 if (!AfterLegalize) 4213 return false; 4214 4215 bool isLoad = true; 4216 SDOperand Ptr; 4217 MVT VT; 4218 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4219 if (LD->isIndexed()) 4220 return false; 4221 VT = LD->getMemoryVT(); 4222 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 4223 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 4224 return false; 4225 Ptr = LD->getBasePtr(); 4226 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4227 if (ST->isIndexed()) 4228 return false; 4229 VT = ST->getMemoryVT(); 4230 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 4231 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 4232 return false; 4233 Ptr = ST->getBasePtr(); 4234 isLoad = false; 4235 } else 4236 return false; 4237 4238 if (Ptr.Val->hasOneUse()) 4239 return false; 4240 4241 for (SDNode::use_iterator I = Ptr.Val->use_begin(), 4242 E = Ptr.Val->use_end(); I != E; ++I) { 4243 SDNode *Op = I->getUser(); 4244 if (Op == N || 4245 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 4246 continue; 4247 4248 SDOperand BasePtr; 4249 SDOperand Offset; 4250 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4251 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 4252 if (Ptr == Offset) 4253 std::swap(BasePtr, Offset); 4254 if (Ptr != BasePtr) 4255 continue; 4256 // Don't create a indexed load / store with zero offset. 4257 if (isa<ConstantSDNode>(Offset) && 4258 cast<ConstantSDNode>(Offset)->isNullValue()) 4259 continue; 4260 4261 // Try turning it into a post-indexed load / store except when 4262 // 1) All uses are load / store ops that use it as base ptr. 4263 // 2) Op must be independent of N, i.e. Op is neither a predecessor 4264 // nor a successor of N. Otherwise, if Op is folded that would 4265 // create a cycle. 4266 4267 // Check for #1. 4268 bool TryNext = false; 4269 for (SDNode::use_iterator II = BasePtr.Val->use_begin(), 4270 EE = BasePtr.Val->use_end(); II != EE; ++II) { 4271 SDNode *Use = II->getUser(); 4272 if (Use == Ptr.Val) 4273 continue; 4274 4275 // If all the uses are load / store addresses, then don't do the 4276 // transformation. 4277 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 4278 bool RealUse = false; 4279 for (SDNode::use_iterator III = Use->use_begin(), 4280 EEE = Use->use_end(); III != EEE; ++III) { 4281 SDNode *UseUse = III->getUser(); 4282 if (!((UseUse->getOpcode() == ISD::LOAD && 4283 cast<LoadSDNode>(UseUse)->getBasePtr().Val == Use) || 4284 (UseUse->getOpcode() == ISD::STORE && 4285 cast<StoreSDNode>(UseUse)->getBasePtr().Val == Use))) 4286 RealUse = true; 4287 } 4288 4289 if (!RealUse) { 4290 TryNext = true; 4291 break; 4292 } 4293 } 4294 } 4295 if (TryNext) 4296 continue; 4297 4298 // Check for #2 4299 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 4300 SDOperand Result = isLoad 4301 ? DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM) 4302 : DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM); 4303 ++PostIndexedNodes; 4304 ++NodesCombined; 4305 DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG)); 4306 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG)); 4307 DOUT << '\n'; 4308 WorkListRemover DeadNodes(*this); 4309 if (isLoad) { 4310 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0), 4311 &DeadNodes); 4312 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2), 4313 &DeadNodes); 4314 } else { 4315 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1), 4316 &DeadNodes); 4317 } 4318 4319 // Finally, since the node is now dead, remove it from the graph. 4320 DAG.DeleteNode(N); 4321 4322 // Replace the uses of Use with uses of the updated base value. 4323 DAG.ReplaceAllUsesOfValueWith(SDOperand(Op, 0), 4324 Result.getValue(isLoad ? 1 : 0), 4325 &DeadNodes); 4326 removeFromWorkList(Op); 4327 DAG.DeleteNode(Op); 4328 return true; 4329 } 4330 } 4331 } 4332 return false; 4333} 4334 4335/// InferAlignment - If we can infer some alignment information from this 4336/// pointer, return it. 4337static unsigned InferAlignment(SDOperand Ptr, SelectionDAG &DAG) { 4338 // If this is a direct reference to a stack slot, use information about the 4339 // stack slot's alignment. 4340 int FrameIdx = 1 << 31; 4341 int64_t FrameOffset = 0; 4342 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Ptr)) { 4343 FrameIdx = FI->getIndex(); 4344 } else if (Ptr.getOpcode() == ISD::ADD && 4345 isa<ConstantSDNode>(Ptr.getOperand(1)) && 4346 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 4347 FrameIdx = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 4348 FrameOffset = Ptr.getConstantOperandVal(1); 4349 } 4350 4351 if (FrameIdx != (1 << 31)) { 4352 // FIXME: Handle FI+CST. 4353 const MachineFrameInfo &MFI = *DAG.getMachineFunction().getFrameInfo(); 4354 if (MFI.isFixedObjectIndex(FrameIdx)) { 4355 int64_t ObjectOffset = MFI.getObjectOffset(FrameIdx); 4356 4357 // The alignment of the frame index can be determined from its offset from 4358 // the incoming frame position. If the frame object is at offset 32 and 4359 // the stack is guaranteed to be 16-byte aligned, then we know that the 4360 // object is 16-byte aligned. 4361 unsigned StackAlign = DAG.getTarget().getFrameInfo()->getStackAlignment(); 4362 unsigned Align = MinAlign(ObjectOffset, StackAlign); 4363 4364 // Finally, the frame object itself may have a known alignment. Factor 4365 // the alignment + offset into a new alignment. For example, if we know 4366 // the FI is 8 byte aligned, but the pointer is 4 off, we really have a 4367 // 4-byte alignment of the resultant pointer. Likewise align 4 + 4-byte 4368 // offset = 4-byte alignment, align 4 + 1-byte offset = align 1, etc. 4369 unsigned FIInfoAlign = MinAlign(MFI.getObjectAlignment(FrameIdx), 4370 FrameOffset); 4371 return std::max(Align, FIInfoAlign); 4372 } 4373 } 4374 4375 return 0; 4376} 4377 4378SDOperand DAGCombiner::visitLOAD(SDNode *N) { 4379 LoadSDNode *LD = cast<LoadSDNode>(N); 4380 SDOperand Chain = LD->getChain(); 4381 SDOperand Ptr = LD->getBasePtr(); 4382 4383 // Try to infer better alignment information than the load already has. 4384 if (LD->isUnindexed()) { 4385 if (unsigned Align = InferAlignment(Ptr, DAG)) { 4386 if (Align > LD->getAlignment()) 4387 return DAG.getExtLoad(LD->getExtensionType(), LD->getValueType(0), 4388 Chain, Ptr, LD->getSrcValue(), 4389 LD->getSrcValueOffset(), LD->getMemoryVT(), 4390 LD->isVolatile(), Align); 4391 } 4392 } 4393 4394 4395 // If load is not volatile and there are no uses of the loaded value (and 4396 // the updated indexed value in case of indexed loads), change uses of the 4397 // chain value into uses of the chain input (i.e. delete the dead load). 4398 if (!LD->isVolatile()) { 4399 if (N->getValueType(1) == MVT::Other) { 4400 // Unindexed loads. 4401 if (N->hasNUsesOfValue(0, 0)) { 4402 // It's not safe to use the two value CombineTo variant here. e.g. 4403 // v1, chain2 = load chain1, loc 4404 // v2, chain3 = load chain2, loc 4405 // v3 = add v2, c 4406 // Now we replace use of chain2 with chain1. This makes the second load 4407 // isomorphic to the one we are deleting, and thus makes this load live. 4408 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4409 DOUT << "\nWith chain: "; DEBUG(Chain.Val->dump(&DAG)); 4410 DOUT << "\n"; 4411 WorkListRemover DeadNodes(*this); 4412 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Chain, &DeadNodes); 4413 if (N->use_empty()) { 4414 removeFromWorkList(N); 4415 DAG.DeleteNode(N); 4416 } 4417 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 4418 } 4419 } else { 4420 // Indexed loads. 4421 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 4422 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 4423 SDOperand Undef = DAG.getNode(ISD::UNDEF, N->getValueType(0)); 4424 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4425 DOUT << "\nWith: "; DEBUG(Undef.Val->dump(&DAG)); 4426 DOUT << " and 2 other values\n"; 4427 WorkListRemover DeadNodes(*this); 4428 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Undef, &DeadNodes); 4429 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), 4430 DAG.getNode(ISD::UNDEF, N->getValueType(1)), 4431 &DeadNodes); 4432 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 2), Chain, &DeadNodes); 4433 removeFromWorkList(N); 4434 DAG.DeleteNode(N); 4435 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 4436 } 4437 } 4438 } 4439 4440 // If this load is directly stored, replace the load value with the stored 4441 // value. 4442 // TODO: Handle store large -> read small portion. 4443 // TODO: Handle TRUNCSTORE/LOADEXT 4444 if (LD->getExtensionType() == ISD::NON_EXTLOAD && 4445 !LD->isVolatile()) { 4446 if (ISD::isNON_TRUNCStore(Chain.Val)) { 4447 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 4448 if (PrevST->getBasePtr() == Ptr && 4449 PrevST->getValue().getValueType() == N->getValueType(0)) 4450 return CombineTo(N, Chain.getOperand(1), Chain); 4451 } 4452 } 4453 4454 if (CombinerAA) { 4455 // Walk up chain skipping non-aliasing memory nodes. 4456 SDOperand BetterChain = FindBetterChain(N, Chain); 4457 4458 // If there is a better chain. 4459 if (Chain != BetterChain) { 4460 SDOperand ReplLoad; 4461 4462 // Replace the chain to void dependency. 4463 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 4464 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr, 4465 LD->getSrcValue(), LD->getSrcValueOffset(), 4466 LD->isVolatile(), LD->getAlignment()); 4467 } else { 4468 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), 4469 LD->getValueType(0), 4470 BetterChain, Ptr, LD->getSrcValue(), 4471 LD->getSrcValueOffset(), 4472 LD->getMemoryVT(), 4473 LD->isVolatile(), 4474 LD->getAlignment()); 4475 } 4476 4477 // Create token factor to keep old chain connected. 4478 SDOperand Token = DAG.getNode(ISD::TokenFactor, MVT::Other, 4479 Chain, ReplLoad.getValue(1)); 4480 4481 // Replace uses with load result and token factor. Don't add users 4482 // to work list. 4483 return CombineTo(N, ReplLoad.getValue(0), Token, false); 4484 } 4485 } 4486 4487 // Try transforming N to an indexed load. 4488 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4489 return SDOperand(N, 0); 4490 4491 return SDOperand(); 4492} 4493 4494 4495SDOperand DAGCombiner::visitSTORE(SDNode *N) { 4496 StoreSDNode *ST = cast<StoreSDNode>(N); 4497 SDOperand Chain = ST->getChain(); 4498 SDOperand Value = ST->getValue(); 4499 SDOperand Ptr = ST->getBasePtr(); 4500 4501 // Try to infer better alignment information than the store already has. 4502 if (ST->isUnindexed()) { 4503 if (unsigned Align = InferAlignment(Ptr, DAG)) { 4504 if (Align > ST->getAlignment()) 4505 return DAG.getTruncStore(Chain, Value, Ptr, ST->getSrcValue(), 4506 ST->getSrcValueOffset(), ST->getMemoryVT(), 4507 ST->isVolatile(), Align); 4508 } 4509 } 4510 4511 // If this is a store of a bit convert, store the input value if the 4512 // resultant store does not need a higher alignment than the original. 4513 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() && 4514 ST->isUnindexed()) { 4515 unsigned Align = ST->getAlignment(); 4516 MVT SVT = Value.getOperand(0).getValueType(); 4517 unsigned OrigAlign = TLI.getTargetMachine().getTargetData()-> 4518 getABITypeAlignment(SVT.getTypeForMVT()); 4519 if (Align <= OrigAlign && TLI.isOperationLegal(ISD::STORE, SVT)) 4520 return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), 4521 ST->getSrcValueOffset(), ST->isVolatile(), Align); 4522 } 4523 4524 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 4525 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 4526 if (Value.getOpcode() != ISD::TargetConstantFP) { 4527 SDOperand Tmp; 4528 switch (CFP->getValueType(0).getSimpleVT()) { 4529 default: assert(0 && "Unknown FP type"); 4530 case MVT::f80: // We don't do this for these yet. 4531 case MVT::f128: 4532 case MVT::ppcf128: 4533 break; 4534 case MVT::f32: 4535 if (!AfterLegalize || TLI.isTypeLegal(MVT::i32)) { 4536 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 4537 convertToAPInt().getZExtValue(), MVT::i32); 4538 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 4539 ST->getSrcValueOffset(), ST->isVolatile(), 4540 ST->getAlignment()); 4541 } 4542 break; 4543 case MVT::f64: 4544 if (!AfterLegalize || TLI.isTypeLegal(MVT::i64)) { 4545 Tmp = DAG.getConstant(CFP->getValueAPF().convertToAPInt(). 4546 getZExtValue(), MVT::i64); 4547 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 4548 ST->getSrcValueOffset(), ST->isVolatile(), 4549 ST->getAlignment()); 4550 } else if (TLI.isTypeLegal(MVT::i32)) { 4551 // Many FP stores are not made apparent until after legalize, e.g. for 4552 // argument passing. Since this is so common, custom legalize the 4553 // 64-bit integer store into two 32-bit stores. 4554 uint64_t Val = CFP->getValueAPF().convertToAPInt().getZExtValue(); 4555 SDOperand Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 4556 SDOperand Hi = DAG.getConstant(Val >> 32, MVT::i32); 4557 if (TLI.isBigEndian()) std::swap(Lo, Hi); 4558 4559 int SVOffset = ST->getSrcValueOffset(); 4560 unsigned Alignment = ST->getAlignment(); 4561 bool isVolatile = ST->isVolatile(); 4562 4563 SDOperand St0 = DAG.getStore(Chain, Lo, Ptr, ST->getSrcValue(), 4564 ST->getSrcValueOffset(), 4565 isVolatile, ST->getAlignment()); 4566 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 4567 DAG.getConstant(4, Ptr.getValueType())); 4568 SVOffset += 4; 4569 Alignment = MinAlign(Alignment, 4U); 4570 SDOperand St1 = DAG.getStore(Chain, Hi, Ptr, ST->getSrcValue(), 4571 SVOffset, isVolatile, Alignment); 4572 return DAG.getNode(ISD::TokenFactor, MVT::Other, St0, St1); 4573 } 4574 break; 4575 } 4576 } 4577 } 4578 4579 if (CombinerAA) { 4580 // Walk up chain skipping non-aliasing memory nodes. 4581 SDOperand BetterChain = FindBetterChain(N, Chain); 4582 4583 // If there is a better chain. 4584 if (Chain != BetterChain) { 4585 // Replace the chain to avoid dependency. 4586 SDOperand ReplStore; 4587 if (ST->isTruncatingStore()) { 4588 ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr, 4589 ST->getSrcValue(),ST->getSrcValueOffset(), 4590 ST->getMemoryVT(), 4591 ST->isVolatile(), ST->getAlignment()); 4592 } else { 4593 ReplStore = DAG.getStore(BetterChain, Value, Ptr, 4594 ST->getSrcValue(), ST->getSrcValueOffset(), 4595 ST->isVolatile(), ST->getAlignment()); 4596 } 4597 4598 // Create token to keep both nodes around. 4599 SDOperand Token = 4600 DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore); 4601 4602 // Don't add users to work list. 4603 return CombineTo(N, Token, false); 4604 } 4605 } 4606 4607 // Try transforming N to an indexed store. 4608 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4609 return SDOperand(N, 0); 4610 4611 // FIXME: is there such a thing as a truncating indexed store? 4612 if (ST->isTruncatingStore() && ST->isUnindexed() && 4613 Value.getValueType().isInteger()) { 4614 // See if we can simplify the input to this truncstore with knowledge that 4615 // only the low bits are being used. For example: 4616 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 4617 SDOperand Shorter = 4618 GetDemandedBits(Value, 4619 APInt::getLowBitsSet(Value.getValueSizeInBits(), 4620 ST->getMemoryVT().getSizeInBits())); 4621 AddToWorkList(Value.Val); 4622 if (Shorter.Val) 4623 return DAG.getTruncStore(Chain, Shorter, Ptr, ST->getSrcValue(), 4624 ST->getSrcValueOffset(), ST->getMemoryVT(), 4625 ST->isVolatile(), ST->getAlignment()); 4626 4627 // Otherwise, see if we can simplify the operation with 4628 // SimplifyDemandedBits, which only works if the value has a single use. 4629 if (SimplifyDemandedBits(Value, 4630 APInt::getLowBitsSet( 4631 Value.getValueSizeInBits(), 4632 ST->getMemoryVT().getSizeInBits()))) 4633 return SDOperand(N, 0); 4634 } 4635 4636 // If this is a load followed by a store to the same location, then the store 4637 // is dead/noop. 4638 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 4639 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 4640 ST->isUnindexed() && !ST->isVolatile() && 4641 // There can't be any side effects between the load and store, such as 4642 // a call or store. 4643 Chain.reachesChainWithoutSideEffects(SDOperand(Ld, 1))) { 4644 // The store is dead, remove it. 4645 return Chain; 4646 } 4647 } 4648 4649 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 4650 // truncating store. We can do this even if this is already a truncstore. 4651 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 4652 && TLI.isTypeLegal(Value.getOperand(0).getValueType()) && 4653 Value.Val->hasOneUse() && ST->isUnindexed() && 4654 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 4655 ST->getMemoryVT())) { 4656 return DAG.getTruncStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), 4657 ST->getSrcValueOffset(), ST->getMemoryVT(), 4658 ST->isVolatile(), ST->getAlignment()); 4659 } 4660 4661 return SDOperand(); 4662} 4663 4664SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 4665 SDOperand InVec = N->getOperand(0); 4666 SDOperand InVal = N->getOperand(1); 4667 SDOperand EltNo = N->getOperand(2); 4668 4669 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 4670 // vector with the inserted element. 4671 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 4672 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 4673 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end()); 4674 if (Elt < Ops.size()) 4675 Ops[Elt] = InVal; 4676 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(), 4677 &Ops[0], Ops.size()); 4678 } 4679 4680 return SDOperand(); 4681} 4682 4683SDOperand DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 4684 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 4685 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 4686 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 4687 4688 // Perform only after legalization to ensure build_vector / vector_shuffle 4689 // optimizations have already been done. 4690 if (!AfterLegalize) return SDOperand(); 4691 4692 SDOperand InVec = N->getOperand(0); 4693 SDOperand EltNo = N->getOperand(1); 4694 4695 if (isa<ConstantSDNode>(EltNo)) { 4696 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 4697 bool NewLoad = false; 4698 MVT VT = InVec.getValueType(); 4699 MVT EVT = VT.getVectorElementType(); 4700 MVT LVT = EVT; 4701 if (InVec.getOpcode() == ISD::BIT_CONVERT) { 4702 MVT BCVT = InVec.getOperand(0).getValueType(); 4703 if (!BCVT.isVector() || EVT.bitsGT(BCVT.getVectorElementType())) 4704 return SDOperand(); 4705 InVec = InVec.getOperand(0); 4706 EVT = BCVT.getVectorElementType(); 4707 NewLoad = true; 4708 } 4709 4710 LoadSDNode *LN0 = NULL; 4711 if (ISD::isNormalLoad(InVec.Val)) 4712 LN0 = cast<LoadSDNode>(InVec); 4713 else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 4714 InVec.getOperand(0).getValueType() == EVT && 4715 ISD::isNormalLoad(InVec.getOperand(0).Val)) { 4716 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 4717 } else if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE) { 4718 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 4719 // => 4720 // (load $addr+1*size) 4721 unsigned Idx = cast<ConstantSDNode>(InVec.getOperand(2). 4722 getOperand(Elt))->getValue(); 4723 unsigned NumElems = InVec.getOperand(2).getNumOperands(); 4724 InVec = (Idx < NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 4725 if (InVec.getOpcode() == ISD::BIT_CONVERT) 4726 InVec = InVec.getOperand(0); 4727 if (ISD::isNormalLoad(InVec.Val)) { 4728 LN0 = cast<LoadSDNode>(InVec); 4729 Elt = (Idx < NumElems) ? Idx : Idx - NumElems; 4730 } 4731 } 4732 if (!LN0 || !LN0->hasOneUse()) 4733 return SDOperand(); 4734 4735 unsigned Align = LN0->getAlignment(); 4736 if (NewLoad) { 4737 // Check the resultant load doesn't need a higher alignment than the 4738 // original load. 4739 unsigned NewAlign = TLI.getTargetMachine().getTargetData()-> 4740 getABITypeAlignment(LVT.getTypeForMVT()); 4741 if (!TLI.isOperationLegal(ISD::LOAD, LVT) || NewAlign > Align) 4742 return SDOperand(); 4743 Align = NewAlign; 4744 } 4745 4746 SDOperand NewPtr = LN0->getBasePtr(); 4747 if (Elt) { 4748 unsigned PtrOff = LVT.getSizeInBits() * Elt / 8; 4749 MVT PtrType = NewPtr.getValueType(); 4750 if (TLI.isBigEndian()) 4751 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 4752 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, 4753 DAG.getConstant(PtrOff, PtrType)); 4754 } 4755 return DAG.getLoad(LVT, LN0->getChain(), NewPtr, 4756 LN0->getSrcValue(), LN0->getSrcValueOffset(), 4757 LN0->isVolatile(), Align); 4758 } 4759 return SDOperand(); 4760} 4761 4762 4763SDOperand DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 4764 unsigned NumInScalars = N->getNumOperands(); 4765 MVT VT = N->getValueType(0); 4766 unsigned NumElts = VT.getVectorNumElements(); 4767 MVT EltType = VT.getVectorElementType(); 4768 4769 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 4770 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 4771 // at most two distinct vectors, turn this into a shuffle node. 4772 SDOperand VecIn1, VecIn2; 4773 for (unsigned i = 0; i != NumInScalars; ++i) { 4774 // Ignore undef inputs. 4775 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 4776 4777 // If this input is something other than a EXTRACT_VECTOR_ELT with a 4778 // constant index, bail out. 4779 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 4780 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 4781 VecIn1 = VecIn2 = SDOperand(0, 0); 4782 break; 4783 } 4784 4785 // If the input vector type disagrees with the result of the build_vector, 4786 // we can't make a shuffle. 4787 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0); 4788 if (ExtractedFromVec.getValueType() != VT) { 4789 VecIn1 = VecIn2 = SDOperand(0, 0); 4790 break; 4791 } 4792 4793 // Otherwise, remember this. We allow up to two distinct input vectors. 4794 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 4795 continue; 4796 4797 if (VecIn1.Val == 0) { 4798 VecIn1 = ExtractedFromVec; 4799 } else if (VecIn2.Val == 0) { 4800 VecIn2 = ExtractedFromVec; 4801 } else { 4802 // Too many inputs. 4803 VecIn1 = VecIn2 = SDOperand(0, 0); 4804 break; 4805 } 4806 } 4807 4808 // If everything is good, we can make a shuffle operation. 4809 if (VecIn1.Val) { 4810 SmallVector<SDOperand, 8> BuildVecIndices; 4811 for (unsigned i = 0; i != NumInScalars; ++i) { 4812 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 4813 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, TLI.getPointerTy())); 4814 continue; 4815 } 4816 4817 SDOperand Extract = N->getOperand(i); 4818 4819 // If extracting from the first vector, just use the index directly. 4820 if (Extract.getOperand(0) == VecIn1) { 4821 BuildVecIndices.push_back(Extract.getOperand(1)); 4822 continue; 4823 } 4824 4825 // Otherwise, use InIdx + VecSize 4826 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue(); 4827 BuildVecIndices.push_back(DAG.getIntPtrConstant(Idx+NumInScalars)); 4828 } 4829 4830 // Add count and size info. 4831 MVT BuildVecVT = MVT::getVectorVT(TLI.getPointerTy(), NumElts); 4832 4833 // Return the new VECTOR_SHUFFLE node. 4834 SDOperand Ops[5]; 4835 Ops[0] = VecIn1; 4836 if (VecIn2.Val) { 4837 Ops[1] = VecIn2; 4838 } else { 4839 // Use an undef build_vector as input for the second operand. 4840 std::vector<SDOperand> UnOps(NumInScalars, 4841 DAG.getNode(ISD::UNDEF, 4842 EltType)); 4843 Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, VT, 4844 &UnOps[0], UnOps.size()); 4845 AddToWorkList(Ops[1].Val); 4846 } 4847 Ops[2] = DAG.getNode(ISD::BUILD_VECTOR, BuildVecVT, 4848 &BuildVecIndices[0], BuildVecIndices.size()); 4849 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Ops, 3); 4850 } 4851 4852 return SDOperand(); 4853} 4854 4855SDOperand DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 4856 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 4857 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 4858 // inputs come from at most two distinct vectors, turn this into a shuffle 4859 // node. 4860 4861 // If we only have one input vector, we don't need to do any concatenation. 4862 if (N->getNumOperands() == 1) { 4863 return N->getOperand(0); 4864 } 4865 4866 return SDOperand(); 4867} 4868 4869SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 4870 SDOperand ShufMask = N->getOperand(2); 4871 unsigned NumElts = ShufMask.getNumOperands(); 4872 4873 // If the shuffle mask is an identity operation on the LHS, return the LHS. 4874 bool isIdentity = true; 4875 for (unsigned i = 0; i != NumElts; ++i) { 4876 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 4877 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) { 4878 isIdentity = false; 4879 break; 4880 } 4881 } 4882 if (isIdentity) return N->getOperand(0); 4883 4884 // If the shuffle mask is an identity operation on the RHS, return the RHS. 4885 isIdentity = true; 4886 for (unsigned i = 0; i != NumElts; ++i) { 4887 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 4888 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) { 4889 isIdentity = false; 4890 break; 4891 } 4892 } 4893 if (isIdentity) return N->getOperand(1); 4894 4895 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not 4896 // needed at all. 4897 bool isUnary = true; 4898 bool isSplat = true; 4899 int VecNum = -1; 4900 unsigned BaseIdx = 0; 4901 for (unsigned i = 0; i != NumElts; ++i) 4902 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) { 4903 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue(); 4904 int V = (Idx < NumElts) ? 0 : 1; 4905 if (VecNum == -1) { 4906 VecNum = V; 4907 BaseIdx = Idx; 4908 } else { 4909 if (BaseIdx != Idx) 4910 isSplat = false; 4911 if (VecNum != V) { 4912 isUnary = false; 4913 break; 4914 } 4915 } 4916 } 4917 4918 SDOperand N0 = N->getOperand(0); 4919 SDOperand N1 = N->getOperand(1); 4920 // Normalize unary shuffle so the RHS is undef. 4921 if (isUnary && VecNum == 1) 4922 std::swap(N0, N1); 4923 4924 // If it is a splat, check if the argument vector is a build_vector with 4925 // all scalar elements the same. 4926 if (isSplat) { 4927 SDNode *V = N0.Val; 4928 4929 // If this is a bit convert that changes the element type of the vector but 4930 // not the number of vector elements, look through it. Be careful not to 4931 // look though conversions that change things like v4f32 to v2f64. 4932 if (V->getOpcode() == ISD::BIT_CONVERT) { 4933 SDOperand ConvInput = V->getOperand(0); 4934 if (ConvInput.getValueType().getVectorNumElements() == NumElts) 4935 V = ConvInput.Val; 4936 } 4937 4938 if (V->getOpcode() == ISD::BUILD_VECTOR) { 4939 unsigned NumElems = V->getNumOperands(); 4940 if (NumElems > BaseIdx) { 4941 SDOperand Base; 4942 bool AllSame = true; 4943 for (unsigned i = 0; i != NumElems; ++i) { 4944 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 4945 Base = V->getOperand(i); 4946 break; 4947 } 4948 } 4949 // Splat of <u, u, u, u>, return <u, u, u, u> 4950 if (!Base.Val) 4951 return N0; 4952 for (unsigned i = 0; i != NumElems; ++i) { 4953 if (V->getOperand(i) != Base) { 4954 AllSame = false; 4955 break; 4956 } 4957 } 4958 // Splat of <x, x, x, x>, return <x, x, x, x> 4959 if (AllSame) 4960 return N0; 4961 } 4962 } 4963 } 4964 4965 // If it is a unary or the LHS and the RHS are the same node, turn the RHS 4966 // into an undef. 4967 if (isUnary || N0 == N1) { 4968 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the 4969 // first operand. 4970 SmallVector<SDOperand, 8> MappedOps; 4971 for (unsigned i = 0; i != NumElts; ++i) { 4972 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || 4973 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) { 4974 MappedOps.push_back(ShufMask.getOperand(i)); 4975 } else { 4976 unsigned NewIdx = 4977 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts; 4978 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32)); 4979 } 4980 } 4981 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(), 4982 &MappedOps[0], MappedOps.size()); 4983 AddToWorkList(ShufMask.Val); 4984 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0), 4985 N0, 4986 DAG.getNode(ISD::UNDEF, N->getValueType(0)), 4987 ShufMask); 4988 } 4989 4990 return SDOperand(); 4991} 4992 4993/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 4994/// an AND to a vector_shuffle with the destination vector and a zero vector. 4995/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 4996/// vector_shuffle V, Zero, <0, 4, 2, 4> 4997SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) { 4998 SDOperand LHS = N->getOperand(0); 4999 SDOperand RHS = N->getOperand(1); 5000 if (N->getOpcode() == ISD::AND) { 5001 if (RHS.getOpcode() == ISD::BIT_CONVERT) 5002 RHS = RHS.getOperand(0); 5003 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 5004 std::vector<SDOperand> IdxOps; 5005 unsigned NumOps = RHS.getNumOperands(); 5006 unsigned NumElts = NumOps; 5007 MVT EVT = RHS.getValueType().getVectorElementType(); 5008 for (unsigned i = 0; i != NumElts; ++i) { 5009 SDOperand Elt = RHS.getOperand(i); 5010 if (!isa<ConstantSDNode>(Elt)) 5011 return SDOperand(); 5012 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 5013 IdxOps.push_back(DAG.getConstant(i, EVT)); 5014 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 5015 IdxOps.push_back(DAG.getConstant(NumElts, EVT)); 5016 else 5017 return SDOperand(); 5018 } 5019 5020 // Let's see if the target supports this vector_shuffle. 5021 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG)) 5022 return SDOperand(); 5023 5024 // Return the new VECTOR_SHUFFLE node. 5025 MVT VT = MVT::getVectorVT(EVT, NumElts); 5026 std::vector<SDOperand> Ops; 5027 LHS = DAG.getNode(ISD::BIT_CONVERT, VT, LHS); 5028 Ops.push_back(LHS); 5029 AddToWorkList(LHS.Val); 5030 std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT)); 5031 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT, 5032 &ZeroOps[0], ZeroOps.size())); 5033 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT, 5034 &IdxOps[0], IdxOps.size())); 5035 SDOperand Result = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, 5036 &Ops[0], Ops.size()); 5037 if (VT != LHS.getValueType()) { 5038 Result = DAG.getNode(ISD::BIT_CONVERT, LHS.getValueType(), Result); 5039 } 5040 return Result; 5041 } 5042 } 5043 return SDOperand(); 5044} 5045 5046/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 5047SDOperand DAGCombiner::SimplifyVBinOp(SDNode *N) { 5048 // After legalize, the target may be depending on adds and other 5049 // binary ops to provide legal ways to construct constants or other 5050 // things. Simplifying them may result in a loss of legality. 5051 if (AfterLegalize) return SDOperand(); 5052 5053 MVT VT = N->getValueType(0); 5054 assert(VT.isVector() && "SimplifyVBinOp only works on vectors!"); 5055 5056 MVT EltType = VT.getVectorElementType(); 5057 SDOperand LHS = N->getOperand(0); 5058 SDOperand RHS = N->getOperand(1); 5059 SDOperand Shuffle = XformToShuffleWithZero(N); 5060 if (Shuffle.Val) return Shuffle; 5061 5062 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 5063 // this operation. 5064 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 5065 RHS.getOpcode() == ISD::BUILD_VECTOR) { 5066 SmallVector<SDOperand, 8> Ops; 5067 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 5068 SDOperand LHSOp = LHS.getOperand(i); 5069 SDOperand RHSOp = RHS.getOperand(i); 5070 // If these two elements can't be folded, bail out. 5071 if ((LHSOp.getOpcode() != ISD::UNDEF && 5072 LHSOp.getOpcode() != ISD::Constant && 5073 LHSOp.getOpcode() != ISD::ConstantFP) || 5074 (RHSOp.getOpcode() != ISD::UNDEF && 5075 RHSOp.getOpcode() != ISD::Constant && 5076 RHSOp.getOpcode() != ISD::ConstantFP)) 5077 break; 5078 // Can't fold divide by zero. 5079 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 5080 N->getOpcode() == ISD::FDIV) { 5081 if ((RHSOp.getOpcode() == ISD::Constant && 5082 cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) || 5083 (RHSOp.getOpcode() == ISD::ConstantFP && 5084 cast<ConstantFPSDNode>(RHSOp.Val)->getValueAPF().isZero())) 5085 break; 5086 } 5087 Ops.push_back(DAG.getNode(N->getOpcode(), EltType, LHSOp, RHSOp)); 5088 AddToWorkList(Ops.back().Val); 5089 assert((Ops.back().getOpcode() == ISD::UNDEF || 5090 Ops.back().getOpcode() == ISD::Constant || 5091 Ops.back().getOpcode() == ISD::ConstantFP) && 5092 "Scalar binop didn't fold!"); 5093 } 5094 5095 if (Ops.size() == LHS.getNumOperands()) { 5096 MVT VT = LHS.getValueType(); 5097 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 5098 } 5099 } 5100 5101 return SDOperand(); 5102} 5103 5104SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){ 5105 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 5106 5107 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2, 5108 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 5109 // If we got a simplified select_cc node back from SimplifySelectCC, then 5110 // break it down into a new SETCC node, and a new SELECT node, and then return 5111 // the SELECT node, since we were called with a SELECT node. 5112 if (SCC.Val) { 5113 // Check to see if we got a select_cc back (to turn into setcc/select). 5114 // Otherwise, just return whatever node we got back, like fabs. 5115 if (SCC.getOpcode() == ISD::SELECT_CC) { 5116 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(), 5117 SCC.getOperand(0), SCC.getOperand(1), 5118 SCC.getOperand(4)); 5119 AddToWorkList(SETCC.Val); 5120 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2), 5121 SCC.getOperand(3), SETCC); 5122 } 5123 return SCC; 5124 } 5125 return SDOperand(); 5126} 5127 5128/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 5129/// are the two values being selected between, see if we can simplify the 5130/// select. Callers of this should assume that TheSelect is deleted if this 5131/// returns true. As such, they should return the appropriate thing (e.g. the 5132/// node) back to the top-level of the DAG combiner loop to avoid it being 5133/// looked at. 5134/// 5135bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS, 5136 SDOperand RHS) { 5137 5138 // If this is a select from two identical things, try to pull the operation 5139 // through the select. 5140 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 5141 // If this is a load and the token chain is identical, replace the select 5142 // of two loads with a load through a select of the address to load from. 5143 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 5144 // constants have been dropped into the constant pool. 5145 if (LHS.getOpcode() == ISD::LOAD && 5146 // Token chains must be identical. 5147 LHS.getOperand(0) == RHS.getOperand(0)) { 5148 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 5149 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 5150 5151 // If this is an EXTLOAD, the VT's must match. 5152 if (LLD->getMemoryVT() == RLD->getMemoryVT()) { 5153 // FIXME: this conflates two src values, discarding one. This is not 5154 // the right thing to do, but nothing uses srcvalues now. When they do, 5155 // turn SrcValue into a list of locations. 5156 SDOperand Addr; 5157 if (TheSelect->getOpcode() == ISD::SELECT) { 5158 // Check that the condition doesn't reach either load. If so, folding 5159 // this will induce a cycle into the DAG. 5160 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).Val) && 5161 !RLD->isPredecessorOf(TheSelect->getOperand(0).Val)) { 5162 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(), 5163 TheSelect->getOperand(0), LLD->getBasePtr(), 5164 RLD->getBasePtr()); 5165 } 5166 } else { 5167 // Check that the condition doesn't reach either load. If so, folding 5168 // this will induce a cycle into the DAG. 5169 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).Val) && 5170 !RLD->isPredecessorOf(TheSelect->getOperand(0).Val) && 5171 !LLD->isPredecessorOf(TheSelect->getOperand(1).Val) && 5172 !RLD->isPredecessorOf(TheSelect->getOperand(1).Val)) { 5173 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(), 5174 TheSelect->getOperand(0), 5175 TheSelect->getOperand(1), 5176 LLD->getBasePtr(), RLD->getBasePtr(), 5177 TheSelect->getOperand(4)); 5178 } 5179 } 5180 5181 if (Addr.Val) { 5182 SDOperand Load; 5183 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) 5184 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(), 5185 Addr,LLD->getSrcValue(), 5186 LLD->getSrcValueOffset(), 5187 LLD->isVolatile(), 5188 LLD->getAlignment()); 5189 else { 5190 Load = DAG.getExtLoad(LLD->getExtensionType(), 5191 TheSelect->getValueType(0), 5192 LLD->getChain(), Addr, LLD->getSrcValue(), 5193 LLD->getSrcValueOffset(), 5194 LLD->getMemoryVT(), 5195 LLD->isVolatile(), 5196 LLD->getAlignment()); 5197 } 5198 // Users of the select now use the result of the load. 5199 CombineTo(TheSelect, Load); 5200 5201 // Users of the old loads now use the new load's chain. We know the 5202 // old-load value is dead now. 5203 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1)); 5204 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1)); 5205 return true; 5206 } 5207 } 5208 } 5209 } 5210 5211 return false; 5212} 5213 5214SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1, 5215 SDOperand N2, SDOperand N3, 5216 ISD::CondCode CC, bool NotExtCompare) { 5217 5218 MVT VT = N2.getValueType(); 5219 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 5220 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 5221 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 5222 5223 // Determine if the condition we're dealing with is constant 5224 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultType(N0), N0, N1, CC, false); 5225 if (SCC.Val) AddToWorkList(SCC.Val); 5226 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 5227 5228 // fold select_cc true, x, y -> x 5229 if (SCCC && !SCCC->isNullValue()) 5230 return N2; 5231 // fold select_cc false, x, y -> y 5232 if (SCCC && SCCC->isNullValue()) 5233 return N3; 5234 5235 // Check to see if we can simplify the select into an fabs node 5236 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 5237 // Allow either -0.0 or 0.0 5238 if (CFP->getValueAPF().isZero()) { 5239 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 5240 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 5241 N0 == N2 && N3.getOpcode() == ISD::FNEG && 5242 N2 == N3.getOperand(0)) 5243 return DAG.getNode(ISD::FABS, VT, N0); 5244 5245 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 5246 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 5247 N0 == N3 && N2.getOpcode() == ISD::FNEG && 5248 N2.getOperand(0) == N3) 5249 return DAG.getNode(ISD::FABS, VT, N3); 5250 } 5251 } 5252 5253 // Check to see if we can perform the "gzip trick", transforming 5254 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 5255 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 5256 N0.getValueType().isInteger() && 5257 N2.getValueType().isInteger() && 5258 (N1C->isNullValue() || // (a < 0) ? b : 0 5259 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 5260 MVT XType = N0.getValueType(); 5261 MVT AType = N2.getValueType(); 5262 if (XType.bitsGE(AType)) { 5263 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 5264 // single-bit constant. 5265 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 5266 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 5267 ShCtV = XType.getSizeInBits()-ShCtV-1; 5268 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy()); 5269 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt); 5270 AddToWorkList(Shift.Val); 5271 if (XType.bitsGT(AType)) { 5272 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 5273 AddToWorkList(Shift.Val); 5274 } 5275 return DAG.getNode(ISD::AND, AType, Shift, N2); 5276 } 5277 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 5278 DAG.getConstant(XType.getSizeInBits()-1, 5279 TLI.getShiftAmountTy())); 5280 AddToWorkList(Shift.Val); 5281 if (XType.bitsGT(AType)) { 5282 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 5283 AddToWorkList(Shift.Val); 5284 } 5285 return DAG.getNode(ISD::AND, AType, Shift, N2); 5286 } 5287 } 5288 5289 // fold select C, 16, 0 -> shl C, 4 5290 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 5291 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) { 5292 5293 // If the caller doesn't want us to simplify this into a zext of a compare, 5294 // don't do it. 5295 if (NotExtCompare && N2C->getAPIntValue() == 1) 5296 return SDOperand(); 5297 5298 // Get a SetCC of the condition 5299 // FIXME: Should probably make sure that setcc is legal if we ever have a 5300 // target where it isn't. 5301 SDOperand Temp, SCC; 5302 // cast from setcc result type to select result type 5303 if (AfterLegalize) { 5304 SCC = DAG.getSetCC(TLI.getSetCCResultType(N0), N0, N1, CC); 5305 if (N2.getValueType().bitsLT(SCC.getValueType())) 5306 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType()); 5307 else 5308 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 5309 } else { 5310 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC); 5311 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 5312 } 5313 AddToWorkList(SCC.Val); 5314 AddToWorkList(Temp.Val); 5315 5316 if (N2C->getAPIntValue() == 1) 5317 return Temp; 5318 // shl setcc result by log2 n2c 5319 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp, 5320 DAG.getConstant(N2C->getAPIntValue().logBase2(), 5321 TLI.getShiftAmountTy())); 5322 } 5323 5324 // Check to see if this is the equivalent of setcc 5325 // FIXME: Turn all of these into setcc if setcc if setcc is legal 5326 // otherwise, go ahead with the folds. 5327 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 5328 MVT XType = N0.getValueType(); 5329 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(N0))) { 5330 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultType(N0), N0, N1, CC); 5331 if (Res.getValueType() != VT) 5332 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res); 5333 return Res; 5334 } 5335 5336 // seteq X, 0 -> srl (ctlz X, log2(size(X))) 5337 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 5338 TLI.isOperationLegal(ISD::CTLZ, XType)) { 5339 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0); 5340 return DAG.getNode(ISD::SRL, XType, Ctlz, 5341 DAG.getConstant(Log2_32(XType.getSizeInBits()), 5342 TLI.getShiftAmountTy())); 5343 } 5344 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) 5345 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 5346 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType), 5347 N0); 5348 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0, 5349 DAG.getConstant(~0ULL, XType)); 5350 return DAG.getNode(ISD::SRL, XType, 5351 DAG.getNode(ISD::AND, XType, NegN0, NotN0), 5352 DAG.getConstant(XType.getSizeInBits()-1, 5353 TLI.getShiftAmountTy())); 5354 } 5355 // setgt X, -1 -> xor (srl (X, size(X)-1), 1) 5356 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 5357 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0, 5358 DAG.getConstant(XType.getSizeInBits()-1, 5359 TLI.getShiftAmountTy())); 5360 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType)); 5361 } 5362 } 5363 5364 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 5365 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5366 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 5367 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) && 5368 N2.getOperand(0) == N1 && N0.getValueType().isInteger()) { 5369 MVT XType = N0.getValueType(); 5370 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 5371 DAG.getConstant(XType.getSizeInBits()-1, 5372 TLI.getShiftAmountTy())); 5373 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 5374 AddToWorkList(Shift.Val); 5375 AddToWorkList(Add.Val); 5376 return DAG.getNode(ISD::XOR, XType, Add, Shift); 5377 } 5378 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X -> 5379 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5380 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT && 5381 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) { 5382 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 5383 MVT XType = N0.getValueType(); 5384 if (SubC->isNullValue() && XType.isInteger()) { 5385 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 5386 DAG.getConstant(XType.getSizeInBits()-1, 5387 TLI.getShiftAmountTy())); 5388 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 5389 AddToWorkList(Shift.Val); 5390 AddToWorkList(Add.Val); 5391 return DAG.getNode(ISD::XOR, XType, Add, Shift); 5392 } 5393 } 5394 } 5395 5396 return SDOperand(); 5397} 5398 5399/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 5400SDOperand DAGCombiner::SimplifySetCC(MVT VT, SDOperand N0, 5401 SDOperand N1, ISD::CondCode Cond, 5402 bool foldBooleans) { 5403 TargetLowering::DAGCombinerInfo 5404 DagCombineInfo(DAG, !AfterLegalize, false, this); 5405 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo); 5406} 5407 5408/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 5409/// return a DAG expression to select that will generate the same value by 5410/// multiplying by a magic number. See: 5411/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 5412SDOperand DAGCombiner::BuildSDIV(SDNode *N) { 5413 std::vector<SDNode*> Built; 5414 SDOperand S = TLI.BuildSDIV(N, DAG, &Built); 5415 5416 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 5417 ii != ee; ++ii) 5418 AddToWorkList(*ii); 5419 return S; 5420} 5421 5422/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 5423/// return a DAG expression to select that will generate the same value by 5424/// multiplying by a magic number. See: 5425/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 5426SDOperand DAGCombiner::BuildUDIV(SDNode *N) { 5427 std::vector<SDNode*> Built; 5428 SDOperand S = TLI.BuildUDIV(N, DAG, &Built); 5429 5430 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 5431 ii != ee; ++ii) 5432 AddToWorkList(*ii); 5433 return S; 5434} 5435 5436/// FindBaseOffset - Return true if base is known not to alias with anything 5437/// but itself. Provides base object and offset as results. 5438static bool FindBaseOffset(SDOperand Ptr, SDOperand &Base, int64_t &Offset) { 5439 // Assume it is a primitive operation. 5440 Base = Ptr; Offset = 0; 5441 5442 // If it's an adding a simple constant then integrate the offset. 5443 if (Base.getOpcode() == ISD::ADD) { 5444 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 5445 Base = Base.getOperand(0); 5446 Offset += C->getValue(); 5447 } 5448 } 5449 5450 // If it's any of the following then it can't alias with anything but itself. 5451 return isa<FrameIndexSDNode>(Base) || 5452 isa<ConstantPoolSDNode>(Base) || 5453 isa<GlobalAddressSDNode>(Base); 5454} 5455 5456/// isAlias - Return true if there is any possibility that the two addresses 5457/// overlap. 5458bool DAGCombiner::isAlias(SDOperand Ptr1, int64_t Size1, 5459 const Value *SrcValue1, int SrcValueOffset1, 5460 SDOperand Ptr2, int64_t Size2, 5461 const Value *SrcValue2, int SrcValueOffset2) 5462{ 5463 // If they are the same then they must be aliases. 5464 if (Ptr1 == Ptr2) return true; 5465 5466 // Gather base node and offset information. 5467 SDOperand Base1, Base2; 5468 int64_t Offset1, Offset2; 5469 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1); 5470 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2); 5471 5472 // If they have a same base address then... 5473 if (Base1 == Base2) { 5474 // Check to see if the addresses overlap. 5475 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 5476 } 5477 5478 // If we know both bases then they can't alias. 5479 if (KnownBase1 && KnownBase2) return false; 5480 5481 if (CombinerGlobalAA) { 5482 // Use alias analysis information. 5483 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 5484 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 5485 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 5486 AliasAnalysis::AliasResult AAResult = 5487 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2); 5488 if (AAResult == AliasAnalysis::NoAlias) 5489 return false; 5490 } 5491 5492 // Otherwise we have to assume they alias. 5493 return true; 5494} 5495 5496/// FindAliasInfo - Extracts the relevant alias information from the memory 5497/// node. Returns true if the operand was a load. 5498bool DAGCombiner::FindAliasInfo(SDNode *N, 5499 SDOperand &Ptr, int64_t &Size, 5500 const Value *&SrcValue, int &SrcValueOffset) { 5501 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 5502 Ptr = LD->getBasePtr(); 5503 Size = LD->getMemoryVT().getSizeInBits() >> 3; 5504 SrcValue = LD->getSrcValue(); 5505 SrcValueOffset = LD->getSrcValueOffset(); 5506 return true; 5507 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 5508 Ptr = ST->getBasePtr(); 5509 Size = ST->getMemoryVT().getSizeInBits() >> 3; 5510 SrcValue = ST->getSrcValue(); 5511 SrcValueOffset = ST->getSrcValueOffset(); 5512 } else { 5513 assert(0 && "FindAliasInfo expected a memory operand"); 5514 } 5515 5516 return false; 5517} 5518 5519/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 5520/// looking for aliasing nodes and adding them to the Aliases vector. 5521void DAGCombiner::GatherAllAliases(SDNode *N, SDOperand OriginalChain, 5522 SmallVector<SDOperand, 8> &Aliases) { 5523 SmallVector<SDOperand, 8> Chains; // List of chains to visit. 5524 std::set<SDNode *> Visited; // Visited node set. 5525 5526 // Get alias information for node. 5527 SDOperand Ptr; 5528 int64_t Size; 5529 const Value *SrcValue; 5530 int SrcValueOffset; 5531 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset); 5532 5533 // Starting off. 5534 Chains.push_back(OriginalChain); 5535 5536 // Look at each chain and determine if it is an alias. If so, add it to the 5537 // aliases list. If not, then continue up the chain looking for the next 5538 // candidate. 5539 while (!Chains.empty()) { 5540 SDOperand Chain = Chains.back(); 5541 Chains.pop_back(); 5542 5543 // Don't bother if we've been before. 5544 if (Visited.find(Chain.Val) != Visited.end()) continue; 5545 Visited.insert(Chain.Val); 5546 5547 switch (Chain.getOpcode()) { 5548 case ISD::EntryToken: 5549 // Entry token is ideal chain operand, but handled in FindBetterChain. 5550 break; 5551 5552 case ISD::LOAD: 5553 case ISD::STORE: { 5554 // Get alias information for Chain. 5555 SDOperand OpPtr; 5556 int64_t OpSize; 5557 const Value *OpSrcValue; 5558 int OpSrcValueOffset; 5559 bool IsOpLoad = FindAliasInfo(Chain.Val, OpPtr, OpSize, 5560 OpSrcValue, OpSrcValueOffset); 5561 5562 // If chain is alias then stop here. 5563 if (!(IsLoad && IsOpLoad) && 5564 isAlias(Ptr, Size, SrcValue, SrcValueOffset, 5565 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) { 5566 Aliases.push_back(Chain); 5567 } else { 5568 // Look further up the chain. 5569 Chains.push_back(Chain.getOperand(0)); 5570 // Clean up old chain. 5571 AddToWorkList(Chain.Val); 5572 } 5573 break; 5574 } 5575 5576 case ISD::TokenFactor: 5577 // We have to check each of the operands of the token factor, so we queue 5578 // then up. Adding the operands to the queue (stack) in reverse order 5579 // maintains the original order and increases the likelihood that getNode 5580 // will find a matching token factor (CSE.) 5581 for (unsigned n = Chain.getNumOperands(); n;) 5582 Chains.push_back(Chain.getOperand(--n)); 5583 // Eliminate the token factor if we can. 5584 AddToWorkList(Chain.Val); 5585 break; 5586 5587 default: 5588 // For all other instructions we will just have to take what we can get. 5589 Aliases.push_back(Chain); 5590 break; 5591 } 5592 } 5593} 5594 5595/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 5596/// for a better chain (aliasing node.) 5597SDOperand DAGCombiner::FindBetterChain(SDNode *N, SDOperand OldChain) { 5598 SmallVector<SDOperand, 8> Aliases; // Ops for replacing token factor. 5599 5600 // Accumulate all the aliases to this node. 5601 GatherAllAliases(N, OldChain, Aliases); 5602 5603 if (Aliases.size() == 0) { 5604 // If no operands then chain to entry token. 5605 return DAG.getEntryNode(); 5606 } else if (Aliases.size() == 1) { 5607 // If a single operand then chain to it. We don't need to revisit it. 5608 return Aliases[0]; 5609 } 5610 5611 // Construct a custom tailored token factor. 5612 SDOperand NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 5613 &Aliases[0], Aliases.size()); 5614 5615 // Make sure the old chain gets cleaned up. 5616 if (NewChain != OldChain) AddToWorkList(OldChain.Val); 5617 5618 return NewChain; 5619} 5620 5621// SelectionDAG::Combine - This is the entry point for the file. 5622// 5623void SelectionDAG::Combine(bool RunningAfterLegalize, AliasAnalysis &AA) { 5624 if (!RunningAfterLegalize && ViewDAGCombine1) 5625 viewGraph(); 5626 if (RunningAfterLegalize && ViewDAGCombine2) 5627 viewGraph(); 5628 /// run - This is the main entry point to this class. 5629 /// 5630 DAGCombiner(*this, AA).Run(RunningAfterLegalize); 5631} 5632