DAGCombiner.cpp revision fd58cd75630b1a2ace727d6caaee8c9308ba0240
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// This pass is not a substitute for the LLVM IR instcombine pass. This pass is 14// primarily intended to handle simplification opportunities that are implicit 15// in the LLVM IR and exposed by the various codegen lowering phases. 16// 17//===----------------------------------------------------------------------===// 18 19#define DEBUG_TYPE "dagcombine" 20#include "llvm/CodeGen/SelectionDAG.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/LLVMContext.h" 23#include "llvm/CodeGen/MachineFunction.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/PseudoSourceValue.h" 26#include "llvm/Analysis/AliasAnalysis.h" 27#include "llvm/Target/TargetData.h" 28#include "llvm/Target/TargetLowering.h" 29#include "llvm/Target/TargetMachine.h" 30#include "llvm/Target/TargetOptions.h" 31#include "llvm/ADT/SmallPtrSet.h" 32#include "llvm/ADT/Statistic.h" 33#include "llvm/Support/CommandLine.h" 34#include "llvm/Support/Debug.h" 35#include "llvm/Support/ErrorHandling.h" 36#include "llvm/Support/MathExtras.h" 37#include "llvm/Support/raw_ostream.h" 38#include <algorithm> 39using namespace llvm; 40 41STATISTIC(NodesCombined , "Number of dag nodes combined"); 42STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 43STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 44STATISTIC(OpsNarrowed , "Number of load/op/store narrowed"); 45STATISTIC(LdStFP2Int , "Number of fp load/store pairs transformed to int"); 46 47namespace { 48 static cl::opt<bool> 49 CombinerAA("combiner-alias-analysis", cl::Hidden, 50 cl::desc("Turn on alias analysis during testing")); 51 52 static cl::opt<bool> 53 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 54 cl::desc("Include global information in alias analysis")); 55 56//------------------------------ DAGCombiner ---------------------------------// 57 58 class DAGCombiner { 59 SelectionDAG &DAG; 60 const TargetLowering &TLI; 61 CombineLevel Level; 62 CodeGenOpt::Level OptLevel; 63 bool LegalOperations; 64 bool LegalTypes; 65 66 // Worklist of all of the nodes that need to be simplified. 67 std::vector<SDNode*> WorkList; 68 69 // AA - Used for DAG load/store alias analysis. 70 AliasAnalysis &AA; 71 72 /// AddUsersToWorkList - When an instruction is simplified, add all users of 73 /// the instruction to the work lists because they might get more simplified 74 /// now. 75 /// 76 void AddUsersToWorkList(SDNode *N) { 77 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 78 UI != UE; ++UI) 79 AddToWorkList(*UI); 80 } 81 82 /// visit - call the node-specific routine that knows how to fold each 83 /// particular type of node. 84 SDValue visit(SDNode *N); 85 86 public: 87 /// AddToWorkList - Add to the work list making sure it's instance is at the 88 /// the back (next to be processed.) 89 void AddToWorkList(SDNode *N) { 90 removeFromWorkList(N); 91 WorkList.push_back(N); 92 } 93 94 /// removeFromWorkList - remove all instances of N from the worklist. 95 /// 96 void removeFromWorkList(SDNode *N) { 97 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 98 WorkList.end()); 99 } 100 101 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 102 bool AddTo = true); 103 104 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 105 return CombineTo(N, &Res, 1, AddTo); 106 } 107 108 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 109 bool AddTo = true) { 110 SDValue To[] = { Res0, Res1 }; 111 return CombineTo(N, To, 2, AddTo); 112 } 113 114 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO); 115 116 private: 117 118 /// SimplifyDemandedBits - Check the specified integer node value to see if 119 /// it can be simplified or if things it uses can be simplified by bit 120 /// propagation. If so, return true. 121 bool SimplifyDemandedBits(SDValue Op) { 122 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits(); 123 APInt Demanded = APInt::getAllOnesValue(BitWidth); 124 return SimplifyDemandedBits(Op, Demanded); 125 } 126 127 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 128 129 bool CombineToPreIndexedLoadStore(SDNode *N); 130 bool CombineToPostIndexedLoadStore(SDNode *N); 131 132 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad); 133 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace); 134 SDValue SExtPromoteOperand(SDValue Op, EVT PVT); 135 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT); 136 SDValue PromoteIntBinOp(SDValue Op); 137 SDValue PromoteIntShiftOp(SDValue Op); 138 SDValue PromoteExtend(SDValue Op); 139 bool PromoteLoad(SDValue Op); 140 141 void ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs, 142 SDValue Trunc, SDValue ExtLoad, DebugLoc DL, 143 ISD::NodeType ExtType); 144 145 /// combine - call the node-specific routine that knows how to fold each 146 /// particular type of node. If that doesn't do anything, try the 147 /// target-specific DAG combines. 148 SDValue combine(SDNode *N); 149 150 // Visitation implementation - Implement dag node combining for different 151 // node types. The semantics are as follows: 152 // Return Value: 153 // SDValue.getNode() == 0 - No change was made 154 // SDValue.getNode() == N - N was replaced, is dead and has been handled. 155 // otherwise - N should be replaced by the returned Operand. 156 // 157 SDValue visitTokenFactor(SDNode *N); 158 SDValue visitMERGE_VALUES(SDNode *N); 159 SDValue visitADD(SDNode *N); 160 SDValue visitSUB(SDNode *N); 161 SDValue visitADDC(SDNode *N); 162 SDValue visitADDE(SDNode *N); 163 SDValue visitMUL(SDNode *N); 164 SDValue visitSDIV(SDNode *N); 165 SDValue visitUDIV(SDNode *N); 166 SDValue visitSREM(SDNode *N); 167 SDValue visitUREM(SDNode *N); 168 SDValue visitMULHU(SDNode *N); 169 SDValue visitMULHS(SDNode *N); 170 SDValue visitSMUL_LOHI(SDNode *N); 171 SDValue visitUMUL_LOHI(SDNode *N); 172 SDValue visitSMULO(SDNode *N); 173 SDValue visitUMULO(SDNode *N); 174 SDValue visitSDIVREM(SDNode *N); 175 SDValue visitUDIVREM(SDNode *N); 176 SDValue visitAND(SDNode *N); 177 SDValue visitOR(SDNode *N); 178 SDValue visitXOR(SDNode *N); 179 SDValue SimplifyVBinOp(SDNode *N); 180 SDValue visitSHL(SDNode *N); 181 SDValue visitSRA(SDNode *N); 182 SDValue visitSRL(SDNode *N); 183 SDValue visitCTLZ(SDNode *N); 184 SDValue visitCTTZ(SDNode *N); 185 SDValue visitCTPOP(SDNode *N); 186 SDValue visitSELECT(SDNode *N); 187 SDValue visitSELECT_CC(SDNode *N); 188 SDValue visitSETCC(SDNode *N); 189 SDValue visitSIGN_EXTEND(SDNode *N); 190 SDValue visitZERO_EXTEND(SDNode *N); 191 SDValue visitANY_EXTEND(SDNode *N); 192 SDValue visitSIGN_EXTEND_INREG(SDNode *N); 193 SDValue visitTRUNCATE(SDNode *N); 194 SDValue visitBITCAST(SDNode *N); 195 SDValue visitBUILD_PAIR(SDNode *N); 196 SDValue visitFADD(SDNode *N); 197 SDValue visitFSUB(SDNode *N); 198 SDValue visitFMUL(SDNode *N); 199 SDValue visitFDIV(SDNode *N); 200 SDValue visitFREM(SDNode *N); 201 SDValue visitFCOPYSIGN(SDNode *N); 202 SDValue visitSINT_TO_FP(SDNode *N); 203 SDValue visitUINT_TO_FP(SDNode *N); 204 SDValue visitFP_TO_SINT(SDNode *N); 205 SDValue visitFP_TO_UINT(SDNode *N); 206 SDValue visitFP_ROUND(SDNode *N); 207 SDValue visitFP_ROUND_INREG(SDNode *N); 208 SDValue visitFP_EXTEND(SDNode *N); 209 SDValue visitFNEG(SDNode *N); 210 SDValue visitFABS(SDNode *N); 211 SDValue visitBRCOND(SDNode *N); 212 SDValue visitBR_CC(SDNode *N); 213 SDValue visitLOAD(SDNode *N); 214 SDValue visitSTORE(SDNode *N); 215 SDValue visitINSERT_VECTOR_ELT(SDNode *N); 216 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 217 SDValue visitBUILD_VECTOR(SDNode *N); 218 SDValue visitCONCAT_VECTORS(SDNode *N); 219 SDValue visitEXTRACT_SUBVECTOR(SDNode *N); 220 SDValue visitVECTOR_SHUFFLE(SDNode *N); 221 SDValue visitMEMBARRIER(SDNode *N); 222 223 SDValue XformToShuffleWithZero(SDNode *N); 224 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS); 225 226 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 227 228 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 229 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 230 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2); 231 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2, 232 SDValue N3, ISD::CondCode CC, 233 bool NotExtCompare = false); 234 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 235 DebugLoc DL, bool foldBooleans = true); 236 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 237 unsigned HiOp); 238 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT); 239 SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT); 240 SDValue BuildSDIV(SDNode *N); 241 SDValue BuildUDIV(SDNode *N); 242 SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1, 243 bool DemandHighBits = true); 244 SDValue MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1); 245 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL); 246 SDValue ReduceLoadWidth(SDNode *N); 247 SDValue ReduceLoadOpStoreWidth(SDNode *N); 248 SDValue TransformFPLoadStorePair(SDNode *N); 249 250 SDValue GetDemandedBits(SDValue V, const APInt &Mask); 251 252 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 253 /// looking for aliasing nodes and adding them to the Aliases vector. 254 void GatherAllAliases(SDNode *N, SDValue OriginalChain, 255 SmallVector<SDValue, 8> &Aliases); 256 257 /// isAlias - Return true if there is any possibility that the two addresses 258 /// overlap. 259 bool isAlias(SDValue Ptr1, int64_t Size1, 260 const Value *SrcValue1, int SrcValueOffset1, 261 unsigned SrcValueAlign1, 262 const MDNode *TBAAInfo1, 263 SDValue Ptr2, int64_t Size2, 264 const Value *SrcValue2, int SrcValueOffset2, 265 unsigned SrcValueAlign2, 266 const MDNode *TBAAInfo2) const; 267 268 /// FindAliasInfo - Extracts the relevant alias information from the memory 269 /// node. Returns true if the operand was a load. 270 bool FindAliasInfo(SDNode *N, 271 SDValue &Ptr, int64_t &Size, 272 const Value *&SrcValue, int &SrcValueOffset, 273 unsigned &SrcValueAlignment, 274 const MDNode *&TBAAInfo) const; 275 276 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 277 /// looking for a better chain (aliasing node.) 278 SDValue FindBetterChain(SDNode *N, SDValue Chain); 279 280 public: 281 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL) 282 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(Unrestricted), 283 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {} 284 285 /// Run - runs the dag combiner on all nodes in the work list 286 void Run(CombineLevel AtLevel); 287 288 SelectionDAG &getDAG() const { return DAG; } 289 290 /// getShiftAmountTy - Returns a type large enough to hold any valid 291 /// shift amount - before type legalization these can be huge. 292 EVT getShiftAmountTy(EVT LHSTy) { 293 return LegalTypes ? TLI.getShiftAmountTy(LHSTy) : TLI.getPointerTy(); 294 } 295 296 /// isTypeLegal - This method returns true if we are running before type 297 /// legalization or if the specified VT is legal. 298 bool isTypeLegal(const EVT &VT) { 299 if (!LegalTypes) return true; 300 return TLI.isTypeLegal(VT); 301 } 302 }; 303} 304 305 306namespace { 307/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 308/// nodes from the worklist. 309class WorkListRemover : public SelectionDAG::DAGUpdateListener { 310 DAGCombiner &DC; 311public: 312 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {} 313 314 virtual void NodeDeleted(SDNode *N, SDNode *E) { 315 DC.removeFromWorkList(N); 316 } 317 318 virtual void NodeUpdated(SDNode *N) { 319 // Ignore updates. 320 } 321}; 322} 323 324//===----------------------------------------------------------------------===// 325// TargetLowering::DAGCombinerInfo implementation 326//===----------------------------------------------------------------------===// 327 328void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 329 ((DAGCombiner*)DC)->AddToWorkList(N); 330} 331 332void TargetLowering::DAGCombinerInfo::RemoveFromWorklist(SDNode *N) { 333 ((DAGCombiner*)DC)->removeFromWorkList(N); 334} 335 336SDValue TargetLowering::DAGCombinerInfo:: 337CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) { 338 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo); 339} 340 341SDValue TargetLowering::DAGCombinerInfo:: 342CombineTo(SDNode *N, SDValue Res, bool AddTo) { 343 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo); 344} 345 346 347SDValue TargetLowering::DAGCombinerInfo:: 348CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) { 349 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo); 350} 351 352void TargetLowering::DAGCombinerInfo:: 353CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 354 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO); 355} 356 357//===----------------------------------------------------------------------===// 358// Helper Functions 359//===----------------------------------------------------------------------===// 360 361/// isNegatibleForFree - Return 1 if we can compute the negated form of the 362/// specified expression for the same cost as the expression itself, or 2 if we 363/// can compute the negated form more cheaply than the expression itself. 364static char isNegatibleForFree(SDValue Op, bool LegalOperations, 365 unsigned Depth = 0) { 366 // No compile time optimizations on this type. 367 if (Op.getValueType() == MVT::ppcf128) 368 return 0; 369 370 // fneg is removable even if it has multiple uses. 371 if (Op.getOpcode() == ISD::FNEG) return 2; 372 373 // Don't allow anything with multiple uses. 374 if (!Op.hasOneUse()) return 0; 375 376 // Don't recurse exponentially. 377 if (Depth > 6) return 0; 378 379 switch (Op.getOpcode()) { 380 default: return false; 381 case ISD::ConstantFP: 382 // Don't invert constant FP values after legalize. The negated constant 383 // isn't necessarily legal. 384 return LegalOperations ? 0 : 1; 385 case ISD::FADD: 386 // FIXME: determine better conditions for this xform. 387 if (!UnsafeFPMath) return 0; 388 389 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B) 390 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 391 return V; 392 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 393 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 394 case ISD::FSUB: 395 // We can't turn -(A-B) into B-A when we honor signed zeros. 396 if (!UnsafeFPMath) return 0; 397 398 // fold (fneg (fsub A, B)) -> (fsub B, A) 399 return 1; 400 401 case ISD::FMUL: 402 case ISD::FDIV: 403 if (HonorSignDependentRoundingFPMath()) return 0; 404 405 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y)) 406 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 407 return V; 408 409 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 410 411 case ISD::FP_EXTEND: 412 case ISD::FP_ROUND: 413 case ISD::FSIN: 414 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1); 415 } 416} 417 418/// GetNegatedExpression - If isNegatibleForFree returns true, this function 419/// returns the newly negated expression. 420static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 421 bool LegalOperations, unsigned Depth = 0) { 422 // fneg is removable even if it has multiple uses. 423 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 424 425 // Don't allow anything with multiple uses. 426 assert(Op.hasOneUse() && "Unknown reuse!"); 427 428 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 429 switch (Op.getOpcode()) { 430 default: llvm_unreachable("Unknown code"); 431 case ISD::ConstantFP: { 432 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 433 V.changeSign(); 434 return DAG.getConstantFP(V, Op.getValueType()); 435 } 436 case ISD::FADD: 437 // FIXME: determine better conditions for this xform. 438 assert(UnsafeFPMath); 439 440 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 441 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 442 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 443 GetNegatedExpression(Op.getOperand(0), DAG, 444 LegalOperations, Depth+1), 445 Op.getOperand(1)); 446 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 447 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 448 GetNegatedExpression(Op.getOperand(1), DAG, 449 LegalOperations, Depth+1), 450 Op.getOperand(0)); 451 case ISD::FSUB: 452 // We can't turn -(A-B) into B-A when we honor signed zeros. 453 assert(UnsafeFPMath); 454 455 // fold (fneg (fsub 0, B)) -> B 456 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 457 if (N0CFP->getValueAPF().isZero()) 458 return Op.getOperand(1); 459 460 // fold (fneg (fsub A, B)) -> (fsub B, A) 461 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 462 Op.getOperand(1), Op.getOperand(0)); 463 464 case ISD::FMUL: 465 case ISD::FDIV: 466 assert(!HonorSignDependentRoundingFPMath()); 467 468 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) 469 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 470 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 471 GetNegatedExpression(Op.getOperand(0), DAG, 472 LegalOperations, Depth+1), 473 Op.getOperand(1)); 474 475 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y)) 476 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 477 Op.getOperand(0), 478 GetNegatedExpression(Op.getOperand(1), DAG, 479 LegalOperations, Depth+1)); 480 481 case ISD::FP_EXTEND: 482 case ISD::FSIN: 483 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 484 GetNegatedExpression(Op.getOperand(0), DAG, 485 LegalOperations, Depth+1)); 486 case ISD::FP_ROUND: 487 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(), 488 GetNegatedExpression(Op.getOperand(0), DAG, 489 LegalOperations, Depth+1), 490 Op.getOperand(1)); 491 } 492} 493 494 495// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 496// that selects between the values 1 and 0, making it equivalent to a setcc. 497// Also, set the incoming LHS, RHS, and CC references to the appropriate 498// nodes based on the type of node we are checking. This simplifies life a 499// bit for the callers. 500static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 501 SDValue &CC) { 502 if (N.getOpcode() == ISD::SETCC) { 503 LHS = N.getOperand(0); 504 RHS = N.getOperand(1); 505 CC = N.getOperand(2); 506 return true; 507 } 508 if (N.getOpcode() == ISD::SELECT_CC && 509 N.getOperand(2).getOpcode() == ISD::Constant && 510 N.getOperand(3).getOpcode() == ISD::Constant && 511 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 512 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 513 LHS = N.getOperand(0); 514 RHS = N.getOperand(1); 515 CC = N.getOperand(4); 516 return true; 517 } 518 return false; 519} 520 521// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 522// one use. If this is true, it allows the users to invert the operation for 523// free when it is profitable to do so. 524static bool isOneUseSetCC(SDValue N) { 525 SDValue N0, N1, N2; 526 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 527 return true; 528 return false; 529} 530 531SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL, 532 SDValue N0, SDValue N1) { 533 EVT VT = N0.getValueType(); 534 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 535 if (isa<ConstantSDNode>(N1)) { 536 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 537 SDValue OpNode = 538 DAG.FoldConstantArithmetic(Opc, VT, 539 cast<ConstantSDNode>(N0.getOperand(1)), 540 cast<ConstantSDNode>(N1)); 541 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode); 542 } 543 if (N0.hasOneUse()) { 544 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 545 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 546 N0.getOperand(0), N1); 547 AddToWorkList(OpNode.getNode()); 548 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1)); 549 } 550 } 551 552 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 553 if (isa<ConstantSDNode>(N0)) { 554 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 555 SDValue OpNode = 556 DAG.FoldConstantArithmetic(Opc, VT, 557 cast<ConstantSDNode>(N1.getOperand(1)), 558 cast<ConstantSDNode>(N0)); 559 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode); 560 } 561 if (N1.hasOneUse()) { 562 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 563 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 564 N1.getOperand(0), N0); 565 AddToWorkList(OpNode.getNode()); 566 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1)); 567 } 568 } 569 570 return SDValue(); 571} 572 573SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 574 bool AddTo) { 575 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 576 ++NodesCombined; 577 DEBUG(dbgs() << "\nReplacing.1 "; 578 N->dump(&DAG); 579 dbgs() << "\nWith: "; 580 To[0].getNode()->dump(&DAG); 581 dbgs() << " and " << NumTo-1 << " other values\n"; 582 for (unsigned i = 0, e = NumTo; i != e; ++i) 583 assert((!To[i].getNode() || 584 N->getValueType(i) == To[i].getValueType()) && 585 "Cannot combine value to value of different type!")); 586 WorkListRemover DeadNodes(*this); 587 DAG.ReplaceAllUsesWith(N, To, &DeadNodes); 588 589 if (AddTo) { 590 // Push the new nodes and any users onto the worklist 591 for (unsigned i = 0, e = NumTo; i != e; ++i) { 592 if (To[i].getNode()) { 593 AddToWorkList(To[i].getNode()); 594 AddUsersToWorkList(To[i].getNode()); 595 } 596 } 597 } 598 599 // Finally, if the node is now dead, remove it from the graph. The node 600 // may not be dead if the replacement process recursively simplified to 601 // something else needing this node. 602 if (N->use_empty()) { 603 // Nodes can be reintroduced into the worklist. Make sure we do not 604 // process a node that has been replaced. 605 removeFromWorkList(N); 606 607 // Finally, since the node is now dead, remove it from the graph. 608 DAG.DeleteNode(N); 609 } 610 return SDValue(N, 0); 611} 612 613void DAGCombiner:: 614CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 615 // Replace all uses. If any nodes become isomorphic to other nodes and 616 // are deleted, make sure to remove them from our worklist. 617 WorkListRemover DeadNodes(*this); 618 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 619 620 // Push the new node and any (possibly new) users onto the worklist. 621 AddToWorkList(TLO.New.getNode()); 622 AddUsersToWorkList(TLO.New.getNode()); 623 624 // Finally, if the node is now dead, remove it from the graph. The node 625 // may not be dead if the replacement process recursively simplified to 626 // something else needing this node. 627 if (TLO.Old.getNode()->use_empty()) { 628 removeFromWorkList(TLO.Old.getNode()); 629 630 // If the operands of this node are only used by the node, they will now 631 // be dead. Make sure to visit them first to delete dead nodes early. 632 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i) 633 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse()) 634 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode()); 635 636 DAG.DeleteNode(TLO.Old.getNode()); 637 } 638} 639 640/// SimplifyDemandedBits - Check the specified integer node value to see if 641/// it can be simplified or if things it uses can be simplified by bit 642/// propagation. If so, return true. 643bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 644 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations); 645 APInt KnownZero, KnownOne; 646 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 647 return false; 648 649 // Revisit the node. 650 AddToWorkList(Op.getNode()); 651 652 // Replace the old value with the new one. 653 ++NodesCombined; 654 DEBUG(dbgs() << "\nReplacing.2 "; 655 TLO.Old.getNode()->dump(&DAG); 656 dbgs() << "\nWith: "; 657 TLO.New.getNode()->dump(&DAG); 658 dbgs() << '\n'); 659 660 CommitTargetLoweringOpt(TLO); 661 return true; 662} 663 664void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) { 665 DebugLoc dl = Load->getDebugLoc(); 666 EVT VT = Load->getValueType(0); 667 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0)); 668 669 DEBUG(dbgs() << "\nReplacing.9 "; 670 Load->dump(&DAG); 671 dbgs() << "\nWith: "; 672 Trunc.getNode()->dump(&DAG); 673 dbgs() << '\n'); 674 WorkListRemover DeadNodes(*this); 675 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc, &DeadNodes); 676 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1), 677 &DeadNodes); 678 removeFromWorkList(Load); 679 DAG.DeleteNode(Load); 680 AddToWorkList(Trunc.getNode()); 681} 682 683SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) { 684 Replace = false; 685 DebugLoc dl = Op.getDebugLoc(); 686 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) { 687 EVT MemVT = LD->getMemoryVT(); 688 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 689 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD 690 : ISD::EXTLOAD) 691 : LD->getExtensionType(); 692 Replace = true; 693 return DAG.getExtLoad(ExtType, dl, PVT, 694 LD->getChain(), LD->getBasePtr(), 695 LD->getPointerInfo(), 696 MemVT, LD->isVolatile(), 697 LD->isNonTemporal(), LD->getAlignment()); 698 } 699 700 unsigned Opc = Op.getOpcode(); 701 switch (Opc) { 702 default: break; 703 case ISD::AssertSext: 704 return DAG.getNode(ISD::AssertSext, dl, PVT, 705 SExtPromoteOperand(Op.getOperand(0), PVT), 706 Op.getOperand(1)); 707 case ISD::AssertZext: 708 return DAG.getNode(ISD::AssertZext, dl, PVT, 709 ZExtPromoteOperand(Op.getOperand(0), PVT), 710 Op.getOperand(1)); 711 case ISD::Constant: { 712 unsigned ExtOpc = 713 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 714 return DAG.getNode(ExtOpc, dl, PVT, Op); 715 } 716 } 717 718 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT)) 719 return SDValue(); 720 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op); 721} 722 723SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) { 724 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT)) 725 return SDValue(); 726 EVT OldVT = Op.getValueType(); 727 DebugLoc dl = Op.getDebugLoc(); 728 bool Replace = false; 729 SDValue NewOp = PromoteOperand(Op, PVT, Replace); 730 if (NewOp.getNode() == 0) 731 return SDValue(); 732 AddToWorkList(NewOp.getNode()); 733 734 if (Replace) 735 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 736 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp, 737 DAG.getValueType(OldVT)); 738} 739 740SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) { 741 EVT OldVT = Op.getValueType(); 742 DebugLoc dl = Op.getDebugLoc(); 743 bool Replace = false; 744 SDValue NewOp = PromoteOperand(Op, PVT, Replace); 745 if (NewOp.getNode() == 0) 746 return SDValue(); 747 AddToWorkList(NewOp.getNode()); 748 749 if (Replace) 750 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 751 return DAG.getZeroExtendInReg(NewOp, dl, OldVT); 752} 753 754/// PromoteIntBinOp - Promote the specified integer binary operation if the 755/// target indicates it is beneficial. e.g. On x86, it's usually better to 756/// promote i16 operations to i32 since i16 instructions are longer. 757SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) { 758 if (!LegalOperations) 759 return SDValue(); 760 761 EVT VT = Op.getValueType(); 762 if (VT.isVector() || !VT.isInteger()) 763 return SDValue(); 764 765 // If operation type is 'undesirable', e.g. i16 on x86, consider 766 // promoting it. 767 unsigned Opc = Op.getOpcode(); 768 if (TLI.isTypeDesirableForOp(Opc, VT)) 769 return SDValue(); 770 771 EVT PVT = VT; 772 // Consult target whether it is a good idea to promote this operation and 773 // what's the right type to promote it to. 774 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 775 assert(PVT != VT && "Don't know what type to promote to!"); 776 777 bool Replace0 = false; 778 SDValue N0 = Op.getOperand(0); 779 SDValue NN0 = PromoteOperand(N0, PVT, Replace0); 780 if (NN0.getNode() == 0) 781 return SDValue(); 782 783 bool Replace1 = false; 784 SDValue N1 = Op.getOperand(1); 785 SDValue NN1; 786 if (N0 == N1) 787 NN1 = NN0; 788 else { 789 NN1 = PromoteOperand(N1, PVT, Replace1); 790 if (NN1.getNode() == 0) 791 return SDValue(); 792 } 793 794 AddToWorkList(NN0.getNode()); 795 if (NN1.getNode()) 796 AddToWorkList(NN1.getNode()); 797 798 if (Replace0) 799 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode()); 800 if (Replace1) 801 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode()); 802 803 DEBUG(dbgs() << "\nPromoting "; 804 Op.getNode()->dump(&DAG)); 805 DebugLoc dl = Op.getDebugLoc(); 806 return DAG.getNode(ISD::TRUNCATE, dl, VT, 807 DAG.getNode(Opc, dl, PVT, NN0, NN1)); 808 } 809 return SDValue(); 810} 811 812/// PromoteIntShiftOp - Promote the specified integer shift operation if the 813/// target indicates it is beneficial. e.g. On x86, it's usually better to 814/// promote i16 operations to i32 since i16 instructions are longer. 815SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) { 816 if (!LegalOperations) 817 return SDValue(); 818 819 EVT VT = Op.getValueType(); 820 if (VT.isVector() || !VT.isInteger()) 821 return SDValue(); 822 823 // If operation type is 'undesirable', e.g. i16 on x86, consider 824 // promoting it. 825 unsigned Opc = Op.getOpcode(); 826 if (TLI.isTypeDesirableForOp(Opc, VT)) 827 return SDValue(); 828 829 EVT PVT = VT; 830 // Consult target whether it is a good idea to promote this operation and 831 // what's the right type to promote it to. 832 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 833 assert(PVT != VT && "Don't know what type to promote to!"); 834 835 bool Replace = false; 836 SDValue N0 = Op.getOperand(0); 837 if (Opc == ISD::SRA) 838 N0 = SExtPromoteOperand(Op.getOperand(0), PVT); 839 else if (Opc == ISD::SRL) 840 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT); 841 else 842 N0 = PromoteOperand(N0, PVT, Replace); 843 if (N0.getNode() == 0) 844 return SDValue(); 845 846 AddToWorkList(N0.getNode()); 847 if (Replace) 848 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode()); 849 850 DEBUG(dbgs() << "\nPromoting "; 851 Op.getNode()->dump(&DAG)); 852 DebugLoc dl = Op.getDebugLoc(); 853 return DAG.getNode(ISD::TRUNCATE, dl, VT, 854 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1))); 855 } 856 return SDValue(); 857} 858 859SDValue DAGCombiner::PromoteExtend(SDValue Op) { 860 if (!LegalOperations) 861 return SDValue(); 862 863 EVT VT = Op.getValueType(); 864 if (VT.isVector() || !VT.isInteger()) 865 return SDValue(); 866 867 // If operation type is 'undesirable', e.g. i16 on x86, consider 868 // promoting it. 869 unsigned Opc = Op.getOpcode(); 870 if (TLI.isTypeDesirableForOp(Opc, VT)) 871 return SDValue(); 872 873 EVT PVT = VT; 874 // Consult target whether it is a good idea to promote this operation and 875 // what's the right type to promote it to. 876 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 877 assert(PVT != VT && "Don't know what type to promote to!"); 878 // fold (aext (aext x)) -> (aext x) 879 // fold (aext (zext x)) -> (zext x) 880 // fold (aext (sext x)) -> (sext x) 881 DEBUG(dbgs() << "\nPromoting "; 882 Op.getNode()->dump(&DAG)); 883 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), VT, Op.getOperand(0)); 884 } 885 return SDValue(); 886} 887 888bool DAGCombiner::PromoteLoad(SDValue Op) { 889 if (!LegalOperations) 890 return false; 891 892 EVT VT = Op.getValueType(); 893 if (VT.isVector() || !VT.isInteger()) 894 return false; 895 896 // If operation type is 'undesirable', e.g. i16 on x86, consider 897 // promoting it. 898 unsigned Opc = Op.getOpcode(); 899 if (TLI.isTypeDesirableForOp(Opc, VT)) 900 return false; 901 902 EVT PVT = VT; 903 // Consult target whether it is a good idea to promote this operation and 904 // what's the right type to promote it to. 905 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 906 assert(PVT != VT && "Don't know what type to promote to!"); 907 908 DebugLoc dl = Op.getDebugLoc(); 909 SDNode *N = Op.getNode(); 910 LoadSDNode *LD = cast<LoadSDNode>(N); 911 EVT MemVT = LD->getMemoryVT(); 912 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 913 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD 914 : ISD::EXTLOAD) 915 : LD->getExtensionType(); 916 SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT, 917 LD->getChain(), LD->getBasePtr(), 918 LD->getPointerInfo(), 919 MemVT, LD->isVolatile(), 920 LD->isNonTemporal(), LD->getAlignment()); 921 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD); 922 923 DEBUG(dbgs() << "\nPromoting "; 924 N->dump(&DAG); 925 dbgs() << "\nTo: "; 926 Result.getNode()->dump(&DAG); 927 dbgs() << '\n'); 928 WorkListRemover DeadNodes(*this); 929 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result, &DeadNodes); 930 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1), &DeadNodes); 931 removeFromWorkList(N); 932 DAG.DeleteNode(N); 933 AddToWorkList(Result.getNode()); 934 return true; 935 } 936 return false; 937} 938 939 940//===----------------------------------------------------------------------===// 941// Main DAG Combiner implementation 942//===----------------------------------------------------------------------===// 943 944void DAGCombiner::Run(CombineLevel AtLevel) { 945 // set the instance variables, so that the various visit routines may use it. 946 Level = AtLevel; 947 LegalOperations = Level >= NoIllegalOperations; 948 LegalTypes = Level >= NoIllegalTypes; 949 950 // Add all the dag nodes to the worklist. 951 WorkList.reserve(DAG.allnodes_size()); 952 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 953 E = DAG.allnodes_end(); I != E; ++I) 954 WorkList.push_back(I); 955 956 // Create a dummy node (which is not added to allnodes), that adds a reference 957 // to the root node, preventing it from being deleted, and tracking any 958 // changes of the root. 959 HandleSDNode Dummy(DAG.getRoot()); 960 961 // The root of the dag may dangle to deleted nodes until the dag combiner is 962 // done. Set it to null to avoid confusion. 963 DAG.setRoot(SDValue()); 964 965 // while the worklist isn't empty, inspect the node on the end of it and 966 // try and combine it. 967 while (!WorkList.empty()) { 968 SDNode *N = WorkList.back(); 969 WorkList.pop_back(); 970 971 // If N has no uses, it is dead. Make sure to revisit all N's operands once 972 // N is deleted from the DAG, since they too may now be dead or may have a 973 // reduced number of uses, allowing other xforms. 974 if (N->use_empty() && N != &Dummy) { 975 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 976 AddToWorkList(N->getOperand(i).getNode()); 977 978 DAG.DeleteNode(N); 979 continue; 980 } 981 982 SDValue RV = combine(N); 983 984 if (RV.getNode() == 0) 985 continue; 986 987 ++NodesCombined; 988 989 // If we get back the same node we passed in, rather than a new node or 990 // zero, we know that the node must have defined multiple values and 991 // CombineTo was used. Since CombineTo takes care of the worklist 992 // mechanics for us, we have no work to do in this case. 993 if (RV.getNode() == N) 994 continue; 995 996 assert(N->getOpcode() != ISD::DELETED_NODE && 997 RV.getNode()->getOpcode() != ISD::DELETED_NODE && 998 "Node was deleted but visit returned new node!"); 999 1000 DEBUG(dbgs() << "\nReplacing.3 "; 1001 N->dump(&DAG); 1002 dbgs() << "\nWith: "; 1003 RV.getNode()->dump(&DAG); 1004 dbgs() << '\n'); 1005 1006 // Transfer debug value. 1007 DAG.TransferDbgValues(SDValue(N, 0), RV); 1008 WorkListRemover DeadNodes(*this); 1009 if (N->getNumValues() == RV.getNode()->getNumValues()) 1010 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes); 1011 else { 1012 assert(N->getValueType(0) == RV.getValueType() && 1013 N->getNumValues() == 1 && "Type mismatch"); 1014 SDValue OpV = RV; 1015 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes); 1016 } 1017 1018 // Push the new node and any users onto the worklist 1019 AddToWorkList(RV.getNode()); 1020 AddUsersToWorkList(RV.getNode()); 1021 1022 // Add any uses of the old node to the worklist in case this node is the 1023 // last one that uses them. They may become dead after this node is 1024 // deleted. 1025 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1026 AddToWorkList(N->getOperand(i).getNode()); 1027 1028 // Finally, if the node is now dead, remove it from the graph. The node 1029 // may not be dead if the replacement process recursively simplified to 1030 // something else needing this node. 1031 if (N->use_empty()) { 1032 // Nodes can be reintroduced into the worklist. Make sure we do not 1033 // process a node that has been replaced. 1034 removeFromWorkList(N); 1035 1036 // Finally, since the node is now dead, remove it from the graph. 1037 DAG.DeleteNode(N); 1038 } 1039 } 1040 1041 // If the root changed (e.g. it was a dead load, update the root). 1042 DAG.setRoot(Dummy.getValue()); 1043} 1044 1045SDValue DAGCombiner::visit(SDNode *N) { 1046 switch (N->getOpcode()) { 1047 default: break; 1048 case ISD::TokenFactor: return visitTokenFactor(N); 1049 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 1050 case ISD::ADD: return visitADD(N); 1051 case ISD::SUB: return visitSUB(N); 1052 case ISD::ADDC: return visitADDC(N); 1053 case ISD::ADDE: return visitADDE(N); 1054 case ISD::MUL: return visitMUL(N); 1055 case ISD::SDIV: return visitSDIV(N); 1056 case ISD::UDIV: return visitUDIV(N); 1057 case ISD::SREM: return visitSREM(N); 1058 case ISD::UREM: return visitUREM(N); 1059 case ISD::MULHU: return visitMULHU(N); 1060 case ISD::MULHS: return visitMULHS(N); 1061 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 1062 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 1063 case ISD::SMULO: return visitSMULO(N); 1064 case ISD::UMULO: return visitUMULO(N); 1065 case ISD::SDIVREM: return visitSDIVREM(N); 1066 case ISD::UDIVREM: return visitUDIVREM(N); 1067 case ISD::AND: return visitAND(N); 1068 case ISD::OR: return visitOR(N); 1069 case ISD::XOR: return visitXOR(N); 1070 case ISD::SHL: return visitSHL(N); 1071 case ISD::SRA: return visitSRA(N); 1072 case ISD::SRL: return visitSRL(N); 1073 case ISD::CTLZ: return visitCTLZ(N); 1074 case ISD::CTTZ: return visitCTTZ(N); 1075 case ISD::CTPOP: return visitCTPOP(N); 1076 case ISD::SELECT: return visitSELECT(N); 1077 case ISD::SELECT_CC: return visitSELECT_CC(N); 1078 case ISD::SETCC: return visitSETCC(N); 1079 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 1080 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 1081 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 1082 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 1083 case ISD::TRUNCATE: return visitTRUNCATE(N); 1084 case ISD::BITCAST: return visitBITCAST(N); 1085 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 1086 case ISD::FADD: return visitFADD(N); 1087 case ISD::FSUB: return visitFSUB(N); 1088 case ISD::FMUL: return visitFMUL(N); 1089 case ISD::FDIV: return visitFDIV(N); 1090 case ISD::FREM: return visitFREM(N); 1091 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 1092 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 1093 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 1094 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 1095 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 1096 case ISD::FP_ROUND: return visitFP_ROUND(N); 1097 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 1098 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 1099 case ISD::FNEG: return visitFNEG(N); 1100 case ISD::FABS: return visitFABS(N); 1101 case ISD::BRCOND: return visitBRCOND(N); 1102 case ISD::BR_CC: return visitBR_CC(N); 1103 case ISD::LOAD: return visitLOAD(N); 1104 case ISD::STORE: return visitSTORE(N); 1105 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 1106 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 1107 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 1108 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 1109 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N); 1110 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 1111 case ISD::MEMBARRIER: return visitMEMBARRIER(N); 1112 } 1113 return SDValue(); 1114} 1115 1116SDValue DAGCombiner::combine(SDNode *N) { 1117 SDValue RV = visit(N); 1118 1119 // If nothing happened, try a target-specific DAG combine. 1120 if (RV.getNode() == 0) { 1121 assert(N->getOpcode() != ISD::DELETED_NODE && 1122 "Node was deleted but visit returned NULL!"); 1123 1124 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 1125 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 1126 1127 // Expose the DAG combiner to the target combiner impls. 1128 TargetLowering::DAGCombinerInfo 1129 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 1130 1131 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 1132 } 1133 } 1134 1135 // If nothing happened still, try promoting the operation. 1136 if (RV.getNode() == 0) { 1137 switch (N->getOpcode()) { 1138 default: break; 1139 case ISD::ADD: 1140 case ISD::SUB: 1141 case ISD::MUL: 1142 case ISD::AND: 1143 case ISD::OR: 1144 case ISD::XOR: 1145 RV = PromoteIntBinOp(SDValue(N, 0)); 1146 break; 1147 case ISD::SHL: 1148 case ISD::SRA: 1149 case ISD::SRL: 1150 RV = PromoteIntShiftOp(SDValue(N, 0)); 1151 break; 1152 case ISD::SIGN_EXTEND: 1153 case ISD::ZERO_EXTEND: 1154 case ISD::ANY_EXTEND: 1155 RV = PromoteExtend(SDValue(N, 0)); 1156 break; 1157 case ISD::LOAD: 1158 if (PromoteLoad(SDValue(N, 0))) 1159 RV = SDValue(N, 0); 1160 break; 1161 } 1162 } 1163 1164 // If N is a commutative binary node, try commuting it to enable more 1165 // sdisel CSE. 1166 if (RV.getNode() == 0 && 1167 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 1168 N->getNumValues() == 1) { 1169 SDValue N0 = N->getOperand(0); 1170 SDValue N1 = N->getOperand(1); 1171 1172 // Constant operands are canonicalized to RHS. 1173 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 1174 SDValue Ops[] = { N1, N0 }; 1175 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 1176 Ops, 2); 1177 if (CSENode) 1178 return SDValue(CSENode, 0); 1179 } 1180 } 1181 1182 return RV; 1183} 1184 1185/// getInputChainForNode - Given a node, return its input chain if it has one, 1186/// otherwise return a null sd operand. 1187static SDValue getInputChainForNode(SDNode *N) { 1188 if (unsigned NumOps = N->getNumOperands()) { 1189 if (N->getOperand(0).getValueType() == MVT::Other) 1190 return N->getOperand(0); 1191 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 1192 return N->getOperand(NumOps-1); 1193 for (unsigned i = 1; i < NumOps-1; ++i) 1194 if (N->getOperand(i).getValueType() == MVT::Other) 1195 return N->getOperand(i); 1196 } 1197 return SDValue(); 1198} 1199 1200SDValue DAGCombiner::visitTokenFactor(SDNode *N) { 1201 // If N has two operands, where one has an input chain equal to the other, 1202 // the 'other' chain is redundant. 1203 if (N->getNumOperands() == 2) { 1204 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) 1205 return N->getOperand(0); 1206 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) 1207 return N->getOperand(1); 1208 } 1209 1210 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 1211 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 1212 SmallPtrSet<SDNode*, 16> SeenOps; 1213 bool Changed = false; // If we should replace this token factor. 1214 1215 // Start out with this token factor. 1216 TFs.push_back(N); 1217 1218 // Iterate through token factors. The TFs grows when new token factors are 1219 // encountered. 1220 for (unsigned i = 0; i < TFs.size(); ++i) { 1221 SDNode *TF = TFs[i]; 1222 1223 // Check each of the operands. 1224 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 1225 SDValue Op = TF->getOperand(i); 1226 1227 switch (Op.getOpcode()) { 1228 case ISD::EntryToken: 1229 // Entry tokens don't need to be added to the list. They are 1230 // rededundant. 1231 Changed = true; 1232 break; 1233 1234 case ISD::TokenFactor: 1235 if (Op.hasOneUse() && 1236 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { 1237 // Queue up for processing. 1238 TFs.push_back(Op.getNode()); 1239 // Clean up in case the token factor is removed. 1240 AddToWorkList(Op.getNode()); 1241 Changed = true; 1242 break; 1243 } 1244 // Fall thru 1245 1246 default: 1247 // Only add if it isn't already in the list. 1248 if (SeenOps.insert(Op.getNode())) 1249 Ops.push_back(Op); 1250 else 1251 Changed = true; 1252 break; 1253 } 1254 } 1255 } 1256 1257 SDValue Result; 1258 1259 // If we've change things around then replace token factor. 1260 if (Changed) { 1261 if (Ops.empty()) { 1262 // The entry token is the only possible outcome. 1263 Result = DAG.getEntryNode(); 1264 } else { 1265 // New and improved token factor. 1266 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 1267 MVT::Other, &Ops[0], Ops.size()); 1268 } 1269 1270 // Don't add users to work list. 1271 return CombineTo(N, Result, false); 1272 } 1273 1274 return Result; 1275} 1276 1277/// MERGE_VALUES can always be eliminated. 1278SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 1279 WorkListRemover DeadNodes(*this); 1280 // Replacing results may cause a different MERGE_VALUES to suddenly 1281 // be CSE'd with N, and carry its uses with it. Iterate until no 1282 // uses remain, to ensure that the node can be safely deleted. 1283 do { 1284 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1285 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i), 1286 &DeadNodes); 1287 } while (!N->use_empty()); 1288 removeFromWorkList(N); 1289 DAG.DeleteNode(N); 1290 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1291} 1292 1293static 1294SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1, 1295 SelectionDAG &DAG) { 1296 EVT VT = N0.getValueType(); 1297 SDValue N00 = N0.getOperand(0); 1298 SDValue N01 = N0.getOperand(1); 1299 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 1300 1301 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && 1302 isa<ConstantSDNode>(N00.getOperand(1))) { 1303 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1304 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, 1305 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT, 1306 N00.getOperand(0), N01), 1307 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT, 1308 N00.getOperand(1), N01)); 1309 return DAG.getNode(ISD::ADD, DL, VT, N0, N1); 1310 } 1311 1312 return SDValue(); 1313} 1314 1315SDValue DAGCombiner::visitADD(SDNode *N) { 1316 SDValue N0 = N->getOperand(0); 1317 SDValue N1 = N->getOperand(1); 1318 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1319 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1320 EVT VT = N0.getValueType(); 1321 1322 // fold vector ops 1323 if (VT.isVector()) { 1324 SDValue FoldedVOp = SimplifyVBinOp(N); 1325 if (FoldedVOp.getNode()) return FoldedVOp; 1326 } 1327 1328 // fold (add x, undef) -> undef 1329 if (N0.getOpcode() == ISD::UNDEF) 1330 return N0; 1331 if (N1.getOpcode() == ISD::UNDEF) 1332 return N1; 1333 // fold (add c1, c2) -> c1+c2 1334 if (N0C && N1C) 1335 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C); 1336 // canonicalize constant to RHS 1337 if (N0C && !N1C) 1338 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0); 1339 // fold (add x, 0) -> x 1340 if (N1C && N1C->isNullValue()) 1341 return N0; 1342 // fold (add Sym, c) -> Sym+c 1343 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1344 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C && 1345 GA->getOpcode() == ISD::GlobalAddress) 1346 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT, 1347 GA->getOffset() + 1348 (uint64_t)N1C->getSExtValue()); 1349 // fold ((c1-A)+c2) -> (c1+c2)-A 1350 if (N1C && N0.getOpcode() == ISD::SUB) 1351 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 1352 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1353 DAG.getConstant(N1C->getAPIntValue()+ 1354 N0C->getAPIntValue(), VT), 1355 N0.getOperand(1)); 1356 // reassociate add 1357 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1); 1358 if (RADD.getNode() != 0) 1359 return RADD; 1360 // fold ((0-A) + B) -> B-A 1361 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 1362 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 1363 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1)); 1364 // fold (A + (0-B)) -> A-B 1365 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1366 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 1367 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1)); 1368 // fold (A+(B-A)) -> B 1369 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 1370 return N1.getOperand(0); 1371 // fold ((B-A)+A) -> B 1372 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) 1373 return N0.getOperand(0); 1374 // fold (A+(B-(A+C))) to (B-C) 1375 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1376 N0 == N1.getOperand(1).getOperand(0)) 1377 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1378 N1.getOperand(1).getOperand(1)); 1379 // fold (A+(B-(C+A))) to (B-C) 1380 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1381 N0 == N1.getOperand(1).getOperand(1)) 1382 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1383 N1.getOperand(1).getOperand(0)); 1384 // fold (A+((B-A)+or-C)) to (B+or-C) 1385 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && 1386 N1.getOperand(0).getOpcode() == ISD::SUB && 1387 N0 == N1.getOperand(0).getOperand(1)) 1388 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT, 1389 N1.getOperand(0).getOperand(0), N1.getOperand(1)); 1390 1391 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant 1392 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) { 1393 SDValue N00 = N0.getOperand(0); 1394 SDValue N01 = N0.getOperand(1); 1395 SDValue N10 = N1.getOperand(0); 1396 SDValue N11 = N1.getOperand(1); 1397 1398 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10)) 1399 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1400 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10), 1401 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11)); 1402 } 1403 1404 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 1405 return SDValue(N, 0); 1406 1407 // fold (a+b) -> (a|b) iff a and b share no bits. 1408 if (VT.isInteger() && !VT.isVector()) { 1409 APInt LHSZero, LHSOne; 1410 APInt RHSZero, RHSOne; 1411 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 1412 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1413 1414 if (LHSZero.getBoolValue()) { 1415 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1416 1417 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1418 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1419 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1420 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1421 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1); 1422 } 1423 } 1424 1425 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1426 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1427 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG); 1428 if (Result.getNode()) return Result; 1429 } 1430 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1431 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG); 1432 if (Result.getNode()) return Result; 1433 } 1434 1435 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n)) 1436 if (N1.getOpcode() == ISD::SHL && 1437 N1.getOperand(0).getOpcode() == ISD::SUB) 1438 if (ConstantSDNode *C = 1439 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0))) 1440 if (C->getAPIntValue() == 0) 1441 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, 1442 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1443 N1.getOperand(0).getOperand(1), 1444 N1.getOperand(1))); 1445 if (N0.getOpcode() == ISD::SHL && 1446 N0.getOperand(0).getOpcode() == ISD::SUB) 1447 if (ConstantSDNode *C = 1448 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0))) 1449 if (C->getAPIntValue() == 0) 1450 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, 1451 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1452 N0.getOperand(0).getOperand(1), 1453 N0.getOperand(1))); 1454 1455 if (N1.getOpcode() == ISD::AND) { 1456 SDValue AndOp0 = N1.getOperand(0); 1457 ConstantSDNode *AndOp1 = dyn_cast<ConstantSDNode>(N1->getOperand(1)); 1458 unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0); 1459 unsigned DestBits = VT.getScalarType().getSizeInBits(); 1460 1461 // (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x)) 1462 // and similar xforms where the inner op is either ~0 or 0. 1463 if (NumSignBits == DestBits && AndOp1 && AndOp1->isOne()) { 1464 DebugLoc DL = N->getDebugLoc(); 1465 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0); 1466 } 1467 } 1468 1469 // add (sext i1), X -> sub X, (zext i1) 1470 if (N0.getOpcode() == ISD::SIGN_EXTEND && 1471 N0.getOperand(0).getValueType() == MVT::i1 && 1472 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) { 1473 DebugLoc DL = N->getDebugLoc(); 1474 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)); 1475 return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt); 1476 } 1477 1478 return SDValue(); 1479} 1480 1481SDValue DAGCombiner::visitADDC(SDNode *N) { 1482 SDValue N0 = N->getOperand(0); 1483 SDValue N1 = N->getOperand(1); 1484 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1485 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1486 EVT VT = N0.getValueType(); 1487 1488 // If the flag result is dead, turn this into an ADD. 1489 if (N->hasNUsesOfValue(0, 1)) 1490 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0), 1491 DAG.getNode(ISD::CARRY_FALSE, 1492 N->getDebugLoc(), MVT::Glue)); 1493 1494 // canonicalize constant to RHS. 1495 if (N0C && !N1C) 1496 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1497 1498 // fold (addc x, 0) -> x + no carry out 1499 if (N1C && N1C->isNullValue()) 1500 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, 1501 N->getDebugLoc(), MVT::Glue)); 1502 1503 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1504 APInt LHSZero, LHSOne; 1505 APInt RHSZero, RHSOne; 1506 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 1507 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1508 1509 if (LHSZero.getBoolValue()) { 1510 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1511 1512 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1513 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1514 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1515 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1516 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1), 1517 DAG.getNode(ISD::CARRY_FALSE, 1518 N->getDebugLoc(), MVT::Glue)); 1519 } 1520 1521 return SDValue(); 1522} 1523 1524SDValue DAGCombiner::visitADDE(SDNode *N) { 1525 SDValue N0 = N->getOperand(0); 1526 SDValue N1 = N->getOperand(1); 1527 SDValue CarryIn = N->getOperand(2); 1528 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1529 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1530 1531 // canonicalize constant to RHS 1532 if (N0C && !N1C) 1533 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), 1534 N1, N0, CarryIn); 1535 1536 // fold (adde x, y, false) -> (addc x, y) 1537 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1538 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1539 1540 return SDValue(); 1541} 1542 1543// Since it may not be valid to emit a fold to zero for vector initializers 1544// check if we can before folding. 1545static SDValue tryFoldToZero(DebugLoc DL, const TargetLowering &TLI, EVT VT, 1546 SelectionDAG &DAG, bool LegalOperations) { 1547 if (!VT.isVector()) { 1548 return DAG.getConstant(0, VT); 1549 } 1550 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 1551 // Produce a vector of zeros. 1552 SDValue El = DAG.getConstant(0, VT.getVectorElementType()); 1553 std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 1554 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, 1555 &Ops[0], Ops.size()); 1556 } 1557 return SDValue(); 1558} 1559 1560SDValue DAGCombiner::visitSUB(SDNode *N) { 1561 SDValue N0 = N->getOperand(0); 1562 SDValue N1 = N->getOperand(1); 1563 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1564 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1565 ConstantSDNode *N1C1 = N1.getOpcode() != ISD::ADD ? 0 : 1566 dyn_cast<ConstantSDNode>(N1.getOperand(1).getNode()); 1567 EVT VT = N0.getValueType(); 1568 1569 // fold vector ops 1570 if (VT.isVector()) { 1571 SDValue FoldedVOp = SimplifyVBinOp(N); 1572 if (FoldedVOp.getNode()) return FoldedVOp; 1573 } 1574 1575 // fold (sub x, x) -> 0 1576 // FIXME: Refactor this and xor and other similar operations together. 1577 if (N0 == N1) 1578 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations); 1579 // fold (sub c1, c2) -> c1-c2 1580 if (N0C && N1C) 1581 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C); 1582 // fold (sub x, c) -> (add x, -c) 1583 if (N1C) 1584 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, 1585 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1586 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) 1587 if (N0C && N0C->isAllOnesValue()) 1588 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 1589 // fold A-(A-B) -> B 1590 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0)) 1591 return N1.getOperand(1); 1592 // fold (A+B)-A -> B 1593 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1594 return N0.getOperand(1); 1595 // fold (A+B)-B -> A 1596 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1597 return N0.getOperand(0); 1598 // fold C2-(A+C1) -> (C2-C1)-A 1599 if (N1.getOpcode() == ISD::ADD && N0C && N1C1) { 1600 SDValue NewC = DAG.getConstant((N0C->getAPIntValue() - N1C1->getAPIntValue()), VT); 1601 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, NewC, 1602 N1.getOperand(0)); 1603 } 1604 // fold ((A+(B+or-C))-B) -> A+or-C 1605 if (N0.getOpcode() == ISD::ADD && 1606 (N0.getOperand(1).getOpcode() == ISD::SUB || 1607 N0.getOperand(1).getOpcode() == ISD::ADD) && 1608 N0.getOperand(1).getOperand(0) == N1) 1609 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT, 1610 N0.getOperand(0), N0.getOperand(1).getOperand(1)); 1611 // fold ((A+(C+B))-B) -> A+C 1612 if (N0.getOpcode() == ISD::ADD && 1613 N0.getOperand(1).getOpcode() == ISD::ADD && 1614 N0.getOperand(1).getOperand(1) == N1) 1615 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1616 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1617 // fold ((A-(B-C))-C) -> A-B 1618 if (N0.getOpcode() == ISD::SUB && 1619 N0.getOperand(1).getOpcode() == ISD::SUB && 1620 N0.getOperand(1).getOperand(1) == N1) 1621 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1622 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1623 1624 // If either operand of a sub is undef, the result is undef 1625 if (N0.getOpcode() == ISD::UNDEF) 1626 return N0; 1627 if (N1.getOpcode() == ISD::UNDEF) 1628 return N1; 1629 1630 // If the relocation model supports it, consider symbol offsets. 1631 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1632 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) { 1633 // fold (sub Sym, c) -> Sym-c 1634 if (N1C && GA->getOpcode() == ISD::GlobalAddress) 1635 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT, 1636 GA->getOffset() - 1637 (uint64_t)N1C->getSExtValue()); 1638 // fold (sub Sym+c1, Sym+c2) -> c1-c2 1639 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1)) 1640 if (GA->getGlobal() == GB->getGlobal()) 1641 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(), 1642 VT); 1643 } 1644 1645 return SDValue(); 1646} 1647 1648SDValue DAGCombiner::visitMUL(SDNode *N) { 1649 SDValue N0 = N->getOperand(0); 1650 SDValue N1 = N->getOperand(1); 1651 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1652 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1653 EVT VT = N0.getValueType(); 1654 1655 // fold vector ops 1656 if (VT.isVector()) { 1657 SDValue FoldedVOp = SimplifyVBinOp(N); 1658 if (FoldedVOp.getNode()) return FoldedVOp; 1659 } 1660 1661 // fold (mul x, undef) -> 0 1662 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1663 return DAG.getConstant(0, VT); 1664 // fold (mul c1, c2) -> c1*c2 1665 if (N0C && N1C) 1666 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C); 1667 // canonicalize constant to RHS 1668 if (N0C && !N1C) 1669 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0); 1670 // fold (mul x, 0) -> 0 1671 if (N1C && N1C->isNullValue()) 1672 return N1; 1673 // fold (mul x, -1) -> 0-x 1674 if (N1C && N1C->isAllOnesValue()) 1675 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1676 DAG.getConstant(0, VT), N0); 1677 // fold (mul x, (1 << c)) -> x << c 1678 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1679 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1680 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1681 getShiftAmountTy(N0.getValueType()))); 1682 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1683 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) { 1684 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2(); 1685 // FIXME: If the input is something that is easily negated (e.g. a 1686 // single-use add), we should put the negate there. 1687 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1688 DAG.getConstant(0, VT), 1689 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1690 DAG.getConstant(Log2Val, 1691 getShiftAmountTy(N0.getValueType())))); 1692 } 1693 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1694 if (N1C && N0.getOpcode() == ISD::SHL && 1695 isa<ConstantSDNode>(N0.getOperand(1))) { 1696 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1697 N1, N0.getOperand(1)); 1698 AddToWorkList(C3.getNode()); 1699 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1700 N0.getOperand(0), C3); 1701 } 1702 1703 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1704 // use. 1705 { 1706 SDValue Sh(0,0), Y(0,0); 1707 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1708 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1709 N0.getNode()->hasOneUse()) { 1710 Sh = N0; Y = N1; 1711 } else if (N1.getOpcode() == ISD::SHL && 1712 isa<ConstantSDNode>(N1.getOperand(1)) && 1713 N1.getNode()->hasOneUse()) { 1714 Sh = N1; Y = N0; 1715 } 1716 1717 if (Sh.getNode()) { 1718 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1719 Sh.getOperand(0), Y); 1720 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1721 Mul, Sh.getOperand(1)); 1722 } 1723 } 1724 1725 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1726 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 1727 isa<ConstantSDNode>(N0.getOperand(1))) 1728 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1729 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT, 1730 N0.getOperand(0), N1), 1731 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT, 1732 N0.getOperand(1), N1)); 1733 1734 // reassociate mul 1735 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1); 1736 if (RMUL.getNode() != 0) 1737 return RMUL; 1738 1739 return SDValue(); 1740} 1741 1742SDValue DAGCombiner::visitSDIV(SDNode *N) { 1743 SDValue N0 = N->getOperand(0); 1744 SDValue N1 = N->getOperand(1); 1745 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1746 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1747 EVT VT = N->getValueType(0); 1748 1749 // fold vector ops 1750 if (VT.isVector()) { 1751 SDValue FoldedVOp = SimplifyVBinOp(N); 1752 if (FoldedVOp.getNode()) return FoldedVOp; 1753 } 1754 1755 // fold (sdiv c1, c2) -> c1/c2 1756 if (N0C && N1C && !N1C->isNullValue()) 1757 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); 1758 // fold (sdiv X, 1) -> X 1759 if (N1C && N1C->getAPIntValue() == 1LL) 1760 return N0; 1761 // fold (sdiv X, -1) -> 0-X 1762 if (N1C && N1C->isAllOnesValue()) 1763 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1764 DAG.getConstant(0, VT), N0); 1765 // If we know the sign bits of both operands are zero, strength reduce to a 1766 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1767 if (!VT.isVector()) { 1768 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1769 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(), 1770 N0, N1); 1771 } 1772 // fold (sdiv X, pow2) -> simple ops after legalize 1773 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() && 1774 (N1C->getAPIntValue().isPowerOf2() || 1775 (-N1C->getAPIntValue()).isPowerOf2())) { 1776 // If dividing by powers of two is cheap, then don't perform the following 1777 // fold. 1778 if (TLI.isPow2DivCheap()) 1779 return SDValue(); 1780 1781 unsigned lg2 = N1C->getAPIntValue().countTrailingZeros(); 1782 1783 // Splat the sign bit into the register 1784 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 1785 DAG.getConstant(VT.getSizeInBits()-1, 1786 getShiftAmountTy(N0.getValueType()))); 1787 AddToWorkList(SGN.getNode()); 1788 1789 // Add (N0 < 0) ? abs2 - 1 : 0; 1790 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN, 1791 DAG.getConstant(VT.getSizeInBits() - lg2, 1792 getShiftAmountTy(SGN.getValueType()))); 1793 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL); 1794 AddToWorkList(SRL.getNode()); 1795 AddToWorkList(ADD.getNode()); // Divide by pow2 1796 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD, 1797 DAG.getConstant(lg2, getShiftAmountTy(ADD.getValueType()))); 1798 1799 // If we're dividing by a positive value, we're done. Otherwise, we must 1800 // negate the result. 1801 if (N1C->getAPIntValue().isNonNegative()) 1802 return SRA; 1803 1804 AddToWorkList(SRA.getNode()); 1805 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1806 DAG.getConstant(0, VT), SRA); 1807 } 1808 1809 // if integer divide is expensive and we satisfy the requirements, emit an 1810 // alternate sequence. 1811 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1812 SDValue Op = BuildSDIV(N); 1813 if (Op.getNode()) return Op; 1814 } 1815 1816 // undef / X -> 0 1817 if (N0.getOpcode() == ISD::UNDEF) 1818 return DAG.getConstant(0, VT); 1819 // X / undef -> undef 1820 if (N1.getOpcode() == ISD::UNDEF) 1821 return N1; 1822 1823 return SDValue(); 1824} 1825 1826SDValue DAGCombiner::visitUDIV(SDNode *N) { 1827 SDValue N0 = N->getOperand(0); 1828 SDValue N1 = N->getOperand(1); 1829 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1830 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1831 EVT VT = N->getValueType(0); 1832 1833 // fold vector ops 1834 if (VT.isVector()) { 1835 SDValue FoldedVOp = SimplifyVBinOp(N); 1836 if (FoldedVOp.getNode()) return FoldedVOp; 1837 } 1838 1839 // fold (udiv c1, c2) -> c1/c2 1840 if (N0C && N1C && !N1C->isNullValue()) 1841 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); 1842 // fold (udiv x, (1 << c)) -> x >>u c 1843 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1844 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 1845 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1846 getShiftAmountTy(N0.getValueType()))); 1847 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1848 if (N1.getOpcode() == ISD::SHL) { 1849 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1850 if (SHC->getAPIntValue().isPowerOf2()) { 1851 EVT ADDVT = N1.getOperand(1).getValueType(); 1852 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT, 1853 N1.getOperand(1), 1854 DAG.getConstant(SHC->getAPIntValue() 1855 .logBase2(), 1856 ADDVT)); 1857 AddToWorkList(Add.getNode()); 1858 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add); 1859 } 1860 } 1861 } 1862 // fold (udiv x, c) -> alternate 1863 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1864 SDValue Op = BuildUDIV(N); 1865 if (Op.getNode()) return Op; 1866 } 1867 1868 // undef / X -> 0 1869 if (N0.getOpcode() == ISD::UNDEF) 1870 return DAG.getConstant(0, VT); 1871 // X / undef -> undef 1872 if (N1.getOpcode() == ISD::UNDEF) 1873 return N1; 1874 1875 return SDValue(); 1876} 1877 1878SDValue DAGCombiner::visitSREM(SDNode *N) { 1879 SDValue N0 = N->getOperand(0); 1880 SDValue N1 = N->getOperand(1); 1881 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1882 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1883 EVT VT = N->getValueType(0); 1884 1885 // fold (srem c1, c2) -> c1%c2 1886 if (N0C && N1C && !N1C->isNullValue()) 1887 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); 1888 // If we know the sign bits of both operands are zero, strength reduce to a 1889 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1890 if (!VT.isVector()) { 1891 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1892 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1); 1893 } 1894 1895 // If X/C can be simplified by the division-by-constant logic, lower 1896 // X%C to the equivalent of X-X/C*C. 1897 if (N1C && !N1C->isNullValue()) { 1898 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1); 1899 AddToWorkList(Div.getNode()); 1900 SDValue OptimizedDiv = combine(Div.getNode()); 1901 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1902 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1903 OptimizedDiv, N1); 1904 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1905 AddToWorkList(Mul.getNode()); 1906 return Sub; 1907 } 1908 } 1909 1910 // undef % X -> 0 1911 if (N0.getOpcode() == ISD::UNDEF) 1912 return DAG.getConstant(0, VT); 1913 // X % undef -> undef 1914 if (N1.getOpcode() == ISD::UNDEF) 1915 return N1; 1916 1917 return SDValue(); 1918} 1919 1920SDValue DAGCombiner::visitUREM(SDNode *N) { 1921 SDValue N0 = N->getOperand(0); 1922 SDValue N1 = N->getOperand(1); 1923 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1924 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1925 EVT VT = N->getValueType(0); 1926 1927 // fold (urem c1, c2) -> c1%c2 1928 if (N0C && N1C && !N1C->isNullValue()) 1929 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C); 1930 // fold (urem x, pow2) -> (and x, pow2-1) 1931 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 1932 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, 1933 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 1934 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1935 if (N1.getOpcode() == ISD::SHL) { 1936 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1937 if (SHC->getAPIntValue().isPowerOf2()) { 1938 SDValue Add = 1939 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, 1940 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 1941 VT)); 1942 AddToWorkList(Add.getNode()); 1943 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add); 1944 } 1945 } 1946 } 1947 1948 // If X/C can be simplified by the division-by-constant logic, lower 1949 // X%C to the equivalent of X-X/C*C. 1950 if (N1C && !N1C->isNullValue()) { 1951 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1); 1952 AddToWorkList(Div.getNode()); 1953 SDValue OptimizedDiv = combine(Div.getNode()); 1954 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1955 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1956 OptimizedDiv, N1); 1957 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1958 AddToWorkList(Mul.getNode()); 1959 return Sub; 1960 } 1961 } 1962 1963 // undef % X -> 0 1964 if (N0.getOpcode() == ISD::UNDEF) 1965 return DAG.getConstant(0, VT); 1966 // X % undef -> undef 1967 if (N1.getOpcode() == ISD::UNDEF) 1968 return N1; 1969 1970 return SDValue(); 1971} 1972 1973SDValue DAGCombiner::visitMULHS(SDNode *N) { 1974 SDValue N0 = N->getOperand(0); 1975 SDValue N1 = N->getOperand(1); 1976 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1977 EVT VT = N->getValueType(0); 1978 DebugLoc DL = N->getDebugLoc(); 1979 1980 // fold (mulhs x, 0) -> 0 1981 if (N1C && N1C->isNullValue()) 1982 return N1; 1983 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1984 if (N1C && N1C->getAPIntValue() == 1) 1985 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0, 1986 DAG.getConstant(N0.getValueType().getSizeInBits() - 1, 1987 getShiftAmountTy(N0.getValueType()))); 1988 // fold (mulhs x, undef) -> 0 1989 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1990 return DAG.getConstant(0, VT); 1991 1992 // If the type twice as wide is legal, transform the mulhs to a wider multiply 1993 // plus a shift. 1994 if (VT.isSimple() && !VT.isVector()) { 1995 MVT Simple = VT.getSimpleVT(); 1996 unsigned SimpleSize = Simple.getSizeInBits(); 1997 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 1998 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 1999 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0); 2000 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1); 2001 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); 2002 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, 2003 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType()))); 2004 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); 2005 } 2006 } 2007 2008 return SDValue(); 2009} 2010 2011SDValue DAGCombiner::visitMULHU(SDNode *N) { 2012 SDValue N0 = N->getOperand(0); 2013 SDValue N1 = N->getOperand(1); 2014 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2015 EVT VT = N->getValueType(0); 2016 DebugLoc DL = N->getDebugLoc(); 2017 2018 // fold (mulhu x, 0) -> 0 2019 if (N1C && N1C->isNullValue()) 2020 return N1; 2021 // fold (mulhu x, 1) -> 0 2022 if (N1C && N1C->getAPIntValue() == 1) 2023 return DAG.getConstant(0, N0.getValueType()); 2024 // fold (mulhu x, undef) -> 0 2025 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2026 return DAG.getConstant(0, VT); 2027 2028 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2029 // plus a shift. 2030 if (VT.isSimple() && !VT.isVector()) { 2031 MVT Simple = VT.getSimpleVT(); 2032 unsigned SimpleSize = Simple.getSizeInBits(); 2033 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2034 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2035 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0); 2036 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1); 2037 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); 2038 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, 2039 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType()))); 2040 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); 2041 } 2042 } 2043 2044 return SDValue(); 2045} 2046 2047/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 2048/// compute two values. LoOp and HiOp give the opcodes for the two computations 2049/// that are being performed. Return true if a simplification was made. 2050/// 2051SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 2052 unsigned HiOp) { 2053 // If the high half is not needed, just compute the low half. 2054 bool HiExists = N->hasAnyUseOfValue(1); 2055 if (!HiExists && 2056 (!LegalOperations || 2057 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 2058 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 2059 N->op_begin(), N->getNumOperands()); 2060 return CombineTo(N, Res, Res); 2061 } 2062 2063 // If the low half is not needed, just compute the high half. 2064 bool LoExists = N->hasAnyUseOfValue(0); 2065 if (!LoExists && 2066 (!LegalOperations || 2067 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 2068 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 2069 N->op_begin(), N->getNumOperands()); 2070 return CombineTo(N, Res, Res); 2071 } 2072 2073 // If both halves are used, return as it is. 2074 if (LoExists && HiExists) 2075 return SDValue(); 2076 2077 // If the two computed results can be simplified separately, separate them. 2078 if (LoExists) { 2079 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 2080 N->op_begin(), N->getNumOperands()); 2081 AddToWorkList(Lo.getNode()); 2082 SDValue LoOpt = combine(Lo.getNode()); 2083 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && 2084 (!LegalOperations || 2085 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 2086 return CombineTo(N, LoOpt, LoOpt); 2087 } 2088 2089 if (HiExists) { 2090 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 2091 N->op_begin(), N->getNumOperands()); 2092 AddToWorkList(Hi.getNode()); 2093 SDValue HiOpt = combine(Hi.getNode()); 2094 if (HiOpt.getNode() && HiOpt != Hi && 2095 (!LegalOperations || 2096 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 2097 return CombineTo(N, HiOpt, HiOpt); 2098 } 2099 2100 return SDValue(); 2101} 2102 2103SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 2104 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 2105 if (Res.getNode()) return Res; 2106 2107 EVT VT = N->getValueType(0); 2108 DebugLoc DL = N->getDebugLoc(); 2109 2110 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2111 // plus a shift. 2112 if (VT.isSimple() && !VT.isVector()) { 2113 MVT Simple = VT.getSimpleVT(); 2114 unsigned SimpleSize = Simple.getSizeInBits(); 2115 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2116 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2117 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0)); 2118 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1)); 2119 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi); 2120 // Compute the high part as N1. 2121 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, 2122 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType()))); 2123 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); 2124 // Compute the low part as N0. 2125 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo); 2126 return CombineTo(N, Lo, Hi); 2127 } 2128 } 2129 2130 return SDValue(); 2131} 2132 2133SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 2134 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 2135 if (Res.getNode()) return Res; 2136 2137 EVT VT = N->getValueType(0); 2138 DebugLoc DL = N->getDebugLoc(); 2139 2140 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2141 // plus a shift. 2142 if (VT.isSimple() && !VT.isVector()) { 2143 MVT Simple = VT.getSimpleVT(); 2144 unsigned SimpleSize = Simple.getSizeInBits(); 2145 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2146 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2147 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0)); 2148 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1)); 2149 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi); 2150 // Compute the high part as N1. 2151 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, 2152 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType()))); 2153 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); 2154 // Compute the low part as N0. 2155 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo); 2156 return CombineTo(N, Lo, Hi); 2157 } 2158 } 2159 2160 return SDValue(); 2161} 2162 2163SDValue DAGCombiner::visitSMULO(SDNode *N) { 2164 // (smulo x, 2) -> (saddo x, x) 2165 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1))) 2166 if (C2->getAPIntValue() == 2) 2167 return DAG.getNode(ISD::SADDO, N->getDebugLoc(), N->getVTList(), 2168 N->getOperand(0), N->getOperand(0)); 2169 2170 return SDValue(); 2171} 2172 2173SDValue DAGCombiner::visitUMULO(SDNode *N) { 2174 // (umulo x, 2) -> (uaddo x, x) 2175 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1))) 2176 if (C2->getAPIntValue() == 2) 2177 return DAG.getNode(ISD::UADDO, N->getDebugLoc(), N->getVTList(), 2178 N->getOperand(0), N->getOperand(0)); 2179 2180 return SDValue(); 2181} 2182 2183SDValue DAGCombiner::visitSDIVREM(SDNode *N) { 2184 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 2185 if (Res.getNode()) return Res; 2186 2187 return SDValue(); 2188} 2189 2190SDValue DAGCombiner::visitUDIVREM(SDNode *N) { 2191 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 2192 if (Res.getNode()) return Res; 2193 2194 return SDValue(); 2195} 2196 2197/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 2198/// two operands of the same opcode, try to simplify it. 2199SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 2200 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 2201 EVT VT = N0.getValueType(); 2202 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 2203 2204 // Bail early if none of these transforms apply. 2205 if (N0.getNode()->getNumOperands() == 0) return SDValue(); 2206 2207 // For each of OP in AND/OR/XOR: 2208 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 2209 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 2210 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 2211 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free) 2212 // 2213 // do not sink logical op inside of a vector extend, since it may combine 2214 // into a vsetcc. 2215 EVT Op0VT = N0.getOperand(0).getValueType(); 2216 if ((N0.getOpcode() == ISD::ZERO_EXTEND || 2217 N0.getOpcode() == ISD::SIGN_EXTEND || 2218 // Avoid infinite looping with PromoteIntBinOp. 2219 (N0.getOpcode() == ISD::ANY_EXTEND && 2220 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) || 2221 (N0.getOpcode() == ISD::TRUNCATE && 2222 (!TLI.isZExtFree(VT, Op0VT) || 2223 !TLI.isTruncateFree(Op0VT, VT)) && 2224 TLI.isTypeLegal(Op0VT))) && 2225 !VT.isVector() && 2226 Op0VT == N1.getOperand(0).getValueType() && 2227 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) { 2228 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 2229 N0.getOperand(0).getValueType(), 2230 N0.getOperand(0), N1.getOperand(0)); 2231 AddToWorkList(ORNode.getNode()); 2232 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode); 2233 } 2234 2235 // For each of OP in SHL/SRL/SRA/AND... 2236 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 2237 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 2238 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 2239 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 2240 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 2241 N0.getOperand(1) == N1.getOperand(1)) { 2242 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 2243 N0.getOperand(0).getValueType(), 2244 N0.getOperand(0), N1.getOperand(0)); 2245 AddToWorkList(ORNode.getNode()); 2246 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 2247 ORNode, N0.getOperand(1)); 2248 } 2249 2250 return SDValue(); 2251} 2252 2253SDValue DAGCombiner::visitAND(SDNode *N) { 2254 SDValue N0 = N->getOperand(0); 2255 SDValue N1 = N->getOperand(1); 2256 SDValue LL, LR, RL, RR, CC0, CC1; 2257 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2258 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2259 EVT VT = N1.getValueType(); 2260 unsigned BitWidth = VT.getScalarType().getSizeInBits(); 2261 2262 // fold vector ops 2263 if (VT.isVector()) { 2264 SDValue FoldedVOp = SimplifyVBinOp(N); 2265 if (FoldedVOp.getNode()) return FoldedVOp; 2266 } 2267 2268 // fold (and x, undef) -> 0 2269 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2270 return DAG.getConstant(0, VT); 2271 // fold (and c1, c2) -> c1&c2 2272 if (N0C && N1C) 2273 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C); 2274 // canonicalize constant to RHS 2275 if (N0C && !N1C) 2276 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0); 2277 // fold (and x, -1) -> x 2278 if (N1C && N1C->isAllOnesValue()) 2279 return N0; 2280 // if (and x, c) is known to be zero, return 0 2281 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2282 APInt::getAllOnesValue(BitWidth))) 2283 return DAG.getConstant(0, VT); 2284 // reassociate and 2285 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1); 2286 if (RAND.getNode() != 0) 2287 return RAND; 2288 // fold (and (or x, C), D) -> D if (C & D) == D 2289 if (N1C && N0.getOpcode() == ISD::OR) 2290 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 2291 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 2292 return N1; 2293 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 2294 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2295 SDValue N0Op0 = N0.getOperand(0); 2296 APInt Mask = ~N1C->getAPIntValue(); 2297 Mask = Mask.trunc(N0Op0.getValueSizeInBits()); 2298 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 2299 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), 2300 N0.getValueType(), N0Op0); 2301 2302 // Replace uses of the AND with uses of the Zero extend node. 2303 CombineTo(N, Zext); 2304 2305 // We actually want to replace all uses of the any_extend with the 2306 // zero_extend, to avoid duplicating things. This will later cause this 2307 // AND to be folded. 2308 CombineTo(N0.getNode(), Zext); 2309 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2310 } 2311 } 2312 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 2313 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 2314 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 2315 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 2316 2317 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 2318 LL.getValueType().isInteger()) { 2319 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0) 2320 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 2321 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 2322 LR.getValueType(), LL, RL); 2323 AddToWorkList(ORNode.getNode()); 2324 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2325 } 2326 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1) 2327 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 2328 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(), 2329 LR.getValueType(), LL, RL); 2330 AddToWorkList(ANDNode.getNode()); 2331 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 2332 } 2333 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1) 2334 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 2335 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 2336 LR.getValueType(), LL, RL); 2337 AddToWorkList(ORNode.getNode()); 2338 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2339 } 2340 } 2341 // canonicalize equivalent to ll == rl 2342 if (LL == RR && LR == RL) { 2343 Op1 = ISD::getSetCCSwappedOperands(Op1); 2344 std::swap(RL, RR); 2345 } 2346 if (LL == RL && LR == RR) { 2347 bool isInteger = LL.getValueType().isInteger(); 2348 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 2349 if (Result != ISD::SETCC_INVALID && 2350 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 2351 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 2352 LL, LR, Result); 2353 } 2354 } 2355 2356 // Simplify: (and (op x...), (op y...)) -> (op (and x, y)) 2357 if (N0.getOpcode() == N1.getOpcode()) { 2358 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2359 if (Tmp.getNode()) return Tmp; 2360 } 2361 2362 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 2363 // fold (and (sra)) -> (and (srl)) when possible. 2364 if (!VT.isVector() && 2365 SimplifyDemandedBits(SDValue(N, 0))) 2366 return SDValue(N, 0); 2367 2368 // fold (zext_inreg (extload x)) -> (zextload x) 2369 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { 2370 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2371 EVT MemVT = LN0->getMemoryVT(); 2372 // If we zero all the possible extended bits, then we can turn this into 2373 // a zextload if we are running before legalize or the operation is legal. 2374 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2375 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2376 BitWidth - MemVT.getScalarType().getSizeInBits())) && 2377 ((!LegalOperations && !LN0->isVolatile()) || 2378 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2379 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 2380 LN0->getChain(), LN0->getBasePtr(), 2381 LN0->getPointerInfo(), MemVT, 2382 LN0->isVolatile(), LN0->isNonTemporal(), 2383 LN0->getAlignment()); 2384 AddToWorkList(N); 2385 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2386 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2387 } 2388 } 2389 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 2390 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 2391 N0.hasOneUse()) { 2392 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2393 EVT MemVT = LN0->getMemoryVT(); 2394 // If we zero all the possible extended bits, then we can turn this into 2395 // a zextload if we are running before legalize or the operation is legal. 2396 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2397 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2398 BitWidth - MemVT.getScalarType().getSizeInBits())) && 2399 ((!LegalOperations && !LN0->isVolatile()) || 2400 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2401 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 2402 LN0->getChain(), 2403 LN0->getBasePtr(), LN0->getPointerInfo(), 2404 MemVT, 2405 LN0->isVolatile(), LN0->isNonTemporal(), 2406 LN0->getAlignment()); 2407 AddToWorkList(N); 2408 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2409 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2410 } 2411 } 2412 2413 // fold (and (load x), 255) -> (zextload x, i8) 2414 // fold (and (extload x, i16), 255) -> (zextload x, i8) 2415 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8) 2416 if (N1C && (N0.getOpcode() == ISD::LOAD || 2417 (N0.getOpcode() == ISD::ANY_EXTEND && 2418 N0.getOperand(0).getOpcode() == ISD::LOAD))) { 2419 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND; 2420 LoadSDNode *LN0 = HasAnyExt 2421 ? cast<LoadSDNode>(N0.getOperand(0)) 2422 : cast<LoadSDNode>(N0); 2423 if (LN0->getExtensionType() != ISD::SEXTLOAD && 2424 LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) { 2425 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 2426 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){ 2427 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits); 2428 EVT LoadedVT = LN0->getMemoryVT(); 2429 2430 if (ExtVT == LoadedVT && 2431 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2432 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2433 2434 SDValue NewLoad = 2435 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 2436 LN0->getChain(), LN0->getBasePtr(), 2437 LN0->getPointerInfo(), 2438 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 2439 LN0->getAlignment()); 2440 AddToWorkList(N); 2441 CombineTo(LN0, NewLoad, NewLoad.getValue(1)); 2442 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2443 } 2444 2445 // Do not change the width of a volatile load. 2446 // Do not generate loads of non-round integer types since these can 2447 // be expensive (and would be wrong if the type is not byte sized). 2448 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() && 2449 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2450 EVT PtrType = LN0->getOperand(1).getValueType(); 2451 2452 unsigned Alignment = LN0->getAlignment(); 2453 SDValue NewPtr = LN0->getBasePtr(); 2454 2455 // For big endian targets, we need to add an offset to the pointer 2456 // to load the correct bytes. For little endian systems, we merely 2457 // need to read fewer bytes from the same pointer. 2458 if (TLI.isBigEndian()) { 2459 unsigned LVTStoreBytes = LoadedVT.getStoreSize(); 2460 unsigned EVTStoreBytes = ExtVT.getStoreSize(); 2461 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 2462 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType, 2463 NewPtr, DAG.getConstant(PtrOff, PtrType)); 2464 Alignment = MinAlign(Alignment, PtrOff); 2465 } 2466 2467 AddToWorkList(NewPtr.getNode()); 2468 2469 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2470 SDValue Load = 2471 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 2472 LN0->getChain(), NewPtr, 2473 LN0->getPointerInfo(), 2474 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 2475 Alignment); 2476 AddToWorkList(N); 2477 CombineTo(LN0, Load, Load.getValue(1)); 2478 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2479 } 2480 } 2481 } 2482 } 2483 2484 return SDValue(); 2485} 2486 2487/// MatchBSwapHWord - Match (a >> 8) | (a << 8) as (bswap a) >> 16 2488/// 2489SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1, 2490 bool DemandHighBits) { 2491 if (!LegalOperations) 2492 return SDValue(); 2493 2494 EVT VT = N->getValueType(0); 2495 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16) 2496 return SDValue(); 2497 if (!TLI.isOperationLegal(ISD::BSWAP, VT)) 2498 return SDValue(); 2499 2500 // Recognize (and (shl a, 8), 0xff), (and (srl a, 8), 0xff00) 2501 bool LookPassAnd0 = false; 2502 bool LookPassAnd1 = false; 2503 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL) 2504 std::swap(N0, N1); 2505 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL) 2506 std::swap(N0, N1); 2507 if (N0.getOpcode() == ISD::AND) { 2508 if (!N0.getNode()->hasOneUse()) 2509 return SDValue(); 2510 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2511 if (!N01C || N01C->getZExtValue() != 0xFF00) 2512 return SDValue(); 2513 N0 = N0.getOperand(0); 2514 LookPassAnd0 = true; 2515 } 2516 2517 if (N1.getOpcode() == ISD::AND) { 2518 if (!N1.getNode()->hasOneUse()) 2519 return SDValue(); 2520 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1)); 2521 if (!N11C || N11C->getZExtValue() != 0xFF) 2522 return SDValue(); 2523 N1 = N1.getOperand(0); 2524 LookPassAnd1 = true; 2525 } 2526 2527 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 2528 std::swap(N0, N1); 2529 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) 2530 return SDValue(); 2531 if (!N0.getNode()->hasOneUse() || 2532 !N1.getNode()->hasOneUse()) 2533 return SDValue(); 2534 2535 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2536 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1)); 2537 if (!N01C || !N11C) 2538 return SDValue(); 2539 if (N01C->getZExtValue() != 8 || N11C->getZExtValue() != 8) 2540 return SDValue(); 2541 2542 // Look for (shl (and a, 0xff), 8), (srl (and a, 0xff00), 8) 2543 SDValue N00 = N0->getOperand(0); 2544 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) { 2545 if (!N00.getNode()->hasOneUse()) 2546 return SDValue(); 2547 ConstantSDNode *N001C = dyn_cast<ConstantSDNode>(N00.getOperand(1)); 2548 if (!N001C || N001C->getZExtValue() != 0xFF) 2549 return SDValue(); 2550 N00 = N00.getOperand(0); 2551 LookPassAnd0 = true; 2552 } 2553 2554 SDValue N10 = N1->getOperand(0); 2555 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) { 2556 if (!N10.getNode()->hasOneUse()) 2557 return SDValue(); 2558 ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N10.getOperand(1)); 2559 if (!N101C || N101C->getZExtValue() != 0xFF00) 2560 return SDValue(); 2561 N10 = N10.getOperand(0); 2562 LookPassAnd1 = true; 2563 } 2564 2565 if (N00 != N10) 2566 return SDValue(); 2567 2568 // Make sure everything beyond the low halfword is zero since the SRL 16 2569 // will clear the top bits. 2570 unsigned OpSizeInBits = VT.getSizeInBits(); 2571 if (DemandHighBits && OpSizeInBits > 16 && 2572 (!LookPassAnd0 || !LookPassAnd1) && 2573 !DAG.MaskedValueIsZero(N10, APInt::getHighBitsSet(OpSizeInBits, 16))) 2574 return SDValue(); 2575 2576 SDValue Res = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT, N00); 2577 if (OpSizeInBits > 16) 2578 Res = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Res, 2579 DAG.getConstant(OpSizeInBits-16, getShiftAmountTy(VT))); 2580 return Res; 2581} 2582 2583/// isBSwapHWordElement - Return true if the specified node is an element 2584/// that makes up a 32-bit packed halfword byteswap. i.e. 2585/// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8) 2586static bool isBSwapHWordElement(SDValue N, SmallVector<SDNode*,4> &Parts) { 2587 if (!N.getNode()->hasOneUse()) 2588 return false; 2589 2590 unsigned Opc = N.getOpcode(); 2591 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL) 2592 return false; 2593 2594 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N.getOperand(1)); 2595 if (!N1C) 2596 return false; 2597 2598 unsigned Num; 2599 switch (N1C->getZExtValue()) { 2600 default: 2601 return false; 2602 case 0xFF: Num = 0; break; 2603 case 0xFF00: Num = 1; break; 2604 case 0xFF0000: Num = 2; break; 2605 case 0xFF000000: Num = 3; break; 2606 } 2607 2608 // Look for (x & 0xff) << 8 as well as ((x << 8) & 0xff00). 2609 SDValue N0 = N.getOperand(0); 2610 if (Opc == ISD::AND) { 2611 if (Num == 0 || Num == 2) { 2612 // (x >> 8) & 0xff 2613 // (x >> 8) & 0xff0000 2614 if (N0.getOpcode() != ISD::SRL) 2615 return false; 2616 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2617 if (!C || C->getZExtValue() != 8) 2618 return false; 2619 } else { 2620 // (x << 8) & 0xff00 2621 // (x << 8) & 0xff000000 2622 if (N0.getOpcode() != ISD::SHL) 2623 return false; 2624 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2625 if (!C || C->getZExtValue() != 8) 2626 return false; 2627 } 2628 } else if (Opc == ISD::SHL) { 2629 // (x & 0xff) << 8 2630 // (x & 0xff0000) << 8 2631 if (Num != 0 && Num != 2) 2632 return false; 2633 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1)); 2634 if (!C || C->getZExtValue() != 8) 2635 return false; 2636 } else { // Opc == ISD::SRL 2637 // (x & 0xff00) >> 8 2638 // (x & 0xff000000) >> 8 2639 if (Num != 1 && Num != 3) 2640 return false; 2641 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1)); 2642 if (!C || C->getZExtValue() != 8) 2643 return false; 2644 } 2645 2646 if (Parts[Num]) 2647 return false; 2648 2649 Parts[Num] = N0.getOperand(0).getNode(); 2650 return true; 2651} 2652 2653/// MatchBSwapHWord - Match a 32-bit packed halfword bswap. That is 2654/// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8) 2655/// => (rotl (bswap x), 16) 2656SDValue DAGCombiner::MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) { 2657 if (!LegalOperations) 2658 return SDValue(); 2659 2660 EVT VT = N->getValueType(0); 2661 if (VT != MVT::i32) 2662 return SDValue(); 2663 if (!TLI.isOperationLegal(ISD::BSWAP, VT)) 2664 return SDValue(); 2665 2666 SmallVector<SDNode*,4> Parts(4, (SDNode*)0); 2667 // Look for either 2668 // (or (or (and), (and)), (or (and), (and))) 2669 // (or (or (or (and), (and)), (and)), (and)) 2670 if (N0.getOpcode() != ISD::OR) 2671 return SDValue(); 2672 SDValue N00 = N0.getOperand(0); 2673 SDValue N01 = N0.getOperand(1); 2674 2675 if (N1.getOpcode() == ISD::OR) { 2676 // (or (or (and), (and)), (or (and), (and))) 2677 SDValue N000 = N00.getOperand(0); 2678 if (!isBSwapHWordElement(N000, Parts)) 2679 return SDValue(); 2680 2681 SDValue N001 = N00.getOperand(1); 2682 if (!isBSwapHWordElement(N001, Parts)) 2683 return SDValue(); 2684 SDValue N010 = N01.getOperand(0); 2685 if (!isBSwapHWordElement(N010, Parts)) 2686 return SDValue(); 2687 SDValue N011 = N01.getOperand(1); 2688 if (!isBSwapHWordElement(N011, Parts)) 2689 return SDValue(); 2690 } else { 2691 // (or (or (or (and), (and)), (and)), (and)) 2692 if (!isBSwapHWordElement(N1, Parts)) 2693 return SDValue(); 2694 if (!isBSwapHWordElement(N01, Parts)) 2695 return SDValue(); 2696 if (N00.getOpcode() != ISD::OR) 2697 return SDValue(); 2698 SDValue N000 = N00.getOperand(0); 2699 if (!isBSwapHWordElement(N000, Parts)) 2700 return SDValue(); 2701 SDValue N001 = N00.getOperand(1); 2702 if (!isBSwapHWordElement(N001, Parts)) 2703 return SDValue(); 2704 } 2705 2706 // Make sure the parts are all coming from the same node. 2707 if (Parts[0] != Parts[1] || Parts[0] != Parts[2] || Parts[0] != Parts[3]) 2708 return SDValue(); 2709 2710 SDValue BSwap = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT, 2711 SDValue(Parts[0],0)); 2712 2713 // Result of the bswap should be rotated by 16. If it's not legal, than 2714 // do (x << 16) | (x >> 16). 2715 SDValue ShAmt = DAG.getConstant(16, getShiftAmountTy(VT)); 2716 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT)) 2717 return DAG.getNode(ISD::ROTL, N->getDebugLoc(), VT, BSwap, ShAmt); 2718 else if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT)) 2719 return DAG.getNode(ISD::ROTR, N->getDebugLoc(), VT, BSwap, ShAmt); 2720 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, 2721 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, BSwap, ShAmt), 2722 DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, BSwap, ShAmt)); 2723} 2724 2725SDValue DAGCombiner::visitOR(SDNode *N) { 2726 SDValue N0 = N->getOperand(0); 2727 SDValue N1 = N->getOperand(1); 2728 SDValue LL, LR, RL, RR, CC0, CC1; 2729 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2730 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2731 EVT VT = N1.getValueType(); 2732 2733 // fold vector ops 2734 if (VT.isVector()) { 2735 SDValue FoldedVOp = SimplifyVBinOp(N); 2736 if (FoldedVOp.getNode()) return FoldedVOp; 2737 } 2738 2739 // fold (or x, undef) -> -1 2740 if (!LegalOperations && 2741 (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) { 2742 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 2743 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT); 2744 } 2745 // fold (or c1, c2) -> c1|c2 2746 if (N0C && N1C) 2747 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); 2748 // canonicalize constant to RHS 2749 if (N0C && !N1C) 2750 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0); 2751 // fold (or x, 0) -> x 2752 if (N1C && N1C->isNullValue()) 2753 return N0; 2754 // fold (or x, -1) -> -1 2755 if (N1C && N1C->isAllOnesValue()) 2756 return N1; 2757 // fold (or x, c) -> c iff (x & ~c) == 0 2758 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 2759 return N1; 2760 2761 // Recognize halfword bswaps as (bswap + rotl 16) or (bswap + shl 16) 2762 SDValue BSwap = MatchBSwapHWord(N, N0, N1); 2763 if (BSwap.getNode() != 0) 2764 return BSwap; 2765 BSwap = MatchBSwapHWordLow(N, N0, N1); 2766 if (BSwap.getNode() != 0) 2767 return BSwap; 2768 2769 // reassociate or 2770 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1); 2771 if (ROR.getNode() != 0) 2772 return ROR; 2773 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 2774 // iff (c1 & c2) == 0. 2775 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 2776 isa<ConstantSDNode>(N0.getOperand(1))) { 2777 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 2778 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0) 2779 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 2780 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 2781 N0.getOperand(0), N1), 2782 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1)); 2783 } 2784 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 2785 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 2786 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 2787 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 2788 2789 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 2790 LL.getValueType().isInteger()) { 2791 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0) 2792 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0) 2793 if (cast<ConstantSDNode>(LR)->isNullValue() && 2794 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 2795 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(), 2796 LR.getValueType(), LL, RL); 2797 AddToWorkList(ORNode.getNode()); 2798 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2799 } 2800 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1) 2801 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1) 2802 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 2803 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 2804 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(), 2805 LR.getValueType(), LL, RL); 2806 AddToWorkList(ANDNode.getNode()); 2807 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 2808 } 2809 } 2810 // canonicalize equivalent to ll == rl 2811 if (LL == RR && LR == RL) { 2812 Op1 = ISD::getSetCCSwappedOperands(Op1); 2813 std::swap(RL, RR); 2814 } 2815 if (LL == RL && LR == RR) { 2816 bool isInteger = LL.getValueType().isInteger(); 2817 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 2818 if (Result != ISD::SETCC_INVALID && 2819 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 2820 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 2821 LL, LR, Result); 2822 } 2823 } 2824 2825 // Simplify: (or (op x...), (op y...)) -> (op (or x, y)) 2826 if (N0.getOpcode() == N1.getOpcode()) { 2827 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2828 if (Tmp.getNode()) return Tmp; 2829 } 2830 2831 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible. 2832 if (N0.getOpcode() == ISD::AND && 2833 N1.getOpcode() == ISD::AND && 2834 N0.getOperand(1).getOpcode() == ISD::Constant && 2835 N1.getOperand(1).getOpcode() == ISD::Constant && 2836 // Don't increase # computations. 2837 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) { 2838 // We can only do this xform if we know that bits from X that are set in C2 2839 // but not in C1 are already zero. Likewise for Y. 2840 const APInt &LHSMask = 2841 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 2842 const APInt &RHSMask = 2843 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 2844 2845 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 2846 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 2847 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 2848 N0.getOperand(0), N1.getOperand(0)); 2849 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X, 2850 DAG.getConstant(LHSMask | RHSMask, VT)); 2851 } 2852 } 2853 2854 // See if this is some rotate idiom. 2855 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc())) 2856 return SDValue(Rot, 0); 2857 2858 // Simplify the operands using demanded-bits information. 2859 if (!VT.isVector() && 2860 SimplifyDemandedBits(SDValue(N, 0))) 2861 return SDValue(N, 0); 2862 2863 return SDValue(); 2864} 2865 2866/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 2867static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 2868 if (Op.getOpcode() == ISD::AND) { 2869 if (isa<ConstantSDNode>(Op.getOperand(1))) { 2870 Mask = Op.getOperand(1); 2871 Op = Op.getOperand(0); 2872 } else { 2873 return false; 2874 } 2875 } 2876 2877 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 2878 Shift = Op; 2879 return true; 2880 } 2881 2882 return false; 2883} 2884 2885// MatchRotate - Handle an 'or' of two operands. If this is one of the many 2886// idioms for rotate, and if the target supports rotation instructions, generate 2887// a rot[lr]. 2888SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) { 2889 // Must be a legal type. Expanded 'n promoted things won't work with rotates. 2890 EVT VT = LHS.getValueType(); 2891 if (!TLI.isTypeLegal(VT)) return 0; 2892 2893 // The target must have at least one rotate flavor. 2894 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT); 2895 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT); 2896 if (!HasROTL && !HasROTR) return 0; 2897 2898 // Match "(X shl/srl V1) & V2" where V2 may not be present. 2899 SDValue LHSShift; // The shift. 2900 SDValue LHSMask; // AND value if any. 2901 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 2902 return 0; // Not part of a rotate. 2903 2904 SDValue RHSShift; // The shift. 2905 SDValue RHSMask; // AND value if any. 2906 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 2907 return 0; // Not part of a rotate. 2908 2909 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 2910 return 0; // Not shifting the same value. 2911 2912 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 2913 return 0; // Shifts must disagree. 2914 2915 // Canonicalize shl to left side in a shl/srl pair. 2916 if (RHSShift.getOpcode() == ISD::SHL) { 2917 std::swap(LHS, RHS); 2918 std::swap(LHSShift, RHSShift); 2919 std::swap(LHSMask , RHSMask ); 2920 } 2921 2922 unsigned OpSizeInBits = VT.getSizeInBits(); 2923 SDValue LHSShiftArg = LHSShift.getOperand(0); 2924 SDValue LHSShiftAmt = LHSShift.getOperand(1); 2925 SDValue RHSShiftAmt = RHSShift.getOperand(1); 2926 2927 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 2928 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 2929 if (LHSShiftAmt.getOpcode() == ISD::Constant && 2930 RHSShiftAmt.getOpcode() == ISD::Constant) { 2931 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue(); 2932 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue(); 2933 if ((LShVal + RShVal) != OpSizeInBits) 2934 return 0; 2935 2936 SDValue Rot; 2937 if (HasROTL) 2938 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt); 2939 else 2940 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt); 2941 2942 // If there is an AND of either shifted operand, apply it to the result. 2943 if (LHSMask.getNode() || RHSMask.getNode()) { 2944 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 2945 2946 if (LHSMask.getNode()) { 2947 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 2948 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 2949 } 2950 if (RHSMask.getNode()) { 2951 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 2952 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 2953 } 2954 2955 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT)); 2956 } 2957 2958 return Rot.getNode(); 2959 } 2960 2961 // If there is a mask here, and we have a variable shift, we can't be sure 2962 // that we're masking out the right stuff. 2963 if (LHSMask.getNode() || RHSMask.getNode()) 2964 return 0; 2965 2966 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 2967 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 2968 if (RHSShiftAmt.getOpcode() == ISD::SUB && 2969 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 2970 if (ConstantSDNode *SUBC = 2971 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 2972 if (SUBC->getAPIntValue() == OpSizeInBits) { 2973 if (HasROTL) 2974 return DAG.getNode(ISD::ROTL, DL, VT, 2975 LHSShiftArg, LHSShiftAmt).getNode(); 2976 else 2977 return DAG.getNode(ISD::ROTR, DL, VT, 2978 LHSShiftArg, RHSShiftAmt).getNode(); 2979 } 2980 } 2981 } 2982 2983 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 2984 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 2985 if (LHSShiftAmt.getOpcode() == ISD::SUB && 2986 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 2987 if (ConstantSDNode *SUBC = 2988 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 2989 if (SUBC->getAPIntValue() == OpSizeInBits) { 2990 if (HasROTR) 2991 return DAG.getNode(ISD::ROTR, DL, VT, 2992 LHSShiftArg, RHSShiftAmt).getNode(); 2993 else 2994 return DAG.getNode(ISD::ROTL, DL, VT, 2995 LHSShiftArg, LHSShiftAmt).getNode(); 2996 } 2997 } 2998 } 2999 3000 // Look for sign/zext/any-extended or truncate cases: 3001 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 3002 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 3003 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 3004 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && 3005 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 3006 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 3007 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 3008 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { 3009 SDValue LExtOp0 = LHSShiftAmt.getOperand(0); 3010 SDValue RExtOp0 = RHSShiftAmt.getOperand(0); 3011 if (RExtOp0.getOpcode() == ISD::SUB && 3012 RExtOp0.getOperand(1) == LExtOp0) { 3013 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 3014 // (rotl x, y) 3015 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 3016 // (rotr x, (sub 32, y)) 3017 if (ConstantSDNode *SUBC = 3018 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 3019 if (SUBC->getAPIntValue() == OpSizeInBits) { 3020 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 3021 LHSShiftArg, 3022 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 3023 } 3024 } 3025 } else if (LExtOp0.getOpcode() == ISD::SUB && 3026 RExtOp0 == LExtOp0.getOperand(1)) { 3027 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 3028 // (rotr x, y) 3029 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 3030 // (rotl x, (sub 32, y)) 3031 if (ConstantSDNode *SUBC = 3032 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 3033 if (SUBC->getAPIntValue() == OpSizeInBits) { 3034 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, 3035 LHSShiftArg, 3036 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 3037 } 3038 } 3039 } 3040 } 3041 3042 return 0; 3043} 3044 3045SDValue DAGCombiner::visitXOR(SDNode *N) { 3046 SDValue N0 = N->getOperand(0); 3047 SDValue N1 = N->getOperand(1); 3048 SDValue LHS, RHS, CC; 3049 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3050 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3051 EVT VT = N0.getValueType(); 3052 3053 // fold vector ops 3054 if (VT.isVector()) { 3055 SDValue FoldedVOp = SimplifyVBinOp(N); 3056 if (FoldedVOp.getNode()) return FoldedVOp; 3057 } 3058 3059 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 3060 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 3061 return DAG.getConstant(0, VT); 3062 // fold (xor x, undef) -> undef 3063 if (N0.getOpcode() == ISD::UNDEF) 3064 return N0; 3065 if (N1.getOpcode() == ISD::UNDEF) 3066 return N1; 3067 // fold (xor c1, c2) -> c1^c2 3068 if (N0C && N1C) 3069 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); 3070 // canonicalize constant to RHS 3071 if (N0C && !N1C) 3072 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 3073 // fold (xor x, 0) -> x 3074 if (N1C && N1C->isNullValue()) 3075 return N0; 3076 // reassociate xor 3077 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1); 3078 if (RXOR.getNode() != 0) 3079 return RXOR; 3080 3081 // fold !(x cc y) -> (x !cc y) 3082 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 3083 bool isInt = LHS.getValueType().isInteger(); 3084 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 3085 isInt); 3086 3087 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) { 3088 switch (N0.getOpcode()) { 3089 default: 3090 llvm_unreachable("Unhandled SetCC Equivalent!"); 3091 case ISD::SETCC: 3092 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC); 3093 case ISD::SELECT_CC: 3094 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2), 3095 N0.getOperand(3), NotCC); 3096 } 3097 } 3098 } 3099 3100 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 3101 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 3102 N0.getNode()->hasOneUse() && 3103 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 3104 SDValue V = N0.getOperand(0); 3105 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V, 3106 DAG.getConstant(1, V.getValueType())); 3107 AddToWorkList(V.getNode()); 3108 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V); 3109 } 3110 3111 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc 3112 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 3113 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 3114 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 3115 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 3116 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 3117 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 3118 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 3119 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 3120 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 3121 } 3122 } 3123 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants 3124 if (N1C && N1C->isAllOnesValue() && 3125 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 3126 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 3127 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 3128 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 3129 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 3130 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 3131 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 3132 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 3133 } 3134 } 3135 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2)) 3136 if (N1C && N0.getOpcode() == ISD::XOR) { 3137 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 3138 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 3139 if (N00C) 3140 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1), 3141 DAG.getConstant(N1C->getAPIntValue() ^ 3142 N00C->getAPIntValue(), VT)); 3143 if (N01C) 3144 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0), 3145 DAG.getConstant(N1C->getAPIntValue() ^ 3146 N01C->getAPIntValue(), VT)); 3147 } 3148 // fold (xor x, x) -> 0 3149 if (N0 == N1) 3150 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations); 3151 3152 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 3153 if (N0.getOpcode() == N1.getOpcode()) { 3154 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 3155 if (Tmp.getNode()) return Tmp; 3156 } 3157 3158 // Simplify the expression using non-local knowledge. 3159 if (!VT.isVector() && 3160 SimplifyDemandedBits(SDValue(N, 0))) 3161 return SDValue(N, 0); 3162 3163 return SDValue(); 3164} 3165 3166/// visitShiftByConstant - Handle transforms common to the three shifts, when 3167/// the shift amount is a constant. 3168SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 3169 SDNode *LHS = N->getOperand(0).getNode(); 3170 if (!LHS->hasOneUse()) return SDValue(); 3171 3172 // We want to pull some binops through shifts, so that we have (and (shift)) 3173 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 3174 // thing happens with address calculations, so it's important to canonicalize 3175 // it. 3176 bool HighBitSet = false; // Can we transform this if the high bit is set? 3177 3178 switch (LHS->getOpcode()) { 3179 default: return SDValue(); 3180 case ISD::OR: 3181 case ISD::XOR: 3182 HighBitSet = false; // We can only transform sra if the high bit is clear. 3183 break; 3184 case ISD::AND: 3185 HighBitSet = true; // We can only transform sra if the high bit is set. 3186 break; 3187 case ISD::ADD: 3188 if (N->getOpcode() != ISD::SHL) 3189 return SDValue(); // only shl(add) not sr[al](add). 3190 HighBitSet = false; // We can only transform sra if the high bit is clear. 3191 break; 3192 } 3193 3194 // We require the RHS of the binop to be a constant as well. 3195 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 3196 if (!BinOpCst) return SDValue(); 3197 3198 // FIXME: disable this unless the input to the binop is a shift by a constant. 3199 // If it is not a shift, it pessimizes some common cases like: 3200 // 3201 // void foo(int *X, int i) { X[i & 1235] = 1; } 3202 // int bar(int *X, int i) { return X[i & 255]; } 3203 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); 3204 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 3205 BinOpLHSVal->getOpcode() != ISD::SRA && 3206 BinOpLHSVal->getOpcode() != ISD::SRL) || 3207 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 3208 return SDValue(); 3209 3210 EVT VT = N->getValueType(0); 3211 3212 // If this is a signed shift right, and the high bit is modified by the 3213 // logical operation, do not perform the transformation. The highBitSet 3214 // boolean indicates the value of the high bit of the constant which would 3215 // cause it to be modified for this operation. 3216 if (N->getOpcode() == ISD::SRA) { 3217 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 3218 if (BinOpRHSSignSet != HighBitSet) 3219 return SDValue(); 3220 } 3221 3222 // Fold the constants, shifting the binop RHS by the shift amount. 3223 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(), 3224 N->getValueType(0), 3225 LHS->getOperand(1), N->getOperand(1)); 3226 3227 // Create the new shift. 3228 SDValue NewShift = DAG.getNode(N->getOpcode(), 3229 LHS->getOperand(0).getDebugLoc(), 3230 VT, LHS->getOperand(0), N->getOperand(1)); 3231 3232 // Create the new binop. 3233 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS); 3234} 3235 3236SDValue DAGCombiner::visitSHL(SDNode *N) { 3237 SDValue N0 = N->getOperand(0); 3238 SDValue N1 = N->getOperand(1); 3239 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3240 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3241 EVT VT = N0.getValueType(); 3242 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3243 3244 // fold (shl c1, c2) -> c1<<c2 3245 if (N0C && N1C) 3246 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C); 3247 // fold (shl 0, x) -> 0 3248 if (N0C && N0C->isNullValue()) 3249 return N0; 3250 // fold (shl x, c >= size(x)) -> undef 3251 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3252 return DAG.getUNDEF(VT); 3253 // fold (shl x, 0) -> x 3254 if (N1C && N1C->isNullValue()) 3255 return N0; 3256 // fold (shl undef, x) -> 0 3257 if (N0.getOpcode() == ISD::UNDEF) 3258 return DAG.getConstant(0, VT); 3259 // if (shl x, c) is known to be zero, return 0 3260 if (DAG.MaskedValueIsZero(SDValue(N, 0), 3261 APInt::getAllOnesValue(OpSizeInBits))) 3262 return DAG.getConstant(0, VT); 3263 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))). 3264 if (N1.getOpcode() == ISD::TRUNCATE && 3265 N1.getOperand(0).getOpcode() == ISD::AND && 3266 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3267 SDValue N101 = N1.getOperand(0).getOperand(1); 3268 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3269 EVT TruncVT = N1.getValueType(); 3270 SDValue N100 = N1.getOperand(0).getOperand(0); 3271 APInt TruncC = N101C->getAPIntValue(); 3272 TruncC = TruncC.trunc(TruncVT.getSizeInBits()); 3273 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 3274 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT, 3275 DAG.getNode(ISD::TRUNCATE, 3276 N->getDebugLoc(), 3277 TruncVT, N100), 3278 DAG.getConstant(TruncC, TruncVT))); 3279 } 3280 } 3281 3282 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3283 return SDValue(N, 0); 3284 3285 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2)) 3286 if (N1C && N0.getOpcode() == ISD::SHL && 3287 N0.getOperand(1).getOpcode() == ISD::Constant) { 3288 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3289 uint64_t c2 = N1C->getZExtValue(); 3290 if (c1 + c2 >= OpSizeInBits) 3291 return DAG.getConstant(0, VT); 3292 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 3293 DAG.getConstant(c1 + c2, N1.getValueType())); 3294 } 3295 3296 // fold (shl (ext (shl x, c1)), c2) -> (ext (shl x, (add c1, c2))) 3297 // For this to be valid, the second form must not preserve any of the bits 3298 // that are shifted out by the inner shift in the first form. This means 3299 // the outer shift size must be >= the number of bits added by the ext. 3300 // As a corollary, we don't care what kind of ext it is. 3301 if (N1C && (N0.getOpcode() == ISD::ZERO_EXTEND || 3302 N0.getOpcode() == ISD::ANY_EXTEND || 3303 N0.getOpcode() == ISD::SIGN_EXTEND) && 3304 N0.getOperand(0).getOpcode() == ISD::SHL && 3305 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) { 3306 uint64_t c1 = 3307 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue(); 3308 uint64_t c2 = N1C->getZExtValue(); 3309 EVT InnerShiftVT = N0.getOperand(0).getValueType(); 3310 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits(); 3311 if (c2 >= OpSizeInBits - InnerShiftSize) { 3312 if (c1 + c2 >= OpSizeInBits) 3313 return DAG.getConstant(0, VT); 3314 return DAG.getNode(ISD::SHL, N0->getDebugLoc(), VT, 3315 DAG.getNode(N0.getOpcode(), N0->getDebugLoc(), VT, 3316 N0.getOperand(0)->getOperand(0)), 3317 DAG.getConstant(c1 + c2, N1.getValueType())); 3318 } 3319 } 3320 3321 // fold (shl (srl x, c1), c2) -> (and (shl x, (sub c2, c1), MASK) or 3322 // (and (srl x, (sub c1, c2), MASK) 3323 if (N1C && N0.getOpcode() == ISD::SRL && 3324 N0.getOperand(1).getOpcode() == ISD::Constant) { 3325 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3326 if (c1 < VT.getSizeInBits()) { 3327 uint64_t c2 = N1C->getZExtValue(); 3328 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(), 3329 VT.getSizeInBits() - c1); 3330 SDValue Shift; 3331 if (c2 > c1) { 3332 Mask = Mask.shl(c2-c1); 3333 Shift = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 3334 DAG.getConstant(c2-c1, N1.getValueType())); 3335 } else { 3336 Mask = Mask.lshr(c1-c2); 3337 Shift = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 3338 DAG.getConstant(c1-c2, N1.getValueType())); 3339 } 3340 return DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, Shift, 3341 DAG.getConstant(Mask, VT)); 3342 } 3343 } 3344 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1)) 3345 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) { 3346 SDValue HiBitsMask = 3347 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 3348 VT.getSizeInBits() - 3349 N1C->getZExtValue()), 3350 VT); 3351 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 3352 HiBitsMask); 3353 } 3354 3355 if (N1C) { 3356 SDValue NewSHL = visitShiftByConstant(N, N1C->getZExtValue()); 3357 if (NewSHL.getNode()) 3358 return NewSHL; 3359 } 3360 3361 return SDValue(); 3362} 3363 3364SDValue DAGCombiner::visitSRA(SDNode *N) { 3365 SDValue N0 = N->getOperand(0); 3366 SDValue N1 = N->getOperand(1); 3367 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3368 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3369 EVT VT = N0.getValueType(); 3370 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3371 3372 // fold (sra c1, c2) -> (sra c1, c2) 3373 if (N0C && N1C) 3374 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); 3375 // fold (sra 0, x) -> 0 3376 if (N0C && N0C->isNullValue()) 3377 return N0; 3378 // fold (sra -1, x) -> -1 3379 if (N0C && N0C->isAllOnesValue()) 3380 return N0; 3381 // fold (sra x, (setge c, size(x))) -> undef 3382 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3383 return DAG.getUNDEF(VT); 3384 // fold (sra x, 0) -> x 3385 if (N1C && N1C->isNullValue()) 3386 return N0; 3387 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 3388 // sext_inreg. 3389 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 3390 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue(); 3391 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits); 3392 if (VT.isVector()) 3393 ExtVT = EVT::getVectorVT(*DAG.getContext(), 3394 ExtVT, VT.getVectorNumElements()); 3395 if ((!LegalOperations || 3396 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT))) 3397 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 3398 N0.getOperand(0), DAG.getValueType(ExtVT)); 3399 } 3400 3401 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) 3402 if (N1C && N0.getOpcode() == ISD::SRA) { 3403 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3404 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); 3405 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1; 3406 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0), 3407 DAG.getConstant(Sum, N1C->getValueType(0))); 3408 } 3409 } 3410 3411 // fold (sra (shl X, m), (sub result_size, n)) 3412 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for 3413 // result_size - n != m. 3414 // If truncate is free for the target sext(shl) is likely to result in better 3415 // code. 3416 if (N0.getOpcode() == ISD::SHL) { 3417 // Get the two constanst of the shifts, CN0 = m, CN = n. 3418 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 3419 if (N01C && N1C) { 3420 // Determine what the truncate's result bitsize and type would be. 3421 EVT TruncVT = 3422 EVT::getIntegerVT(*DAG.getContext(), 3423 OpSizeInBits - N1C->getZExtValue()); 3424 // Determine the residual right-shift amount. 3425 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); 3426 3427 // If the shift is not a no-op (in which case this should be just a sign 3428 // extend already), the truncated to type is legal, sign_extend is legal 3429 // on that type, and the truncate to that type is both legal and free, 3430 // perform the transform. 3431 if ((ShiftAmt > 0) && 3432 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) && 3433 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) && 3434 TLI.isTruncateFree(VT, TruncVT)) { 3435 3436 SDValue Amt = DAG.getConstant(ShiftAmt, 3437 getShiftAmountTy(N0.getOperand(0).getValueType())); 3438 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, 3439 N0.getOperand(0), Amt); 3440 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT, 3441 Shift); 3442 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), 3443 N->getValueType(0), Trunc); 3444 } 3445 } 3446 } 3447 3448 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))). 3449 if (N1.getOpcode() == ISD::TRUNCATE && 3450 N1.getOperand(0).getOpcode() == ISD::AND && 3451 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3452 SDValue N101 = N1.getOperand(0).getOperand(1); 3453 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3454 EVT TruncVT = N1.getValueType(); 3455 SDValue N100 = N1.getOperand(0).getOperand(0); 3456 APInt TruncC = N101C->getAPIntValue(); 3457 TruncC = TruncC.trunc(TruncVT.getScalarType().getSizeInBits()); 3458 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 3459 DAG.getNode(ISD::AND, N->getDebugLoc(), 3460 TruncVT, 3461 DAG.getNode(ISD::TRUNCATE, 3462 N->getDebugLoc(), 3463 TruncVT, N100), 3464 DAG.getConstant(TruncC, TruncVT))); 3465 } 3466 } 3467 3468 // fold (sra (trunc (sr x, c1)), c2) -> (trunc (sra x, c1+c2)) 3469 // if c1 is equal to the number of bits the trunc removes 3470 if (N0.getOpcode() == ISD::TRUNCATE && 3471 (N0.getOperand(0).getOpcode() == ISD::SRL || 3472 N0.getOperand(0).getOpcode() == ISD::SRA) && 3473 N0.getOperand(0).hasOneUse() && 3474 N0.getOperand(0).getOperand(1).hasOneUse() && 3475 N1C && isa<ConstantSDNode>(N0.getOperand(0).getOperand(1))) { 3476 EVT LargeVT = N0.getOperand(0).getValueType(); 3477 ConstantSDNode *LargeShiftAmt = 3478 cast<ConstantSDNode>(N0.getOperand(0).getOperand(1)); 3479 3480 if (LargeVT.getScalarType().getSizeInBits() - OpSizeInBits == 3481 LargeShiftAmt->getZExtValue()) { 3482 SDValue Amt = 3483 DAG.getConstant(LargeShiftAmt->getZExtValue() + N1C->getZExtValue(), 3484 getShiftAmountTy(N0.getOperand(0).getOperand(0).getValueType())); 3485 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), LargeVT, 3486 N0.getOperand(0).getOperand(0), Amt); 3487 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, SRA); 3488 } 3489 } 3490 3491 // Simplify, based on bits shifted out of the LHS. 3492 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3493 return SDValue(N, 0); 3494 3495 3496 // If the sign bit is known to be zero, switch this to a SRL. 3497 if (DAG.SignBitIsZero(N0)) 3498 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1); 3499 3500 if (N1C) { 3501 SDValue NewSRA = visitShiftByConstant(N, N1C->getZExtValue()); 3502 if (NewSRA.getNode()) 3503 return NewSRA; 3504 } 3505 3506 return SDValue(); 3507} 3508 3509SDValue DAGCombiner::visitSRL(SDNode *N) { 3510 SDValue N0 = N->getOperand(0); 3511 SDValue N1 = N->getOperand(1); 3512 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3513 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3514 EVT VT = N0.getValueType(); 3515 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3516 3517 // fold (srl c1, c2) -> c1 >>u c2 3518 if (N0C && N1C) 3519 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); 3520 // fold (srl 0, x) -> 0 3521 if (N0C && N0C->isNullValue()) 3522 return N0; 3523 // fold (srl x, c >= size(x)) -> undef 3524 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3525 return DAG.getUNDEF(VT); 3526 // fold (srl x, 0) -> x 3527 if (N1C && N1C->isNullValue()) 3528 return N0; 3529 // if (srl x, c) is known to be zero, return 0 3530 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 3531 APInt::getAllOnesValue(OpSizeInBits))) 3532 return DAG.getConstant(0, VT); 3533 3534 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2)) 3535 if (N1C && N0.getOpcode() == ISD::SRL && 3536 N0.getOperand(1).getOpcode() == ISD::Constant) { 3537 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3538 uint64_t c2 = N1C->getZExtValue(); 3539 if (c1 + c2 >= OpSizeInBits) 3540 return DAG.getConstant(0, VT); 3541 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 3542 DAG.getConstant(c1 + c2, N1.getValueType())); 3543 } 3544 3545 // fold (srl (trunc (srl x, c1)), c2) -> 0 or (trunc (srl x, (add c1, c2))) 3546 if (N1C && N0.getOpcode() == ISD::TRUNCATE && 3547 N0.getOperand(0).getOpcode() == ISD::SRL && 3548 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) { 3549 uint64_t c1 = 3550 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue(); 3551 uint64_t c2 = N1C->getZExtValue(); 3552 EVT InnerShiftVT = N0.getOperand(0).getValueType(); 3553 EVT ShiftCountVT = N0.getOperand(0)->getOperand(1).getValueType(); 3554 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits(); 3555 // This is only valid if the OpSizeInBits + c1 = size of inner shift. 3556 if (c1 + OpSizeInBits == InnerShiftSize) { 3557 if (c1 + c2 >= InnerShiftSize) 3558 return DAG.getConstant(0, VT); 3559 return DAG.getNode(ISD::TRUNCATE, N0->getDebugLoc(), VT, 3560 DAG.getNode(ISD::SRL, N0->getDebugLoc(), InnerShiftVT, 3561 N0.getOperand(0)->getOperand(0), 3562 DAG.getConstant(c1 + c2, ShiftCountVT))); 3563 } 3564 } 3565 3566 // fold (srl (shl x, c), c) -> (and x, cst2) 3567 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 && 3568 N0.getValueSizeInBits() <= 64) { 3569 uint64_t ShAmt = N1C->getZExtValue()+64-N0.getValueSizeInBits(); 3570 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 3571 DAG.getConstant(~0ULL >> ShAmt, VT)); 3572 } 3573 3574 3575 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 3576 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 3577 // Shifting in all undef bits? 3578 EVT SmallVT = N0.getOperand(0).getValueType(); 3579 if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) 3580 return DAG.getUNDEF(VT); 3581 3582 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) { 3583 uint64_t ShiftAmt = N1C->getZExtValue(); 3584 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT, 3585 N0.getOperand(0), 3586 DAG.getConstant(ShiftAmt, getShiftAmountTy(SmallVT))); 3587 AddToWorkList(SmallShift.getNode()); 3588 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift); 3589 } 3590 } 3591 3592 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 3593 // bit, which is unmodified by sra. 3594 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) { 3595 if (N0.getOpcode() == ISD::SRA) 3596 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1); 3597 } 3598 3599 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 3600 if (N1C && N0.getOpcode() == ISD::CTLZ && 3601 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 3602 APInt KnownZero, KnownOne; 3603 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 3604 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 3605 3606 // If any of the input bits are KnownOne, then the input couldn't be all 3607 // zeros, thus the result of the srl will always be zero. 3608 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 3609 3610 // If all of the bits input the to ctlz node are known to be zero, then 3611 // the result of the ctlz is "32" and the result of the shift is one. 3612 APInt UnknownBits = ~KnownZero & Mask; 3613 if (UnknownBits == 0) return DAG.getConstant(1, VT); 3614 3615 // Otherwise, check to see if there is exactly one bit input to the ctlz. 3616 if ((UnknownBits & (UnknownBits - 1)) == 0) { 3617 // Okay, we know that only that the single bit specified by UnknownBits 3618 // could be set on input to the CTLZ node. If this bit is set, the SRL 3619 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 3620 // to an SRL/XOR pair, which is likely to simplify more. 3621 unsigned ShAmt = UnknownBits.countTrailingZeros(); 3622 SDValue Op = N0.getOperand(0); 3623 3624 if (ShAmt) { 3625 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op, 3626 DAG.getConstant(ShAmt, getShiftAmountTy(Op.getValueType()))); 3627 AddToWorkList(Op.getNode()); 3628 } 3629 3630 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 3631 Op, DAG.getConstant(1, VT)); 3632 } 3633 } 3634 3635 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))). 3636 if (N1.getOpcode() == ISD::TRUNCATE && 3637 N1.getOperand(0).getOpcode() == ISD::AND && 3638 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3639 SDValue N101 = N1.getOperand(0).getOperand(1); 3640 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3641 EVT TruncVT = N1.getValueType(); 3642 SDValue N100 = N1.getOperand(0).getOperand(0); 3643 APInt TruncC = N101C->getAPIntValue(); 3644 TruncC = TruncC.trunc(TruncVT.getSizeInBits()); 3645 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 3646 DAG.getNode(ISD::AND, N->getDebugLoc(), 3647 TruncVT, 3648 DAG.getNode(ISD::TRUNCATE, 3649 N->getDebugLoc(), 3650 TruncVT, N100), 3651 DAG.getConstant(TruncC, TruncVT))); 3652 } 3653 } 3654 3655 // fold operands of srl based on knowledge that the low bits are not 3656 // demanded. 3657 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3658 return SDValue(N, 0); 3659 3660 if (N1C) { 3661 SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue()); 3662 if (NewSRL.getNode()) 3663 return NewSRL; 3664 } 3665 3666 // Attempt to convert a srl of a load into a narrower zero-extending load. 3667 SDValue NarrowLoad = ReduceLoadWidth(N); 3668 if (NarrowLoad.getNode()) 3669 return NarrowLoad; 3670 3671 // Here is a common situation. We want to optimize: 3672 // 3673 // %a = ... 3674 // %b = and i32 %a, 2 3675 // %c = srl i32 %b, 1 3676 // brcond i32 %c ... 3677 // 3678 // into 3679 // 3680 // %a = ... 3681 // %b = and %a, 2 3682 // %c = setcc eq %b, 0 3683 // brcond %c ... 3684 // 3685 // However when after the source operand of SRL is optimized into AND, the SRL 3686 // itself may not be optimized further. Look for it and add the BRCOND into 3687 // the worklist. 3688 if (N->hasOneUse()) { 3689 SDNode *Use = *N->use_begin(); 3690 if (Use->getOpcode() == ISD::BRCOND) 3691 AddToWorkList(Use); 3692 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) { 3693 // Also look pass the truncate. 3694 Use = *Use->use_begin(); 3695 if (Use->getOpcode() == ISD::BRCOND) 3696 AddToWorkList(Use); 3697 } 3698 } 3699 3700 return SDValue(); 3701} 3702 3703SDValue DAGCombiner::visitCTLZ(SDNode *N) { 3704 SDValue N0 = N->getOperand(0); 3705 EVT VT = N->getValueType(0); 3706 3707 // fold (ctlz c1) -> c2 3708 if (isa<ConstantSDNode>(N0)) 3709 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0); 3710 return SDValue(); 3711} 3712 3713SDValue DAGCombiner::visitCTTZ(SDNode *N) { 3714 SDValue N0 = N->getOperand(0); 3715 EVT VT = N->getValueType(0); 3716 3717 // fold (cttz c1) -> c2 3718 if (isa<ConstantSDNode>(N0)) 3719 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0); 3720 return SDValue(); 3721} 3722 3723SDValue DAGCombiner::visitCTPOP(SDNode *N) { 3724 SDValue N0 = N->getOperand(0); 3725 EVT VT = N->getValueType(0); 3726 3727 // fold (ctpop c1) -> c2 3728 if (isa<ConstantSDNode>(N0)) 3729 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0); 3730 return SDValue(); 3731} 3732 3733SDValue DAGCombiner::visitSELECT(SDNode *N) { 3734 SDValue N0 = N->getOperand(0); 3735 SDValue N1 = N->getOperand(1); 3736 SDValue N2 = N->getOperand(2); 3737 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3738 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3739 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 3740 EVT VT = N->getValueType(0); 3741 EVT VT0 = N0.getValueType(); 3742 3743 // fold (select C, X, X) -> X 3744 if (N1 == N2) 3745 return N1; 3746 // fold (select true, X, Y) -> X 3747 if (N0C && !N0C->isNullValue()) 3748 return N1; 3749 // fold (select false, X, Y) -> Y 3750 if (N0C && N0C->isNullValue()) 3751 return N2; 3752 // fold (select C, 1, X) -> (or C, X) 3753 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 3754 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 3755 // fold (select C, 0, 1) -> (xor C, 1) 3756 if (VT.isInteger() && 3757 (VT0 == MVT::i1 || 3758 (VT0.isInteger() && 3759 TLI.getBooleanContents(false) == TargetLowering::ZeroOrOneBooleanContent)) && 3760 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 3761 SDValue XORNode; 3762 if (VT == VT0) 3763 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0, 3764 N0, DAG.getConstant(1, VT0)); 3765 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0, 3766 N0, DAG.getConstant(1, VT0)); 3767 AddToWorkList(XORNode.getNode()); 3768 if (VT.bitsGT(VT0)) 3769 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode); 3770 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode); 3771 } 3772 // fold (select C, 0, X) -> (and (not C), X) 3773 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 3774 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 3775 AddToWorkList(NOTNode.getNode()); 3776 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2); 3777 } 3778 // fold (select C, X, 1) -> (or (not C), X) 3779 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 3780 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 3781 AddToWorkList(NOTNode.getNode()); 3782 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1); 3783 } 3784 // fold (select C, X, 0) -> (and C, X) 3785 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 3786 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 3787 // fold (select X, X, Y) -> (or X, Y) 3788 // fold (select X, 1, Y) -> (or X, Y) 3789 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1))) 3790 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 3791 // fold (select X, Y, X) -> (and X, Y) 3792 // fold (select X, Y, 0) -> (and X, Y) 3793 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0))) 3794 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 3795 3796 // If we can fold this based on the true/false value, do so. 3797 if (SimplifySelectOps(N, N1, N2)) 3798 return SDValue(N, 0); // Don't revisit N. 3799 3800 // fold selects based on a setcc into other things, such as min/max/abs 3801 if (N0.getOpcode() == ISD::SETCC) { 3802 // FIXME: 3803 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 3804 // having to say they don't support SELECT_CC on every type the DAG knows 3805 // about, since there is no way to mark an opcode illegal at all value types 3806 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) && 3807 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT)) 3808 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, 3809 N0.getOperand(0), N0.getOperand(1), 3810 N1, N2, N0.getOperand(2)); 3811 return SimplifySelect(N->getDebugLoc(), N0, N1, N2); 3812 } 3813 3814 return SDValue(); 3815} 3816 3817SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 3818 SDValue N0 = N->getOperand(0); 3819 SDValue N1 = N->getOperand(1); 3820 SDValue N2 = N->getOperand(2); 3821 SDValue N3 = N->getOperand(3); 3822 SDValue N4 = N->getOperand(4); 3823 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 3824 3825 // fold select_cc lhs, rhs, x, x, cc -> x 3826 if (N2 == N3) 3827 return N2; 3828 3829 // Determine if the condition we're dealing with is constant 3830 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 3831 N0, N1, CC, N->getDebugLoc(), false); 3832 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 3833 3834 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) { 3835 if (!SCCC->isNullValue()) 3836 return N2; // cond always true -> true val 3837 else 3838 return N3; // cond always false -> false val 3839 } 3840 3841 // Fold to a simpler select_cc 3842 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) 3843 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(), 3844 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 3845 SCC.getOperand(2)); 3846 3847 // If we can fold this based on the true/false value, do so. 3848 if (SimplifySelectOps(N, N2, N3)) 3849 return SDValue(N, 0); // Don't revisit N. 3850 3851 // fold select_cc into other things, such as min/max/abs 3852 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC); 3853} 3854 3855SDValue DAGCombiner::visitSETCC(SDNode *N) { 3856 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 3857 cast<CondCodeSDNode>(N->getOperand(2))->get(), 3858 N->getDebugLoc()); 3859} 3860 3861// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 3862// "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))" 3863// transformation. Returns true if extension are possible and the above 3864// mentioned transformation is profitable. 3865static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 3866 unsigned ExtOpc, 3867 SmallVector<SDNode*, 4> &ExtendNodes, 3868 const TargetLowering &TLI) { 3869 bool HasCopyToRegUses = false; 3870 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 3871 for (SDNode::use_iterator UI = N0.getNode()->use_begin(), 3872 UE = N0.getNode()->use_end(); 3873 UI != UE; ++UI) { 3874 SDNode *User = *UI; 3875 if (User == N) 3876 continue; 3877 if (UI.getUse().getResNo() != N0.getResNo()) 3878 continue; 3879 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 3880 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { 3881 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 3882 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 3883 // Sign bits will be lost after a zext. 3884 return false; 3885 bool Add = false; 3886 for (unsigned i = 0; i != 2; ++i) { 3887 SDValue UseOp = User->getOperand(i); 3888 if (UseOp == N0) 3889 continue; 3890 if (!isa<ConstantSDNode>(UseOp)) 3891 return false; 3892 Add = true; 3893 } 3894 if (Add) 3895 ExtendNodes.push_back(User); 3896 continue; 3897 } 3898 // If truncates aren't free and there are users we can't 3899 // extend, it isn't worthwhile. 3900 if (!isTruncFree) 3901 return false; 3902 // Remember if this value is live-out. 3903 if (User->getOpcode() == ISD::CopyToReg) 3904 HasCopyToRegUses = true; 3905 } 3906 3907 if (HasCopyToRegUses) { 3908 bool BothLiveOut = false; 3909 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 3910 UI != UE; ++UI) { 3911 SDUse &Use = UI.getUse(); 3912 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) { 3913 BothLiveOut = true; 3914 break; 3915 } 3916 } 3917 if (BothLiveOut) 3918 // Both unextended and extended values are live out. There had better be 3919 // a good reason for the transformation. 3920 return ExtendNodes.size(); 3921 } 3922 return true; 3923} 3924 3925void DAGCombiner::ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs, 3926 SDValue Trunc, SDValue ExtLoad, DebugLoc DL, 3927 ISD::NodeType ExtType) { 3928 // Extend SetCC uses if necessary. 3929 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3930 SDNode *SetCC = SetCCs[i]; 3931 SmallVector<SDValue, 4> Ops; 3932 3933 for (unsigned j = 0; j != 2; ++j) { 3934 SDValue SOp = SetCC->getOperand(j); 3935 if (SOp == Trunc) 3936 Ops.push_back(ExtLoad); 3937 else 3938 Ops.push_back(DAG.getNode(ExtType, DL, ExtLoad->getValueType(0), SOp)); 3939 } 3940 3941 Ops.push_back(SetCC->getOperand(2)); 3942 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0), 3943 &Ops[0], Ops.size())); 3944 } 3945} 3946 3947SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 3948 SDValue N0 = N->getOperand(0); 3949 EVT VT = N->getValueType(0); 3950 3951 // fold (sext c1) -> c1 3952 if (isa<ConstantSDNode>(N0)) 3953 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0); 3954 3955 // fold (sext (sext x)) -> (sext x) 3956 // fold (sext (aext x)) -> (sext x) 3957 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 3958 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, 3959 N0.getOperand(0)); 3960 3961 if (N0.getOpcode() == ISD::TRUNCATE) { 3962 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 3963 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 3964 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3965 if (NarrowLoad.getNode()) { 3966 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 3967 if (NarrowLoad.getNode() != N0.getNode()) { 3968 CombineTo(N0.getNode(), NarrowLoad); 3969 // CombineTo deleted the truncate, if needed, but not what's under it. 3970 AddToWorkList(oye); 3971 } 3972 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3973 } 3974 3975 // See if the value being truncated is already sign extended. If so, just 3976 // eliminate the trunc/sext pair. 3977 SDValue Op = N0.getOperand(0); 3978 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits(); 3979 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits(); 3980 unsigned DestBits = VT.getScalarType().getSizeInBits(); 3981 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 3982 3983 if (OpBits == DestBits) { 3984 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 3985 // bits, it is already ready. 3986 if (NumSignBits > DestBits-MidBits) 3987 return Op; 3988 } else if (OpBits < DestBits) { 3989 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 3990 // bits, just sext from i32. 3991 if (NumSignBits > OpBits-MidBits) 3992 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op); 3993 } else { 3994 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 3995 // bits, just truncate to i32. 3996 if (NumSignBits > OpBits-MidBits) 3997 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 3998 } 3999 4000 // fold (sext (truncate x)) -> (sextinreg x). 4001 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 4002 N0.getValueType())) { 4003 if (OpBits < DestBits) 4004 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op); 4005 else if (OpBits > DestBits) 4006 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op); 4007 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op, 4008 DAG.getValueType(N0.getValueType())); 4009 } 4010 } 4011 4012 // fold (sext (load x)) -> (sext (truncate (sextload x))) 4013 // None of the supported targets knows how to perform load and sign extend 4014 // on vectors in one instruction. We only perform this transformation on 4015 // scalars. 4016 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4017 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4018 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { 4019 bool DoXform = true; 4020 SmallVector<SDNode*, 4> SetCCs; 4021 if (!N0.hasOneUse()) 4022 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 4023 if (DoXform) { 4024 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4025 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 4026 LN0->getChain(), 4027 LN0->getBasePtr(), LN0->getPointerInfo(), 4028 N0.getValueType(), 4029 LN0->isVolatile(), LN0->isNonTemporal(), 4030 LN0->getAlignment()); 4031 CombineTo(N, ExtLoad); 4032 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4033 N0.getValueType(), ExtLoad); 4034 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4035 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4036 ISD::SIGN_EXTEND); 4037 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4038 } 4039 } 4040 4041 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 4042 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 4043 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 4044 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 4045 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4046 EVT MemVT = LN0->getMemoryVT(); 4047 if ((!LegalOperations && !LN0->isVolatile()) || 4048 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) { 4049 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 4050 LN0->getChain(), 4051 LN0->getBasePtr(), LN0->getPointerInfo(), 4052 MemVT, 4053 LN0->isVolatile(), LN0->isNonTemporal(), 4054 LN0->getAlignment()); 4055 CombineTo(N, ExtLoad); 4056 CombineTo(N0.getNode(), 4057 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4058 N0.getValueType(), ExtLoad), 4059 ExtLoad.getValue(1)); 4060 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4061 } 4062 } 4063 4064 // fold (sext (and/or/xor (load x), cst)) -> 4065 // (and/or/xor (sextload x), (sext cst)) 4066 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR || 4067 N0.getOpcode() == ISD::XOR) && 4068 isa<LoadSDNode>(N0.getOperand(0)) && 4069 N0.getOperand(1).getOpcode() == ISD::Constant && 4070 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()) && 4071 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) { 4072 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0)); 4073 if (LN0->getExtensionType() != ISD::ZEXTLOAD) { 4074 bool DoXform = true; 4075 SmallVector<SDNode*, 4> SetCCs; 4076 if (!N0.hasOneUse()) 4077 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::SIGN_EXTEND, 4078 SetCCs, TLI); 4079 if (DoXform) { 4080 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, LN0->getDebugLoc(), VT, 4081 LN0->getChain(), LN0->getBasePtr(), 4082 LN0->getPointerInfo(), 4083 LN0->getMemoryVT(), 4084 LN0->isVolatile(), 4085 LN0->isNonTemporal(), 4086 LN0->getAlignment()); 4087 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4088 Mask = Mask.sext(VT.getSizeInBits()); 4089 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 4090 ExtLoad, DAG.getConstant(Mask, VT)); 4091 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, 4092 N0.getOperand(0).getDebugLoc(), 4093 N0.getOperand(0).getValueType(), ExtLoad); 4094 CombineTo(N, And); 4095 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1)); 4096 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4097 ISD::SIGN_EXTEND); 4098 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4099 } 4100 } 4101 } 4102 4103 if (N0.getOpcode() == ISD::SETCC) { 4104 // sext(setcc) -> sext_in_reg(vsetcc) for vectors. 4105 // Only do this before legalize for now. 4106 if (VT.isVector() && !LegalOperations) { 4107 EVT N0VT = N0.getOperand(0).getValueType(); 4108 // We know that the # elements of the results is the same as the 4109 // # elements of the compare (and the # elements of the compare result 4110 // for that matter). Check to see that they are the same size. If so, 4111 // we know that the element size of the sext'd result matches the 4112 // element size of the compare operands. 4113 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 4114 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4115 N0.getOperand(1), 4116 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4117 // If the desired elements are smaller or larger than the source 4118 // elements we can use a matching integer vector type and then 4119 // truncate/sign extend 4120 else { 4121 EVT MatchingElementType = 4122 EVT::getIntegerVT(*DAG.getContext(), 4123 N0VT.getScalarType().getSizeInBits()); 4124 EVT MatchingVectorType = 4125 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4126 N0VT.getVectorNumElements()); 4127 SDValue VsetCC = 4128 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 4129 N0.getOperand(1), 4130 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4131 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); 4132 } 4133 } 4134 4135 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc) 4136 unsigned ElementWidth = VT.getScalarType().getSizeInBits(); 4137 SDValue NegOne = 4138 DAG.getConstant(APInt::getAllOnesValue(ElementWidth), VT); 4139 SDValue SCC = 4140 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4141 NegOne, DAG.getConstant(0, VT), 4142 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4143 if (SCC.getNode()) return SCC; 4144 if (!LegalOperations || 4145 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT))) 4146 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT, 4147 DAG.getSetCC(N->getDebugLoc(), 4148 TLI.getSetCCResultType(VT), 4149 N0.getOperand(0), N0.getOperand(1), 4150 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 4151 NegOne, DAG.getConstant(0, VT)); 4152 } 4153 4154 // fold (sext x) -> (zext x) if the sign bit is known zero. 4155 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 4156 DAG.SignBitIsZero(N0)) 4157 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 4158 4159 return SDValue(); 4160} 4161 4162SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 4163 SDValue N0 = N->getOperand(0); 4164 EVT VT = N->getValueType(0); 4165 4166 // fold (zext c1) -> c1 4167 if (isa<ConstantSDNode>(N0)) 4168 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 4169 // fold (zext (zext x)) -> (zext x) 4170 // fold (zext (aext x)) -> (zext x) 4171 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 4172 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, 4173 N0.getOperand(0)); 4174 4175 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 4176 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 4177 if (N0.getOpcode() == ISD::TRUNCATE) { 4178 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4179 if (NarrowLoad.getNode()) { 4180 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4181 if (NarrowLoad.getNode() != N0.getNode()) { 4182 CombineTo(N0.getNode(), NarrowLoad); 4183 // CombineTo deleted the truncate, if needed, but not what's under it. 4184 AddToWorkList(oye); 4185 } 4186 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4187 } 4188 } 4189 4190 // fold (zext (truncate x)) -> (and x, mask) 4191 if (N0.getOpcode() == ISD::TRUNCATE && 4192 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) { 4193 4194 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 4195 // fold (zext (truncate (srl (load x), c))) -> (zext (smaller load (x+c/n))) 4196 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4197 if (NarrowLoad.getNode()) { 4198 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4199 if (NarrowLoad.getNode() != N0.getNode()) { 4200 CombineTo(N0.getNode(), NarrowLoad); 4201 // CombineTo deleted the truncate, if needed, but not what's under it. 4202 AddToWorkList(oye); 4203 } 4204 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4205 } 4206 4207 SDValue Op = N0.getOperand(0); 4208 if (Op.getValueType().bitsLT(VT)) { 4209 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op); 4210 } else if (Op.getValueType().bitsGT(VT)) { 4211 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 4212 } 4213 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), 4214 N0.getValueType().getScalarType()); 4215 } 4216 4217 // Fold (zext (and (trunc x), cst)) -> (and x, cst), 4218 // if either of the casts is not free. 4219 if (N0.getOpcode() == ISD::AND && 4220 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 4221 N0.getOperand(1).getOpcode() == ISD::Constant && 4222 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 4223 N0.getValueType()) || 4224 !TLI.isZExtFree(N0.getValueType(), VT))) { 4225 SDValue X = N0.getOperand(0).getOperand(0); 4226 if (X.getValueType().bitsLT(VT)) { 4227 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X); 4228 } else if (X.getValueType().bitsGT(VT)) { 4229 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 4230 } 4231 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4232 Mask = Mask.zext(VT.getSizeInBits()); 4233 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4234 X, DAG.getConstant(Mask, VT)); 4235 } 4236 4237 // fold (zext (load x)) -> (zext (truncate (zextload x))) 4238 // None of the supported targets knows how to perform load and vector_zext 4239 // on vectors in one instruction. We only perform this transformation on 4240 // scalars. 4241 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4242 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4243 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 4244 bool DoXform = true; 4245 SmallVector<SDNode*, 4> SetCCs; 4246 if (!N0.hasOneUse()) 4247 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 4248 if (DoXform) { 4249 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4250 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 4251 LN0->getChain(), 4252 LN0->getBasePtr(), LN0->getPointerInfo(), 4253 N0.getValueType(), 4254 LN0->isVolatile(), LN0->isNonTemporal(), 4255 LN0->getAlignment()); 4256 CombineTo(N, ExtLoad); 4257 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4258 N0.getValueType(), ExtLoad); 4259 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4260 4261 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4262 ISD::ZERO_EXTEND); 4263 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4264 } 4265 } 4266 4267 // fold (zext (and/or/xor (load x), cst)) -> 4268 // (and/or/xor (zextload x), (zext cst)) 4269 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR || 4270 N0.getOpcode() == ISD::XOR) && 4271 isa<LoadSDNode>(N0.getOperand(0)) && 4272 N0.getOperand(1).getOpcode() == ISD::Constant && 4273 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()) && 4274 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) { 4275 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0)); 4276 if (LN0->getExtensionType() != ISD::SEXTLOAD) { 4277 bool DoXform = true; 4278 SmallVector<SDNode*, 4> SetCCs; 4279 if (!N0.hasOneUse()) 4280 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::ZERO_EXTEND, 4281 SetCCs, TLI); 4282 if (DoXform) { 4283 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), VT, 4284 LN0->getChain(), LN0->getBasePtr(), 4285 LN0->getPointerInfo(), 4286 LN0->getMemoryVT(), 4287 LN0->isVolatile(), 4288 LN0->isNonTemporal(), 4289 LN0->getAlignment()); 4290 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4291 Mask = Mask.zext(VT.getSizeInBits()); 4292 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 4293 ExtLoad, DAG.getConstant(Mask, VT)); 4294 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, 4295 N0.getOperand(0).getDebugLoc(), 4296 N0.getOperand(0).getValueType(), ExtLoad); 4297 CombineTo(N, And); 4298 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1)); 4299 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4300 ISD::ZERO_EXTEND); 4301 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4302 } 4303 } 4304 } 4305 4306 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 4307 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 4308 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 4309 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 4310 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4311 EVT MemVT = LN0->getMemoryVT(); 4312 if ((!LegalOperations && !LN0->isVolatile()) || 4313 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) { 4314 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 4315 LN0->getChain(), 4316 LN0->getBasePtr(), LN0->getPointerInfo(), 4317 MemVT, 4318 LN0->isVolatile(), LN0->isNonTemporal(), 4319 LN0->getAlignment()); 4320 CombineTo(N, ExtLoad); 4321 CombineTo(N0.getNode(), 4322 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(), 4323 ExtLoad), 4324 ExtLoad.getValue(1)); 4325 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4326 } 4327 } 4328 4329 if (N0.getOpcode() == ISD::SETCC) { 4330 if (!LegalOperations && VT.isVector()) { 4331 // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors. 4332 // Only do this before legalize for now. 4333 EVT N0VT = N0.getOperand(0).getValueType(); 4334 EVT EltVT = VT.getVectorElementType(); 4335 SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(), 4336 DAG.getConstant(1, EltVT)); 4337 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 4338 // We know that the # elements of the results is the same as the 4339 // # elements of the compare (and the # elements of the compare result 4340 // for that matter). Check to see that they are the same size. If so, 4341 // we know that the element size of the sext'd result matches the 4342 // element size of the compare operands. 4343 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4344 DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4345 N0.getOperand(1), 4346 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 4347 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 4348 &OneOps[0], OneOps.size())); 4349 4350 // If the desired elements are smaller or larger than the source 4351 // elements we can use a matching integer vector type and then 4352 // truncate/sign extend 4353 EVT MatchingElementType = 4354 EVT::getIntegerVT(*DAG.getContext(), 4355 N0VT.getScalarType().getSizeInBits()); 4356 EVT MatchingVectorType = 4357 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4358 N0VT.getVectorNumElements()); 4359 SDValue VsetCC = 4360 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 4361 N0.getOperand(1), 4362 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4363 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4364 DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT), 4365 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 4366 &OneOps[0], OneOps.size())); 4367 } 4368 4369 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 4370 SDValue SCC = 4371 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4372 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 4373 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4374 if (SCC.getNode()) return SCC; 4375 } 4376 4377 // (zext (shl (zext x), cst)) -> (shl (zext x), cst) 4378 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && 4379 isa<ConstantSDNode>(N0.getOperand(1)) && 4380 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && 4381 N0.hasOneUse()) { 4382 SDValue ShAmt = N0.getOperand(1); 4383 unsigned ShAmtVal = cast<ConstantSDNode>(ShAmt)->getZExtValue(); 4384 if (N0.getOpcode() == ISD::SHL) { 4385 SDValue InnerZExt = N0.getOperand(0); 4386 // If the original shl may be shifting out bits, do not perform this 4387 // transformation. 4388 unsigned KnownZeroBits = InnerZExt.getValueType().getSizeInBits() - 4389 InnerZExt.getOperand(0).getValueType().getSizeInBits(); 4390 if (ShAmtVal > KnownZeroBits) 4391 return SDValue(); 4392 } 4393 4394 DebugLoc DL = N->getDebugLoc(); 4395 4396 // Ensure that the shift amount is wide enough for the shifted value. 4397 if (VT.getSizeInBits() >= 256) 4398 ShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, ShAmt); 4399 4400 return DAG.getNode(N0.getOpcode(), DL, VT, 4401 DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)), 4402 ShAmt); 4403 } 4404 4405 return SDValue(); 4406} 4407 4408SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 4409 SDValue N0 = N->getOperand(0); 4410 EVT VT = N->getValueType(0); 4411 4412 // fold (aext c1) -> c1 4413 if (isa<ConstantSDNode>(N0)) 4414 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0); 4415 // fold (aext (aext x)) -> (aext x) 4416 // fold (aext (zext x)) -> (zext x) 4417 // fold (aext (sext x)) -> (sext x) 4418 if (N0.getOpcode() == ISD::ANY_EXTEND || 4419 N0.getOpcode() == ISD::ZERO_EXTEND || 4420 N0.getOpcode() == ISD::SIGN_EXTEND) 4421 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0)); 4422 4423 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 4424 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 4425 if (N0.getOpcode() == ISD::TRUNCATE) { 4426 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4427 if (NarrowLoad.getNode()) { 4428 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4429 if (NarrowLoad.getNode() != N0.getNode()) { 4430 CombineTo(N0.getNode(), NarrowLoad); 4431 // CombineTo deleted the truncate, if needed, but not what's under it. 4432 AddToWorkList(oye); 4433 } 4434 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4435 } 4436 } 4437 4438 // fold (aext (truncate x)) 4439 if (N0.getOpcode() == ISD::TRUNCATE) { 4440 SDValue TruncOp = N0.getOperand(0); 4441 if (TruncOp.getValueType() == VT) 4442 return TruncOp; // x iff x size == zext size. 4443 if (TruncOp.getValueType().bitsGT(VT)) 4444 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp); 4445 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp); 4446 } 4447 4448 // Fold (aext (and (trunc x), cst)) -> (and x, cst) 4449 // if the trunc is not free. 4450 if (N0.getOpcode() == ISD::AND && 4451 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 4452 N0.getOperand(1).getOpcode() == ISD::Constant && 4453 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 4454 N0.getValueType())) { 4455 SDValue X = N0.getOperand(0).getOperand(0); 4456 if (X.getValueType().bitsLT(VT)) { 4457 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X); 4458 } else if (X.getValueType().bitsGT(VT)) { 4459 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X); 4460 } 4461 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4462 Mask = Mask.zext(VT.getSizeInBits()); 4463 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4464 X, DAG.getConstant(Mask, VT)); 4465 } 4466 4467 // fold (aext (load x)) -> (aext (truncate (extload x))) 4468 // None of the supported targets knows how to perform load and any_ext 4469 // on vectors in one instruction. We only perform this transformation on 4470 // scalars. 4471 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4472 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4473 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 4474 bool DoXform = true; 4475 SmallVector<SDNode*, 4> SetCCs; 4476 if (!N0.hasOneUse()) 4477 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI); 4478 if (DoXform) { 4479 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4480 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 4481 LN0->getChain(), 4482 LN0->getBasePtr(), LN0->getPointerInfo(), 4483 N0.getValueType(), 4484 LN0->isVolatile(), LN0->isNonTemporal(), 4485 LN0->getAlignment()); 4486 CombineTo(N, ExtLoad); 4487 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4488 N0.getValueType(), ExtLoad); 4489 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4490 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4491 ISD::ANY_EXTEND); 4492 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4493 } 4494 } 4495 4496 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 4497 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 4498 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 4499 if (N0.getOpcode() == ISD::LOAD && 4500 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 4501 N0.hasOneUse()) { 4502 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4503 EVT MemVT = LN0->getMemoryVT(); 4504 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(), 4505 VT, LN0->getChain(), LN0->getBasePtr(), 4506 LN0->getPointerInfo(), MemVT, 4507 LN0->isVolatile(), LN0->isNonTemporal(), 4508 LN0->getAlignment()); 4509 CombineTo(N, ExtLoad); 4510 CombineTo(N0.getNode(), 4511 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4512 N0.getValueType(), ExtLoad), 4513 ExtLoad.getValue(1)); 4514 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4515 } 4516 4517 if (N0.getOpcode() == ISD::SETCC) { 4518 // aext(setcc) -> sext_in_reg(vsetcc) for vectors. 4519 // Only do this before legalize for now. 4520 if (VT.isVector() && !LegalOperations) { 4521 EVT N0VT = N0.getOperand(0).getValueType(); 4522 // We know that the # elements of the results is the same as the 4523 // # elements of the compare (and the # elements of the compare result 4524 // for that matter). Check to see that they are the same size. If so, 4525 // we know that the element size of the sext'd result matches the 4526 // element size of the compare operands. 4527 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 4528 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4529 N0.getOperand(1), 4530 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4531 // If the desired elements are smaller or larger than the source 4532 // elements we can use a matching integer vector type and then 4533 // truncate/sign extend 4534 else { 4535 EVT MatchingElementType = 4536 EVT::getIntegerVT(*DAG.getContext(), 4537 N0VT.getScalarType().getSizeInBits()); 4538 EVT MatchingVectorType = 4539 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4540 N0VT.getVectorNumElements()); 4541 SDValue VsetCC = 4542 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 4543 N0.getOperand(1), 4544 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4545 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); 4546 } 4547 } 4548 4549 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 4550 SDValue SCC = 4551 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4552 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 4553 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4554 if (SCC.getNode()) 4555 return SCC; 4556 } 4557 4558 return SDValue(); 4559} 4560 4561/// GetDemandedBits - See if the specified operand can be simplified with the 4562/// knowledge that only the bits specified by Mask are used. If so, return the 4563/// simpler operand, otherwise return a null SDValue. 4564SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 4565 switch (V.getOpcode()) { 4566 default: break; 4567 case ISD::OR: 4568 case ISD::XOR: 4569 // If the LHS or RHS don't contribute bits to the or, drop them. 4570 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 4571 return V.getOperand(1); 4572 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 4573 return V.getOperand(0); 4574 break; 4575 case ISD::SRL: 4576 // Only look at single-use SRLs. 4577 if (!V.getNode()->hasOneUse()) 4578 break; 4579 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 4580 // See if we can recursively simplify the LHS. 4581 unsigned Amt = RHSC->getZExtValue(); 4582 4583 // Watch out for shift count overflow though. 4584 if (Amt >= Mask.getBitWidth()) break; 4585 APInt NewMask = Mask << Amt; 4586 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 4587 if (SimplifyLHS.getNode()) 4588 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(), 4589 SimplifyLHS, V.getOperand(1)); 4590 } 4591 } 4592 return SDValue(); 4593} 4594 4595/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 4596/// bits and then truncated to a narrower type and where N is a multiple 4597/// of number of bits of the narrower type, transform it to a narrower load 4598/// from address + N / num of bits of new type. If the result is to be 4599/// extended, also fold the extension to form a extending load. 4600SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 4601 unsigned Opc = N->getOpcode(); 4602 4603 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 4604 SDValue N0 = N->getOperand(0); 4605 EVT VT = N->getValueType(0); 4606 EVT ExtVT = VT; 4607 4608 // This transformation isn't valid for vector loads. 4609 if (VT.isVector()) 4610 return SDValue(); 4611 4612 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then 4613 // extended to VT. 4614 if (Opc == ISD::SIGN_EXTEND_INREG) { 4615 ExtType = ISD::SEXTLOAD; 4616 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 4617 } else if (Opc == ISD::SRL) { 4618 // Another special-case: SRL is basically zero-extending a narrower value. 4619 ExtType = ISD::ZEXTLOAD; 4620 N0 = SDValue(N, 0); 4621 ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 4622 if (!N01) return SDValue(); 4623 ExtVT = EVT::getIntegerVT(*DAG.getContext(), 4624 VT.getSizeInBits() - N01->getZExtValue()); 4625 } 4626 if (LegalOperations && !TLI.isLoadExtLegal(ExtType, ExtVT)) 4627 return SDValue(); 4628 4629 unsigned EVTBits = ExtVT.getSizeInBits(); 4630 4631 // Do not generate loads of non-round integer types since these can 4632 // be expensive (and would be wrong if the type is not byte sized). 4633 if (!ExtVT.isRound()) 4634 return SDValue(); 4635 4636 unsigned ShAmt = 0; 4637 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 4638 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 4639 ShAmt = N01->getZExtValue(); 4640 // Is the shift amount a multiple of size of VT? 4641 if ((ShAmt & (EVTBits-1)) == 0) { 4642 N0 = N0.getOperand(0); 4643 // Is the load width a multiple of size of VT? 4644 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0) 4645 return SDValue(); 4646 } 4647 4648 // At this point, we must have a load or else we can't do the transform. 4649 if (!isa<LoadSDNode>(N0)) return SDValue(); 4650 4651 // If the shift amount is larger than the input type then we're not 4652 // accessing any of the loaded bytes. If the load was a zextload/extload 4653 // then the result of the shift+trunc is zero/undef (handled elsewhere). 4654 // If the load was a sextload then the result is a splat of the sign bit 4655 // of the extended byte. This is not worth optimizing for. 4656 if (ShAmt >= cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits()) 4657 return SDValue(); 4658 } 4659 } 4660 4661 // If the load is shifted left (and the result isn't shifted back right), 4662 // we can fold the truncate through the shift. 4663 unsigned ShLeftAmt = 0; 4664 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() && 4665 ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) { 4666 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 4667 ShLeftAmt = N01->getZExtValue(); 4668 N0 = N0.getOperand(0); 4669 } 4670 } 4671 4672 // If we haven't found a load, we can't narrow it. Don't transform one with 4673 // multiple uses, this would require adding a new load. 4674 if (!isa<LoadSDNode>(N0) || !N0.hasOneUse() || 4675 // Don't change the width of a volatile load. 4676 cast<LoadSDNode>(N0)->isVolatile()) 4677 return SDValue(); 4678 4679 // Verify that we are actually reducing a load width here. 4680 if (cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() < EVTBits) 4681 return SDValue(); 4682 4683 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4684 EVT PtrType = N0.getOperand(1).getValueType(); 4685 4686 // For big endian targets, we need to adjust the offset to the pointer to 4687 // load the correct bytes. 4688 if (TLI.isBigEndian()) { 4689 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 4690 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits(); 4691 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 4692 } 4693 4694 uint64_t PtrOff = ShAmt / 8; 4695 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 4696 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), 4697 PtrType, LN0->getBasePtr(), 4698 DAG.getConstant(PtrOff, PtrType)); 4699 AddToWorkList(NewPtr.getNode()); 4700 4701 SDValue Load; 4702 if (ExtType == ISD::NON_EXTLOAD) 4703 Load = DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr, 4704 LN0->getPointerInfo().getWithOffset(PtrOff), 4705 LN0->isVolatile(), LN0->isNonTemporal(), NewAlign); 4706 else 4707 Load = DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(),NewPtr, 4708 LN0->getPointerInfo().getWithOffset(PtrOff), 4709 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 4710 NewAlign); 4711 4712 // Replace the old load's chain with the new load's chain. 4713 WorkListRemover DeadNodes(*this); 4714 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), 4715 &DeadNodes); 4716 4717 // Shift the result left, if we've swallowed a left shift. 4718 SDValue Result = Load; 4719 if (ShLeftAmt != 0) { 4720 EVT ShImmTy = getShiftAmountTy(Result.getValueType()); 4721 if (!isUIntN(ShImmTy.getSizeInBits(), ShLeftAmt)) 4722 ShImmTy = VT; 4723 Result = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, 4724 Result, DAG.getConstant(ShLeftAmt, ShImmTy)); 4725 } 4726 4727 // Return the new loaded value. 4728 return Result; 4729} 4730 4731SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 4732 SDValue N0 = N->getOperand(0); 4733 SDValue N1 = N->getOperand(1); 4734 EVT VT = N->getValueType(0); 4735 EVT EVT = cast<VTSDNode>(N1)->getVT(); 4736 unsigned VTBits = VT.getScalarType().getSizeInBits(); 4737 unsigned EVTBits = EVT.getScalarType().getSizeInBits(); 4738 4739 // fold (sext_in_reg c1) -> c1 4740 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 4741 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1); 4742 4743 // If the input is already sign extended, just drop the extension. 4744 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1) 4745 return N0; 4746 4747 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 4748 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 4749 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 4750 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 4751 N0.getOperand(0), N1); 4752 } 4753 4754 // fold (sext_in_reg (sext x)) -> (sext x) 4755 // fold (sext_in_reg (aext x)) -> (sext x) 4756 // if x is small enough. 4757 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 4758 SDValue N00 = N0.getOperand(0); 4759 if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits && 4760 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT))) 4761 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1); 4762 } 4763 4764 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 4765 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 4766 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT); 4767 4768 // fold operands of sext_in_reg based on knowledge that the top bits are not 4769 // demanded. 4770 if (SimplifyDemandedBits(SDValue(N, 0))) 4771 return SDValue(N, 0); 4772 4773 // fold (sext_in_reg (load x)) -> (smaller sextload x) 4774 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 4775 SDValue NarrowLoad = ReduceLoadWidth(N); 4776 if (NarrowLoad.getNode()) 4777 return NarrowLoad; 4778 4779 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24) 4780 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible. 4781 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 4782 if (N0.getOpcode() == ISD::SRL) { 4783 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 4784 if (ShAmt->getZExtValue()+EVTBits <= VTBits) { 4785 // We can turn this into an SRA iff the input to the SRL is already sign 4786 // extended enough. 4787 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 4788 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits) 4789 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, 4790 N0.getOperand(0), N0.getOperand(1)); 4791 } 4792 } 4793 4794 // fold (sext_inreg (extload x)) -> (sextload x) 4795 if (ISD::isEXTLoad(N0.getNode()) && 4796 ISD::isUNINDEXEDLoad(N0.getNode()) && 4797 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 4798 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4799 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 4800 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4801 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 4802 LN0->getChain(), 4803 LN0->getBasePtr(), LN0->getPointerInfo(), 4804 EVT, 4805 LN0->isVolatile(), LN0->isNonTemporal(), 4806 LN0->getAlignment()); 4807 CombineTo(N, ExtLoad); 4808 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 4809 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4810 } 4811 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 4812 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 4813 N0.hasOneUse() && 4814 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 4815 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4816 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 4817 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4818 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 4819 LN0->getChain(), 4820 LN0->getBasePtr(), LN0->getPointerInfo(), 4821 EVT, 4822 LN0->isVolatile(), LN0->isNonTemporal(), 4823 LN0->getAlignment()); 4824 CombineTo(N, ExtLoad); 4825 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 4826 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4827 } 4828 4829 // Form (sext_inreg (bswap >> 16)) or (sext_inreg (rotl (bswap) 16)) 4830 if (EVTBits <= 16 && N0.getOpcode() == ISD::OR) { 4831 SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0), 4832 N0.getOperand(1), false); 4833 if (BSwap.getNode() != 0) 4834 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 4835 BSwap, N1); 4836 } 4837 4838 return SDValue(); 4839} 4840 4841SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 4842 SDValue N0 = N->getOperand(0); 4843 EVT VT = N->getValueType(0); 4844 4845 // noop truncate 4846 if (N0.getValueType() == N->getValueType(0)) 4847 return N0; 4848 // fold (truncate c1) -> c1 4849 if (isa<ConstantSDNode>(N0)) 4850 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0); 4851 // fold (truncate (truncate x)) -> (truncate x) 4852 if (N0.getOpcode() == ISD::TRUNCATE) 4853 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 4854 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 4855 if (N0.getOpcode() == ISD::ZERO_EXTEND || 4856 N0.getOpcode() == ISD::SIGN_EXTEND || 4857 N0.getOpcode() == ISD::ANY_EXTEND) { 4858 if (N0.getOperand(0).getValueType().bitsLT(VT)) 4859 // if the source is smaller than the dest, we still need an extend 4860 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 4861 N0.getOperand(0)); 4862 else if (N0.getOperand(0).getValueType().bitsGT(VT)) 4863 // if the source is larger than the dest, than we just need the truncate 4864 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 4865 else 4866 // if the source and dest are the same type, we can drop both the extend 4867 // and the truncate. 4868 return N0.getOperand(0); 4869 } 4870 4871 // See if we can simplify the input to this truncate through knowledge that 4872 // only the low bits are being used. 4873 // For example "trunc (or (shl x, 8), y)" // -> trunc y 4874 // Currently we only perform this optimization on scalars because vectors 4875 // may have different active low bits. 4876 if (!VT.isVector()) { 4877 SDValue Shorter = 4878 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 4879 VT.getSizeInBits())); 4880 if (Shorter.getNode()) 4881 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter); 4882 } 4883 // fold (truncate (load x)) -> (smaller load x) 4884 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 4885 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) { 4886 SDValue Reduced = ReduceLoadWidth(N); 4887 if (Reduced.getNode()) 4888 return Reduced; 4889 } 4890 4891 // Simplify the operands using demanded-bits information. 4892 if (!VT.isVector() && 4893 SimplifyDemandedBits(SDValue(N, 0))) 4894 return SDValue(N, 0); 4895 4896 return SDValue(); 4897} 4898 4899static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 4900 SDValue Elt = N->getOperand(i); 4901 if (Elt.getOpcode() != ISD::MERGE_VALUES) 4902 return Elt.getNode(); 4903 return Elt.getOperand(Elt.getResNo()).getNode(); 4904} 4905 4906/// CombineConsecutiveLoads - build_pair (load, load) -> load 4907/// if load locations are consecutive. 4908SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) { 4909 assert(N->getOpcode() == ISD::BUILD_PAIR); 4910 4911 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0)); 4912 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1)); 4913 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse() || 4914 LD1->getPointerInfo().getAddrSpace() != 4915 LD2->getPointerInfo().getAddrSpace()) 4916 return SDValue(); 4917 EVT LD1VT = LD1->getValueType(0); 4918 4919 if (ISD::isNON_EXTLoad(LD2) && 4920 LD2->hasOneUse() && 4921 // If both are volatile this would reduce the number of volatile loads. 4922 // If one is volatile it might be ok, but play conservative and bail out. 4923 !LD1->isVolatile() && 4924 !LD2->isVolatile() && 4925 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) { 4926 unsigned Align = LD1->getAlignment(); 4927 unsigned NewAlign = TLI.getTargetData()-> 4928 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 4929 4930 if (NewAlign <= Align && 4931 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) 4932 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(), 4933 LD1->getBasePtr(), LD1->getPointerInfo(), 4934 false, false, Align); 4935 } 4936 4937 return SDValue(); 4938} 4939 4940SDValue DAGCombiner::visitBITCAST(SDNode *N) { 4941 SDValue N0 = N->getOperand(0); 4942 EVT VT = N->getValueType(0); 4943 4944 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 4945 // Only do this before legalize, since afterward the target may be depending 4946 // on the bitconvert. 4947 // First check to see if this is all constant. 4948 if (!LegalTypes && 4949 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 4950 VT.isVector()) { 4951 bool isSimple = true; 4952 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 4953 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 4954 N0.getOperand(i).getOpcode() != ISD::Constant && 4955 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 4956 isSimple = false; 4957 break; 4958 } 4959 4960 EVT DestEltVT = N->getValueType(0).getVectorElementType(); 4961 assert(!DestEltVT.isVector() && 4962 "Element type of vector ValueType must not be vector!"); 4963 if (isSimple) 4964 return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(), DestEltVT); 4965 } 4966 4967 // If the input is a constant, let getNode fold it. 4968 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 4969 SDValue Res = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, N0); 4970 if (Res.getNode() != N) { 4971 if (!LegalOperations || 4972 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT)) 4973 return Res; 4974 4975 // Folding it resulted in an illegal node, and it's too late to 4976 // do that. Clean up the old node and forego the transformation. 4977 // Ideally this won't happen very often, because instcombine 4978 // and the earlier dagcombine runs (where illegal nodes are 4979 // permitted) should have folded most of them already. 4980 DAG.DeleteNode(Res.getNode()); 4981 } 4982 } 4983 4984 // (conv (conv x, t1), t2) -> (conv x, t2) 4985 if (N0.getOpcode() == ISD::BITCAST) 4986 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, 4987 N0.getOperand(0)); 4988 4989 // fold (conv (load x)) -> (load (conv*)x) 4990 // If the resultant load doesn't need a higher alignment than the original! 4991 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 4992 // Do not change the width of a volatile load. 4993 !cast<LoadSDNode>(N0)->isVolatile() && 4994 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) { 4995 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4996 unsigned Align = TLI.getTargetData()-> 4997 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 4998 unsigned OrigAlign = LN0->getAlignment(); 4999 5000 if (Align <= OrigAlign) { 5001 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(), 5002 LN0->getBasePtr(), LN0->getPointerInfo(), 5003 LN0->isVolatile(), LN0->isNonTemporal(), 5004 OrigAlign); 5005 AddToWorkList(N); 5006 CombineTo(N0.getNode(), 5007 DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 5008 N0.getValueType(), Load), 5009 Load.getValue(1)); 5010 return Load; 5011 } 5012 } 5013 5014 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit) 5015 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit)) 5016 // This often reduces constant pool loads. 5017 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && 5018 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) { 5019 SDValue NewConv = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), VT, 5020 N0.getOperand(0)); 5021 AddToWorkList(NewConv.getNode()); 5022 5023 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 5024 if (N0.getOpcode() == ISD::FNEG) 5025 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 5026 NewConv, DAG.getConstant(SignBit, VT)); 5027 assert(N0.getOpcode() == ISD::FABS); 5028 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 5029 NewConv, DAG.getConstant(~SignBit, VT)); 5030 } 5031 5032 // fold (bitconvert (fcopysign cst, x)) -> 5033 // (or (and (bitconvert x), sign), (and cst, (not sign))) 5034 // Note that we don't handle (copysign x, cst) because this can always be 5035 // folded to an fneg or fabs. 5036 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 5037 isa<ConstantFPSDNode>(N0.getOperand(0)) && 5038 VT.isInteger() && !VT.isVector()) { 5039 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 5040 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth); 5041 if (isTypeLegal(IntXVT)) { 5042 SDValue X = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 5043 IntXVT, N0.getOperand(1)); 5044 AddToWorkList(X.getNode()); 5045 5046 // If X has a different width than the result/lhs, sext it or truncate it. 5047 unsigned VTWidth = VT.getSizeInBits(); 5048 if (OrigXWidth < VTWidth) { 5049 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X); 5050 AddToWorkList(X.getNode()); 5051 } else if (OrigXWidth > VTWidth) { 5052 // To get the sign bit in the right place, we have to shift it right 5053 // before truncating. 5054 X = DAG.getNode(ISD::SRL, X.getDebugLoc(), 5055 X.getValueType(), X, 5056 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 5057 AddToWorkList(X.getNode()); 5058 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 5059 AddToWorkList(X.getNode()); 5060 } 5061 5062 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 5063 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT, 5064 X, DAG.getConstant(SignBit, VT)); 5065 AddToWorkList(X.getNode()); 5066 5067 SDValue Cst = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 5068 VT, N0.getOperand(0)); 5069 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT, 5070 Cst, DAG.getConstant(~SignBit, VT)); 5071 AddToWorkList(Cst.getNode()); 5072 5073 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst); 5074 } 5075 } 5076 5077 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 5078 if (N0.getOpcode() == ISD::BUILD_PAIR) { 5079 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT); 5080 if (CombineLD.getNode()) 5081 return CombineLD; 5082 } 5083 5084 return SDValue(); 5085} 5086 5087SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 5088 EVT VT = N->getValueType(0); 5089 return CombineConsecutiveLoads(N, VT); 5090} 5091 5092/// ConstantFoldBITCASTofBUILD_VECTOR - We know that BV is a build_vector 5093/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 5094/// destination element value type. 5095SDValue DAGCombiner:: 5096ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) { 5097 EVT SrcEltVT = BV->getValueType(0).getVectorElementType(); 5098 5099 // If this is already the right type, we're done. 5100 if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 5101 5102 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 5103 unsigned DstBitSize = DstEltVT.getSizeInBits(); 5104 5105 // If this is a conversion of N elements of one type to N elements of another 5106 // type, convert each element. This handles FP<->INT cases. 5107 if (SrcBitSize == DstBitSize) { 5108 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 5109 BV->getValueType(0).getVectorNumElements()); 5110 5111 // Due to the FP element handling below calling this routine recursively, 5112 // we can end up with a scalar-to-vector node here. 5113 if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR) 5114 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 5115 DAG.getNode(ISD::BITCAST, BV->getDebugLoc(), 5116 DstEltVT, BV->getOperand(0))); 5117 5118 SmallVector<SDValue, 8> Ops; 5119 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 5120 SDValue Op = BV->getOperand(i); 5121 // If the vector element type is not legal, the BUILD_VECTOR operands 5122 // are promoted and implicitly truncated. Make that explicit here. 5123 if (Op.getValueType() != SrcEltVT) 5124 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op); 5125 Ops.push_back(DAG.getNode(ISD::BITCAST, BV->getDebugLoc(), 5126 DstEltVT, Op)); 5127 AddToWorkList(Ops.back().getNode()); 5128 } 5129 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 5130 &Ops[0], Ops.size()); 5131 } 5132 5133 // Otherwise, we're growing or shrinking the elements. To avoid having to 5134 // handle annoying details of growing/shrinking FP values, we convert them to 5135 // int first. 5136 if (SrcEltVT.isFloatingPoint()) { 5137 // Convert the input float vector to a int vector where the elements are the 5138 // same sizes. 5139 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 5140 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits()); 5141 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode(); 5142 SrcEltVT = IntVT; 5143 } 5144 5145 // Now we know the input is an integer vector. If the output is a FP type, 5146 // convert to integer first, then to FP of the right size. 5147 if (DstEltVT.isFloatingPoint()) { 5148 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 5149 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits()); 5150 SDNode *Tmp = ConstantFoldBITCASTofBUILD_VECTOR(BV, TmpVT).getNode(); 5151 5152 // Next, convert to FP elements of the same size. 5153 return ConstantFoldBITCASTofBUILD_VECTOR(Tmp, DstEltVT); 5154 } 5155 5156 // Okay, we know the src/dst types are both integers of differing types. 5157 // Handling growing first. 5158 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 5159 if (SrcBitSize < DstBitSize) { 5160 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 5161 5162 SmallVector<SDValue, 8> Ops; 5163 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 5164 i += NumInputsPerOutput) { 5165 bool isLE = TLI.isLittleEndian(); 5166 APInt NewBits = APInt(DstBitSize, 0); 5167 bool EltIsUndef = true; 5168 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 5169 // Shift the previously computed bits over. 5170 NewBits <<= SrcBitSize; 5171 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 5172 if (Op.getOpcode() == ISD::UNDEF) continue; 5173 EltIsUndef = false; 5174 5175 NewBits |= cast<ConstantSDNode>(Op)->getAPIntValue(). 5176 zextOrTrunc(SrcBitSize).zext(DstBitSize); 5177 } 5178 5179 if (EltIsUndef) 5180 Ops.push_back(DAG.getUNDEF(DstEltVT)); 5181 else 5182 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 5183 } 5184 5185 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size()); 5186 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 5187 &Ops[0], Ops.size()); 5188 } 5189 5190 // Finally, this must be the case where we are shrinking elements: each input 5191 // turns into multiple outputs. 5192 bool isS2V = ISD::isScalarToVector(BV); 5193 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 5194 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 5195 NumOutputsPerInput*BV->getNumOperands()); 5196 SmallVector<SDValue, 8> Ops; 5197 5198 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 5199 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 5200 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 5201 Ops.push_back(DAG.getUNDEF(DstEltVT)); 5202 continue; 5203 } 5204 5205 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))-> 5206 getAPIntValue().zextOrTrunc(SrcBitSize); 5207 5208 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 5209 APInt ThisVal = OpVal.trunc(DstBitSize); 5210 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 5211 if (isS2V && i == 0 && j == 0 && ThisVal.zext(SrcBitSize) == OpVal) 5212 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 5213 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 5214 Ops[0]); 5215 OpVal = OpVal.lshr(DstBitSize); 5216 } 5217 5218 // For big endian targets, swap the order of the pieces of each element. 5219 if (TLI.isBigEndian()) 5220 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 5221 } 5222 5223 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 5224 &Ops[0], Ops.size()); 5225} 5226 5227SDValue DAGCombiner::visitFADD(SDNode *N) { 5228 SDValue N0 = N->getOperand(0); 5229 SDValue N1 = N->getOperand(1); 5230 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5231 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5232 EVT VT = N->getValueType(0); 5233 5234 // fold vector ops 5235 if (VT.isVector()) { 5236 SDValue FoldedVOp = SimplifyVBinOp(N); 5237 if (FoldedVOp.getNode()) return FoldedVOp; 5238 } 5239 5240 // fold (fadd c1, c2) -> (fadd c1, c2) 5241 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5242 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1); 5243 // canonicalize constant to RHS 5244 if (N0CFP && !N1CFP) 5245 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0); 5246 // fold (fadd A, 0) -> A 5247 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 5248 return N0; 5249 // fold (fadd A, (fneg B)) -> (fsub A, B) 5250 if (isNegatibleForFree(N1, LegalOperations) == 2) 5251 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, 5252 GetNegatedExpression(N1, DAG, LegalOperations)); 5253 // fold (fadd (fneg A), B) -> (fsub B, A) 5254 if (isNegatibleForFree(N0, LegalOperations) == 2) 5255 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1, 5256 GetNegatedExpression(N0, DAG, LegalOperations)); 5257 5258 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 5259 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 5260 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 5261 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0), 5262 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5263 N0.getOperand(1), N1)); 5264 5265 return SDValue(); 5266} 5267 5268SDValue DAGCombiner::visitFSUB(SDNode *N) { 5269 SDValue N0 = N->getOperand(0); 5270 SDValue N1 = N->getOperand(1); 5271 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5272 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5273 EVT VT = N->getValueType(0); 5274 5275 // fold vector ops 5276 if (VT.isVector()) { 5277 SDValue FoldedVOp = SimplifyVBinOp(N); 5278 if (FoldedVOp.getNode()) return FoldedVOp; 5279 } 5280 5281 // fold (fsub c1, c2) -> c1-c2 5282 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5283 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1); 5284 // fold (fsub A, 0) -> A 5285 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 5286 return N0; 5287 // fold (fsub 0, B) -> -B 5288 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { 5289 if (isNegatibleForFree(N1, LegalOperations)) 5290 return GetNegatedExpression(N1, DAG, LegalOperations); 5291 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 5292 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1); 5293 } 5294 // fold (fsub A, (fneg B)) -> (fadd A, B) 5295 if (isNegatibleForFree(N1, LegalOperations)) 5296 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, 5297 GetNegatedExpression(N1, DAG, LegalOperations)); 5298 5299 return SDValue(); 5300} 5301 5302SDValue DAGCombiner::visitFMUL(SDNode *N) { 5303 SDValue N0 = N->getOperand(0); 5304 SDValue N1 = N->getOperand(1); 5305 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5306 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5307 EVT VT = N->getValueType(0); 5308 5309 // fold vector ops 5310 if (VT.isVector()) { 5311 SDValue FoldedVOp = SimplifyVBinOp(N); 5312 if (FoldedVOp.getNode()) return FoldedVOp; 5313 } 5314 5315 // fold (fmul c1, c2) -> c1*c2 5316 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5317 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1); 5318 // canonicalize constant to RHS 5319 if (N0CFP && !N1CFP) 5320 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0); 5321 // fold (fmul A, 0) -> 0 5322 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 5323 return N1; 5324 // fold (fmul A, 0) -> 0, vector edition. 5325 if (UnsafeFPMath && ISD::isBuildVectorAllZeros(N1.getNode())) 5326 return N1; 5327 // fold (fmul X, 2.0) -> (fadd X, X) 5328 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 5329 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0); 5330 // fold (fmul X, -1.0) -> (fneg X) 5331 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 5332 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 5333 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0); 5334 5335 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y) 5336 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 5337 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 5338 // Both can be negated for free, check to see if at least one is cheaper 5339 // negated. 5340 if (LHSNeg == 2 || RHSNeg == 2) 5341 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5342 GetNegatedExpression(N0, DAG, LegalOperations), 5343 GetNegatedExpression(N1, DAG, LegalOperations)); 5344 } 5345 } 5346 5347 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 5348 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 5349 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 5350 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0), 5351 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5352 N0.getOperand(1), N1)); 5353 5354 return SDValue(); 5355} 5356 5357SDValue DAGCombiner::visitFDIV(SDNode *N) { 5358 SDValue N0 = N->getOperand(0); 5359 SDValue N1 = N->getOperand(1); 5360 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5361 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5362 EVT VT = N->getValueType(0); 5363 5364 // fold vector ops 5365 if (VT.isVector()) { 5366 SDValue FoldedVOp = SimplifyVBinOp(N); 5367 if (FoldedVOp.getNode()) return FoldedVOp; 5368 } 5369 5370 // fold (fdiv c1, c2) -> c1/c2 5371 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5372 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1); 5373 5374 5375 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y) 5376 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 5377 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 5378 // Both can be negated for free, check to see if at least one is cheaper 5379 // negated. 5380 if (LHSNeg == 2 || RHSNeg == 2) 5381 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, 5382 GetNegatedExpression(N0, DAG, LegalOperations), 5383 GetNegatedExpression(N1, DAG, LegalOperations)); 5384 } 5385 } 5386 5387 return SDValue(); 5388} 5389 5390SDValue DAGCombiner::visitFREM(SDNode *N) { 5391 SDValue N0 = N->getOperand(0); 5392 SDValue N1 = N->getOperand(1); 5393 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5394 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5395 EVT VT = N->getValueType(0); 5396 5397 // fold (frem c1, c2) -> fmod(c1,c2) 5398 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5399 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1); 5400 5401 return SDValue(); 5402} 5403 5404SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 5405 SDValue N0 = N->getOperand(0); 5406 SDValue N1 = N->getOperand(1); 5407 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5408 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5409 EVT VT = N->getValueType(0); 5410 5411 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 5412 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1); 5413 5414 if (N1CFP) { 5415 const APFloat& V = N1CFP->getValueAPF(); 5416 // copysign(x, c1) -> fabs(x) iff ispos(c1) 5417 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 5418 if (!V.isNegative()) { 5419 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) 5420 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 5421 } else { 5422 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 5423 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, 5424 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0)); 5425 } 5426 } 5427 5428 // copysign(fabs(x), y) -> copysign(x, y) 5429 // copysign(fneg(x), y) -> copysign(x, y) 5430 // copysign(copysign(x,z), y) -> copysign(x, y) 5431 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 5432 N0.getOpcode() == ISD::FCOPYSIGN) 5433 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 5434 N0.getOperand(0), N1); 5435 5436 // copysign(x, abs(y)) -> abs(x) 5437 if (N1.getOpcode() == ISD::FABS) 5438 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 5439 5440 // copysign(x, copysign(y,z)) -> copysign(x, z) 5441 if (N1.getOpcode() == ISD::FCOPYSIGN) 5442 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 5443 N0, N1.getOperand(1)); 5444 5445 // copysign(x, fp_extend(y)) -> copysign(x, y) 5446 // copysign(x, fp_round(y)) -> copysign(x, y) 5447 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 5448 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 5449 N0, N1.getOperand(0)); 5450 5451 return SDValue(); 5452} 5453 5454SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 5455 SDValue N0 = N->getOperand(0); 5456 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 5457 EVT VT = N->getValueType(0); 5458 EVT OpVT = N0.getValueType(); 5459 5460 // fold (sint_to_fp c1) -> c1fp 5461 if (N0C && OpVT != MVT::ppcf128 && 5462 // ...but only if the target supports immediate floating-point values 5463 (Level == llvm::Unrestricted || 5464 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) 5465 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 5466 5467 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 5468 // but UINT_TO_FP is legal on this target, try to convert. 5469 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && 5470 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { 5471 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 5472 if (DAG.SignBitIsZero(N0)) 5473 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 5474 } 5475 5476 return SDValue(); 5477} 5478 5479SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 5480 SDValue N0 = N->getOperand(0); 5481 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 5482 EVT VT = N->getValueType(0); 5483 EVT OpVT = N0.getValueType(); 5484 5485 // fold (uint_to_fp c1) -> c1fp 5486 if (N0C && OpVT != MVT::ppcf128 && 5487 // ...but only if the target supports immediate floating-point values 5488 (Level == llvm::Unrestricted || 5489 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) 5490 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 5491 5492 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 5493 // but SINT_TO_FP is legal on this target, try to convert. 5494 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && 5495 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { 5496 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 5497 if (DAG.SignBitIsZero(N0)) 5498 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 5499 } 5500 5501 return SDValue(); 5502} 5503 5504SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 5505 SDValue N0 = N->getOperand(0); 5506 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5507 EVT VT = N->getValueType(0); 5508 5509 // fold (fp_to_sint c1fp) -> c1 5510 if (N0CFP) 5511 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0); 5512 5513 return SDValue(); 5514} 5515 5516SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 5517 SDValue N0 = N->getOperand(0); 5518 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5519 EVT VT = N->getValueType(0); 5520 5521 // fold (fp_to_uint c1fp) -> c1 5522 if (N0CFP && VT != MVT::ppcf128) 5523 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0); 5524 5525 return SDValue(); 5526} 5527 5528SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 5529 SDValue N0 = N->getOperand(0); 5530 SDValue N1 = N->getOperand(1); 5531 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5532 EVT VT = N->getValueType(0); 5533 5534 // fold (fp_round c1fp) -> c1fp 5535 if (N0CFP && N0.getValueType() != MVT::ppcf128) 5536 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1); 5537 5538 // fold (fp_round (fp_extend x)) -> x 5539 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 5540 return N0.getOperand(0); 5541 5542 // fold (fp_round (fp_round x)) -> (fp_round x) 5543 if (N0.getOpcode() == ISD::FP_ROUND) { 5544 // This is a value preserving truncation if both round's are. 5545 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 5546 N0.getNode()->getConstantOperandVal(1) == 1; 5547 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0), 5548 DAG.getIntPtrConstant(IsTrunc)); 5549 } 5550 5551 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 5552 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { 5553 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT, 5554 N0.getOperand(0), N1); 5555 AddToWorkList(Tmp.getNode()); 5556 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 5557 Tmp, N0.getOperand(1)); 5558 } 5559 5560 return SDValue(); 5561} 5562 5563SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 5564 SDValue N0 = N->getOperand(0); 5565 EVT VT = N->getValueType(0); 5566 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 5567 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5568 5569 // fold (fp_round_inreg c1fp) -> c1fp 5570 if (N0CFP && isTypeLegal(EVT)) { 5571 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT); 5572 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round); 5573 } 5574 5575 return SDValue(); 5576} 5577 5578SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 5579 SDValue N0 = N->getOperand(0); 5580 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5581 EVT VT = N->getValueType(0); 5582 5583 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 5584 if (N->hasOneUse() && 5585 N->use_begin()->getOpcode() == ISD::FP_ROUND) 5586 return SDValue(); 5587 5588 // fold (fp_extend c1fp) -> c1fp 5589 if (N0CFP && VT != MVT::ppcf128) 5590 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0); 5591 5592 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 5593 // value of X. 5594 if (N0.getOpcode() == ISD::FP_ROUND 5595 && N0.getNode()->getConstantOperandVal(1) == 1) { 5596 SDValue In = N0.getOperand(0); 5597 if (In.getValueType() == VT) return In; 5598 if (VT.bitsLT(In.getValueType())) 5599 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, 5600 In, N0.getOperand(1)); 5601 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In); 5602 } 5603 5604 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 5605 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 5606 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 5607 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 5608 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5609 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 5610 LN0->getChain(), 5611 LN0->getBasePtr(), LN0->getPointerInfo(), 5612 N0.getValueType(), 5613 LN0->isVolatile(), LN0->isNonTemporal(), 5614 LN0->getAlignment()); 5615 CombineTo(N, ExtLoad); 5616 CombineTo(N0.getNode(), 5617 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), 5618 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)), 5619 ExtLoad.getValue(1)); 5620 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5621 } 5622 5623 return SDValue(); 5624} 5625 5626SDValue DAGCombiner::visitFNEG(SDNode *N) { 5627 SDValue N0 = N->getOperand(0); 5628 EVT VT = N->getValueType(0); 5629 5630 if (isNegatibleForFree(N0, LegalOperations)) 5631 return GetNegatedExpression(N0, DAG, LegalOperations); 5632 5633 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 5634 // constant pool values. 5635 if (N0.getOpcode() == ISD::BITCAST && 5636 !VT.isVector() && 5637 N0.getNode()->hasOneUse() && 5638 N0.getOperand(0).getValueType().isInteger()) { 5639 SDValue Int = N0.getOperand(0); 5640 EVT IntVT = Int.getValueType(); 5641 if (IntVT.isInteger() && !IntVT.isVector()) { 5642 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int, 5643 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 5644 AddToWorkList(Int.getNode()); 5645 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 5646 VT, Int); 5647 } 5648 } 5649 5650 return SDValue(); 5651} 5652 5653SDValue DAGCombiner::visitFABS(SDNode *N) { 5654 SDValue N0 = N->getOperand(0); 5655 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5656 EVT VT = N->getValueType(0); 5657 5658 // fold (fabs c1) -> fabs(c1) 5659 if (N0CFP && VT != MVT::ppcf128) 5660 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 5661 // fold (fabs (fabs x)) -> (fabs x) 5662 if (N0.getOpcode() == ISD::FABS) 5663 return N->getOperand(0); 5664 // fold (fabs (fneg x)) -> (fabs x) 5665 // fold (fabs (fcopysign x, y)) -> (fabs x) 5666 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 5667 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0)); 5668 5669 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 5670 // constant pool values. 5671 if (N0.getOpcode() == ISD::BITCAST && N0.getNode()->hasOneUse() && 5672 N0.getOperand(0).getValueType().isInteger() && 5673 !N0.getOperand(0).getValueType().isVector()) { 5674 SDValue Int = N0.getOperand(0); 5675 EVT IntVT = Int.getValueType(); 5676 if (IntVT.isInteger() && !IntVT.isVector()) { 5677 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int, 5678 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 5679 AddToWorkList(Int.getNode()); 5680 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 5681 N->getValueType(0), Int); 5682 } 5683 } 5684 5685 return SDValue(); 5686} 5687 5688SDValue DAGCombiner::visitBRCOND(SDNode *N) { 5689 SDValue Chain = N->getOperand(0); 5690 SDValue N1 = N->getOperand(1); 5691 SDValue N2 = N->getOperand(2); 5692 5693 // If N is a constant we could fold this into a fallthrough or unconditional 5694 // branch. However that doesn't happen very often in normal code, because 5695 // Instcombine/SimplifyCFG should have handled the available opportunities. 5696 // If we did this folding here, it would be necessary to update the 5697 // MachineBasicBlock CFG, which is awkward. 5698 5699 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 5700 // on the target. 5701 if (N1.getOpcode() == ISD::SETCC && 5702 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) { 5703 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 5704 Chain, N1.getOperand(2), 5705 N1.getOperand(0), N1.getOperand(1), N2); 5706 } 5707 5708 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) || 5709 ((N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) && 5710 (N1.getOperand(0).hasOneUse() && 5711 N1.getOperand(0).getOpcode() == ISD::SRL))) { 5712 SDNode *Trunc = 0; 5713 if (N1.getOpcode() == ISD::TRUNCATE) { 5714 // Look pass the truncate. 5715 Trunc = N1.getNode(); 5716 N1 = N1.getOperand(0); 5717 } 5718 5719 // Match this pattern so that we can generate simpler code: 5720 // 5721 // %a = ... 5722 // %b = and i32 %a, 2 5723 // %c = srl i32 %b, 1 5724 // brcond i32 %c ... 5725 // 5726 // into 5727 // 5728 // %a = ... 5729 // %b = and i32 %a, 2 5730 // %c = setcc eq %b, 0 5731 // brcond %c ... 5732 // 5733 // This applies only when the AND constant value has one bit set and the 5734 // SRL constant is equal to the log2 of the AND constant. The back-end is 5735 // smart enough to convert the result into a TEST/JMP sequence. 5736 SDValue Op0 = N1.getOperand(0); 5737 SDValue Op1 = N1.getOperand(1); 5738 5739 if (Op0.getOpcode() == ISD::AND && 5740 Op1.getOpcode() == ISD::Constant) { 5741 SDValue AndOp1 = Op0.getOperand(1); 5742 5743 if (AndOp1.getOpcode() == ISD::Constant) { 5744 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue(); 5745 5746 if (AndConst.isPowerOf2() && 5747 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) { 5748 SDValue SetCC = 5749 DAG.getSetCC(N->getDebugLoc(), 5750 TLI.getSetCCResultType(Op0.getValueType()), 5751 Op0, DAG.getConstant(0, Op0.getValueType()), 5752 ISD::SETNE); 5753 5754 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 5755 MVT::Other, Chain, SetCC, N2); 5756 // Don't add the new BRCond into the worklist or else SimplifySelectCC 5757 // will convert it back to (X & C1) >> C2. 5758 CombineTo(N, NewBRCond, false); 5759 // Truncate is dead. 5760 if (Trunc) { 5761 removeFromWorkList(Trunc); 5762 DAG.DeleteNode(Trunc); 5763 } 5764 // Replace the uses of SRL with SETCC 5765 WorkListRemover DeadNodes(*this); 5766 DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes); 5767 removeFromWorkList(N1.getNode()); 5768 DAG.DeleteNode(N1.getNode()); 5769 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5770 } 5771 } 5772 } 5773 5774 if (Trunc) 5775 // Restore N1 if the above transformation doesn't match. 5776 N1 = N->getOperand(1); 5777 } 5778 5779 // Transform br(xor(x, y)) -> br(x != y) 5780 // Transform br(xor(xor(x,y), 1)) -> br (x == y) 5781 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) { 5782 SDNode *TheXor = N1.getNode(); 5783 SDValue Op0 = TheXor->getOperand(0); 5784 SDValue Op1 = TheXor->getOperand(1); 5785 if (Op0.getOpcode() == Op1.getOpcode()) { 5786 // Avoid missing important xor optimizations. 5787 SDValue Tmp = visitXOR(TheXor); 5788 if (Tmp.getNode() && Tmp.getNode() != TheXor) { 5789 DEBUG(dbgs() << "\nReplacing.8 "; 5790 TheXor->dump(&DAG); 5791 dbgs() << "\nWith: "; 5792 Tmp.getNode()->dump(&DAG); 5793 dbgs() << '\n'); 5794 WorkListRemover DeadNodes(*this); 5795 DAG.ReplaceAllUsesOfValueWith(N1, Tmp, &DeadNodes); 5796 removeFromWorkList(TheXor); 5797 DAG.DeleteNode(TheXor); 5798 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 5799 MVT::Other, Chain, Tmp, N2); 5800 } 5801 } 5802 5803 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) { 5804 bool Equal = false; 5805 if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0)) 5806 if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() && 5807 Op0.getOpcode() == ISD::XOR) { 5808 TheXor = Op0.getNode(); 5809 Equal = true; 5810 } 5811 5812 EVT SetCCVT = N1.getValueType(); 5813 if (LegalTypes) 5814 SetCCVT = TLI.getSetCCResultType(SetCCVT); 5815 SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(), 5816 SetCCVT, 5817 Op0, Op1, 5818 Equal ? ISD::SETEQ : ISD::SETNE); 5819 // Replace the uses of XOR with SETCC 5820 WorkListRemover DeadNodes(*this); 5821 DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes); 5822 removeFromWorkList(N1.getNode()); 5823 DAG.DeleteNode(N1.getNode()); 5824 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 5825 MVT::Other, Chain, SetCC, N2); 5826 } 5827 } 5828 5829 return SDValue(); 5830} 5831 5832// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 5833// 5834SDValue DAGCombiner::visitBR_CC(SDNode *N) { 5835 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 5836 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 5837 5838 // If N is a constant we could fold this into a fallthrough or unconditional 5839 // branch. However that doesn't happen very often in normal code, because 5840 // Instcombine/SimplifyCFG should have handled the available opportunities. 5841 // If we did this folding here, it would be necessary to update the 5842 // MachineBasicBlock CFG, which is awkward. 5843 5844 // Use SimplifySetCC to simplify SETCC's. 5845 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()), 5846 CondLHS, CondRHS, CC->get(), N->getDebugLoc(), 5847 false); 5848 if (Simp.getNode()) AddToWorkList(Simp.getNode()); 5849 5850 // fold to a simpler setcc 5851 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) 5852 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 5853 N->getOperand(0), Simp.getOperand(2), 5854 Simp.getOperand(0), Simp.getOperand(1), 5855 N->getOperand(4)); 5856 5857 return SDValue(); 5858} 5859 5860/// CombineToPreIndexedLoadStore - Try turning a load / store into a 5861/// pre-indexed load / store when the base pointer is an add or subtract 5862/// and it has other uses besides the load / store. After the 5863/// transformation, the new indexed load / store has effectively folded 5864/// the add / subtract in and all of its other uses are redirected to the 5865/// new load / store. 5866bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 5867 if (!LegalOperations) 5868 return false; 5869 5870 bool isLoad = true; 5871 SDValue Ptr; 5872 EVT VT; 5873 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 5874 if (LD->isIndexed()) 5875 return false; 5876 VT = LD->getMemoryVT(); 5877 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 5878 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 5879 return false; 5880 Ptr = LD->getBasePtr(); 5881 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 5882 if (ST->isIndexed()) 5883 return false; 5884 VT = ST->getMemoryVT(); 5885 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 5886 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 5887 return false; 5888 Ptr = ST->getBasePtr(); 5889 isLoad = false; 5890 } else { 5891 return false; 5892 } 5893 5894 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 5895 // out. There is no reason to make this a preinc/predec. 5896 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 5897 Ptr.getNode()->hasOneUse()) 5898 return false; 5899 5900 // Ask the target to do addressing mode selection. 5901 SDValue BasePtr; 5902 SDValue Offset; 5903 ISD::MemIndexedMode AM = ISD::UNINDEXED; 5904 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 5905 return false; 5906 // Don't create a indexed load / store with zero offset. 5907 if (isa<ConstantSDNode>(Offset) && 5908 cast<ConstantSDNode>(Offset)->isNullValue()) 5909 return false; 5910 5911 // Try turning it into a pre-indexed load / store except when: 5912 // 1) The new base ptr is a frame index. 5913 // 2) If N is a store and the new base ptr is either the same as or is a 5914 // predecessor of the value being stored. 5915 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 5916 // that would create a cycle. 5917 // 4) All uses are load / store ops that use it as old base ptr. 5918 5919 // Check #1. Preinc'ing a frame index would require copying the stack pointer 5920 // (plus the implicit offset) to a register to preinc anyway. 5921 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 5922 return false; 5923 5924 // Check #2. 5925 if (!isLoad) { 5926 SDValue Val = cast<StoreSDNode>(N)->getValue(); 5927 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode())) 5928 return false; 5929 } 5930 5931 // Now check for #3 and #4. 5932 bool RealUse = false; 5933 5934 // Caches for hasPredecessorHelper 5935 SmallPtrSet<const SDNode *, 32> Visited; 5936 SmallVector<const SDNode *, 16> Worklist; 5937 5938 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 5939 E = Ptr.getNode()->use_end(); I != E; ++I) { 5940 SDNode *Use = *I; 5941 if (Use == N) 5942 continue; 5943 if (N->hasPredecessorHelper(Use, Visited, Worklist)) 5944 return false; 5945 5946 if (!((Use->getOpcode() == ISD::LOAD && 5947 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 5948 (Use->getOpcode() == ISD::STORE && 5949 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))) 5950 RealUse = true; 5951 } 5952 5953 if (!RealUse) 5954 return false; 5955 5956 SDValue Result; 5957 if (isLoad) 5958 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 5959 BasePtr, Offset, AM); 5960 else 5961 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 5962 BasePtr, Offset, AM); 5963 ++PreIndexedNodes; 5964 ++NodesCombined; 5965 DEBUG(dbgs() << "\nReplacing.4 "; 5966 N->dump(&DAG); 5967 dbgs() << "\nWith: "; 5968 Result.getNode()->dump(&DAG); 5969 dbgs() << '\n'); 5970 WorkListRemover DeadNodes(*this); 5971 if (isLoad) { 5972 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 5973 &DeadNodes); 5974 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 5975 &DeadNodes); 5976 } else { 5977 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 5978 &DeadNodes); 5979 } 5980 5981 // Finally, since the node is now dead, remove it from the graph. 5982 DAG.DeleteNode(N); 5983 5984 // Replace the uses of Ptr with uses of the updated base value. 5985 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 5986 &DeadNodes); 5987 removeFromWorkList(Ptr.getNode()); 5988 DAG.DeleteNode(Ptr.getNode()); 5989 5990 return true; 5991} 5992 5993/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 5994/// add / sub of the base pointer node into a post-indexed load / store. 5995/// The transformation folded the add / subtract into the new indexed 5996/// load / store effectively and all of its uses are redirected to the 5997/// new load / store. 5998bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 5999 if (!LegalOperations) 6000 return false; 6001 6002 bool isLoad = true; 6003 SDValue Ptr; 6004 EVT VT; 6005 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 6006 if (LD->isIndexed()) 6007 return false; 6008 VT = LD->getMemoryVT(); 6009 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 6010 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 6011 return false; 6012 Ptr = LD->getBasePtr(); 6013 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 6014 if (ST->isIndexed()) 6015 return false; 6016 VT = ST->getMemoryVT(); 6017 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 6018 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 6019 return false; 6020 Ptr = ST->getBasePtr(); 6021 isLoad = false; 6022 } else { 6023 return false; 6024 } 6025 6026 if (Ptr.getNode()->hasOneUse()) 6027 return false; 6028 6029 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 6030 E = Ptr.getNode()->use_end(); I != E; ++I) { 6031 SDNode *Op = *I; 6032 if (Op == N || 6033 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 6034 continue; 6035 6036 SDValue BasePtr; 6037 SDValue Offset; 6038 ISD::MemIndexedMode AM = ISD::UNINDEXED; 6039 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 6040 // Don't create a indexed load / store with zero offset. 6041 if (isa<ConstantSDNode>(Offset) && 6042 cast<ConstantSDNode>(Offset)->isNullValue()) 6043 continue; 6044 6045 // Try turning it into a post-indexed load / store except when 6046 // 1) All uses are load / store ops that use it as base ptr. 6047 // 2) Op must be independent of N, i.e. Op is neither a predecessor 6048 // nor a successor of N. Otherwise, if Op is folded that would 6049 // create a cycle. 6050 6051 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 6052 continue; 6053 6054 // Check for #1. 6055 bool TryNext = false; 6056 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), 6057 EE = BasePtr.getNode()->use_end(); II != EE; ++II) { 6058 SDNode *Use = *II; 6059 if (Use == Ptr.getNode()) 6060 continue; 6061 6062 // If all the uses are load / store addresses, then don't do the 6063 // transformation. 6064 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 6065 bool RealUse = false; 6066 for (SDNode::use_iterator III = Use->use_begin(), 6067 EEE = Use->use_end(); III != EEE; ++III) { 6068 SDNode *UseUse = *III; 6069 if (!((UseUse->getOpcode() == ISD::LOAD && 6070 cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) || 6071 (UseUse->getOpcode() == ISD::STORE && 6072 cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use))) 6073 RealUse = true; 6074 } 6075 6076 if (!RealUse) { 6077 TryNext = true; 6078 break; 6079 } 6080 } 6081 } 6082 6083 if (TryNext) 6084 continue; 6085 6086 // Check for #2 6087 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 6088 SDValue Result = isLoad 6089 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 6090 BasePtr, Offset, AM) 6091 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 6092 BasePtr, Offset, AM); 6093 ++PostIndexedNodes; 6094 ++NodesCombined; 6095 DEBUG(dbgs() << "\nReplacing.5 "; 6096 N->dump(&DAG); 6097 dbgs() << "\nWith: "; 6098 Result.getNode()->dump(&DAG); 6099 dbgs() << '\n'); 6100 WorkListRemover DeadNodes(*this); 6101 if (isLoad) { 6102 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 6103 &DeadNodes); 6104 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 6105 &DeadNodes); 6106 } else { 6107 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 6108 &DeadNodes); 6109 } 6110 6111 // Finally, since the node is now dead, remove it from the graph. 6112 DAG.DeleteNode(N); 6113 6114 // Replace the uses of Use with uses of the updated base value. 6115 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 6116 Result.getValue(isLoad ? 1 : 0), 6117 &DeadNodes); 6118 removeFromWorkList(Op); 6119 DAG.DeleteNode(Op); 6120 return true; 6121 } 6122 } 6123 } 6124 6125 return false; 6126} 6127 6128SDValue DAGCombiner::visitLOAD(SDNode *N) { 6129 LoadSDNode *LD = cast<LoadSDNode>(N); 6130 SDValue Chain = LD->getChain(); 6131 SDValue Ptr = LD->getBasePtr(); 6132 6133 // If load is not volatile and there are no uses of the loaded value (and 6134 // the updated indexed value in case of indexed loads), change uses of the 6135 // chain value into uses of the chain input (i.e. delete the dead load). 6136 if (!LD->isVolatile()) { 6137 if (N->getValueType(1) == MVT::Other) { 6138 // Unindexed loads. 6139 if (N->hasNUsesOfValue(0, 0)) { 6140 // It's not safe to use the two value CombineTo variant here. e.g. 6141 // v1, chain2 = load chain1, loc 6142 // v2, chain3 = load chain2, loc 6143 // v3 = add v2, c 6144 // Now we replace use of chain2 with chain1. This makes the second load 6145 // isomorphic to the one we are deleting, and thus makes this load live. 6146 DEBUG(dbgs() << "\nReplacing.6 "; 6147 N->dump(&DAG); 6148 dbgs() << "\nWith chain: "; 6149 Chain.getNode()->dump(&DAG); 6150 dbgs() << "\n"); 6151 WorkListRemover DeadNodes(*this); 6152 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes); 6153 6154 if (N->use_empty()) { 6155 removeFromWorkList(N); 6156 DAG.DeleteNode(N); 6157 } 6158 6159 return SDValue(N, 0); // Return N so it doesn't get rechecked! 6160 } 6161 } else { 6162 // Indexed loads. 6163 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 6164 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 6165 SDValue Undef = DAG.getUNDEF(N->getValueType(0)); 6166 DEBUG(dbgs() << "\nReplacing.7 "; 6167 N->dump(&DAG); 6168 dbgs() << "\nWith: "; 6169 Undef.getNode()->dump(&DAG); 6170 dbgs() << " and 2 other values\n"); 6171 WorkListRemover DeadNodes(*this); 6172 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes); 6173 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 6174 DAG.getUNDEF(N->getValueType(1)), 6175 &DeadNodes); 6176 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes); 6177 removeFromWorkList(N); 6178 DAG.DeleteNode(N); 6179 return SDValue(N, 0); // Return N so it doesn't get rechecked! 6180 } 6181 } 6182 } 6183 6184 // If this load is directly stored, replace the load value with the stored 6185 // value. 6186 // TODO: Handle store large -> read small portion. 6187 // TODO: Handle TRUNCSTORE/LOADEXT 6188 if (ISD::isNormalLoad(N) && !LD->isVolatile()) { 6189 if (ISD::isNON_TRUNCStore(Chain.getNode())) { 6190 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 6191 if (PrevST->getBasePtr() == Ptr && 6192 PrevST->getValue().getValueType() == N->getValueType(0)) 6193 return CombineTo(N, Chain.getOperand(1), Chain); 6194 } 6195 } 6196 6197 // Try to infer better alignment information than the load already has. 6198 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) { 6199 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 6200 if (Align > LD->getAlignment()) 6201 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(), 6202 LD->getValueType(0), 6203 Chain, Ptr, LD->getPointerInfo(), 6204 LD->getMemoryVT(), 6205 LD->isVolatile(), LD->isNonTemporal(), Align); 6206 } 6207 } 6208 6209 if (CombinerAA) { 6210 // Walk up chain skipping non-aliasing memory nodes. 6211 SDValue BetterChain = FindBetterChain(N, Chain); 6212 6213 // If there is a better chain. 6214 if (Chain != BetterChain) { 6215 SDValue ReplLoad; 6216 6217 // Replace the chain to void dependency. 6218 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 6219 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(), 6220 BetterChain, Ptr, LD->getPointerInfo(), 6221 LD->isVolatile(), LD->isNonTemporal(), 6222 LD->getAlignment()); 6223 } else { 6224 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(), 6225 LD->getValueType(0), 6226 BetterChain, Ptr, LD->getPointerInfo(), 6227 LD->getMemoryVT(), 6228 LD->isVolatile(), 6229 LD->isNonTemporal(), 6230 LD->getAlignment()); 6231 } 6232 6233 // Create token factor to keep old chain connected. 6234 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 6235 MVT::Other, Chain, ReplLoad.getValue(1)); 6236 6237 // Make sure the new and old chains are cleaned up. 6238 AddToWorkList(Token.getNode()); 6239 6240 // Replace uses with load result and token factor. Don't add users 6241 // to work list. 6242 return CombineTo(N, ReplLoad.getValue(0), Token, false); 6243 } 6244 } 6245 6246 // Try transforming N to an indexed load. 6247 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 6248 return SDValue(N, 0); 6249 6250 return SDValue(); 6251} 6252 6253/// CheckForMaskedLoad - Check to see if V is (and load (ptr), imm), where the 6254/// load is having specific bytes cleared out. If so, return the byte size 6255/// being masked out and the shift amount. 6256static std::pair<unsigned, unsigned> 6257CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) { 6258 std::pair<unsigned, unsigned> Result(0, 0); 6259 6260 // Check for the structure we're looking for. 6261 if (V->getOpcode() != ISD::AND || 6262 !isa<ConstantSDNode>(V->getOperand(1)) || 6263 !ISD::isNormalLoad(V->getOperand(0).getNode())) 6264 return Result; 6265 6266 // Check the chain and pointer. 6267 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0)); 6268 if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer. 6269 6270 // The store should be chained directly to the load or be an operand of a 6271 // tokenfactor. 6272 if (LD == Chain.getNode()) 6273 ; // ok. 6274 else if (Chain->getOpcode() != ISD::TokenFactor) 6275 return Result; // Fail. 6276 else { 6277 bool isOk = false; 6278 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i) 6279 if (Chain->getOperand(i).getNode() == LD) { 6280 isOk = true; 6281 break; 6282 } 6283 if (!isOk) return Result; 6284 } 6285 6286 // This only handles simple types. 6287 if (V.getValueType() != MVT::i16 && 6288 V.getValueType() != MVT::i32 && 6289 V.getValueType() != MVT::i64) 6290 return Result; 6291 6292 // Check the constant mask. Invert it so that the bits being masked out are 6293 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits 6294 // follow the sign bit for uniformity. 6295 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue(); 6296 unsigned NotMaskLZ = CountLeadingZeros_64(NotMask); 6297 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte. 6298 unsigned NotMaskTZ = CountTrailingZeros_64(NotMask); 6299 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte. 6300 if (NotMaskLZ == 64) return Result; // All zero mask. 6301 6302 // See if we have a continuous run of bits. If so, we have 0*1+0* 6303 if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64) 6304 return Result; 6305 6306 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64. 6307 if (V.getValueType() != MVT::i64 && NotMaskLZ) 6308 NotMaskLZ -= 64-V.getValueSizeInBits(); 6309 6310 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8; 6311 switch (MaskedBytes) { 6312 case 1: 6313 case 2: 6314 case 4: break; 6315 default: return Result; // All one mask, or 5-byte mask. 6316 } 6317 6318 // Verify that the first bit starts at a multiple of mask so that the access 6319 // is aligned the same as the access width. 6320 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result; 6321 6322 Result.first = MaskedBytes; 6323 Result.second = NotMaskTZ/8; 6324 return Result; 6325} 6326 6327 6328/// ShrinkLoadReplaceStoreWithStore - Check to see if IVal is something that 6329/// provides a value as specified by MaskInfo. If so, replace the specified 6330/// store with a narrower store of truncated IVal. 6331static SDNode * 6332ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo, 6333 SDValue IVal, StoreSDNode *St, 6334 DAGCombiner *DC) { 6335 unsigned NumBytes = MaskInfo.first; 6336 unsigned ByteShift = MaskInfo.second; 6337 SelectionDAG &DAG = DC->getDAG(); 6338 6339 // Check to see if IVal is all zeros in the part being masked in by the 'or' 6340 // that uses this. If not, this is not a replacement. 6341 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(), 6342 ByteShift*8, (ByteShift+NumBytes)*8); 6343 if (!DAG.MaskedValueIsZero(IVal, Mask)) return 0; 6344 6345 // Check that it is legal on the target to do this. It is legal if the new 6346 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type 6347 // legalization. 6348 MVT VT = MVT::getIntegerVT(NumBytes*8); 6349 if (!DC->isTypeLegal(VT)) 6350 return 0; 6351 6352 // Okay, we can do this! Replace the 'St' store with a store of IVal that is 6353 // shifted by ByteShift and truncated down to NumBytes. 6354 if (ByteShift) 6355 IVal = DAG.getNode(ISD::SRL, IVal->getDebugLoc(), IVal.getValueType(), IVal, 6356 DAG.getConstant(ByteShift*8, 6357 DC->getShiftAmountTy(IVal.getValueType()))); 6358 6359 // Figure out the offset for the store and the alignment of the access. 6360 unsigned StOffset; 6361 unsigned NewAlign = St->getAlignment(); 6362 6363 if (DAG.getTargetLoweringInfo().isLittleEndian()) 6364 StOffset = ByteShift; 6365 else 6366 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes; 6367 6368 SDValue Ptr = St->getBasePtr(); 6369 if (StOffset) { 6370 Ptr = DAG.getNode(ISD::ADD, IVal->getDebugLoc(), Ptr.getValueType(), 6371 Ptr, DAG.getConstant(StOffset, Ptr.getValueType())); 6372 NewAlign = MinAlign(NewAlign, StOffset); 6373 } 6374 6375 // Truncate down to the new size. 6376 IVal = DAG.getNode(ISD::TRUNCATE, IVal->getDebugLoc(), VT, IVal); 6377 6378 ++OpsNarrowed; 6379 return DAG.getStore(St->getChain(), St->getDebugLoc(), IVal, Ptr, 6380 St->getPointerInfo().getWithOffset(StOffset), 6381 false, false, NewAlign).getNode(); 6382} 6383 6384 6385/// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is 6386/// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some 6387/// of the loaded bits, try narrowing the load and store if it would end up 6388/// being a win for performance or code size. 6389SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) { 6390 StoreSDNode *ST = cast<StoreSDNode>(N); 6391 if (ST->isVolatile()) 6392 return SDValue(); 6393 6394 SDValue Chain = ST->getChain(); 6395 SDValue Value = ST->getValue(); 6396 SDValue Ptr = ST->getBasePtr(); 6397 EVT VT = Value.getValueType(); 6398 6399 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse()) 6400 return SDValue(); 6401 6402 unsigned Opc = Value.getOpcode(); 6403 6404 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst 6405 // is a byte mask indicating a consecutive number of bytes, check to see if 6406 // Y is known to provide just those bytes. If so, we try to replace the 6407 // load + replace + store sequence with a single (narrower) store, which makes 6408 // the load dead. 6409 if (Opc == ISD::OR) { 6410 std::pair<unsigned, unsigned> MaskedLoad; 6411 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain); 6412 if (MaskedLoad.first) 6413 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 6414 Value.getOperand(1), ST,this)) 6415 return SDValue(NewST, 0); 6416 6417 // Or is commutative, so try swapping X and Y. 6418 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain); 6419 if (MaskedLoad.first) 6420 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 6421 Value.getOperand(0), ST,this)) 6422 return SDValue(NewST, 0); 6423 } 6424 6425 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) || 6426 Value.getOperand(1).getOpcode() != ISD::Constant) 6427 return SDValue(); 6428 6429 SDValue N0 = Value.getOperand(0); 6430 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 6431 Chain == SDValue(N0.getNode(), 1)) { 6432 LoadSDNode *LD = cast<LoadSDNode>(N0); 6433 if (LD->getBasePtr() != Ptr || 6434 LD->getPointerInfo().getAddrSpace() != 6435 ST->getPointerInfo().getAddrSpace()) 6436 return SDValue(); 6437 6438 // Find the type to narrow it the load / op / store to. 6439 SDValue N1 = Value.getOperand(1); 6440 unsigned BitWidth = N1.getValueSizeInBits(); 6441 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue(); 6442 if (Opc == ISD::AND) 6443 Imm ^= APInt::getAllOnesValue(BitWidth); 6444 if (Imm == 0 || Imm.isAllOnesValue()) 6445 return SDValue(); 6446 unsigned ShAmt = Imm.countTrailingZeros(); 6447 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1; 6448 unsigned NewBW = NextPowerOf2(MSB - ShAmt); 6449 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 6450 while (NewBW < BitWidth && 6451 !(TLI.isOperationLegalOrCustom(Opc, NewVT) && 6452 TLI.isNarrowingProfitable(VT, NewVT))) { 6453 NewBW = NextPowerOf2(NewBW); 6454 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 6455 } 6456 if (NewBW >= BitWidth) 6457 return SDValue(); 6458 6459 // If the lsb changed does not start at the type bitwidth boundary, 6460 // start at the previous one. 6461 if (ShAmt % NewBW) 6462 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW; 6463 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW); 6464 if ((Imm & Mask) == Imm) { 6465 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW); 6466 if (Opc == ISD::AND) 6467 NewImm ^= APInt::getAllOnesValue(NewBW); 6468 uint64_t PtrOff = ShAmt / 8; 6469 // For big endian targets, we need to adjust the offset to the pointer to 6470 // load the correct bytes. 6471 if (TLI.isBigEndian()) 6472 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff; 6473 6474 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff); 6475 Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext()); 6476 if (NewAlign < TLI.getTargetData()->getABITypeAlignment(NewVTTy)) 6477 return SDValue(); 6478 6479 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(), 6480 Ptr.getValueType(), Ptr, 6481 DAG.getConstant(PtrOff, Ptr.getValueType())); 6482 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(), 6483 LD->getChain(), NewPtr, 6484 LD->getPointerInfo().getWithOffset(PtrOff), 6485 LD->isVolatile(), LD->isNonTemporal(), 6486 NewAlign); 6487 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD, 6488 DAG.getConstant(NewImm, NewVT)); 6489 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(), 6490 NewVal, NewPtr, 6491 ST->getPointerInfo().getWithOffset(PtrOff), 6492 false, false, NewAlign); 6493 6494 AddToWorkList(NewPtr.getNode()); 6495 AddToWorkList(NewLD.getNode()); 6496 AddToWorkList(NewVal.getNode()); 6497 WorkListRemover DeadNodes(*this); 6498 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1), 6499 &DeadNodes); 6500 ++OpsNarrowed; 6501 return NewST; 6502 } 6503 } 6504 6505 return SDValue(); 6506} 6507 6508/// TransformFPLoadStorePair - For a given floating point load / store pair, 6509/// if the load value isn't used by any other operations, then consider 6510/// transforming the pair to integer load / store operations if the target 6511/// deems the transformation profitable. 6512SDValue DAGCombiner::TransformFPLoadStorePair(SDNode *N) { 6513 StoreSDNode *ST = cast<StoreSDNode>(N); 6514 SDValue Chain = ST->getChain(); 6515 SDValue Value = ST->getValue(); 6516 if (ISD::isNormalStore(ST) && ISD::isNormalLoad(Value.getNode()) && 6517 Value.hasOneUse() && 6518 Chain == SDValue(Value.getNode(), 1)) { 6519 LoadSDNode *LD = cast<LoadSDNode>(Value); 6520 EVT VT = LD->getMemoryVT(); 6521 if (!VT.isFloatingPoint() || 6522 VT != ST->getMemoryVT() || 6523 LD->isNonTemporal() || 6524 ST->isNonTemporal() || 6525 LD->getPointerInfo().getAddrSpace() != 0 || 6526 ST->getPointerInfo().getAddrSpace() != 0) 6527 return SDValue(); 6528 6529 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits()); 6530 if (!TLI.isOperationLegal(ISD::LOAD, IntVT) || 6531 !TLI.isOperationLegal(ISD::STORE, IntVT) || 6532 !TLI.isDesirableToTransformToIntegerOp(ISD::LOAD, VT) || 6533 !TLI.isDesirableToTransformToIntegerOp(ISD::STORE, VT)) 6534 return SDValue(); 6535 6536 unsigned LDAlign = LD->getAlignment(); 6537 unsigned STAlign = ST->getAlignment(); 6538 Type *IntVTTy = IntVT.getTypeForEVT(*DAG.getContext()); 6539 unsigned ABIAlign = TLI.getTargetData()->getABITypeAlignment(IntVTTy); 6540 if (LDAlign < ABIAlign || STAlign < ABIAlign) 6541 return SDValue(); 6542 6543 SDValue NewLD = DAG.getLoad(IntVT, Value.getDebugLoc(), 6544 LD->getChain(), LD->getBasePtr(), 6545 LD->getPointerInfo(), 6546 false, false, LDAlign); 6547 6548 SDValue NewST = DAG.getStore(NewLD.getValue(1), N->getDebugLoc(), 6549 NewLD, ST->getBasePtr(), 6550 ST->getPointerInfo(), 6551 false, false, STAlign); 6552 6553 AddToWorkList(NewLD.getNode()); 6554 AddToWorkList(NewST.getNode()); 6555 WorkListRemover DeadNodes(*this); 6556 DAG.ReplaceAllUsesOfValueWith(Value.getValue(1), NewLD.getValue(1), 6557 &DeadNodes); 6558 ++LdStFP2Int; 6559 return NewST; 6560 } 6561 6562 return SDValue(); 6563} 6564 6565SDValue DAGCombiner::visitSTORE(SDNode *N) { 6566 StoreSDNode *ST = cast<StoreSDNode>(N); 6567 SDValue Chain = ST->getChain(); 6568 SDValue Value = ST->getValue(); 6569 SDValue Ptr = ST->getBasePtr(); 6570 6571 // If this is a store of a bit convert, store the input value if the 6572 // resultant store does not need a higher alignment than the original. 6573 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() && 6574 ST->isUnindexed()) { 6575 unsigned OrigAlign = ST->getAlignment(); 6576 EVT SVT = Value.getOperand(0).getValueType(); 6577 unsigned Align = TLI.getTargetData()-> 6578 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext())); 6579 if (Align <= OrigAlign && 6580 ((!LegalOperations && !ST->isVolatile()) || 6581 TLI.isOperationLegalOrCustom(ISD::STORE, SVT))) 6582 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0), 6583 Ptr, ST->getPointerInfo(), ST->isVolatile(), 6584 ST->isNonTemporal(), OrigAlign); 6585 } 6586 6587 // Turn 'store undef, Ptr' -> nothing. 6588 if (Value.getOpcode() == ISD::UNDEF && ST->isUnindexed()) 6589 return Chain; 6590 6591 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 6592 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 6593 // NOTE: If the original store is volatile, this transform must not increase 6594 // the number of stores. For example, on x86-32 an f64 can be stored in one 6595 // processor operation but an i64 (which is not legal) requires two. So the 6596 // transform should not be done in this case. 6597 if (Value.getOpcode() != ISD::TargetConstantFP) { 6598 SDValue Tmp; 6599 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) { 6600 default: llvm_unreachable("Unknown FP type"); 6601 case MVT::f80: // We don't do this for these yet. 6602 case MVT::f128: 6603 case MVT::ppcf128: 6604 break; 6605 case MVT::f32: 6606 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) || 6607 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 6608 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 6609 bitcastToAPInt().getZExtValue(), MVT::i32); 6610 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 6611 Ptr, ST->getPointerInfo(), ST->isVolatile(), 6612 ST->isNonTemporal(), ST->getAlignment()); 6613 } 6614 break; 6615 case MVT::f64: 6616 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations && 6617 !ST->isVolatile()) || 6618 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) { 6619 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 6620 getZExtValue(), MVT::i64); 6621 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 6622 Ptr, ST->getPointerInfo(), ST->isVolatile(), 6623 ST->isNonTemporal(), ST->getAlignment()); 6624 } 6625 6626 if (!ST->isVolatile() && 6627 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 6628 // Many FP stores are not made apparent until after legalize, e.g. for 6629 // argument passing. Since this is so common, custom legalize the 6630 // 64-bit integer store into two 32-bit stores. 6631 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); 6632 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 6633 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 6634 if (TLI.isBigEndian()) std::swap(Lo, Hi); 6635 6636 unsigned Alignment = ST->getAlignment(); 6637 bool isVolatile = ST->isVolatile(); 6638 bool isNonTemporal = ST->isNonTemporal(); 6639 6640 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo, 6641 Ptr, ST->getPointerInfo(), 6642 isVolatile, isNonTemporal, 6643 ST->getAlignment()); 6644 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr, 6645 DAG.getConstant(4, Ptr.getValueType())); 6646 Alignment = MinAlign(Alignment, 4U); 6647 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi, 6648 Ptr, ST->getPointerInfo().getWithOffset(4), 6649 isVolatile, isNonTemporal, 6650 Alignment); 6651 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 6652 St0, St1); 6653 } 6654 6655 break; 6656 } 6657 } 6658 } 6659 6660 // Try to infer better alignment information than the store already has. 6661 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) { 6662 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 6663 if (Align > ST->getAlignment()) 6664 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value, 6665 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 6666 ST->isVolatile(), ST->isNonTemporal(), Align); 6667 } 6668 } 6669 6670 // Try transforming a pair floating point load / store ops to integer 6671 // load / store ops. 6672 SDValue NewST = TransformFPLoadStorePair(N); 6673 if (NewST.getNode()) 6674 return NewST; 6675 6676 if (CombinerAA) { 6677 // Walk up chain skipping non-aliasing memory nodes. 6678 SDValue BetterChain = FindBetterChain(N, Chain); 6679 6680 // If there is a better chain. 6681 if (Chain != BetterChain) { 6682 SDValue ReplStore; 6683 6684 // Replace the chain to avoid dependency. 6685 if (ST->isTruncatingStore()) { 6686 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr, 6687 ST->getPointerInfo(), 6688 ST->getMemoryVT(), ST->isVolatile(), 6689 ST->isNonTemporal(), ST->getAlignment()); 6690 } else { 6691 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr, 6692 ST->getPointerInfo(), 6693 ST->isVolatile(), ST->isNonTemporal(), 6694 ST->getAlignment()); 6695 } 6696 6697 // Create token to keep both nodes around. 6698 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 6699 MVT::Other, Chain, ReplStore); 6700 6701 // Make sure the new and old chains are cleaned up. 6702 AddToWorkList(Token.getNode()); 6703 6704 // Don't add users to work list. 6705 return CombineTo(N, Token, false); 6706 } 6707 } 6708 6709 // Try transforming N to an indexed store. 6710 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 6711 return SDValue(N, 0); 6712 6713 // FIXME: is there such a thing as a truncating indexed store? 6714 if (ST->isTruncatingStore() && ST->isUnindexed() && 6715 Value.getValueType().isInteger()) { 6716 // See if we can simplify the input to this truncstore with knowledge that 6717 // only the low bits are being used. For example: 6718 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 6719 SDValue Shorter = 6720 GetDemandedBits(Value, 6721 APInt::getLowBitsSet( 6722 Value.getValueType().getScalarType().getSizeInBits(), 6723 ST->getMemoryVT().getScalarType().getSizeInBits())); 6724 AddToWorkList(Value.getNode()); 6725 if (Shorter.getNode()) 6726 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter, 6727 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 6728 ST->isVolatile(), ST->isNonTemporal(), 6729 ST->getAlignment()); 6730 6731 // Otherwise, see if we can simplify the operation with 6732 // SimplifyDemandedBits, which only works if the value has a single use. 6733 if (SimplifyDemandedBits(Value, 6734 APInt::getLowBitsSet( 6735 Value.getValueType().getScalarType().getSizeInBits(), 6736 ST->getMemoryVT().getScalarType().getSizeInBits()))) 6737 return SDValue(N, 0); 6738 } 6739 6740 // If this is a load followed by a store to the same location, then the store 6741 // is dead/noop. 6742 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 6743 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 6744 ST->isUnindexed() && !ST->isVolatile() && 6745 // There can't be any side effects between the load and store, such as 6746 // a call or store. 6747 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 6748 // The store is dead, remove it. 6749 return Chain; 6750 } 6751 } 6752 6753 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 6754 // truncating store. We can do this even if this is already a truncstore. 6755 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 6756 && Value.getNode()->hasOneUse() && ST->isUnindexed() && 6757 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 6758 ST->getMemoryVT())) { 6759 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0), 6760 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 6761 ST->isVolatile(), ST->isNonTemporal(), 6762 ST->getAlignment()); 6763 } 6764 6765 return ReduceLoadOpStoreWidth(N); 6766} 6767 6768SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 6769 SDValue InVec = N->getOperand(0); 6770 SDValue InVal = N->getOperand(1); 6771 SDValue EltNo = N->getOperand(2); 6772 DebugLoc dl = N->getDebugLoc(); 6773 6774 // If the inserted element is an UNDEF, just use the input vector. 6775 if (InVal.getOpcode() == ISD::UNDEF) 6776 return InVec; 6777 6778 EVT VT = InVec.getValueType(); 6779 6780 // If we can't generate a legal BUILD_VECTOR, exit 6781 if (LegalOperations && !TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) 6782 return SDValue(); 6783 6784 // Check that we know which element is being inserted 6785 if (!isa<ConstantSDNode>(EltNo)) 6786 return SDValue(); 6787 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 6788 6789 // Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially 6790 // be converted to a BUILD_VECTOR). Fill in the Ops vector with the 6791 // vector elements. 6792 SmallVector<SDValue, 8> Ops; 6793 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { 6794 Ops.append(InVec.getNode()->op_begin(), 6795 InVec.getNode()->op_end()); 6796 } else if (InVec.getOpcode() == ISD::UNDEF) { 6797 unsigned NElts = VT.getVectorNumElements(); 6798 Ops.append(NElts, DAG.getUNDEF(InVal.getValueType())); 6799 } else { 6800 return SDValue(); 6801 } 6802 6803 // Insert the element 6804 if (Elt < Ops.size()) { 6805 // All the operands of BUILD_VECTOR must have the same type; 6806 // we enforce that here. 6807 EVT OpVT = Ops[0].getValueType(); 6808 if (InVal.getValueType() != OpVT) 6809 InVal = OpVT.bitsGT(InVal.getValueType()) ? 6810 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) : 6811 DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal); 6812 Ops[Elt] = InVal; 6813 } 6814 6815 // Return the new vector 6816 return DAG.getNode(ISD::BUILD_VECTOR, dl, 6817 VT, &Ops[0], Ops.size()); 6818} 6819 6820SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 6821 // (vextract (scalar_to_vector val, 0) -> val 6822 SDValue InVec = N->getOperand(0); 6823 6824 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 6825 // Check if the result type doesn't match the inserted element type. A 6826 // SCALAR_TO_VECTOR may truncate the inserted element and the 6827 // EXTRACT_VECTOR_ELT may widen the extracted vector. 6828 SDValue InOp = InVec.getOperand(0); 6829 EVT NVT = N->getValueType(0); 6830 if (InOp.getValueType() != NVT) { 6831 assert(InOp.getValueType().isInteger() && NVT.isInteger()); 6832 return DAG.getSExtOrTrunc(InOp, InVec.getDebugLoc(), NVT); 6833 } 6834 return InOp; 6835 } 6836 6837 // Perform only after legalization to ensure build_vector / vector_shuffle 6838 // optimizations have already been done. 6839 if (!LegalOperations) return SDValue(); 6840 6841 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 6842 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 6843 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 6844 SDValue EltNo = N->getOperand(1); 6845 6846 if (isa<ConstantSDNode>(EltNo)) { 6847 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 6848 bool NewLoad = false; 6849 bool BCNumEltsChanged = false; 6850 EVT VT = InVec.getValueType(); 6851 EVT ExtVT = VT.getVectorElementType(); 6852 EVT LVT = ExtVT; 6853 6854 if (InVec.getOpcode() == ISD::BITCAST) { 6855 EVT BCVT = InVec.getOperand(0).getValueType(); 6856 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType())) 6857 return SDValue(); 6858 if (VT.getVectorNumElements() != BCVT.getVectorNumElements()) 6859 BCNumEltsChanged = true; 6860 InVec = InVec.getOperand(0); 6861 ExtVT = BCVT.getVectorElementType(); 6862 NewLoad = true; 6863 } 6864 6865 LoadSDNode *LN0 = NULL; 6866 const ShuffleVectorSDNode *SVN = NULL; 6867 if (ISD::isNormalLoad(InVec.getNode())) { 6868 LN0 = cast<LoadSDNode>(InVec); 6869 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 6870 InVec.getOperand(0).getValueType() == ExtVT && 6871 ISD::isNormalLoad(InVec.getOperand(0).getNode())) { 6872 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 6873 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) { 6874 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 6875 // => 6876 // (load $addr+1*size) 6877 6878 // If the bit convert changed the number of elements, it is unsafe 6879 // to examine the mask. 6880 if (BCNumEltsChanged) 6881 return SDValue(); 6882 6883 // Select the input vector, guarding against out of range extract vector. 6884 unsigned NumElems = VT.getVectorNumElements(); 6885 int Idx = (Elt > (int)NumElems) ? -1 : SVN->getMaskElt(Elt); 6886 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 6887 6888 if (InVec.getOpcode() == ISD::BITCAST) 6889 InVec = InVec.getOperand(0); 6890 if (ISD::isNormalLoad(InVec.getNode())) { 6891 LN0 = cast<LoadSDNode>(InVec); 6892 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems; 6893 } 6894 } 6895 6896 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile()) 6897 return SDValue(); 6898 6899 // If Idx was -1 above, Elt is going to be -1, so just return undef. 6900 if (Elt == -1) 6901 return DAG.getUNDEF(LVT); 6902 6903 unsigned Align = LN0->getAlignment(); 6904 if (NewLoad) { 6905 // Check the resultant load doesn't need a higher alignment than the 6906 // original load. 6907 unsigned NewAlign = 6908 TLI.getTargetData() 6909 ->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext())); 6910 6911 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT)) 6912 return SDValue(); 6913 6914 Align = NewAlign; 6915 } 6916 6917 SDValue NewPtr = LN0->getBasePtr(); 6918 unsigned PtrOff = 0; 6919 6920 if (Elt) { 6921 PtrOff = LVT.getSizeInBits() * Elt / 8; 6922 EVT PtrType = NewPtr.getValueType(); 6923 if (TLI.isBigEndian()) 6924 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 6925 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr, 6926 DAG.getConstant(PtrOff, PtrType)); 6927 } 6928 6929 return DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr, 6930 LN0->getPointerInfo().getWithOffset(PtrOff), 6931 LN0->isVolatile(), LN0->isNonTemporal(), Align); 6932 } 6933 6934 return SDValue(); 6935} 6936 6937SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 6938 unsigned NumInScalars = N->getNumOperands(); 6939 EVT VT = N->getValueType(0); 6940 6941 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 6942 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 6943 // at most two distinct vectors, turn this into a shuffle node. 6944 SDValue VecIn1, VecIn2; 6945 for (unsigned i = 0; i != NumInScalars; ++i) { 6946 // Ignore undef inputs. 6947 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 6948 6949 // If this input is something other than a EXTRACT_VECTOR_ELT with a 6950 // constant index, bail out. 6951 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 6952 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 6953 VecIn1 = VecIn2 = SDValue(0, 0); 6954 break; 6955 } 6956 6957 // If the input vector type disagrees with the result of the build_vector, 6958 // we can't make a shuffle. 6959 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 6960 if (ExtractedFromVec.getValueType() != VT) { 6961 VecIn1 = VecIn2 = SDValue(0, 0); 6962 break; 6963 } 6964 6965 // Otherwise, remember this. We allow up to two distinct input vectors. 6966 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 6967 continue; 6968 6969 if (VecIn1.getNode() == 0) { 6970 VecIn1 = ExtractedFromVec; 6971 } else if (VecIn2.getNode() == 0) { 6972 VecIn2 = ExtractedFromVec; 6973 } else { 6974 // Too many inputs. 6975 VecIn1 = VecIn2 = SDValue(0, 0); 6976 break; 6977 } 6978 } 6979 6980 // If everything is good, we can make a shuffle operation. 6981 if (VecIn1.getNode()) { 6982 SmallVector<int, 8> Mask; 6983 for (unsigned i = 0; i != NumInScalars; ++i) { 6984 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 6985 Mask.push_back(-1); 6986 continue; 6987 } 6988 6989 // If extracting from the first vector, just use the index directly. 6990 SDValue Extract = N->getOperand(i); 6991 SDValue ExtVal = Extract.getOperand(1); 6992 if (Extract.getOperand(0) == VecIn1) { 6993 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 6994 if (ExtIndex > VT.getVectorNumElements()) 6995 return SDValue(); 6996 6997 Mask.push_back(ExtIndex); 6998 continue; 6999 } 7000 7001 // Otherwise, use InIdx + VecSize 7002 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 7003 Mask.push_back(Idx+NumInScalars); 7004 } 7005 7006 // Add count and size info. 7007 if (!isTypeLegal(VT)) 7008 return SDValue(); 7009 7010 // Return the new VECTOR_SHUFFLE node. 7011 SDValue Ops[2]; 7012 Ops[0] = VecIn1; 7013 Ops[1] = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT); 7014 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]); 7015 } 7016 7017 return SDValue(); 7018} 7019 7020SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 7021 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 7022 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 7023 // inputs come from at most two distinct vectors, turn this into a shuffle 7024 // node. 7025 7026 // If we only have one input vector, we don't need to do any concatenation. 7027 if (N->getNumOperands() == 1) 7028 return N->getOperand(0); 7029 7030 return SDValue(); 7031} 7032 7033SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode* N) { 7034 EVT NVT = N->getValueType(0); 7035 SDValue V = N->getOperand(0); 7036 7037 if (V->getOpcode() == ISD::INSERT_SUBVECTOR) { 7038 // Handle only simple case where vector being inserted and vector 7039 // being extracted are of same type, and are half size of larger vectors. 7040 EVT BigVT = V->getOperand(0).getValueType(); 7041 EVT SmallVT = V->getOperand(1).getValueType(); 7042 if (NVT != SmallVT || NVT.getSizeInBits()*2 != BigVT.getSizeInBits()) 7043 return SDValue(); 7044 7045 // Combine: 7046 // (extract_subvec (insert_subvec V1, V2, InsIdx), ExtIdx) 7047 // Into: 7048 // indicies are equal => V1 7049 // otherwise => (extract_subvec V1, ExtIdx) 7050 // 7051 SDValue InsIdx = N->getOperand(1); 7052 SDValue ExtIdx = V->getOperand(2); 7053 7054 if (InsIdx == ExtIdx) 7055 return V->getOperand(1); 7056 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, N->getDebugLoc(), NVT, 7057 V->getOperand(0), N->getOperand(1)); 7058 } 7059 7060 return SDValue(); 7061} 7062 7063SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 7064 EVT VT = N->getValueType(0); 7065 unsigned NumElts = VT.getVectorNumElements(); 7066 7067 SDValue N0 = N->getOperand(0); 7068 7069 assert(N0.getValueType().getVectorNumElements() == NumElts && 7070 "Vector shuffle must be normalized in DAG"); 7071 7072 // FIXME: implement canonicalizations from DAG.getVectorShuffle() 7073 7074 // If it is a splat, check if the argument vector is another splat or a 7075 // build_vector with all scalar elements the same. 7076 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N); 7077 if (SVN->isSplat() && SVN->getSplatIndex() < (int)NumElts) { 7078 SDNode *V = N0.getNode(); 7079 7080 // If this is a bit convert that changes the element type of the vector but 7081 // not the number of vector elements, look through it. Be careful not to 7082 // look though conversions that change things like v4f32 to v2f64. 7083 if (V->getOpcode() == ISD::BITCAST) { 7084 SDValue ConvInput = V->getOperand(0); 7085 if (ConvInput.getValueType().isVector() && 7086 ConvInput.getValueType().getVectorNumElements() == NumElts) 7087 V = ConvInput.getNode(); 7088 } 7089 7090 if (V->getOpcode() == ISD::BUILD_VECTOR) { 7091 assert(V->getNumOperands() == NumElts && 7092 "BUILD_VECTOR has wrong number of operands"); 7093 SDValue Base; 7094 bool AllSame = true; 7095 for (unsigned i = 0; i != NumElts; ++i) { 7096 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 7097 Base = V->getOperand(i); 7098 break; 7099 } 7100 } 7101 // Splat of <u, u, u, u>, return <u, u, u, u> 7102 if (!Base.getNode()) 7103 return N0; 7104 for (unsigned i = 0; i != NumElts; ++i) { 7105 if (V->getOperand(i) != Base) { 7106 AllSame = false; 7107 break; 7108 } 7109 } 7110 // Splat of <x, x, x, x>, return <x, x, x, x> 7111 if (AllSame) 7112 return N0; 7113 } 7114 } 7115 return SDValue(); 7116} 7117 7118SDValue DAGCombiner::visitMEMBARRIER(SDNode* N) { 7119 if (!TLI.getShouldFoldAtomicFences()) 7120 return SDValue(); 7121 7122 SDValue atomic = N->getOperand(0); 7123 switch (atomic.getOpcode()) { 7124 case ISD::ATOMIC_CMP_SWAP: 7125 case ISD::ATOMIC_SWAP: 7126 case ISD::ATOMIC_LOAD_ADD: 7127 case ISD::ATOMIC_LOAD_SUB: 7128 case ISD::ATOMIC_LOAD_AND: 7129 case ISD::ATOMIC_LOAD_OR: 7130 case ISD::ATOMIC_LOAD_XOR: 7131 case ISD::ATOMIC_LOAD_NAND: 7132 case ISD::ATOMIC_LOAD_MIN: 7133 case ISD::ATOMIC_LOAD_MAX: 7134 case ISD::ATOMIC_LOAD_UMIN: 7135 case ISD::ATOMIC_LOAD_UMAX: 7136 break; 7137 default: 7138 return SDValue(); 7139 } 7140 7141 SDValue fence = atomic.getOperand(0); 7142 if (fence.getOpcode() != ISD::MEMBARRIER) 7143 return SDValue(); 7144 7145 switch (atomic.getOpcode()) { 7146 case ISD::ATOMIC_CMP_SWAP: 7147 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(), 7148 fence.getOperand(0), 7149 atomic.getOperand(1), atomic.getOperand(2), 7150 atomic.getOperand(3)), atomic.getResNo()); 7151 case ISD::ATOMIC_SWAP: 7152 case ISD::ATOMIC_LOAD_ADD: 7153 case ISD::ATOMIC_LOAD_SUB: 7154 case ISD::ATOMIC_LOAD_AND: 7155 case ISD::ATOMIC_LOAD_OR: 7156 case ISD::ATOMIC_LOAD_XOR: 7157 case ISD::ATOMIC_LOAD_NAND: 7158 case ISD::ATOMIC_LOAD_MIN: 7159 case ISD::ATOMIC_LOAD_MAX: 7160 case ISD::ATOMIC_LOAD_UMIN: 7161 case ISD::ATOMIC_LOAD_UMAX: 7162 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(), 7163 fence.getOperand(0), 7164 atomic.getOperand(1), atomic.getOperand(2)), 7165 atomic.getResNo()); 7166 default: 7167 return SDValue(); 7168 } 7169} 7170 7171/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 7172/// an AND to a vector_shuffle with the destination vector and a zero vector. 7173/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 7174/// vector_shuffle V, Zero, <0, 4, 2, 4> 7175SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 7176 EVT VT = N->getValueType(0); 7177 DebugLoc dl = N->getDebugLoc(); 7178 SDValue LHS = N->getOperand(0); 7179 SDValue RHS = N->getOperand(1); 7180 if (N->getOpcode() == ISD::AND) { 7181 if (RHS.getOpcode() == ISD::BITCAST) 7182 RHS = RHS.getOperand(0); 7183 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 7184 SmallVector<int, 8> Indices; 7185 unsigned NumElts = RHS.getNumOperands(); 7186 for (unsigned i = 0; i != NumElts; ++i) { 7187 SDValue Elt = RHS.getOperand(i); 7188 if (!isa<ConstantSDNode>(Elt)) 7189 return SDValue(); 7190 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 7191 Indices.push_back(i); 7192 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 7193 Indices.push_back(NumElts); 7194 else 7195 return SDValue(); 7196 } 7197 7198 // Let's see if the target supports this vector_shuffle. 7199 EVT RVT = RHS.getValueType(); 7200 if (!TLI.isVectorClearMaskLegal(Indices, RVT)) 7201 return SDValue(); 7202 7203 // Return the new VECTOR_SHUFFLE node. 7204 EVT EltVT = RVT.getVectorElementType(); 7205 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(), 7206 DAG.getConstant(0, EltVT)); 7207 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 7208 RVT, &ZeroOps[0], ZeroOps.size()); 7209 LHS = DAG.getNode(ISD::BITCAST, dl, RVT, LHS); 7210 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]); 7211 return DAG.getNode(ISD::BITCAST, dl, VT, Shuf); 7212 } 7213 } 7214 7215 return SDValue(); 7216} 7217 7218/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 7219SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 7220 // After legalize, the target may be depending on adds and other 7221 // binary ops to provide legal ways to construct constants or other 7222 // things. Simplifying them may result in a loss of legality. 7223 if (LegalOperations) return SDValue(); 7224 7225 assert(N->getValueType(0).isVector() && 7226 "SimplifyVBinOp only works on vectors!"); 7227 7228 SDValue LHS = N->getOperand(0); 7229 SDValue RHS = N->getOperand(1); 7230 SDValue Shuffle = XformToShuffleWithZero(N); 7231 if (Shuffle.getNode()) return Shuffle; 7232 7233 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 7234 // this operation. 7235 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 7236 RHS.getOpcode() == ISD::BUILD_VECTOR) { 7237 SmallVector<SDValue, 8> Ops; 7238 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 7239 SDValue LHSOp = LHS.getOperand(i); 7240 SDValue RHSOp = RHS.getOperand(i); 7241 // If these two elements can't be folded, bail out. 7242 if ((LHSOp.getOpcode() != ISD::UNDEF && 7243 LHSOp.getOpcode() != ISD::Constant && 7244 LHSOp.getOpcode() != ISD::ConstantFP) || 7245 (RHSOp.getOpcode() != ISD::UNDEF && 7246 RHSOp.getOpcode() != ISD::Constant && 7247 RHSOp.getOpcode() != ISD::ConstantFP)) 7248 break; 7249 7250 // Can't fold divide by zero. 7251 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 7252 N->getOpcode() == ISD::FDIV) { 7253 if ((RHSOp.getOpcode() == ISD::Constant && 7254 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) || 7255 (RHSOp.getOpcode() == ISD::ConstantFP && 7256 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero())) 7257 break; 7258 } 7259 7260 EVT VT = LHSOp.getValueType(); 7261 EVT RVT = RHSOp.getValueType(); 7262 if (RVT != VT) { 7263 // Integer BUILD_VECTOR operands may have types larger than the element 7264 // size (e.g., when the element type is not legal). Prior to type 7265 // legalization, the types may not match between the two BUILD_VECTORS. 7266 // Truncate one of the operands to make them match. 7267 if (RVT.getSizeInBits() > VT.getSizeInBits()) { 7268 RHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, RHSOp); 7269 } else { 7270 LHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), RVT, LHSOp); 7271 VT = RVT; 7272 } 7273 } 7274 SDValue FoldOp = DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), VT, 7275 LHSOp, RHSOp); 7276 if (FoldOp.getOpcode() != ISD::UNDEF && 7277 FoldOp.getOpcode() != ISD::Constant && 7278 FoldOp.getOpcode() != ISD::ConstantFP) 7279 break; 7280 Ops.push_back(FoldOp); 7281 AddToWorkList(FoldOp.getNode()); 7282 } 7283 7284 if (Ops.size() == LHS.getNumOperands()) 7285 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 7286 LHS.getValueType(), &Ops[0], Ops.size()); 7287 } 7288 7289 return SDValue(); 7290} 7291 7292SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0, 7293 SDValue N1, SDValue N2){ 7294 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 7295 7296 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2, 7297 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 7298 7299 // If we got a simplified select_cc node back from SimplifySelectCC, then 7300 // break it down into a new SETCC node, and a new SELECT node, and then return 7301 // the SELECT node, since we were called with a SELECT node. 7302 if (SCC.getNode()) { 7303 // Check to see if we got a select_cc back (to turn into setcc/select). 7304 // Otherwise, just return whatever node we got back, like fabs. 7305 if (SCC.getOpcode() == ISD::SELECT_CC) { 7306 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(), 7307 N0.getValueType(), 7308 SCC.getOperand(0), SCC.getOperand(1), 7309 SCC.getOperand(4)); 7310 AddToWorkList(SETCC.getNode()); 7311 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(), 7312 SCC.getOperand(2), SCC.getOperand(3), SETCC); 7313 } 7314 7315 return SCC; 7316 } 7317 return SDValue(); 7318} 7319 7320/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 7321/// are the two values being selected between, see if we can simplify the 7322/// select. Callers of this should assume that TheSelect is deleted if this 7323/// returns true. As such, they should return the appropriate thing (e.g. the 7324/// node) back to the top-level of the DAG combiner loop to avoid it being 7325/// looked at. 7326bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 7327 SDValue RHS) { 7328 7329 // Cannot simplify select with vector condition 7330 if (TheSelect->getOperand(0).getValueType().isVector()) return false; 7331 7332 // If this is a select from two identical things, try to pull the operation 7333 // through the select. 7334 if (LHS.getOpcode() != RHS.getOpcode() || 7335 !LHS.hasOneUse() || !RHS.hasOneUse()) 7336 return false; 7337 7338 // If this is a load and the token chain is identical, replace the select 7339 // of two loads with a load through a select of the address to load from. 7340 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 7341 // constants have been dropped into the constant pool. 7342 if (LHS.getOpcode() == ISD::LOAD) { 7343 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 7344 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 7345 7346 // Token chains must be identical. 7347 if (LHS.getOperand(0) != RHS.getOperand(0) || 7348 // Do not let this transformation reduce the number of volatile loads. 7349 LLD->isVolatile() || RLD->isVolatile() || 7350 // If this is an EXTLOAD, the VT's must match. 7351 LLD->getMemoryVT() != RLD->getMemoryVT() || 7352 // If this is an EXTLOAD, the kind of extension must match. 7353 (LLD->getExtensionType() != RLD->getExtensionType() && 7354 // The only exception is if one of the extensions is anyext. 7355 LLD->getExtensionType() != ISD::EXTLOAD && 7356 RLD->getExtensionType() != ISD::EXTLOAD) || 7357 // FIXME: this discards src value information. This is 7358 // over-conservative. It would be beneficial to be able to remember 7359 // both potential memory locations. Since we are discarding 7360 // src value info, don't do the transformation if the memory 7361 // locations are not in the default address space. 7362 LLD->getPointerInfo().getAddrSpace() != 0 || 7363 RLD->getPointerInfo().getAddrSpace() != 0) 7364 return false; 7365 7366 // Check that the select condition doesn't reach either load. If so, 7367 // folding this will induce a cycle into the DAG. If not, this is safe to 7368 // xform, so create a select of the addresses. 7369 SDValue Addr; 7370 if (TheSelect->getOpcode() == ISD::SELECT) { 7371 SDNode *CondNode = TheSelect->getOperand(0).getNode(); 7372 if ((LLD->hasAnyUseOfValue(1) && LLD->isPredecessorOf(CondNode)) || 7373 (RLD->hasAnyUseOfValue(1) && RLD->isPredecessorOf(CondNode))) 7374 return false; 7375 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(), 7376 LLD->getBasePtr().getValueType(), 7377 TheSelect->getOperand(0), LLD->getBasePtr(), 7378 RLD->getBasePtr()); 7379 } else { // Otherwise SELECT_CC 7380 SDNode *CondLHS = TheSelect->getOperand(0).getNode(); 7381 SDNode *CondRHS = TheSelect->getOperand(1).getNode(); 7382 7383 if ((LLD->hasAnyUseOfValue(1) && 7384 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))) || 7385 (LLD->hasAnyUseOfValue(1) && 7386 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS)))) 7387 return false; 7388 7389 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(), 7390 LLD->getBasePtr().getValueType(), 7391 TheSelect->getOperand(0), 7392 TheSelect->getOperand(1), 7393 LLD->getBasePtr(), RLD->getBasePtr(), 7394 TheSelect->getOperand(4)); 7395 } 7396 7397 SDValue Load; 7398 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) { 7399 Load = DAG.getLoad(TheSelect->getValueType(0), 7400 TheSelect->getDebugLoc(), 7401 // FIXME: Discards pointer info. 7402 LLD->getChain(), Addr, MachinePointerInfo(), 7403 LLD->isVolatile(), LLD->isNonTemporal(), 7404 LLD->getAlignment()); 7405 } else { 7406 Load = DAG.getExtLoad(LLD->getExtensionType() == ISD::EXTLOAD ? 7407 RLD->getExtensionType() : LLD->getExtensionType(), 7408 TheSelect->getDebugLoc(), 7409 TheSelect->getValueType(0), 7410 // FIXME: Discards pointer info. 7411 LLD->getChain(), Addr, MachinePointerInfo(), 7412 LLD->getMemoryVT(), LLD->isVolatile(), 7413 LLD->isNonTemporal(), LLD->getAlignment()); 7414 } 7415 7416 // Users of the select now use the result of the load. 7417 CombineTo(TheSelect, Load); 7418 7419 // Users of the old loads now use the new load's chain. We know the 7420 // old-load value is dead now. 7421 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); 7422 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); 7423 return true; 7424 } 7425 7426 return false; 7427} 7428 7429/// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3 7430/// where 'cond' is the comparison specified by CC. 7431SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, 7432 SDValue N2, SDValue N3, 7433 ISD::CondCode CC, bool NotExtCompare) { 7434 // (x ? y : y) -> y. 7435 if (N2 == N3) return N2; 7436 7437 EVT VT = N2.getValueType(); 7438 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 7439 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 7440 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); 7441 7442 // Determine if the condition we're dealing with is constant 7443 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 7444 N0, N1, CC, DL, false); 7445 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 7446 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode()); 7447 7448 // fold select_cc true, x, y -> x 7449 if (SCCC && !SCCC->isNullValue()) 7450 return N2; 7451 // fold select_cc false, x, y -> y 7452 if (SCCC && SCCC->isNullValue()) 7453 return N3; 7454 7455 // Check to see if we can simplify the select into an fabs node 7456 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 7457 // Allow either -0.0 or 0.0 7458 if (CFP->getValueAPF().isZero()) { 7459 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 7460 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 7461 N0 == N2 && N3.getOpcode() == ISD::FNEG && 7462 N2 == N3.getOperand(0)) 7463 return DAG.getNode(ISD::FABS, DL, VT, N0); 7464 7465 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 7466 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 7467 N0 == N3 && N2.getOpcode() == ISD::FNEG && 7468 N2.getOperand(0) == N3) 7469 return DAG.getNode(ISD::FABS, DL, VT, N3); 7470 } 7471 } 7472 7473 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)" 7474 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0 7475 // in it. This is a win when the constant is not otherwise available because 7476 // it replaces two constant pool loads with one. We only do this if the FP 7477 // type is known to be legal, because if it isn't, then we are before legalize 7478 // types an we want the other legalization to happen first (e.g. to avoid 7479 // messing with soft float) and if the ConstantFP is not legal, because if 7480 // it is legal, we may not need to store the FP constant in a constant pool. 7481 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2)) 7482 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) { 7483 if (TLI.isTypeLegal(N2.getValueType()) && 7484 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) != 7485 TargetLowering::Legal) && 7486 // If both constants have multiple uses, then we won't need to do an 7487 // extra load, they are likely around in registers for other users. 7488 (TV->hasOneUse() || FV->hasOneUse())) { 7489 Constant *Elts[] = { 7490 const_cast<ConstantFP*>(FV->getConstantFPValue()), 7491 const_cast<ConstantFP*>(TV->getConstantFPValue()) 7492 }; 7493 Type *FPTy = Elts[0]->getType(); 7494 const TargetData &TD = *TLI.getTargetData(); 7495 7496 // Create a ConstantArray of the two constants. 7497 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts); 7498 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(), 7499 TD.getPrefTypeAlignment(FPTy)); 7500 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 7501 7502 // Get the offsets to the 0 and 1 element of the array so that we can 7503 // select between them. 7504 SDValue Zero = DAG.getIntPtrConstant(0); 7505 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType()); 7506 SDValue One = DAG.getIntPtrConstant(EltSize); 7507 7508 SDValue Cond = DAG.getSetCC(DL, 7509 TLI.getSetCCResultType(N0.getValueType()), 7510 N0, N1, CC); 7511 AddToWorkList(Cond.getNode()); 7512 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(), 7513 Cond, One, Zero); 7514 AddToWorkList(CstOffset.getNode()); 7515 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx, 7516 CstOffset); 7517 AddToWorkList(CPIdx.getNode()); 7518 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx, 7519 MachinePointerInfo::getConstantPool(), false, 7520 false, Alignment); 7521 7522 } 7523 } 7524 7525 // Check to see if we can perform the "gzip trick", transforming 7526 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A) 7527 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 7528 (N1C->isNullValue() || // (a < 0) ? b : 0 7529 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 7530 EVT XType = N0.getValueType(); 7531 EVT AType = N2.getValueType(); 7532 if (XType.bitsGE(AType)) { 7533 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 7534 // single-bit constant. 7535 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 7536 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 7537 ShCtV = XType.getSizeInBits()-ShCtV-1; 7538 SDValue ShCt = DAG.getConstant(ShCtV, 7539 getShiftAmountTy(N0.getValueType())); 7540 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), 7541 XType, N0, ShCt); 7542 AddToWorkList(Shift.getNode()); 7543 7544 if (XType.bitsGT(AType)) { 7545 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 7546 AddToWorkList(Shift.getNode()); 7547 } 7548 7549 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 7550 } 7551 7552 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), 7553 XType, N0, 7554 DAG.getConstant(XType.getSizeInBits()-1, 7555 getShiftAmountTy(N0.getValueType()))); 7556 AddToWorkList(Shift.getNode()); 7557 7558 if (XType.bitsGT(AType)) { 7559 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 7560 AddToWorkList(Shift.getNode()); 7561 } 7562 7563 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 7564 } 7565 } 7566 7567 // fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A) 7568 // where y is has a single bit set. 7569 // A plaintext description would be, we can turn the SELECT_CC into an AND 7570 // when the condition can be materialized as an all-ones register. Any 7571 // single bit-test can be materialized as an all-ones register with 7572 // shift-left and shift-right-arith. 7573 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND && 7574 N0->getValueType(0) == VT && 7575 N1C && N1C->isNullValue() && 7576 N2C && N2C->isNullValue()) { 7577 SDValue AndLHS = N0->getOperand(0); 7578 ConstantSDNode *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1)); 7579 if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) { 7580 // Shift the tested bit over the sign bit. 7581 APInt AndMask = ConstAndRHS->getAPIntValue(); 7582 SDValue ShlAmt = 7583 DAG.getConstant(AndMask.countLeadingZeros(), 7584 getShiftAmountTy(AndLHS.getValueType())); 7585 SDValue Shl = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, AndLHS, ShlAmt); 7586 7587 // Now arithmetic right shift it all the way over, so the result is either 7588 // all-ones, or zero. 7589 SDValue ShrAmt = 7590 DAG.getConstant(AndMask.getBitWidth()-1, 7591 getShiftAmountTy(Shl.getValueType())); 7592 SDValue Shr = DAG.getNode(ISD::SRA, N0.getDebugLoc(), VT, Shl, ShrAmt); 7593 7594 return DAG.getNode(ISD::AND, DL, VT, Shr, N3); 7595 } 7596 } 7597 7598 // fold select C, 16, 0 -> shl C, 4 7599 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 7600 TLI.getBooleanContents(N0.getValueType().isVector()) == 7601 TargetLowering::ZeroOrOneBooleanContent) { 7602 7603 // If the caller doesn't want us to simplify this into a zext of a compare, 7604 // don't do it. 7605 if (NotExtCompare && N2C->getAPIntValue() == 1) 7606 return SDValue(); 7607 7608 // Get a SetCC of the condition 7609 // FIXME: Should probably make sure that setcc is legal if we ever have a 7610 // target where it isn't. 7611 SDValue Temp, SCC; 7612 // cast from setcc result type to select result type 7613 if (LegalTypes) { 7614 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()), 7615 N0, N1, CC); 7616 if (N2.getValueType().bitsLT(SCC.getValueType())) 7617 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType()); 7618 else 7619 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 7620 N2.getValueType(), SCC); 7621 } else { 7622 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC); 7623 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 7624 N2.getValueType(), SCC); 7625 } 7626 7627 AddToWorkList(SCC.getNode()); 7628 AddToWorkList(Temp.getNode()); 7629 7630 if (N2C->getAPIntValue() == 1) 7631 return Temp; 7632 7633 // shl setcc result by log2 n2c 7634 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp, 7635 DAG.getConstant(N2C->getAPIntValue().logBase2(), 7636 getShiftAmountTy(Temp.getValueType()))); 7637 } 7638 7639 // Check to see if this is the equivalent of setcc 7640 // FIXME: Turn all of these into setcc if setcc if setcc is legal 7641 // otherwise, go ahead with the folds. 7642 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 7643 EVT XType = N0.getValueType(); 7644 if (!LegalOperations || 7645 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) { 7646 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC); 7647 if (Res.getValueType() != VT) 7648 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res); 7649 return Res; 7650 } 7651 7652 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X)))) 7653 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 7654 (!LegalOperations || 7655 TLI.isOperationLegal(ISD::CTLZ, XType))) { 7656 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0); 7657 return DAG.getNode(ISD::SRL, DL, XType, Ctlz, 7658 DAG.getConstant(Log2_32(XType.getSizeInBits()), 7659 getShiftAmountTy(Ctlz.getValueType()))); 7660 } 7661 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1)) 7662 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 7663 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(), 7664 XType, DAG.getConstant(0, XType), N0); 7665 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType); 7666 return DAG.getNode(ISD::SRL, DL, XType, 7667 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0), 7668 DAG.getConstant(XType.getSizeInBits()-1, 7669 getShiftAmountTy(XType))); 7670 } 7671 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1)) 7672 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 7673 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0, 7674 DAG.getConstant(XType.getSizeInBits()-1, 7675 getShiftAmountTy(N0.getValueType()))); 7676 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType)); 7677 } 7678 } 7679 7680 // Check to see if this is an integer abs. 7681 // select_cc setg[te] X, 0, X, -X -> 7682 // select_cc setgt X, -1, X, -X -> 7683 // select_cc setl[te] X, 0, -X, X -> 7684 // select_cc setlt X, 1, -X, X -> 7685 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 7686 if (N1C) { 7687 ConstantSDNode *SubC = NULL; 7688 if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) || 7689 (N1C->isAllOnesValue() && CC == ISD::SETGT)) && 7690 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) 7691 SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0)); 7692 else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) || 7693 (N1C->isOne() && CC == ISD::SETLT)) && 7694 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) 7695 SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0)); 7696 7697 EVT XType = N0.getValueType(); 7698 if (SubC && SubC->isNullValue() && XType.isInteger()) { 7699 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, 7700 N0, 7701 DAG.getConstant(XType.getSizeInBits()-1, 7702 getShiftAmountTy(N0.getValueType()))); 7703 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), 7704 XType, N0, Shift); 7705 AddToWorkList(Shift.getNode()); 7706 AddToWorkList(Add.getNode()); 7707 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 7708 } 7709 } 7710 7711 return SDValue(); 7712} 7713 7714/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 7715SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0, 7716 SDValue N1, ISD::CondCode Cond, 7717 DebugLoc DL, bool foldBooleans) { 7718 TargetLowering::DAGCombinerInfo 7719 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 7720 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL); 7721} 7722 7723/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 7724/// return a DAG expression to select that will generate the same value by 7725/// multiplying by a magic number. See: 7726/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 7727SDValue DAGCombiner::BuildSDIV(SDNode *N) { 7728 std::vector<SDNode*> Built; 7729 SDValue S = TLI.BuildSDIV(N, DAG, &Built); 7730 7731 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 7732 ii != ee; ++ii) 7733 AddToWorkList(*ii); 7734 return S; 7735} 7736 7737/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 7738/// return a DAG expression to select that will generate the same value by 7739/// multiplying by a magic number. See: 7740/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 7741SDValue DAGCombiner::BuildUDIV(SDNode *N) { 7742 std::vector<SDNode*> Built; 7743 SDValue S = TLI.BuildUDIV(N, DAG, &Built); 7744 7745 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 7746 ii != ee; ++ii) 7747 AddToWorkList(*ii); 7748 return S; 7749} 7750 7751/// FindBaseOffset - Return true if base is a frame index, which is known not 7752// to alias with anything but itself. Provides base object and offset as 7753// results. 7754static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset, 7755 const GlobalValue *&GV, void *&CV) { 7756 // Assume it is a primitive operation. 7757 Base = Ptr; Offset = 0; GV = 0; CV = 0; 7758 7759 // If it's an adding a simple constant then integrate the offset. 7760 if (Base.getOpcode() == ISD::ADD) { 7761 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 7762 Base = Base.getOperand(0); 7763 Offset += C->getZExtValue(); 7764 } 7765 } 7766 7767 // Return the underlying GlobalValue, and update the Offset. Return false 7768 // for GlobalAddressSDNode since the same GlobalAddress may be represented 7769 // by multiple nodes with different offsets. 7770 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) { 7771 GV = G->getGlobal(); 7772 Offset += G->getOffset(); 7773 return false; 7774 } 7775 7776 // Return the underlying Constant value, and update the Offset. Return false 7777 // for ConstantSDNodes since the same constant pool entry may be represented 7778 // by multiple nodes with different offsets. 7779 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) { 7780 CV = C->isMachineConstantPoolEntry() ? (void *)C->getMachineCPVal() 7781 : (void *)C->getConstVal(); 7782 Offset += C->getOffset(); 7783 return false; 7784 } 7785 // If it's any of the following then it can't alias with anything but itself. 7786 return isa<FrameIndexSDNode>(Base); 7787} 7788 7789/// isAlias - Return true if there is any possibility that the two addresses 7790/// overlap. 7791bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, 7792 const Value *SrcValue1, int SrcValueOffset1, 7793 unsigned SrcValueAlign1, 7794 const MDNode *TBAAInfo1, 7795 SDValue Ptr2, int64_t Size2, 7796 const Value *SrcValue2, int SrcValueOffset2, 7797 unsigned SrcValueAlign2, 7798 const MDNode *TBAAInfo2) const { 7799 // If they are the same then they must be aliases. 7800 if (Ptr1 == Ptr2) return true; 7801 7802 // Gather base node and offset information. 7803 SDValue Base1, Base2; 7804 int64_t Offset1, Offset2; 7805 const GlobalValue *GV1, *GV2; 7806 void *CV1, *CV2; 7807 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1); 7808 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2); 7809 7810 // If they have a same base address then check to see if they overlap. 7811 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2))) 7812 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 7813 7814 // It is possible for different frame indices to alias each other, mostly 7815 // when tail call optimization reuses return address slots for arguments. 7816 // To catch this case, look up the actual index of frame indices to compute 7817 // the real alias relationship. 7818 if (isFrameIndex1 && isFrameIndex2) { 7819 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7820 Offset1 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base1)->getIndex()); 7821 Offset2 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base2)->getIndex()); 7822 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 7823 } 7824 7825 // Otherwise, if we know what the bases are, and they aren't identical, then 7826 // we know they cannot alias. 7827 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2)) 7828 return false; 7829 7830 // If we know required SrcValue1 and SrcValue2 have relatively large alignment 7831 // compared to the size and offset of the access, we may be able to prove they 7832 // do not alias. This check is conservative for now to catch cases created by 7833 // splitting vector types. 7834 if ((SrcValueAlign1 == SrcValueAlign2) && 7835 (SrcValueOffset1 != SrcValueOffset2) && 7836 (Size1 == Size2) && (SrcValueAlign1 > Size1)) { 7837 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1; 7838 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1; 7839 7840 // There is no overlap between these relatively aligned accesses of similar 7841 // size, return no alias. 7842 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1) 7843 return false; 7844 } 7845 7846 if (CombinerGlobalAA) { 7847 // Use alias analysis information. 7848 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 7849 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 7850 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 7851 AliasAnalysis::AliasResult AAResult = 7852 AA.alias(AliasAnalysis::Location(SrcValue1, Overlap1, TBAAInfo1), 7853 AliasAnalysis::Location(SrcValue2, Overlap2, TBAAInfo2)); 7854 if (AAResult == AliasAnalysis::NoAlias) 7855 return false; 7856 } 7857 7858 // Otherwise we have to assume they alias. 7859 return true; 7860} 7861 7862/// FindAliasInfo - Extracts the relevant alias information from the memory 7863/// node. Returns true if the operand was a load. 7864bool DAGCombiner::FindAliasInfo(SDNode *N, 7865 SDValue &Ptr, int64_t &Size, 7866 const Value *&SrcValue, 7867 int &SrcValueOffset, 7868 unsigned &SrcValueAlign, 7869 const MDNode *&TBAAInfo) const { 7870 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 7871 Ptr = LD->getBasePtr(); 7872 Size = LD->getMemoryVT().getSizeInBits() >> 3; 7873 SrcValue = LD->getSrcValue(); 7874 SrcValueOffset = LD->getSrcValueOffset(); 7875 SrcValueAlign = LD->getOriginalAlignment(); 7876 TBAAInfo = LD->getTBAAInfo(); 7877 return true; 7878 } 7879 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 7880 Ptr = ST->getBasePtr(); 7881 Size = ST->getMemoryVT().getSizeInBits() >> 3; 7882 SrcValue = ST->getSrcValue(); 7883 SrcValueOffset = ST->getSrcValueOffset(); 7884 SrcValueAlign = ST->getOriginalAlignment(); 7885 TBAAInfo = ST->getTBAAInfo(); 7886 return false; 7887 } 7888 llvm_unreachable("FindAliasInfo expected a memory operand"); 7889} 7890 7891/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 7892/// looking for aliasing nodes and adding them to the Aliases vector. 7893void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 7894 SmallVector<SDValue, 8> &Aliases) { 7895 SmallVector<SDValue, 8> Chains; // List of chains to visit. 7896 SmallPtrSet<SDNode *, 16> Visited; // Visited node set. 7897 7898 // Get alias information for node. 7899 SDValue Ptr; 7900 int64_t Size; 7901 const Value *SrcValue; 7902 int SrcValueOffset; 7903 unsigned SrcValueAlign; 7904 const MDNode *SrcTBAAInfo; 7905 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset, 7906 SrcValueAlign, SrcTBAAInfo); 7907 7908 // Starting off. 7909 Chains.push_back(OriginalChain); 7910 unsigned Depth = 0; 7911 7912 // Look at each chain and determine if it is an alias. If so, add it to the 7913 // aliases list. If not, then continue up the chain looking for the next 7914 // candidate. 7915 while (!Chains.empty()) { 7916 SDValue Chain = Chains.back(); 7917 Chains.pop_back(); 7918 7919 // For TokenFactor nodes, look at each operand and only continue up the 7920 // chain until we find two aliases. If we've seen two aliases, assume we'll 7921 // find more and revert to original chain since the xform is unlikely to be 7922 // profitable. 7923 // 7924 // FIXME: The depth check could be made to return the last non-aliasing 7925 // chain we found before we hit a tokenfactor rather than the original 7926 // chain. 7927 if (Depth > 6 || Aliases.size() == 2) { 7928 Aliases.clear(); 7929 Aliases.push_back(OriginalChain); 7930 break; 7931 } 7932 7933 // Don't bother if we've been before. 7934 if (!Visited.insert(Chain.getNode())) 7935 continue; 7936 7937 switch (Chain.getOpcode()) { 7938 case ISD::EntryToken: 7939 // Entry token is ideal chain operand, but handled in FindBetterChain. 7940 break; 7941 7942 case ISD::LOAD: 7943 case ISD::STORE: { 7944 // Get alias information for Chain. 7945 SDValue OpPtr; 7946 int64_t OpSize; 7947 const Value *OpSrcValue; 7948 int OpSrcValueOffset; 7949 unsigned OpSrcValueAlign; 7950 const MDNode *OpSrcTBAAInfo; 7951 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, 7952 OpSrcValue, OpSrcValueOffset, 7953 OpSrcValueAlign, 7954 OpSrcTBAAInfo); 7955 7956 // If chain is alias then stop here. 7957 if (!(IsLoad && IsOpLoad) && 7958 isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign, 7959 SrcTBAAInfo, 7960 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset, 7961 OpSrcValueAlign, OpSrcTBAAInfo)) { 7962 Aliases.push_back(Chain); 7963 } else { 7964 // Look further up the chain. 7965 Chains.push_back(Chain.getOperand(0)); 7966 ++Depth; 7967 } 7968 break; 7969 } 7970 7971 case ISD::TokenFactor: 7972 // We have to check each of the operands of the token factor for "small" 7973 // token factors, so we queue them up. Adding the operands to the queue 7974 // (stack) in reverse order maintains the original order and increases the 7975 // likelihood that getNode will find a matching token factor (CSE.) 7976 if (Chain.getNumOperands() > 16) { 7977 Aliases.push_back(Chain); 7978 break; 7979 } 7980 for (unsigned n = Chain.getNumOperands(); n;) 7981 Chains.push_back(Chain.getOperand(--n)); 7982 ++Depth; 7983 break; 7984 7985 default: 7986 // For all other instructions we will just have to take what we can get. 7987 Aliases.push_back(Chain); 7988 break; 7989 } 7990 } 7991} 7992 7993/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 7994/// for a better chain (aliasing node.) 7995SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 7996 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 7997 7998 // Accumulate all the aliases to this node. 7999 GatherAllAliases(N, OldChain, Aliases); 8000 8001 // If no operands then chain to entry token. 8002 if (Aliases.size() == 0) 8003 return DAG.getEntryNode(); 8004 8005 // If a single operand then chain to it. We don't need to revisit it. 8006 if (Aliases.size() == 1) 8007 return Aliases[0]; 8008 8009 // Construct a custom tailored token factor. 8010 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 8011 &Aliases[0], Aliases.size()); 8012} 8013 8014// SelectionDAG::Combine - This is the entry point for the file. 8015// 8016void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, 8017 CodeGenOpt::Level OptLevel) { 8018 /// run - This is the main entry point to this class. 8019 /// 8020 DAGCombiner(*this, AA, OptLevel).Run(Level); 8021} 8022