DAGCombiner.cpp revision fdb230a154ead49cf0ded5b4587be994ec2f43e0
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// This pass is not a substitute for the LLVM IR instcombine pass. This pass is 14// primarily intended to handle simplification opportunities that are implicit 15// in the LLVM IR and exposed by the various codegen lowering phases. 16// 17//===----------------------------------------------------------------------===// 18 19#define DEBUG_TYPE "dagcombine" 20#include "llvm/CodeGen/SelectionDAG.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/LLVMContext.h" 23#include "llvm/CodeGen/MachineFunction.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/Analysis/AliasAnalysis.h" 26#include "llvm/Target/TargetData.h" 27#include "llvm/Target/TargetLowering.h" 28#include "llvm/Target/TargetMachine.h" 29#include "llvm/Target/TargetOptions.h" 30#include "llvm/ADT/SmallPtrSet.h" 31#include "llvm/ADT/Statistic.h" 32#include "llvm/Support/CommandLine.h" 33#include "llvm/Support/Debug.h" 34#include "llvm/Support/ErrorHandling.h" 35#include "llvm/Support/MathExtras.h" 36#include "llvm/Support/raw_ostream.h" 37#include <algorithm> 38using namespace llvm; 39 40STATISTIC(NodesCombined , "Number of dag nodes combined"); 41STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 42STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 43STATISTIC(OpsNarrowed , "Number of load/op/store narrowed"); 44STATISTIC(LdStFP2Int , "Number of fp load/store pairs transformed to int"); 45 46namespace { 47 static cl::opt<bool> 48 CombinerAA("combiner-alias-analysis", cl::Hidden, 49 cl::desc("Turn on alias analysis during testing")); 50 51 static cl::opt<bool> 52 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 53 cl::desc("Include global information in alias analysis")); 54 55//------------------------------ DAGCombiner ---------------------------------// 56 57 class DAGCombiner { 58 SelectionDAG &DAG; 59 const TargetLowering &TLI; 60 CombineLevel Level; 61 CodeGenOpt::Level OptLevel; 62 bool LegalOperations; 63 bool LegalTypes; 64 65 // Worklist of all of the nodes that need to be simplified. 66 // 67 // This has the semantics that when adding to the worklist, 68 // the item added must be next to be processed. It should 69 // also only appear once. The naive approach to this takes 70 // linear time. 71 // 72 // To reduce the insert/remove time to logarithmic, we use 73 // a set and a vector to maintain our worklist. 74 // 75 // The set contains the items on the worklist, but does not 76 // maintain the order they should be visited. 77 // 78 // The vector maintains the order nodes should be visited, but may 79 // contain duplicate or removed nodes. When choosing a node to 80 // visit, we pop off the order stack until we find an item that is 81 // also in the contents set. All operations are O(log N). 82 SmallPtrSet<SDNode*, 64> WorkListContents; 83 SmallVector<SDNode*, 64> WorkListOrder; 84 85 // AA - Used for DAG load/store alias analysis. 86 AliasAnalysis &AA; 87 88 /// AddUsersToWorkList - When an instruction is simplified, add all users of 89 /// the instruction to the work lists because they might get more simplified 90 /// now. 91 /// 92 void AddUsersToWorkList(SDNode *N) { 93 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 94 UI != UE; ++UI) 95 AddToWorkList(*UI); 96 } 97 98 /// visit - call the node-specific routine that knows how to fold each 99 /// particular type of node. 100 SDValue visit(SDNode *N); 101 102 public: 103 /// AddToWorkList - Add to the work list making sure its instance is at the 104 /// back (next to be processed.) 105 void AddToWorkList(SDNode *N) { 106 WorkListContents.insert(N); 107 WorkListOrder.push_back(N); 108 } 109 110 /// removeFromWorkList - remove all instances of N from the worklist. 111 /// 112 void removeFromWorkList(SDNode *N) { 113 WorkListContents.erase(N); 114 } 115 116 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 117 bool AddTo = true); 118 119 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 120 return CombineTo(N, &Res, 1, AddTo); 121 } 122 123 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 124 bool AddTo = true) { 125 SDValue To[] = { Res0, Res1 }; 126 return CombineTo(N, To, 2, AddTo); 127 } 128 129 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO); 130 131 private: 132 133 /// SimplifyDemandedBits - Check the specified integer node value to see if 134 /// it can be simplified or if things it uses can be simplified by bit 135 /// propagation. If so, return true. 136 bool SimplifyDemandedBits(SDValue Op) { 137 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits(); 138 APInt Demanded = APInt::getAllOnesValue(BitWidth); 139 return SimplifyDemandedBits(Op, Demanded); 140 } 141 142 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 143 144 bool CombineToPreIndexedLoadStore(SDNode *N); 145 bool CombineToPostIndexedLoadStore(SDNode *N); 146 147 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad); 148 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace); 149 SDValue SExtPromoteOperand(SDValue Op, EVT PVT); 150 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT); 151 SDValue PromoteIntBinOp(SDValue Op); 152 SDValue PromoteIntShiftOp(SDValue Op); 153 SDValue PromoteExtend(SDValue Op); 154 bool PromoteLoad(SDValue Op); 155 156 void ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs, 157 SDValue Trunc, SDValue ExtLoad, DebugLoc DL, 158 ISD::NodeType ExtType); 159 160 /// combine - call the node-specific routine that knows how to fold each 161 /// particular type of node. If that doesn't do anything, try the 162 /// target-specific DAG combines. 163 SDValue combine(SDNode *N); 164 165 // Visitation implementation - Implement dag node combining for different 166 // node types. The semantics are as follows: 167 // Return Value: 168 // SDValue.getNode() == 0 - No change was made 169 // SDValue.getNode() == N - N was replaced, is dead and has been handled. 170 // otherwise - N should be replaced by the returned Operand. 171 // 172 SDValue visitTokenFactor(SDNode *N); 173 SDValue visitMERGE_VALUES(SDNode *N); 174 SDValue visitADD(SDNode *N); 175 SDValue visitSUB(SDNode *N); 176 SDValue visitADDC(SDNode *N); 177 SDValue visitSUBC(SDNode *N); 178 SDValue visitADDE(SDNode *N); 179 SDValue visitSUBE(SDNode *N); 180 SDValue visitMUL(SDNode *N); 181 SDValue visitSDIV(SDNode *N); 182 SDValue visitUDIV(SDNode *N); 183 SDValue visitSREM(SDNode *N); 184 SDValue visitUREM(SDNode *N); 185 SDValue visitMULHU(SDNode *N); 186 SDValue visitMULHS(SDNode *N); 187 SDValue visitSMUL_LOHI(SDNode *N); 188 SDValue visitUMUL_LOHI(SDNode *N); 189 SDValue visitSMULO(SDNode *N); 190 SDValue visitUMULO(SDNode *N); 191 SDValue visitSDIVREM(SDNode *N); 192 SDValue visitUDIVREM(SDNode *N); 193 SDValue visitAND(SDNode *N); 194 SDValue visitOR(SDNode *N); 195 SDValue visitXOR(SDNode *N); 196 SDValue SimplifyVBinOp(SDNode *N); 197 SDValue visitSHL(SDNode *N); 198 SDValue visitSRA(SDNode *N); 199 SDValue visitSRL(SDNode *N); 200 SDValue visitCTLZ(SDNode *N); 201 SDValue visitCTLZ_ZERO_UNDEF(SDNode *N); 202 SDValue visitCTTZ(SDNode *N); 203 SDValue visitCTTZ_ZERO_UNDEF(SDNode *N); 204 SDValue visitCTPOP(SDNode *N); 205 SDValue visitSELECT(SDNode *N); 206 SDValue visitSELECT_CC(SDNode *N); 207 SDValue visitSETCC(SDNode *N); 208 SDValue visitSIGN_EXTEND(SDNode *N); 209 SDValue visitZERO_EXTEND(SDNode *N); 210 SDValue visitANY_EXTEND(SDNode *N); 211 SDValue visitSIGN_EXTEND_INREG(SDNode *N); 212 SDValue visitTRUNCATE(SDNode *N); 213 SDValue visitBITCAST(SDNode *N); 214 SDValue visitBUILD_PAIR(SDNode *N); 215 SDValue visitFADD(SDNode *N); 216 SDValue visitFSUB(SDNode *N); 217 SDValue visitFMUL(SDNode *N); 218 SDValue visitFDIV(SDNode *N); 219 SDValue visitFREM(SDNode *N); 220 SDValue visitFCOPYSIGN(SDNode *N); 221 SDValue visitSINT_TO_FP(SDNode *N); 222 SDValue visitUINT_TO_FP(SDNode *N); 223 SDValue visitFP_TO_SINT(SDNode *N); 224 SDValue visitFP_TO_UINT(SDNode *N); 225 SDValue visitFP_ROUND(SDNode *N); 226 SDValue visitFP_ROUND_INREG(SDNode *N); 227 SDValue visitFP_EXTEND(SDNode *N); 228 SDValue visitFNEG(SDNode *N); 229 SDValue visitFABS(SDNode *N); 230 SDValue visitBRCOND(SDNode *N); 231 SDValue visitBR_CC(SDNode *N); 232 SDValue visitLOAD(SDNode *N); 233 SDValue visitSTORE(SDNode *N); 234 SDValue visitINSERT_VECTOR_ELT(SDNode *N); 235 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 236 SDValue visitBUILD_VECTOR(SDNode *N); 237 SDValue visitCONCAT_VECTORS(SDNode *N); 238 SDValue visitEXTRACT_SUBVECTOR(SDNode *N); 239 SDValue visitVECTOR_SHUFFLE(SDNode *N); 240 SDValue visitMEMBARRIER(SDNode *N); 241 242 SDValue XformToShuffleWithZero(SDNode *N); 243 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS); 244 245 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 246 247 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 248 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 249 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2); 250 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2, 251 SDValue N3, ISD::CondCode CC, 252 bool NotExtCompare = false); 253 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 254 DebugLoc DL, bool foldBooleans = true); 255 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 256 unsigned HiOp); 257 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT); 258 SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT); 259 SDValue BuildSDIV(SDNode *N); 260 SDValue BuildUDIV(SDNode *N); 261 SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1, 262 bool DemandHighBits = true); 263 SDValue MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1); 264 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL); 265 SDValue ReduceLoadWidth(SDNode *N); 266 SDValue ReduceLoadOpStoreWidth(SDNode *N); 267 SDValue TransformFPLoadStorePair(SDNode *N); 268 269 SDValue GetDemandedBits(SDValue V, const APInt &Mask); 270 271 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 272 /// looking for aliasing nodes and adding them to the Aliases vector. 273 void GatherAllAliases(SDNode *N, SDValue OriginalChain, 274 SmallVector<SDValue, 8> &Aliases); 275 276 /// isAlias - Return true if there is any possibility that the two addresses 277 /// overlap. 278 bool isAlias(SDValue Ptr1, int64_t Size1, 279 const Value *SrcValue1, int SrcValueOffset1, 280 unsigned SrcValueAlign1, 281 const MDNode *TBAAInfo1, 282 SDValue Ptr2, int64_t Size2, 283 const Value *SrcValue2, int SrcValueOffset2, 284 unsigned SrcValueAlign2, 285 const MDNode *TBAAInfo2) const; 286 287 /// FindAliasInfo - Extracts the relevant alias information from the memory 288 /// node. Returns true if the operand was a load. 289 bool FindAliasInfo(SDNode *N, 290 SDValue &Ptr, int64_t &Size, 291 const Value *&SrcValue, int &SrcValueOffset, 292 unsigned &SrcValueAlignment, 293 const MDNode *&TBAAInfo) const; 294 295 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 296 /// looking for a better chain (aliasing node.) 297 SDValue FindBetterChain(SDNode *N, SDValue Chain); 298 299 public: 300 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL) 301 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(BeforeLegalizeTypes), 302 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {} 303 304 /// Run - runs the dag combiner on all nodes in the work list 305 void Run(CombineLevel AtLevel); 306 307 SelectionDAG &getDAG() const { return DAG; } 308 309 /// getShiftAmountTy - Returns a type large enough to hold any valid 310 /// shift amount - before type legalization these can be huge. 311 EVT getShiftAmountTy(EVT LHSTy) { 312 return LegalTypes ? TLI.getShiftAmountTy(LHSTy) : TLI.getPointerTy(); 313 } 314 315 /// isTypeLegal - This method returns true if we are running before type 316 /// legalization or if the specified VT is legal. 317 bool isTypeLegal(const EVT &VT) { 318 if (!LegalTypes) return true; 319 return TLI.isTypeLegal(VT); 320 } 321 }; 322} 323 324 325namespace { 326/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 327/// nodes from the worklist. 328class WorkListRemover : public SelectionDAG::DAGUpdateListener { 329 DAGCombiner &DC; 330public: 331 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {} 332 333 virtual void NodeDeleted(SDNode *N, SDNode *E) { 334 DC.removeFromWorkList(N); 335 } 336 337 virtual void NodeUpdated(SDNode *N) { 338 // Ignore updates. 339 } 340}; 341} 342 343//===----------------------------------------------------------------------===// 344// TargetLowering::DAGCombinerInfo implementation 345//===----------------------------------------------------------------------===// 346 347void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 348 ((DAGCombiner*)DC)->AddToWorkList(N); 349} 350 351void TargetLowering::DAGCombinerInfo::RemoveFromWorklist(SDNode *N) { 352 ((DAGCombiner*)DC)->removeFromWorkList(N); 353} 354 355SDValue TargetLowering::DAGCombinerInfo:: 356CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) { 357 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo); 358} 359 360SDValue TargetLowering::DAGCombinerInfo:: 361CombineTo(SDNode *N, SDValue Res, bool AddTo) { 362 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo); 363} 364 365 366SDValue TargetLowering::DAGCombinerInfo:: 367CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) { 368 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo); 369} 370 371void TargetLowering::DAGCombinerInfo:: 372CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 373 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO); 374} 375 376//===----------------------------------------------------------------------===// 377// Helper Functions 378//===----------------------------------------------------------------------===// 379 380/// isNegatibleForFree - Return 1 if we can compute the negated form of the 381/// specified expression for the same cost as the expression itself, or 2 if we 382/// can compute the negated form more cheaply than the expression itself. 383static char isNegatibleForFree(SDValue Op, bool LegalOperations, 384 const TargetLowering &TLI, 385 const TargetOptions *Options, 386 unsigned Depth = 0) { 387 // No compile time optimizations on this type. 388 if (Op.getValueType() == MVT::ppcf128) 389 return 0; 390 391 // fneg is removable even if it has multiple uses. 392 if (Op.getOpcode() == ISD::FNEG) return 2; 393 394 // Don't allow anything with multiple uses. 395 if (!Op.hasOneUse()) return 0; 396 397 // Don't recurse exponentially. 398 if (Depth > 6) return 0; 399 400 switch (Op.getOpcode()) { 401 default: return false; 402 case ISD::ConstantFP: 403 // Don't invert constant FP values after legalize. The negated constant 404 // isn't necessarily legal. 405 return LegalOperations ? 0 : 1; 406 case ISD::FADD: 407 // FIXME: determine better conditions for this xform. 408 if (!Options->UnsafeFPMath) return 0; 409 410 // After operation legalization, it might not be legal to create new FSUBs. 411 if (LegalOperations && 412 !TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) 413 return 0; 414 415 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B) 416 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, 417 Options, Depth + 1)) 418 return V; 419 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 420 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options, 421 Depth + 1); 422 case ISD::FSUB: 423 // We can't turn -(A-B) into B-A when we honor signed zeros. 424 if (!Options->UnsafeFPMath) return 0; 425 426 // fold (fneg (fsub A, B)) -> (fsub B, A) 427 return 1; 428 429 case ISD::FMUL: 430 case ISD::FDIV: 431 if (Options->HonorSignDependentRoundingFPMath()) return 0; 432 433 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y)) 434 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, 435 Options, Depth + 1)) 436 return V; 437 438 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options, 439 Depth + 1); 440 441 case ISD::FP_EXTEND: 442 case ISD::FP_ROUND: 443 case ISD::FSIN: 444 return isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, Options, 445 Depth + 1); 446 } 447} 448 449/// GetNegatedExpression - If isNegatibleForFree returns true, this function 450/// returns the newly negated expression. 451static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 452 bool LegalOperations, unsigned Depth = 0) { 453 // fneg is removable even if it has multiple uses. 454 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 455 456 // Don't allow anything with multiple uses. 457 assert(Op.hasOneUse() && "Unknown reuse!"); 458 459 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 460 switch (Op.getOpcode()) { 461 default: llvm_unreachable("Unknown code"); 462 case ISD::ConstantFP: { 463 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 464 V.changeSign(); 465 return DAG.getConstantFP(V, Op.getValueType()); 466 } 467 case ISD::FADD: 468 // FIXME: determine better conditions for this xform. 469 assert(DAG.getTarget().Options.UnsafeFPMath); 470 471 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 472 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, 473 DAG.getTargetLoweringInfo(), 474 &DAG.getTarget().Options, Depth+1)) 475 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 476 GetNegatedExpression(Op.getOperand(0), DAG, 477 LegalOperations, Depth+1), 478 Op.getOperand(1)); 479 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 480 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 481 GetNegatedExpression(Op.getOperand(1), DAG, 482 LegalOperations, Depth+1), 483 Op.getOperand(0)); 484 case ISD::FSUB: 485 // We can't turn -(A-B) into B-A when we honor signed zeros. 486 assert(DAG.getTarget().Options.UnsafeFPMath); 487 488 // fold (fneg (fsub 0, B)) -> B 489 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 490 if (N0CFP->getValueAPF().isZero()) 491 return Op.getOperand(1); 492 493 // fold (fneg (fsub A, B)) -> (fsub B, A) 494 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 495 Op.getOperand(1), Op.getOperand(0)); 496 497 case ISD::FMUL: 498 case ISD::FDIV: 499 assert(!DAG.getTarget().Options.HonorSignDependentRoundingFPMath()); 500 501 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) 502 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, 503 DAG.getTargetLoweringInfo(), 504 &DAG.getTarget().Options, Depth+1)) 505 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 506 GetNegatedExpression(Op.getOperand(0), DAG, 507 LegalOperations, Depth+1), 508 Op.getOperand(1)); 509 510 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y)) 511 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 512 Op.getOperand(0), 513 GetNegatedExpression(Op.getOperand(1), DAG, 514 LegalOperations, Depth+1)); 515 516 case ISD::FP_EXTEND: 517 case ISD::FSIN: 518 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 519 GetNegatedExpression(Op.getOperand(0), DAG, 520 LegalOperations, Depth+1)); 521 case ISD::FP_ROUND: 522 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(), 523 GetNegatedExpression(Op.getOperand(0), DAG, 524 LegalOperations, Depth+1), 525 Op.getOperand(1)); 526 } 527} 528 529 530// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 531// that selects between the values 1 and 0, making it equivalent to a setcc. 532// Also, set the incoming LHS, RHS, and CC references to the appropriate 533// nodes based on the type of node we are checking. This simplifies life a 534// bit for the callers. 535static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 536 SDValue &CC) { 537 if (N.getOpcode() == ISD::SETCC) { 538 LHS = N.getOperand(0); 539 RHS = N.getOperand(1); 540 CC = N.getOperand(2); 541 return true; 542 } 543 if (N.getOpcode() == ISD::SELECT_CC && 544 N.getOperand(2).getOpcode() == ISD::Constant && 545 N.getOperand(3).getOpcode() == ISD::Constant && 546 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 547 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 548 LHS = N.getOperand(0); 549 RHS = N.getOperand(1); 550 CC = N.getOperand(4); 551 return true; 552 } 553 return false; 554} 555 556// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 557// one use. If this is true, it allows the users to invert the operation for 558// free when it is profitable to do so. 559static bool isOneUseSetCC(SDValue N) { 560 SDValue N0, N1, N2; 561 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 562 return true; 563 return false; 564} 565 566SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL, 567 SDValue N0, SDValue N1) { 568 EVT VT = N0.getValueType(); 569 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 570 if (isa<ConstantSDNode>(N1)) { 571 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 572 SDValue OpNode = 573 DAG.FoldConstantArithmetic(Opc, VT, 574 cast<ConstantSDNode>(N0.getOperand(1)), 575 cast<ConstantSDNode>(N1)); 576 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode); 577 } 578 if (N0.hasOneUse()) { 579 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 580 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 581 N0.getOperand(0), N1); 582 AddToWorkList(OpNode.getNode()); 583 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1)); 584 } 585 } 586 587 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 588 if (isa<ConstantSDNode>(N0)) { 589 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 590 SDValue OpNode = 591 DAG.FoldConstantArithmetic(Opc, VT, 592 cast<ConstantSDNode>(N1.getOperand(1)), 593 cast<ConstantSDNode>(N0)); 594 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode); 595 } 596 if (N1.hasOneUse()) { 597 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 598 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 599 N1.getOperand(0), N0); 600 AddToWorkList(OpNode.getNode()); 601 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1)); 602 } 603 } 604 605 return SDValue(); 606} 607 608SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 609 bool AddTo) { 610 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 611 ++NodesCombined; 612 DEBUG(dbgs() << "\nReplacing.1 "; 613 N->dump(&DAG); 614 dbgs() << "\nWith: "; 615 To[0].getNode()->dump(&DAG); 616 dbgs() << " and " << NumTo-1 << " other values\n"; 617 for (unsigned i = 0, e = NumTo; i != e; ++i) 618 assert((!To[i].getNode() || 619 N->getValueType(i) == To[i].getValueType()) && 620 "Cannot combine value to value of different type!")); 621 WorkListRemover DeadNodes(*this); 622 DAG.ReplaceAllUsesWith(N, To, &DeadNodes); 623 624 if (AddTo) { 625 // Push the new nodes and any users onto the worklist 626 for (unsigned i = 0, e = NumTo; i != e; ++i) { 627 if (To[i].getNode()) { 628 AddToWorkList(To[i].getNode()); 629 AddUsersToWorkList(To[i].getNode()); 630 } 631 } 632 } 633 634 // Finally, if the node is now dead, remove it from the graph. The node 635 // may not be dead if the replacement process recursively simplified to 636 // something else needing this node. 637 if (N->use_empty()) { 638 // Nodes can be reintroduced into the worklist. Make sure we do not 639 // process a node that has been replaced. 640 removeFromWorkList(N); 641 642 // Finally, since the node is now dead, remove it from the graph. 643 DAG.DeleteNode(N); 644 } 645 return SDValue(N, 0); 646} 647 648void DAGCombiner:: 649CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 650 // Replace all uses. If any nodes become isomorphic to other nodes and 651 // are deleted, make sure to remove them from our worklist. 652 WorkListRemover DeadNodes(*this); 653 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 654 655 // Push the new node and any (possibly new) users onto the worklist. 656 AddToWorkList(TLO.New.getNode()); 657 AddUsersToWorkList(TLO.New.getNode()); 658 659 // Finally, if the node is now dead, remove it from the graph. The node 660 // may not be dead if the replacement process recursively simplified to 661 // something else needing this node. 662 if (TLO.Old.getNode()->use_empty()) { 663 removeFromWorkList(TLO.Old.getNode()); 664 665 // If the operands of this node are only used by the node, they will now 666 // be dead. Make sure to visit them first to delete dead nodes early. 667 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i) 668 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse()) 669 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode()); 670 671 DAG.DeleteNode(TLO.Old.getNode()); 672 } 673} 674 675/// SimplifyDemandedBits - Check the specified integer node value to see if 676/// it can be simplified or if things it uses can be simplified by bit 677/// propagation. If so, return true. 678bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 679 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations); 680 APInt KnownZero, KnownOne; 681 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 682 return false; 683 684 // Revisit the node. 685 AddToWorkList(Op.getNode()); 686 687 // Replace the old value with the new one. 688 ++NodesCombined; 689 DEBUG(dbgs() << "\nReplacing.2 "; 690 TLO.Old.getNode()->dump(&DAG); 691 dbgs() << "\nWith: "; 692 TLO.New.getNode()->dump(&DAG); 693 dbgs() << '\n'); 694 695 CommitTargetLoweringOpt(TLO); 696 return true; 697} 698 699void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) { 700 DebugLoc dl = Load->getDebugLoc(); 701 EVT VT = Load->getValueType(0); 702 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0)); 703 704 DEBUG(dbgs() << "\nReplacing.9 "; 705 Load->dump(&DAG); 706 dbgs() << "\nWith: "; 707 Trunc.getNode()->dump(&DAG); 708 dbgs() << '\n'); 709 WorkListRemover DeadNodes(*this); 710 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc, &DeadNodes); 711 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1), 712 &DeadNodes); 713 removeFromWorkList(Load); 714 DAG.DeleteNode(Load); 715 AddToWorkList(Trunc.getNode()); 716} 717 718SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) { 719 Replace = false; 720 DebugLoc dl = Op.getDebugLoc(); 721 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) { 722 EVT MemVT = LD->getMemoryVT(); 723 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 724 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD 725 : ISD::EXTLOAD) 726 : LD->getExtensionType(); 727 Replace = true; 728 return DAG.getExtLoad(ExtType, dl, PVT, 729 LD->getChain(), LD->getBasePtr(), 730 LD->getPointerInfo(), 731 MemVT, LD->isVolatile(), 732 LD->isNonTemporal(), LD->getAlignment()); 733 } 734 735 unsigned Opc = Op.getOpcode(); 736 switch (Opc) { 737 default: break; 738 case ISD::AssertSext: 739 return DAG.getNode(ISD::AssertSext, dl, PVT, 740 SExtPromoteOperand(Op.getOperand(0), PVT), 741 Op.getOperand(1)); 742 case ISD::AssertZext: 743 return DAG.getNode(ISD::AssertZext, dl, PVT, 744 ZExtPromoteOperand(Op.getOperand(0), PVT), 745 Op.getOperand(1)); 746 case ISD::Constant: { 747 unsigned ExtOpc = 748 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 749 return DAG.getNode(ExtOpc, dl, PVT, Op); 750 } 751 } 752 753 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT)) 754 return SDValue(); 755 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op); 756} 757 758SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) { 759 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT)) 760 return SDValue(); 761 EVT OldVT = Op.getValueType(); 762 DebugLoc dl = Op.getDebugLoc(); 763 bool Replace = false; 764 SDValue NewOp = PromoteOperand(Op, PVT, Replace); 765 if (NewOp.getNode() == 0) 766 return SDValue(); 767 AddToWorkList(NewOp.getNode()); 768 769 if (Replace) 770 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 771 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp, 772 DAG.getValueType(OldVT)); 773} 774 775SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) { 776 EVT OldVT = Op.getValueType(); 777 DebugLoc dl = Op.getDebugLoc(); 778 bool Replace = false; 779 SDValue NewOp = PromoteOperand(Op, PVT, Replace); 780 if (NewOp.getNode() == 0) 781 return SDValue(); 782 AddToWorkList(NewOp.getNode()); 783 784 if (Replace) 785 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 786 return DAG.getZeroExtendInReg(NewOp, dl, OldVT); 787} 788 789/// PromoteIntBinOp - Promote the specified integer binary operation if the 790/// target indicates it is beneficial. e.g. On x86, it's usually better to 791/// promote i16 operations to i32 since i16 instructions are longer. 792SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) { 793 if (!LegalOperations) 794 return SDValue(); 795 796 EVT VT = Op.getValueType(); 797 if (VT.isVector() || !VT.isInteger()) 798 return SDValue(); 799 800 // If operation type is 'undesirable', e.g. i16 on x86, consider 801 // promoting it. 802 unsigned Opc = Op.getOpcode(); 803 if (TLI.isTypeDesirableForOp(Opc, VT)) 804 return SDValue(); 805 806 EVT PVT = VT; 807 // Consult target whether it is a good idea to promote this operation and 808 // what's the right type to promote it to. 809 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 810 assert(PVT != VT && "Don't know what type to promote to!"); 811 812 bool Replace0 = false; 813 SDValue N0 = Op.getOperand(0); 814 SDValue NN0 = PromoteOperand(N0, PVT, Replace0); 815 if (NN0.getNode() == 0) 816 return SDValue(); 817 818 bool Replace1 = false; 819 SDValue N1 = Op.getOperand(1); 820 SDValue NN1; 821 if (N0 == N1) 822 NN1 = NN0; 823 else { 824 NN1 = PromoteOperand(N1, PVT, Replace1); 825 if (NN1.getNode() == 0) 826 return SDValue(); 827 } 828 829 AddToWorkList(NN0.getNode()); 830 if (NN1.getNode()) 831 AddToWorkList(NN1.getNode()); 832 833 if (Replace0) 834 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode()); 835 if (Replace1) 836 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode()); 837 838 DEBUG(dbgs() << "\nPromoting "; 839 Op.getNode()->dump(&DAG)); 840 DebugLoc dl = Op.getDebugLoc(); 841 return DAG.getNode(ISD::TRUNCATE, dl, VT, 842 DAG.getNode(Opc, dl, PVT, NN0, NN1)); 843 } 844 return SDValue(); 845} 846 847/// PromoteIntShiftOp - Promote the specified integer shift operation if the 848/// target indicates it is beneficial. e.g. On x86, it's usually better to 849/// promote i16 operations to i32 since i16 instructions are longer. 850SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) { 851 if (!LegalOperations) 852 return SDValue(); 853 854 EVT VT = Op.getValueType(); 855 if (VT.isVector() || !VT.isInteger()) 856 return SDValue(); 857 858 // If operation type is 'undesirable', e.g. i16 on x86, consider 859 // promoting it. 860 unsigned Opc = Op.getOpcode(); 861 if (TLI.isTypeDesirableForOp(Opc, VT)) 862 return SDValue(); 863 864 EVT PVT = VT; 865 // Consult target whether it is a good idea to promote this operation and 866 // what's the right type to promote it to. 867 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 868 assert(PVT != VT && "Don't know what type to promote to!"); 869 870 bool Replace = false; 871 SDValue N0 = Op.getOperand(0); 872 if (Opc == ISD::SRA) 873 N0 = SExtPromoteOperand(Op.getOperand(0), PVT); 874 else if (Opc == ISD::SRL) 875 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT); 876 else 877 N0 = PromoteOperand(N0, PVT, Replace); 878 if (N0.getNode() == 0) 879 return SDValue(); 880 881 AddToWorkList(N0.getNode()); 882 if (Replace) 883 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode()); 884 885 DEBUG(dbgs() << "\nPromoting "; 886 Op.getNode()->dump(&DAG)); 887 DebugLoc dl = Op.getDebugLoc(); 888 return DAG.getNode(ISD::TRUNCATE, dl, VT, 889 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1))); 890 } 891 return SDValue(); 892} 893 894SDValue DAGCombiner::PromoteExtend(SDValue Op) { 895 if (!LegalOperations) 896 return SDValue(); 897 898 EVT VT = Op.getValueType(); 899 if (VT.isVector() || !VT.isInteger()) 900 return SDValue(); 901 902 // If operation type is 'undesirable', e.g. i16 on x86, consider 903 // promoting it. 904 unsigned Opc = Op.getOpcode(); 905 if (TLI.isTypeDesirableForOp(Opc, VT)) 906 return SDValue(); 907 908 EVT PVT = VT; 909 // Consult target whether it is a good idea to promote this operation and 910 // what's the right type to promote it to. 911 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 912 assert(PVT != VT && "Don't know what type to promote to!"); 913 // fold (aext (aext x)) -> (aext x) 914 // fold (aext (zext x)) -> (zext x) 915 // fold (aext (sext x)) -> (sext x) 916 DEBUG(dbgs() << "\nPromoting "; 917 Op.getNode()->dump(&DAG)); 918 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), VT, Op.getOperand(0)); 919 } 920 return SDValue(); 921} 922 923bool DAGCombiner::PromoteLoad(SDValue Op) { 924 if (!LegalOperations) 925 return false; 926 927 EVT VT = Op.getValueType(); 928 if (VT.isVector() || !VT.isInteger()) 929 return false; 930 931 // If operation type is 'undesirable', e.g. i16 on x86, consider 932 // promoting it. 933 unsigned Opc = Op.getOpcode(); 934 if (TLI.isTypeDesirableForOp(Opc, VT)) 935 return false; 936 937 EVT PVT = VT; 938 // Consult target whether it is a good idea to promote this operation and 939 // what's the right type to promote it to. 940 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 941 assert(PVT != VT && "Don't know what type to promote to!"); 942 943 DebugLoc dl = Op.getDebugLoc(); 944 SDNode *N = Op.getNode(); 945 LoadSDNode *LD = cast<LoadSDNode>(N); 946 EVT MemVT = LD->getMemoryVT(); 947 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 948 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD 949 : ISD::EXTLOAD) 950 : LD->getExtensionType(); 951 SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT, 952 LD->getChain(), LD->getBasePtr(), 953 LD->getPointerInfo(), 954 MemVT, LD->isVolatile(), 955 LD->isNonTemporal(), LD->getAlignment()); 956 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD); 957 958 DEBUG(dbgs() << "\nPromoting "; 959 N->dump(&DAG); 960 dbgs() << "\nTo: "; 961 Result.getNode()->dump(&DAG); 962 dbgs() << '\n'); 963 WorkListRemover DeadNodes(*this); 964 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result, &DeadNodes); 965 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1), &DeadNodes); 966 removeFromWorkList(N); 967 DAG.DeleteNode(N); 968 AddToWorkList(Result.getNode()); 969 return true; 970 } 971 return false; 972} 973 974 975//===----------------------------------------------------------------------===// 976// Main DAG Combiner implementation 977//===----------------------------------------------------------------------===// 978 979void DAGCombiner::Run(CombineLevel AtLevel) { 980 // set the instance variables, so that the various visit routines may use it. 981 Level = AtLevel; 982 LegalOperations = Level >= AfterLegalizeVectorOps; 983 LegalTypes = Level >= AfterLegalizeTypes; 984 985 // Add all the dag nodes to the worklist. 986 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 987 E = DAG.allnodes_end(); I != E; ++I) 988 AddToWorkList(I); 989 990 // Create a dummy node (which is not added to allnodes), that adds a reference 991 // to the root node, preventing it from being deleted, and tracking any 992 // changes of the root. 993 HandleSDNode Dummy(DAG.getRoot()); 994 995 // The root of the dag may dangle to deleted nodes until the dag combiner is 996 // done. Set it to null to avoid confusion. 997 DAG.setRoot(SDValue()); 998 999 // while the worklist isn't empty, find a node and 1000 // try and combine it. 1001 while (!WorkListContents.empty()) { 1002 SDNode *N; 1003 // The WorkListOrder holds the SDNodes in order, but it may contain duplicates. 1004 // In order to avoid a linear scan, we use a set (O(log N)) to hold what the 1005 // worklist *should* contain, and check the node we want to visit is should 1006 // actually be visited. 1007 do { 1008 N = WorkListOrder.pop_back_val(); 1009 } while (!WorkListContents.erase(N)); 1010 1011 // If N has no uses, it is dead. Make sure to revisit all N's operands once 1012 // N is deleted from the DAG, since they too may now be dead or may have a 1013 // reduced number of uses, allowing other xforms. 1014 if (N->use_empty() && N != &Dummy) { 1015 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1016 AddToWorkList(N->getOperand(i).getNode()); 1017 1018 DAG.DeleteNode(N); 1019 continue; 1020 } 1021 1022 SDValue RV = combine(N); 1023 1024 if (RV.getNode() == 0) 1025 continue; 1026 1027 ++NodesCombined; 1028 1029 // If we get back the same node we passed in, rather than a new node or 1030 // zero, we know that the node must have defined multiple values and 1031 // CombineTo was used. Since CombineTo takes care of the worklist 1032 // mechanics for us, we have no work to do in this case. 1033 if (RV.getNode() == N) 1034 continue; 1035 1036 assert(N->getOpcode() != ISD::DELETED_NODE && 1037 RV.getNode()->getOpcode() != ISD::DELETED_NODE && 1038 "Node was deleted but visit returned new node!"); 1039 1040 DEBUG(dbgs() << "\nReplacing.3 "; 1041 N->dump(&DAG); 1042 dbgs() << "\nWith: "; 1043 RV.getNode()->dump(&DAG); 1044 dbgs() << '\n'); 1045 1046 // Transfer debug value. 1047 DAG.TransferDbgValues(SDValue(N, 0), RV); 1048 WorkListRemover DeadNodes(*this); 1049 if (N->getNumValues() == RV.getNode()->getNumValues()) 1050 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes); 1051 else { 1052 assert(N->getValueType(0) == RV.getValueType() && 1053 N->getNumValues() == 1 && "Type mismatch"); 1054 SDValue OpV = RV; 1055 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes); 1056 } 1057 1058 // Push the new node and any users onto the worklist 1059 AddToWorkList(RV.getNode()); 1060 AddUsersToWorkList(RV.getNode()); 1061 1062 // Add any uses of the old node to the worklist in case this node is the 1063 // last one that uses them. They may become dead after this node is 1064 // deleted. 1065 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1066 AddToWorkList(N->getOperand(i).getNode()); 1067 1068 // Finally, if the node is now dead, remove it from the graph. The node 1069 // may not be dead if the replacement process recursively simplified to 1070 // something else needing this node. 1071 if (N->use_empty()) { 1072 // Nodes can be reintroduced into the worklist. Make sure we do not 1073 // process a node that has been replaced. 1074 removeFromWorkList(N); 1075 1076 // Finally, since the node is now dead, remove it from the graph. 1077 DAG.DeleteNode(N); 1078 } 1079 } 1080 1081 // If the root changed (e.g. it was a dead load, update the root). 1082 DAG.setRoot(Dummy.getValue()); 1083} 1084 1085SDValue DAGCombiner::visit(SDNode *N) { 1086 switch (N->getOpcode()) { 1087 default: break; 1088 case ISD::TokenFactor: return visitTokenFactor(N); 1089 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 1090 case ISD::ADD: return visitADD(N); 1091 case ISD::SUB: return visitSUB(N); 1092 case ISD::ADDC: return visitADDC(N); 1093 case ISD::SUBC: return visitSUBC(N); 1094 case ISD::ADDE: return visitADDE(N); 1095 case ISD::SUBE: return visitSUBE(N); 1096 case ISD::MUL: return visitMUL(N); 1097 case ISD::SDIV: return visitSDIV(N); 1098 case ISD::UDIV: return visitUDIV(N); 1099 case ISD::SREM: return visitSREM(N); 1100 case ISD::UREM: return visitUREM(N); 1101 case ISD::MULHU: return visitMULHU(N); 1102 case ISD::MULHS: return visitMULHS(N); 1103 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 1104 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 1105 case ISD::SMULO: return visitSMULO(N); 1106 case ISD::UMULO: return visitUMULO(N); 1107 case ISD::SDIVREM: return visitSDIVREM(N); 1108 case ISD::UDIVREM: return visitUDIVREM(N); 1109 case ISD::AND: return visitAND(N); 1110 case ISD::OR: return visitOR(N); 1111 case ISD::XOR: return visitXOR(N); 1112 case ISD::SHL: return visitSHL(N); 1113 case ISD::SRA: return visitSRA(N); 1114 case ISD::SRL: return visitSRL(N); 1115 case ISD::CTLZ: return visitCTLZ(N); 1116 case ISD::CTLZ_ZERO_UNDEF: return visitCTLZ_ZERO_UNDEF(N); 1117 case ISD::CTTZ: return visitCTTZ(N); 1118 case ISD::CTTZ_ZERO_UNDEF: return visitCTTZ_ZERO_UNDEF(N); 1119 case ISD::CTPOP: return visitCTPOP(N); 1120 case ISD::SELECT: return visitSELECT(N); 1121 case ISD::SELECT_CC: return visitSELECT_CC(N); 1122 case ISD::SETCC: return visitSETCC(N); 1123 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 1124 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 1125 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 1126 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 1127 case ISD::TRUNCATE: return visitTRUNCATE(N); 1128 case ISD::BITCAST: return visitBITCAST(N); 1129 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 1130 case ISD::FADD: return visitFADD(N); 1131 case ISD::FSUB: return visitFSUB(N); 1132 case ISD::FMUL: return visitFMUL(N); 1133 case ISD::FDIV: return visitFDIV(N); 1134 case ISD::FREM: return visitFREM(N); 1135 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 1136 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 1137 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 1138 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 1139 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 1140 case ISD::FP_ROUND: return visitFP_ROUND(N); 1141 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 1142 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 1143 case ISD::FNEG: return visitFNEG(N); 1144 case ISD::FABS: return visitFABS(N); 1145 case ISD::BRCOND: return visitBRCOND(N); 1146 case ISD::BR_CC: return visitBR_CC(N); 1147 case ISD::LOAD: return visitLOAD(N); 1148 case ISD::STORE: return visitSTORE(N); 1149 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 1150 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 1151 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 1152 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 1153 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N); 1154 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 1155 case ISD::MEMBARRIER: return visitMEMBARRIER(N); 1156 } 1157 return SDValue(); 1158} 1159 1160SDValue DAGCombiner::combine(SDNode *N) { 1161 SDValue RV = visit(N); 1162 1163 // If nothing happened, try a target-specific DAG combine. 1164 if (RV.getNode() == 0) { 1165 assert(N->getOpcode() != ISD::DELETED_NODE && 1166 "Node was deleted but visit returned NULL!"); 1167 1168 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 1169 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 1170 1171 // Expose the DAG combiner to the target combiner impls. 1172 TargetLowering::DAGCombinerInfo 1173 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 1174 1175 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 1176 } 1177 } 1178 1179 // If nothing happened still, try promoting the operation. 1180 if (RV.getNode() == 0) { 1181 switch (N->getOpcode()) { 1182 default: break; 1183 case ISD::ADD: 1184 case ISD::SUB: 1185 case ISD::MUL: 1186 case ISD::AND: 1187 case ISD::OR: 1188 case ISD::XOR: 1189 RV = PromoteIntBinOp(SDValue(N, 0)); 1190 break; 1191 case ISD::SHL: 1192 case ISD::SRA: 1193 case ISD::SRL: 1194 RV = PromoteIntShiftOp(SDValue(N, 0)); 1195 break; 1196 case ISD::SIGN_EXTEND: 1197 case ISD::ZERO_EXTEND: 1198 case ISD::ANY_EXTEND: 1199 RV = PromoteExtend(SDValue(N, 0)); 1200 break; 1201 case ISD::LOAD: 1202 if (PromoteLoad(SDValue(N, 0))) 1203 RV = SDValue(N, 0); 1204 break; 1205 } 1206 } 1207 1208 // If N is a commutative binary node, try commuting it to enable more 1209 // sdisel CSE. 1210 if (RV.getNode() == 0 && 1211 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 1212 N->getNumValues() == 1) { 1213 SDValue N0 = N->getOperand(0); 1214 SDValue N1 = N->getOperand(1); 1215 1216 // Constant operands are canonicalized to RHS. 1217 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 1218 SDValue Ops[] = { N1, N0 }; 1219 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 1220 Ops, 2); 1221 if (CSENode) 1222 return SDValue(CSENode, 0); 1223 } 1224 } 1225 1226 return RV; 1227} 1228 1229/// getInputChainForNode - Given a node, return its input chain if it has one, 1230/// otherwise return a null sd operand. 1231static SDValue getInputChainForNode(SDNode *N) { 1232 if (unsigned NumOps = N->getNumOperands()) { 1233 if (N->getOperand(0).getValueType() == MVT::Other) 1234 return N->getOperand(0); 1235 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 1236 return N->getOperand(NumOps-1); 1237 for (unsigned i = 1; i < NumOps-1; ++i) 1238 if (N->getOperand(i).getValueType() == MVT::Other) 1239 return N->getOperand(i); 1240 } 1241 return SDValue(); 1242} 1243 1244SDValue DAGCombiner::visitTokenFactor(SDNode *N) { 1245 // If N has two operands, where one has an input chain equal to the other, 1246 // the 'other' chain is redundant. 1247 if (N->getNumOperands() == 2) { 1248 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) 1249 return N->getOperand(0); 1250 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) 1251 return N->getOperand(1); 1252 } 1253 1254 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 1255 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 1256 SmallPtrSet<SDNode*, 16> SeenOps; 1257 bool Changed = false; // If we should replace this token factor. 1258 1259 // Start out with this token factor. 1260 TFs.push_back(N); 1261 1262 // Iterate through token factors. The TFs grows when new token factors are 1263 // encountered. 1264 for (unsigned i = 0; i < TFs.size(); ++i) { 1265 SDNode *TF = TFs[i]; 1266 1267 // Check each of the operands. 1268 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 1269 SDValue Op = TF->getOperand(i); 1270 1271 switch (Op.getOpcode()) { 1272 case ISD::EntryToken: 1273 // Entry tokens don't need to be added to the list. They are 1274 // rededundant. 1275 Changed = true; 1276 break; 1277 1278 case ISD::TokenFactor: 1279 if (Op.hasOneUse() && 1280 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { 1281 // Queue up for processing. 1282 TFs.push_back(Op.getNode()); 1283 // Clean up in case the token factor is removed. 1284 AddToWorkList(Op.getNode()); 1285 Changed = true; 1286 break; 1287 } 1288 // Fall thru 1289 1290 default: 1291 // Only add if it isn't already in the list. 1292 if (SeenOps.insert(Op.getNode())) 1293 Ops.push_back(Op); 1294 else 1295 Changed = true; 1296 break; 1297 } 1298 } 1299 } 1300 1301 SDValue Result; 1302 1303 // If we've change things around then replace token factor. 1304 if (Changed) { 1305 if (Ops.empty()) { 1306 // The entry token is the only possible outcome. 1307 Result = DAG.getEntryNode(); 1308 } else { 1309 // New and improved token factor. 1310 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 1311 MVT::Other, &Ops[0], Ops.size()); 1312 } 1313 1314 // Don't add users to work list. 1315 return CombineTo(N, Result, false); 1316 } 1317 1318 return Result; 1319} 1320 1321/// MERGE_VALUES can always be eliminated. 1322SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 1323 WorkListRemover DeadNodes(*this); 1324 // Replacing results may cause a different MERGE_VALUES to suddenly 1325 // be CSE'd with N, and carry its uses with it. Iterate until no 1326 // uses remain, to ensure that the node can be safely deleted. 1327 do { 1328 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1329 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i), 1330 &DeadNodes); 1331 } while (!N->use_empty()); 1332 removeFromWorkList(N); 1333 DAG.DeleteNode(N); 1334 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1335} 1336 1337static 1338SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1, 1339 SelectionDAG &DAG) { 1340 EVT VT = N0.getValueType(); 1341 SDValue N00 = N0.getOperand(0); 1342 SDValue N01 = N0.getOperand(1); 1343 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 1344 1345 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && 1346 isa<ConstantSDNode>(N00.getOperand(1))) { 1347 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1348 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, 1349 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT, 1350 N00.getOperand(0), N01), 1351 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT, 1352 N00.getOperand(1), N01)); 1353 return DAG.getNode(ISD::ADD, DL, VT, N0, N1); 1354 } 1355 1356 return SDValue(); 1357} 1358 1359SDValue DAGCombiner::visitADD(SDNode *N) { 1360 SDValue N0 = N->getOperand(0); 1361 SDValue N1 = N->getOperand(1); 1362 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1363 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1364 EVT VT = N0.getValueType(); 1365 1366 // fold vector ops 1367 if (VT.isVector()) { 1368 SDValue FoldedVOp = SimplifyVBinOp(N); 1369 if (FoldedVOp.getNode()) return FoldedVOp; 1370 } 1371 1372 // fold (add x, undef) -> undef 1373 if (N0.getOpcode() == ISD::UNDEF) 1374 return N0; 1375 if (N1.getOpcode() == ISD::UNDEF) 1376 return N1; 1377 // fold (add c1, c2) -> c1+c2 1378 if (N0C && N1C) 1379 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C); 1380 // canonicalize constant to RHS 1381 if (N0C && !N1C) 1382 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0); 1383 // fold (add x, 0) -> x 1384 if (N1C && N1C->isNullValue()) 1385 return N0; 1386 // fold (add Sym, c) -> Sym+c 1387 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1388 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C && 1389 GA->getOpcode() == ISD::GlobalAddress) 1390 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT, 1391 GA->getOffset() + 1392 (uint64_t)N1C->getSExtValue()); 1393 // fold ((c1-A)+c2) -> (c1+c2)-A 1394 if (N1C && N0.getOpcode() == ISD::SUB) 1395 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 1396 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1397 DAG.getConstant(N1C->getAPIntValue()+ 1398 N0C->getAPIntValue(), VT), 1399 N0.getOperand(1)); 1400 // reassociate add 1401 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1); 1402 if (RADD.getNode() != 0) 1403 return RADD; 1404 // fold ((0-A) + B) -> B-A 1405 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 1406 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 1407 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1)); 1408 // fold (A + (0-B)) -> A-B 1409 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1410 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 1411 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1)); 1412 // fold (A+(B-A)) -> B 1413 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 1414 return N1.getOperand(0); 1415 // fold ((B-A)+A) -> B 1416 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) 1417 return N0.getOperand(0); 1418 // fold (A+(B-(A+C))) to (B-C) 1419 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1420 N0 == N1.getOperand(1).getOperand(0)) 1421 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1422 N1.getOperand(1).getOperand(1)); 1423 // fold (A+(B-(C+A))) to (B-C) 1424 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1425 N0 == N1.getOperand(1).getOperand(1)) 1426 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1427 N1.getOperand(1).getOperand(0)); 1428 // fold (A+((B-A)+or-C)) to (B+or-C) 1429 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && 1430 N1.getOperand(0).getOpcode() == ISD::SUB && 1431 N0 == N1.getOperand(0).getOperand(1)) 1432 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT, 1433 N1.getOperand(0).getOperand(0), N1.getOperand(1)); 1434 1435 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant 1436 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) { 1437 SDValue N00 = N0.getOperand(0); 1438 SDValue N01 = N0.getOperand(1); 1439 SDValue N10 = N1.getOperand(0); 1440 SDValue N11 = N1.getOperand(1); 1441 1442 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10)) 1443 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1444 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10), 1445 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11)); 1446 } 1447 1448 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 1449 return SDValue(N, 0); 1450 1451 // fold (a+b) -> (a|b) iff a and b share no bits. 1452 if (VT.isInteger() && !VT.isVector()) { 1453 APInt LHSZero, LHSOne; 1454 APInt RHSZero, RHSOne; 1455 DAG.ComputeMaskedBits(N0, LHSZero, LHSOne); 1456 1457 if (LHSZero.getBoolValue()) { 1458 DAG.ComputeMaskedBits(N1, RHSZero, RHSOne); 1459 1460 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1461 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1462 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero) 1463 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1); 1464 } 1465 } 1466 1467 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1468 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1469 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG); 1470 if (Result.getNode()) return Result; 1471 } 1472 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1473 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG); 1474 if (Result.getNode()) return Result; 1475 } 1476 1477 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n)) 1478 if (N1.getOpcode() == ISD::SHL && 1479 N1.getOperand(0).getOpcode() == ISD::SUB) 1480 if (ConstantSDNode *C = 1481 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0))) 1482 if (C->getAPIntValue() == 0) 1483 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, 1484 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1485 N1.getOperand(0).getOperand(1), 1486 N1.getOperand(1))); 1487 if (N0.getOpcode() == ISD::SHL && 1488 N0.getOperand(0).getOpcode() == ISD::SUB) 1489 if (ConstantSDNode *C = 1490 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0))) 1491 if (C->getAPIntValue() == 0) 1492 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, 1493 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1494 N0.getOperand(0).getOperand(1), 1495 N0.getOperand(1))); 1496 1497 if (N1.getOpcode() == ISD::AND) { 1498 SDValue AndOp0 = N1.getOperand(0); 1499 ConstantSDNode *AndOp1 = dyn_cast<ConstantSDNode>(N1->getOperand(1)); 1500 unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0); 1501 unsigned DestBits = VT.getScalarType().getSizeInBits(); 1502 1503 // (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x)) 1504 // and similar xforms where the inner op is either ~0 or 0. 1505 if (NumSignBits == DestBits && AndOp1 && AndOp1->isOne()) { 1506 DebugLoc DL = N->getDebugLoc(); 1507 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0); 1508 } 1509 } 1510 1511 // add (sext i1), X -> sub X, (zext i1) 1512 if (N0.getOpcode() == ISD::SIGN_EXTEND && 1513 N0.getOperand(0).getValueType() == MVT::i1 && 1514 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) { 1515 DebugLoc DL = N->getDebugLoc(); 1516 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)); 1517 return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt); 1518 } 1519 1520 return SDValue(); 1521} 1522 1523SDValue DAGCombiner::visitADDC(SDNode *N) { 1524 SDValue N0 = N->getOperand(0); 1525 SDValue N1 = N->getOperand(1); 1526 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1527 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1528 EVT VT = N0.getValueType(); 1529 1530 // If the flag result is dead, turn this into an ADD. 1531 if (!N->hasAnyUseOfValue(1)) 1532 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N1), 1533 DAG.getNode(ISD::CARRY_FALSE, 1534 N->getDebugLoc(), MVT::Glue)); 1535 1536 // canonicalize constant to RHS. 1537 if (N0C && !N1C) 1538 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1539 1540 // fold (addc x, 0) -> x + no carry out 1541 if (N1C && N1C->isNullValue()) 1542 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, 1543 N->getDebugLoc(), MVT::Glue)); 1544 1545 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1546 APInt LHSZero, LHSOne; 1547 APInt RHSZero, RHSOne; 1548 DAG.ComputeMaskedBits(N0, LHSZero, LHSOne); 1549 1550 if (LHSZero.getBoolValue()) { 1551 DAG.ComputeMaskedBits(N1, RHSZero, RHSOne); 1552 1553 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1554 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1555 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero) 1556 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1), 1557 DAG.getNode(ISD::CARRY_FALSE, 1558 N->getDebugLoc(), MVT::Glue)); 1559 } 1560 1561 return SDValue(); 1562} 1563 1564SDValue DAGCombiner::visitADDE(SDNode *N) { 1565 SDValue N0 = N->getOperand(0); 1566 SDValue N1 = N->getOperand(1); 1567 SDValue CarryIn = N->getOperand(2); 1568 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1569 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1570 1571 // canonicalize constant to RHS 1572 if (N0C && !N1C) 1573 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), 1574 N1, N0, CarryIn); 1575 1576 // fold (adde x, y, false) -> (addc x, y) 1577 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1578 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N0, N1); 1579 1580 return SDValue(); 1581} 1582 1583// Since it may not be valid to emit a fold to zero for vector initializers 1584// check if we can before folding. 1585static SDValue tryFoldToZero(DebugLoc DL, const TargetLowering &TLI, EVT VT, 1586 SelectionDAG &DAG, bool LegalOperations) { 1587 if (!VT.isVector()) { 1588 return DAG.getConstant(0, VT); 1589 } 1590 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 1591 // Produce a vector of zeros. 1592 SDValue El = DAG.getConstant(0, VT.getVectorElementType()); 1593 std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 1594 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, 1595 &Ops[0], Ops.size()); 1596 } 1597 return SDValue(); 1598} 1599 1600SDValue DAGCombiner::visitSUB(SDNode *N) { 1601 SDValue N0 = N->getOperand(0); 1602 SDValue N1 = N->getOperand(1); 1603 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1604 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1605 ConstantSDNode *N1C1 = N1.getOpcode() != ISD::ADD ? 0 : 1606 dyn_cast<ConstantSDNode>(N1.getOperand(1).getNode()); 1607 EVT VT = N0.getValueType(); 1608 1609 // fold vector ops 1610 if (VT.isVector()) { 1611 SDValue FoldedVOp = SimplifyVBinOp(N); 1612 if (FoldedVOp.getNode()) return FoldedVOp; 1613 } 1614 1615 // fold (sub x, x) -> 0 1616 // FIXME: Refactor this and xor and other similar operations together. 1617 if (N0 == N1) 1618 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations); 1619 // fold (sub c1, c2) -> c1-c2 1620 if (N0C && N1C) 1621 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C); 1622 // fold (sub x, c) -> (add x, -c) 1623 if (N1C) 1624 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, 1625 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1626 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) 1627 if (N0C && N0C->isAllOnesValue()) 1628 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 1629 // fold A-(A-B) -> B 1630 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0)) 1631 return N1.getOperand(1); 1632 // fold (A+B)-A -> B 1633 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1634 return N0.getOperand(1); 1635 // fold (A+B)-B -> A 1636 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1637 return N0.getOperand(0); 1638 // fold C2-(A+C1) -> (C2-C1)-A 1639 if (N1.getOpcode() == ISD::ADD && N0C && N1C1) { 1640 SDValue NewC = DAG.getConstant((N0C->getAPIntValue() - N1C1->getAPIntValue()), VT); 1641 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, NewC, 1642 N1.getOperand(0)); 1643 } 1644 // fold ((A+(B+or-C))-B) -> A+or-C 1645 if (N0.getOpcode() == ISD::ADD && 1646 (N0.getOperand(1).getOpcode() == ISD::SUB || 1647 N0.getOperand(1).getOpcode() == ISD::ADD) && 1648 N0.getOperand(1).getOperand(0) == N1) 1649 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT, 1650 N0.getOperand(0), N0.getOperand(1).getOperand(1)); 1651 // fold ((A+(C+B))-B) -> A+C 1652 if (N0.getOpcode() == ISD::ADD && 1653 N0.getOperand(1).getOpcode() == ISD::ADD && 1654 N0.getOperand(1).getOperand(1) == N1) 1655 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1656 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1657 // fold ((A-(B-C))-C) -> A-B 1658 if (N0.getOpcode() == ISD::SUB && 1659 N0.getOperand(1).getOpcode() == ISD::SUB && 1660 N0.getOperand(1).getOperand(1) == N1) 1661 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1662 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1663 1664 // If either operand of a sub is undef, the result is undef 1665 if (N0.getOpcode() == ISD::UNDEF) 1666 return N0; 1667 if (N1.getOpcode() == ISD::UNDEF) 1668 return N1; 1669 1670 // If the relocation model supports it, consider symbol offsets. 1671 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1672 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) { 1673 // fold (sub Sym, c) -> Sym-c 1674 if (N1C && GA->getOpcode() == ISD::GlobalAddress) 1675 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT, 1676 GA->getOffset() - 1677 (uint64_t)N1C->getSExtValue()); 1678 // fold (sub Sym+c1, Sym+c2) -> c1-c2 1679 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1)) 1680 if (GA->getGlobal() == GB->getGlobal()) 1681 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(), 1682 VT); 1683 } 1684 1685 return SDValue(); 1686} 1687 1688SDValue DAGCombiner::visitSUBC(SDNode *N) { 1689 SDValue N0 = N->getOperand(0); 1690 SDValue N1 = N->getOperand(1); 1691 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1692 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1693 EVT VT = N0.getValueType(); 1694 1695 // If the flag result is dead, turn this into an SUB. 1696 if (!N->hasAnyUseOfValue(1)) 1697 return CombineTo(N, DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1), 1698 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1699 MVT::Glue)); 1700 1701 // fold (subc x, x) -> 0 + no borrow 1702 if (N0 == N1) 1703 return CombineTo(N, DAG.getConstant(0, VT), 1704 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1705 MVT::Glue)); 1706 1707 // fold (subc x, 0) -> x + no borrow 1708 if (N1C && N1C->isNullValue()) 1709 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1710 MVT::Glue)); 1711 1712 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) + no borrow 1713 if (N0C && N0C->isAllOnesValue()) 1714 return CombineTo(N, DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0), 1715 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1716 MVT::Glue)); 1717 1718 return SDValue(); 1719} 1720 1721SDValue DAGCombiner::visitSUBE(SDNode *N) { 1722 SDValue N0 = N->getOperand(0); 1723 SDValue N1 = N->getOperand(1); 1724 SDValue CarryIn = N->getOperand(2); 1725 1726 // fold (sube x, y, false) -> (subc x, y) 1727 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1728 return DAG.getNode(ISD::SUBC, N->getDebugLoc(), N->getVTList(), N0, N1); 1729 1730 return SDValue(); 1731} 1732 1733SDValue DAGCombiner::visitMUL(SDNode *N) { 1734 SDValue N0 = N->getOperand(0); 1735 SDValue N1 = N->getOperand(1); 1736 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1737 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1738 EVT VT = N0.getValueType(); 1739 1740 // fold vector ops 1741 if (VT.isVector()) { 1742 SDValue FoldedVOp = SimplifyVBinOp(N); 1743 if (FoldedVOp.getNode()) return FoldedVOp; 1744 } 1745 1746 // fold (mul x, undef) -> 0 1747 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1748 return DAG.getConstant(0, VT); 1749 // fold (mul c1, c2) -> c1*c2 1750 if (N0C && N1C) 1751 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C); 1752 // canonicalize constant to RHS 1753 if (N0C && !N1C) 1754 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0); 1755 // fold (mul x, 0) -> 0 1756 if (N1C && N1C->isNullValue()) 1757 return N1; 1758 // fold (mul x, -1) -> 0-x 1759 if (N1C && N1C->isAllOnesValue()) 1760 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1761 DAG.getConstant(0, VT), N0); 1762 // fold (mul x, (1 << c)) -> x << c 1763 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1764 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1765 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1766 getShiftAmountTy(N0.getValueType()))); 1767 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1768 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) { 1769 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2(); 1770 // FIXME: If the input is something that is easily negated (e.g. a 1771 // single-use add), we should put the negate there. 1772 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1773 DAG.getConstant(0, VT), 1774 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1775 DAG.getConstant(Log2Val, 1776 getShiftAmountTy(N0.getValueType())))); 1777 } 1778 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1779 if (N1C && N0.getOpcode() == ISD::SHL && 1780 isa<ConstantSDNode>(N0.getOperand(1))) { 1781 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1782 N1, N0.getOperand(1)); 1783 AddToWorkList(C3.getNode()); 1784 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1785 N0.getOperand(0), C3); 1786 } 1787 1788 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1789 // use. 1790 { 1791 SDValue Sh(0,0), Y(0,0); 1792 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1793 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1794 N0.getNode()->hasOneUse()) { 1795 Sh = N0; Y = N1; 1796 } else if (N1.getOpcode() == ISD::SHL && 1797 isa<ConstantSDNode>(N1.getOperand(1)) && 1798 N1.getNode()->hasOneUse()) { 1799 Sh = N1; Y = N0; 1800 } 1801 1802 if (Sh.getNode()) { 1803 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1804 Sh.getOperand(0), Y); 1805 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1806 Mul, Sh.getOperand(1)); 1807 } 1808 } 1809 1810 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1811 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 1812 isa<ConstantSDNode>(N0.getOperand(1))) 1813 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1814 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT, 1815 N0.getOperand(0), N1), 1816 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT, 1817 N0.getOperand(1), N1)); 1818 1819 // reassociate mul 1820 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1); 1821 if (RMUL.getNode() != 0) 1822 return RMUL; 1823 1824 return SDValue(); 1825} 1826 1827SDValue DAGCombiner::visitSDIV(SDNode *N) { 1828 SDValue N0 = N->getOperand(0); 1829 SDValue N1 = N->getOperand(1); 1830 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1831 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1832 EVT VT = N->getValueType(0); 1833 1834 // fold vector ops 1835 if (VT.isVector()) { 1836 SDValue FoldedVOp = SimplifyVBinOp(N); 1837 if (FoldedVOp.getNode()) return FoldedVOp; 1838 } 1839 1840 // fold (sdiv c1, c2) -> c1/c2 1841 if (N0C && N1C && !N1C->isNullValue()) 1842 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); 1843 // fold (sdiv X, 1) -> X 1844 if (N1C && N1C->getAPIntValue() == 1LL) 1845 return N0; 1846 // fold (sdiv X, -1) -> 0-X 1847 if (N1C && N1C->isAllOnesValue()) 1848 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1849 DAG.getConstant(0, VT), N0); 1850 // If we know the sign bits of both operands are zero, strength reduce to a 1851 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1852 if (!VT.isVector()) { 1853 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1854 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(), 1855 N0, N1); 1856 } 1857 // fold (sdiv X, pow2) -> simple ops after legalize 1858 if (N1C && !N1C->isNullValue() && 1859 (N1C->getAPIntValue().isPowerOf2() || 1860 (-N1C->getAPIntValue()).isPowerOf2())) { 1861 // If dividing by powers of two is cheap, then don't perform the following 1862 // fold. 1863 if (TLI.isPow2DivCheap()) 1864 return SDValue(); 1865 1866 unsigned lg2 = N1C->getAPIntValue().countTrailingZeros(); 1867 1868 // Splat the sign bit into the register 1869 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 1870 DAG.getConstant(VT.getSizeInBits()-1, 1871 getShiftAmountTy(N0.getValueType()))); 1872 AddToWorkList(SGN.getNode()); 1873 1874 // Add (N0 < 0) ? abs2 - 1 : 0; 1875 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN, 1876 DAG.getConstant(VT.getSizeInBits() - lg2, 1877 getShiftAmountTy(SGN.getValueType()))); 1878 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL); 1879 AddToWorkList(SRL.getNode()); 1880 AddToWorkList(ADD.getNode()); // Divide by pow2 1881 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD, 1882 DAG.getConstant(lg2, getShiftAmountTy(ADD.getValueType()))); 1883 1884 // If we're dividing by a positive value, we're done. Otherwise, we must 1885 // negate the result. 1886 if (N1C->getAPIntValue().isNonNegative()) 1887 return SRA; 1888 1889 AddToWorkList(SRA.getNode()); 1890 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1891 DAG.getConstant(0, VT), SRA); 1892 } 1893 1894 // if integer divide is expensive and we satisfy the requirements, emit an 1895 // alternate sequence. 1896 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1897 SDValue Op = BuildSDIV(N); 1898 if (Op.getNode()) return Op; 1899 } 1900 1901 // undef / X -> 0 1902 if (N0.getOpcode() == ISD::UNDEF) 1903 return DAG.getConstant(0, VT); 1904 // X / undef -> undef 1905 if (N1.getOpcode() == ISD::UNDEF) 1906 return N1; 1907 1908 return SDValue(); 1909} 1910 1911SDValue DAGCombiner::visitUDIV(SDNode *N) { 1912 SDValue N0 = N->getOperand(0); 1913 SDValue N1 = N->getOperand(1); 1914 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1915 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1916 EVT VT = N->getValueType(0); 1917 1918 // fold vector ops 1919 if (VT.isVector()) { 1920 SDValue FoldedVOp = SimplifyVBinOp(N); 1921 if (FoldedVOp.getNode()) return FoldedVOp; 1922 } 1923 1924 // fold (udiv c1, c2) -> c1/c2 1925 if (N0C && N1C && !N1C->isNullValue()) 1926 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); 1927 // fold (udiv x, (1 << c)) -> x >>u c 1928 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1929 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 1930 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1931 getShiftAmountTy(N0.getValueType()))); 1932 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1933 if (N1.getOpcode() == ISD::SHL) { 1934 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1935 if (SHC->getAPIntValue().isPowerOf2()) { 1936 EVT ADDVT = N1.getOperand(1).getValueType(); 1937 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT, 1938 N1.getOperand(1), 1939 DAG.getConstant(SHC->getAPIntValue() 1940 .logBase2(), 1941 ADDVT)); 1942 AddToWorkList(Add.getNode()); 1943 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add); 1944 } 1945 } 1946 } 1947 // fold (udiv x, c) -> alternate 1948 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1949 SDValue Op = BuildUDIV(N); 1950 if (Op.getNode()) return Op; 1951 } 1952 1953 // undef / X -> 0 1954 if (N0.getOpcode() == ISD::UNDEF) 1955 return DAG.getConstant(0, VT); 1956 // X / undef -> undef 1957 if (N1.getOpcode() == ISD::UNDEF) 1958 return N1; 1959 1960 return SDValue(); 1961} 1962 1963SDValue DAGCombiner::visitSREM(SDNode *N) { 1964 SDValue N0 = N->getOperand(0); 1965 SDValue N1 = N->getOperand(1); 1966 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1967 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1968 EVT VT = N->getValueType(0); 1969 1970 // fold (srem c1, c2) -> c1%c2 1971 if (N0C && N1C && !N1C->isNullValue()) 1972 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); 1973 // If we know the sign bits of both operands are zero, strength reduce to a 1974 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1975 if (!VT.isVector()) { 1976 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1977 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1); 1978 } 1979 1980 // If X/C can be simplified by the division-by-constant logic, lower 1981 // X%C to the equivalent of X-X/C*C. 1982 if (N1C && !N1C->isNullValue()) { 1983 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1); 1984 AddToWorkList(Div.getNode()); 1985 SDValue OptimizedDiv = combine(Div.getNode()); 1986 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1987 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1988 OptimizedDiv, N1); 1989 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1990 AddToWorkList(Mul.getNode()); 1991 return Sub; 1992 } 1993 } 1994 1995 // undef % X -> 0 1996 if (N0.getOpcode() == ISD::UNDEF) 1997 return DAG.getConstant(0, VT); 1998 // X % undef -> undef 1999 if (N1.getOpcode() == ISD::UNDEF) 2000 return N1; 2001 2002 return SDValue(); 2003} 2004 2005SDValue DAGCombiner::visitUREM(SDNode *N) { 2006 SDValue N0 = N->getOperand(0); 2007 SDValue N1 = N->getOperand(1); 2008 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2009 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2010 EVT VT = N->getValueType(0); 2011 2012 // fold (urem c1, c2) -> c1%c2 2013 if (N0C && N1C && !N1C->isNullValue()) 2014 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C); 2015 // fold (urem x, pow2) -> (and x, pow2-1) 2016 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 2017 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, 2018 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 2019 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 2020 if (N1.getOpcode() == ISD::SHL) { 2021 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 2022 if (SHC->getAPIntValue().isPowerOf2()) { 2023 SDValue Add = 2024 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, 2025 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 2026 VT)); 2027 AddToWorkList(Add.getNode()); 2028 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add); 2029 } 2030 } 2031 } 2032 2033 // If X/C can be simplified by the division-by-constant logic, lower 2034 // X%C to the equivalent of X-X/C*C. 2035 if (N1C && !N1C->isNullValue()) { 2036 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1); 2037 AddToWorkList(Div.getNode()); 2038 SDValue OptimizedDiv = combine(Div.getNode()); 2039 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 2040 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 2041 OptimizedDiv, N1); 2042 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 2043 AddToWorkList(Mul.getNode()); 2044 return Sub; 2045 } 2046 } 2047 2048 // undef % X -> 0 2049 if (N0.getOpcode() == ISD::UNDEF) 2050 return DAG.getConstant(0, VT); 2051 // X % undef -> undef 2052 if (N1.getOpcode() == ISD::UNDEF) 2053 return N1; 2054 2055 return SDValue(); 2056} 2057 2058SDValue DAGCombiner::visitMULHS(SDNode *N) { 2059 SDValue N0 = N->getOperand(0); 2060 SDValue N1 = N->getOperand(1); 2061 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2062 EVT VT = N->getValueType(0); 2063 DebugLoc DL = N->getDebugLoc(); 2064 2065 // fold (mulhs x, 0) -> 0 2066 if (N1C && N1C->isNullValue()) 2067 return N1; 2068 // fold (mulhs x, 1) -> (sra x, size(x)-1) 2069 if (N1C && N1C->getAPIntValue() == 1) 2070 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0, 2071 DAG.getConstant(N0.getValueType().getSizeInBits() - 1, 2072 getShiftAmountTy(N0.getValueType()))); 2073 // fold (mulhs x, undef) -> 0 2074 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2075 return DAG.getConstant(0, VT); 2076 2077 // If the type twice as wide is legal, transform the mulhs to a wider multiply 2078 // plus a shift. 2079 if (VT.isSimple() && !VT.isVector()) { 2080 MVT Simple = VT.getSimpleVT(); 2081 unsigned SimpleSize = Simple.getSizeInBits(); 2082 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2083 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2084 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0); 2085 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1); 2086 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); 2087 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, 2088 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType()))); 2089 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); 2090 } 2091 } 2092 2093 return SDValue(); 2094} 2095 2096SDValue DAGCombiner::visitMULHU(SDNode *N) { 2097 SDValue N0 = N->getOperand(0); 2098 SDValue N1 = N->getOperand(1); 2099 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2100 EVT VT = N->getValueType(0); 2101 DebugLoc DL = N->getDebugLoc(); 2102 2103 // fold (mulhu x, 0) -> 0 2104 if (N1C && N1C->isNullValue()) 2105 return N1; 2106 // fold (mulhu x, 1) -> 0 2107 if (N1C && N1C->getAPIntValue() == 1) 2108 return DAG.getConstant(0, N0.getValueType()); 2109 // fold (mulhu x, undef) -> 0 2110 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2111 return DAG.getConstant(0, VT); 2112 2113 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2114 // plus a shift. 2115 if (VT.isSimple() && !VT.isVector()) { 2116 MVT Simple = VT.getSimpleVT(); 2117 unsigned SimpleSize = Simple.getSizeInBits(); 2118 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2119 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2120 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0); 2121 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1); 2122 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); 2123 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, 2124 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType()))); 2125 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); 2126 } 2127 } 2128 2129 return SDValue(); 2130} 2131 2132/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 2133/// compute two values. LoOp and HiOp give the opcodes for the two computations 2134/// that are being performed. Return true if a simplification was made. 2135/// 2136SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 2137 unsigned HiOp) { 2138 // If the high half is not needed, just compute the low half. 2139 bool HiExists = N->hasAnyUseOfValue(1); 2140 if (!HiExists && 2141 (!LegalOperations || 2142 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 2143 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 2144 N->op_begin(), N->getNumOperands()); 2145 return CombineTo(N, Res, Res); 2146 } 2147 2148 // If the low half is not needed, just compute the high half. 2149 bool LoExists = N->hasAnyUseOfValue(0); 2150 if (!LoExists && 2151 (!LegalOperations || 2152 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 2153 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 2154 N->op_begin(), N->getNumOperands()); 2155 return CombineTo(N, Res, Res); 2156 } 2157 2158 // If both halves are used, return as it is. 2159 if (LoExists && HiExists) 2160 return SDValue(); 2161 2162 // If the two computed results can be simplified separately, separate them. 2163 if (LoExists) { 2164 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 2165 N->op_begin(), N->getNumOperands()); 2166 AddToWorkList(Lo.getNode()); 2167 SDValue LoOpt = combine(Lo.getNode()); 2168 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && 2169 (!LegalOperations || 2170 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 2171 return CombineTo(N, LoOpt, LoOpt); 2172 } 2173 2174 if (HiExists) { 2175 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 2176 N->op_begin(), N->getNumOperands()); 2177 AddToWorkList(Hi.getNode()); 2178 SDValue HiOpt = combine(Hi.getNode()); 2179 if (HiOpt.getNode() && HiOpt != Hi && 2180 (!LegalOperations || 2181 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 2182 return CombineTo(N, HiOpt, HiOpt); 2183 } 2184 2185 return SDValue(); 2186} 2187 2188SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 2189 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 2190 if (Res.getNode()) return Res; 2191 2192 EVT VT = N->getValueType(0); 2193 DebugLoc DL = N->getDebugLoc(); 2194 2195 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2196 // plus a shift. 2197 if (VT.isSimple() && !VT.isVector()) { 2198 MVT Simple = VT.getSimpleVT(); 2199 unsigned SimpleSize = Simple.getSizeInBits(); 2200 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2201 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2202 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0)); 2203 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1)); 2204 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi); 2205 // Compute the high part as N1. 2206 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, 2207 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType()))); 2208 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); 2209 // Compute the low part as N0. 2210 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo); 2211 return CombineTo(N, Lo, Hi); 2212 } 2213 } 2214 2215 return SDValue(); 2216} 2217 2218SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 2219 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 2220 if (Res.getNode()) return Res; 2221 2222 EVT VT = N->getValueType(0); 2223 DebugLoc DL = N->getDebugLoc(); 2224 2225 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2226 // plus a shift. 2227 if (VT.isSimple() && !VT.isVector()) { 2228 MVT Simple = VT.getSimpleVT(); 2229 unsigned SimpleSize = Simple.getSizeInBits(); 2230 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2231 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2232 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0)); 2233 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1)); 2234 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi); 2235 // Compute the high part as N1. 2236 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, 2237 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType()))); 2238 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); 2239 // Compute the low part as N0. 2240 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo); 2241 return CombineTo(N, Lo, Hi); 2242 } 2243 } 2244 2245 return SDValue(); 2246} 2247 2248SDValue DAGCombiner::visitSMULO(SDNode *N) { 2249 // (smulo x, 2) -> (saddo x, x) 2250 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1))) 2251 if (C2->getAPIntValue() == 2) 2252 return DAG.getNode(ISD::SADDO, N->getDebugLoc(), N->getVTList(), 2253 N->getOperand(0), N->getOperand(0)); 2254 2255 return SDValue(); 2256} 2257 2258SDValue DAGCombiner::visitUMULO(SDNode *N) { 2259 // (umulo x, 2) -> (uaddo x, x) 2260 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1))) 2261 if (C2->getAPIntValue() == 2) 2262 return DAG.getNode(ISD::UADDO, N->getDebugLoc(), N->getVTList(), 2263 N->getOperand(0), N->getOperand(0)); 2264 2265 return SDValue(); 2266} 2267 2268SDValue DAGCombiner::visitSDIVREM(SDNode *N) { 2269 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 2270 if (Res.getNode()) return Res; 2271 2272 return SDValue(); 2273} 2274 2275SDValue DAGCombiner::visitUDIVREM(SDNode *N) { 2276 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 2277 if (Res.getNode()) return Res; 2278 2279 return SDValue(); 2280} 2281 2282/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 2283/// two operands of the same opcode, try to simplify it. 2284SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 2285 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 2286 EVT VT = N0.getValueType(); 2287 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 2288 2289 // Bail early if none of these transforms apply. 2290 if (N0.getNode()->getNumOperands() == 0) return SDValue(); 2291 2292 // For each of OP in AND/OR/XOR: 2293 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 2294 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 2295 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 2296 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free) 2297 // 2298 // do not sink logical op inside of a vector extend, since it may combine 2299 // into a vsetcc. 2300 EVT Op0VT = N0.getOperand(0).getValueType(); 2301 if ((N0.getOpcode() == ISD::ZERO_EXTEND || 2302 N0.getOpcode() == ISD::SIGN_EXTEND || 2303 // Avoid infinite looping with PromoteIntBinOp. 2304 (N0.getOpcode() == ISD::ANY_EXTEND && 2305 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) || 2306 (N0.getOpcode() == ISD::TRUNCATE && 2307 (!TLI.isZExtFree(VT, Op0VT) || 2308 !TLI.isTruncateFree(Op0VT, VT)) && 2309 TLI.isTypeLegal(Op0VT))) && 2310 !VT.isVector() && 2311 Op0VT == N1.getOperand(0).getValueType() && 2312 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) { 2313 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 2314 N0.getOperand(0).getValueType(), 2315 N0.getOperand(0), N1.getOperand(0)); 2316 AddToWorkList(ORNode.getNode()); 2317 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode); 2318 } 2319 2320 // For each of OP in SHL/SRL/SRA/AND... 2321 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 2322 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 2323 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 2324 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 2325 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 2326 N0.getOperand(1) == N1.getOperand(1)) { 2327 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 2328 N0.getOperand(0).getValueType(), 2329 N0.getOperand(0), N1.getOperand(0)); 2330 AddToWorkList(ORNode.getNode()); 2331 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 2332 ORNode, N0.getOperand(1)); 2333 } 2334 2335 // Simplify xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B)) 2336 // Only perform this optimization after type legalization and before 2337 // LegalizeVectorOprs. LegalizeVectorOprs promotes vector operations by 2338 // adding bitcasts. For example (xor v4i32) is promoted to (v2i64), and 2339 // we don't want to undo this promotion. 2340 // We also handle SCALAR_TO_VECTOR because xor/or/and operations are cheaper 2341 // on scalars. 2342 if ((N0.getOpcode() == ISD::BITCAST || N0.getOpcode() == ISD::SCALAR_TO_VECTOR) 2343 && Level == AfterLegalizeVectorOps) { 2344 SDValue In0 = N0.getOperand(0); 2345 SDValue In1 = N1.getOperand(0); 2346 EVT In0Ty = In0.getValueType(); 2347 EVT In1Ty = In1.getValueType(); 2348 // If both incoming values are integers, and the original types are the same. 2349 if (In0Ty.isInteger() && In1Ty.isInteger() && In0Ty == In1Ty) { 2350 SDValue Op = DAG.getNode(N->getOpcode(), N->getDebugLoc(), In0Ty, In0, In1); 2351 SDValue BC = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, Op); 2352 AddToWorkList(Op.getNode()); 2353 return BC; 2354 } 2355 } 2356 2357 // Xor/and/or are indifferent to the swizzle operation (shuffle of one value). 2358 // Simplify xor/and/or (shuff(A), shuff(B)) -> shuff(op (A,B)) 2359 // If both shuffles use the same mask, and both shuffle within a single 2360 // vector, then it is worthwhile to move the swizzle after the operation. 2361 // The type-legalizer generates this pattern when loading illegal 2362 // vector types from memory. In many cases this allows additional shuffle 2363 // optimizations. 2364 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG && 2365 N0.getOperand(1).getOpcode() == ISD::UNDEF && 2366 N1.getOperand(1).getOpcode() == ISD::UNDEF) { 2367 ShuffleVectorSDNode *SVN0 = cast<ShuffleVectorSDNode>(N0); 2368 ShuffleVectorSDNode *SVN1 = cast<ShuffleVectorSDNode>(N1); 2369 2370 assert(N0.getOperand(0).getValueType() == N1.getOperand(1).getValueType() && 2371 "Inputs to shuffles are not the same type"); 2372 2373 unsigned NumElts = VT.getVectorNumElements(); 2374 2375 // Check that both shuffles use the same mask. The masks are known to be of 2376 // the same length because the result vector type is the same. 2377 bool SameMask = true; 2378 for (unsigned i = 0; i != NumElts; ++i) { 2379 int Idx0 = SVN0->getMaskElt(i); 2380 int Idx1 = SVN1->getMaskElt(i); 2381 if (Idx0 != Idx1) { 2382 SameMask = false; 2383 break; 2384 } 2385 } 2386 2387 if (SameMask) { 2388 SDValue Op = DAG.getNode(N->getOpcode(), N->getDebugLoc(), VT, 2389 N0.getOperand(0), N1.getOperand(0)); 2390 AddToWorkList(Op.getNode()); 2391 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Op, 2392 DAG.getUNDEF(VT), &SVN0->getMask()[0]); 2393 } 2394 } 2395 2396 return SDValue(); 2397} 2398 2399SDValue DAGCombiner::visitAND(SDNode *N) { 2400 SDValue N0 = N->getOperand(0); 2401 SDValue N1 = N->getOperand(1); 2402 SDValue LL, LR, RL, RR, CC0, CC1; 2403 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2404 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2405 EVT VT = N1.getValueType(); 2406 unsigned BitWidth = VT.getScalarType().getSizeInBits(); 2407 2408 // fold vector ops 2409 if (VT.isVector()) { 2410 SDValue FoldedVOp = SimplifyVBinOp(N); 2411 if (FoldedVOp.getNode()) return FoldedVOp; 2412 } 2413 2414 // fold (and x, undef) -> 0 2415 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2416 return DAG.getConstant(0, VT); 2417 // fold (and c1, c2) -> c1&c2 2418 if (N0C && N1C) 2419 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C); 2420 // canonicalize constant to RHS 2421 if (N0C && !N1C) 2422 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0); 2423 // fold (and x, -1) -> x 2424 if (N1C && N1C->isAllOnesValue()) 2425 return N0; 2426 // if (and x, c) is known to be zero, return 0 2427 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2428 APInt::getAllOnesValue(BitWidth))) 2429 return DAG.getConstant(0, VT); 2430 // reassociate and 2431 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1); 2432 if (RAND.getNode() != 0) 2433 return RAND; 2434 // fold (and (or x, C), D) -> D if (C & D) == D 2435 if (N1C && N0.getOpcode() == ISD::OR) 2436 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 2437 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 2438 return N1; 2439 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 2440 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2441 SDValue N0Op0 = N0.getOperand(0); 2442 APInt Mask = ~N1C->getAPIntValue(); 2443 Mask = Mask.trunc(N0Op0.getValueSizeInBits()); 2444 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 2445 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), 2446 N0.getValueType(), N0Op0); 2447 2448 // Replace uses of the AND with uses of the Zero extend node. 2449 CombineTo(N, Zext); 2450 2451 // We actually want to replace all uses of the any_extend with the 2452 // zero_extend, to avoid duplicating things. This will later cause this 2453 // AND to be folded. 2454 CombineTo(N0.getNode(), Zext); 2455 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2456 } 2457 } 2458 // similarly fold (and (X (load ([non_ext|any_ext|zero_ext] V))), c) -> 2459 // (X (load ([non_ext|zero_ext] V))) if 'and' only clears top bits which must 2460 // already be zero by virtue of the width of the base type of the load. 2461 // 2462 // the 'X' node here can either be nothing or an extract_vector_elt to catch 2463 // more cases. 2464 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && 2465 N0.getOperand(0).getOpcode() == ISD::LOAD) || 2466 N0.getOpcode() == ISD::LOAD) { 2467 LoadSDNode *Load = cast<LoadSDNode>( (N0.getOpcode() == ISD::LOAD) ? 2468 N0 : N0.getOperand(0) ); 2469 2470 // Get the constant (if applicable) the zero'th operand is being ANDed with. 2471 // This can be a pure constant or a vector splat, in which case we treat the 2472 // vector as a scalar and use the splat value. 2473 APInt Constant = APInt::getNullValue(1); 2474 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) { 2475 Constant = C->getAPIntValue(); 2476 } else if (BuildVectorSDNode *Vector = dyn_cast<BuildVectorSDNode>(N1)) { 2477 APInt SplatValue, SplatUndef; 2478 unsigned SplatBitSize; 2479 bool HasAnyUndefs; 2480 bool IsSplat = Vector->isConstantSplat(SplatValue, SplatUndef, 2481 SplatBitSize, HasAnyUndefs); 2482 if (IsSplat) { 2483 // Undef bits can contribute to a possible optimisation if set, so 2484 // set them. 2485 SplatValue |= SplatUndef; 2486 2487 // The splat value may be something like "0x00FFFFFF", which means 0 for 2488 // the first vector value and FF for the rest, repeating. We need a mask 2489 // that will apply equally to all members of the vector, so AND all the 2490 // lanes of the constant together. 2491 EVT VT = Vector->getValueType(0); 2492 unsigned BitWidth = VT.getVectorElementType().getSizeInBits(); 2493 Constant = APInt::getAllOnesValue(BitWidth); 2494 for (unsigned i = 0, n = VT.getVectorNumElements(); i < n; ++i) 2495 Constant &= SplatValue.lshr(i*BitWidth).zextOrTrunc(BitWidth); 2496 } 2497 } 2498 2499 // If we want to change an EXTLOAD to a ZEXTLOAD, ensure a ZEXTLOAD is 2500 // actually legal and isn't going to get expanded, else this is a false 2501 // optimisation. 2502 bool CanZextLoadProfitably = TLI.isLoadExtLegal(ISD::ZEXTLOAD, 2503 Load->getMemoryVT()); 2504 2505 // Resize the constant to the same size as the original memory access before 2506 // extension. If it is still the AllOnesValue then this AND is completely 2507 // unneeded. 2508 Constant = 2509 Constant.zextOrTrunc(Load->getMemoryVT().getScalarType().getSizeInBits()); 2510 2511 bool B; 2512 switch (Load->getExtensionType()) { 2513 default: B = false; break; 2514 case ISD::EXTLOAD: B = CanZextLoadProfitably; break; 2515 case ISD::ZEXTLOAD: 2516 case ISD::NON_EXTLOAD: B = true; break; 2517 } 2518 2519 if (B && Constant.isAllOnesValue()) { 2520 // If the load type was an EXTLOAD, convert to ZEXTLOAD in order to 2521 // preserve semantics once we get rid of the AND. 2522 SDValue NewLoad(Load, 0); 2523 if (Load->getExtensionType() == ISD::EXTLOAD) { 2524 NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD, 2525 Load->getValueType(0), Load->getDebugLoc(), 2526 Load->getChain(), Load->getBasePtr(), 2527 Load->getOffset(), Load->getMemoryVT(), 2528 Load->getMemOperand()); 2529 // Replace uses of the EXTLOAD with the new ZEXTLOAD. 2530 CombineTo(Load, NewLoad.getValue(0), NewLoad.getValue(1)); 2531 } 2532 2533 // Fold the AND away, taking care not to fold to the old load node if we 2534 // replaced it. 2535 CombineTo(N, (N0.getNode() == Load) ? NewLoad : N0); 2536 2537 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2538 } 2539 } 2540 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 2541 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 2542 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 2543 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 2544 2545 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 2546 LL.getValueType().isInteger()) { 2547 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0) 2548 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 2549 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 2550 LR.getValueType(), LL, RL); 2551 AddToWorkList(ORNode.getNode()); 2552 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2553 } 2554 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1) 2555 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 2556 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(), 2557 LR.getValueType(), LL, RL); 2558 AddToWorkList(ANDNode.getNode()); 2559 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 2560 } 2561 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1) 2562 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 2563 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 2564 LR.getValueType(), LL, RL); 2565 AddToWorkList(ORNode.getNode()); 2566 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2567 } 2568 } 2569 // canonicalize equivalent to ll == rl 2570 if (LL == RR && LR == RL) { 2571 Op1 = ISD::getSetCCSwappedOperands(Op1); 2572 std::swap(RL, RR); 2573 } 2574 if (LL == RL && LR == RR) { 2575 bool isInteger = LL.getValueType().isInteger(); 2576 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 2577 if (Result != ISD::SETCC_INVALID && 2578 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 2579 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 2580 LL, LR, Result); 2581 } 2582 } 2583 2584 // Simplify: (and (op x...), (op y...)) -> (op (and x, y)) 2585 if (N0.getOpcode() == N1.getOpcode()) { 2586 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2587 if (Tmp.getNode()) return Tmp; 2588 } 2589 2590 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 2591 // fold (and (sra)) -> (and (srl)) when possible. 2592 if (!VT.isVector() && 2593 SimplifyDemandedBits(SDValue(N, 0))) 2594 return SDValue(N, 0); 2595 2596 // fold (zext_inreg (extload x)) -> (zextload x) 2597 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { 2598 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2599 EVT MemVT = LN0->getMemoryVT(); 2600 // If we zero all the possible extended bits, then we can turn this into 2601 // a zextload if we are running before legalize or the operation is legal. 2602 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2603 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2604 BitWidth - MemVT.getScalarType().getSizeInBits())) && 2605 ((!LegalOperations && !LN0->isVolatile()) || 2606 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2607 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 2608 LN0->getChain(), LN0->getBasePtr(), 2609 LN0->getPointerInfo(), MemVT, 2610 LN0->isVolatile(), LN0->isNonTemporal(), 2611 LN0->getAlignment()); 2612 AddToWorkList(N); 2613 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2614 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2615 } 2616 } 2617 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 2618 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 2619 N0.hasOneUse()) { 2620 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2621 EVT MemVT = LN0->getMemoryVT(); 2622 // If we zero all the possible extended bits, then we can turn this into 2623 // a zextload if we are running before legalize or the operation is legal. 2624 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2625 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2626 BitWidth - MemVT.getScalarType().getSizeInBits())) && 2627 ((!LegalOperations && !LN0->isVolatile()) || 2628 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2629 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 2630 LN0->getChain(), 2631 LN0->getBasePtr(), LN0->getPointerInfo(), 2632 MemVT, 2633 LN0->isVolatile(), LN0->isNonTemporal(), 2634 LN0->getAlignment()); 2635 AddToWorkList(N); 2636 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2637 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2638 } 2639 } 2640 2641 // fold (and (load x), 255) -> (zextload x, i8) 2642 // fold (and (extload x, i16), 255) -> (zextload x, i8) 2643 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8) 2644 if (N1C && (N0.getOpcode() == ISD::LOAD || 2645 (N0.getOpcode() == ISD::ANY_EXTEND && 2646 N0.getOperand(0).getOpcode() == ISD::LOAD))) { 2647 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND; 2648 LoadSDNode *LN0 = HasAnyExt 2649 ? cast<LoadSDNode>(N0.getOperand(0)) 2650 : cast<LoadSDNode>(N0); 2651 if (LN0->getExtensionType() != ISD::SEXTLOAD && 2652 LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) { 2653 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 2654 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){ 2655 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits); 2656 EVT LoadedVT = LN0->getMemoryVT(); 2657 2658 if (ExtVT == LoadedVT && 2659 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2660 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2661 2662 SDValue NewLoad = 2663 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 2664 LN0->getChain(), LN0->getBasePtr(), 2665 LN0->getPointerInfo(), 2666 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 2667 LN0->getAlignment()); 2668 AddToWorkList(N); 2669 CombineTo(LN0, NewLoad, NewLoad.getValue(1)); 2670 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2671 } 2672 2673 // Do not change the width of a volatile load. 2674 // Do not generate loads of non-round integer types since these can 2675 // be expensive (and would be wrong if the type is not byte sized). 2676 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() && 2677 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2678 EVT PtrType = LN0->getOperand(1).getValueType(); 2679 2680 unsigned Alignment = LN0->getAlignment(); 2681 SDValue NewPtr = LN0->getBasePtr(); 2682 2683 // For big endian targets, we need to add an offset to the pointer 2684 // to load the correct bytes. For little endian systems, we merely 2685 // need to read fewer bytes from the same pointer. 2686 if (TLI.isBigEndian()) { 2687 unsigned LVTStoreBytes = LoadedVT.getStoreSize(); 2688 unsigned EVTStoreBytes = ExtVT.getStoreSize(); 2689 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 2690 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType, 2691 NewPtr, DAG.getConstant(PtrOff, PtrType)); 2692 Alignment = MinAlign(Alignment, PtrOff); 2693 } 2694 2695 AddToWorkList(NewPtr.getNode()); 2696 2697 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2698 SDValue Load = 2699 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 2700 LN0->getChain(), NewPtr, 2701 LN0->getPointerInfo(), 2702 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 2703 Alignment); 2704 AddToWorkList(N); 2705 CombineTo(LN0, Load, Load.getValue(1)); 2706 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2707 } 2708 } 2709 } 2710 } 2711 2712 return SDValue(); 2713} 2714 2715/// MatchBSwapHWord - Match (a >> 8) | (a << 8) as (bswap a) >> 16 2716/// 2717SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1, 2718 bool DemandHighBits) { 2719 if (!LegalOperations) 2720 return SDValue(); 2721 2722 EVT VT = N->getValueType(0); 2723 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16) 2724 return SDValue(); 2725 if (!TLI.isOperationLegal(ISD::BSWAP, VT)) 2726 return SDValue(); 2727 2728 // Recognize (and (shl a, 8), 0xff), (and (srl a, 8), 0xff00) 2729 bool LookPassAnd0 = false; 2730 bool LookPassAnd1 = false; 2731 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL) 2732 std::swap(N0, N1); 2733 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL) 2734 std::swap(N0, N1); 2735 if (N0.getOpcode() == ISD::AND) { 2736 if (!N0.getNode()->hasOneUse()) 2737 return SDValue(); 2738 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2739 if (!N01C || N01C->getZExtValue() != 0xFF00) 2740 return SDValue(); 2741 N0 = N0.getOperand(0); 2742 LookPassAnd0 = true; 2743 } 2744 2745 if (N1.getOpcode() == ISD::AND) { 2746 if (!N1.getNode()->hasOneUse()) 2747 return SDValue(); 2748 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1)); 2749 if (!N11C || N11C->getZExtValue() != 0xFF) 2750 return SDValue(); 2751 N1 = N1.getOperand(0); 2752 LookPassAnd1 = true; 2753 } 2754 2755 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 2756 std::swap(N0, N1); 2757 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) 2758 return SDValue(); 2759 if (!N0.getNode()->hasOneUse() || 2760 !N1.getNode()->hasOneUse()) 2761 return SDValue(); 2762 2763 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2764 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1)); 2765 if (!N01C || !N11C) 2766 return SDValue(); 2767 if (N01C->getZExtValue() != 8 || N11C->getZExtValue() != 8) 2768 return SDValue(); 2769 2770 // Look for (shl (and a, 0xff), 8), (srl (and a, 0xff00), 8) 2771 SDValue N00 = N0->getOperand(0); 2772 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) { 2773 if (!N00.getNode()->hasOneUse()) 2774 return SDValue(); 2775 ConstantSDNode *N001C = dyn_cast<ConstantSDNode>(N00.getOperand(1)); 2776 if (!N001C || N001C->getZExtValue() != 0xFF) 2777 return SDValue(); 2778 N00 = N00.getOperand(0); 2779 LookPassAnd0 = true; 2780 } 2781 2782 SDValue N10 = N1->getOperand(0); 2783 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) { 2784 if (!N10.getNode()->hasOneUse()) 2785 return SDValue(); 2786 ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N10.getOperand(1)); 2787 if (!N101C || N101C->getZExtValue() != 0xFF00) 2788 return SDValue(); 2789 N10 = N10.getOperand(0); 2790 LookPassAnd1 = true; 2791 } 2792 2793 if (N00 != N10) 2794 return SDValue(); 2795 2796 // Make sure everything beyond the low halfword is zero since the SRL 16 2797 // will clear the top bits. 2798 unsigned OpSizeInBits = VT.getSizeInBits(); 2799 if (DemandHighBits && OpSizeInBits > 16 && 2800 (!LookPassAnd0 || !LookPassAnd1) && 2801 !DAG.MaskedValueIsZero(N10, APInt::getHighBitsSet(OpSizeInBits, 16))) 2802 return SDValue(); 2803 2804 SDValue Res = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT, N00); 2805 if (OpSizeInBits > 16) 2806 Res = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Res, 2807 DAG.getConstant(OpSizeInBits-16, getShiftAmountTy(VT))); 2808 return Res; 2809} 2810 2811/// isBSwapHWordElement - Return true if the specified node is an element 2812/// that makes up a 32-bit packed halfword byteswap. i.e. 2813/// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8) 2814static bool isBSwapHWordElement(SDValue N, SmallVector<SDNode*,4> &Parts) { 2815 if (!N.getNode()->hasOneUse()) 2816 return false; 2817 2818 unsigned Opc = N.getOpcode(); 2819 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL) 2820 return false; 2821 2822 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N.getOperand(1)); 2823 if (!N1C) 2824 return false; 2825 2826 unsigned Num; 2827 switch (N1C->getZExtValue()) { 2828 default: 2829 return false; 2830 case 0xFF: Num = 0; break; 2831 case 0xFF00: Num = 1; break; 2832 case 0xFF0000: Num = 2; break; 2833 case 0xFF000000: Num = 3; break; 2834 } 2835 2836 // Look for (x & 0xff) << 8 as well as ((x << 8) & 0xff00). 2837 SDValue N0 = N.getOperand(0); 2838 if (Opc == ISD::AND) { 2839 if (Num == 0 || Num == 2) { 2840 // (x >> 8) & 0xff 2841 // (x >> 8) & 0xff0000 2842 if (N0.getOpcode() != ISD::SRL) 2843 return false; 2844 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2845 if (!C || C->getZExtValue() != 8) 2846 return false; 2847 } else { 2848 // (x << 8) & 0xff00 2849 // (x << 8) & 0xff000000 2850 if (N0.getOpcode() != ISD::SHL) 2851 return false; 2852 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2853 if (!C || C->getZExtValue() != 8) 2854 return false; 2855 } 2856 } else if (Opc == ISD::SHL) { 2857 // (x & 0xff) << 8 2858 // (x & 0xff0000) << 8 2859 if (Num != 0 && Num != 2) 2860 return false; 2861 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1)); 2862 if (!C || C->getZExtValue() != 8) 2863 return false; 2864 } else { // Opc == ISD::SRL 2865 // (x & 0xff00) >> 8 2866 // (x & 0xff000000) >> 8 2867 if (Num != 1 && Num != 3) 2868 return false; 2869 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1)); 2870 if (!C || C->getZExtValue() != 8) 2871 return false; 2872 } 2873 2874 if (Parts[Num]) 2875 return false; 2876 2877 Parts[Num] = N0.getOperand(0).getNode(); 2878 return true; 2879} 2880 2881/// MatchBSwapHWord - Match a 32-bit packed halfword bswap. That is 2882/// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8) 2883/// => (rotl (bswap x), 16) 2884SDValue DAGCombiner::MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) { 2885 if (!LegalOperations) 2886 return SDValue(); 2887 2888 EVT VT = N->getValueType(0); 2889 if (VT != MVT::i32) 2890 return SDValue(); 2891 if (!TLI.isOperationLegal(ISD::BSWAP, VT)) 2892 return SDValue(); 2893 2894 SmallVector<SDNode*,4> Parts(4, (SDNode*)0); 2895 // Look for either 2896 // (or (or (and), (and)), (or (and), (and))) 2897 // (or (or (or (and), (and)), (and)), (and)) 2898 if (N0.getOpcode() != ISD::OR) 2899 return SDValue(); 2900 SDValue N00 = N0.getOperand(0); 2901 SDValue N01 = N0.getOperand(1); 2902 2903 if (N1.getOpcode() == ISD::OR) { 2904 // (or (or (and), (and)), (or (and), (and))) 2905 SDValue N000 = N00.getOperand(0); 2906 if (!isBSwapHWordElement(N000, Parts)) 2907 return SDValue(); 2908 2909 SDValue N001 = N00.getOperand(1); 2910 if (!isBSwapHWordElement(N001, Parts)) 2911 return SDValue(); 2912 SDValue N010 = N01.getOperand(0); 2913 if (!isBSwapHWordElement(N010, Parts)) 2914 return SDValue(); 2915 SDValue N011 = N01.getOperand(1); 2916 if (!isBSwapHWordElement(N011, Parts)) 2917 return SDValue(); 2918 } else { 2919 // (or (or (or (and), (and)), (and)), (and)) 2920 if (!isBSwapHWordElement(N1, Parts)) 2921 return SDValue(); 2922 if (!isBSwapHWordElement(N01, Parts)) 2923 return SDValue(); 2924 if (N00.getOpcode() != ISD::OR) 2925 return SDValue(); 2926 SDValue N000 = N00.getOperand(0); 2927 if (!isBSwapHWordElement(N000, Parts)) 2928 return SDValue(); 2929 SDValue N001 = N00.getOperand(1); 2930 if (!isBSwapHWordElement(N001, Parts)) 2931 return SDValue(); 2932 } 2933 2934 // Make sure the parts are all coming from the same node. 2935 if (Parts[0] != Parts[1] || Parts[0] != Parts[2] || Parts[0] != Parts[3]) 2936 return SDValue(); 2937 2938 SDValue BSwap = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT, 2939 SDValue(Parts[0],0)); 2940 2941 // Result of the bswap should be rotated by 16. If it's not legal, than 2942 // do (x << 16) | (x >> 16). 2943 SDValue ShAmt = DAG.getConstant(16, getShiftAmountTy(VT)); 2944 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT)) 2945 return DAG.getNode(ISD::ROTL, N->getDebugLoc(), VT, BSwap, ShAmt); 2946 else if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT)) 2947 return DAG.getNode(ISD::ROTR, N->getDebugLoc(), VT, BSwap, ShAmt); 2948 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, 2949 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, BSwap, ShAmt), 2950 DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, BSwap, ShAmt)); 2951} 2952 2953SDValue DAGCombiner::visitOR(SDNode *N) { 2954 SDValue N0 = N->getOperand(0); 2955 SDValue N1 = N->getOperand(1); 2956 SDValue LL, LR, RL, RR, CC0, CC1; 2957 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2958 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2959 EVT VT = N1.getValueType(); 2960 2961 // fold vector ops 2962 if (VT.isVector()) { 2963 SDValue FoldedVOp = SimplifyVBinOp(N); 2964 if (FoldedVOp.getNode()) return FoldedVOp; 2965 } 2966 2967 // fold (or x, undef) -> -1 2968 if (!LegalOperations && 2969 (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) { 2970 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 2971 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT); 2972 } 2973 // fold (or c1, c2) -> c1|c2 2974 if (N0C && N1C) 2975 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); 2976 // canonicalize constant to RHS 2977 if (N0C && !N1C) 2978 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0); 2979 // fold (or x, 0) -> x 2980 if (N1C && N1C->isNullValue()) 2981 return N0; 2982 // fold (or x, -1) -> -1 2983 if (N1C && N1C->isAllOnesValue()) 2984 return N1; 2985 // fold (or x, c) -> c iff (x & ~c) == 0 2986 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 2987 return N1; 2988 2989 // Recognize halfword bswaps as (bswap + rotl 16) or (bswap + shl 16) 2990 SDValue BSwap = MatchBSwapHWord(N, N0, N1); 2991 if (BSwap.getNode() != 0) 2992 return BSwap; 2993 BSwap = MatchBSwapHWordLow(N, N0, N1); 2994 if (BSwap.getNode() != 0) 2995 return BSwap; 2996 2997 // reassociate or 2998 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1); 2999 if (ROR.getNode() != 0) 3000 return ROR; 3001 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 3002 // iff (c1 & c2) == 0. 3003 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 3004 isa<ConstantSDNode>(N0.getOperand(1))) { 3005 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 3006 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0) 3007 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3008 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 3009 N0.getOperand(0), N1), 3010 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1)); 3011 } 3012 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 3013 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 3014 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 3015 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 3016 3017 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 3018 LL.getValueType().isInteger()) { 3019 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0) 3020 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0) 3021 if (cast<ConstantSDNode>(LR)->isNullValue() && 3022 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 3023 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(), 3024 LR.getValueType(), LL, RL); 3025 AddToWorkList(ORNode.getNode()); 3026 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 3027 } 3028 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1) 3029 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1) 3030 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 3031 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 3032 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(), 3033 LR.getValueType(), LL, RL); 3034 AddToWorkList(ANDNode.getNode()); 3035 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 3036 } 3037 } 3038 // canonicalize equivalent to ll == rl 3039 if (LL == RR && LR == RL) { 3040 Op1 = ISD::getSetCCSwappedOperands(Op1); 3041 std::swap(RL, RR); 3042 } 3043 if (LL == RL && LR == RR) { 3044 bool isInteger = LL.getValueType().isInteger(); 3045 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 3046 if (Result != ISD::SETCC_INVALID && 3047 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 3048 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 3049 LL, LR, Result); 3050 } 3051 } 3052 3053 // Simplify: (or (op x...), (op y...)) -> (op (or x, y)) 3054 if (N0.getOpcode() == N1.getOpcode()) { 3055 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 3056 if (Tmp.getNode()) return Tmp; 3057 } 3058 3059 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible. 3060 if (N0.getOpcode() == ISD::AND && 3061 N1.getOpcode() == ISD::AND && 3062 N0.getOperand(1).getOpcode() == ISD::Constant && 3063 N1.getOperand(1).getOpcode() == ISD::Constant && 3064 // Don't increase # computations. 3065 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) { 3066 // We can only do this xform if we know that bits from X that are set in C2 3067 // but not in C1 are already zero. Likewise for Y. 3068 const APInt &LHSMask = 3069 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3070 const APInt &RHSMask = 3071 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 3072 3073 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 3074 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 3075 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 3076 N0.getOperand(0), N1.getOperand(0)); 3077 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X, 3078 DAG.getConstant(LHSMask | RHSMask, VT)); 3079 } 3080 } 3081 3082 // See if this is some rotate idiom. 3083 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc())) 3084 return SDValue(Rot, 0); 3085 3086 // Simplify the operands using demanded-bits information. 3087 if (!VT.isVector() && 3088 SimplifyDemandedBits(SDValue(N, 0))) 3089 return SDValue(N, 0); 3090 3091 return SDValue(); 3092} 3093 3094/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 3095static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 3096 if (Op.getOpcode() == ISD::AND) { 3097 if (isa<ConstantSDNode>(Op.getOperand(1))) { 3098 Mask = Op.getOperand(1); 3099 Op = Op.getOperand(0); 3100 } else { 3101 return false; 3102 } 3103 } 3104 3105 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 3106 Shift = Op; 3107 return true; 3108 } 3109 3110 return false; 3111} 3112 3113// MatchRotate - Handle an 'or' of two operands. If this is one of the many 3114// idioms for rotate, and if the target supports rotation instructions, generate 3115// a rot[lr]. 3116SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) { 3117 // Must be a legal type. Expanded 'n promoted things won't work with rotates. 3118 EVT VT = LHS.getValueType(); 3119 if (!TLI.isTypeLegal(VT)) return 0; 3120 3121 // The target must have at least one rotate flavor. 3122 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT); 3123 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT); 3124 if (!HasROTL && !HasROTR) return 0; 3125 3126 // Match "(X shl/srl V1) & V2" where V2 may not be present. 3127 SDValue LHSShift; // The shift. 3128 SDValue LHSMask; // AND value if any. 3129 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 3130 return 0; // Not part of a rotate. 3131 3132 SDValue RHSShift; // The shift. 3133 SDValue RHSMask; // AND value if any. 3134 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 3135 return 0; // Not part of a rotate. 3136 3137 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 3138 return 0; // Not shifting the same value. 3139 3140 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 3141 return 0; // Shifts must disagree. 3142 3143 // Canonicalize shl to left side in a shl/srl pair. 3144 if (RHSShift.getOpcode() == ISD::SHL) { 3145 std::swap(LHS, RHS); 3146 std::swap(LHSShift, RHSShift); 3147 std::swap(LHSMask , RHSMask ); 3148 } 3149 3150 unsigned OpSizeInBits = VT.getSizeInBits(); 3151 SDValue LHSShiftArg = LHSShift.getOperand(0); 3152 SDValue LHSShiftAmt = LHSShift.getOperand(1); 3153 SDValue RHSShiftAmt = RHSShift.getOperand(1); 3154 3155 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 3156 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 3157 if (LHSShiftAmt.getOpcode() == ISD::Constant && 3158 RHSShiftAmt.getOpcode() == ISD::Constant) { 3159 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue(); 3160 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue(); 3161 if ((LShVal + RShVal) != OpSizeInBits) 3162 return 0; 3163 3164 SDValue Rot; 3165 if (HasROTL) 3166 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt); 3167 else 3168 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt); 3169 3170 // If there is an AND of either shifted operand, apply it to the result. 3171 if (LHSMask.getNode() || RHSMask.getNode()) { 3172 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 3173 3174 if (LHSMask.getNode()) { 3175 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 3176 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 3177 } 3178 if (RHSMask.getNode()) { 3179 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 3180 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 3181 } 3182 3183 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT)); 3184 } 3185 3186 return Rot.getNode(); 3187 } 3188 3189 // If there is a mask here, and we have a variable shift, we can't be sure 3190 // that we're masking out the right stuff. 3191 if (LHSMask.getNode() || RHSMask.getNode()) 3192 return 0; 3193 3194 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 3195 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 3196 if (RHSShiftAmt.getOpcode() == ISD::SUB && 3197 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 3198 if (ConstantSDNode *SUBC = 3199 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 3200 if (SUBC->getAPIntValue() == OpSizeInBits) { 3201 if (HasROTL) 3202 return DAG.getNode(ISD::ROTL, DL, VT, 3203 LHSShiftArg, LHSShiftAmt).getNode(); 3204 else 3205 return DAG.getNode(ISD::ROTR, DL, VT, 3206 LHSShiftArg, RHSShiftAmt).getNode(); 3207 } 3208 } 3209 } 3210 3211 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 3212 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 3213 if (LHSShiftAmt.getOpcode() == ISD::SUB && 3214 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 3215 if (ConstantSDNode *SUBC = 3216 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 3217 if (SUBC->getAPIntValue() == OpSizeInBits) { 3218 if (HasROTR) 3219 return DAG.getNode(ISD::ROTR, DL, VT, 3220 LHSShiftArg, RHSShiftAmt).getNode(); 3221 else 3222 return DAG.getNode(ISD::ROTL, DL, VT, 3223 LHSShiftArg, LHSShiftAmt).getNode(); 3224 } 3225 } 3226 } 3227 3228 // Look for sign/zext/any-extended or truncate cases: 3229 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 3230 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 3231 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 3232 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && 3233 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 3234 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 3235 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 3236 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { 3237 SDValue LExtOp0 = LHSShiftAmt.getOperand(0); 3238 SDValue RExtOp0 = RHSShiftAmt.getOperand(0); 3239 if (RExtOp0.getOpcode() == ISD::SUB && 3240 RExtOp0.getOperand(1) == LExtOp0) { 3241 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 3242 // (rotl x, y) 3243 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 3244 // (rotr x, (sub 32, y)) 3245 if (ConstantSDNode *SUBC = 3246 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 3247 if (SUBC->getAPIntValue() == OpSizeInBits) { 3248 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 3249 LHSShiftArg, 3250 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 3251 } 3252 } 3253 } else if (LExtOp0.getOpcode() == ISD::SUB && 3254 RExtOp0 == LExtOp0.getOperand(1)) { 3255 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 3256 // (rotr x, y) 3257 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 3258 // (rotl x, (sub 32, y)) 3259 if (ConstantSDNode *SUBC = 3260 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 3261 if (SUBC->getAPIntValue() == OpSizeInBits) { 3262 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, 3263 LHSShiftArg, 3264 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 3265 } 3266 } 3267 } 3268 } 3269 3270 return 0; 3271} 3272 3273SDValue DAGCombiner::visitXOR(SDNode *N) { 3274 SDValue N0 = N->getOperand(0); 3275 SDValue N1 = N->getOperand(1); 3276 SDValue LHS, RHS, CC; 3277 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3278 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3279 EVT VT = N0.getValueType(); 3280 3281 // fold vector ops 3282 if (VT.isVector()) { 3283 SDValue FoldedVOp = SimplifyVBinOp(N); 3284 if (FoldedVOp.getNode()) return FoldedVOp; 3285 } 3286 3287 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 3288 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 3289 return DAG.getConstant(0, VT); 3290 // fold (xor x, undef) -> undef 3291 if (N0.getOpcode() == ISD::UNDEF) 3292 return N0; 3293 if (N1.getOpcode() == ISD::UNDEF) 3294 return N1; 3295 // fold (xor c1, c2) -> c1^c2 3296 if (N0C && N1C) 3297 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); 3298 // canonicalize constant to RHS 3299 if (N0C && !N1C) 3300 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 3301 // fold (xor x, 0) -> x 3302 if (N1C && N1C->isNullValue()) 3303 return N0; 3304 // reassociate xor 3305 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1); 3306 if (RXOR.getNode() != 0) 3307 return RXOR; 3308 3309 // fold !(x cc y) -> (x !cc y) 3310 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 3311 bool isInt = LHS.getValueType().isInteger(); 3312 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 3313 isInt); 3314 3315 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) { 3316 switch (N0.getOpcode()) { 3317 default: 3318 llvm_unreachable("Unhandled SetCC Equivalent!"); 3319 case ISD::SETCC: 3320 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC); 3321 case ISD::SELECT_CC: 3322 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2), 3323 N0.getOperand(3), NotCC); 3324 } 3325 } 3326 } 3327 3328 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 3329 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 3330 N0.getNode()->hasOneUse() && 3331 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 3332 SDValue V = N0.getOperand(0); 3333 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V, 3334 DAG.getConstant(1, V.getValueType())); 3335 AddToWorkList(V.getNode()); 3336 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V); 3337 } 3338 3339 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc 3340 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 3341 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 3342 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 3343 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 3344 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 3345 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 3346 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 3347 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 3348 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 3349 } 3350 } 3351 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants 3352 if (N1C && N1C->isAllOnesValue() && 3353 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 3354 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 3355 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 3356 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 3357 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 3358 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 3359 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 3360 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 3361 } 3362 } 3363 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2)) 3364 if (N1C && N0.getOpcode() == ISD::XOR) { 3365 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 3366 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 3367 if (N00C) 3368 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1), 3369 DAG.getConstant(N1C->getAPIntValue() ^ 3370 N00C->getAPIntValue(), VT)); 3371 if (N01C) 3372 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0), 3373 DAG.getConstant(N1C->getAPIntValue() ^ 3374 N01C->getAPIntValue(), VT)); 3375 } 3376 // fold (xor x, x) -> 0 3377 if (N0 == N1) 3378 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations); 3379 3380 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 3381 if (N0.getOpcode() == N1.getOpcode()) { 3382 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 3383 if (Tmp.getNode()) return Tmp; 3384 } 3385 3386 // Simplify the expression using non-local knowledge. 3387 if (!VT.isVector() && 3388 SimplifyDemandedBits(SDValue(N, 0))) 3389 return SDValue(N, 0); 3390 3391 return SDValue(); 3392} 3393 3394/// visitShiftByConstant - Handle transforms common to the three shifts, when 3395/// the shift amount is a constant. 3396SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 3397 SDNode *LHS = N->getOperand(0).getNode(); 3398 if (!LHS->hasOneUse()) return SDValue(); 3399 3400 // We want to pull some binops through shifts, so that we have (and (shift)) 3401 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 3402 // thing happens with address calculations, so it's important to canonicalize 3403 // it. 3404 bool HighBitSet = false; // Can we transform this if the high bit is set? 3405 3406 switch (LHS->getOpcode()) { 3407 default: return SDValue(); 3408 case ISD::OR: 3409 case ISD::XOR: 3410 HighBitSet = false; // We can only transform sra if the high bit is clear. 3411 break; 3412 case ISD::AND: 3413 HighBitSet = true; // We can only transform sra if the high bit is set. 3414 break; 3415 case ISD::ADD: 3416 if (N->getOpcode() != ISD::SHL) 3417 return SDValue(); // only shl(add) not sr[al](add). 3418 HighBitSet = false; // We can only transform sra if the high bit is clear. 3419 break; 3420 } 3421 3422 // We require the RHS of the binop to be a constant as well. 3423 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 3424 if (!BinOpCst) return SDValue(); 3425 3426 // FIXME: disable this unless the input to the binop is a shift by a constant. 3427 // If it is not a shift, it pessimizes some common cases like: 3428 // 3429 // void foo(int *X, int i) { X[i & 1235] = 1; } 3430 // int bar(int *X, int i) { return X[i & 255]; } 3431 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); 3432 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 3433 BinOpLHSVal->getOpcode() != ISD::SRA && 3434 BinOpLHSVal->getOpcode() != ISD::SRL) || 3435 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 3436 return SDValue(); 3437 3438 EVT VT = N->getValueType(0); 3439 3440 // If this is a signed shift right, and the high bit is modified by the 3441 // logical operation, do not perform the transformation. The highBitSet 3442 // boolean indicates the value of the high bit of the constant which would 3443 // cause it to be modified for this operation. 3444 if (N->getOpcode() == ISD::SRA) { 3445 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 3446 if (BinOpRHSSignSet != HighBitSet) 3447 return SDValue(); 3448 } 3449 3450 // Fold the constants, shifting the binop RHS by the shift amount. 3451 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(), 3452 N->getValueType(0), 3453 LHS->getOperand(1), N->getOperand(1)); 3454 3455 // Create the new shift. 3456 SDValue NewShift = DAG.getNode(N->getOpcode(), 3457 LHS->getOperand(0).getDebugLoc(), 3458 VT, LHS->getOperand(0), N->getOperand(1)); 3459 3460 // Create the new binop. 3461 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS); 3462} 3463 3464SDValue DAGCombiner::visitSHL(SDNode *N) { 3465 SDValue N0 = N->getOperand(0); 3466 SDValue N1 = N->getOperand(1); 3467 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3468 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3469 EVT VT = N0.getValueType(); 3470 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3471 3472 // fold (shl c1, c2) -> c1<<c2 3473 if (N0C && N1C) 3474 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C); 3475 // fold (shl 0, x) -> 0 3476 if (N0C && N0C->isNullValue()) 3477 return N0; 3478 // fold (shl x, c >= size(x)) -> undef 3479 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3480 return DAG.getUNDEF(VT); 3481 // fold (shl x, 0) -> x 3482 if (N1C && N1C->isNullValue()) 3483 return N0; 3484 // fold (shl undef, x) -> 0 3485 if (N0.getOpcode() == ISD::UNDEF) 3486 return DAG.getConstant(0, VT); 3487 // if (shl x, c) is known to be zero, return 0 3488 if (DAG.MaskedValueIsZero(SDValue(N, 0), 3489 APInt::getAllOnesValue(OpSizeInBits))) 3490 return DAG.getConstant(0, VT); 3491 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))). 3492 if (N1.getOpcode() == ISD::TRUNCATE && 3493 N1.getOperand(0).getOpcode() == ISD::AND && 3494 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3495 SDValue N101 = N1.getOperand(0).getOperand(1); 3496 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3497 EVT TruncVT = N1.getValueType(); 3498 SDValue N100 = N1.getOperand(0).getOperand(0); 3499 APInt TruncC = N101C->getAPIntValue(); 3500 TruncC = TruncC.trunc(TruncVT.getSizeInBits()); 3501 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 3502 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT, 3503 DAG.getNode(ISD::TRUNCATE, 3504 N->getDebugLoc(), 3505 TruncVT, N100), 3506 DAG.getConstant(TruncC, TruncVT))); 3507 } 3508 } 3509 3510 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3511 return SDValue(N, 0); 3512 3513 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2)) 3514 if (N1C && N0.getOpcode() == ISD::SHL && 3515 N0.getOperand(1).getOpcode() == ISD::Constant) { 3516 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3517 uint64_t c2 = N1C->getZExtValue(); 3518 if (c1 + c2 >= OpSizeInBits) 3519 return DAG.getConstant(0, VT); 3520 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 3521 DAG.getConstant(c1 + c2, N1.getValueType())); 3522 } 3523 3524 // fold (shl (ext (shl x, c1)), c2) -> (ext (shl x, (add c1, c2))) 3525 // For this to be valid, the second form must not preserve any of the bits 3526 // that are shifted out by the inner shift in the first form. This means 3527 // the outer shift size must be >= the number of bits added by the ext. 3528 // As a corollary, we don't care what kind of ext it is. 3529 if (N1C && (N0.getOpcode() == ISD::ZERO_EXTEND || 3530 N0.getOpcode() == ISD::ANY_EXTEND || 3531 N0.getOpcode() == ISD::SIGN_EXTEND) && 3532 N0.getOperand(0).getOpcode() == ISD::SHL && 3533 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) { 3534 uint64_t c1 = 3535 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue(); 3536 uint64_t c2 = N1C->getZExtValue(); 3537 EVT InnerShiftVT = N0.getOperand(0).getValueType(); 3538 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits(); 3539 if (c2 >= OpSizeInBits - InnerShiftSize) { 3540 if (c1 + c2 >= OpSizeInBits) 3541 return DAG.getConstant(0, VT); 3542 return DAG.getNode(ISD::SHL, N0->getDebugLoc(), VT, 3543 DAG.getNode(N0.getOpcode(), N0->getDebugLoc(), VT, 3544 N0.getOperand(0)->getOperand(0)), 3545 DAG.getConstant(c1 + c2, N1.getValueType())); 3546 } 3547 } 3548 3549 // fold (shl (srl x, c1), c2) -> (and (shl x, (sub c2, c1), MASK) or 3550 // (and (srl x, (sub c1, c2), MASK) 3551 // Only fold this if the inner shift has no other uses -- if it does, folding 3552 // this will increase the total number of instructions. 3553 if (N1C && N0.getOpcode() == ISD::SRL && N0.hasOneUse() && 3554 N0.getOperand(1).getOpcode() == ISD::Constant) { 3555 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3556 if (c1 < VT.getSizeInBits()) { 3557 uint64_t c2 = N1C->getZExtValue(); 3558 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(), 3559 VT.getSizeInBits() - c1); 3560 SDValue Shift; 3561 if (c2 > c1) { 3562 Mask = Mask.shl(c2-c1); 3563 Shift = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 3564 DAG.getConstant(c2-c1, N1.getValueType())); 3565 } else { 3566 Mask = Mask.lshr(c1-c2); 3567 Shift = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 3568 DAG.getConstant(c1-c2, N1.getValueType())); 3569 } 3570 return DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, Shift, 3571 DAG.getConstant(Mask, VT)); 3572 } 3573 } 3574 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1)) 3575 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) { 3576 SDValue HiBitsMask = 3577 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 3578 VT.getSizeInBits() - 3579 N1C->getZExtValue()), 3580 VT); 3581 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 3582 HiBitsMask); 3583 } 3584 3585 if (N1C) { 3586 SDValue NewSHL = visitShiftByConstant(N, N1C->getZExtValue()); 3587 if (NewSHL.getNode()) 3588 return NewSHL; 3589 } 3590 3591 return SDValue(); 3592} 3593 3594SDValue DAGCombiner::visitSRA(SDNode *N) { 3595 SDValue N0 = N->getOperand(0); 3596 SDValue N1 = N->getOperand(1); 3597 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3598 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3599 EVT VT = N0.getValueType(); 3600 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3601 3602 // fold (sra c1, c2) -> (sra c1, c2) 3603 if (N0C && N1C) 3604 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); 3605 // fold (sra 0, x) -> 0 3606 if (N0C && N0C->isNullValue()) 3607 return N0; 3608 // fold (sra -1, x) -> -1 3609 if (N0C && N0C->isAllOnesValue()) 3610 return N0; 3611 // fold (sra x, (setge c, size(x))) -> undef 3612 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3613 return DAG.getUNDEF(VT); 3614 // fold (sra x, 0) -> x 3615 if (N1C && N1C->isNullValue()) 3616 return N0; 3617 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 3618 // sext_inreg. 3619 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 3620 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue(); 3621 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits); 3622 if (VT.isVector()) 3623 ExtVT = EVT::getVectorVT(*DAG.getContext(), 3624 ExtVT, VT.getVectorNumElements()); 3625 if ((!LegalOperations || 3626 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT))) 3627 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 3628 N0.getOperand(0), DAG.getValueType(ExtVT)); 3629 } 3630 3631 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) 3632 if (N1C && N0.getOpcode() == ISD::SRA) { 3633 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3634 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); 3635 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1; 3636 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0), 3637 DAG.getConstant(Sum, N1C->getValueType(0))); 3638 } 3639 } 3640 3641 // fold (sra (shl X, m), (sub result_size, n)) 3642 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for 3643 // result_size - n != m. 3644 // If truncate is free for the target sext(shl) is likely to result in better 3645 // code. 3646 if (N0.getOpcode() == ISD::SHL) { 3647 // Get the two constanst of the shifts, CN0 = m, CN = n. 3648 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 3649 if (N01C && N1C) { 3650 // Determine what the truncate's result bitsize and type would be. 3651 EVT TruncVT = 3652 EVT::getIntegerVT(*DAG.getContext(), 3653 OpSizeInBits - N1C->getZExtValue()); 3654 // Determine the residual right-shift amount. 3655 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); 3656 3657 // If the shift is not a no-op (in which case this should be just a sign 3658 // extend already), the truncated to type is legal, sign_extend is legal 3659 // on that type, and the truncate to that type is both legal and free, 3660 // perform the transform. 3661 if ((ShiftAmt > 0) && 3662 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) && 3663 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) && 3664 TLI.isTruncateFree(VT, TruncVT)) { 3665 3666 SDValue Amt = DAG.getConstant(ShiftAmt, 3667 getShiftAmountTy(N0.getOperand(0).getValueType())); 3668 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, 3669 N0.getOperand(0), Amt); 3670 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT, 3671 Shift); 3672 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), 3673 N->getValueType(0), Trunc); 3674 } 3675 } 3676 } 3677 3678 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))). 3679 if (N1.getOpcode() == ISD::TRUNCATE && 3680 N1.getOperand(0).getOpcode() == ISD::AND && 3681 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3682 SDValue N101 = N1.getOperand(0).getOperand(1); 3683 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3684 EVT TruncVT = N1.getValueType(); 3685 SDValue N100 = N1.getOperand(0).getOperand(0); 3686 APInt TruncC = N101C->getAPIntValue(); 3687 TruncC = TruncC.trunc(TruncVT.getScalarType().getSizeInBits()); 3688 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 3689 DAG.getNode(ISD::AND, N->getDebugLoc(), 3690 TruncVT, 3691 DAG.getNode(ISD::TRUNCATE, 3692 N->getDebugLoc(), 3693 TruncVT, N100), 3694 DAG.getConstant(TruncC, TruncVT))); 3695 } 3696 } 3697 3698 // fold (sra (trunc (sr x, c1)), c2) -> (trunc (sra x, c1+c2)) 3699 // if c1 is equal to the number of bits the trunc removes 3700 if (N0.getOpcode() == ISD::TRUNCATE && 3701 (N0.getOperand(0).getOpcode() == ISD::SRL || 3702 N0.getOperand(0).getOpcode() == ISD::SRA) && 3703 N0.getOperand(0).hasOneUse() && 3704 N0.getOperand(0).getOperand(1).hasOneUse() && 3705 N1C && isa<ConstantSDNode>(N0.getOperand(0).getOperand(1))) { 3706 EVT LargeVT = N0.getOperand(0).getValueType(); 3707 ConstantSDNode *LargeShiftAmt = 3708 cast<ConstantSDNode>(N0.getOperand(0).getOperand(1)); 3709 3710 if (LargeVT.getScalarType().getSizeInBits() - OpSizeInBits == 3711 LargeShiftAmt->getZExtValue()) { 3712 SDValue Amt = 3713 DAG.getConstant(LargeShiftAmt->getZExtValue() + N1C->getZExtValue(), 3714 getShiftAmountTy(N0.getOperand(0).getOperand(0).getValueType())); 3715 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), LargeVT, 3716 N0.getOperand(0).getOperand(0), Amt); 3717 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, SRA); 3718 } 3719 } 3720 3721 // Simplify, based on bits shifted out of the LHS. 3722 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3723 return SDValue(N, 0); 3724 3725 3726 // If the sign bit is known to be zero, switch this to a SRL. 3727 if (DAG.SignBitIsZero(N0)) 3728 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1); 3729 3730 if (N1C) { 3731 SDValue NewSRA = visitShiftByConstant(N, N1C->getZExtValue()); 3732 if (NewSRA.getNode()) 3733 return NewSRA; 3734 } 3735 3736 return SDValue(); 3737} 3738 3739SDValue DAGCombiner::visitSRL(SDNode *N) { 3740 SDValue N0 = N->getOperand(0); 3741 SDValue N1 = N->getOperand(1); 3742 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3743 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3744 EVT VT = N0.getValueType(); 3745 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3746 3747 // fold (srl c1, c2) -> c1 >>u c2 3748 if (N0C && N1C) 3749 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); 3750 // fold (srl 0, x) -> 0 3751 if (N0C && N0C->isNullValue()) 3752 return N0; 3753 // fold (srl x, c >= size(x)) -> undef 3754 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3755 return DAG.getUNDEF(VT); 3756 // fold (srl x, 0) -> x 3757 if (N1C && N1C->isNullValue()) 3758 return N0; 3759 // if (srl x, c) is known to be zero, return 0 3760 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 3761 APInt::getAllOnesValue(OpSizeInBits))) 3762 return DAG.getConstant(0, VT); 3763 3764 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2)) 3765 if (N1C && N0.getOpcode() == ISD::SRL && 3766 N0.getOperand(1).getOpcode() == ISD::Constant) { 3767 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3768 uint64_t c2 = N1C->getZExtValue(); 3769 if (c1 + c2 >= OpSizeInBits) 3770 return DAG.getConstant(0, VT); 3771 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 3772 DAG.getConstant(c1 + c2, N1.getValueType())); 3773 } 3774 3775 // fold (srl (trunc (srl x, c1)), c2) -> 0 or (trunc (srl x, (add c1, c2))) 3776 if (N1C && N0.getOpcode() == ISD::TRUNCATE && 3777 N0.getOperand(0).getOpcode() == ISD::SRL && 3778 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) { 3779 uint64_t c1 = 3780 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue(); 3781 uint64_t c2 = N1C->getZExtValue(); 3782 EVT InnerShiftVT = N0.getOperand(0).getValueType(); 3783 EVT ShiftCountVT = N0.getOperand(0)->getOperand(1).getValueType(); 3784 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits(); 3785 // This is only valid if the OpSizeInBits + c1 = size of inner shift. 3786 if (c1 + OpSizeInBits == InnerShiftSize) { 3787 if (c1 + c2 >= InnerShiftSize) 3788 return DAG.getConstant(0, VT); 3789 return DAG.getNode(ISD::TRUNCATE, N0->getDebugLoc(), VT, 3790 DAG.getNode(ISD::SRL, N0->getDebugLoc(), InnerShiftVT, 3791 N0.getOperand(0)->getOperand(0), 3792 DAG.getConstant(c1 + c2, ShiftCountVT))); 3793 } 3794 } 3795 3796 // fold (srl (shl x, c), c) -> (and x, cst2) 3797 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 && 3798 N0.getValueSizeInBits() <= 64) { 3799 uint64_t ShAmt = N1C->getZExtValue()+64-N0.getValueSizeInBits(); 3800 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 3801 DAG.getConstant(~0ULL >> ShAmt, VT)); 3802 } 3803 3804 3805 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 3806 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 3807 // Shifting in all undef bits? 3808 EVT SmallVT = N0.getOperand(0).getValueType(); 3809 if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) 3810 return DAG.getUNDEF(VT); 3811 3812 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) { 3813 uint64_t ShiftAmt = N1C->getZExtValue(); 3814 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT, 3815 N0.getOperand(0), 3816 DAG.getConstant(ShiftAmt, getShiftAmountTy(SmallVT))); 3817 AddToWorkList(SmallShift.getNode()); 3818 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift); 3819 } 3820 } 3821 3822 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 3823 // bit, which is unmodified by sra. 3824 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) { 3825 if (N0.getOpcode() == ISD::SRA) 3826 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1); 3827 } 3828 3829 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 3830 if (N1C && N0.getOpcode() == ISD::CTLZ && 3831 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 3832 APInt KnownZero, KnownOne; 3833 DAG.ComputeMaskedBits(N0.getOperand(0), KnownZero, KnownOne); 3834 3835 // If any of the input bits are KnownOne, then the input couldn't be all 3836 // zeros, thus the result of the srl will always be zero. 3837 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 3838 3839 // If all of the bits input the to ctlz node are known to be zero, then 3840 // the result of the ctlz is "32" and the result of the shift is one. 3841 APInt UnknownBits = ~KnownZero; 3842 if (UnknownBits == 0) return DAG.getConstant(1, VT); 3843 3844 // Otherwise, check to see if there is exactly one bit input to the ctlz. 3845 if ((UnknownBits & (UnknownBits - 1)) == 0) { 3846 // Okay, we know that only that the single bit specified by UnknownBits 3847 // could be set on input to the CTLZ node. If this bit is set, the SRL 3848 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 3849 // to an SRL/XOR pair, which is likely to simplify more. 3850 unsigned ShAmt = UnknownBits.countTrailingZeros(); 3851 SDValue Op = N0.getOperand(0); 3852 3853 if (ShAmt) { 3854 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op, 3855 DAG.getConstant(ShAmt, getShiftAmountTy(Op.getValueType()))); 3856 AddToWorkList(Op.getNode()); 3857 } 3858 3859 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 3860 Op, DAG.getConstant(1, VT)); 3861 } 3862 } 3863 3864 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))). 3865 if (N1.getOpcode() == ISD::TRUNCATE && 3866 N1.getOperand(0).getOpcode() == ISD::AND && 3867 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3868 SDValue N101 = N1.getOperand(0).getOperand(1); 3869 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3870 EVT TruncVT = N1.getValueType(); 3871 SDValue N100 = N1.getOperand(0).getOperand(0); 3872 APInt TruncC = N101C->getAPIntValue(); 3873 TruncC = TruncC.trunc(TruncVT.getSizeInBits()); 3874 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 3875 DAG.getNode(ISD::AND, N->getDebugLoc(), 3876 TruncVT, 3877 DAG.getNode(ISD::TRUNCATE, 3878 N->getDebugLoc(), 3879 TruncVT, N100), 3880 DAG.getConstant(TruncC, TruncVT))); 3881 } 3882 } 3883 3884 // fold operands of srl based on knowledge that the low bits are not 3885 // demanded. 3886 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3887 return SDValue(N, 0); 3888 3889 if (N1C) { 3890 SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue()); 3891 if (NewSRL.getNode()) 3892 return NewSRL; 3893 } 3894 3895 // Attempt to convert a srl of a load into a narrower zero-extending load. 3896 SDValue NarrowLoad = ReduceLoadWidth(N); 3897 if (NarrowLoad.getNode()) 3898 return NarrowLoad; 3899 3900 // Here is a common situation. We want to optimize: 3901 // 3902 // %a = ... 3903 // %b = and i32 %a, 2 3904 // %c = srl i32 %b, 1 3905 // brcond i32 %c ... 3906 // 3907 // into 3908 // 3909 // %a = ... 3910 // %b = and %a, 2 3911 // %c = setcc eq %b, 0 3912 // brcond %c ... 3913 // 3914 // However when after the source operand of SRL is optimized into AND, the SRL 3915 // itself may not be optimized further. Look for it and add the BRCOND into 3916 // the worklist. 3917 if (N->hasOneUse()) { 3918 SDNode *Use = *N->use_begin(); 3919 if (Use->getOpcode() == ISD::BRCOND) 3920 AddToWorkList(Use); 3921 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) { 3922 // Also look pass the truncate. 3923 Use = *Use->use_begin(); 3924 if (Use->getOpcode() == ISD::BRCOND) 3925 AddToWorkList(Use); 3926 } 3927 } 3928 3929 return SDValue(); 3930} 3931 3932SDValue DAGCombiner::visitCTLZ(SDNode *N) { 3933 SDValue N0 = N->getOperand(0); 3934 EVT VT = N->getValueType(0); 3935 3936 // fold (ctlz c1) -> c2 3937 if (isa<ConstantSDNode>(N0)) 3938 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0); 3939 return SDValue(); 3940} 3941 3942SDValue DAGCombiner::visitCTLZ_ZERO_UNDEF(SDNode *N) { 3943 SDValue N0 = N->getOperand(0); 3944 EVT VT = N->getValueType(0); 3945 3946 // fold (ctlz_zero_undef c1) -> c2 3947 if (isa<ConstantSDNode>(N0)) 3948 return DAG.getNode(ISD::CTLZ_ZERO_UNDEF, N->getDebugLoc(), VT, N0); 3949 return SDValue(); 3950} 3951 3952SDValue DAGCombiner::visitCTTZ(SDNode *N) { 3953 SDValue N0 = N->getOperand(0); 3954 EVT VT = N->getValueType(0); 3955 3956 // fold (cttz c1) -> c2 3957 if (isa<ConstantSDNode>(N0)) 3958 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0); 3959 return SDValue(); 3960} 3961 3962SDValue DAGCombiner::visitCTTZ_ZERO_UNDEF(SDNode *N) { 3963 SDValue N0 = N->getOperand(0); 3964 EVT VT = N->getValueType(0); 3965 3966 // fold (cttz_zero_undef c1) -> c2 3967 if (isa<ConstantSDNode>(N0)) 3968 return DAG.getNode(ISD::CTTZ_ZERO_UNDEF, N->getDebugLoc(), VT, N0); 3969 return SDValue(); 3970} 3971 3972SDValue DAGCombiner::visitCTPOP(SDNode *N) { 3973 SDValue N0 = N->getOperand(0); 3974 EVT VT = N->getValueType(0); 3975 3976 // fold (ctpop c1) -> c2 3977 if (isa<ConstantSDNode>(N0)) 3978 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0); 3979 return SDValue(); 3980} 3981 3982SDValue DAGCombiner::visitSELECT(SDNode *N) { 3983 SDValue N0 = N->getOperand(0); 3984 SDValue N1 = N->getOperand(1); 3985 SDValue N2 = N->getOperand(2); 3986 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3987 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3988 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 3989 EVT VT = N->getValueType(0); 3990 EVT VT0 = N0.getValueType(); 3991 3992 // fold (select C, X, X) -> X 3993 if (N1 == N2) 3994 return N1; 3995 // fold (select true, X, Y) -> X 3996 if (N0C && !N0C->isNullValue()) 3997 return N1; 3998 // fold (select false, X, Y) -> Y 3999 if (N0C && N0C->isNullValue()) 4000 return N2; 4001 // fold (select C, 1, X) -> (or C, X) 4002 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 4003 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 4004 // fold (select C, 0, 1) -> (xor C, 1) 4005 if (VT.isInteger() && 4006 (VT0 == MVT::i1 || 4007 (VT0.isInteger() && 4008 TLI.getBooleanContents(false) == TargetLowering::ZeroOrOneBooleanContent)) && 4009 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 4010 SDValue XORNode; 4011 if (VT == VT0) 4012 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0, 4013 N0, DAG.getConstant(1, VT0)); 4014 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0, 4015 N0, DAG.getConstant(1, VT0)); 4016 AddToWorkList(XORNode.getNode()); 4017 if (VT.bitsGT(VT0)) 4018 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode); 4019 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode); 4020 } 4021 // fold (select C, 0, X) -> (and (not C), X) 4022 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 4023 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 4024 AddToWorkList(NOTNode.getNode()); 4025 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2); 4026 } 4027 // fold (select C, X, 1) -> (or (not C), X) 4028 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 4029 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 4030 AddToWorkList(NOTNode.getNode()); 4031 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1); 4032 } 4033 // fold (select C, X, 0) -> (and C, X) 4034 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 4035 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 4036 // fold (select X, X, Y) -> (or X, Y) 4037 // fold (select X, 1, Y) -> (or X, Y) 4038 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1))) 4039 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 4040 // fold (select X, Y, X) -> (and X, Y) 4041 // fold (select X, Y, 0) -> (and X, Y) 4042 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0))) 4043 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 4044 4045 // If we can fold this based on the true/false value, do so. 4046 if (SimplifySelectOps(N, N1, N2)) 4047 return SDValue(N, 0); // Don't revisit N. 4048 4049 // fold selects based on a setcc into other things, such as min/max/abs 4050 if (N0.getOpcode() == ISD::SETCC) { 4051 // FIXME: 4052 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 4053 // having to say they don't support SELECT_CC on every type the DAG knows 4054 // about, since there is no way to mark an opcode illegal at all value types 4055 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) && 4056 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT)) 4057 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, 4058 N0.getOperand(0), N0.getOperand(1), 4059 N1, N2, N0.getOperand(2)); 4060 return SimplifySelect(N->getDebugLoc(), N0, N1, N2); 4061 } 4062 4063 return SDValue(); 4064} 4065 4066SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 4067 SDValue N0 = N->getOperand(0); 4068 SDValue N1 = N->getOperand(1); 4069 SDValue N2 = N->getOperand(2); 4070 SDValue N3 = N->getOperand(3); 4071 SDValue N4 = N->getOperand(4); 4072 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 4073 4074 // fold select_cc lhs, rhs, x, x, cc -> x 4075 if (N2 == N3) 4076 return N2; 4077 4078 // Determine if the condition we're dealing with is constant 4079 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 4080 N0, N1, CC, N->getDebugLoc(), false); 4081 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 4082 4083 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) { 4084 if (!SCCC->isNullValue()) 4085 return N2; // cond always true -> true val 4086 else 4087 return N3; // cond always false -> false val 4088 } 4089 4090 // Fold to a simpler select_cc 4091 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) 4092 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(), 4093 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 4094 SCC.getOperand(2)); 4095 4096 // If we can fold this based on the true/false value, do so. 4097 if (SimplifySelectOps(N, N2, N3)) 4098 return SDValue(N, 0); // Don't revisit N. 4099 4100 // fold select_cc into other things, such as min/max/abs 4101 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC); 4102} 4103 4104SDValue DAGCombiner::visitSETCC(SDNode *N) { 4105 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 4106 cast<CondCodeSDNode>(N->getOperand(2))->get(), 4107 N->getDebugLoc()); 4108} 4109 4110// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 4111// "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))" 4112// transformation. Returns true if extension are possible and the above 4113// mentioned transformation is profitable. 4114static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 4115 unsigned ExtOpc, 4116 SmallVector<SDNode*, 4> &ExtendNodes, 4117 const TargetLowering &TLI) { 4118 bool HasCopyToRegUses = false; 4119 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 4120 for (SDNode::use_iterator UI = N0.getNode()->use_begin(), 4121 UE = N0.getNode()->use_end(); 4122 UI != UE; ++UI) { 4123 SDNode *User = *UI; 4124 if (User == N) 4125 continue; 4126 if (UI.getUse().getResNo() != N0.getResNo()) 4127 continue; 4128 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 4129 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { 4130 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 4131 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 4132 // Sign bits will be lost after a zext. 4133 return false; 4134 bool Add = false; 4135 for (unsigned i = 0; i != 2; ++i) { 4136 SDValue UseOp = User->getOperand(i); 4137 if (UseOp == N0) 4138 continue; 4139 if (!isa<ConstantSDNode>(UseOp)) 4140 return false; 4141 Add = true; 4142 } 4143 if (Add) 4144 ExtendNodes.push_back(User); 4145 continue; 4146 } 4147 // If truncates aren't free and there are users we can't 4148 // extend, it isn't worthwhile. 4149 if (!isTruncFree) 4150 return false; 4151 // Remember if this value is live-out. 4152 if (User->getOpcode() == ISD::CopyToReg) 4153 HasCopyToRegUses = true; 4154 } 4155 4156 if (HasCopyToRegUses) { 4157 bool BothLiveOut = false; 4158 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 4159 UI != UE; ++UI) { 4160 SDUse &Use = UI.getUse(); 4161 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) { 4162 BothLiveOut = true; 4163 break; 4164 } 4165 } 4166 if (BothLiveOut) 4167 // Both unextended and extended values are live out. There had better be 4168 // a good reason for the transformation. 4169 return ExtendNodes.size(); 4170 } 4171 return true; 4172} 4173 4174void DAGCombiner::ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs, 4175 SDValue Trunc, SDValue ExtLoad, DebugLoc DL, 4176 ISD::NodeType ExtType) { 4177 // Extend SetCC uses if necessary. 4178 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 4179 SDNode *SetCC = SetCCs[i]; 4180 SmallVector<SDValue, 4> Ops; 4181 4182 for (unsigned j = 0; j != 2; ++j) { 4183 SDValue SOp = SetCC->getOperand(j); 4184 if (SOp == Trunc) 4185 Ops.push_back(ExtLoad); 4186 else 4187 Ops.push_back(DAG.getNode(ExtType, DL, ExtLoad->getValueType(0), SOp)); 4188 } 4189 4190 Ops.push_back(SetCC->getOperand(2)); 4191 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0), 4192 &Ops[0], Ops.size())); 4193 } 4194} 4195 4196SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 4197 SDValue N0 = N->getOperand(0); 4198 EVT VT = N->getValueType(0); 4199 4200 // fold (sext c1) -> c1 4201 if (isa<ConstantSDNode>(N0)) 4202 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0); 4203 4204 // fold (sext (sext x)) -> (sext x) 4205 // fold (sext (aext x)) -> (sext x) 4206 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 4207 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, 4208 N0.getOperand(0)); 4209 4210 if (N0.getOpcode() == ISD::TRUNCATE) { 4211 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 4212 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 4213 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4214 if (NarrowLoad.getNode()) { 4215 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4216 if (NarrowLoad.getNode() != N0.getNode()) { 4217 CombineTo(N0.getNode(), NarrowLoad); 4218 // CombineTo deleted the truncate, if needed, but not what's under it. 4219 AddToWorkList(oye); 4220 } 4221 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4222 } 4223 4224 // See if the value being truncated is already sign extended. If so, just 4225 // eliminate the trunc/sext pair. 4226 SDValue Op = N0.getOperand(0); 4227 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits(); 4228 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits(); 4229 unsigned DestBits = VT.getScalarType().getSizeInBits(); 4230 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 4231 4232 if (OpBits == DestBits) { 4233 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 4234 // bits, it is already ready. 4235 if (NumSignBits > DestBits-MidBits) 4236 return Op; 4237 } else if (OpBits < DestBits) { 4238 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 4239 // bits, just sext from i32. 4240 if (NumSignBits > OpBits-MidBits) 4241 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op); 4242 } else { 4243 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 4244 // bits, just truncate to i32. 4245 if (NumSignBits > OpBits-MidBits) 4246 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 4247 } 4248 4249 // fold (sext (truncate x)) -> (sextinreg x). 4250 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 4251 N0.getValueType())) { 4252 if (OpBits < DestBits) 4253 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op); 4254 else if (OpBits > DestBits) 4255 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op); 4256 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op, 4257 DAG.getValueType(N0.getValueType())); 4258 } 4259 } 4260 4261 // fold (sext (load x)) -> (sext (truncate (sextload x))) 4262 // None of the supported targets knows how to perform load and sign extend 4263 // on vectors in one instruction. We only perform this transformation on 4264 // scalars. 4265 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4266 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4267 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { 4268 bool DoXform = true; 4269 SmallVector<SDNode*, 4> SetCCs; 4270 if (!N0.hasOneUse()) 4271 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 4272 if (DoXform) { 4273 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4274 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 4275 LN0->getChain(), 4276 LN0->getBasePtr(), LN0->getPointerInfo(), 4277 N0.getValueType(), 4278 LN0->isVolatile(), LN0->isNonTemporal(), 4279 LN0->getAlignment()); 4280 CombineTo(N, ExtLoad); 4281 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4282 N0.getValueType(), ExtLoad); 4283 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4284 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4285 ISD::SIGN_EXTEND); 4286 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4287 } 4288 } 4289 4290 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 4291 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 4292 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 4293 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 4294 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4295 EVT MemVT = LN0->getMemoryVT(); 4296 if ((!LegalOperations && !LN0->isVolatile()) || 4297 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) { 4298 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 4299 LN0->getChain(), 4300 LN0->getBasePtr(), LN0->getPointerInfo(), 4301 MemVT, 4302 LN0->isVolatile(), LN0->isNonTemporal(), 4303 LN0->getAlignment()); 4304 CombineTo(N, ExtLoad); 4305 CombineTo(N0.getNode(), 4306 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4307 N0.getValueType(), ExtLoad), 4308 ExtLoad.getValue(1)); 4309 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4310 } 4311 } 4312 4313 // fold (sext (and/or/xor (load x), cst)) -> 4314 // (and/or/xor (sextload x), (sext cst)) 4315 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR || 4316 N0.getOpcode() == ISD::XOR) && 4317 isa<LoadSDNode>(N0.getOperand(0)) && 4318 N0.getOperand(1).getOpcode() == ISD::Constant && 4319 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()) && 4320 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) { 4321 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0)); 4322 if (LN0->getExtensionType() != ISD::ZEXTLOAD) { 4323 bool DoXform = true; 4324 SmallVector<SDNode*, 4> SetCCs; 4325 if (!N0.hasOneUse()) 4326 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::SIGN_EXTEND, 4327 SetCCs, TLI); 4328 if (DoXform) { 4329 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, LN0->getDebugLoc(), VT, 4330 LN0->getChain(), LN0->getBasePtr(), 4331 LN0->getPointerInfo(), 4332 LN0->getMemoryVT(), 4333 LN0->isVolatile(), 4334 LN0->isNonTemporal(), 4335 LN0->getAlignment()); 4336 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4337 Mask = Mask.sext(VT.getSizeInBits()); 4338 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 4339 ExtLoad, DAG.getConstant(Mask, VT)); 4340 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, 4341 N0.getOperand(0).getDebugLoc(), 4342 N0.getOperand(0).getValueType(), ExtLoad); 4343 CombineTo(N, And); 4344 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1)); 4345 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4346 ISD::SIGN_EXTEND); 4347 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4348 } 4349 } 4350 } 4351 4352 if (N0.getOpcode() == ISD::SETCC) { 4353 // sext(setcc) -> sext_in_reg(vsetcc) for vectors. 4354 // Only do this before legalize for now. 4355 if (VT.isVector() && !LegalOperations) { 4356 EVT N0VT = N0.getOperand(0).getValueType(); 4357 // We know that the # elements of the results is the same as the 4358 // # elements of the compare (and the # elements of the compare result 4359 // for that matter). Check to see that they are the same size. If so, 4360 // we know that the element size of the sext'd result matches the 4361 // element size of the compare operands. 4362 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 4363 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4364 N0.getOperand(1), 4365 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4366 // If the desired elements are smaller or larger than the source 4367 // elements we can use a matching integer vector type and then 4368 // truncate/sign extend 4369 else { 4370 EVT MatchingElementType = 4371 EVT::getIntegerVT(*DAG.getContext(), 4372 N0VT.getScalarType().getSizeInBits()); 4373 EVT MatchingVectorType = 4374 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4375 N0VT.getVectorNumElements()); 4376 SDValue VsetCC = 4377 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 4378 N0.getOperand(1), 4379 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4380 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); 4381 } 4382 } 4383 4384 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc) 4385 unsigned ElementWidth = VT.getScalarType().getSizeInBits(); 4386 SDValue NegOne = 4387 DAG.getConstant(APInt::getAllOnesValue(ElementWidth), VT); 4388 SDValue SCC = 4389 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4390 NegOne, DAG.getConstant(0, VT), 4391 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4392 if (SCC.getNode()) return SCC; 4393 if (!LegalOperations || 4394 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT))) 4395 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT, 4396 DAG.getSetCC(N->getDebugLoc(), 4397 TLI.getSetCCResultType(VT), 4398 N0.getOperand(0), N0.getOperand(1), 4399 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 4400 NegOne, DAG.getConstant(0, VT)); 4401 } 4402 4403 // fold (sext x) -> (zext x) if the sign bit is known zero. 4404 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 4405 DAG.SignBitIsZero(N0)) 4406 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 4407 4408 return SDValue(); 4409} 4410 4411// isTruncateOf - If N is a truncate of some other value, return true, record 4412// the value being truncated in Op and which of Op's bits are zero in KnownZero. 4413// This function computes KnownZero to avoid a duplicated call to 4414// ComputeMaskedBits in the caller. 4415static bool isTruncateOf(SelectionDAG &DAG, SDValue N, SDValue &Op, 4416 APInt &KnownZero) { 4417 APInt KnownOne; 4418 if (N->getOpcode() == ISD::TRUNCATE) { 4419 Op = N->getOperand(0); 4420 DAG.ComputeMaskedBits(Op, KnownZero, KnownOne); 4421 return true; 4422 } 4423 4424 if (N->getOpcode() != ISD::SETCC || N->getValueType(0) != MVT::i1 || 4425 cast<CondCodeSDNode>(N->getOperand(2))->get() != ISD::SETNE) 4426 return false; 4427 4428 SDValue Op0 = N->getOperand(0); 4429 SDValue Op1 = N->getOperand(1); 4430 assert(Op0.getValueType() == Op1.getValueType()); 4431 4432 ConstantSDNode *COp0 = dyn_cast<ConstantSDNode>(Op0); 4433 ConstantSDNode *COp1 = dyn_cast<ConstantSDNode>(Op1); 4434 if (COp0 && COp0->isNullValue()) 4435 Op = Op1; 4436 else if (COp1 && COp1->isNullValue()) 4437 Op = Op0; 4438 else 4439 return false; 4440 4441 DAG.ComputeMaskedBits(Op, KnownZero, KnownOne); 4442 4443 if (!(KnownZero | APInt(Op.getValueSizeInBits(), 1)).isAllOnesValue()) 4444 return false; 4445 4446 return true; 4447} 4448 4449SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 4450 SDValue N0 = N->getOperand(0); 4451 EVT VT = N->getValueType(0); 4452 4453 // fold (zext c1) -> c1 4454 if (isa<ConstantSDNode>(N0)) 4455 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 4456 // fold (zext (zext x)) -> (zext x) 4457 // fold (zext (aext x)) -> (zext x) 4458 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 4459 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, 4460 N0.getOperand(0)); 4461 4462 // fold (zext (truncate x)) -> (zext x) or 4463 // (zext (truncate x)) -> (truncate x) 4464 // This is valid when the truncated bits of x are already zero. 4465 // FIXME: We should extend this to work for vectors too. 4466 SDValue Op; 4467 APInt KnownZero; 4468 if (!VT.isVector() && isTruncateOf(DAG, N0, Op, KnownZero)) { 4469 APInt TruncatedBits = 4470 (Op.getValueSizeInBits() == N0.getValueSizeInBits()) ? 4471 APInt(Op.getValueSizeInBits(), 0) : 4472 APInt::getBitsSet(Op.getValueSizeInBits(), 4473 N0.getValueSizeInBits(), 4474 std::min(Op.getValueSizeInBits(), 4475 VT.getSizeInBits())); 4476 if (TruncatedBits == (KnownZero & TruncatedBits)) { 4477 if (VT.bitsGT(Op.getValueType())) 4478 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, Op); 4479 if (VT.bitsLT(Op.getValueType())) 4480 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 4481 4482 return Op; 4483 } 4484 } 4485 4486 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 4487 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 4488 if (N0.getOpcode() == ISD::TRUNCATE) { 4489 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4490 if (NarrowLoad.getNode()) { 4491 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4492 if (NarrowLoad.getNode() != N0.getNode()) { 4493 CombineTo(N0.getNode(), NarrowLoad); 4494 // CombineTo deleted the truncate, if needed, but not what's under it. 4495 AddToWorkList(oye); 4496 } 4497 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4498 } 4499 } 4500 4501 // fold (zext (truncate x)) -> (and x, mask) 4502 if (N0.getOpcode() == ISD::TRUNCATE && 4503 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) { 4504 4505 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 4506 // fold (zext (truncate (srl (load x), c))) -> (zext (smaller load (x+c/n))) 4507 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4508 if (NarrowLoad.getNode()) { 4509 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4510 if (NarrowLoad.getNode() != N0.getNode()) { 4511 CombineTo(N0.getNode(), NarrowLoad); 4512 // CombineTo deleted the truncate, if needed, but not what's under it. 4513 AddToWorkList(oye); 4514 } 4515 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4516 } 4517 4518 SDValue Op = N0.getOperand(0); 4519 if (Op.getValueType().bitsLT(VT)) { 4520 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op); 4521 } else if (Op.getValueType().bitsGT(VT)) { 4522 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 4523 } 4524 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), 4525 N0.getValueType().getScalarType()); 4526 } 4527 4528 // Fold (zext (and (trunc x), cst)) -> (and x, cst), 4529 // if either of the casts is not free. 4530 if (N0.getOpcode() == ISD::AND && 4531 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 4532 N0.getOperand(1).getOpcode() == ISD::Constant && 4533 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 4534 N0.getValueType()) || 4535 !TLI.isZExtFree(N0.getValueType(), VT))) { 4536 SDValue X = N0.getOperand(0).getOperand(0); 4537 if (X.getValueType().bitsLT(VT)) { 4538 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X); 4539 } else if (X.getValueType().bitsGT(VT)) { 4540 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 4541 } 4542 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4543 Mask = Mask.zext(VT.getSizeInBits()); 4544 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4545 X, DAG.getConstant(Mask, VT)); 4546 } 4547 4548 // fold (zext (load x)) -> (zext (truncate (zextload x))) 4549 // None of the supported targets knows how to perform load and vector_zext 4550 // on vectors in one instruction. We only perform this transformation on 4551 // scalars. 4552 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4553 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4554 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 4555 bool DoXform = true; 4556 SmallVector<SDNode*, 4> SetCCs; 4557 if (!N0.hasOneUse()) 4558 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 4559 if (DoXform) { 4560 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4561 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 4562 LN0->getChain(), 4563 LN0->getBasePtr(), LN0->getPointerInfo(), 4564 N0.getValueType(), 4565 LN0->isVolatile(), LN0->isNonTemporal(), 4566 LN0->getAlignment()); 4567 CombineTo(N, ExtLoad); 4568 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4569 N0.getValueType(), ExtLoad); 4570 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4571 4572 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4573 ISD::ZERO_EXTEND); 4574 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4575 } 4576 } 4577 4578 // fold (zext (and/or/xor (load x), cst)) -> 4579 // (and/or/xor (zextload x), (zext cst)) 4580 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR || 4581 N0.getOpcode() == ISD::XOR) && 4582 isa<LoadSDNode>(N0.getOperand(0)) && 4583 N0.getOperand(1).getOpcode() == ISD::Constant && 4584 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()) && 4585 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) { 4586 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0)); 4587 if (LN0->getExtensionType() != ISD::SEXTLOAD) { 4588 bool DoXform = true; 4589 SmallVector<SDNode*, 4> SetCCs; 4590 if (!N0.hasOneUse()) 4591 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::ZERO_EXTEND, 4592 SetCCs, TLI); 4593 if (DoXform) { 4594 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), VT, 4595 LN0->getChain(), LN0->getBasePtr(), 4596 LN0->getPointerInfo(), 4597 LN0->getMemoryVT(), 4598 LN0->isVolatile(), 4599 LN0->isNonTemporal(), 4600 LN0->getAlignment()); 4601 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4602 Mask = Mask.zext(VT.getSizeInBits()); 4603 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 4604 ExtLoad, DAG.getConstant(Mask, VT)); 4605 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, 4606 N0.getOperand(0).getDebugLoc(), 4607 N0.getOperand(0).getValueType(), ExtLoad); 4608 CombineTo(N, And); 4609 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1)); 4610 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4611 ISD::ZERO_EXTEND); 4612 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4613 } 4614 } 4615 } 4616 4617 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 4618 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 4619 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 4620 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 4621 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4622 EVT MemVT = LN0->getMemoryVT(); 4623 if ((!LegalOperations && !LN0->isVolatile()) || 4624 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) { 4625 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 4626 LN0->getChain(), 4627 LN0->getBasePtr(), LN0->getPointerInfo(), 4628 MemVT, 4629 LN0->isVolatile(), LN0->isNonTemporal(), 4630 LN0->getAlignment()); 4631 CombineTo(N, ExtLoad); 4632 CombineTo(N0.getNode(), 4633 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(), 4634 ExtLoad), 4635 ExtLoad.getValue(1)); 4636 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4637 } 4638 } 4639 4640 if (N0.getOpcode() == ISD::SETCC) { 4641 if (!LegalOperations && VT.isVector()) { 4642 // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors. 4643 // Only do this before legalize for now. 4644 EVT N0VT = N0.getOperand(0).getValueType(); 4645 EVT EltVT = VT.getVectorElementType(); 4646 SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(), 4647 DAG.getConstant(1, EltVT)); 4648 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 4649 // We know that the # elements of the results is the same as the 4650 // # elements of the compare (and the # elements of the compare result 4651 // for that matter). Check to see that they are the same size. If so, 4652 // we know that the element size of the sext'd result matches the 4653 // element size of the compare operands. 4654 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4655 DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4656 N0.getOperand(1), 4657 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 4658 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 4659 &OneOps[0], OneOps.size())); 4660 4661 // If the desired elements are smaller or larger than the source 4662 // elements we can use a matching integer vector type and then 4663 // truncate/sign extend 4664 EVT MatchingElementType = 4665 EVT::getIntegerVT(*DAG.getContext(), 4666 N0VT.getScalarType().getSizeInBits()); 4667 EVT MatchingVectorType = 4668 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4669 N0VT.getVectorNumElements()); 4670 SDValue VsetCC = 4671 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 4672 N0.getOperand(1), 4673 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4674 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4675 DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT), 4676 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 4677 &OneOps[0], OneOps.size())); 4678 } 4679 4680 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 4681 SDValue SCC = 4682 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4683 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 4684 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4685 if (SCC.getNode()) return SCC; 4686 } 4687 4688 // (zext (shl (zext x), cst)) -> (shl (zext x), cst) 4689 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && 4690 isa<ConstantSDNode>(N0.getOperand(1)) && 4691 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && 4692 N0.hasOneUse()) { 4693 SDValue ShAmt = N0.getOperand(1); 4694 unsigned ShAmtVal = cast<ConstantSDNode>(ShAmt)->getZExtValue(); 4695 if (N0.getOpcode() == ISD::SHL) { 4696 SDValue InnerZExt = N0.getOperand(0); 4697 // If the original shl may be shifting out bits, do not perform this 4698 // transformation. 4699 unsigned KnownZeroBits = InnerZExt.getValueType().getSizeInBits() - 4700 InnerZExt.getOperand(0).getValueType().getSizeInBits(); 4701 if (ShAmtVal > KnownZeroBits) 4702 return SDValue(); 4703 } 4704 4705 DebugLoc DL = N->getDebugLoc(); 4706 4707 // Ensure that the shift amount is wide enough for the shifted value. 4708 if (VT.getSizeInBits() >= 256) 4709 ShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, ShAmt); 4710 4711 return DAG.getNode(N0.getOpcode(), DL, VT, 4712 DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)), 4713 ShAmt); 4714 } 4715 4716 return SDValue(); 4717} 4718 4719SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 4720 SDValue N0 = N->getOperand(0); 4721 EVT VT = N->getValueType(0); 4722 4723 // fold (aext c1) -> c1 4724 if (isa<ConstantSDNode>(N0)) 4725 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0); 4726 // fold (aext (aext x)) -> (aext x) 4727 // fold (aext (zext x)) -> (zext x) 4728 // fold (aext (sext x)) -> (sext x) 4729 if (N0.getOpcode() == ISD::ANY_EXTEND || 4730 N0.getOpcode() == ISD::ZERO_EXTEND || 4731 N0.getOpcode() == ISD::SIGN_EXTEND) 4732 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0)); 4733 4734 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 4735 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 4736 if (N0.getOpcode() == ISD::TRUNCATE) { 4737 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4738 if (NarrowLoad.getNode()) { 4739 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4740 if (NarrowLoad.getNode() != N0.getNode()) { 4741 CombineTo(N0.getNode(), NarrowLoad); 4742 // CombineTo deleted the truncate, if needed, but not what's under it. 4743 AddToWorkList(oye); 4744 } 4745 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4746 } 4747 } 4748 4749 // fold (aext (truncate x)) 4750 if (N0.getOpcode() == ISD::TRUNCATE) { 4751 SDValue TruncOp = N0.getOperand(0); 4752 if (TruncOp.getValueType() == VT) 4753 return TruncOp; // x iff x size == zext size. 4754 if (TruncOp.getValueType().bitsGT(VT)) 4755 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp); 4756 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp); 4757 } 4758 4759 // Fold (aext (and (trunc x), cst)) -> (and x, cst) 4760 // if the trunc is not free. 4761 if (N0.getOpcode() == ISD::AND && 4762 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 4763 N0.getOperand(1).getOpcode() == ISD::Constant && 4764 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 4765 N0.getValueType())) { 4766 SDValue X = N0.getOperand(0).getOperand(0); 4767 if (X.getValueType().bitsLT(VT)) { 4768 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X); 4769 } else if (X.getValueType().bitsGT(VT)) { 4770 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X); 4771 } 4772 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4773 Mask = Mask.zext(VT.getSizeInBits()); 4774 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4775 X, DAG.getConstant(Mask, VT)); 4776 } 4777 4778 // fold (aext (load x)) -> (aext (truncate (extload x))) 4779 // None of the supported targets knows how to perform load and any_ext 4780 // on vectors in one instruction. We only perform this transformation on 4781 // scalars. 4782 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4783 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4784 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 4785 bool DoXform = true; 4786 SmallVector<SDNode*, 4> SetCCs; 4787 if (!N0.hasOneUse()) 4788 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI); 4789 if (DoXform) { 4790 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4791 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 4792 LN0->getChain(), 4793 LN0->getBasePtr(), LN0->getPointerInfo(), 4794 N0.getValueType(), 4795 LN0->isVolatile(), LN0->isNonTemporal(), 4796 LN0->getAlignment()); 4797 CombineTo(N, ExtLoad); 4798 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4799 N0.getValueType(), ExtLoad); 4800 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4801 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4802 ISD::ANY_EXTEND); 4803 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4804 } 4805 } 4806 4807 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 4808 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 4809 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 4810 if (N0.getOpcode() == ISD::LOAD && 4811 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 4812 N0.hasOneUse()) { 4813 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4814 EVT MemVT = LN0->getMemoryVT(); 4815 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(), 4816 VT, LN0->getChain(), LN0->getBasePtr(), 4817 LN0->getPointerInfo(), MemVT, 4818 LN0->isVolatile(), LN0->isNonTemporal(), 4819 LN0->getAlignment()); 4820 CombineTo(N, ExtLoad); 4821 CombineTo(N0.getNode(), 4822 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4823 N0.getValueType(), ExtLoad), 4824 ExtLoad.getValue(1)); 4825 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4826 } 4827 4828 if (N0.getOpcode() == ISD::SETCC) { 4829 // aext(setcc) -> sext_in_reg(vsetcc) for vectors. 4830 // Only do this before legalize for now. 4831 if (VT.isVector() && !LegalOperations) { 4832 EVT N0VT = N0.getOperand(0).getValueType(); 4833 // We know that the # elements of the results is the same as the 4834 // # elements of the compare (and the # elements of the compare result 4835 // for that matter). Check to see that they are the same size. If so, 4836 // we know that the element size of the sext'd result matches the 4837 // element size of the compare operands. 4838 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 4839 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4840 N0.getOperand(1), 4841 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4842 // If the desired elements are smaller or larger than the source 4843 // elements we can use a matching integer vector type and then 4844 // truncate/sign extend 4845 else { 4846 EVT MatchingElementType = 4847 EVT::getIntegerVT(*DAG.getContext(), 4848 N0VT.getScalarType().getSizeInBits()); 4849 EVT MatchingVectorType = 4850 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4851 N0VT.getVectorNumElements()); 4852 SDValue VsetCC = 4853 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 4854 N0.getOperand(1), 4855 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4856 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); 4857 } 4858 } 4859 4860 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 4861 SDValue SCC = 4862 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4863 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 4864 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4865 if (SCC.getNode()) 4866 return SCC; 4867 } 4868 4869 return SDValue(); 4870} 4871 4872/// GetDemandedBits - See if the specified operand can be simplified with the 4873/// knowledge that only the bits specified by Mask are used. If so, return the 4874/// simpler operand, otherwise return a null SDValue. 4875SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 4876 switch (V.getOpcode()) { 4877 default: break; 4878 case ISD::Constant: { 4879 const ConstantSDNode *CV = cast<ConstantSDNode>(V.getNode()); 4880 assert(CV != 0 && "Const value should be ConstSDNode."); 4881 const APInt &CVal = CV->getAPIntValue(); 4882 APInt NewVal = CVal & Mask; 4883 if (NewVal != CVal) { 4884 return DAG.getConstant(NewVal, V.getValueType()); 4885 } 4886 break; 4887 } 4888 case ISD::OR: 4889 case ISD::XOR: 4890 // If the LHS or RHS don't contribute bits to the or, drop them. 4891 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 4892 return V.getOperand(1); 4893 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 4894 return V.getOperand(0); 4895 break; 4896 case ISD::SRL: 4897 // Only look at single-use SRLs. 4898 if (!V.getNode()->hasOneUse()) 4899 break; 4900 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 4901 // See if we can recursively simplify the LHS. 4902 unsigned Amt = RHSC->getZExtValue(); 4903 4904 // Watch out for shift count overflow though. 4905 if (Amt >= Mask.getBitWidth()) break; 4906 APInt NewMask = Mask << Amt; 4907 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 4908 if (SimplifyLHS.getNode()) 4909 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(), 4910 SimplifyLHS, V.getOperand(1)); 4911 } 4912 } 4913 return SDValue(); 4914} 4915 4916/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 4917/// bits and then truncated to a narrower type and where N is a multiple 4918/// of number of bits of the narrower type, transform it to a narrower load 4919/// from address + N / num of bits of new type. If the result is to be 4920/// extended, also fold the extension to form a extending load. 4921SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 4922 unsigned Opc = N->getOpcode(); 4923 4924 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 4925 SDValue N0 = N->getOperand(0); 4926 EVT VT = N->getValueType(0); 4927 EVT ExtVT = VT; 4928 4929 // This transformation isn't valid for vector loads. 4930 if (VT.isVector()) 4931 return SDValue(); 4932 4933 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then 4934 // extended to VT. 4935 if (Opc == ISD::SIGN_EXTEND_INREG) { 4936 ExtType = ISD::SEXTLOAD; 4937 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 4938 } else if (Opc == ISD::SRL) { 4939 // Another special-case: SRL is basically zero-extending a narrower value. 4940 ExtType = ISD::ZEXTLOAD; 4941 N0 = SDValue(N, 0); 4942 ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 4943 if (!N01) return SDValue(); 4944 ExtVT = EVT::getIntegerVT(*DAG.getContext(), 4945 VT.getSizeInBits() - N01->getZExtValue()); 4946 } 4947 if (LegalOperations && !TLI.isLoadExtLegal(ExtType, ExtVT)) 4948 return SDValue(); 4949 4950 unsigned EVTBits = ExtVT.getSizeInBits(); 4951 4952 // Do not generate loads of non-round integer types since these can 4953 // be expensive (and would be wrong if the type is not byte sized). 4954 if (!ExtVT.isRound()) 4955 return SDValue(); 4956 4957 unsigned ShAmt = 0; 4958 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 4959 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 4960 ShAmt = N01->getZExtValue(); 4961 // Is the shift amount a multiple of size of VT? 4962 if ((ShAmt & (EVTBits-1)) == 0) { 4963 N0 = N0.getOperand(0); 4964 // Is the load width a multiple of size of VT? 4965 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0) 4966 return SDValue(); 4967 } 4968 4969 // At this point, we must have a load or else we can't do the transform. 4970 if (!isa<LoadSDNode>(N0)) return SDValue(); 4971 4972 // If the shift amount is larger than the input type then we're not 4973 // accessing any of the loaded bytes. If the load was a zextload/extload 4974 // then the result of the shift+trunc is zero/undef (handled elsewhere). 4975 // If the load was a sextload then the result is a splat of the sign bit 4976 // of the extended byte. This is not worth optimizing for. 4977 if (ShAmt >= cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits()) 4978 return SDValue(); 4979 } 4980 } 4981 4982 // If the load is shifted left (and the result isn't shifted back right), 4983 // we can fold the truncate through the shift. 4984 unsigned ShLeftAmt = 0; 4985 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() && 4986 ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) { 4987 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 4988 ShLeftAmt = N01->getZExtValue(); 4989 N0 = N0.getOperand(0); 4990 } 4991 } 4992 4993 // If we haven't found a load, we can't narrow it. Don't transform one with 4994 // multiple uses, this would require adding a new load. 4995 if (!isa<LoadSDNode>(N0) || !N0.hasOneUse() || 4996 // Don't change the width of a volatile load. 4997 cast<LoadSDNode>(N0)->isVolatile()) 4998 return SDValue(); 4999 5000 // Verify that we are actually reducing a load width here. 5001 if (cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() < EVTBits) 5002 return SDValue(); 5003 5004 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5005 EVT PtrType = N0.getOperand(1).getValueType(); 5006 5007 // For big endian targets, we need to adjust the offset to the pointer to 5008 // load the correct bytes. 5009 if (TLI.isBigEndian()) { 5010 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 5011 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits(); 5012 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 5013 } 5014 5015 uint64_t PtrOff = ShAmt / 8; 5016 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 5017 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), 5018 PtrType, LN0->getBasePtr(), 5019 DAG.getConstant(PtrOff, PtrType)); 5020 AddToWorkList(NewPtr.getNode()); 5021 5022 SDValue Load; 5023 if (ExtType == ISD::NON_EXTLOAD) 5024 Load = DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr, 5025 LN0->getPointerInfo().getWithOffset(PtrOff), 5026 LN0->isVolatile(), LN0->isNonTemporal(), 5027 LN0->isInvariant(), NewAlign); 5028 else 5029 Load = DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(),NewPtr, 5030 LN0->getPointerInfo().getWithOffset(PtrOff), 5031 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 5032 NewAlign); 5033 5034 // Replace the old load's chain with the new load's chain. 5035 WorkListRemover DeadNodes(*this); 5036 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), 5037 &DeadNodes); 5038 5039 // Shift the result left, if we've swallowed a left shift. 5040 SDValue Result = Load; 5041 if (ShLeftAmt != 0) { 5042 EVT ShImmTy = getShiftAmountTy(Result.getValueType()); 5043 if (!isUIntN(ShImmTy.getSizeInBits(), ShLeftAmt)) 5044 ShImmTy = VT; 5045 Result = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, 5046 Result, DAG.getConstant(ShLeftAmt, ShImmTy)); 5047 } 5048 5049 // Return the new loaded value. 5050 return Result; 5051} 5052 5053SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 5054 SDValue N0 = N->getOperand(0); 5055 SDValue N1 = N->getOperand(1); 5056 EVT VT = N->getValueType(0); 5057 EVT EVT = cast<VTSDNode>(N1)->getVT(); 5058 unsigned VTBits = VT.getScalarType().getSizeInBits(); 5059 unsigned EVTBits = EVT.getScalarType().getSizeInBits(); 5060 5061 // fold (sext_in_reg c1) -> c1 5062 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 5063 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1); 5064 5065 // If the input is already sign extended, just drop the extension. 5066 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1) 5067 return N0; 5068 5069 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 5070 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 5071 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 5072 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 5073 N0.getOperand(0), N1); 5074 } 5075 5076 // fold (sext_in_reg (sext x)) -> (sext x) 5077 // fold (sext_in_reg (aext x)) -> (sext x) 5078 // if x is small enough. 5079 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 5080 SDValue N00 = N0.getOperand(0); 5081 if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits && 5082 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT))) 5083 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1); 5084 } 5085 5086 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 5087 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 5088 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT); 5089 5090 // fold operands of sext_in_reg based on knowledge that the top bits are not 5091 // demanded. 5092 if (SimplifyDemandedBits(SDValue(N, 0))) 5093 return SDValue(N, 0); 5094 5095 // fold (sext_in_reg (load x)) -> (smaller sextload x) 5096 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 5097 SDValue NarrowLoad = ReduceLoadWidth(N); 5098 if (NarrowLoad.getNode()) 5099 return NarrowLoad; 5100 5101 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24) 5102 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible. 5103 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 5104 if (N0.getOpcode() == ISD::SRL) { 5105 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 5106 if (ShAmt->getZExtValue()+EVTBits <= VTBits) { 5107 // We can turn this into an SRA iff the input to the SRL is already sign 5108 // extended enough. 5109 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 5110 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits) 5111 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, 5112 N0.getOperand(0), N0.getOperand(1)); 5113 } 5114 } 5115 5116 // fold (sext_inreg (extload x)) -> (sextload x) 5117 if (ISD::isEXTLoad(N0.getNode()) && 5118 ISD::isUNINDEXEDLoad(N0.getNode()) && 5119 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 5120 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 5121 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 5122 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5123 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 5124 LN0->getChain(), 5125 LN0->getBasePtr(), LN0->getPointerInfo(), 5126 EVT, 5127 LN0->isVolatile(), LN0->isNonTemporal(), 5128 LN0->getAlignment()); 5129 CombineTo(N, ExtLoad); 5130 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 5131 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5132 } 5133 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 5134 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 5135 N0.hasOneUse() && 5136 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 5137 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 5138 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 5139 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5140 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 5141 LN0->getChain(), 5142 LN0->getBasePtr(), LN0->getPointerInfo(), 5143 EVT, 5144 LN0->isVolatile(), LN0->isNonTemporal(), 5145 LN0->getAlignment()); 5146 CombineTo(N, ExtLoad); 5147 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 5148 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5149 } 5150 5151 // Form (sext_inreg (bswap >> 16)) or (sext_inreg (rotl (bswap) 16)) 5152 if (EVTBits <= 16 && N0.getOpcode() == ISD::OR) { 5153 SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0), 5154 N0.getOperand(1), false); 5155 if (BSwap.getNode() != 0) 5156 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 5157 BSwap, N1); 5158 } 5159 5160 return SDValue(); 5161} 5162 5163SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 5164 SDValue N0 = N->getOperand(0); 5165 EVT VT = N->getValueType(0); 5166 bool isLE = TLI.isLittleEndian(); 5167 5168 // noop truncate 5169 if (N0.getValueType() == N->getValueType(0)) 5170 return N0; 5171 // fold (truncate c1) -> c1 5172 if (isa<ConstantSDNode>(N0)) 5173 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0); 5174 // fold (truncate (truncate x)) -> (truncate x) 5175 if (N0.getOpcode() == ISD::TRUNCATE) 5176 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 5177 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 5178 if (N0.getOpcode() == ISD::ZERO_EXTEND || 5179 N0.getOpcode() == ISD::SIGN_EXTEND || 5180 N0.getOpcode() == ISD::ANY_EXTEND) { 5181 if (N0.getOperand(0).getValueType().bitsLT(VT)) 5182 // if the source is smaller than the dest, we still need an extend 5183 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 5184 N0.getOperand(0)); 5185 else if (N0.getOperand(0).getValueType().bitsGT(VT)) 5186 // if the source is larger than the dest, than we just need the truncate 5187 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 5188 else 5189 // if the source and dest are the same type, we can drop both the extend 5190 // and the truncate. 5191 return N0.getOperand(0); 5192 } 5193 5194 // Fold extract-and-trunc into a narrow extract. For example: 5195 // i64 x = EXTRACT_VECTOR_ELT(v2i64 val, i32 1) 5196 // i32 y = TRUNCATE(i64 x) 5197 // -- becomes -- 5198 // v16i8 b = BITCAST (v2i64 val) 5199 // i8 x = EXTRACT_VECTOR_ELT(v16i8 b, i32 8) 5200 // 5201 // Note: We only run this optimization after type legalization (which often 5202 // creates this pattern) and before operation legalization after which 5203 // we need to be more careful about the vector instructions that we generate. 5204 if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && 5205 LegalTypes && !LegalOperations && N0->hasOneUse()) { 5206 5207 EVT VecTy = N0.getOperand(0).getValueType(); 5208 EVT ExTy = N0.getValueType(); 5209 EVT TrTy = N->getValueType(0); 5210 5211 unsigned NumElem = VecTy.getVectorNumElements(); 5212 unsigned SizeRatio = ExTy.getSizeInBits()/TrTy.getSizeInBits(); 5213 5214 EVT NVT = EVT::getVectorVT(*DAG.getContext(), TrTy, SizeRatio * NumElem); 5215 assert(NVT.getSizeInBits() == VecTy.getSizeInBits() && "Invalid Size"); 5216 5217 SDValue EltNo = N0->getOperand(1); 5218 if (isa<ConstantSDNode>(EltNo) && isTypeLegal(NVT)) { 5219 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5220 5221 int Index = isLE ? (Elt*SizeRatio) : (Elt*SizeRatio + (SizeRatio-1)); 5222 5223 SDValue V = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 5224 NVT, N0.getOperand(0)); 5225 5226 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 5227 N->getDebugLoc(), TrTy, V, 5228 DAG.getConstant(Index, MVT::i32)); 5229 } 5230 } 5231 5232 // See if we can simplify the input to this truncate through knowledge that 5233 // only the low bits are being used. 5234 // For example "trunc (or (shl x, 8), y)" // -> trunc y 5235 // Currently we only perform this optimization on scalars because vectors 5236 // may have different active low bits. 5237 if (!VT.isVector()) { 5238 SDValue Shorter = 5239 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 5240 VT.getSizeInBits())); 5241 if (Shorter.getNode()) 5242 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter); 5243 } 5244 // fold (truncate (load x)) -> (smaller load x) 5245 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 5246 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) { 5247 SDValue Reduced = ReduceLoadWidth(N); 5248 if (Reduced.getNode()) 5249 return Reduced; 5250 } 5251 5252 // Simplify the operands using demanded-bits information. 5253 if (!VT.isVector() && 5254 SimplifyDemandedBits(SDValue(N, 0))) 5255 return SDValue(N, 0); 5256 5257 return SDValue(); 5258} 5259 5260static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 5261 SDValue Elt = N->getOperand(i); 5262 if (Elt.getOpcode() != ISD::MERGE_VALUES) 5263 return Elt.getNode(); 5264 return Elt.getOperand(Elt.getResNo()).getNode(); 5265} 5266 5267/// CombineConsecutiveLoads - build_pair (load, load) -> load 5268/// if load locations are consecutive. 5269SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) { 5270 assert(N->getOpcode() == ISD::BUILD_PAIR); 5271 5272 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0)); 5273 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1)); 5274 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse() || 5275 LD1->getPointerInfo().getAddrSpace() != 5276 LD2->getPointerInfo().getAddrSpace()) 5277 return SDValue(); 5278 EVT LD1VT = LD1->getValueType(0); 5279 5280 if (ISD::isNON_EXTLoad(LD2) && 5281 LD2->hasOneUse() && 5282 // If both are volatile this would reduce the number of volatile loads. 5283 // If one is volatile it might be ok, but play conservative and bail out. 5284 !LD1->isVolatile() && 5285 !LD2->isVolatile() && 5286 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) { 5287 unsigned Align = LD1->getAlignment(); 5288 unsigned NewAlign = TLI.getTargetData()-> 5289 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 5290 5291 if (NewAlign <= Align && 5292 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) 5293 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(), 5294 LD1->getBasePtr(), LD1->getPointerInfo(), 5295 false, false, false, Align); 5296 } 5297 5298 return SDValue(); 5299} 5300 5301SDValue DAGCombiner::visitBITCAST(SDNode *N) { 5302 SDValue N0 = N->getOperand(0); 5303 EVT VT = N->getValueType(0); 5304 5305 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 5306 // Only do this before legalize, since afterward the target may be depending 5307 // on the bitconvert. 5308 // First check to see if this is all constant. 5309 if (!LegalTypes && 5310 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 5311 VT.isVector()) { 5312 bool isSimple = true; 5313 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 5314 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 5315 N0.getOperand(i).getOpcode() != ISD::Constant && 5316 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 5317 isSimple = false; 5318 break; 5319 } 5320 5321 EVT DestEltVT = N->getValueType(0).getVectorElementType(); 5322 assert(!DestEltVT.isVector() && 5323 "Element type of vector ValueType must not be vector!"); 5324 if (isSimple) 5325 return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(), DestEltVT); 5326 } 5327 5328 // If the input is a constant, let getNode fold it. 5329 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 5330 SDValue Res = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, N0); 5331 if (Res.getNode() != N) { 5332 if (!LegalOperations || 5333 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT)) 5334 return Res; 5335 5336 // Folding it resulted in an illegal node, and it's too late to 5337 // do that. Clean up the old node and forego the transformation. 5338 // Ideally this won't happen very often, because instcombine 5339 // and the earlier dagcombine runs (where illegal nodes are 5340 // permitted) should have folded most of them already. 5341 DAG.DeleteNode(Res.getNode()); 5342 } 5343 } 5344 5345 // (conv (conv x, t1), t2) -> (conv x, t2) 5346 if (N0.getOpcode() == ISD::BITCAST) 5347 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, 5348 N0.getOperand(0)); 5349 5350 // fold (conv (load x)) -> (load (conv*)x) 5351 // If the resultant load doesn't need a higher alignment than the original! 5352 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 5353 // Do not change the width of a volatile load. 5354 !cast<LoadSDNode>(N0)->isVolatile() && 5355 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) { 5356 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5357 unsigned Align = TLI.getTargetData()-> 5358 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 5359 unsigned OrigAlign = LN0->getAlignment(); 5360 5361 if (Align <= OrigAlign) { 5362 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(), 5363 LN0->getBasePtr(), LN0->getPointerInfo(), 5364 LN0->isVolatile(), LN0->isNonTemporal(), 5365 LN0->isInvariant(), OrigAlign); 5366 AddToWorkList(N); 5367 CombineTo(N0.getNode(), 5368 DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 5369 N0.getValueType(), Load), 5370 Load.getValue(1)); 5371 return Load; 5372 } 5373 } 5374 5375 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit) 5376 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit)) 5377 // This often reduces constant pool loads. 5378 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(VT)) || 5379 (N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(VT))) && 5380 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) { 5381 SDValue NewConv = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), VT, 5382 N0.getOperand(0)); 5383 AddToWorkList(NewConv.getNode()); 5384 5385 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 5386 if (N0.getOpcode() == ISD::FNEG) 5387 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 5388 NewConv, DAG.getConstant(SignBit, VT)); 5389 assert(N0.getOpcode() == ISD::FABS); 5390 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 5391 NewConv, DAG.getConstant(~SignBit, VT)); 5392 } 5393 5394 // fold (bitconvert (fcopysign cst, x)) -> 5395 // (or (and (bitconvert x), sign), (and cst, (not sign))) 5396 // Note that we don't handle (copysign x, cst) because this can always be 5397 // folded to an fneg or fabs. 5398 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 5399 isa<ConstantFPSDNode>(N0.getOperand(0)) && 5400 VT.isInteger() && !VT.isVector()) { 5401 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 5402 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth); 5403 if (isTypeLegal(IntXVT)) { 5404 SDValue X = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 5405 IntXVT, N0.getOperand(1)); 5406 AddToWorkList(X.getNode()); 5407 5408 // If X has a different width than the result/lhs, sext it or truncate it. 5409 unsigned VTWidth = VT.getSizeInBits(); 5410 if (OrigXWidth < VTWidth) { 5411 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X); 5412 AddToWorkList(X.getNode()); 5413 } else if (OrigXWidth > VTWidth) { 5414 // To get the sign bit in the right place, we have to shift it right 5415 // before truncating. 5416 X = DAG.getNode(ISD::SRL, X.getDebugLoc(), 5417 X.getValueType(), X, 5418 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 5419 AddToWorkList(X.getNode()); 5420 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 5421 AddToWorkList(X.getNode()); 5422 } 5423 5424 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 5425 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT, 5426 X, DAG.getConstant(SignBit, VT)); 5427 AddToWorkList(X.getNode()); 5428 5429 SDValue Cst = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 5430 VT, N0.getOperand(0)); 5431 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT, 5432 Cst, DAG.getConstant(~SignBit, VT)); 5433 AddToWorkList(Cst.getNode()); 5434 5435 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst); 5436 } 5437 } 5438 5439 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 5440 if (N0.getOpcode() == ISD::BUILD_PAIR) { 5441 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT); 5442 if (CombineLD.getNode()) 5443 return CombineLD; 5444 } 5445 5446 return SDValue(); 5447} 5448 5449SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 5450 EVT VT = N->getValueType(0); 5451 return CombineConsecutiveLoads(N, VT); 5452} 5453 5454/// ConstantFoldBITCASTofBUILD_VECTOR - We know that BV is a build_vector 5455/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 5456/// destination element value type. 5457SDValue DAGCombiner:: 5458ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) { 5459 EVT SrcEltVT = BV->getValueType(0).getVectorElementType(); 5460 5461 // If this is already the right type, we're done. 5462 if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 5463 5464 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 5465 unsigned DstBitSize = DstEltVT.getSizeInBits(); 5466 5467 // If this is a conversion of N elements of one type to N elements of another 5468 // type, convert each element. This handles FP<->INT cases. 5469 if (SrcBitSize == DstBitSize) { 5470 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 5471 BV->getValueType(0).getVectorNumElements()); 5472 5473 // Due to the FP element handling below calling this routine recursively, 5474 // we can end up with a scalar-to-vector node here. 5475 if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR) 5476 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 5477 DAG.getNode(ISD::BITCAST, BV->getDebugLoc(), 5478 DstEltVT, BV->getOperand(0))); 5479 5480 SmallVector<SDValue, 8> Ops; 5481 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 5482 SDValue Op = BV->getOperand(i); 5483 // If the vector element type is not legal, the BUILD_VECTOR operands 5484 // are promoted and implicitly truncated. Make that explicit here. 5485 if (Op.getValueType() != SrcEltVT) 5486 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op); 5487 Ops.push_back(DAG.getNode(ISD::BITCAST, BV->getDebugLoc(), 5488 DstEltVT, Op)); 5489 AddToWorkList(Ops.back().getNode()); 5490 } 5491 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 5492 &Ops[0], Ops.size()); 5493 } 5494 5495 // Otherwise, we're growing or shrinking the elements. To avoid having to 5496 // handle annoying details of growing/shrinking FP values, we convert them to 5497 // int first. 5498 if (SrcEltVT.isFloatingPoint()) { 5499 // Convert the input float vector to a int vector where the elements are the 5500 // same sizes. 5501 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 5502 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits()); 5503 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode(); 5504 SrcEltVT = IntVT; 5505 } 5506 5507 // Now we know the input is an integer vector. If the output is a FP type, 5508 // convert to integer first, then to FP of the right size. 5509 if (DstEltVT.isFloatingPoint()) { 5510 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 5511 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits()); 5512 SDNode *Tmp = ConstantFoldBITCASTofBUILD_VECTOR(BV, TmpVT).getNode(); 5513 5514 // Next, convert to FP elements of the same size. 5515 return ConstantFoldBITCASTofBUILD_VECTOR(Tmp, DstEltVT); 5516 } 5517 5518 // Okay, we know the src/dst types are both integers of differing types. 5519 // Handling growing first. 5520 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 5521 if (SrcBitSize < DstBitSize) { 5522 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 5523 5524 SmallVector<SDValue, 8> Ops; 5525 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 5526 i += NumInputsPerOutput) { 5527 bool isLE = TLI.isLittleEndian(); 5528 APInt NewBits = APInt(DstBitSize, 0); 5529 bool EltIsUndef = true; 5530 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 5531 // Shift the previously computed bits over. 5532 NewBits <<= SrcBitSize; 5533 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 5534 if (Op.getOpcode() == ISD::UNDEF) continue; 5535 EltIsUndef = false; 5536 5537 NewBits |= cast<ConstantSDNode>(Op)->getAPIntValue(). 5538 zextOrTrunc(SrcBitSize).zext(DstBitSize); 5539 } 5540 5541 if (EltIsUndef) 5542 Ops.push_back(DAG.getUNDEF(DstEltVT)); 5543 else 5544 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 5545 } 5546 5547 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size()); 5548 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 5549 &Ops[0], Ops.size()); 5550 } 5551 5552 // Finally, this must be the case where we are shrinking elements: each input 5553 // turns into multiple outputs. 5554 bool isS2V = ISD::isScalarToVector(BV); 5555 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 5556 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 5557 NumOutputsPerInput*BV->getNumOperands()); 5558 SmallVector<SDValue, 8> Ops; 5559 5560 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 5561 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 5562 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 5563 Ops.push_back(DAG.getUNDEF(DstEltVT)); 5564 continue; 5565 } 5566 5567 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))-> 5568 getAPIntValue().zextOrTrunc(SrcBitSize); 5569 5570 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 5571 APInt ThisVal = OpVal.trunc(DstBitSize); 5572 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 5573 if (isS2V && i == 0 && j == 0 && ThisVal.zext(SrcBitSize) == OpVal) 5574 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 5575 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 5576 Ops[0]); 5577 OpVal = OpVal.lshr(DstBitSize); 5578 } 5579 5580 // For big endian targets, swap the order of the pieces of each element. 5581 if (TLI.isBigEndian()) 5582 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 5583 } 5584 5585 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 5586 &Ops[0], Ops.size()); 5587} 5588 5589SDValue DAGCombiner::visitFADD(SDNode *N) { 5590 SDValue N0 = N->getOperand(0); 5591 SDValue N1 = N->getOperand(1); 5592 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5593 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5594 EVT VT = N->getValueType(0); 5595 5596 // fold vector ops 5597 if (VT.isVector()) { 5598 SDValue FoldedVOp = SimplifyVBinOp(N); 5599 if (FoldedVOp.getNode()) return FoldedVOp; 5600 } 5601 5602 // fold (fadd c1, c2) -> (fadd c1, c2) 5603 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5604 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1); 5605 // canonicalize constant to RHS 5606 if (N0CFP && !N1CFP) 5607 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0); 5608 // fold (fadd A, 0) -> A 5609 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && 5610 N1CFP->getValueAPF().isZero()) 5611 return N0; 5612 // fold (fadd A, (fneg B)) -> (fsub A, B) 5613 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) && 5614 isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options) == 2) 5615 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, 5616 GetNegatedExpression(N1, DAG, LegalOperations)); 5617 // fold (fadd (fneg A), B) -> (fsub B, A) 5618 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) && 5619 isNegatibleForFree(N0, LegalOperations, TLI, &DAG.getTarget().Options) == 2) 5620 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1, 5621 GetNegatedExpression(N0, DAG, LegalOperations)); 5622 5623 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 5624 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && 5625 N0.getOpcode() == ISD::FADD && N0.getNode()->hasOneUse() && 5626 isa<ConstantFPSDNode>(N0.getOperand(1))) 5627 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0), 5628 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5629 N0.getOperand(1), N1)); 5630 5631 return SDValue(); 5632} 5633 5634SDValue DAGCombiner::visitFSUB(SDNode *N) { 5635 SDValue N0 = N->getOperand(0); 5636 SDValue N1 = N->getOperand(1); 5637 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5638 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5639 EVT VT = N->getValueType(0); 5640 5641 // fold vector ops 5642 if (VT.isVector()) { 5643 SDValue FoldedVOp = SimplifyVBinOp(N); 5644 if (FoldedVOp.getNode()) return FoldedVOp; 5645 } 5646 5647 // fold (fsub c1, c2) -> c1-c2 5648 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5649 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1); 5650 // fold (fsub A, 0) -> A 5651 if (DAG.getTarget().Options.UnsafeFPMath && 5652 N1CFP && N1CFP->getValueAPF().isZero()) 5653 return N0; 5654 // fold (fsub 0, B) -> -B 5655 if (DAG.getTarget().Options.UnsafeFPMath && 5656 N0CFP && N0CFP->getValueAPF().isZero()) { 5657 if (isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options)) 5658 return GetNegatedExpression(N1, DAG, LegalOperations); 5659 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 5660 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1); 5661 } 5662 // fold (fsub A, (fneg B)) -> (fadd A, B) 5663 if (isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options)) 5664 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, 5665 GetNegatedExpression(N1, DAG, LegalOperations)); 5666 5667 // If 'unsafe math' is enabled, fold 5668 // (fsub x, (fadd x, y)) -> (fneg y) & 5669 // (fsub x, (fadd y, x)) -> (fneg y) 5670 if (DAG.getTarget().Options.UnsafeFPMath) { 5671 if (N1.getOpcode() == ISD::FADD) { 5672 SDValue N10 = N1->getOperand(0); 5673 SDValue N11 = N1->getOperand(1); 5674 5675 if (N10 == N0 && isNegatibleForFree(N11, LegalOperations, TLI, 5676 &DAG.getTarget().Options)) 5677 return GetNegatedExpression(N11, DAG, LegalOperations); 5678 else if (N11 == N0 && isNegatibleForFree(N10, LegalOperations, TLI, 5679 &DAG.getTarget().Options)) 5680 return GetNegatedExpression(N10, DAG, LegalOperations); 5681 } 5682 } 5683 5684 return SDValue(); 5685} 5686 5687SDValue DAGCombiner::visitFMUL(SDNode *N) { 5688 SDValue N0 = N->getOperand(0); 5689 SDValue N1 = N->getOperand(1); 5690 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5691 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5692 EVT VT = N->getValueType(0); 5693 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 5694 5695 // fold vector ops 5696 if (VT.isVector()) { 5697 SDValue FoldedVOp = SimplifyVBinOp(N); 5698 if (FoldedVOp.getNode()) return FoldedVOp; 5699 } 5700 5701 // fold (fmul c1, c2) -> c1*c2 5702 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5703 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1); 5704 // canonicalize constant to RHS 5705 if (N0CFP && !N1CFP) 5706 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0); 5707 // fold (fmul A, 0) -> 0 5708 if (DAG.getTarget().Options.UnsafeFPMath && 5709 N1CFP && N1CFP->getValueAPF().isZero()) 5710 return N1; 5711 // fold (fmul A, 0) -> 0, vector edition. 5712 if (DAG.getTarget().Options.UnsafeFPMath && 5713 ISD::isBuildVectorAllZeros(N1.getNode())) 5714 return N1; 5715 // fold (fmul X, 2.0) -> (fadd X, X) 5716 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 5717 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0); 5718 // fold (fmul X, -1.0) -> (fneg X) 5719 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 5720 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 5721 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0); 5722 5723 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y) 5724 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI, 5725 &DAG.getTarget().Options)) { 5726 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI, 5727 &DAG.getTarget().Options)) { 5728 // Both can be negated for free, check to see if at least one is cheaper 5729 // negated. 5730 if (LHSNeg == 2 || RHSNeg == 2) 5731 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5732 GetNegatedExpression(N0, DAG, LegalOperations), 5733 GetNegatedExpression(N1, DAG, LegalOperations)); 5734 } 5735 } 5736 5737 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 5738 if (DAG.getTarget().Options.UnsafeFPMath && 5739 N1CFP && N0.getOpcode() == ISD::FMUL && 5740 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 5741 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0), 5742 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5743 N0.getOperand(1), N1)); 5744 5745 return SDValue(); 5746} 5747 5748SDValue DAGCombiner::visitFDIV(SDNode *N) { 5749 SDValue N0 = N->getOperand(0); 5750 SDValue N1 = N->getOperand(1); 5751 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5752 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5753 EVT VT = N->getValueType(0); 5754 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 5755 5756 // fold vector ops 5757 if (VT.isVector()) { 5758 SDValue FoldedVOp = SimplifyVBinOp(N); 5759 if (FoldedVOp.getNode()) return FoldedVOp; 5760 } 5761 5762 // fold (fdiv c1, c2) -> c1/c2 5763 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5764 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1); 5765 5766 // fold (fdiv X, c2) -> fmul X, 1/c2 if losing precision is acceptable. 5767 if (N1CFP && VT != MVT::ppcf128 && DAG.getTarget().Options.UnsafeFPMath) { 5768 // Compute the reciprocal 1.0 / c2. 5769 APFloat N1APF = N1CFP->getValueAPF(); 5770 APFloat Recip(N1APF.getSemantics(), 1); // 1.0 5771 APFloat::opStatus st = Recip.divide(N1APF, APFloat::rmNearestTiesToEven); 5772 // Only do the transform if the reciprocal is not too horrible (eg not NaN). 5773 if (st == APFloat::opOK || st == APFloat::opInexact) 5774 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, 5775 DAG.getConstantFP(Recip, VT)); 5776 } 5777 5778 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y) 5779 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI, 5780 &DAG.getTarget().Options)) { 5781 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI, 5782 &DAG.getTarget().Options)) { 5783 // Both can be negated for free, check to see if at least one is cheaper 5784 // negated. 5785 if (LHSNeg == 2 || RHSNeg == 2) 5786 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, 5787 GetNegatedExpression(N0, DAG, LegalOperations), 5788 GetNegatedExpression(N1, DAG, LegalOperations)); 5789 } 5790 } 5791 5792 return SDValue(); 5793} 5794 5795SDValue DAGCombiner::visitFREM(SDNode *N) { 5796 SDValue N0 = N->getOperand(0); 5797 SDValue N1 = N->getOperand(1); 5798 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5799 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5800 EVT VT = N->getValueType(0); 5801 5802 // fold (frem c1, c2) -> fmod(c1,c2) 5803 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5804 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1); 5805 5806 return SDValue(); 5807} 5808 5809SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 5810 SDValue N0 = N->getOperand(0); 5811 SDValue N1 = N->getOperand(1); 5812 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5813 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5814 EVT VT = N->getValueType(0); 5815 5816 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 5817 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1); 5818 5819 if (N1CFP) { 5820 const APFloat& V = N1CFP->getValueAPF(); 5821 // copysign(x, c1) -> fabs(x) iff ispos(c1) 5822 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 5823 if (!V.isNegative()) { 5824 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) 5825 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 5826 } else { 5827 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 5828 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, 5829 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0)); 5830 } 5831 } 5832 5833 // copysign(fabs(x), y) -> copysign(x, y) 5834 // copysign(fneg(x), y) -> copysign(x, y) 5835 // copysign(copysign(x,z), y) -> copysign(x, y) 5836 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 5837 N0.getOpcode() == ISD::FCOPYSIGN) 5838 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 5839 N0.getOperand(0), N1); 5840 5841 // copysign(x, abs(y)) -> abs(x) 5842 if (N1.getOpcode() == ISD::FABS) 5843 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 5844 5845 // copysign(x, copysign(y,z)) -> copysign(x, z) 5846 if (N1.getOpcode() == ISD::FCOPYSIGN) 5847 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 5848 N0, N1.getOperand(1)); 5849 5850 // copysign(x, fp_extend(y)) -> copysign(x, y) 5851 // copysign(x, fp_round(y)) -> copysign(x, y) 5852 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 5853 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 5854 N0, N1.getOperand(0)); 5855 5856 return SDValue(); 5857} 5858 5859SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 5860 SDValue N0 = N->getOperand(0); 5861 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 5862 EVT VT = N->getValueType(0); 5863 EVT OpVT = N0.getValueType(); 5864 5865 // fold (sint_to_fp c1) -> c1fp 5866 if (N0C && OpVT != MVT::ppcf128 && 5867 // ...but only if the target supports immediate floating-point values 5868 (!LegalOperations || 5869 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) 5870 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 5871 5872 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 5873 // but UINT_TO_FP is legal on this target, try to convert. 5874 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && 5875 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { 5876 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 5877 if (DAG.SignBitIsZero(N0)) 5878 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 5879 } 5880 5881 return SDValue(); 5882} 5883 5884SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 5885 SDValue N0 = N->getOperand(0); 5886 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 5887 EVT VT = N->getValueType(0); 5888 EVT OpVT = N0.getValueType(); 5889 5890 // fold (uint_to_fp c1) -> c1fp 5891 if (N0C && OpVT != MVT::ppcf128 && 5892 // ...but only if the target supports immediate floating-point values 5893 (!LegalOperations || 5894 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) 5895 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 5896 5897 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 5898 // but SINT_TO_FP is legal on this target, try to convert. 5899 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && 5900 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { 5901 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 5902 if (DAG.SignBitIsZero(N0)) 5903 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 5904 } 5905 5906 return SDValue(); 5907} 5908 5909SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 5910 SDValue N0 = N->getOperand(0); 5911 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5912 EVT VT = N->getValueType(0); 5913 5914 // fold (fp_to_sint c1fp) -> c1 5915 if (N0CFP) 5916 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0); 5917 5918 return SDValue(); 5919} 5920 5921SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 5922 SDValue N0 = N->getOperand(0); 5923 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5924 EVT VT = N->getValueType(0); 5925 5926 // fold (fp_to_uint c1fp) -> c1 5927 if (N0CFP && VT != MVT::ppcf128) 5928 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0); 5929 5930 return SDValue(); 5931} 5932 5933SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 5934 SDValue N0 = N->getOperand(0); 5935 SDValue N1 = N->getOperand(1); 5936 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5937 EVT VT = N->getValueType(0); 5938 5939 // fold (fp_round c1fp) -> c1fp 5940 if (N0CFP && N0.getValueType() != MVT::ppcf128) 5941 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1); 5942 5943 // fold (fp_round (fp_extend x)) -> x 5944 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 5945 return N0.getOperand(0); 5946 5947 // fold (fp_round (fp_round x)) -> (fp_round x) 5948 if (N0.getOpcode() == ISD::FP_ROUND) { 5949 // This is a value preserving truncation if both round's are. 5950 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 5951 N0.getNode()->getConstantOperandVal(1) == 1; 5952 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0), 5953 DAG.getIntPtrConstant(IsTrunc)); 5954 } 5955 5956 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 5957 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { 5958 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT, 5959 N0.getOperand(0), N1); 5960 AddToWorkList(Tmp.getNode()); 5961 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 5962 Tmp, N0.getOperand(1)); 5963 } 5964 5965 return SDValue(); 5966} 5967 5968SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 5969 SDValue N0 = N->getOperand(0); 5970 EVT VT = N->getValueType(0); 5971 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 5972 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5973 5974 // fold (fp_round_inreg c1fp) -> c1fp 5975 if (N0CFP && isTypeLegal(EVT)) { 5976 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT); 5977 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round); 5978 } 5979 5980 return SDValue(); 5981} 5982 5983SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 5984 SDValue N0 = N->getOperand(0); 5985 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5986 EVT VT = N->getValueType(0); 5987 5988 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 5989 if (N->hasOneUse() && 5990 N->use_begin()->getOpcode() == ISD::FP_ROUND) 5991 return SDValue(); 5992 5993 // fold (fp_extend c1fp) -> c1fp 5994 if (N0CFP && VT != MVT::ppcf128) 5995 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0); 5996 5997 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 5998 // value of X. 5999 if (N0.getOpcode() == ISD::FP_ROUND 6000 && N0.getNode()->getConstantOperandVal(1) == 1) { 6001 SDValue In = N0.getOperand(0); 6002 if (In.getValueType() == VT) return In; 6003 if (VT.bitsLT(In.getValueType())) 6004 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, 6005 In, N0.getOperand(1)); 6006 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In); 6007 } 6008 6009 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 6010 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 6011 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 6012 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 6013 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 6014 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 6015 LN0->getChain(), 6016 LN0->getBasePtr(), LN0->getPointerInfo(), 6017 N0.getValueType(), 6018 LN0->isVolatile(), LN0->isNonTemporal(), 6019 LN0->getAlignment()); 6020 CombineTo(N, ExtLoad); 6021 CombineTo(N0.getNode(), 6022 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), 6023 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)), 6024 ExtLoad.getValue(1)); 6025 return SDValue(N, 0); // Return N so it doesn't get rechecked! 6026 } 6027 6028 return SDValue(); 6029} 6030 6031SDValue DAGCombiner::visitFNEG(SDNode *N) { 6032 SDValue N0 = N->getOperand(0); 6033 EVT VT = N->getValueType(0); 6034 6035 if (isNegatibleForFree(N0, LegalOperations, DAG.getTargetLoweringInfo(), 6036 &DAG.getTarget().Options)) 6037 return GetNegatedExpression(N0, DAG, LegalOperations); 6038 6039 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 6040 // constant pool values. 6041 if (!TLI.isFNegFree(VT) && N0.getOpcode() == ISD::BITCAST && 6042 !VT.isVector() && 6043 N0.getNode()->hasOneUse() && 6044 N0.getOperand(0).getValueType().isInteger()) { 6045 SDValue Int = N0.getOperand(0); 6046 EVT IntVT = Int.getValueType(); 6047 if (IntVT.isInteger() && !IntVT.isVector()) { 6048 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int, 6049 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 6050 AddToWorkList(Int.getNode()); 6051 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 6052 VT, Int); 6053 } 6054 } 6055 6056 return SDValue(); 6057} 6058 6059SDValue DAGCombiner::visitFABS(SDNode *N) { 6060 SDValue N0 = N->getOperand(0); 6061 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6062 EVT VT = N->getValueType(0); 6063 6064 // fold (fabs c1) -> fabs(c1) 6065 if (N0CFP && VT != MVT::ppcf128) 6066 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 6067 // fold (fabs (fabs x)) -> (fabs x) 6068 if (N0.getOpcode() == ISD::FABS) 6069 return N->getOperand(0); 6070 // fold (fabs (fneg x)) -> (fabs x) 6071 // fold (fabs (fcopysign x, y)) -> (fabs x) 6072 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 6073 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0)); 6074 6075 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 6076 // constant pool values. 6077 if (!TLI.isFAbsFree(VT) && 6078 N0.getOpcode() == ISD::BITCAST && N0.getNode()->hasOneUse() && 6079 N0.getOperand(0).getValueType().isInteger() && 6080 !N0.getOperand(0).getValueType().isVector()) { 6081 SDValue Int = N0.getOperand(0); 6082 EVT IntVT = Int.getValueType(); 6083 if (IntVT.isInteger() && !IntVT.isVector()) { 6084 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int, 6085 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 6086 AddToWorkList(Int.getNode()); 6087 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 6088 N->getValueType(0), Int); 6089 } 6090 } 6091 6092 return SDValue(); 6093} 6094 6095SDValue DAGCombiner::visitBRCOND(SDNode *N) { 6096 SDValue Chain = N->getOperand(0); 6097 SDValue N1 = N->getOperand(1); 6098 SDValue N2 = N->getOperand(2); 6099 6100 // If N is a constant we could fold this into a fallthrough or unconditional 6101 // branch. However that doesn't happen very often in normal code, because 6102 // Instcombine/SimplifyCFG should have handled the available opportunities. 6103 // If we did this folding here, it would be necessary to update the 6104 // MachineBasicBlock CFG, which is awkward. 6105 6106 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 6107 // on the target. 6108 if (N1.getOpcode() == ISD::SETCC && 6109 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) { 6110 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 6111 Chain, N1.getOperand(2), 6112 N1.getOperand(0), N1.getOperand(1), N2); 6113 } 6114 6115 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) || 6116 ((N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) && 6117 (N1.getOperand(0).hasOneUse() && 6118 N1.getOperand(0).getOpcode() == ISD::SRL))) { 6119 SDNode *Trunc = 0; 6120 if (N1.getOpcode() == ISD::TRUNCATE) { 6121 // Look pass the truncate. 6122 Trunc = N1.getNode(); 6123 N1 = N1.getOperand(0); 6124 } 6125 6126 // Match this pattern so that we can generate simpler code: 6127 // 6128 // %a = ... 6129 // %b = and i32 %a, 2 6130 // %c = srl i32 %b, 1 6131 // brcond i32 %c ... 6132 // 6133 // into 6134 // 6135 // %a = ... 6136 // %b = and i32 %a, 2 6137 // %c = setcc eq %b, 0 6138 // brcond %c ... 6139 // 6140 // This applies only when the AND constant value has one bit set and the 6141 // SRL constant is equal to the log2 of the AND constant. The back-end is 6142 // smart enough to convert the result into a TEST/JMP sequence. 6143 SDValue Op0 = N1.getOperand(0); 6144 SDValue Op1 = N1.getOperand(1); 6145 6146 if (Op0.getOpcode() == ISD::AND && 6147 Op1.getOpcode() == ISD::Constant) { 6148 SDValue AndOp1 = Op0.getOperand(1); 6149 6150 if (AndOp1.getOpcode() == ISD::Constant) { 6151 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue(); 6152 6153 if (AndConst.isPowerOf2() && 6154 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) { 6155 SDValue SetCC = 6156 DAG.getSetCC(N->getDebugLoc(), 6157 TLI.getSetCCResultType(Op0.getValueType()), 6158 Op0, DAG.getConstant(0, Op0.getValueType()), 6159 ISD::SETNE); 6160 6161 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 6162 MVT::Other, Chain, SetCC, N2); 6163 // Don't add the new BRCond into the worklist or else SimplifySelectCC 6164 // will convert it back to (X & C1) >> C2. 6165 CombineTo(N, NewBRCond, false); 6166 // Truncate is dead. 6167 if (Trunc) { 6168 removeFromWorkList(Trunc); 6169 DAG.DeleteNode(Trunc); 6170 } 6171 // Replace the uses of SRL with SETCC 6172 WorkListRemover DeadNodes(*this); 6173 DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes); 6174 removeFromWorkList(N1.getNode()); 6175 DAG.DeleteNode(N1.getNode()); 6176 return SDValue(N, 0); // Return N so it doesn't get rechecked! 6177 } 6178 } 6179 } 6180 6181 if (Trunc) 6182 // Restore N1 if the above transformation doesn't match. 6183 N1 = N->getOperand(1); 6184 } 6185 6186 // Transform br(xor(x, y)) -> br(x != y) 6187 // Transform br(xor(xor(x,y), 1)) -> br (x == y) 6188 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) { 6189 SDNode *TheXor = N1.getNode(); 6190 SDValue Op0 = TheXor->getOperand(0); 6191 SDValue Op1 = TheXor->getOperand(1); 6192 if (Op0.getOpcode() == Op1.getOpcode()) { 6193 // Avoid missing important xor optimizations. 6194 SDValue Tmp = visitXOR(TheXor); 6195 if (Tmp.getNode() && Tmp.getNode() != TheXor) { 6196 DEBUG(dbgs() << "\nReplacing.8 "; 6197 TheXor->dump(&DAG); 6198 dbgs() << "\nWith: "; 6199 Tmp.getNode()->dump(&DAG); 6200 dbgs() << '\n'); 6201 WorkListRemover DeadNodes(*this); 6202 DAG.ReplaceAllUsesOfValueWith(N1, Tmp, &DeadNodes); 6203 removeFromWorkList(TheXor); 6204 DAG.DeleteNode(TheXor); 6205 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 6206 MVT::Other, Chain, Tmp, N2); 6207 } 6208 } 6209 6210 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) { 6211 bool Equal = false; 6212 if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0)) 6213 if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() && 6214 Op0.getOpcode() == ISD::XOR) { 6215 TheXor = Op0.getNode(); 6216 Equal = true; 6217 } 6218 6219 EVT SetCCVT = N1.getValueType(); 6220 if (LegalTypes) 6221 SetCCVT = TLI.getSetCCResultType(SetCCVT); 6222 SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(), 6223 SetCCVT, 6224 Op0, Op1, 6225 Equal ? ISD::SETEQ : ISD::SETNE); 6226 // Replace the uses of XOR with SETCC 6227 WorkListRemover DeadNodes(*this); 6228 DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes); 6229 removeFromWorkList(N1.getNode()); 6230 DAG.DeleteNode(N1.getNode()); 6231 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 6232 MVT::Other, Chain, SetCC, N2); 6233 } 6234 } 6235 6236 return SDValue(); 6237} 6238 6239// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 6240// 6241SDValue DAGCombiner::visitBR_CC(SDNode *N) { 6242 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 6243 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 6244 6245 // If N is a constant we could fold this into a fallthrough or unconditional 6246 // branch. However that doesn't happen very often in normal code, because 6247 // Instcombine/SimplifyCFG should have handled the available opportunities. 6248 // If we did this folding here, it would be necessary to update the 6249 // MachineBasicBlock CFG, which is awkward. 6250 6251 // Use SimplifySetCC to simplify SETCC's. 6252 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()), 6253 CondLHS, CondRHS, CC->get(), N->getDebugLoc(), 6254 false); 6255 if (Simp.getNode()) AddToWorkList(Simp.getNode()); 6256 6257 // fold to a simpler setcc 6258 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) 6259 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 6260 N->getOperand(0), Simp.getOperand(2), 6261 Simp.getOperand(0), Simp.getOperand(1), 6262 N->getOperand(4)); 6263 6264 return SDValue(); 6265} 6266 6267/// canFoldInAddressingMode - Return true if 'Use' is a load or a store that 6268/// uses N as its base pointer and that N may be folded in the load / store 6269/// addressing mode. 6270static bool canFoldInAddressingMode(SDNode *N, SDNode *Use, 6271 SelectionDAG &DAG, 6272 const TargetLowering &TLI) { 6273 EVT VT; 6274 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Use)) { 6275 if (LD->isIndexed() || LD->getBasePtr().getNode() != N) 6276 return false; 6277 VT = Use->getValueType(0); 6278 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(Use)) { 6279 if (ST->isIndexed() || ST->getBasePtr().getNode() != N) 6280 return false; 6281 VT = ST->getValue().getValueType(); 6282 } else 6283 return false; 6284 6285 TargetLowering::AddrMode AM; 6286 if (N->getOpcode() == ISD::ADD) { 6287 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1)); 6288 if (Offset) 6289 // [reg +/- imm] 6290 AM.BaseOffs = Offset->getSExtValue(); 6291 else 6292 // [reg +/- reg] 6293 AM.Scale = 1; 6294 } else if (N->getOpcode() == ISD::SUB) { 6295 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1)); 6296 if (Offset) 6297 // [reg +/- imm] 6298 AM.BaseOffs = -Offset->getSExtValue(); 6299 else 6300 // [reg +/- reg] 6301 AM.Scale = 1; 6302 } else 6303 return false; 6304 6305 return TLI.isLegalAddressingMode(AM, VT.getTypeForEVT(*DAG.getContext())); 6306} 6307 6308/// CombineToPreIndexedLoadStore - Try turning a load / store into a 6309/// pre-indexed load / store when the base pointer is an add or subtract 6310/// and it has other uses besides the load / store. After the 6311/// transformation, the new indexed load / store has effectively folded 6312/// the add / subtract in and all of its other uses are redirected to the 6313/// new load / store. 6314bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 6315 if (Level < AfterLegalizeDAG) 6316 return false; 6317 6318 bool isLoad = true; 6319 SDValue Ptr; 6320 EVT VT; 6321 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 6322 if (LD->isIndexed()) 6323 return false; 6324 VT = LD->getMemoryVT(); 6325 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 6326 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 6327 return false; 6328 Ptr = LD->getBasePtr(); 6329 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 6330 if (ST->isIndexed()) 6331 return false; 6332 VT = ST->getMemoryVT(); 6333 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 6334 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 6335 return false; 6336 Ptr = ST->getBasePtr(); 6337 isLoad = false; 6338 } else { 6339 return false; 6340 } 6341 6342 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 6343 // out. There is no reason to make this a preinc/predec. 6344 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 6345 Ptr.getNode()->hasOneUse()) 6346 return false; 6347 6348 // Ask the target to do addressing mode selection. 6349 SDValue BasePtr; 6350 SDValue Offset; 6351 ISD::MemIndexedMode AM = ISD::UNINDEXED; 6352 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 6353 return false; 6354 // Don't create a indexed load / store with zero offset. 6355 if (isa<ConstantSDNode>(Offset) && 6356 cast<ConstantSDNode>(Offset)->isNullValue()) 6357 return false; 6358 6359 // Try turning it into a pre-indexed load / store except when: 6360 // 1) The new base ptr is a frame index. 6361 // 2) If N is a store and the new base ptr is either the same as or is a 6362 // predecessor of the value being stored. 6363 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 6364 // that would create a cycle. 6365 // 4) All uses are load / store ops that use it as old base ptr. 6366 6367 // Check #1. Preinc'ing a frame index would require copying the stack pointer 6368 // (plus the implicit offset) to a register to preinc anyway. 6369 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 6370 return false; 6371 6372 // Check #2. 6373 if (!isLoad) { 6374 SDValue Val = cast<StoreSDNode>(N)->getValue(); 6375 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode())) 6376 return false; 6377 } 6378 6379 // Now check for #3 and #4. 6380 bool RealUse = false; 6381 6382 // Caches for hasPredecessorHelper 6383 SmallPtrSet<const SDNode *, 32> Visited; 6384 SmallVector<const SDNode *, 16> Worklist; 6385 6386 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 6387 E = Ptr.getNode()->use_end(); I != E; ++I) { 6388 SDNode *Use = *I; 6389 if (Use == N) 6390 continue; 6391 if (N->hasPredecessorHelper(Use, Visited, Worklist)) 6392 return false; 6393 6394 // If Ptr may be folded in addressing mode of other use, then it's 6395 // not profitable to do this transformation. 6396 if (!canFoldInAddressingMode(Ptr.getNode(), Use, DAG, TLI)) 6397 RealUse = true; 6398 } 6399 6400 if (!RealUse) 6401 return false; 6402 6403 SDValue Result; 6404 if (isLoad) 6405 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 6406 BasePtr, Offset, AM); 6407 else 6408 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 6409 BasePtr, Offset, AM); 6410 ++PreIndexedNodes; 6411 ++NodesCombined; 6412 DEBUG(dbgs() << "\nReplacing.4 "; 6413 N->dump(&DAG); 6414 dbgs() << "\nWith: "; 6415 Result.getNode()->dump(&DAG); 6416 dbgs() << '\n'); 6417 WorkListRemover DeadNodes(*this); 6418 if (isLoad) { 6419 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 6420 &DeadNodes); 6421 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 6422 &DeadNodes); 6423 } else { 6424 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 6425 &DeadNodes); 6426 } 6427 6428 // Finally, since the node is now dead, remove it from the graph. 6429 DAG.DeleteNode(N); 6430 6431 // Replace the uses of Ptr with uses of the updated base value. 6432 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 6433 &DeadNodes); 6434 removeFromWorkList(Ptr.getNode()); 6435 DAG.DeleteNode(Ptr.getNode()); 6436 6437 return true; 6438} 6439 6440/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 6441/// add / sub of the base pointer node into a post-indexed load / store. 6442/// The transformation folded the add / subtract into the new indexed 6443/// load / store effectively and all of its uses are redirected to the 6444/// new load / store. 6445bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 6446 if (Level < AfterLegalizeDAG) 6447 return false; 6448 6449 bool isLoad = true; 6450 SDValue Ptr; 6451 EVT VT; 6452 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 6453 if (LD->isIndexed()) 6454 return false; 6455 VT = LD->getMemoryVT(); 6456 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 6457 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 6458 return false; 6459 Ptr = LD->getBasePtr(); 6460 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 6461 if (ST->isIndexed()) 6462 return false; 6463 VT = ST->getMemoryVT(); 6464 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 6465 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 6466 return false; 6467 Ptr = ST->getBasePtr(); 6468 isLoad = false; 6469 } else { 6470 return false; 6471 } 6472 6473 if (Ptr.getNode()->hasOneUse()) 6474 return false; 6475 6476 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 6477 E = Ptr.getNode()->use_end(); I != E; ++I) { 6478 SDNode *Op = *I; 6479 if (Op == N || 6480 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 6481 continue; 6482 6483 SDValue BasePtr; 6484 SDValue Offset; 6485 ISD::MemIndexedMode AM = ISD::UNINDEXED; 6486 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 6487 // Don't create a indexed load / store with zero offset. 6488 if (isa<ConstantSDNode>(Offset) && 6489 cast<ConstantSDNode>(Offset)->isNullValue()) 6490 continue; 6491 6492 // Try turning it into a post-indexed load / store except when 6493 // 1) All uses are load / store ops that use it as base ptr (and 6494 // it may be folded as addressing mmode). 6495 // 2) Op must be independent of N, i.e. Op is neither a predecessor 6496 // nor a successor of N. Otherwise, if Op is folded that would 6497 // create a cycle. 6498 6499 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 6500 continue; 6501 6502 // Check for #1. 6503 bool TryNext = false; 6504 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), 6505 EE = BasePtr.getNode()->use_end(); II != EE; ++II) { 6506 SDNode *Use = *II; 6507 if (Use == Ptr.getNode()) 6508 continue; 6509 6510 // If all the uses are load / store addresses, then don't do the 6511 // transformation. 6512 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 6513 bool RealUse = false; 6514 for (SDNode::use_iterator III = Use->use_begin(), 6515 EEE = Use->use_end(); III != EEE; ++III) { 6516 SDNode *UseUse = *III; 6517 if (!canFoldInAddressingMode(Use, UseUse, DAG, TLI)) 6518 RealUse = true; 6519 } 6520 6521 if (!RealUse) { 6522 TryNext = true; 6523 break; 6524 } 6525 } 6526 } 6527 6528 if (TryNext) 6529 continue; 6530 6531 // Check for #2 6532 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 6533 SDValue Result = isLoad 6534 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 6535 BasePtr, Offset, AM) 6536 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 6537 BasePtr, Offset, AM); 6538 ++PostIndexedNodes; 6539 ++NodesCombined; 6540 DEBUG(dbgs() << "\nReplacing.5 "; 6541 N->dump(&DAG); 6542 dbgs() << "\nWith: "; 6543 Result.getNode()->dump(&DAG); 6544 dbgs() << '\n'); 6545 WorkListRemover DeadNodes(*this); 6546 if (isLoad) { 6547 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 6548 &DeadNodes); 6549 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 6550 &DeadNodes); 6551 } else { 6552 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 6553 &DeadNodes); 6554 } 6555 6556 // Finally, since the node is now dead, remove it from the graph. 6557 DAG.DeleteNode(N); 6558 6559 // Replace the uses of Use with uses of the updated base value. 6560 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 6561 Result.getValue(isLoad ? 1 : 0), 6562 &DeadNodes); 6563 removeFromWorkList(Op); 6564 DAG.DeleteNode(Op); 6565 return true; 6566 } 6567 } 6568 } 6569 6570 return false; 6571} 6572 6573SDValue DAGCombiner::visitLOAD(SDNode *N) { 6574 LoadSDNode *LD = cast<LoadSDNode>(N); 6575 SDValue Chain = LD->getChain(); 6576 SDValue Ptr = LD->getBasePtr(); 6577 6578 // If load is not volatile and there are no uses of the loaded value (and 6579 // the updated indexed value in case of indexed loads), change uses of the 6580 // chain value into uses of the chain input (i.e. delete the dead load). 6581 if (!LD->isVolatile()) { 6582 if (N->getValueType(1) == MVT::Other) { 6583 // Unindexed loads. 6584 if (!N->hasAnyUseOfValue(0)) { 6585 // It's not safe to use the two value CombineTo variant here. e.g. 6586 // v1, chain2 = load chain1, loc 6587 // v2, chain3 = load chain2, loc 6588 // v3 = add v2, c 6589 // Now we replace use of chain2 with chain1. This makes the second load 6590 // isomorphic to the one we are deleting, and thus makes this load live. 6591 DEBUG(dbgs() << "\nReplacing.6 "; 6592 N->dump(&DAG); 6593 dbgs() << "\nWith chain: "; 6594 Chain.getNode()->dump(&DAG); 6595 dbgs() << "\n"); 6596 WorkListRemover DeadNodes(*this); 6597 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes); 6598 6599 if (N->use_empty()) { 6600 removeFromWorkList(N); 6601 DAG.DeleteNode(N); 6602 } 6603 6604 return SDValue(N, 0); // Return N so it doesn't get rechecked! 6605 } 6606 } else { 6607 // Indexed loads. 6608 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 6609 if (!N->hasAnyUseOfValue(0) && !N->hasAnyUseOfValue(1)) { 6610 SDValue Undef = DAG.getUNDEF(N->getValueType(0)); 6611 DEBUG(dbgs() << "\nReplacing.7 "; 6612 N->dump(&DAG); 6613 dbgs() << "\nWith: "; 6614 Undef.getNode()->dump(&DAG); 6615 dbgs() << " and 2 other values\n"); 6616 WorkListRemover DeadNodes(*this); 6617 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes); 6618 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 6619 DAG.getUNDEF(N->getValueType(1)), 6620 &DeadNodes); 6621 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes); 6622 removeFromWorkList(N); 6623 DAG.DeleteNode(N); 6624 return SDValue(N, 0); // Return N so it doesn't get rechecked! 6625 } 6626 } 6627 } 6628 6629 // If this load is directly stored, replace the load value with the stored 6630 // value. 6631 // TODO: Handle store large -> read small portion. 6632 // TODO: Handle TRUNCSTORE/LOADEXT 6633 if (ISD::isNormalLoad(N) && !LD->isVolatile()) { 6634 if (ISD::isNON_TRUNCStore(Chain.getNode())) { 6635 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 6636 if (PrevST->getBasePtr() == Ptr && 6637 PrevST->getValue().getValueType() == N->getValueType(0)) 6638 return CombineTo(N, Chain.getOperand(1), Chain); 6639 } 6640 } 6641 6642 // Try to infer better alignment information than the load already has. 6643 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) { 6644 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 6645 if (Align > LD->getAlignment()) 6646 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(), 6647 LD->getValueType(0), 6648 Chain, Ptr, LD->getPointerInfo(), 6649 LD->getMemoryVT(), 6650 LD->isVolatile(), LD->isNonTemporal(), Align); 6651 } 6652 } 6653 6654 if (CombinerAA) { 6655 // Walk up chain skipping non-aliasing memory nodes. 6656 SDValue BetterChain = FindBetterChain(N, Chain); 6657 6658 // If there is a better chain. 6659 if (Chain != BetterChain) { 6660 SDValue ReplLoad; 6661 6662 // Replace the chain to void dependency. 6663 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 6664 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(), 6665 BetterChain, Ptr, LD->getPointerInfo(), 6666 LD->isVolatile(), LD->isNonTemporal(), 6667 LD->isInvariant(), LD->getAlignment()); 6668 } else { 6669 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(), 6670 LD->getValueType(0), 6671 BetterChain, Ptr, LD->getPointerInfo(), 6672 LD->getMemoryVT(), 6673 LD->isVolatile(), 6674 LD->isNonTemporal(), 6675 LD->getAlignment()); 6676 } 6677 6678 // Create token factor to keep old chain connected. 6679 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 6680 MVT::Other, Chain, ReplLoad.getValue(1)); 6681 6682 // Make sure the new and old chains are cleaned up. 6683 AddToWorkList(Token.getNode()); 6684 6685 // Replace uses with load result and token factor. Don't add users 6686 // to work list. 6687 return CombineTo(N, ReplLoad.getValue(0), Token, false); 6688 } 6689 } 6690 6691 // Try transforming N to an indexed load. 6692 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 6693 return SDValue(N, 0); 6694 6695 return SDValue(); 6696} 6697 6698/// CheckForMaskedLoad - Check to see if V is (and load (ptr), imm), where the 6699/// load is having specific bytes cleared out. If so, return the byte size 6700/// being masked out and the shift amount. 6701static std::pair<unsigned, unsigned> 6702CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) { 6703 std::pair<unsigned, unsigned> Result(0, 0); 6704 6705 // Check for the structure we're looking for. 6706 if (V->getOpcode() != ISD::AND || 6707 !isa<ConstantSDNode>(V->getOperand(1)) || 6708 !ISD::isNormalLoad(V->getOperand(0).getNode())) 6709 return Result; 6710 6711 // Check the chain and pointer. 6712 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0)); 6713 if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer. 6714 6715 // The store should be chained directly to the load or be an operand of a 6716 // tokenfactor. 6717 if (LD == Chain.getNode()) 6718 ; // ok. 6719 else if (Chain->getOpcode() != ISD::TokenFactor) 6720 return Result; // Fail. 6721 else { 6722 bool isOk = false; 6723 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i) 6724 if (Chain->getOperand(i).getNode() == LD) { 6725 isOk = true; 6726 break; 6727 } 6728 if (!isOk) return Result; 6729 } 6730 6731 // This only handles simple types. 6732 if (V.getValueType() != MVT::i16 && 6733 V.getValueType() != MVT::i32 && 6734 V.getValueType() != MVT::i64) 6735 return Result; 6736 6737 // Check the constant mask. Invert it so that the bits being masked out are 6738 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits 6739 // follow the sign bit for uniformity. 6740 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue(); 6741 unsigned NotMaskLZ = CountLeadingZeros_64(NotMask); 6742 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte. 6743 unsigned NotMaskTZ = CountTrailingZeros_64(NotMask); 6744 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte. 6745 if (NotMaskLZ == 64) return Result; // All zero mask. 6746 6747 // See if we have a continuous run of bits. If so, we have 0*1+0* 6748 if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64) 6749 return Result; 6750 6751 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64. 6752 if (V.getValueType() != MVT::i64 && NotMaskLZ) 6753 NotMaskLZ -= 64-V.getValueSizeInBits(); 6754 6755 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8; 6756 switch (MaskedBytes) { 6757 case 1: 6758 case 2: 6759 case 4: break; 6760 default: return Result; // All one mask, or 5-byte mask. 6761 } 6762 6763 // Verify that the first bit starts at a multiple of mask so that the access 6764 // is aligned the same as the access width. 6765 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result; 6766 6767 Result.first = MaskedBytes; 6768 Result.second = NotMaskTZ/8; 6769 return Result; 6770} 6771 6772 6773/// ShrinkLoadReplaceStoreWithStore - Check to see if IVal is something that 6774/// provides a value as specified by MaskInfo. If so, replace the specified 6775/// store with a narrower store of truncated IVal. 6776static SDNode * 6777ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo, 6778 SDValue IVal, StoreSDNode *St, 6779 DAGCombiner *DC) { 6780 unsigned NumBytes = MaskInfo.first; 6781 unsigned ByteShift = MaskInfo.second; 6782 SelectionDAG &DAG = DC->getDAG(); 6783 6784 // Check to see if IVal is all zeros in the part being masked in by the 'or' 6785 // that uses this. If not, this is not a replacement. 6786 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(), 6787 ByteShift*8, (ByteShift+NumBytes)*8); 6788 if (!DAG.MaskedValueIsZero(IVal, Mask)) return 0; 6789 6790 // Check that it is legal on the target to do this. It is legal if the new 6791 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type 6792 // legalization. 6793 MVT VT = MVT::getIntegerVT(NumBytes*8); 6794 if (!DC->isTypeLegal(VT)) 6795 return 0; 6796 6797 // Okay, we can do this! Replace the 'St' store with a store of IVal that is 6798 // shifted by ByteShift and truncated down to NumBytes. 6799 if (ByteShift) 6800 IVal = DAG.getNode(ISD::SRL, IVal->getDebugLoc(), IVal.getValueType(), IVal, 6801 DAG.getConstant(ByteShift*8, 6802 DC->getShiftAmountTy(IVal.getValueType()))); 6803 6804 // Figure out the offset for the store and the alignment of the access. 6805 unsigned StOffset; 6806 unsigned NewAlign = St->getAlignment(); 6807 6808 if (DAG.getTargetLoweringInfo().isLittleEndian()) 6809 StOffset = ByteShift; 6810 else 6811 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes; 6812 6813 SDValue Ptr = St->getBasePtr(); 6814 if (StOffset) { 6815 Ptr = DAG.getNode(ISD::ADD, IVal->getDebugLoc(), Ptr.getValueType(), 6816 Ptr, DAG.getConstant(StOffset, Ptr.getValueType())); 6817 NewAlign = MinAlign(NewAlign, StOffset); 6818 } 6819 6820 // Truncate down to the new size. 6821 IVal = DAG.getNode(ISD::TRUNCATE, IVal->getDebugLoc(), VT, IVal); 6822 6823 ++OpsNarrowed; 6824 return DAG.getStore(St->getChain(), St->getDebugLoc(), IVal, Ptr, 6825 St->getPointerInfo().getWithOffset(StOffset), 6826 false, false, NewAlign).getNode(); 6827} 6828 6829 6830/// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is 6831/// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some 6832/// of the loaded bits, try narrowing the load and store if it would end up 6833/// being a win for performance or code size. 6834SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) { 6835 StoreSDNode *ST = cast<StoreSDNode>(N); 6836 if (ST->isVolatile()) 6837 return SDValue(); 6838 6839 SDValue Chain = ST->getChain(); 6840 SDValue Value = ST->getValue(); 6841 SDValue Ptr = ST->getBasePtr(); 6842 EVT VT = Value.getValueType(); 6843 6844 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse()) 6845 return SDValue(); 6846 6847 unsigned Opc = Value.getOpcode(); 6848 6849 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst 6850 // is a byte mask indicating a consecutive number of bytes, check to see if 6851 // Y is known to provide just those bytes. If so, we try to replace the 6852 // load + replace + store sequence with a single (narrower) store, which makes 6853 // the load dead. 6854 if (Opc == ISD::OR) { 6855 std::pair<unsigned, unsigned> MaskedLoad; 6856 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain); 6857 if (MaskedLoad.first) 6858 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 6859 Value.getOperand(1), ST,this)) 6860 return SDValue(NewST, 0); 6861 6862 // Or is commutative, so try swapping X and Y. 6863 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain); 6864 if (MaskedLoad.first) 6865 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 6866 Value.getOperand(0), ST,this)) 6867 return SDValue(NewST, 0); 6868 } 6869 6870 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) || 6871 Value.getOperand(1).getOpcode() != ISD::Constant) 6872 return SDValue(); 6873 6874 SDValue N0 = Value.getOperand(0); 6875 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 6876 Chain == SDValue(N0.getNode(), 1)) { 6877 LoadSDNode *LD = cast<LoadSDNode>(N0); 6878 if (LD->getBasePtr() != Ptr || 6879 LD->getPointerInfo().getAddrSpace() != 6880 ST->getPointerInfo().getAddrSpace()) 6881 return SDValue(); 6882 6883 // Find the type to narrow it the load / op / store to. 6884 SDValue N1 = Value.getOperand(1); 6885 unsigned BitWidth = N1.getValueSizeInBits(); 6886 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue(); 6887 if (Opc == ISD::AND) 6888 Imm ^= APInt::getAllOnesValue(BitWidth); 6889 if (Imm == 0 || Imm.isAllOnesValue()) 6890 return SDValue(); 6891 unsigned ShAmt = Imm.countTrailingZeros(); 6892 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1; 6893 unsigned NewBW = NextPowerOf2(MSB - ShAmt); 6894 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 6895 while (NewBW < BitWidth && 6896 !(TLI.isOperationLegalOrCustom(Opc, NewVT) && 6897 TLI.isNarrowingProfitable(VT, NewVT))) { 6898 NewBW = NextPowerOf2(NewBW); 6899 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 6900 } 6901 if (NewBW >= BitWidth) 6902 return SDValue(); 6903 6904 // If the lsb changed does not start at the type bitwidth boundary, 6905 // start at the previous one. 6906 if (ShAmt % NewBW) 6907 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW; 6908 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW); 6909 if ((Imm & Mask) == Imm) { 6910 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW); 6911 if (Opc == ISD::AND) 6912 NewImm ^= APInt::getAllOnesValue(NewBW); 6913 uint64_t PtrOff = ShAmt / 8; 6914 // For big endian targets, we need to adjust the offset to the pointer to 6915 // load the correct bytes. 6916 if (TLI.isBigEndian()) 6917 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff; 6918 6919 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff); 6920 Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext()); 6921 if (NewAlign < TLI.getTargetData()->getABITypeAlignment(NewVTTy)) 6922 return SDValue(); 6923 6924 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(), 6925 Ptr.getValueType(), Ptr, 6926 DAG.getConstant(PtrOff, Ptr.getValueType())); 6927 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(), 6928 LD->getChain(), NewPtr, 6929 LD->getPointerInfo().getWithOffset(PtrOff), 6930 LD->isVolatile(), LD->isNonTemporal(), 6931 LD->isInvariant(), NewAlign); 6932 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD, 6933 DAG.getConstant(NewImm, NewVT)); 6934 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(), 6935 NewVal, NewPtr, 6936 ST->getPointerInfo().getWithOffset(PtrOff), 6937 false, false, NewAlign); 6938 6939 AddToWorkList(NewPtr.getNode()); 6940 AddToWorkList(NewLD.getNode()); 6941 AddToWorkList(NewVal.getNode()); 6942 WorkListRemover DeadNodes(*this); 6943 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1), 6944 &DeadNodes); 6945 ++OpsNarrowed; 6946 return NewST; 6947 } 6948 } 6949 6950 return SDValue(); 6951} 6952 6953/// TransformFPLoadStorePair - For a given floating point load / store pair, 6954/// if the load value isn't used by any other operations, then consider 6955/// transforming the pair to integer load / store operations if the target 6956/// deems the transformation profitable. 6957SDValue DAGCombiner::TransformFPLoadStorePair(SDNode *N) { 6958 StoreSDNode *ST = cast<StoreSDNode>(N); 6959 SDValue Chain = ST->getChain(); 6960 SDValue Value = ST->getValue(); 6961 if (ISD::isNormalStore(ST) && ISD::isNormalLoad(Value.getNode()) && 6962 Value.hasOneUse() && 6963 Chain == SDValue(Value.getNode(), 1)) { 6964 LoadSDNode *LD = cast<LoadSDNode>(Value); 6965 EVT VT = LD->getMemoryVT(); 6966 if (!VT.isFloatingPoint() || 6967 VT != ST->getMemoryVT() || 6968 LD->isNonTemporal() || 6969 ST->isNonTemporal() || 6970 LD->getPointerInfo().getAddrSpace() != 0 || 6971 ST->getPointerInfo().getAddrSpace() != 0) 6972 return SDValue(); 6973 6974 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits()); 6975 if (!TLI.isOperationLegal(ISD::LOAD, IntVT) || 6976 !TLI.isOperationLegal(ISD::STORE, IntVT) || 6977 !TLI.isDesirableToTransformToIntegerOp(ISD::LOAD, VT) || 6978 !TLI.isDesirableToTransformToIntegerOp(ISD::STORE, VT)) 6979 return SDValue(); 6980 6981 unsigned LDAlign = LD->getAlignment(); 6982 unsigned STAlign = ST->getAlignment(); 6983 Type *IntVTTy = IntVT.getTypeForEVT(*DAG.getContext()); 6984 unsigned ABIAlign = TLI.getTargetData()->getABITypeAlignment(IntVTTy); 6985 if (LDAlign < ABIAlign || STAlign < ABIAlign) 6986 return SDValue(); 6987 6988 SDValue NewLD = DAG.getLoad(IntVT, Value.getDebugLoc(), 6989 LD->getChain(), LD->getBasePtr(), 6990 LD->getPointerInfo(), 6991 false, false, false, LDAlign); 6992 6993 SDValue NewST = DAG.getStore(NewLD.getValue(1), N->getDebugLoc(), 6994 NewLD, ST->getBasePtr(), 6995 ST->getPointerInfo(), 6996 false, false, STAlign); 6997 6998 AddToWorkList(NewLD.getNode()); 6999 AddToWorkList(NewST.getNode()); 7000 WorkListRemover DeadNodes(*this); 7001 DAG.ReplaceAllUsesOfValueWith(Value.getValue(1), NewLD.getValue(1), 7002 &DeadNodes); 7003 ++LdStFP2Int; 7004 return NewST; 7005 } 7006 7007 return SDValue(); 7008} 7009 7010SDValue DAGCombiner::visitSTORE(SDNode *N) { 7011 StoreSDNode *ST = cast<StoreSDNode>(N); 7012 SDValue Chain = ST->getChain(); 7013 SDValue Value = ST->getValue(); 7014 SDValue Ptr = ST->getBasePtr(); 7015 7016 // If this is a store of a bit convert, store the input value if the 7017 // resultant store does not need a higher alignment than the original. 7018 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() && 7019 ST->isUnindexed()) { 7020 unsigned OrigAlign = ST->getAlignment(); 7021 EVT SVT = Value.getOperand(0).getValueType(); 7022 unsigned Align = TLI.getTargetData()-> 7023 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext())); 7024 if (Align <= OrigAlign && 7025 ((!LegalOperations && !ST->isVolatile()) || 7026 TLI.isOperationLegalOrCustom(ISD::STORE, SVT))) 7027 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0), 7028 Ptr, ST->getPointerInfo(), ST->isVolatile(), 7029 ST->isNonTemporal(), OrigAlign); 7030 } 7031 7032 // Turn 'store undef, Ptr' -> nothing. 7033 if (Value.getOpcode() == ISD::UNDEF && ST->isUnindexed()) 7034 return Chain; 7035 7036 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 7037 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 7038 // NOTE: If the original store is volatile, this transform must not increase 7039 // the number of stores. For example, on x86-32 an f64 can be stored in one 7040 // processor operation but an i64 (which is not legal) requires two. So the 7041 // transform should not be done in this case. 7042 if (Value.getOpcode() != ISD::TargetConstantFP) { 7043 SDValue Tmp; 7044 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) { 7045 default: llvm_unreachable("Unknown FP type"); 7046 case MVT::f80: // We don't do this for these yet. 7047 case MVT::f128: 7048 case MVT::ppcf128: 7049 break; 7050 case MVT::f32: 7051 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) || 7052 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 7053 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 7054 bitcastToAPInt().getZExtValue(), MVT::i32); 7055 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 7056 Ptr, ST->getPointerInfo(), ST->isVolatile(), 7057 ST->isNonTemporal(), ST->getAlignment()); 7058 } 7059 break; 7060 case MVT::f64: 7061 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations && 7062 !ST->isVolatile()) || 7063 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) { 7064 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 7065 getZExtValue(), MVT::i64); 7066 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 7067 Ptr, ST->getPointerInfo(), ST->isVolatile(), 7068 ST->isNonTemporal(), ST->getAlignment()); 7069 } 7070 7071 if (!ST->isVolatile() && 7072 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 7073 // Many FP stores are not made apparent until after legalize, e.g. for 7074 // argument passing. Since this is so common, custom legalize the 7075 // 64-bit integer store into two 32-bit stores. 7076 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); 7077 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 7078 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 7079 if (TLI.isBigEndian()) std::swap(Lo, Hi); 7080 7081 unsigned Alignment = ST->getAlignment(); 7082 bool isVolatile = ST->isVolatile(); 7083 bool isNonTemporal = ST->isNonTemporal(); 7084 7085 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo, 7086 Ptr, ST->getPointerInfo(), 7087 isVolatile, isNonTemporal, 7088 ST->getAlignment()); 7089 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr, 7090 DAG.getConstant(4, Ptr.getValueType())); 7091 Alignment = MinAlign(Alignment, 4U); 7092 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi, 7093 Ptr, ST->getPointerInfo().getWithOffset(4), 7094 isVolatile, isNonTemporal, 7095 Alignment); 7096 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 7097 St0, St1); 7098 } 7099 7100 break; 7101 } 7102 } 7103 } 7104 7105 // Try to infer better alignment information than the store already has. 7106 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) { 7107 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 7108 if (Align > ST->getAlignment()) 7109 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value, 7110 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 7111 ST->isVolatile(), ST->isNonTemporal(), Align); 7112 } 7113 } 7114 7115 // Try transforming a pair floating point load / store ops to integer 7116 // load / store ops. 7117 SDValue NewST = TransformFPLoadStorePair(N); 7118 if (NewST.getNode()) 7119 return NewST; 7120 7121 if (CombinerAA) { 7122 // Walk up chain skipping non-aliasing memory nodes. 7123 SDValue BetterChain = FindBetterChain(N, Chain); 7124 7125 // If there is a better chain. 7126 if (Chain != BetterChain) { 7127 SDValue ReplStore; 7128 7129 // Replace the chain to avoid dependency. 7130 if (ST->isTruncatingStore()) { 7131 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr, 7132 ST->getPointerInfo(), 7133 ST->getMemoryVT(), ST->isVolatile(), 7134 ST->isNonTemporal(), ST->getAlignment()); 7135 } else { 7136 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr, 7137 ST->getPointerInfo(), 7138 ST->isVolatile(), ST->isNonTemporal(), 7139 ST->getAlignment()); 7140 } 7141 7142 // Create token to keep both nodes around. 7143 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 7144 MVT::Other, Chain, ReplStore); 7145 7146 // Make sure the new and old chains are cleaned up. 7147 AddToWorkList(Token.getNode()); 7148 7149 // Don't add users to work list. 7150 return CombineTo(N, Token, false); 7151 } 7152 } 7153 7154 // Try transforming N to an indexed store. 7155 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 7156 return SDValue(N, 0); 7157 7158 // FIXME: is there such a thing as a truncating indexed store? 7159 if (ST->isTruncatingStore() && ST->isUnindexed() && 7160 Value.getValueType().isInteger()) { 7161 // See if we can simplify the input to this truncstore with knowledge that 7162 // only the low bits are being used. For example: 7163 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 7164 SDValue Shorter = 7165 GetDemandedBits(Value, 7166 APInt::getLowBitsSet( 7167 Value.getValueType().getScalarType().getSizeInBits(), 7168 ST->getMemoryVT().getScalarType().getSizeInBits())); 7169 AddToWorkList(Value.getNode()); 7170 if (Shorter.getNode()) 7171 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter, 7172 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 7173 ST->isVolatile(), ST->isNonTemporal(), 7174 ST->getAlignment()); 7175 7176 // Otherwise, see if we can simplify the operation with 7177 // SimplifyDemandedBits, which only works if the value has a single use. 7178 if (SimplifyDemandedBits(Value, 7179 APInt::getLowBitsSet( 7180 Value.getValueType().getScalarType().getSizeInBits(), 7181 ST->getMemoryVT().getScalarType().getSizeInBits()))) 7182 return SDValue(N, 0); 7183 } 7184 7185 // If this is a load followed by a store to the same location, then the store 7186 // is dead/noop. 7187 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 7188 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 7189 ST->isUnindexed() && !ST->isVolatile() && 7190 // There can't be any side effects between the load and store, such as 7191 // a call or store. 7192 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 7193 // The store is dead, remove it. 7194 return Chain; 7195 } 7196 } 7197 7198 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 7199 // truncating store. We can do this even if this is already a truncstore. 7200 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 7201 && Value.getNode()->hasOneUse() && ST->isUnindexed() && 7202 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 7203 ST->getMemoryVT())) { 7204 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0), 7205 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 7206 ST->isVolatile(), ST->isNonTemporal(), 7207 ST->getAlignment()); 7208 } 7209 7210 return ReduceLoadOpStoreWidth(N); 7211} 7212 7213SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 7214 SDValue InVec = N->getOperand(0); 7215 SDValue InVal = N->getOperand(1); 7216 SDValue EltNo = N->getOperand(2); 7217 DebugLoc dl = N->getDebugLoc(); 7218 7219 // If the inserted element is an UNDEF, just use the input vector. 7220 if (InVal.getOpcode() == ISD::UNDEF) 7221 return InVec; 7222 7223 EVT VT = InVec.getValueType(); 7224 7225 // If we can't generate a legal BUILD_VECTOR, exit 7226 if (LegalOperations && !TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) 7227 return SDValue(); 7228 7229 // Check that we know which element is being inserted 7230 if (!isa<ConstantSDNode>(EltNo)) 7231 return SDValue(); 7232 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 7233 7234 // Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially 7235 // be converted to a BUILD_VECTOR). Fill in the Ops vector with the 7236 // vector elements. 7237 SmallVector<SDValue, 8> Ops; 7238 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { 7239 Ops.append(InVec.getNode()->op_begin(), 7240 InVec.getNode()->op_end()); 7241 } else if (InVec.getOpcode() == ISD::UNDEF) { 7242 unsigned NElts = VT.getVectorNumElements(); 7243 Ops.append(NElts, DAG.getUNDEF(InVal.getValueType())); 7244 } else { 7245 return SDValue(); 7246 } 7247 7248 // Insert the element 7249 if (Elt < Ops.size()) { 7250 // All the operands of BUILD_VECTOR must have the same type; 7251 // we enforce that here. 7252 EVT OpVT = Ops[0].getValueType(); 7253 if (InVal.getValueType() != OpVT) 7254 InVal = OpVT.bitsGT(InVal.getValueType()) ? 7255 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) : 7256 DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal); 7257 Ops[Elt] = InVal; 7258 } 7259 7260 // Return the new vector 7261 return DAG.getNode(ISD::BUILD_VECTOR, dl, 7262 VT, &Ops[0], Ops.size()); 7263} 7264 7265SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 7266 // (vextract (scalar_to_vector val, 0) -> val 7267 SDValue InVec = N->getOperand(0); 7268 EVT VT = InVec.getValueType(); 7269 EVT NVT = N->getValueType(0); 7270 7271 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 7272 // Check if the result type doesn't match the inserted element type. A 7273 // SCALAR_TO_VECTOR may truncate the inserted element and the 7274 // EXTRACT_VECTOR_ELT may widen the extracted vector. 7275 SDValue InOp = InVec.getOperand(0); 7276 if (InOp.getValueType() != NVT) { 7277 assert(InOp.getValueType().isInteger() && NVT.isInteger()); 7278 return DAG.getSExtOrTrunc(InOp, InVec.getDebugLoc(), NVT); 7279 } 7280 return InOp; 7281 } 7282 7283 SDValue EltNo = N->getOperand(1); 7284 bool ConstEltNo = isa<ConstantSDNode>(EltNo); 7285 7286 // Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT. 7287 // We only perform this optimization before the op legalization phase because 7288 // we may introduce new vector instructions which are not backed by TD patterns. 7289 // For example on AVX, extracting elements from a wide vector without using 7290 // extract_subvector. 7291 if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE 7292 && ConstEltNo && !LegalOperations) { 7293 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 7294 int NumElem = VT.getVectorNumElements(); 7295 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(InVec); 7296 // Find the new index to extract from. 7297 int OrigElt = SVOp->getMaskElt(Elt); 7298 7299 // Extracting an undef index is undef. 7300 if (OrigElt == -1) 7301 return DAG.getUNDEF(NVT); 7302 7303 // Select the right vector half to extract from. 7304 if (OrigElt < NumElem) { 7305 InVec = InVec->getOperand(0); 7306 } else { 7307 InVec = InVec->getOperand(1); 7308 OrigElt -= NumElem; 7309 } 7310 7311 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(), NVT, 7312 InVec, DAG.getConstant(OrigElt, MVT::i32)); 7313 } 7314 7315 // Perform only after legalization to ensure build_vector / vector_shuffle 7316 // optimizations have already been done. 7317 if (!LegalOperations) return SDValue(); 7318 7319 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 7320 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 7321 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 7322 7323 if (ConstEltNo) { 7324 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 7325 bool NewLoad = false; 7326 bool BCNumEltsChanged = false; 7327 EVT ExtVT = VT.getVectorElementType(); 7328 EVT LVT = ExtVT; 7329 7330 // If the result of load has to be truncated, then it's not necessarily 7331 // profitable. 7332 if (NVT.bitsLT(LVT) && !TLI.isTruncateFree(LVT, NVT)) 7333 return SDValue(); 7334 7335 if (InVec.getOpcode() == ISD::BITCAST) { 7336 // Don't duplicate a load with other uses. 7337 if (!InVec.hasOneUse()) 7338 return SDValue(); 7339 7340 EVT BCVT = InVec.getOperand(0).getValueType(); 7341 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType())) 7342 return SDValue(); 7343 if (VT.getVectorNumElements() != BCVT.getVectorNumElements()) 7344 BCNumEltsChanged = true; 7345 InVec = InVec.getOperand(0); 7346 ExtVT = BCVT.getVectorElementType(); 7347 NewLoad = true; 7348 } 7349 7350 LoadSDNode *LN0 = NULL; 7351 const ShuffleVectorSDNode *SVN = NULL; 7352 if (ISD::isNormalLoad(InVec.getNode())) { 7353 LN0 = cast<LoadSDNode>(InVec); 7354 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 7355 InVec.getOperand(0).getValueType() == ExtVT && 7356 ISD::isNormalLoad(InVec.getOperand(0).getNode())) { 7357 // Don't duplicate a load with other uses. 7358 if (!InVec.hasOneUse()) 7359 return SDValue(); 7360 7361 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 7362 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) { 7363 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 7364 // => 7365 // (load $addr+1*size) 7366 7367 // Don't duplicate a load with other uses. 7368 if (!InVec.hasOneUse()) 7369 return SDValue(); 7370 7371 // If the bit convert changed the number of elements, it is unsafe 7372 // to examine the mask. 7373 if (BCNumEltsChanged) 7374 return SDValue(); 7375 7376 // Select the input vector, guarding against out of range extract vector. 7377 unsigned NumElems = VT.getVectorNumElements(); 7378 int Idx = (Elt > (int)NumElems) ? -1 : SVN->getMaskElt(Elt); 7379 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 7380 7381 if (InVec.getOpcode() == ISD::BITCAST) { 7382 // Don't duplicate a load with other uses. 7383 if (!InVec.hasOneUse()) 7384 return SDValue(); 7385 7386 InVec = InVec.getOperand(0); 7387 } 7388 if (ISD::isNormalLoad(InVec.getNode())) { 7389 LN0 = cast<LoadSDNode>(InVec); 7390 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems; 7391 } 7392 } 7393 7394 // Make sure we found a non-volatile load and the extractelement is 7395 // the only use. 7396 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile()) 7397 return SDValue(); 7398 7399 // If Idx was -1 above, Elt is going to be -1, so just return undef. 7400 if (Elt == -1) 7401 return DAG.getUNDEF(LVT); 7402 7403 unsigned Align = LN0->getAlignment(); 7404 if (NewLoad) { 7405 // Check the resultant load doesn't need a higher alignment than the 7406 // original load. 7407 unsigned NewAlign = 7408 TLI.getTargetData() 7409 ->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext())); 7410 7411 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT)) 7412 return SDValue(); 7413 7414 Align = NewAlign; 7415 } 7416 7417 SDValue NewPtr = LN0->getBasePtr(); 7418 unsigned PtrOff = 0; 7419 7420 if (Elt) { 7421 PtrOff = LVT.getSizeInBits() * Elt / 8; 7422 EVT PtrType = NewPtr.getValueType(); 7423 if (TLI.isBigEndian()) 7424 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 7425 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr, 7426 DAG.getConstant(PtrOff, PtrType)); 7427 } 7428 7429 // The replacement we need to do here is a little tricky: we need to 7430 // replace an extractelement of a load with a load. 7431 // Use ReplaceAllUsesOfValuesWith to do the replacement. 7432 // Note that this replacement assumes that the extractvalue is the only 7433 // use of the load; that's okay because we don't want to perform this 7434 // transformation in other cases anyway. 7435 SDValue Load; 7436 SDValue Chain; 7437 if (NVT.bitsGT(LVT)) { 7438 // If the result type of vextract is wider than the load, then issue an 7439 // extending load instead. 7440 ISD::LoadExtType ExtType = TLI.isLoadExtLegal(ISD::ZEXTLOAD, LVT) 7441 ? ISD::ZEXTLOAD : ISD::EXTLOAD; 7442 Load = DAG.getExtLoad(ExtType, N->getDebugLoc(), NVT, LN0->getChain(), 7443 NewPtr, LN0->getPointerInfo().getWithOffset(PtrOff), 7444 LVT, LN0->isVolatile(), LN0->isNonTemporal(),Align); 7445 Chain = Load.getValue(1); 7446 } else { 7447 Load = DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr, 7448 LN0->getPointerInfo().getWithOffset(PtrOff), 7449 LN0->isVolatile(), LN0->isNonTemporal(), 7450 LN0->isInvariant(), Align); 7451 Chain = Load.getValue(1); 7452 if (NVT.bitsLT(LVT)) 7453 Load = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), NVT, Load); 7454 else 7455 Load = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), NVT, Load); 7456 } 7457 WorkListRemover DeadNodes(*this); 7458 SDValue From[] = { SDValue(N, 0), SDValue(LN0,1) }; 7459 SDValue To[] = { Load, Chain }; 7460 DAG.ReplaceAllUsesOfValuesWith(From, To, 2, &DeadNodes); 7461 // Since we're explcitly calling ReplaceAllUses, add the new node to the 7462 // worklist explicitly as well. 7463 AddToWorkList(Load.getNode()); 7464 AddUsersToWorkList(Load.getNode()); // Add users too 7465 // Make sure to revisit this node to clean it up; it will usually be dead. 7466 AddToWorkList(N); 7467 return SDValue(N, 0); 7468 } 7469 7470 return SDValue(); 7471} 7472 7473SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 7474 unsigned NumInScalars = N->getNumOperands(); 7475 DebugLoc dl = N->getDebugLoc(); 7476 EVT VT = N->getValueType(0); 7477 // Check to see if this is a BUILD_VECTOR of a bunch of values 7478 // which come from any_extend or zero_extend nodes. If so, we can create 7479 // a new BUILD_VECTOR using bit-casts which may enable other BUILD_VECTOR 7480 // optimizations. We do not handle sign-extend because we can't fill the sign 7481 // using shuffles. 7482 EVT SourceType = MVT::Other; 7483 bool AllAnyExt = true; 7484 bool AllUndef = true; 7485 for (unsigned i = 0; i != NumInScalars; ++i) { 7486 SDValue In = N->getOperand(i); 7487 // Ignore undef inputs. 7488 if (In.getOpcode() == ISD::UNDEF) continue; 7489 AllUndef = false; 7490 7491 bool AnyExt = In.getOpcode() == ISD::ANY_EXTEND; 7492 bool ZeroExt = In.getOpcode() == ISD::ZERO_EXTEND; 7493 7494 // Abort if the element is not an extension. 7495 if (!ZeroExt && !AnyExt) { 7496 SourceType = MVT::Other; 7497 break; 7498 } 7499 7500 // The input is a ZeroExt or AnyExt. Check the original type. 7501 EVT InTy = In.getOperand(0).getValueType(); 7502 7503 // Check that all of the widened source types are the same. 7504 if (SourceType == MVT::Other) 7505 // First time. 7506 SourceType = InTy; 7507 else if (InTy != SourceType) { 7508 // Multiple income types. Abort. 7509 SourceType = MVT::Other; 7510 break; 7511 } 7512 7513 // Check if all of the extends are ANY_EXTENDs. 7514 AllAnyExt &= AnyExt; 7515 } 7516 7517 if (AllUndef) 7518 return DAG.getUNDEF(VT); 7519 7520 // In order to have valid types, all of the inputs must be extended from the 7521 // same source type and all of the inputs must be any or zero extend. 7522 // Scalar sizes must be a power of two. 7523 EVT OutScalarTy = N->getValueType(0).getScalarType(); 7524 bool ValidTypes = SourceType != MVT::Other && 7525 isPowerOf2_32(OutScalarTy.getSizeInBits()) && 7526 isPowerOf2_32(SourceType.getSizeInBits()); 7527 7528 // We perform this optimization post type-legalization because 7529 // the type-legalizer often scalarizes integer-promoted vectors. 7530 // Performing this optimization before may create bit-casts which 7531 // will be type-legalized to complex code sequences. 7532 // We perform this optimization only before the operation legalizer because we 7533 // may introduce illegal operations. 7534 // Create a new simpler BUILD_VECTOR sequence which other optimizations can 7535 // turn into a single shuffle instruction. 7536 if ((Level == AfterLegalizeVectorOps || Level == AfterLegalizeTypes) && 7537 ValidTypes) { 7538 bool isLE = TLI.isLittleEndian(); 7539 unsigned ElemRatio = OutScalarTy.getSizeInBits()/SourceType.getSizeInBits(); 7540 assert(ElemRatio > 1 && "Invalid element size ratio"); 7541 SDValue Filler = AllAnyExt ? DAG.getUNDEF(SourceType): 7542 DAG.getConstant(0, SourceType); 7543 7544 unsigned NewBVElems = ElemRatio * N->getValueType(0).getVectorNumElements(); 7545 SmallVector<SDValue, 8> Ops(NewBVElems, Filler); 7546 7547 // Populate the new build_vector 7548 for (unsigned i=0; i < N->getNumOperands(); ++i) { 7549 SDValue Cast = N->getOperand(i); 7550 assert((Cast.getOpcode() == ISD::ANY_EXTEND || 7551 Cast.getOpcode() == ISD::ZERO_EXTEND || 7552 Cast.getOpcode() == ISD::UNDEF) && "Invalid cast opcode"); 7553 SDValue In; 7554 if (Cast.getOpcode() == ISD::UNDEF) 7555 In = DAG.getUNDEF(SourceType); 7556 else 7557 In = Cast->getOperand(0); 7558 unsigned Index = isLE ? (i * ElemRatio) : 7559 (i * ElemRatio + (ElemRatio - 1)); 7560 7561 assert(Index < Ops.size() && "Invalid index"); 7562 Ops[Index] = In; 7563 } 7564 7565 // The type of the new BUILD_VECTOR node. 7566 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), SourceType, NewBVElems); 7567 assert(VecVT.getSizeInBits() == N->getValueType(0).getSizeInBits() && 7568 "Invalid vector size"); 7569 // Check if the new vector type is legal. 7570 if (!isTypeLegal(VecVT)) return SDValue(); 7571 7572 // Make the new BUILD_VECTOR. 7573 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 7574 VecVT, &Ops[0], Ops.size()); 7575 7576 // The new BUILD_VECTOR node has the potential to be further optimized. 7577 AddToWorkList(BV.getNode()); 7578 // Bitcast to the desired type. 7579 return DAG.getNode(ISD::BITCAST, dl, N->getValueType(0), BV); 7580 } 7581 7582 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 7583 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 7584 // at most two distinct vectors, turn this into a shuffle node. 7585 7586 // May only combine to shuffle after legalize if shuffle is legal. 7587 if (LegalOperations && 7588 !TLI.isOperationLegalOrCustom(ISD::VECTOR_SHUFFLE, VT)) 7589 return SDValue(); 7590 7591 SDValue VecIn1, VecIn2; 7592 for (unsigned i = 0; i != NumInScalars; ++i) { 7593 // Ignore undef inputs. 7594 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 7595 7596 // If this input is something other than a EXTRACT_VECTOR_ELT with a 7597 // constant index, bail out. 7598 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 7599 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 7600 VecIn1 = VecIn2 = SDValue(0, 0); 7601 break; 7602 } 7603 7604 // We allow up to two distinct input vectors. 7605 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 7606 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 7607 continue; 7608 7609 if (VecIn1.getNode() == 0) { 7610 VecIn1 = ExtractedFromVec; 7611 } else if (VecIn2.getNode() == 0) { 7612 VecIn2 = ExtractedFromVec; 7613 } else { 7614 // Too many inputs. 7615 VecIn1 = VecIn2 = SDValue(0, 0); 7616 break; 7617 } 7618 } 7619 7620 // If everything is good, we can make a shuffle operation. 7621 if (VecIn1.getNode()) { 7622 SmallVector<int, 8> Mask; 7623 for (unsigned i = 0; i != NumInScalars; ++i) { 7624 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 7625 Mask.push_back(-1); 7626 continue; 7627 } 7628 7629 // If extracting from the first vector, just use the index directly. 7630 SDValue Extract = N->getOperand(i); 7631 SDValue ExtVal = Extract.getOperand(1); 7632 if (Extract.getOperand(0) == VecIn1) { 7633 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 7634 if (ExtIndex > VT.getVectorNumElements()) 7635 return SDValue(); 7636 7637 Mask.push_back(ExtIndex); 7638 continue; 7639 } 7640 7641 // Otherwise, use InIdx + VecSize 7642 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 7643 Mask.push_back(Idx+NumInScalars); 7644 } 7645 7646 // We can't generate a shuffle node with mismatched input and output types. 7647 // Attempt to transform a single input vector to the correct type. 7648 if ((VT != VecIn1.getValueType())) { 7649 // We don't support shuffeling between TWO values of different types. 7650 if (VecIn2.getNode() != 0) 7651 return SDValue(); 7652 7653 // We only support widening of vectors which are half the size of the 7654 // output registers. For example XMM->YMM widening on X86 with AVX. 7655 if (VecIn1.getValueType().getSizeInBits()*2 != VT.getSizeInBits()) 7656 return SDValue(); 7657 7658 // Widen the input vector by adding undef values. 7659 VecIn1 = DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT, 7660 VecIn1, DAG.getUNDEF(VecIn1.getValueType())); 7661 } 7662 7663 // If VecIn2 is unused then change it to undef. 7664 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT); 7665 7666 // Check that we were able to transform all incoming values to the same type. 7667 if (VecIn2.getValueType() != VecIn1.getValueType() || 7668 VecIn1.getValueType() != VT) 7669 return SDValue(); 7670 7671 // Only type-legal BUILD_VECTOR nodes are converted to shuffle nodes. 7672 if (!isTypeLegal(VT)) 7673 return SDValue(); 7674 7675 // Return the new VECTOR_SHUFFLE node. 7676 SDValue Ops[2]; 7677 Ops[0] = VecIn1; 7678 Ops[1] = VecIn2; 7679 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]); 7680 } 7681 7682 return SDValue(); 7683} 7684 7685SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 7686 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 7687 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 7688 // inputs come from at most two distinct vectors, turn this into a shuffle 7689 // node. 7690 7691 // If we only have one input vector, we don't need to do any concatenation. 7692 if (N->getNumOperands() == 1) 7693 return N->getOperand(0); 7694 7695 return SDValue(); 7696} 7697 7698SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode* N) { 7699 EVT NVT = N->getValueType(0); 7700 SDValue V = N->getOperand(0); 7701 7702 if (V->getOpcode() == ISD::INSERT_SUBVECTOR) { 7703 // Handle only simple case where vector being inserted and vector 7704 // being extracted are of same type, and are half size of larger vectors. 7705 EVT BigVT = V->getOperand(0).getValueType(); 7706 EVT SmallVT = V->getOperand(1).getValueType(); 7707 if (NVT != SmallVT || NVT.getSizeInBits()*2 != BigVT.getSizeInBits()) 7708 return SDValue(); 7709 7710 // Only handle cases where both indexes are constants with the same type. 7711 ConstantSDNode *InsIdx = dyn_cast<ConstantSDNode>(N->getOperand(1)); 7712 ConstantSDNode *ExtIdx = dyn_cast<ConstantSDNode>(V->getOperand(2)); 7713 7714 if (InsIdx && ExtIdx && 7715 InsIdx->getValueType(0).getSizeInBits() <= 64 && 7716 ExtIdx->getValueType(0).getSizeInBits() <= 64) { 7717 // Combine: 7718 // (extract_subvec (insert_subvec V1, V2, InsIdx), ExtIdx) 7719 // Into: 7720 // indices are equal => V1 7721 // otherwise => (extract_subvec V1, ExtIdx) 7722 if (InsIdx->getZExtValue() == ExtIdx->getZExtValue()) 7723 return V->getOperand(1); 7724 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, N->getDebugLoc(), NVT, 7725 V->getOperand(0), N->getOperand(1)); 7726 } 7727 } 7728 7729 return SDValue(); 7730} 7731 7732SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 7733 EVT VT = N->getValueType(0); 7734 unsigned NumElts = VT.getVectorNumElements(); 7735 7736 SDValue N0 = N->getOperand(0); 7737 SDValue N1 = N->getOperand(1); 7738 7739 assert(N0.getValueType() == VT && "Vector shuffle must be normalized in DAG"); 7740 7741 // Canonicalize shuffle undef, undef -> undef 7742 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 7743 return DAG.getUNDEF(VT); 7744 7745 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N); 7746 7747 // Canonicalize shuffle v, v -> v, undef 7748 if (N0 == N1) { 7749 SmallVector<int, 8> NewMask; 7750 for (unsigned i = 0; i != NumElts; ++i) { 7751 int Idx = SVN->getMaskElt(i); 7752 if (Idx >= (int)NumElts) Idx -= NumElts; 7753 NewMask.push_back(Idx); 7754 } 7755 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N0, DAG.getUNDEF(VT), 7756 &NewMask[0]); 7757 } 7758 7759 // Canonicalize shuffle undef, v -> v, undef. Commute the shuffle mask. 7760 if (N0.getOpcode() == ISD::UNDEF) { 7761 SmallVector<int, 8> NewMask; 7762 for (unsigned i = 0; i != NumElts; ++i) { 7763 int Idx = SVN->getMaskElt(i); 7764 if (Idx >= 0) { 7765 if (Idx < (int)NumElts) 7766 Idx += NumElts; 7767 else 7768 Idx -= NumElts; 7769 } 7770 NewMask.push_back(Idx); 7771 } 7772 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N1, DAG.getUNDEF(VT), 7773 &NewMask[0]); 7774 } 7775 7776 // Remove references to rhs if it is undef 7777 if (N1.getOpcode() == ISD::UNDEF) { 7778 bool Changed = false; 7779 SmallVector<int, 8> NewMask; 7780 for (unsigned i = 0; i != NumElts; ++i) { 7781 int Idx = SVN->getMaskElt(i); 7782 if (Idx >= (int)NumElts) { 7783 Idx = -1; 7784 Changed = true; 7785 } 7786 NewMask.push_back(Idx); 7787 } 7788 if (Changed) 7789 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N0, N1, &NewMask[0]); 7790 } 7791 7792 // If it is a splat, check if the argument vector is another splat or a 7793 // build_vector with all scalar elements the same. 7794 if (SVN->isSplat() && SVN->getSplatIndex() < (int)NumElts) { 7795 SDNode *V = N0.getNode(); 7796 7797 // If this is a bit convert that changes the element type of the vector but 7798 // not the number of vector elements, look through it. Be careful not to 7799 // look though conversions that change things like v4f32 to v2f64. 7800 if (V->getOpcode() == ISD::BITCAST) { 7801 SDValue ConvInput = V->getOperand(0); 7802 if (ConvInput.getValueType().isVector() && 7803 ConvInput.getValueType().getVectorNumElements() == NumElts) 7804 V = ConvInput.getNode(); 7805 } 7806 7807 if (V->getOpcode() == ISD::BUILD_VECTOR) { 7808 assert(V->getNumOperands() == NumElts && 7809 "BUILD_VECTOR has wrong number of operands"); 7810 SDValue Base; 7811 bool AllSame = true; 7812 for (unsigned i = 0; i != NumElts; ++i) { 7813 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 7814 Base = V->getOperand(i); 7815 break; 7816 } 7817 } 7818 // Splat of <u, u, u, u>, return <u, u, u, u> 7819 if (!Base.getNode()) 7820 return N0; 7821 for (unsigned i = 0; i != NumElts; ++i) { 7822 if (V->getOperand(i) != Base) { 7823 AllSame = false; 7824 break; 7825 } 7826 } 7827 // Splat of <x, x, x, x>, return <x, x, x, x> 7828 if (AllSame) 7829 return N0; 7830 } 7831 } 7832 7833 // If this shuffle node is simply a swizzle of another shuffle node, 7834 // and it reverses the swizzle of the previous shuffle then we can 7835 // optimize shuffle(shuffle(x, undef), undef) -> x. 7836 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG && 7837 N1.getOpcode() == ISD::UNDEF) { 7838 7839 ShuffleVectorSDNode *OtherSV = cast<ShuffleVectorSDNode>(N0); 7840 7841 // Shuffle nodes can only reverse shuffles with a single non-undef value. 7842 if (N0.getOperand(1).getOpcode() != ISD::UNDEF) 7843 return SDValue(); 7844 7845 // The incoming shuffle must be of the same type as the result of the 7846 // current shuffle. 7847 assert(OtherSV->getOperand(0).getValueType() == VT && 7848 "Shuffle types don't match"); 7849 7850 for (unsigned i = 0; i != NumElts; ++i) { 7851 int Idx = SVN->getMaskElt(i); 7852 assert(Idx < (int)NumElts && "Index references undef operand"); 7853 // Next, this index comes from the first value, which is the incoming 7854 // shuffle. Adopt the incoming index. 7855 if (Idx >= 0) 7856 Idx = OtherSV->getMaskElt(Idx); 7857 7858 // The combined shuffle must map each index to itself. 7859 if (Idx >= 0 && (unsigned)Idx != i) 7860 return SDValue(); 7861 } 7862 7863 return OtherSV->getOperand(0); 7864 } 7865 7866 return SDValue(); 7867} 7868 7869SDValue DAGCombiner::visitMEMBARRIER(SDNode* N) { 7870 if (!TLI.getShouldFoldAtomicFences()) 7871 return SDValue(); 7872 7873 SDValue atomic = N->getOperand(0); 7874 switch (atomic.getOpcode()) { 7875 case ISD::ATOMIC_CMP_SWAP: 7876 case ISD::ATOMIC_SWAP: 7877 case ISD::ATOMIC_LOAD_ADD: 7878 case ISD::ATOMIC_LOAD_SUB: 7879 case ISD::ATOMIC_LOAD_AND: 7880 case ISD::ATOMIC_LOAD_OR: 7881 case ISD::ATOMIC_LOAD_XOR: 7882 case ISD::ATOMIC_LOAD_NAND: 7883 case ISD::ATOMIC_LOAD_MIN: 7884 case ISD::ATOMIC_LOAD_MAX: 7885 case ISD::ATOMIC_LOAD_UMIN: 7886 case ISD::ATOMIC_LOAD_UMAX: 7887 break; 7888 default: 7889 return SDValue(); 7890 } 7891 7892 SDValue fence = atomic.getOperand(0); 7893 if (fence.getOpcode() != ISD::MEMBARRIER) 7894 return SDValue(); 7895 7896 switch (atomic.getOpcode()) { 7897 case ISD::ATOMIC_CMP_SWAP: 7898 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(), 7899 fence.getOperand(0), 7900 atomic.getOperand(1), atomic.getOperand(2), 7901 atomic.getOperand(3)), atomic.getResNo()); 7902 case ISD::ATOMIC_SWAP: 7903 case ISD::ATOMIC_LOAD_ADD: 7904 case ISD::ATOMIC_LOAD_SUB: 7905 case ISD::ATOMIC_LOAD_AND: 7906 case ISD::ATOMIC_LOAD_OR: 7907 case ISD::ATOMIC_LOAD_XOR: 7908 case ISD::ATOMIC_LOAD_NAND: 7909 case ISD::ATOMIC_LOAD_MIN: 7910 case ISD::ATOMIC_LOAD_MAX: 7911 case ISD::ATOMIC_LOAD_UMIN: 7912 case ISD::ATOMIC_LOAD_UMAX: 7913 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(), 7914 fence.getOperand(0), 7915 atomic.getOperand(1), atomic.getOperand(2)), 7916 atomic.getResNo()); 7917 default: 7918 return SDValue(); 7919 } 7920} 7921 7922/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 7923/// an AND to a vector_shuffle with the destination vector and a zero vector. 7924/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 7925/// vector_shuffle V, Zero, <0, 4, 2, 4> 7926SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 7927 EVT VT = N->getValueType(0); 7928 DebugLoc dl = N->getDebugLoc(); 7929 SDValue LHS = N->getOperand(0); 7930 SDValue RHS = N->getOperand(1); 7931 if (N->getOpcode() == ISD::AND) { 7932 if (RHS.getOpcode() == ISD::BITCAST) 7933 RHS = RHS.getOperand(0); 7934 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 7935 SmallVector<int, 8> Indices; 7936 unsigned NumElts = RHS.getNumOperands(); 7937 for (unsigned i = 0; i != NumElts; ++i) { 7938 SDValue Elt = RHS.getOperand(i); 7939 if (!isa<ConstantSDNode>(Elt)) 7940 return SDValue(); 7941 7942 if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 7943 Indices.push_back(i); 7944 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 7945 Indices.push_back(NumElts); 7946 else 7947 return SDValue(); 7948 } 7949 7950 // Let's see if the target supports this vector_shuffle. 7951 EVT RVT = RHS.getValueType(); 7952 if (!TLI.isVectorClearMaskLegal(Indices, RVT)) 7953 return SDValue(); 7954 7955 // Return the new VECTOR_SHUFFLE node. 7956 EVT EltVT = RVT.getVectorElementType(); 7957 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(), 7958 DAG.getConstant(0, EltVT)); 7959 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 7960 RVT, &ZeroOps[0], ZeroOps.size()); 7961 LHS = DAG.getNode(ISD::BITCAST, dl, RVT, LHS); 7962 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]); 7963 return DAG.getNode(ISD::BITCAST, dl, VT, Shuf); 7964 } 7965 } 7966 7967 return SDValue(); 7968} 7969 7970/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 7971SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 7972 // After legalize, the target may be depending on adds and other 7973 // binary ops to provide legal ways to construct constants or other 7974 // things. Simplifying them may result in a loss of legality. 7975 if (LegalOperations) return SDValue(); 7976 7977 assert(N->getValueType(0).isVector() && 7978 "SimplifyVBinOp only works on vectors!"); 7979 7980 SDValue LHS = N->getOperand(0); 7981 SDValue RHS = N->getOperand(1); 7982 SDValue Shuffle = XformToShuffleWithZero(N); 7983 if (Shuffle.getNode()) return Shuffle; 7984 7985 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 7986 // this operation. 7987 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 7988 RHS.getOpcode() == ISD::BUILD_VECTOR) { 7989 SmallVector<SDValue, 8> Ops; 7990 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 7991 SDValue LHSOp = LHS.getOperand(i); 7992 SDValue RHSOp = RHS.getOperand(i); 7993 // If these two elements can't be folded, bail out. 7994 if ((LHSOp.getOpcode() != ISD::UNDEF && 7995 LHSOp.getOpcode() != ISD::Constant && 7996 LHSOp.getOpcode() != ISD::ConstantFP) || 7997 (RHSOp.getOpcode() != ISD::UNDEF && 7998 RHSOp.getOpcode() != ISD::Constant && 7999 RHSOp.getOpcode() != ISD::ConstantFP)) 8000 break; 8001 8002 // Can't fold divide by zero. 8003 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 8004 N->getOpcode() == ISD::FDIV) { 8005 if ((RHSOp.getOpcode() == ISD::Constant && 8006 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) || 8007 (RHSOp.getOpcode() == ISD::ConstantFP && 8008 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero())) 8009 break; 8010 } 8011 8012 EVT VT = LHSOp.getValueType(); 8013 EVT RVT = RHSOp.getValueType(); 8014 if (RVT != VT) { 8015 // Integer BUILD_VECTOR operands may have types larger than the element 8016 // size (e.g., when the element type is not legal). Prior to type 8017 // legalization, the types may not match between the two BUILD_VECTORS. 8018 // Truncate one of the operands to make them match. 8019 if (RVT.getSizeInBits() > VT.getSizeInBits()) { 8020 RHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, RHSOp); 8021 } else { 8022 LHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), RVT, LHSOp); 8023 VT = RVT; 8024 } 8025 } 8026 SDValue FoldOp = DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), VT, 8027 LHSOp, RHSOp); 8028 if (FoldOp.getOpcode() != ISD::UNDEF && 8029 FoldOp.getOpcode() != ISD::Constant && 8030 FoldOp.getOpcode() != ISD::ConstantFP) 8031 break; 8032 Ops.push_back(FoldOp); 8033 AddToWorkList(FoldOp.getNode()); 8034 } 8035 8036 if (Ops.size() == LHS.getNumOperands()) 8037 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 8038 LHS.getValueType(), &Ops[0], Ops.size()); 8039 } 8040 8041 return SDValue(); 8042} 8043 8044SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0, 8045 SDValue N1, SDValue N2){ 8046 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 8047 8048 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2, 8049 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 8050 8051 // If we got a simplified select_cc node back from SimplifySelectCC, then 8052 // break it down into a new SETCC node, and a new SELECT node, and then return 8053 // the SELECT node, since we were called with a SELECT node. 8054 if (SCC.getNode()) { 8055 // Check to see if we got a select_cc back (to turn into setcc/select). 8056 // Otherwise, just return whatever node we got back, like fabs. 8057 if (SCC.getOpcode() == ISD::SELECT_CC) { 8058 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(), 8059 N0.getValueType(), 8060 SCC.getOperand(0), SCC.getOperand(1), 8061 SCC.getOperand(4)); 8062 AddToWorkList(SETCC.getNode()); 8063 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(), 8064 SCC.getOperand(2), SCC.getOperand(3), SETCC); 8065 } 8066 8067 return SCC; 8068 } 8069 return SDValue(); 8070} 8071 8072/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 8073/// are the two values being selected between, see if we can simplify the 8074/// select. Callers of this should assume that TheSelect is deleted if this 8075/// returns true. As such, they should return the appropriate thing (e.g. the 8076/// node) back to the top-level of the DAG combiner loop to avoid it being 8077/// looked at. 8078bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 8079 SDValue RHS) { 8080 8081 // Cannot simplify select with vector condition 8082 if (TheSelect->getOperand(0).getValueType().isVector()) return false; 8083 8084 // If this is a select from two identical things, try to pull the operation 8085 // through the select. 8086 if (LHS.getOpcode() != RHS.getOpcode() || 8087 !LHS.hasOneUse() || !RHS.hasOneUse()) 8088 return false; 8089 8090 // If this is a load and the token chain is identical, replace the select 8091 // of two loads with a load through a select of the address to load from. 8092 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 8093 // constants have been dropped into the constant pool. 8094 if (LHS.getOpcode() == ISD::LOAD) { 8095 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 8096 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 8097 8098 // Token chains must be identical. 8099 if (LHS.getOperand(0) != RHS.getOperand(0) || 8100 // Do not let this transformation reduce the number of volatile loads. 8101 LLD->isVolatile() || RLD->isVolatile() || 8102 // If this is an EXTLOAD, the VT's must match. 8103 LLD->getMemoryVT() != RLD->getMemoryVT() || 8104 // If this is an EXTLOAD, the kind of extension must match. 8105 (LLD->getExtensionType() != RLD->getExtensionType() && 8106 // The only exception is if one of the extensions is anyext. 8107 LLD->getExtensionType() != ISD::EXTLOAD && 8108 RLD->getExtensionType() != ISD::EXTLOAD) || 8109 // FIXME: this discards src value information. This is 8110 // over-conservative. It would be beneficial to be able to remember 8111 // both potential memory locations. Since we are discarding 8112 // src value info, don't do the transformation if the memory 8113 // locations are not in the default address space. 8114 LLD->getPointerInfo().getAddrSpace() != 0 || 8115 RLD->getPointerInfo().getAddrSpace() != 0) 8116 return false; 8117 8118 // Check that the select condition doesn't reach either load. If so, 8119 // folding this will induce a cycle into the DAG. If not, this is safe to 8120 // xform, so create a select of the addresses. 8121 SDValue Addr; 8122 if (TheSelect->getOpcode() == ISD::SELECT) { 8123 SDNode *CondNode = TheSelect->getOperand(0).getNode(); 8124 if ((LLD->hasAnyUseOfValue(1) && LLD->isPredecessorOf(CondNode)) || 8125 (RLD->hasAnyUseOfValue(1) && RLD->isPredecessorOf(CondNode))) 8126 return false; 8127 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(), 8128 LLD->getBasePtr().getValueType(), 8129 TheSelect->getOperand(0), LLD->getBasePtr(), 8130 RLD->getBasePtr()); 8131 } else { // Otherwise SELECT_CC 8132 SDNode *CondLHS = TheSelect->getOperand(0).getNode(); 8133 SDNode *CondRHS = TheSelect->getOperand(1).getNode(); 8134 8135 if ((LLD->hasAnyUseOfValue(1) && 8136 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))) || 8137 (RLD->hasAnyUseOfValue(1) && 8138 (RLD->isPredecessorOf(CondLHS) || RLD->isPredecessorOf(CondRHS)))) 8139 return false; 8140 8141 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(), 8142 LLD->getBasePtr().getValueType(), 8143 TheSelect->getOperand(0), 8144 TheSelect->getOperand(1), 8145 LLD->getBasePtr(), RLD->getBasePtr(), 8146 TheSelect->getOperand(4)); 8147 } 8148 8149 SDValue Load; 8150 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) { 8151 Load = DAG.getLoad(TheSelect->getValueType(0), 8152 TheSelect->getDebugLoc(), 8153 // FIXME: Discards pointer info. 8154 LLD->getChain(), Addr, MachinePointerInfo(), 8155 LLD->isVolatile(), LLD->isNonTemporal(), 8156 LLD->isInvariant(), LLD->getAlignment()); 8157 } else { 8158 Load = DAG.getExtLoad(LLD->getExtensionType() == ISD::EXTLOAD ? 8159 RLD->getExtensionType() : LLD->getExtensionType(), 8160 TheSelect->getDebugLoc(), 8161 TheSelect->getValueType(0), 8162 // FIXME: Discards pointer info. 8163 LLD->getChain(), Addr, MachinePointerInfo(), 8164 LLD->getMemoryVT(), LLD->isVolatile(), 8165 LLD->isNonTemporal(), LLD->getAlignment()); 8166 } 8167 8168 // Users of the select now use the result of the load. 8169 CombineTo(TheSelect, Load); 8170 8171 // Users of the old loads now use the new load's chain. We know the 8172 // old-load value is dead now. 8173 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); 8174 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); 8175 return true; 8176 } 8177 8178 return false; 8179} 8180 8181/// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3 8182/// where 'cond' is the comparison specified by CC. 8183SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, 8184 SDValue N2, SDValue N3, 8185 ISD::CondCode CC, bool NotExtCompare) { 8186 // (x ? y : y) -> y. 8187 if (N2 == N3) return N2; 8188 8189 EVT VT = N2.getValueType(); 8190 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 8191 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 8192 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); 8193 8194 // Determine if the condition we're dealing with is constant 8195 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 8196 N0, N1, CC, DL, false); 8197 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 8198 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode()); 8199 8200 // fold select_cc true, x, y -> x 8201 if (SCCC && !SCCC->isNullValue()) 8202 return N2; 8203 // fold select_cc false, x, y -> y 8204 if (SCCC && SCCC->isNullValue()) 8205 return N3; 8206 8207 // Check to see if we can simplify the select into an fabs node 8208 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 8209 // Allow either -0.0 or 0.0 8210 if (CFP->getValueAPF().isZero()) { 8211 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 8212 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 8213 N0 == N2 && N3.getOpcode() == ISD::FNEG && 8214 N2 == N3.getOperand(0)) 8215 return DAG.getNode(ISD::FABS, DL, VT, N0); 8216 8217 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 8218 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 8219 N0 == N3 && N2.getOpcode() == ISD::FNEG && 8220 N2.getOperand(0) == N3) 8221 return DAG.getNode(ISD::FABS, DL, VT, N3); 8222 } 8223 } 8224 8225 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)" 8226 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0 8227 // in it. This is a win when the constant is not otherwise available because 8228 // it replaces two constant pool loads with one. We only do this if the FP 8229 // type is known to be legal, because if it isn't, then we are before legalize 8230 // types an we want the other legalization to happen first (e.g. to avoid 8231 // messing with soft float) and if the ConstantFP is not legal, because if 8232 // it is legal, we may not need to store the FP constant in a constant pool. 8233 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2)) 8234 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) { 8235 if (TLI.isTypeLegal(N2.getValueType()) && 8236 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) != 8237 TargetLowering::Legal) && 8238 // If both constants have multiple uses, then we won't need to do an 8239 // extra load, they are likely around in registers for other users. 8240 (TV->hasOneUse() || FV->hasOneUse())) { 8241 Constant *Elts[] = { 8242 const_cast<ConstantFP*>(FV->getConstantFPValue()), 8243 const_cast<ConstantFP*>(TV->getConstantFPValue()) 8244 }; 8245 Type *FPTy = Elts[0]->getType(); 8246 const TargetData &TD = *TLI.getTargetData(); 8247 8248 // Create a ConstantArray of the two constants. 8249 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts); 8250 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(), 8251 TD.getPrefTypeAlignment(FPTy)); 8252 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 8253 8254 // Get the offsets to the 0 and 1 element of the array so that we can 8255 // select between them. 8256 SDValue Zero = DAG.getIntPtrConstant(0); 8257 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType()); 8258 SDValue One = DAG.getIntPtrConstant(EltSize); 8259 8260 SDValue Cond = DAG.getSetCC(DL, 8261 TLI.getSetCCResultType(N0.getValueType()), 8262 N0, N1, CC); 8263 AddToWorkList(Cond.getNode()); 8264 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(), 8265 Cond, One, Zero); 8266 AddToWorkList(CstOffset.getNode()); 8267 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx, 8268 CstOffset); 8269 AddToWorkList(CPIdx.getNode()); 8270 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx, 8271 MachinePointerInfo::getConstantPool(), false, 8272 false, false, Alignment); 8273 8274 } 8275 } 8276 8277 // Check to see if we can perform the "gzip trick", transforming 8278 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A) 8279 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 8280 (N1C->isNullValue() || // (a < 0) ? b : 0 8281 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 8282 EVT XType = N0.getValueType(); 8283 EVT AType = N2.getValueType(); 8284 if (XType.bitsGE(AType)) { 8285 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 8286 // single-bit constant. 8287 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 8288 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 8289 ShCtV = XType.getSizeInBits()-ShCtV-1; 8290 SDValue ShCt = DAG.getConstant(ShCtV, 8291 getShiftAmountTy(N0.getValueType())); 8292 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), 8293 XType, N0, ShCt); 8294 AddToWorkList(Shift.getNode()); 8295 8296 if (XType.bitsGT(AType)) { 8297 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 8298 AddToWorkList(Shift.getNode()); 8299 } 8300 8301 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 8302 } 8303 8304 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), 8305 XType, N0, 8306 DAG.getConstant(XType.getSizeInBits()-1, 8307 getShiftAmountTy(N0.getValueType()))); 8308 AddToWorkList(Shift.getNode()); 8309 8310 if (XType.bitsGT(AType)) { 8311 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 8312 AddToWorkList(Shift.getNode()); 8313 } 8314 8315 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 8316 } 8317 } 8318 8319 // fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A) 8320 // where y is has a single bit set. 8321 // A plaintext description would be, we can turn the SELECT_CC into an AND 8322 // when the condition can be materialized as an all-ones register. Any 8323 // single bit-test can be materialized as an all-ones register with 8324 // shift-left and shift-right-arith. 8325 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND && 8326 N0->getValueType(0) == VT && 8327 N1C && N1C->isNullValue() && 8328 N2C && N2C->isNullValue()) { 8329 SDValue AndLHS = N0->getOperand(0); 8330 ConstantSDNode *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1)); 8331 if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) { 8332 // Shift the tested bit over the sign bit. 8333 APInt AndMask = ConstAndRHS->getAPIntValue(); 8334 SDValue ShlAmt = 8335 DAG.getConstant(AndMask.countLeadingZeros(), 8336 getShiftAmountTy(AndLHS.getValueType())); 8337 SDValue Shl = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, AndLHS, ShlAmt); 8338 8339 // Now arithmetic right shift it all the way over, so the result is either 8340 // all-ones, or zero. 8341 SDValue ShrAmt = 8342 DAG.getConstant(AndMask.getBitWidth()-1, 8343 getShiftAmountTy(Shl.getValueType())); 8344 SDValue Shr = DAG.getNode(ISD::SRA, N0.getDebugLoc(), VT, Shl, ShrAmt); 8345 8346 return DAG.getNode(ISD::AND, DL, VT, Shr, N3); 8347 } 8348 } 8349 8350 // fold select C, 16, 0 -> shl C, 4 8351 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 8352 TLI.getBooleanContents(N0.getValueType().isVector()) == 8353 TargetLowering::ZeroOrOneBooleanContent) { 8354 8355 // If the caller doesn't want us to simplify this into a zext of a compare, 8356 // don't do it. 8357 if (NotExtCompare && N2C->getAPIntValue() == 1) 8358 return SDValue(); 8359 8360 // Get a SetCC of the condition 8361 // FIXME: Should probably make sure that setcc is legal if we ever have a 8362 // target where it isn't. 8363 SDValue Temp, SCC; 8364 // cast from setcc result type to select result type 8365 if (LegalTypes) { 8366 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()), 8367 N0, N1, CC); 8368 if (N2.getValueType().bitsLT(SCC.getValueType())) 8369 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType()); 8370 else 8371 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 8372 N2.getValueType(), SCC); 8373 } else { 8374 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC); 8375 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 8376 N2.getValueType(), SCC); 8377 } 8378 8379 AddToWorkList(SCC.getNode()); 8380 AddToWorkList(Temp.getNode()); 8381 8382 if (N2C->getAPIntValue() == 1) 8383 return Temp; 8384 8385 // shl setcc result by log2 n2c 8386 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp, 8387 DAG.getConstant(N2C->getAPIntValue().logBase2(), 8388 getShiftAmountTy(Temp.getValueType()))); 8389 } 8390 8391 // Check to see if this is the equivalent of setcc 8392 // FIXME: Turn all of these into setcc if setcc if setcc is legal 8393 // otherwise, go ahead with the folds. 8394 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 8395 EVT XType = N0.getValueType(); 8396 if (!LegalOperations || 8397 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) { 8398 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC); 8399 if (Res.getValueType() != VT) 8400 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res); 8401 return Res; 8402 } 8403 8404 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X)))) 8405 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 8406 (!LegalOperations || 8407 TLI.isOperationLegal(ISD::CTLZ, XType))) { 8408 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0); 8409 return DAG.getNode(ISD::SRL, DL, XType, Ctlz, 8410 DAG.getConstant(Log2_32(XType.getSizeInBits()), 8411 getShiftAmountTy(Ctlz.getValueType()))); 8412 } 8413 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1)) 8414 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 8415 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(), 8416 XType, DAG.getConstant(0, XType), N0); 8417 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType); 8418 return DAG.getNode(ISD::SRL, DL, XType, 8419 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0), 8420 DAG.getConstant(XType.getSizeInBits()-1, 8421 getShiftAmountTy(XType))); 8422 } 8423 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1)) 8424 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 8425 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0, 8426 DAG.getConstant(XType.getSizeInBits()-1, 8427 getShiftAmountTy(N0.getValueType()))); 8428 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType)); 8429 } 8430 } 8431 8432 // Check to see if this is an integer abs. 8433 // select_cc setg[te] X, 0, X, -X -> 8434 // select_cc setgt X, -1, X, -X -> 8435 // select_cc setl[te] X, 0, -X, X -> 8436 // select_cc setlt X, 1, -X, X -> 8437 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 8438 if (N1C) { 8439 ConstantSDNode *SubC = NULL; 8440 if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) || 8441 (N1C->isAllOnesValue() && CC == ISD::SETGT)) && 8442 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) 8443 SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0)); 8444 else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) || 8445 (N1C->isOne() && CC == ISD::SETLT)) && 8446 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) 8447 SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0)); 8448 8449 EVT XType = N0.getValueType(); 8450 if (SubC && SubC->isNullValue() && XType.isInteger()) { 8451 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, 8452 N0, 8453 DAG.getConstant(XType.getSizeInBits()-1, 8454 getShiftAmountTy(N0.getValueType()))); 8455 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), 8456 XType, N0, Shift); 8457 AddToWorkList(Shift.getNode()); 8458 AddToWorkList(Add.getNode()); 8459 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 8460 } 8461 } 8462 8463 return SDValue(); 8464} 8465 8466/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 8467SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0, 8468 SDValue N1, ISD::CondCode Cond, 8469 DebugLoc DL, bool foldBooleans) { 8470 TargetLowering::DAGCombinerInfo 8471 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 8472 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL); 8473} 8474 8475/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 8476/// return a DAG expression to select that will generate the same value by 8477/// multiplying by a magic number. See: 8478/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 8479SDValue DAGCombiner::BuildSDIV(SDNode *N) { 8480 std::vector<SDNode*> Built; 8481 SDValue S = TLI.BuildSDIV(N, DAG, LegalOperations, &Built); 8482 8483 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 8484 ii != ee; ++ii) 8485 AddToWorkList(*ii); 8486 return S; 8487} 8488 8489/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 8490/// return a DAG expression to select that will generate the same value by 8491/// multiplying by a magic number. See: 8492/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 8493SDValue DAGCombiner::BuildUDIV(SDNode *N) { 8494 std::vector<SDNode*> Built; 8495 SDValue S = TLI.BuildUDIV(N, DAG, LegalOperations, &Built); 8496 8497 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 8498 ii != ee; ++ii) 8499 AddToWorkList(*ii); 8500 return S; 8501} 8502 8503/// FindBaseOffset - Return true if base is a frame index, which is known not 8504// to alias with anything but itself. Provides base object and offset as 8505// results. 8506static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset, 8507 const GlobalValue *&GV, void *&CV) { 8508 // Assume it is a primitive operation. 8509 Base = Ptr; Offset = 0; GV = 0; CV = 0; 8510 8511 // If it's an adding a simple constant then integrate the offset. 8512 if (Base.getOpcode() == ISD::ADD) { 8513 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 8514 Base = Base.getOperand(0); 8515 Offset += C->getZExtValue(); 8516 } 8517 } 8518 8519 // Return the underlying GlobalValue, and update the Offset. Return false 8520 // for GlobalAddressSDNode since the same GlobalAddress may be represented 8521 // by multiple nodes with different offsets. 8522 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) { 8523 GV = G->getGlobal(); 8524 Offset += G->getOffset(); 8525 return false; 8526 } 8527 8528 // Return the underlying Constant value, and update the Offset. Return false 8529 // for ConstantSDNodes since the same constant pool entry may be represented 8530 // by multiple nodes with different offsets. 8531 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) { 8532 CV = C->isMachineConstantPoolEntry() ? (void *)C->getMachineCPVal() 8533 : (void *)C->getConstVal(); 8534 Offset += C->getOffset(); 8535 return false; 8536 } 8537 // If it's any of the following then it can't alias with anything but itself. 8538 return isa<FrameIndexSDNode>(Base); 8539} 8540 8541/// isAlias - Return true if there is any possibility that the two addresses 8542/// overlap. 8543bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, 8544 const Value *SrcValue1, int SrcValueOffset1, 8545 unsigned SrcValueAlign1, 8546 const MDNode *TBAAInfo1, 8547 SDValue Ptr2, int64_t Size2, 8548 const Value *SrcValue2, int SrcValueOffset2, 8549 unsigned SrcValueAlign2, 8550 const MDNode *TBAAInfo2) const { 8551 // If they are the same then they must be aliases. 8552 if (Ptr1 == Ptr2) return true; 8553 8554 // Gather base node and offset information. 8555 SDValue Base1, Base2; 8556 int64_t Offset1, Offset2; 8557 const GlobalValue *GV1, *GV2; 8558 void *CV1, *CV2; 8559 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1); 8560 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2); 8561 8562 // If they have a same base address then check to see if they overlap. 8563 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2))) 8564 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 8565 8566 // It is possible for different frame indices to alias each other, mostly 8567 // when tail call optimization reuses return address slots for arguments. 8568 // To catch this case, look up the actual index of frame indices to compute 8569 // the real alias relationship. 8570 if (isFrameIndex1 && isFrameIndex2) { 8571 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 8572 Offset1 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base1)->getIndex()); 8573 Offset2 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base2)->getIndex()); 8574 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 8575 } 8576 8577 // Otherwise, if we know what the bases are, and they aren't identical, then 8578 // we know they cannot alias. 8579 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2)) 8580 return false; 8581 8582 // If we know required SrcValue1 and SrcValue2 have relatively large alignment 8583 // compared to the size and offset of the access, we may be able to prove they 8584 // do not alias. This check is conservative for now to catch cases created by 8585 // splitting vector types. 8586 if ((SrcValueAlign1 == SrcValueAlign2) && 8587 (SrcValueOffset1 != SrcValueOffset2) && 8588 (Size1 == Size2) && (SrcValueAlign1 > Size1)) { 8589 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1; 8590 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1; 8591 8592 // There is no overlap between these relatively aligned accesses of similar 8593 // size, return no alias. 8594 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1) 8595 return false; 8596 } 8597 8598 if (CombinerGlobalAA) { 8599 // Use alias analysis information. 8600 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 8601 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 8602 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 8603 AliasAnalysis::AliasResult AAResult = 8604 AA.alias(AliasAnalysis::Location(SrcValue1, Overlap1, TBAAInfo1), 8605 AliasAnalysis::Location(SrcValue2, Overlap2, TBAAInfo2)); 8606 if (AAResult == AliasAnalysis::NoAlias) 8607 return false; 8608 } 8609 8610 // Otherwise we have to assume they alias. 8611 return true; 8612} 8613 8614/// FindAliasInfo - Extracts the relevant alias information from the memory 8615/// node. Returns true if the operand was a load. 8616bool DAGCombiner::FindAliasInfo(SDNode *N, 8617 SDValue &Ptr, int64_t &Size, 8618 const Value *&SrcValue, 8619 int &SrcValueOffset, 8620 unsigned &SrcValueAlign, 8621 const MDNode *&TBAAInfo) const { 8622 LSBaseSDNode *LS = cast<LSBaseSDNode>(N); 8623 8624 Ptr = LS->getBasePtr(); 8625 Size = LS->getMemoryVT().getSizeInBits() >> 3; 8626 SrcValue = LS->getSrcValue(); 8627 SrcValueOffset = LS->getSrcValueOffset(); 8628 SrcValueAlign = LS->getOriginalAlignment(); 8629 TBAAInfo = LS->getTBAAInfo(); 8630 return isa<LoadSDNode>(LS); 8631} 8632 8633/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 8634/// looking for aliasing nodes and adding them to the Aliases vector. 8635void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 8636 SmallVector<SDValue, 8> &Aliases) { 8637 SmallVector<SDValue, 8> Chains; // List of chains to visit. 8638 SmallPtrSet<SDNode *, 16> Visited; // Visited node set. 8639 8640 // Get alias information for node. 8641 SDValue Ptr; 8642 int64_t Size; 8643 const Value *SrcValue; 8644 int SrcValueOffset; 8645 unsigned SrcValueAlign; 8646 const MDNode *SrcTBAAInfo; 8647 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset, 8648 SrcValueAlign, SrcTBAAInfo); 8649 8650 // Starting off. 8651 Chains.push_back(OriginalChain); 8652 unsigned Depth = 0; 8653 8654 // Look at each chain and determine if it is an alias. If so, add it to the 8655 // aliases list. If not, then continue up the chain looking for the next 8656 // candidate. 8657 while (!Chains.empty()) { 8658 SDValue Chain = Chains.back(); 8659 Chains.pop_back(); 8660 8661 // For TokenFactor nodes, look at each operand and only continue up the 8662 // chain until we find two aliases. If we've seen two aliases, assume we'll 8663 // find more and revert to original chain since the xform is unlikely to be 8664 // profitable. 8665 // 8666 // FIXME: The depth check could be made to return the last non-aliasing 8667 // chain we found before we hit a tokenfactor rather than the original 8668 // chain. 8669 if (Depth > 6 || Aliases.size() == 2) { 8670 Aliases.clear(); 8671 Aliases.push_back(OriginalChain); 8672 break; 8673 } 8674 8675 // Don't bother if we've been before. 8676 if (!Visited.insert(Chain.getNode())) 8677 continue; 8678 8679 switch (Chain.getOpcode()) { 8680 case ISD::EntryToken: 8681 // Entry token is ideal chain operand, but handled in FindBetterChain. 8682 break; 8683 8684 case ISD::LOAD: 8685 case ISD::STORE: { 8686 // Get alias information for Chain. 8687 SDValue OpPtr; 8688 int64_t OpSize; 8689 const Value *OpSrcValue; 8690 int OpSrcValueOffset; 8691 unsigned OpSrcValueAlign; 8692 const MDNode *OpSrcTBAAInfo; 8693 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, 8694 OpSrcValue, OpSrcValueOffset, 8695 OpSrcValueAlign, 8696 OpSrcTBAAInfo); 8697 8698 // If chain is alias then stop here. 8699 if (!(IsLoad && IsOpLoad) && 8700 isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign, 8701 SrcTBAAInfo, 8702 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset, 8703 OpSrcValueAlign, OpSrcTBAAInfo)) { 8704 Aliases.push_back(Chain); 8705 } else { 8706 // Look further up the chain. 8707 Chains.push_back(Chain.getOperand(0)); 8708 ++Depth; 8709 } 8710 break; 8711 } 8712 8713 case ISD::TokenFactor: 8714 // We have to check each of the operands of the token factor for "small" 8715 // token factors, so we queue them up. Adding the operands to the queue 8716 // (stack) in reverse order maintains the original order and increases the 8717 // likelihood that getNode will find a matching token factor (CSE.) 8718 if (Chain.getNumOperands() > 16) { 8719 Aliases.push_back(Chain); 8720 break; 8721 } 8722 for (unsigned n = Chain.getNumOperands(); n;) 8723 Chains.push_back(Chain.getOperand(--n)); 8724 ++Depth; 8725 break; 8726 8727 default: 8728 // For all other instructions we will just have to take what we can get. 8729 Aliases.push_back(Chain); 8730 break; 8731 } 8732 } 8733} 8734 8735/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 8736/// for a better chain (aliasing node.) 8737SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 8738 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 8739 8740 // Accumulate all the aliases to this node. 8741 GatherAllAliases(N, OldChain, Aliases); 8742 8743 // If no operands then chain to entry token. 8744 if (Aliases.size() == 0) 8745 return DAG.getEntryNode(); 8746 8747 // If a single operand then chain to it. We don't need to revisit it. 8748 if (Aliases.size() == 1) 8749 return Aliases[0]; 8750 8751 // Construct a custom tailored token factor. 8752 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 8753 &Aliases[0], Aliases.size()); 8754} 8755 8756// SelectionDAG::Combine - This is the entry point for the file. 8757// 8758void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, 8759 CodeGenOpt::Level OptLevel) { 8760 /// run - This is the main entry point to this class. 8761 /// 8762 DAGCombiner(*this, AA, OptLevel).Run(Level); 8763} 8764