DAGCombiner.cpp revision ff00a555171cac0a77c0434fd85ff5a0ae672ade
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// This pass is not a substitute for the LLVM IR instcombine pass. This pass is 14// primarily intended to handle simplification opportunities that are implicit 15// in the LLVM IR and exposed by the various codegen lowering phases. 16// 17//===----------------------------------------------------------------------===// 18 19#define DEBUG_TYPE "dagcombine" 20#include "llvm/CodeGen/SelectionDAG.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/LLVMContext.h" 23#include "llvm/CodeGen/MachineFunction.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/PseudoSourceValue.h" 26#include "llvm/Analysis/AliasAnalysis.h" 27#include "llvm/Target/TargetData.h" 28#include "llvm/Target/TargetFrameInfo.h" 29#include "llvm/Target/TargetLowering.h" 30#include "llvm/Target/TargetMachine.h" 31#include "llvm/Target/TargetOptions.h" 32#include "llvm/ADT/SmallPtrSet.h" 33#include "llvm/ADT/Statistic.h" 34#include "llvm/Support/CommandLine.h" 35#include "llvm/Support/Debug.h" 36#include "llvm/Support/ErrorHandling.h" 37#include "llvm/Support/MathExtras.h" 38#include "llvm/Support/raw_ostream.h" 39#include <algorithm> 40using namespace llvm; 41 42STATISTIC(NodesCombined , "Number of dag nodes combined"); 43STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 44STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 45STATISTIC(OpsNarrowed , "Number of load/op/store narrowed"); 46 47namespace { 48 static cl::opt<bool> 49 CombinerAA("combiner-alias-analysis", cl::Hidden, 50 cl::desc("Turn on alias analysis during testing")); 51 52 static cl::opt<bool> 53 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 54 cl::desc("Include global information in alias analysis")); 55 56//------------------------------ DAGCombiner ---------------------------------// 57 58 class DAGCombiner { 59 SelectionDAG &DAG; 60 const TargetLowering &TLI; 61 CombineLevel Level; 62 CodeGenOpt::Level OptLevel; 63 bool LegalOperations; 64 bool LegalTypes; 65 66 // Worklist of all of the nodes that need to be simplified. 67 std::vector<SDNode*> WorkList; 68 69 // AA - Used for DAG load/store alias analysis. 70 AliasAnalysis &AA; 71 72 /// AddUsersToWorkList - When an instruction is simplified, add all users of 73 /// the instruction to the work lists because they might get more simplified 74 /// now. 75 /// 76 void AddUsersToWorkList(SDNode *N) { 77 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 78 UI != UE; ++UI) 79 AddToWorkList(*UI); 80 } 81 82 /// visit - call the node-specific routine that knows how to fold each 83 /// particular type of node. 84 SDValue visit(SDNode *N); 85 86 public: 87 /// AddToWorkList - Add to the work list making sure it's instance is at the 88 /// the back (next to be processed.) 89 void AddToWorkList(SDNode *N) { 90 removeFromWorkList(N); 91 WorkList.push_back(N); 92 } 93 94 /// removeFromWorkList - remove all instances of N from the worklist. 95 /// 96 void removeFromWorkList(SDNode *N) { 97 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 98 WorkList.end()); 99 } 100 101 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 102 bool AddTo = true); 103 104 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 105 return CombineTo(N, &Res, 1, AddTo); 106 } 107 108 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 109 bool AddTo = true) { 110 SDValue To[] = { Res0, Res1 }; 111 return CombineTo(N, To, 2, AddTo); 112 } 113 114 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO); 115 116 private: 117 118 /// SimplifyDemandedBits - Check the specified integer node value to see if 119 /// it can be simplified or if things it uses can be simplified by bit 120 /// propagation. If so, return true. 121 bool SimplifyDemandedBits(SDValue Op) { 122 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits(); 123 APInt Demanded = APInt::getAllOnesValue(BitWidth); 124 return SimplifyDemandedBits(Op, Demanded); 125 } 126 127 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 128 129 bool CombineToPreIndexedLoadStore(SDNode *N); 130 bool CombineToPostIndexedLoadStore(SDNode *N); 131 132 133 /// combine - call the node-specific routine that knows how to fold each 134 /// particular type of node. If that doesn't do anything, try the 135 /// target-specific DAG combines. 136 SDValue combine(SDNode *N); 137 138 // Visitation implementation - Implement dag node combining for different 139 // node types. The semantics are as follows: 140 // Return Value: 141 // SDValue.getNode() == 0 - No change was made 142 // SDValue.getNode() == N - N was replaced, is dead and has been handled. 143 // otherwise - N should be replaced by the returned Operand. 144 // 145 SDValue visitTokenFactor(SDNode *N); 146 SDValue visitMERGE_VALUES(SDNode *N); 147 SDValue visitADD(SDNode *N); 148 SDValue visitSUB(SDNode *N); 149 SDValue visitADDC(SDNode *N); 150 SDValue visitADDE(SDNode *N); 151 SDValue visitMUL(SDNode *N); 152 SDValue visitSDIV(SDNode *N); 153 SDValue visitUDIV(SDNode *N); 154 SDValue visitSREM(SDNode *N); 155 SDValue visitUREM(SDNode *N); 156 SDValue visitMULHU(SDNode *N); 157 SDValue visitMULHS(SDNode *N); 158 SDValue visitSMUL_LOHI(SDNode *N); 159 SDValue visitUMUL_LOHI(SDNode *N); 160 SDValue visitSDIVREM(SDNode *N); 161 SDValue visitUDIVREM(SDNode *N); 162 SDValue visitAND(SDNode *N); 163 SDValue visitOR(SDNode *N); 164 SDValue visitXOR(SDNode *N); 165 SDValue SimplifyVBinOp(SDNode *N); 166 SDValue visitSHL(SDNode *N); 167 SDValue visitSRA(SDNode *N); 168 SDValue visitSRL(SDNode *N); 169 SDValue visitCTLZ(SDNode *N); 170 SDValue visitCTTZ(SDNode *N); 171 SDValue visitCTPOP(SDNode *N); 172 SDValue visitSELECT(SDNode *N); 173 SDValue visitSELECT_CC(SDNode *N); 174 SDValue visitSETCC(SDNode *N); 175 SDValue visitSIGN_EXTEND(SDNode *N); 176 SDValue visitZERO_EXTEND(SDNode *N); 177 SDValue visitANY_EXTEND(SDNode *N); 178 SDValue visitSIGN_EXTEND_INREG(SDNode *N); 179 SDValue visitTRUNCATE(SDNode *N); 180 SDValue visitBIT_CONVERT(SDNode *N); 181 SDValue visitBUILD_PAIR(SDNode *N); 182 SDValue visitFADD(SDNode *N); 183 SDValue visitFSUB(SDNode *N); 184 SDValue visitFMUL(SDNode *N); 185 SDValue visitFDIV(SDNode *N); 186 SDValue visitFREM(SDNode *N); 187 SDValue visitFCOPYSIGN(SDNode *N); 188 SDValue visitSINT_TO_FP(SDNode *N); 189 SDValue visitUINT_TO_FP(SDNode *N); 190 SDValue visitFP_TO_SINT(SDNode *N); 191 SDValue visitFP_TO_UINT(SDNode *N); 192 SDValue visitFP_ROUND(SDNode *N); 193 SDValue visitFP_ROUND_INREG(SDNode *N); 194 SDValue visitFP_EXTEND(SDNode *N); 195 SDValue visitFNEG(SDNode *N); 196 SDValue visitFABS(SDNode *N); 197 SDValue visitBRCOND(SDNode *N); 198 SDValue visitBR_CC(SDNode *N); 199 SDValue visitLOAD(SDNode *N); 200 SDValue visitSTORE(SDNode *N); 201 SDValue visitINSERT_VECTOR_ELT(SDNode *N); 202 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 203 SDValue visitBUILD_VECTOR(SDNode *N); 204 SDValue visitCONCAT_VECTORS(SDNode *N); 205 SDValue visitVECTOR_SHUFFLE(SDNode *N); 206 207 SDValue XformToShuffleWithZero(SDNode *N); 208 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS); 209 210 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 211 212 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 213 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 214 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2); 215 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2, 216 SDValue N3, ISD::CondCode CC, 217 bool NotExtCompare = false); 218 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 219 DebugLoc DL, bool foldBooleans = true); 220 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 221 unsigned HiOp); 222 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT); 223 SDValue ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, EVT); 224 SDValue BuildSDIV(SDNode *N); 225 SDValue BuildUDIV(SDNode *N); 226 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL); 227 SDValue ReduceLoadWidth(SDNode *N); 228 SDValue ReduceLoadOpStoreWidth(SDNode *N); 229 230 SDValue GetDemandedBits(SDValue V, const APInt &Mask); 231 232 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 233 /// looking for aliasing nodes and adding them to the Aliases vector. 234 void GatherAllAliases(SDNode *N, SDValue OriginalChain, 235 SmallVector<SDValue, 8> &Aliases); 236 237 /// isAlias - Return true if there is any possibility that the two addresses 238 /// overlap. 239 bool isAlias(SDValue Ptr1, int64_t Size1, 240 const Value *SrcValue1, int SrcValueOffset1, 241 unsigned SrcValueAlign1, 242 SDValue Ptr2, int64_t Size2, 243 const Value *SrcValue2, int SrcValueOffset2, 244 unsigned SrcValueAlign2) const; 245 246 /// FindAliasInfo - Extracts the relevant alias information from the memory 247 /// node. Returns true if the operand was a load. 248 bool FindAliasInfo(SDNode *N, 249 SDValue &Ptr, int64_t &Size, 250 const Value *&SrcValue, int &SrcValueOffset, 251 unsigned &SrcValueAlignment) const; 252 253 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 254 /// looking for a better chain (aliasing node.) 255 SDValue FindBetterChain(SDNode *N, SDValue Chain); 256 257 /// getShiftAmountTy - Returns a type large enough to hold any valid 258 /// shift amount - before type legalization these can be huge. 259 EVT getShiftAmountTy() { 260 return LegalTypes ? TLI.getShiftAmountTy() : TLI.getPointerTy(); 261 } 262 263public: 264 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL) 265 : DAG(D), 266 TLI(D.getTargetLoweringInfo()), 267 Level(Unrestricted), 268 OptLevel(OL), 269 LegalOperations(false), 270 LegalTypes(false), 271 AA(A) {} 272 273 /// Run - runs the dag combiner on all nodes in the work list 274 void Run(CombineLevel AtLevel); 275 }; 276} 277 278 279namespace { 280/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 281/// nodes from the worklist. 282class WorkListRemover : public SelectionDAG::DAGUpdateListener { 283 DAGCombiner &DC; 284public: 285 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {} 286 287 virtual void NodeDeleted(SDNode *N, SDNode *E) { 288 DC.removeFromWorkList(N); 289 } 290 291 virtual void NodeUpdated(SDNode *N) { 292 // Ignore updates. 293 } 294}; 295} 296 297//===----------------------------------------------------------------------===// 298// TargetLowering::DAGCombinerInfo implementation 299//===----------------------------------------------------------------------===// 300 301void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 302 ((DAGCombiner*)DC)->AddToWorkList(N); 303} 304 305SDValue TargetLowering::DAGCombinerInfo:: 306CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) { 307 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo); 308} 309 310SDValue TargetLowering::DAGCombinerInfo:: 311CombineTo(SDNode *N, SDValue Res, bool AddTo) { 312 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo); 313} 314 315 316SDValue TargetLowering::DAGCombinerInfo:: 317CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) { 318 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo); 319} 320 321void TargetLowering::DAGCombinerInfo:: 322CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 323 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO); 324} 325 326//===----------------------------------------------------------------------===// 327// Helper Functions 328//===----------------------------------------------------------------------===// 329 330/// isNegatibleForFree - Return 1 if we can compute the negated form of the 331/// specified expression for the same cost as the expression itself, or 2 if we 332/// can compute the negated form more cheaply than the expression itself. 333static char isNegatibleForFree(SDValue Op, bool LegalOperations, 334 unsigned Depth = 0) { 335 // No compile time optimizations on this type. 336 if (Op.getValueType() == MVT::ppcf128) 337 return 0; 338 339 // fneg is removable even if it has multiple uses. 340 if (Op.getOpcode() == ISD::FNEG) return 2; 341 342 // Don't allow anything with multiple uses. 343 if (!Op.hasOneUse()) return 0; 344 345 // Don't recurse exponentially. 346 if (Depth > 6) return 0; 347 348 switch (Op.getOpcode()) { 349 default: return false; 350 case ISD::ConstantFP: 351 // Don't invert constant FP values after legalize. The negated constant 352 // isn't necessarily legal. 353 return LegalOperations ? 0 : 1; 354 case ISD::FADD: 355 // FIXME: determine better conditions for this xform. 356 if (!UnsafeFPMath) return 0; 357 358 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B) 359 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 360 return V; 361 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 362 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 363 case ISD::FSUB: 364 // We can't turn -(A-B) into B-A when we honor signed zeros. 365 if (!UnsafeFPMath) return 0; 366 367 // fold (fneg (fsub A, B)) -> (fsub B, A) 368 return 1; 369 370 case ISD::FMUL: 371 case ISD::FDIV: 372 if (HonorSignDependentRoundingFPMath()) return 0; 373 374 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y)) 375 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 376 return V; 377 378 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 379 380 case ISD::FP_EXTEND: 381 case ISD::FP_ROUND: 382 case ISD::FSIN: 383 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1); 384 } 385} 386 387/// GetNegatedExpression - If isNegatibleForFree returns true, this function 388/// returns the newly negated expression. 389static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 390 bool LegalOperations, unsigned Depth = 0) { 391 // fneg is removable even if it has multiple uses. 392 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 393 394 // Don't allow anything with multiple uses. 395 assert(Op.hasOneUse() && "Unknown reuse!"); 396 397 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 398 switch (Op.getOpcode()) { 399 default: llvm_unreachable("Unknown code"); 400 case ISD::ConstantFP: { 401 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 402 V.changeSign(); 403 return DAG.getConstantFP(V, Op.getValueType()); 404 } 405 case ISD::FADD: 406 // FIXME: determine better conditions for this xform. 407 assert(UnsafeFPMath); 408 409 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 410 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 411 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 412 GetNegatedExpression(Op.getOperand(0), DAG, 413 LegalOperations, Depth+1), 414 Op.getOperand(1)); 415 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 416 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 417 GetNegatedExpression(Op.getOperand(1), DAG, 418 LegalOperations, Depth+1), 419 Op.getOperand(0)); 420 case ISD::FSUB: 421 // We can't turn -(A-B) into B-A when we honor signed zeros. 422 assert(UnsafeFPMath); 423 424 // fold (fneg (fsub 0, B)) -> B 425 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 426 if (N0CFP->getValueAPF().isZero()) 427 return Op.getOperand(1); 428 429 // fold (fneg (fsub A, B)) -> (fsub B, A) 430 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 431 Op.getOperand(1), Op.getOperand(0)); 432 433 case ISD::FMUL: 434 case ISD::FDIV: 435 assert(!HonorSignDependentRoundingFPMath()); 436 437 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) 438 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 439 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 440 GetNegatedExpression(Op.getOperand(0), DAG, 441 LegalOperations, Depth+1), 442 Op.getOperand(1)); 443 444 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y)) 445 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 446 Op.getOperand(0), 447 GetNegatedExpression(Op.getOperand(1), DAG, 448 LegalOperations, Depth+1)); 449 450 case ISD::FP_EXTEND: 451 case ISD::FSIN: 452 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 453 GetNegatedExpression(Op.getOperand(0), DAG, 454 LegalOperations, Depth+1)); 455 case ISD::FP_ROUND: 456 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(), 457 GetNegatedExpression(Op.getOperand(0), DAG, 458 LegalOperations, Depth+1), 459 Op.getOperand(1)); 460 } 461} 462 463 464// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 465// that selects between the values 1 and 0, making it equivalent to a setcc. 466// Also, set the incoming LHS, RHS, and CC references to the appropriate 467// nodes based on the type of node we are checking. This simplifies life a 468// bit for the callers. 469static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 470 SDValue &CC) { 471 if (N.getOpcode() == ISD::SETCC) { 472 LHS = N.getOperand(0); 473 RHS = N.getOperand(1); 474 CC = N.getOperand(2); 475 return true; 476 } 477 if (N.getOpcode() == ISD::SELECT_CC && 478 N.getOperand(2).getOpcode() == ISD::Constant && 479 N.getOperand(3).getOpcode() == ISD::Constant && 480 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 481 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 482 LHS = N.getOperand(0); 483 RHS = N.getOperand(1); 484 CC = N.getOperand(4); 485 return true; 486 } 487 return false; 488} 489 490// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 491// one use. If this is true, it allows the users to invert the operation for 492// free when it is profitable to do so. 493static bool isOneUseSetCC(SDValue N) { 494 SDValue N0, N1, N2; 495 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 496 return true; 497 return false; 498} 499 500SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL, 501 SDValue N0, SDValue N1) { 502 EVT VT = N0.getValueType(); 503 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 504 if (isa<ConstantSDNode>(N1)) { 505 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 506 SDValue OpNode = 507 DAG.FoldConstantArithmetic(Opc, VT, 508 cast<ConstantSDNode>(N0.getOperand(1)), 509 cast<ConstantSDNode>(N1)); 510 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode); 511 } else if (N0.hasOneUse()) { 512 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 513 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 514 N0.getOperand(0), N1); 515 AddToWorkList(OpNode.getNode()); 516 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1)); 517 } 518 } 519 520 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 521 if (isa<ConstantSDNode>(N0)) { 522 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 523 SDValue OpNode = 524 DAG.FoldConstantArithmetic(Opc, VT, 525 cast<ConstantSDNode>(N1.getOperand(1)), 526 cast<ConstantSDNode>(N0)); 527 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode); 528 } else if (N1.hasOneUse()) { 529 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 530 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 531 N1.getOperand(0), N0); 532 AddToWorkList(OpNode.getNode()); 533 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1)); 534 } 535 } 536 537 return SDValue(); 538} 539 540SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 541 bool AddTo) { 542 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 543 ++NodesCombined; 544 DEBUG(dbgs() << "\nReplacing.1 "; 545 N->dump(&DAG); 546 dbgs() << "\nWith: "; 547 To[0].getNode()->dump(&DAG); 548 dbgs() << " and " << NumTo-1 << " other values\n"; 549 for (unsigned i = 0, e = NumTo; i != e; ++i) 550 assert((!To[i].getNode() || 551 N->getValueType(i) == To[i].getValueType()) && 552 "Cannot combine value to value of different type!")); 553 WorkListRemover DeadNodes(*this); 554 DAG.ReplaceAllUsesWith(N, To, &DeadNodes); 555 556 if (AddTo) { 557 // Push the new nodes and any users onto the worklist 558 for (unsigned i = 0, e = NumTo; i != e; ++i) { 559 if (To[i].getNode()) { 560 AddToWorkList(To[i].getNode()); 561 AddUsersToWorkList(To[i].getNode()); 562 } 563 } 564 } 565 566 // Finally, if the node is now dead, remove it from the graph. The node 567 // may not be dead if the replacement process recursively simplified to 568 // something else needing this node. 569 if (N->use_empty()) { 570 // Nodes can be reintroduced into the worklist. Make sure we do not 571 // process a node that has been replaced. 572 removeFromWorkList(N); 573 574 // Finally, since the node is now dead, remove it from the graph. 575 DAG.DeleteNode(N); 576 } 577 return SDValue(N, 0); 578} 579 580void 581DAGCombiner::CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt & 582 TLO) { 583 // Replace all uses. If any nodes become isomorphic to other nodes and 584 // are deleted, make sure to remove them from our worklist. 585 WorkListRemover DeadNodes(*this); 586 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 587 588 // Push the new node and any (possibly new) users onto the worklist. 589 AddToWorkList(TLO.New.getNode()); 590 AddUsersToWorkList(TLO.New.getNode()); 591 592 // Finally, if the node is now dead, remove it from the graph. The node 593 // may not be dead if the replacement process recursively simplified to 594 // something else needing this node. 595 if (TLO.Old.getNode()->use_empty()) { 596 removeFromWorkList(TLO.Old.getNode()); 597 598 // If the operands of this node are only used by the node, they will now 599 // be dead. Make sure to visit them first to delete dead nodes early. 600 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i) 601 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse()) 602 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode()); 603 604 DAG.DeleteNode(TLO.Old.getNode()); 605 } 606} 607 608/// SimplifyDemandedBits - Check the specified integer node value to see if 609/// it can be simplified or if things it uses can be simplified by bit 610/// propagation. If so, return true. 611bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 612 TargetLowering::TargetLoweringOpt TLO(DAG); 613 APInt KnownZero, KnownOne; 614 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 615 return false; 616 617 // Revisit the node. 618 AddToWorkList(Op.getNode()); 619 620 // Replace the old value with the new one. 621 ++NodesCombined; 622 DEBUG(dbgs() << "\nReplacing.2 "; 623 TLO.Old.getNode()->dump(&DAG); 624 dbgs() << "\nWith: "; 625 TLO.New.getNode()->dump(&DAG); 626 dbgs() << '\n'); 627 628 CommitTargetLoweringOpt(TLO); 629 return true; 630} 631 632//===----------------------------------------------------------------------===// 633// Main DAG Combiner implementation 634//===----------------------------------------------------------------------===// 635 636void DAGCombiner::Run(CombineLevel AtLevel) { 637 // set the instance variables, so that the various visit routines may use it. 638 Level = AtLevel; 639 LegalOperations = Level >= NoIllegalOperations; 640 LegalTypes = Level >= NoIllegalTypes; 641 642 // Add all the dag nodes to the worklist. 643 WorkList.reserve(DAG.allnodes_size()); 644 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 645 E = DAG.allnodes_end(); I != E; ++I) 646 WorkList.push_back(I); 647 648 // Create a dummy node (which is not added to allnodes), that adds a reference 649 // to the root node, preventing it from being deleted, and tracking any 650 // changes of the root. 651 HandleSDNode Dummy(DAG.getRoot()); 652 653 // The root of the dag may dangle to deleted nodes until the dag combiner is 654 // done. Set it to null to avoid confusion. 655 DAG.setRoot(SDValue()); 656 657 // while the worklist isn't empty, inspect the node on the end of it and 658 // try and combine it. 659 while (!WorkList.empty()) { 660 SDNode *N = WorkList.back(); 661 WorkList.pop_back(); 662 663 // If N has no uses, it is dead. Make sure to revisit all N's operands once 664 // N is deleted from the DAG, since they too may now be dead or may have a 665 // reduced number of uses, allowing other xforms. 666 if (N->use_empty() && N != &Dummy) { 667 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 668 AddToWorkList(N->getOperand(i).getNode()); 669 670 DAG.DeleteNode(N); 671 continue; 672 } 673 674 SDValue RV = combine(N); 675 676 if (RV.getNode() == 0) 677 continue; 678 679 ++NodesCombined; 680 681 // If we get back the same node we passed in, rather than a new node or 682 // zero, we know that the node must have defined multiple values and 683 // CombineTo was used. Since CombineTo takes care of the worklist 684 // mechanics for us, we have no work to do in this case. 685 if (RV.getNode() == N) 686 continue; 687 688 assert(N->getOpcode() != ISD::DELETED_NODE && 689 RV.getNode()->getOpcode() != ISD::DELETED_NODE && 690 "Node was deleted but visit returned new node!"); 691 692 DEBUG(dbgs() << "\nReplacing.3 "; 693 N->dump(&DAG); 694 dbgs() << "\nWith: "; 695 RV.getNode()->dump(&DAG); 696 dbgs() << '\n'); 697 WorkListRemover DeadNodes(*this); 698 if (N->getNumValues() == RV.getNode()->getNumValues()) 699 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes); 700 else { 701 assert(N->getValueType(0) == RV.getValueType() && 702 N->getNumValues() == 1 && "Type mismatch"); 703 SDValue OpV = RV; 704 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes); 705 } 706 707 // Push the new node and any users onto the worklist 708 AddToWorkList(RV.getNode()); 709 AddUsersToWorkList(RV.getNode()); 710 711 // Add any uses of the old node to the worklist in case this node is the 712 // last one that uses them. They may become dead after this node is 713 // deleted. 714 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 715 AddToWorkList(N->getOperand(i).getNode()); 716 717 // Finally, if the node is now dead, remove it from the graph. The node 718 // may not be dead if the replacement process recursively simplified to 719 // something else needing this node. 720 if (N->use_empty()) { 721 // Nodes can be reintroduced into the worklist. Make sure we do not 722 // process a node that has been replaced. 723 removeFromWorkList(N); 724 725 // Finally, since the node is now dead, remove it from the graph. 726 DAG.DeleteNode(N); 727 } 728 } 729 730 // If the root changed (e.g. it was a dead load, update the root). 731 DAG.setRoot(Dummy.getValue()); 732} 733 734SDValue DAGCombiner::visit(SDNode *N) { 735 switch(N->getOpcode()) { 736 default: break; 737 case ISD::TokenFactor: return visitTokenFactor(N); 738 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 739 case ISD::ADD: return visitADD(N); 740 case ISD::SUB: return visitSUB(N); 741 case ISD::ADDC: return visitADDC(N); 742 case ISD::ADDE: return visitADDE(N); 743 case ISD::MUL: return visitMUL(N); 744 case ISD::SDIV: return visitSDIV(N); 745 case ISD::UDIV: return visitUDIV(N); 746 case ISD::SREM: return visitSREM(N); 747 case ISD::UREM: return visitUREM(N); 748 case ISD::MULHU: return visitMULHU(N); 749 case ISD::MULHS: return visitMULHS(N); 750 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 751 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 752 case ISD::SDIVREM: return visitSDIVREM(N); 753 case ISD::UDIVREM: return visitUDIVREM(N); 754 case ISD::AND: return visitAND(N); 755 case ISD::OR: return visitOR(N); 756 case ISD::XOR: return visitXOR(N); 757 case ISD::SHL: return visitSHL(N); 758 case ISD::SRA: return visitSRA(N); 759 case ISD::SRL: return visitSRL(N); 760 case ISD::CTLZ: return visitCTLZ(N); 761 case ISD::CTTZ: return visitCTTZ(N); 762 case ISD::CTPOP: return visitCTPOP(N); 763 case ISD::SELECT: return visitSELECT(N); 764 case ISD::SELECT_CC: return visitSELECT_CC(N); 765 case ISD::SETCC: return visitSETCC(N); 766 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 767 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 768 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 769 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 770 case ISD::TRUNCATE: return visitTRUNCATE(N); 771 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 772 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 773 case ISD::FADD: return visitFADD(N); 774 case ISD::FSUB: return visitFSUB(N); 775 case ISD::FMUL: return visitFMUL(N); 776 case ISD::FDIV: return visitFDIV(N); 777 case ISD::FREM: return visitFREM(N); 778 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 779 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 780 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 781 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 782 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 783 case ISD::FP_ROUND: return visitFP_ROUND(N); 784 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 785 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 786 case ISD::FNEG: return visitFNEG(N); 787 case ISD::FABS: return visitFABS(N); 788 case ISD::BRCOND: return visitBRCOND(N); 789 case ISD::BR_CC: return visitBR_CC(N); 790 case ISD::LOAD: return visitLOAD(N); 791 case ISD::STORE: return visitSTORE(N); 792 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 793 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 794 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 795 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 796 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 797 } 798 return SDValue(); 799} 800 801SDValue DAGCombiner::combine(SDNode *N) { 802 SDValue RV = visit(N); 803 804 // If nothing happened, try a target-specific DAG combine. 805 if (RV.getNode() == 0) { 806 assert(N->getOpcode() != ISD::DELETED_NODE && 807 "Node was deleted but visit returned NULL!"); 808 809 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 810 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 811 812 // Expose the DAG combiner to the target combiner impls. 813 TargetLowering::DAGCombinerInfo 814 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 815 816 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 817 } 818 } 819 820 // If N is a commutative binary node, try commuting it to enable more 821 // sdisel CSE. 822 if (RV.getNode() == 0 && 823 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 824 N->getNumValues() == 1) { 825 SDValue N0 = N->getOperand(0); 826 SDValue N1 = N->getOperand(1); 827 828 // Constant operands are canonicalized to RHS. 829 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 830 SDValue Ops[] = { N1, N0 }; 831 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 832 Ops, 2); 833 if (CSENode) 834 return SDValue(CSENode, 0); 835 } 836 } 837 838 return RV; 839} 840 841/// getInputChainForNode - Given a node, return its input chain if it has one, 842/// otherwise return a null sd operand. 843static SDValue getInputChainForNode(SDNode *N) { 844 if (unsigned NumOps = N->getNumOperands()) { 845 if (N->getOperand(0).getValueType() == MVT::Other) 846 return N->getOperand(0); 847 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 848 return N->getOperand(NumOps-1); 849 for (unsigned i = 1; i < NumOps-1; ++i) 850 if (N->getOperand(i).getValueType() == MVT::Other) 851 return N->getOperand(i); 852 } 853 return SDValue(); 854} 855 856SDValue DAGCombiner::visitTokenFactor(SDNode *N) { 857 // If N has two operands, where one has an input chain equal to the other, 858 // the 'other' chain is redundant. 859 if (N->getNumOperands() == 2) { 860 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) 861 return N->getOperand(0); 862 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) 863 return N->getOperand(1); 864 } 865 866 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 867 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 868 SmallPtrSet<SDNode*, 16> SeenOps; 869 bool Changed = false; // If we should replace this token factor. 870 871 // Start out with this token factor. 872 TFs.push_back(N); 873 874 // Iterate through token factors. The TFs grows when new token factors are 875 // encountered. 876 for (unsigned i = 0; i < TFs.size(); ++i) { 877 SDNode *TF = TFs[i]; 878 879 // Check each of the operands. 880 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 881 SDValue Op = TF->getOperand(i); 882 883 switch (Op.getOpcode()) { 884 case ISD::EntryToken: 885 // Entry tokens don't need to be added to the list. They are 886 // rededundant. 887 Changed = true; 888 break; 889 890 case ISD::TokenFactor: 891 if (Op.hasOneUse() && 892 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { 893 // Queue up for processing. 894 TFs.push_back(Op.getNode()); 895 // Clean up in case the token factor is removed. 896 AddToWorkList(Op.getNode()); 897 Changed = true; 898 break; 899 } 900 // Fall thru 901 902 default: 903 // Only add if it isn't already in the list. 904 if (SeenOps.insert(Op.getNode())) 905 Ops.push_back(Op); 906 else 907 Changed = true; 908 break; 909 } 910 } 911 } 912 913 SDValue Result; 914 915 // If we've change things around then replace token factor. 916 if (Changed) { 917 if (Ops.empty()) { 918 // The entry token is the only possible outcome. 919 Result = DAG.getEntryNode(); 920 } else { 921 // New and improved token factor. 922 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 923 MVT::Other, &Ops[0], Ops.size()); 924 } 925 926 // Don't add users to work list. 927 return CombineTo(N, Result, false); 928 } 929 930 return Result; 931} 932 933/// MERGE_VALUES can always be eliminated. 934SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 935 WorkListRemover DeadNodes(*this); 936 // Replacing results may cause a different MERGE_VALUES to suddenly 937 // be CSE'd with N, and carry its uses with it. Iterate until no 938 // uses remain, to ensure that the node can be safely deleted. 939 do { 940 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 941 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i), 942 &DeadNodes); 943 } while (!N->use_empty()); 944 removeFromWorkList(N); 945 DAG.DeleteNode(N); 946 return SDValue(N, 0); // Return N so it doesn't get rechecked! 947} 948 949static 950SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1, 951 SelectionDAG &DAG) { 952 EVT VT = N0.getValueType(); 953 SDValue N00 = N0.getOperand(0); 954 SDValue N01 = N0.getOperand(1); 955 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 956 957 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && 958 isa<ConstantSDNode>(N00.getOperand(1))) { 959 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 960 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, 961 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT, 962 N00.getOperand(0), N01), 963 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT, 964 N00.getOperand(1), N01)); 965 return DAG.getNode(ISD::ADD, DL, VT, N0, N1); 966 } 967 968 return SDValue(); 969} 970 971SDValue DAGCombiner::visitADD(SDNode *N) { 972 SDValue N0 = N->getOperand(0); 973 SDValue N1 = N->getOperand(1); 974 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 975 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 976 EVT VT = N0.getValueType(); 977 978 // fold vector ops 979 if (VT.isVector()) { 980 SDValue FoldedVOp = SimplifyVBinOp(N); 981 if (FoldedVOp.getNode()) return FoldedVOp; 982 } 983 984 // fold (add x, undef) -> undef 985 if (N0.getOpcode() == ISD::UNDEF) 986 return N0; 987 if (N1.getOpcode() == ISD::UNDEF) 988 return N1; 989 // fold (add c1, c2) -> c1+c2 990 if (N0C && N1C) 991 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C); 992 // canonicalize constant to RHS 993 if (N0C && !N1C) 994 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0); 995 // fold (add x, 0) -> x 996 if (N1C && N1C->isNullValue()) 997 return N0; 998 // fold (add Sym, c) -> Sym+c 999 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1000 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C && 1001 GA->getOpcode() == ISD::GlobalAddress) 1002 return DAG.getGlobalAddress(GA->getGlobal(), VT, 1003 GA->getOffset() + 1004 (uint64_t)N1C->getSExtValue()); 1005 // fold ((c1-A)+c2) -> (c1+c2)-A 1006 if (N1C && N0.getOpcode() == ISD::SUB) 1007 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 1008 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1009 DAG.getConstant(N1C->getAPIntValue()+ 1010 N0C->getAPIntValue(), VT), 1011 N0.getOperand(1)); 1012 // reassociate add 1013 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1); 1014 if (RADD.getNode() != 0) 1015 return RADD; 1016 // fold ((0-A) + B) -> B-A 1017 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 1018 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 1019 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1)); 1020 // fold (A + (0-B)) -> A-B 1021 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1022 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 1023 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1)); 1024 // fold (A+(B-A)) -> B 1025 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 1026 return N1.getOperand(0); 1027 // fold ((B-A)+A) -> B 1028 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) 1029 return N0.getOperand(0); 1030 // fold (A+(B-(A+C))) to (B-C) 1031 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1032 N0 == N1.getOperand(1).getOperand(0)) 1033 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1034 N1.getOperand(1).getOperand(1)); 1035 // fold (A+(B-(C+A))) to (B-C) 1036 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1037 N0 == N1.getOperand(1).getOperand(1)) 1038 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1039 N1.getOperand(1).getOperand(0)); 1040 // fold (A+((B-A)+or-C)) to (B+or-C) 1041 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && 1042 N1.getOperand(0).getOpcode() == ISD::SUB && 1043 N0 == N1.getOperand(0).getOperand(1)) 1044 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT, 1045 N1.getOperand(0).getOperand(0), N1.getOperand(1)); 1046 1047 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant 1048 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) { 1049 SDValue N00 = N0.getOperand(0); 1050 SDValue N01 = N0.getOperand(1); 1051 SDValue N10 = N1.getOperand(0); 1052 SDValue N11 = N1.getOperand(1); 1053 1054 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10)) 1055 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1056 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10), 1057 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11)); 1058 } 1059 1060 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 1061 return SDValue(N, 0); 1062 1063 // fold (a+b) -> (a|b) iff a and b share no bits. 1064 if (VT.isInteger() && !VT.isVector()) { 1065 APInt LHSZero, LHSOne; 1066 APInt RHSZero, RHSOne; 1067 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 1068 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1069 1070 if (LHSZero.getBoolValue()) { 1071 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1072 1073 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1074 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1075 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1076 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1077 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1); 1078 } 1079 } 1080 1081 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1082 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1083 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG); 1084 if (Result.getNode()) return Result; 1085 } 1086 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1087 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG); 1088 if (Result.getNode()) return Result; 1089 } 1090 1091 return SDValue(); 1092} 1093 1094SDValue DAGCombiner::visitADDC(SDNode *N) { 1095 SDValue N0 = N->getOperand(0); 1096 SDValue N1 = N->getOperand(1); 1097 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1098 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1099 EVT VT = N0.getValueType(); 1100 1101 // If the flag result is dead, turn this into an ADD. 1102 if (N->hasNUsesOfValue(0, 1)) 1103 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0), 1104 DAG.getNode(ISD::CARRY_FALSE, 1105 N->getDebugLoc(), MVT::Flag)); 1106 1107 // canonicalize constant to RHS. 1108 if (N0C && !N1C) 1109 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1110 1111 // fold (addc x, 0) -> x + no carry out 1112 if (N1C && N1C->isNullValue()) 1113 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, 1114 N->getDebugLoc(), MVT::Flag)); 1115 1116 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1117 APInt LHSZero, LHSOne; 1118 APInt RHSZero, RHSOne; 1119 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 1120 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1121 1122 if (LHSZero.getBoolValue()) { 1123 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1124 1125 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1126 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1127 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1128 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1129 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1), 1130 DAG.getNode(ISD::CARRY_FALSE, 1131 N->getDebugLoc(), MVT::Flag)); 1132 } 1133 1134 return SDValue(); 1135} 1136 1137SDValue DAGCombiner::visitADDE(SDNode *N) { 1138 SDValue N0 = N->getOperand(0); 1139 SDValue N1 = N->getOperand(1); 1140 SDValue CarryIn = N->getOperand(2); 1141 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1142 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1143 1144 // canonicalize constant to RHS 1145 if (N0C && !N1C) 1146 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), 1147 N1, N0, CarryIn); 1148 1149 // fold (adde x, y, false) -> (addc x, y) 1150 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1151 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1152 1153 return SDValue(); 1154} 1155 1156SDValue DAGCombiner::visitSUB(SDNode *N) { 1157 SDValue N0 = N->getOperand(0); 1158 SDValue N1 = N->getOperand(1); 1159 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1160 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1161 EVT VT = N0.getValueType(); 1162 1163 // fold vector ops 1164 if (VT.isVector()) { 1165 SDValue FoldedVOp = SimplifyVBinOp(N); 1166 if (FoldedVOp.getNode()) return FoldedVOp; 1167 } 1168 1169 // fold (sub x, x) -> 0 1170 if (N0 == N1) 1171 return DAG.getConstant(0, N->getValueType(0)); 1172 // fold (sub c1, c2) -> c1-c2 1173 if (N0C && N1C) 1174 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C); 1175 // fold (sub x, c) -> (add x, -c) 1176 if (N1C) 1177 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, 1178 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1179 // fold (A+B)-A -> B 1180 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1181 return N0.getOperand(1); 1182 // fold (A+B)-B -> A 1183 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1184 return N0.getOperand(0); 1185 // fold ((A+(B+or-C))-B) -> A+or-C 1186 if (N0.getOpcode() == ISD::ADD && 1187 (N0.getOperand(1).getOpcode() == ISD::SUB || 1188 N0.getOperand(1).getOpcode() == ISD::ADD) && 1189 N0.getOperand(1).getOperand(0) == N1) 1190 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT, 1191 N0.getOperand(0), N0.getOperand(1).getOperand(1)); 1192 // fold ((A+(C+B))-B) -> A+C 1193 if (N0.getOpcode() == ISD::ADD && 1194 N0.getOperand(1).getOpcode() == ISD::ADD && 1195 N0.getOperand(1).getOperand(1) == N1) 1196 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1197 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1198 // fold ((A-(B-C))-C) -> A-B 1199 if (N0.getOpcode() == ISD::SUB && 1200 N0.getOperand(1).getOpcode() == ISD::SUB && 1201 N0.getOperand(1).getOperand(1) == N1) 1202 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1203 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1204 1205 // If either operand of a sub is undef, the result is undef 1206 if (N0.getOpcode() == ISD::UNDEF) 1207 return N0; 1208 if (N1.getOpcode() == ISD::UNDEF) 1209 return N1; 1210 1211 // If the relocation model supports it, consider symbol offsets. 1212 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1213 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) { 1214 // fold (sub Sym, c) -> Sym-c 1215 if (N1C && GA->getOpcode() == ISD::GlobalAddress) 1216 return DAG.getGlobalAddress(GA->getGlobal(), VT, 1217 GA->getOffset() - 1218 (uint64_t)N1C->getSExtValue()); 1219 // fold (sub Sym+c1, Sym+c2) -> c1-c2 1220 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1)) 1221 if (GA->getGlobal() == GB->getGlobal()) 1222 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(), 1223 VT); 1224 } 1225 1226 return SDValue(); 1227} 1228 1229SDValue DAGCombiner::visitMUL(SDNode *N) { 1230 SDValue N0 = N->getOperand(0); 1231 SDValue N1 = N->getOperand(1); 1232 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1233 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1234 EVT VT = N0.getValueType(); 1235 1236 // fold vector ops 1237 if (VT.isVector()) { 1238 SDValue FoldedVOp = SimplifyVBinOp(N); 1239 if (FoldedVOp.getNode()) return FoldedVOp; 1240 } 1241 1242 // fold (mul x, undef) -> 0 1243 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1244 return DAG.getConstant(0, VT); 1245 // fold (mul c1, c2) -> c1*c2 1246 if (N0C && N1C) 1247 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C); 1248 // canonicalize constant to RHS 1249 if (N0C && !N1C) 1250 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0); 1251 // fold (mul x, 0) -> 0 1252 if (N1C && N1C->isNullValue()) 1253 return N1; 1254 // fold (mul x, -1) -> 0-x 1255 if (N1C && N1C->isAllOnesValue()) 1256 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1257 DAG.getConstant(0, VT), N0); 1258 // fold (mul x, (1 << c)) -> x << c 1259 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1260 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1261 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1262 getShiftAmountTy())); 1263 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1264 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) { 1265 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2(); 1266 // FIXME: If the input is something that is easily negated (e.g. a 1267 // single-use add), we should put the negate there. 1268 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1269 DAG.getConstant(0, VT), 1270 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1271 DAG.getConstant(Log2Val, getShiftAmountTy()))); 1272 } 1273 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1274 if (N1C && N0.getOpcode() == ISD::SHL && 1275 isa<ConstantSDNode>(N0.getOperand(1))) { 1276 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1277 N1, N0.getOperand(1)); 1278 AddToWorkList(C3.getNode()); 1279 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1280 N0.getOperand(0), C3); 1281 } 1282 1283 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1284 // use. 1285 { 1286 SDValue Sh(0,0), Y(0,0); 1287 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1288 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1289 N0.getNode()->hasOneUse()) { 1290 Sh = N0; Y = N1; 1291 } else if (N1.getOpcode() == ISD::SHL && 1292 isa<ConstantSDNode>(N1.getOperand(1)) && 1293 N1.getNode()->hasOneUse()) { 1294 Sh = N1; Y = N0; 1295 } 1296 1297 if (Sh.getNode()) { 1298 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1299 Sh.getOperand(0), Y); 1300 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1301 Mul, Sh.getOperand(1)); 1302 } 1303 } 1304 1305 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1306 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 1307 isa<ConstantSDNode>(N0.getOperand(1))) 1308 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1309 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT, 1310 N0.getOperand(0), N1), 1311 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT, 1312 N0.getOperand(1), N1)); 1313 1314 // reassociate mul 1315 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1); 1316 if (RMUL.getNode() != 0) 1317 return RMUL; 1318 1319 return SDValue(); 1320} 1321 1322SDValue DAGCombiner::visitSDIV(SDNode *N) { 1323 SDValue N0 = N->getOperand(0); 1324 SDValue N1 = N->getOperand(1); 1325 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1326 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1327 EVT VT = N->getValueType(0); 1328 1329 // fold vector ops 1330 if (VT.isVector()) { 1331 SDValue FoldedVOp = SimplifyVBinOp(N); 1332 if (FoldedVOp.getNode()) return FoldedVOp; 1333 } 1334 1335 // fold (sdiv c1, c2) -> c1/c2 1336 if (N0C && N1C && !N1C->isNullValue()) 1337 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); 1338 // fold (sdiv X, 1) -> X 1339 if (N1C && N1C->getSExtValue() == 1LL) 1340 return N0; 1341 // fold (sdiv X, -1) -> 0-X 1342 if (N1C && N1C->isAllOnesValue()) 1343 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1344 DAG.getConstant(0, VT), N0); 1345 // If we know the sign bits of both operands are zero, strength reduce to a 1346 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1347 if (!VT.isVector()) { 1348 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1349 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(), 1350 N0, N1); 1351 } 1352 // fold (sdiv X, pow2) -> simple ops after legalize 1353 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() && 1354 (isPowerOf2_64(N1C->getSExtValue()) || 1355 isPowerOf2_64(-N1C->getSExtValue()))) { 1356 // If dividing by powers of two is cheap, then don't perform the following 1357 // fold. 1358 if (TLI.isPow2DivCheap()) 1359 return SDValue(); 1360 1361 int64_t pow2 = N1C->getSExtValue(); 1362 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1363 unsigned lg2 = Log2_64(abs2); 1364 1365 // Splat the sign bit into the register 1366 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 1367 DAG.getConstant(VT.getSizeInBits()-1, 1368 getShiftAmountTy())); 1369 AddToWorkList(SGN.getNode()); 1370 1371 // Add (N0 < 0) ? abs2 - 1 : 0; 1372 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN, 1373 DAG.getConstant(VT.getSizeInBits() - lg2, 1374 getShiftAmountTy())); 1375 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL); 1376 AddToWorkList(SRL.getNode()); 1377 AddToWorkList(ADD.getNode()); // Divide by pow2 1378 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD, 1379 DAG.getConstant(lg2, getShiftAmountTy())); 1380 1381 // If we're dividing by a positive value, we're done. Otherwise, we must 1382 // negate the result. 1383 if (pow2 > 0) 1384 return SRA; 1385 1386 AddToWorkList(SRA.getNode()); 1387 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1388 DAG.getConstant(0, VT), SRA); 1389 } 1390 1391 // if integer divide is expensive and we satisfy the requirements, emit an 1392 // alternate sequence. 1393 if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) && 1394 !TLI.isIntDivCheap()) { 1395 SDValue Op = BuildSDIV(N); 1396 if (Op.getNode()) return Op; 1397 } 1398 1399 // undef / X -> 0 1400 if (N0.getOpcode() == ISD::UNDEF) 1401 return DAG.getConstant(0, VT); 1402 // X / undef -> undef 1403 if (N1.getOpcode() == ISD::UNDEF) 1404 return N1; 1405 1406 return SDValue(); 1407} 1408 1409SDValue DAGCombiner::visitUDIV(SDNode *N) { 1410 SDValue N0 = N->getOperand(0); 1411 SDValue N1 = N->getOperand(1); 1412 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1413 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1414 EVT VT = N->getValueType(0); 1415 1416 // fold vector ops 1417 if (VT.isVector()) { 1418 SDValue FoldedVOp = SimplifyVBinOp(N); 1419 if (FoldedVOp.getNode()) return FoldedVOp; 1420 } 1421 1422 // fold (udiv c1, c2) -> c1/c2 1423 if (N0C && N1C && !N1C->isNullValue()) 1424 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); 1425 // fold (udiv x, (1 << c)) -> x >>u c 1426 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1427 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 1428 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1429 getShiftAmountTy())); 1430 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1431 if (N1.getOpcode() == ISD::SHL) { 1432 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1433 if (SHC->getAPIntValue().isPowerOf2()) { 1434 EVT ADDVT = N1.getOperand(1).getValueType(); 1435 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT, 1436 N1.getOperand(1), 1437 DAG.getConstant(SHC->getAPIntValue() 1438 .logBase2(), 1439 ADDVT)); 1440 AddToWorkList(Add.getNode()); 1441 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add); 1442 } 1443 } 1444 } 1445 // fold (udiv x, c) -> alternate 1446 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1447 SDValue Op = BuildUDIV(N); 1448 if (Op.getNode()) return Op; 1449 } 1450 1451 // undef / X -> 0 1452 if (N0.getOpcode() == ISD::UNDEF) 1453 return DAG.getConstant(0, VT); 1454 // X / undef -> undef 1455 if (N1.getOpcode() == ISD::UNDEF) 1456 return N1; 1457 1458 return SDValue(); 1459} 1460 1461SDValue DAGCombiner::visitSREM(SDNode *N) { 1462 SDValue N0 = N->getOperand(0); 1463 SDValue N1 = N->getOperand(1); 1464 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1465 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1466 EVT VT = N->getValueType(0); 1467 1468 // fold (srem c1, c2) -> c1%c2 1469 if (N0C && N1C && !N1C->isNullValue()) 1470 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); 1471 // If we know the sign bits of both operands are zero, strength reduce to a 1472 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1473 if (!VT.isVector()) { 1474 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1475 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1); 1476 } 1477 1478 // If X/C can be simplified by the division-by-constant logic, lower 1479 // X%C to the equivalent of X-X/C*C. 1480 if (N1C && !N1C->isNullValue()) { 1481 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1); 1482 AddToWorkList(Div.getNode()); 1483 SDValue OptimizedDiv = combine(Div.getNode()); 1484 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1485 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1486 OptimizedDiv, N1); 1487 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1488 AddToWorkList(Mul.getNode()); 1489 return Sub; 1490 } 1491 } 1492 1493 // undef % X -> 0 1494 if (N0.getOpcode() == ISD::UNDEF) 1495 return DAG.getConstant(0, VT); 1496 // X % undef -> undef 1497 if (N1.getOpcode() == ISD::UNDEF) 1498 return N1; 1499 1500 return SDValue(); 1501} 1502 1503SDValue DAGCombiner::visitUREM(SDNode *N) { 1504 SDValue N0 = N->getOperand(0); 1505 SDValue N1 = N->getOperand(1); 1506 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1507 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1508 EVT VT = N->getValueType(0); 1509 1510 // fold (urem c1, c2) -> c1%c2 1511 if (N0C && N1C && !N1C->isNullValue()) 1512 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C); 1513 // fold (urem x, pow2) -> (and x, pow2-1) 1514 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 1515 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, 1516 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 1517 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1518 if (N1.getOpcode() == ISD::SHL) { 1519 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1520 if (SHC->getAPIntValue().isPowerOf2()) { 1521 SDValue Add = 1522 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, 1523 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 1524 VT)); 1525 AddToWorkList(Add.getNode()); 1526 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add); 1527 } 1528 } 1529 } 1530 1531 // If X/C can be simplified by the division-by-constant logic, lower 1532 // X%C to the equivalent of X-X/C*C. 1533 if (N1C && !N1C->isNullValue()) { 1534 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1); 1535 AddToWorkList(Div.getNode()); 1536 SDValue OptimizedDiv = combine(Div.getNode()); 1537 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1538 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1539 OptimizedDiv, N1); 1540 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1541 AddToWorkList(Mul.getNode()); 1542 return Sub; 1543 } 1544 } 1545 1546 // undef % X -> 0 1547 if (N0.getOpcode() == ISD::UNDEF) 1548 return DAG.getConstant(0, VT); 1549 // X % undef -> undef 1550 if (N1.getOpcode() == ISD::UNDEF) 1551 return N1; 1552 1553 return SDValue(); 1554} 1555 1556SDValue DAGCombiner::visitMULHS(SDNode *N) { 1557 SDValue N0 = N->getOperand(0); 1558 SDValue N1 = N->getOperand(1); 1559 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1560 EVT VT = N->getValueType(0); 1561 1562 // fold (mulhs x, 0) -> 0 1563 if (N1C && N1C->isNullValue()) 1564 return N1; 1565 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1566 if (N1C && N1C->getAPIntValue() == 1) 1567 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0, 1568 DAG.getConstant(N0.getValueType().getSizeInBits() - 1, 1569 getShiftAmountTy())); 1570 // fold (mulhs x, undef) -> 0 1571 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1572 return DAG.getConstant(0, VT); 1573 1574 return SDValue(); 1575} 1576 1577SDValue DAGCombiner::visitMULHU(SDNode *N) { 1578 SDValue N0 = N->getOperand(0); 1579 SDValue N1 = N->getOperand(1); 1580 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1581 EVT VT = N->getValueType(0); 1582 1583 // fold (mulhu x, 0) -> 0 1584 if (N1C && N1C->isNullValue()) 1585 return N1; 1586 // fold (mulhu x, 1) -> 0 1587 if (N1C && N1C->getAPIntValue() == 1) 1588 return DAG.getConstant(0, N0.getValueType()); 1589 // fold (mulhu x, undef) -> 0 1590 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1591 return DAG.getConstant(0, VT); 1592 1593 return SDValue(); 1594} 1595 1596/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 1597/// compute two values. LoOp and HiOp give the opcodes for the two computations 1598/// that are being performed. Return true if a simplification was made. 1599/// 1600SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 1601 unsigned HiOp) { 1602 // If the high half is not needed, just compute the low half. 1603 bool HiExists = N->hasAnyUseOfValue(1); 1604 if (!HiExists && 1605 (!LegalOperations || 1606 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 1607 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 1608 N->op_begin(), N->getNumOperands()); 1609 return CombineTo(N, Res, Res); 1610 } 1611 1612 // If the low half is not needed, just compute the high half. 1613 bool LoExists = N->hasAnyUseOfValue(0); 1614 if (!LoExists && 1615 (!LegalOperations || 1616 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 1617 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 1618 N->op_begin(), N->getNumOperands()); 1619 return CombineTo(N, Res, Res); 1620 } 1621 1622 // If both halves are used, return as it is. 1623 if (LoExists && HiExists) 1624 return SDValue(); 1625 1626 // If the two computed results can be simplified separately, separate them. 1627 if (LoExists) { 1628 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 1629 N->op_begin(), N->getNumOperands()); 1630 AddToWorkList(Lo.getNode()); 1631 SDValue LoOpt = combine(Lo.getNode()); 1632 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && 1633 (!LegalOperations || 1634 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 1635 return CombineTo(N, LoOpt, LoOpt); 1636 } 1637 1638 if (HiExists) { 1639 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 1640 N->op_begin(), N->getNumOperands()); 1641 AddToWorkList(Hi.getNode()); 1642 SDValue HiOpt = combine(Hi.getNode()); 1643 if (HiOpt.getNode() && HiOpt != Hi && 1644 (!LegalOperations || 1645 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 1646 return CombineTo(N, HiOpt, HiOpt); 1647 } 1648 1649 return SDValue(); 1650} 1651 1652SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 1653 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 1654 if (Res.getNode()) return Res; 1655 1656 return SDValue(); 1657} 1658 1659SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 1660 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 1661 if (Res.getNode()) return Res; 1662 1663 return SDValue(); 1664} 1665 1666SDValue DAGCombiner::visitSDIVREM(SDNode *N) { 1667 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 1668 if (Res.getNode()) return Res; 1669 1670 return SDValue(); 1671} 1672 1673SDValue DAGCombiner::visitUDIVREM(SDNode *N) { 1674 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 1675 if (Res.getNode()) return Res; 1676 1677 return SDValue(); 1678} 1679 1680/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 1681/// two operands of the same opcode, try to simplify it. 1682SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 1683 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 1684 EVT VT = N0.getValueType(); 1685 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 1686 1687 // Bail early if none of these transforms apply. 1688 if (N0.getNode()->getNumOperands() == 0) return SDValue(); 1689 1690 // For each of OP in AND/OR/XOR: 1691 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 1692 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 1693 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 1694 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) 1695 // 1696 // do not sink logical op inside of a vector extend, since it may combine 1697 // into a vsetcc. 1698 EVT Op0VT = N0.getOperand(0).getValueType(); 1699 if ((N0.getOpcode() == ISD::ZERO_EXTEND || 1700 N0.getOpcode() == ISD::ANY_EXTEND || 1701 N0.getOpcode() == ISD::SIGN_EXTEND || 1702 (N0.getOpcode() == ISD::TRUNCATE && TLI.isTypeLegal(Op0VT))) && 1703 !VT.isVector() && 1704 Op0VT == N1.getOperand(0).getValueType() && 1705 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) { 1706 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 1707 N0.getOperand(0).getValueType(), 1708 N0.getOperand(0), N1.getOperand(0)); 1709 AddToWorkList(ORNode.getNode()); 1710 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode); 1711 } 1712 1713 // For each of OP in SHL/SRL/SRA/AND... 1714 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 1715 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 1716 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 1717 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 1718 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 1719 N0.getOperand(1) == N1.getOperand(1)) { 1720 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 1721 N0.getOperand(0).getValueType(), 1722 N0.getOperand(0), N1.getOperand(0)); 1723 AddToWorkList(ORNode.getNode()); 1724 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 1725 ORNode, N0.getOperand(1)); 1726 } 1727 1728 return SDValue(); 1729} 1730 1731SDValue DAGCombiner::visitAND(SDNode *N) { 1732 SDValue N0 = N->getOperand(0); 1733 SDValue N1 = N->getOperand(1); 1734 SDValue LL, LR, RL, RR, CC0, CC1; 1735 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1736 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1737 EVT VT = N1.getValueType(); 1738 unsigned BitWidth = VT.getSizeInBits(); 1739 1740 // fold vector ops 1741 if (VT.isVector()) { 1742 SDValue FoldedVOp = SimplifyVBinOp(N); 1743 if (FoldedVOp.getNode()) return FoldedVOp; 1744 } 1745 1746 // fold (and x, undef) -> 0 1747 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1748 return DAG.getConstant(0, VT); 1749 // fold (and c1, c2) -> c1&c2 1750 if (N0C && N1C) 1751 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C); 1752 // canonicalize constant to RHS 1753 if (N0C && !N1C) 1754 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0); 1755 // fold (and x, -1) -> x 1756 if (N1C && N1C->isAllOnesValue()) 1757 return N0; 1758 // if (and x, c) is known to be zero, return 0 1759 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 1760 APInt::getAllOnesValue(BitWidth))) 1761 return DAG.getConstant(0, VT); 1762 // reassociate and 1763 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1); 1764 if (RAND.getNode() != 0) 1765 return RAND; 1766 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 1767 if (N1C && N0.getOpcode() == ISD::OR) 1768 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1769 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 1770 return N1; 1771 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 1772 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1773 SDValue N0Op0 = N0.getOperand(0); 1774 APInt Mask = ~N1C->getAPIntValue(); 1775 Mask.trunc(N0Op0.getValueSizeInBits()); 1776 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 1777 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), 1778 N0.getValueType(), N0Op0); 1779 1780 // Replace uses of the AND with uses of the Zero extend node. 1781 CombineTo(N, Zext); 1782 1783 // We actually want to replace all uses of the any_extend with the 1784 // zero_extend, to avoid duplicating things. This will later cause this 1785 // AND to be folded. 1786 CombineTo(N0.getNode(), Zext); 1787 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1788 } 1789 } 1790 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 1791 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1792 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1793 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1794 1795 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1796 LL.getValueType().isInteger()) { 1797 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0) 1798 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 1799 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 1800 LR.getValueType(), LL, RL); 1801 AddToWorkList(ORNode.getNode()); 1802 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 1803 } 1804 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1) 1805 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 1806 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(), 1807 LR.getValueType(), LL, RL); 1808 AddToWorkList(ANDNode.getNode()); 1809 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 1810 } 1811 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1) 1812 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1813 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 1814 LR.getValueType(), LL, RL); 1815 AddToWorkList(ORNode.getNode()); 1816 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 1817 } 1818 } 1819 // canonicalize equivalent to ll == rl 1820 if (LL == RR && LR == RL) { 1821 Op1 = ISD::getSetCCSwappedOperands(Op1); 1822 std::swap(RL, RR); 1823 } 1824 if (LL == RL && LR == RR) { 1825 bool isInteger = LL.getValueType().isInteger(); 1826 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1827 if (Result != ISD::SETCC_INVALID && 1828 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 1829 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 1830 LL, LR, Result); 1831 } 1832 } 1833 1834 // Simplify: (and (op x...), (op y...)) -> (op (and x, y)) 1835 if (N0.getOpcode() == N1.getOpcode()) { 1836 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1837 if (Tmp.getNode()) return Tmp; 1838 } 1839 1840 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1841 // fold (and (sra)) -> (and (srl)) when possible. 1842 if (!VT.isVector() && 1843 SimplifyDemandedBits(SDValue(N, 0))) 1844 return SDValue(N, 0); 1845 1846 // fold (zext_inreg (extload x)) -> (zextload x) 1847 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { 1848 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1849 EVT MemVT = LN0->getMemoryVT(); 1850 // If we zero all the possible extended bits, then we can turn this into 1851 // a zextload if we are running before legalize or the operation is legal. 1852 unsigned BitWidth = N1.getValueSizeInBits(); 1853 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1854 BitWidth - MemVT.getSizeInBits())) && 1855 ((!LegalOperations && !LN0->isVolatile()) || 1856 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 1857 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 1858 LN0->getChain(), LN0->getBasePtr(), 1859 LN0->getSrcValue(), 1860 LN0->getSrcValueOffset(), MemVT, 1861 LN0->isVolatile(), LN0->getAlignment()); 1862 AddToWorkList(N); 1863 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 1864 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1865 } 1866 } 1867 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1868 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 1869 N0.hasOneUse()) { 1870 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1871 EVT MemVT = LN0->getMemoryVT(); 1872 // If we zero all the possible extended bits, then we can turn this into 1873 // a zextload if we are running before legalize or the operation is legal. 1874 unsigned BitWidth = N1.getValueSizeInBits(); 1875 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1876 BitWidth - MemVT.getSizeInBits())) && 1877 ((!LegalOperations && !LN0->isVolatile()) || 1878 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 1879 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 1880 LN0->getChain(), 1881 LN0->getBasePtr(), LN0->getSrcValue(), 1882 LN0->getSrcValueOffset(), MemVT, 1883 LN0->isVolatile(), LN0->getAlignment()); 1884 AddToWorkList(N); 1885 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 1886 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1887 } 1888 } 1889 1890 // fold (and (load x), 255) -> (zextload x, i8) 1891 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1892 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8) 1893 if (N1C && (N0.getOpcode() == ISD::LOAD || 1894 (N0.getOpcode() == ISD::ANY_EXTEND && 1895 N0.getOperand(0).getOpcode() == ISD::LOAD))) { 1896 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND; 1897 LoadSDNode *LN0 = HasAnyExt 1898 ? cast<LoadSDNode>(N0.getOperand(0)) 1899 : cast<LoadSDNode>(N0); 1900 if (LN0->getExtensionType() != ISD::SEXTLOAD && 1901 LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) { 1902 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 1903 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){ 1904 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits); 1905 EVT LoadedVT = LN0->getMemoryVT(); 1906 1907 if (ExtVT == LoadedVT && 1908 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 1909 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 1910 1911 SDValue NewLoad = 1912 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 1913 LN0->getChain(), LN0->getBasePtr(), 1914 LN0->getSrcValue(), LN0->getSrcValueOffset(), 1915 ExtVT, LN0->isVolatile(), LN0->getAlignment()); 1916 AddToWorkList(N); 1917 CombineTo(LN0, NewLoad, NewLoad.getValue(1)); 1918 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1919 } 1920 1921 // Do not change the width of a volatile load. 1922 // Do not generate loads of non-round integer types since these can 1923 // be expensive (and would be wrong if the type is not byte sized). 1924 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() && 1925 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 1926 EVT PtrType = LN0->getOperand(1).getValueType(); 1927 1928 unsigned Alignment = LN0->getAlignment(); 1929 SDValue NewPtr = LN0->getBasePtr(); 1930 1931 // For big endian targets, we need to add an offset to the pointer 1932 // to load the correct bytes. For little endian systems, we merely 1933 // need to read fewer bytes from the same pointer. 1934 if (TLI.isBigEndian()) { 1935 unsigned LVTStoreBytes = LoadedVT.getStoreSize(); 1936 unsigned EVTStoreBytes = ExtVT.getStoreSize(); 1937 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 1938 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType, 1939 NewPtr, DAG.getConstant(PtrOff, PtrType)); 1940 Alignment = MinAlign(Alignment, PtrOff); 1941 } 1942 1943 AddToWorkList(NewPtr.getNode()); 1944 1945 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 1946 SDValue Load = 1947 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 1948 LN0->getChain(), NewPtr, 1949 LN0->getSrcValue(), LN0->getSrcValueOffset(), 1950 ExtVT, LN0->isVolatile(), Alignment); 1951 AddToWorkList(N); 1952 CombineTo(LN0, Load, Load.getValue(1)); 1953 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1954 } 1955 } 1956 } 1957 } 1958 1959 return SDValue(); 1960} 1961 1962SDValue DAGCombiner::visitOR(SDNode *N) { 1963 SDValue N0 = N->getOperand(0); 1964 SDValue N1 = N->getOperand(1); 1965 SDValue LL, LR, RL, RR, CC0, CC1; 1966 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1967 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1968 EVT VT = N1.getValueType(); 1969 1970 // fold vector ops 1971 if (VT.isVector()) { 1972 SDValue FoldedVOp = SimplifyVBinOp(N); 1973 if (FoldedVOp.getNode()) return FoldedVOp; 1974 } 1975 1976 // fold (or x, undef) -> -1 1977 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) { 1978 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 1979 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT); 1980 } 1981 // fold (or c1, c2) -> c1|c2 1982 if (N0C && N1C) 1983 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); 1984 // canonicalize constant to RHS 1985 if (N0C && !N1C) 1986 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0); 1987 // fold (or x, 0) -> x 1988 if (N1C && N1C->isNullValue()) 1989 return N0; 1990 // fold (or x, -1) -> -1 1991 if (N1C && N1C->isAllOnesValue()) 1992 return N1; 1993 // fold (or x, c) -> c iff (x & ~c) == 0 1994 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 1995 return N1; 1996 // reassociate or 1997 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1); 1998 if (ROR.getNode() != 0) 1999 return ROR; 2000 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 2001 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 2002 isa<ConstantSDNode>(N0.getOperand(1))) { 2003 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 2004 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 2005 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 2006 N0.getOperand(0), N1), 2007 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1)); 2008 } 2009 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 2010 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 2011 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 2012 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 2013 2014 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 2015 LL.getValueType().isInteger()) { 2016 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0) 2017 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0) 2018 if (cast<ConstantSDNode>(LR)->isNullValue() && 2019 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 2020 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(), 2021 LR.getValueType(), LL, RL); 2022 AddToWorkList(ORNode.getNode()); 2023 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2024 } 2025 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1) 2026 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1) 2027 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 2028 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 2029 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(), 2030 LR.getValueType(), LL, RL); 2031 AddToWorkList(ANDNode.getNode()); 2032 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 2033 } 2034 } 2035 // canonicalize equivalent to ll == rl 2036 if (LL == RR && LR == RL) { 2037 Op1 = ISD::getSetCCSwappedOperands(Op1); 2038 std::swap(RL, RR); 2039 } 2040 if (LL == RL && LR == RR) { 2041 bool isInteger = LL.getValueType().isInteger(); 2042 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 2043 if (Result != ISD::SETCC_INVALID && 2044 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 2045 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 2046 LL, LR, Result); 2047 } 2048 } 2049 2050 // Simplify: (or (op x...), (op y...)) -> (op (or x, y)) 2051 if (N0.getOpcode() == N1.getOpcode()) { 2052 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2053 if (Tmp.getNode()) return Tmp; 2054 } 2055 2056 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible. 2057 if (N0.getOpcode() == ISD::AND && 2058 N1.getOpcode() == ISD::AND && 2059 N0.getOperand(1).getOpcode() == ISD::Constant && 2060 N1.getOperand(1).getOpcode() == ISD::Constant && 2061 // Don't increase # computations. 2062 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) { 2063 // We can only do this xform if we know that bits from X that are set in C2 2064 // but not in C1 are already zero. Likewise for Y. 2065 const APInt &LHSMask = 2066 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 2067 const APInt &RHSMask = 2068 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 2069 2070 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 2071 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 2072 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 2073 N0.getOperand(0), N1.getOperand(0)); 2074 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X, 2075 DAG.getConstant(LHSMask | RHSMask, VT)); 2076 } 2077 } 2078 2079 // See if this is some rotate idiom. 2080 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc())) 2081 return SDValue(Rot, 0); 2082 2083 return SDValue(); 2084} 2085 2086/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 2087static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 2088 if (Op.getOpcode() == ISD::AND) { 2089 if (isa<ConstantSDNode>(Op.getOperand(1))) { 2090 Mask = Op.getOperand(1); 2091 Op = Op.getOperand(0); 2092 } else { 2093 return false; 2094 } 2095 } 2096 2097 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 2098 Shift = Op; 2099 return true; 2100 } 2101 2102 return false; 2103} 2104 2105// MatchRotate - Handle an 'or' of two operands. If this is one of the many 2106// idioms for rotate, and if the target supports rotation instructions, generate 2107// a rot[lr]. 2108SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) { 2109 // Must be a legal type. Expanded 'n promoted things won't work with rotates. 2110 EVT VT = LHS.getValueType(); 2111 if (!TLI.isTypeLegal(VT)) return 0; 2112 2113 // The target must have at least one rotate flavor. 2114 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT); 2115 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT); 2116 if (!HasROTL && !HasROTR) return 0; 2117 2118 // Match "(X shl/srl V1) & V2" where V2 may not be present. 2119 SDValue LHSShift; // The shift. 2120 SDValue LHSMask; // AND value if any. 2121 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 2122 return 0; // Not part of a rotate. 2123 2124 SDValue RHSShift; // The shift. 2125 SDValue RHSMask; // AND value if any. 2126 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 2127 return 0; // Not part of a rotate. 2128 2129 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 2130 return 0; // Not shifting the same value. 2131 2132 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 2133 return 0; // Shifts must disagree. 2134 2135 // Canonicalize shl to left side in a shl/srl pair. 2136 if (RHSShift.getOpcode() == ISD::SHL) { 2137 std::swap(LHS, RHS); 2138 std::swap(LHSShift, RHSShift); 2139 std::swap(LHSMask , RHSMask ); 2140 } 2141 2142 unsigned OpSizeInBits = VT.getSizeInBits(); 2143 SDValue LHSShiftArg = LHSShift.getOperand(0); 2144 SDValue LHSShiftAmt = LHSShift.getOperand(1); 2145 SDValue RHSShiftAmt = RHSShift.getOperand(1); 2146 2147 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 2148 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 2149 if (LHSShiftAmt.getOpcode() == ISD::Constant && 2150 RHSShiftAmt.getOpcode() == ISD::Constant) { 2151 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue(); 2152 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue(); 2153 if ((LShVal + RShVal) != OpSizeInBits) 2154 return 0; 2155 2156 SDValue Rot; 2157 if (HasROTL) 2158 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt); 2159 else 2160 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt); 2161 2162 // If there is an AND of either shifted operand, apply it to the result. 2163 if (LHSMask.getNode() || RHSMask.getNode()) { 2164 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 2165 2166 if (LHSMask.getNode()) { 2167 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 2168 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 2169 } 2170 if (RHSMask.getNode()) { 2171 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 2172 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 2173 } 2174 2175 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT)); 2176 } 2177 2178 return Rot.getNode(); 2179 } 2180 2181 // If there is a mask here, and we have a variable shift, we can't be sure 2182 // that we're masking out the right stuff. 2183 if (LHSMask.getNode() || RHSMask.getNode()) 2184 return 0; 2185 2186 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 2187 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 2188 if (RHSShiftAmt.getOpcode() == ISD::SUB && 2189 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 2190 if (ConstantSDNode *SUBC = 2191 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 2192 if (SUBC->getAPIntValue() == OpSizeInBits) { 2193 if (HasROTL) 2194 return DAG.getNode(ISD::ROTL, DL, VT, 2195 LHSShiftArg, LHSShiftAmt).getNode(); 2196 else 2197 return DAG.getNode(ISD::ROTR, DL, VT, 2198 LHSShiftArg, RHSShiftAmt).getNode(); 2199 } 2200 } 2201 } 2202 2203 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 2204 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 2205 if (LHSShiftAmt.getOpcode() == ISD::SUB && 2206 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 2207 if (ConstantSDNode *SUBC = 2208 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 2209 if (SUBC->getAPIntValue() == OpSizeInBits) { 2210 if (HasROTR) 2211 return DAG.getNode(ISD::ROTR, DL, VT, 2212 LHSShiftArg, RHSShiftAmt).getNode(); 2213 else 2214 return DAG.getNode(ISD::ROTL, DL, VT, 2215 LHSShiftArg, LHSShiftAmt).getNode(); 2216 } 2217 } 2218 } 2219 2220 // Look for sign/zext/any-extended or truncate cases: 2221 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2222 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2223 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2224 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && 2225 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2226 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2227 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2228 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { 2229 SDValue LExtOp0 = LHSShiftAmt.getOperand(0); 2230 SDValue RExtOp0 = RHSShiftAmt.getOperand(0); 2231 if (RExtOp0.getOpcode() == ISD::SUB && 2232 RExtOp0.getOperand(1) == LExtOp0) { 2233 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2234 // (rotl x, y) 2235 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2236 // (rotr x, (sub 32, y)) 2237 if (ConstantSDNode *SUBC = 2238 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 2239 if (SUBC->getAPIntValue() == OpSizeInBits) { 2240 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 2241 LHSShiftArg, 2242 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 2243 } 2244 } 2245 } else if (LExtOp0.getOpcode() == ISD::SUB && 2246 RExtOp0 == LExtOp0.getOperand(1)) { 2247 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2248 // (rotr x, y) 2249 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2250 // (rotl x, (sub 32, y)) 2251 if (ConstantSDNode *SUBC = 2252 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 2253 if (SUBC->getAPIntValue() == OpSizeInBits) { 2254 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, 2255 LHSShiftArg, 2256 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 2257 } 2258 } 2259 } 2260 } 2261 2262 return 0; 2263} 2264 2265SDValue DAGCombiner::visitXOR(SDNode *N) { 2266 SDValue N0 = N->getOperand(0); 2267 SDValue N1 = N->getOperand(1); 2268 SDValue LHS, RHS, CC; 2269 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2270 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2271 EVT VT = N0.getValueType(); 2272 2273 // fold vector ops 2274 if (VT.isVector()) { 2275 SDValue FoldedVOp = SimplifyVBinOp(N); 2276 if (FoldedVOp.getNode()) return FoldedVOp; 2277 } 2278 2279 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 2280 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 2281 return DAG.getConstant(0, VT); 2282 // fold (xor x, undef) -> undef 2283 if (N0.getOpcode() == ISD::UNDEF) 2284 return N0; 2285 if (N1.getOpcode() == ISD::UNDEF) 2286 return N1; 2287 // fold (xor c1, c2) -> c1^c2 2288 if (N0C && N1C) 2289 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); 2290 // canonicalize constant to RHS 2291 if (N0C && !N1C) 2292 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 2293 // fold (xor x, 0) -> x 2294 if (N1C && N1C->isNullValue()) 2295 return N0; 2296 // reassociate xor 2297 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1); 2298 if (RXOR.getNode() != 0) 2299 return RXOR; 2300 2301 // fold !(x cc y) -> (x !cc y) 2302 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 2303 bool isInt = LHS.getValueType().isInteger(); 2304 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 2305 isInt); 2306 2307 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) { 2308 switch (N0.getOpcode()) { 2309 default: 2310 llvm_unreachable("Unhandled SetCC Equivalent!"); 2311 case ISD::SETCC: 2312 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC); 2313 case ISD::SELECT_CC: 2314 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2), 2315 N0.getOperand(3), NotCC); 2316 } 2317 } 2318 } 2319 2320 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 2321 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 2322 N0.getNode()->hasOneUse() && 2323 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 2324 SDValue V = N0.getOperand(0); 2325 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V, 2326 DAG.getConstant(1, V.getValueType())); 2327 AddToWorkList(V.getNode()); 2328 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V); 2329 } 2330 2331 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc 2332 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 2333 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2334 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2335 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 2336 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2337 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2338 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2339 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2340 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2341 } 2342 } 2343 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants 2344 if (N1C && N1C->isAllOnesValue() && 2345 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2346 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2347 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 2348 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2349 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2350 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2351 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2352 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2353 } 2354 } 2355 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2)) 2356 if (N1C && N0.getOpcode() == ISD::XOR) { 2357 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 2358 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2359 if (N00C) 2360 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1), 2361 DAG.getConstant(N1C->getAPIntValue() ^ 2362 N00C->getAPIntValue(), VT)); 2363 if (N01C) 2364 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0), 2365 DAG.getConstant(N1C->getAPIntValue() ^ 2366 N01C->getAPIntValue(), VT)); 2367 } 2368 // fold (xor x, x) -> 0 2369 if (N0 == N1) { 2370 if (!VT.isVector()) { 2371 return DAG.getConstant(0, VT); 2372 } else if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)){ 2373 // Produce a vector of zeros. 2374 SDValue El = DAG.getConstant(0, VT.getVectorElementType()); 2375 std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 2376 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 2377 &Ops[0], Ops.size()); 2378 } 2379 } 2380 2381 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 2382 if (N0.getOpcode() == N1.getOpcode()) { 2383 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2384 if (Tmp.getNode()) return Tmp; 2385 } 2386 2387 // Simplify the expression using non-local knowledge. 2388 if (!VT.isVector() && 2389 SimplifyDemandedBits(SDValue(N, 0))) 2390 return SDValue(N, 0); 2391 2392 return SDValue(); 2393} 2394 2395/// visitShiftByConstant - Handle transforms common to the three shifts, when 2396/// the shift amount is a constant. 2397SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 2398 SDNode *LHS = N->getOperand(0).getNode(); 2399 if (!LHS->hasOneUse()) return SDValue(); 2400 2401 // We want to pull some binops through shifts, so that we have (and (shift)) 2402 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 2403 // thing happens with address calculations, so it's important to canonicalize 2404 // it. 2405 bool HighBitSet = false; // Can we transform this if the high bit is set? 2406 2407 switch (LHS->getOpcode()) { 2408 default: return SDValue(); 2409 case ISD::OR: 2410 case ISD::XOR: 2411 HighBitSet = false; // We can only transform sra if the high bit is clear. 2412 break; 2413 case ISD::AND: 2414 HighBitSet = true; // We can only transform sra if the high bit is set. 2415 break; 2416 case ISD::ADD: 2417 if (N->getOpcode() != ISD::SHL) 2418 return SDValue(); // only shl(add) not sr[al](add). 2419 HighBitSet = false; // We can only transform sra if the high bit is clear. 2420 break; 2421 } 2422 2423 // We require the RHS of the binop to be a constant as well. 2424 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 2425 if (!BinOpCst) return SDValue(); 2426 2427 // FIXME: disable this unless the input to the binop is a shift by a constant. 2428 // If it is not a shift, it pessimizes some common cases like: 2429 // 2430 // void foo(int *X, int i) { X[i & 1235] = 1; } 2431 // int bar(int *X, int i) { return X[i & 255]; } 2432 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); 2433 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 2434 BinOpLHSVal->getOpcode() != ISD::SRA && 2435 BinOpLHSVal->getOpcode() != ISD::SRL) || 2436 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 2437 return SDValue(); 2438 2439 EVT VT = N->getValueType(0); 2440 2441 // If this is a signed shift right, and the high bit is modified by the 2442 // logical operation, do not perform the transformation. The highBitSet 2443 // boolean indicates the value of the high bit of the constant which would 2444 // cause it to be modified for this operation. 2445 if (N->getOpcode() == ISD::SRA) { 2446 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 2447 if (BinOpRHSSignSet != HighBitSet) 2448 return SDValue(); 2449 } 2450 2451 // Fold the constants, shifting the binop RHS by the shift amount. 2452 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(), 2453 N->getValueType(0), 2454 LHS->getOperand(1), N->getOperand(1)); 2455 2456 // Create the new shift. 2457 SDValue NewShift = DAG.getNode(N->getOpcode(), LHS->getOperand(0).getDebugLoc(), 2458 VT, LHS->getOperand(0), N->getOperand(1)); 2459 2460 // Create the new binop. 2461 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS); 2462} 2463 2464SDValue DAGCombiner::visitSHL(SDNode *N) { 2465 SDValue N0 = N->getOperand(0); 2466 SDValue N1 = N->getOperand(1); 2467 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2468 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2469 EVT VT = N0.getValueType(); 2470 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 2471 2472 // fold (shl c1, c2) -> c1<<c2 2473 if (N0C && N1C) 2474 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C); 2475 // fold (shl 0, x) -> 0 2476 if (N0C && N0C->isNullValue()) 2477 return N0; 2478 // fold (shl x, c >= size(x)) -> undef 2479 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2480 return DAG.getUNDEF(VT); 2481 // fold (shl x, 0) -> x 2482 if (N1C && N1C->isNullValue()) 2483 return N0; 2484 // if (shl x, c) is known to be zero, return 0 2485 if (DAG.MaskedValueIsZero(SDValue(N, 0), 2486 APInt::getAllOnesValue(OpSizeInBits))) 2487 return DAG.getConstant(0, VT); 2488 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))). 2489 if (N1.getOpcode() == ISD::TRUNCATE && 2490 N1.getOperand(0).getOpcode() == ISD::AND && 2491 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2492 SDValue N101 = N1.getOperand(0).getOperand(1); 2493 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2494 EVT TruncVT = N1.getValueType(); 2495 SDValue N100 = N1.getOperand(0).getOperand(0); 2496 APInt TruncC = N101C->getAPIntValue(); 2497 TruncC.trunc(TruncVT.getSizeInBits()); 2498 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 2499 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT, 2500 DAG.getNode(ISD::TRUNCATE, 2501 N->getDebugLoc(), 2502 TruncVT, N100), 2503 DAG.getConstant(TruncC, TruncVT))); 2504 } 2505 } 2506 2507 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2508 return SDValue(N, 0); 2509 2510 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2)) 2511 if (N1C && N0.getOpcode() == ISD::SHL && 2512 N0.getOperand(1).getOpcode() == ISD::Constant) { 2513 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2514 uint64_t c2 = N1C->getZExtValue(); 2515 if (c1 + c2 > OpSizeInBits) 2516 return DAG.getConstant(0, VT); 2517 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 2518 DAG.getConstant(c1 + c2, N1.getValueType())); 2519 } 2520 // fold (shl (srl x, c1), c2) -> (shl (and x, (shl -1, c1)), (sub c2, c1)) or 2521 // (srl (and x, (shl -1, c1)), (sub c1, c2)) 2522 if (N1C && N0.getOpcode() == ISD::SRL && 2523 N0.getOperand(1).getOpcode() == ISD::Constant) { 2524 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2525 if (c1 < VT.getSizeInBits()) { 2526 uint64_t c2 = N1C->getZExtValue(); 2527 SDValue HiBitsMask = 2528 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 2529 VT.getSizeInBits() - c1), 2530 VT); 2531 SDValue Mask = DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, 2532 N0.getOperand(0), 2533 HiBitsMask); 2534 if (c2 > c1) 2535 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, Mask, 2536 DAG.getConstant(c2-c1, N1.getValueType())); 2537 else 2538 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Mask, 2539 DAG.getConstant(c1-c2, N1.getValueType())); 2540 } 2541 } 2542 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1)) 2543 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) { 2544 SDValue HiBitsMask = 2545 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 2546 VT.getSizeInBits() - 2547 N1C->getZExtValue()), 2548 VT); 2549 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 2550 HiBitsMask); 2551 } 2552 2553 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2554} 2555 2556SDValue DAGCombiner::visitSRA(SDNode *N) { 2557 SDValue N0 = N->getOperand(0); 2558 SDValue N1 = N->getOperand(1); 2559 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2560 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2561 EVT VT = N0.getValueType(); 2562 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 2563 2564 // fold (sra c1, c2) -> (sra c1, c2) 2565 if (N0C && N1C) 2566 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); 2567 // fold (sra 0, x) -> 0 2568 if (N0C && N0C->isNullValue()) 2569 return N0; 2570 // fold (sra -1, x) -> -1 2571 if (N0C && N0C->isAllOnesValue()) 2572 return N0; 2573 // fold (sra x, (setge c, size(x))) -> undef 2574 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2575 return DAG.getUNDEF(VT); 2576 // fold (sra x, 0) -> x 2577 if (N1C && N1C->isNullValue()) 2578 return N0; 2579 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 2580 // sext_inreg. 2581 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 2582 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue(); 2583 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits); 2584 if (VT.isVector()) 2585 ExtVT = EVT::getVectorVT(*DAG.getContext(), 2586 ExtVT, VT.getVectorNumElements()); 2587 if ((!LegalOperations || 2588 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT))) 2589 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 2590 N0.getOperand(0), DAG.getValueType(ExtVT)); 2591 } 2592 2593 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) 2594 if (N1C && N0.getOpcode() == ISD::SRA) { 2595 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2596 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); 2597 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1; 2598 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0), 2599 DAG.getConstant(Sum, N1C->getValueType(0))); 2600 } 2601 } 2602 2603 // fold (sra (shl X, m), (sub result_size, n)) 2604 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for 2605 // result_size - n != m. 2606 // If truncate is free for the target sext(shl) is likely to result in better 2607 // code. 2608 if (N0.getOpcode() == ISD::SHL) { 2609 // Get the two constanst of the shifts, CN0 = m, CN = n. 2610 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2611 if (N01C && N1C) { 2612 // Determine what the truncate's result bitsize and type would be. 2613 EVT TruncVT = 2614 EVT::getIntegerVT(*DAG.getContext(), OpSizeInBits - N1C->getZExtValue()); 2615 // Determine the residual right-shift amount. 2616 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); 2617 2618 // If the shift is not a no-op (in which case this should be just a sign 2619 // extend already), the truncated to type is legal, sign_extend is legal 2620 // on that type, and the the truncate to that type is both legal and free, 2621 // perform the transform. 2622 if ((ShiftAmt > 0) && 2623 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) && 2624 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) && 2625 TLI.isTruncateFree(VT, TruncVT)) { 2626 2627 SDValue Amt = DAG.getConstant(ShiftAmt, getShiftAmountTy()); 2628 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, 2629 N0.getOperand(0), Amt); 2630 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT, 2631 Shift); 2632 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), 2633 N->getValueType(0), Trunc); 2634 } 2635 } 2636 } 2637 2638 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))). 2639 if (N1.getOpcode() == ISD::TRUNCATE && 2640 N1.getOperand(0).getOpcode() == ISD::AND && 2641 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2642 SDValue N101 = N1.getOperand(0).getOperand(1); 2643 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2644 EVT TruncVT = N1.getValueType(); 2645 SDValue N100 = N1.getOperand(0).getOperand(0); 2646 APInt TruncC = N101C->getAPIntValue(); 2647 TruncC.trunc(TruncVT.getScalarType().getSizeInBits()); 2648 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 2649 DAG.getNode(ISD::AND, N->getDebugLoc(), 2650 TruncVT, 2651 DAG.getNode(ISD::TRUNCATE, 2652 N->getDebugLoc(), 2653 TruncVT, N100), 2654 DAG.getConstant(TruncC, TruncVT))); 2655 } 2656 } 2657 2658 // Simplify, based on bits shifted out of the LHS. 2659 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2660 return SDValue(N, 0); 2661 2662 2663 // If the sign bit is known to be zero, switch this to a SRL. 2664 if (DAG.SignBitIsZero(N0)) 2665 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1); 2666 2667 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2668} 2669 2670SDValue DAGCombiner::visitSRL(SDNode *N) { 2671 SDValue N0 = N->getOperand(0); 2672 SDValue N1 = N->getOperand(1); 2673 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2674 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2675 EVT VT = N0.getValueType(); 2676 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 2677 2678 // fold (srl c1, c2) -> c1 >>u c2 2679 if (N0C && N1C) 2680 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); 2681 // fold (srl 0, x) -> 0 2682 if (N0C && N0C->isNullValue()) 2683 return N0; 2684 // fold (srl x, c >= size(x)) -> undef 2685 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2686 return DAG.getUNDEF(VT); 2687 // fold (srl x, 0) -> x 2688 if (N1C && N1C->isNullValue()) 2689 return N0; 2690 // if (srl x, c) is known to be zero, return 0 2691 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2692 APInt::getAllOnesValue(OpSizeInBits))) 2693 return DAG.getConstant(0, VT); 2694 2695 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2)) 2696 if (N1C && N0.getOpcode() == ISD::SRL && 2697 N0.getOperand(1).getOpcode() == ISD::Constant) { 2698 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2699 uint64_t c2 = N1C->getZExtValue(); 2700 if (c1 + c2 > OpSizeInBits) 2701 return DAG.getConstant(0, VT); 2702 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 2703 DAG.getConstant(c1 + c2, N1.getValueType())); 2704 } 2705 2706 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 2707 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2708 // Shifting in all undef bits? 2709 EVT SmallVT = N0.getOperand(0).getValueType(); 2710 if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) 2711 return DAG.getUNDEF(VT); 2712 2713 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT, 2714 N0.getOperand(0), N1); 2715 AddToWorkList(SmallShift.getNode()); 2716 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift); 2717 } 2718 2719 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 2720 // bit, which is unmodified by sra. 2721 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) { 2722 if (N0.getOpcode() == ISD::SRA) 2723 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1); 2724 } 2725 2726 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 2727 if (N1C && N0.getOpcode() == ISD::CTLZ && 2728 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 2729 APInt KnownZero, KnownOne; 2730 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 2731 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 2732 2733 // If any of the input bits are KnownOne, then the input couldn't be all 2734 // zeros, thus the result of the srl will always be zero. 2735 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 2736 2737 // If all of the bits input the to ctlz node are known to be zero, then 2738 // the result of the ctlz is "32" and the result of the shift is one. 2739 APInt UnknownBits = ~KnownZero & Mask; 2740 if (UnknownBits == 0) return DAG.getConstant(1, VT); 2741 2742 // Otherwise, check to see if there is exactly one bit input to the ctlz. 2743 if ((UnknownBits & (UnknownBits - 1)) == 0) { 2744 // Okay, we know that only that the single bit specified by UnknownBits 2745 // could be set on input to the CTLZ node. If this bit is set, the SRL 2746 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 2747 // to an SRL/XOR pair, which is likely to simplify more. 2748 unsigned ShAmt = UnknownBits.countTrailingZeros(); 2749 SDValue Op = N0.getOperand(0); 2750 2751 if (ShAmt) { 2752 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op, 2753 DAG.getConstant(ShAmt, getShiftAmountTy())); 2754 AddToWorkList(Op.getNode()); 2755 } 2756 2757 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 2758 Op, DAG.getConstant(1, VT)); 2759 } 2760 } 2761 2762 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))). 2763 if (N1.getOpcode() == ISD::TRUNCATE && 2764 N1.getOperand(0).getOpcode() == ISD::AND && 2765 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2766 SDValue N101 = N1.getOperand(0).getOperand(1); 2767 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2768 EVT TruncVT = N1.getValueType(); 2769 SDValue N100 = N1.getOperand(0).getOperand(0); 2770 APInt TruncC = N101C->getAPIntValue(); 2771 TruncC.trunc(TruncVT.getSizeInBits()); 2772 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 2773 DAG.getNode(ISD::AND, N->getDebugLoc(), 2774 TruncVT, 2775 DAG.getNode(ISD::TRUNCATE, 2776 N->getDebugLoc(), 2777 TruncVT, N100), 2778 DAG.getConstant(TruncC, TruncVT))); 2779 } 2780 } 2781 2782 // fold operands of srl based on knowledge that the low bits are not 2783 // demanded. 2784 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2785 return SDValue(N, 0); 2786 2787 if (N1C) { 2788 SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue()); 2789 if (NewSRL.getNode()) 2790 return NewSRL; 2791 } 2792 2793 // Here is a common situation. We want to optimize: 2794 // 2795 // %a = ... 2796 // %b = and i32 %a, 2 2797 // %c = srl i32 %b, 1 2798 // brcond i32 %c ... 2799 // 2800 // into 2801 // 2802 // %a = ... 2803 // %b = and %a, 2 2804 // %c = setcc eq %b, 0 2805 // brcond %c ... 2806 // 2807 // However when after the source operand of SRL is optimized into AND, the SRL 2808 // itself may not be optimized further. Look for it and add the BRCOND into 2809 // the worklist. 2810 if (N->hasOneUse()) { 2811 SDNode *Use = *N->use_begin(); 2812 if (Use->getOpcode() == ISD::BRCOND) 2813 AddToWorkList(Use); 2814 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) { 2815 // Also look pass the truncate. 2816 Use = *Use->use_begin(); 2817 if (Use->getOpcode() == ISD::BRCOND) 2818 AddToWorkList(Use); 2819 } 2820 } 2821 2822 return SDValue(); 2823} 2824 2825SDValue DAGCombiner::visitCTLZ(SDNode *N) { 2826 SDValue N0 = N->getOperand(0); 2827 EVT VT = N->getValueType(0); 2828 2829 // fold (ctlz c1) -> c2 2830 if (isa<ConstantSDNode>(N0)) 2831 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0); 2832 return SDValue(); 2833} 2834 2835SDValue DAGCombiner::visitCTTZ(SDNode *N) { 2836 SDValue N0 = N->getOperand(0); 2837 EVT VT = N->getValueType(0); 2838 2839 // fold (cttz c1) -> c2 2840 if (isa<ConstantSDNode>(N0)) 2841 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0); 2842 return SDValue(); 2843} 2844 2845SDValue DAGCombiner::visitCTPOP(SDNode *N) { 2846 SDValue N0 = N->getOperand(0); 2847 EVT VT = N->getValueType(0); 2848 2849 // fold (ctpop c1) -> c2 2850 if (isa<ConstantSDNode>(N0)) 2851 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0); 2852 return SDValue(); 2853} 2854 2855SDValue DAGCombiner::visitSELECT(SDNode *N) { 2856 SDValue N0 = N->getOperand(0); 2857 SDValue N1 = N->getOperand(1); 2858 SDValue N2 = N->getOperand(2); 2859 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2860 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2861 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 2862 EVT VT = N->getValueType(0); 2863 EVT VT0 = N0.getValueType(); 2864 2865 // fold (select C, X, X) -> X 2866 if (N1 == N2) 2867 return N1; 2868 // fold (select true, X, Y) -> X 2869 if (N0C && !N0C->isNullValue()) 2870 return N1; 2871 // fold (select false, X, Y) -> Y 2872 if (N0C && N0C->isNullValue()) 2873 return N2; 2874 // fold (select C, 1, X) -> (or C, X) 2875 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 2876 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 2877 // fold (select C, 0, 1) -> (xor C, 1) 2878 if (VT.isInteger() && 2879 (VT0 == MVT::i1 || 2880 (VT0.isInteger() && 2881 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) && 2882 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 2883 SDValue XORNode; 2884 if (VT == VT0) 2885 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0, 2886 N0, DAG.getConstant(1, VT0)); 2887 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0, 2888 N0, DAG.getConstant(1, VT0)); 2889 AddToWorkList(XORNode.getNode()); 2890 if (VT.bitsGT(VT0)) 2891 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode); 2892 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode); 2893 } 2894 // fold (select C, 0, X) -> (and (not C), X) 2895 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 2896 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 2897 AddToWorkList(NOTNode.getNode()); 2898 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2); 2899 } 2900 // fold (select C, X, 1) -> (or (not C), X) 2901 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 2902 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 2903 AddToWorkList(NOTNode.getNode()); 2904 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1); 2905 } 2906 // fold (select C, X, 0) -> (and C, X) 2907 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 2908 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 2909 // fold (select X, X, Y) -> (or X, Y) 2910 // fold (select X, 1, Y) -> (or X, Y) 2911 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1))) 2912 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 2913 // fold (select X, Y, X) -> (and X, Y) 2914 // fold (select X, Y, 0) -> (and X, Y) 2915 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0))) 2916 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 2917 2918 // If we can fold this based on the true/false value, do so. 2919 if (SimplifySelectOps(N, N1, N2)) 2920 return SDValue(N, 0); // Don't revisit N. 2921 2922 // fold selects based on a setcc into other things, such as min/max/abs 2923 if (N0.getOpcode() == ISD::SETCC) { 2924 // FIXME: 2925 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 2926 // having to say they don't support SELECT_CC on every type the DAG knows 2927 // about, since there is no way to mark an opcode illegal at all value types 2928 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) && 2929 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT)) 2930 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, 2931 N0.getOperand(0), N0.getOperand(1), 2932 N1, N2, N0.getOperand(2)); 2933 return SimplifySelect(N->getDebugLoc(), N0, N1, N2); 2934 } 2935 2936 return SDValue(); 2937} 2938 2939SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 2940 SDValue N0 = N->getOperand(0); 2941 SDValue N1 = N->getOperand(1); 2942 SDValue N2 = N->getOperand(2); 2943 SDValue N3 = N->getOperand(3); 2944 SDValue N4 = N->getOperand(4); 2945 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 2946 2947 // fold select_cc lhs, rhs, x, x, cc -> x 2948 if (N2 == N3) 2949 return N2; 2950 2951 // Determine if the condition we're dealing with is constant 2952 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 2953 N0, N1, CC, N->getDebugLoc(), false); 2954 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 2955 2956 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) { 2957 if (!SCCC->isNullValue()) 2958 return N2; // cond always true -> true val 2959 else 2960 return N3; // cond always false -> false val 2961 } 2962 2963 // Fold to a simpler select_cc 2964 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) 2965 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(), 2966 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 2967 SCC.getOperand(2)); 2968 2969 // If we can fold this based on the true/false value, do so. 2970 if (SimplifySelectOps(N, N2, N3)) 2971 return SDValue(N, 0); // Don't revisit N. 2972 2973 // fold select_cc into other things, such as min/max/abs 2974 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC); 2975} 2976 2977SDValue DAGCombiner::visitSETCC(SDNode *N) { 2978 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 2979 cast<CondCodeSDNode>(N->getOperand(2))->get(), 2980 N->getDebugLoc()); 2981} 2982 2983// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 2984// "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))" 2985// transformation. Returns true if extension are possible and the above 2986// mentioned transformation is profitable. 2987static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 2988 unsigned ExtOpc, 2989 SmallVector<SDNode*, 4> &ExtendNodes, 2990 const TargetLowering &TLI) { 2991 bool HasCopyToRegUses = false; 2992 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 2993 for (SDNode::use_iterator UI = N0.getNode()->use_begin(), 2994 UE = N0.getNode()->use_end(); 2995 UI != UE; ++UI) { 2996 SDNode *User = *UI; 2997 if (User == N) 2998 continue; 2999 if (UI.getUse().getResNo() != N0.getResNo()) 3000 continue; 3001 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 3002 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { 3003 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 3004 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 3005 // Sign bits will be lost after a zext. 3006 return false; 3007 bool Add = false; 3008 for (unsigned i = 0; i != 2; ++i) { 3009 SDValue UseOp = User->getOperand(i); 3010 if (UseOp == N0) 3011 continue; 3012 if (!isa<ConstantSDNode>(UseOp)) 3013 return false; 3014 Add = true; 3015 } 3016 if (Add) 3017 ExtendNodes.push_back(User); 3018 continue; 3019 } 3020 // If truncates aren't free and there are users we can't 3021 // extend, it isn't worthwhile. 3022 if (!isTruncFree) 3023 return false; 3024 // Remember if this value is live-out. 3025 if (User->getOpcode() == ISD::CopyToReg) 3026 HasCopyToRegUses = true; 3027 } 3028 3029 if (HasCopyToRegUses) { 3030 bool BothLiveOut = false; 3031 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 3032 UI != UE; ++UI) { 3033 SDUse &Use = UI.getUse(); 3034 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) { 3035 BothLiveOut = true; 3036 break; 3037 } 3038 } 3039 if (BothLiveOut) 3040 // Both unextended and extended values are live out. There had better be 3041 // good a reason for the transformation. 3042 return ExtendNodes.size(); 3043 } 3044 return true; 3045} 3046 3047SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 3048 SDValue N0 = N->getOperand(0); 3049 EVT VT = N->getValueType(0); 3050 3051 // fold (sext c1) -> c1 3052 if (isa<ConstantSDNode>(N0)) 3053 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0); 3054 3055 // fold (sext (sext x)) -> (sext x) 3056 // fold (sext (aext x)) -> (sext x) 3057 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 3058 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, 3059 N0.getOperand(0)); 3060 3061 if (N0.getOpcode() == ISD::TRUNCATE) { 3062 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 3063 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 3064 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3065 if (NarrowLoad.getNode()) { 3066 if (NarrowLoad.getNode() != N0.getNode()) 3067 CombineTo(N0.getNode(), NarrowLoad); 3068 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3069 } 3070 3071 // See if the value being truncated is already sign extended. If so, just 3072 // eliminate the trunc/sext pair. 3073 SDValue Op = N0.getOperand(0); 3074 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits(); 3075 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits(); 3076 unsigned DestBits = VT.getScalarType().getSizeInBits(); 3077 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 3078 3079 if (OpBits == DestBits) { 3080 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 3081 // bits, it is already ready. 3082 if (NumSignBits > DestBits-MidBits) 3083 return Op; 3084 } else if (OpBits < DestBits) { 3085 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 3086 // bits, just sext from i32. 3087 if (NumSignBits > OpBits-MidBits) 3088 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op); 3089 } else { 3090 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 3091 // bits, just truncate to i32. 3092 if (NumSignBits > OpBits-MidBits) 3093 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 3094 } 3095 3096 // fold (sext (truncate x)) -> (sextinreg x). 3097 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 3098 N0.getValueType())) { 3099 if (OpBits < DestBits) 3100 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op); 3101 else if (OpBits > DestBits) 3102 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op); 3103 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op, 3104 DAG.getValueType(N0.getValueType())); 3105 } 3106 } 3107 3108 // fold (sext (load x)) -> (sext (truncate (sextload x))) 3109 if (ISD::isNON_EXTLoad(N0.getNode()) && 3110 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3111 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { 3112 bool DoXform = true; 3113 SmallVector<SDNode*, 4> SetCCs; 3114 if (!N0.hasOneUse()) 3115 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 3116 if (DoXform) { 3117 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3118 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3119 LN0->getChain(), 3120 LN0->getBasePtr(), LN0->getSrcValue(), 3121 LN0->getSrcValueOffset(), 3122 N0.getValueType(), 3123 LN0->isVolatile(), LN0->getAlignment()); 3124 CombineTo(N, ExtLoad); 3125 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3126 N0.getValueType(), ExtLoad); 3127 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3128 3129 // Extend SetCC uses if necessary. 3130 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3131 SDNode *SetCC = SetCCs[i]; 3132 SmallVector<SDValue, 4> Ops; 3133 3134 for (unsigned j = 0; j != 2; ++j) { 3135 SDValue SOp = SetCC->getOperand(j); 3136 if (SOp == Trunc) 3137 Ops.push_back(ExtLoad); 3138 else 3139 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, 3140 N->getDebugLoc(), VT, SOp)); 3141 } 3142 3143 Ops.push_back(SetCC->getOperand(2)); 3144 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3145 SetCC->getValueType(0), 3146 &Ops[0], Ops.size())); 3147 } 3148 3149 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3150 } 3151 } 3152 3153 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 3154 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 3155 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3156 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3157 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3158 EVT MemVT = LN0->getMemoryVT(); 3159 if ((!LegalOperations && !LN0->isVolatile()) || 3160 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) { 3161 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3162 LN0->getChain(), 3163 LN0->getBasePtr(), LN0->getSrcValue(), 3164 LN0->getSrcValueOffset(), MemVT, 3165 LN0->isVolatile(), LN0->getAlignment()); 3166 CombineTo(N, ExtLoad); 3167 CombineTo(N0.getNode(), 3168 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3169 N0.getValueType(), ExtLoad), 3170 ExtLoad.getValue(1)); 3171 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3172 } 3173 } 3174 3175 if (N0.getOpcode() == ISD::SETCC) { 3176 // sext(setcc) -> sext_in_reg(vsetcc) for vectors. 3177 if (VT.isVector() && 3178 // We know that the # elements of the results is the same as the 3179 // # elements of the compare (and the # elements of the compare result 3180 // for that matter). Check to see that they are the same size. If so, 3181 // we know that the element size of the sext'd result matches the 3182 // element size of the compare operands. 3183 VT.getSizeInBits() == N0.getOperand(0).getValueType().getSizeInBits() && 3184 3185 // Only do this before legalize for now. 3186 !LegalOperations) { 3187 return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 3188 N0.getOperand(1), 3189 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 3190 } 3191 3192 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc) 3193 SDValue NegOne = 3194 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT); 3195 SDValue SCC = 3196 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3197 NegOne, DAG.getConstant(0, VT), 3198 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3199 if (SCC.getNode()) return SCC; 3200 } 3201 3202 3203 3204 // fold (sext x) -> (zext x) if the sign bit is known zero. 3205 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 3206 DAG.SignBitIsZero(N0)) 3207 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3208 3209 return SDValue(); 3210} 3211 3212SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 3213 SDValue N0 = N->getOperand(0); 3214 EVT VT = N->getValueType(0); 3215 3216 // fold (zext c1) -> c1 3217 if (isa<ConstantSDNode>(N0)) 3218 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3219 // fold (zext (zext x)) -> (zext x) 3220 // fold (zext (aext x)) -> (zext x) 3221 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 3222 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, 3223 N0.getOperand(0)); 3224 3225 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 3226 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 3227 if (N0.getOpcode() == ISD::TRUNCATE) { 3228 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3229 if (NarrowLoad.getNode()) { 3230 if (NarrowLoad.getNode() != N0.getNode()) 3231 CombineTo(N0.getNode(), NarrowLoad); 3232 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 3233 } 3234 } 3235 3236 // fold (zext (truncate x)) -> (and x, mask) 3237 if (N0.getOpcode() == ISD::TRUNCATE && 3238 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT)) && 3239 (!TLI.isTruncateFree(N0.getOperand(0).getValueType(), 3240 N0.getValueType()) || 3241 !TLI.isZExtFree(N0.getValueType(), VT))) { 3242 SDValue Op = N0.getOperand(0); 3243 if (Op.getValueType().bitsLT(VT)) { 3244 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op); 3245 } else if (Op.getValueType().bitsGT(VT)) { 3246 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 3247 } 3248 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), 3249 N0.getValueType().getScalarType()); 3250 } 3251 3252 // Fold (zext (and (trunc x), cst)) -> (and x, cst), 3253 // if either of the casts is not free. 3254 if (N0.getOpcode() == ISD::AND && 3255 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3256 N0.getOperand(1).getOpcode() == ISD::Constant && 3257 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 3258 N0.getValueType()) || 3259 !TLI.isZExtFree(N0.getValueType(), VT))) { 3260 SDValue X = N0.getOperand(0).getOperand(0); 3261 if (X.getValueType().bitsLT(VT)) { 3262 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X); 3263 } else if (X.getValueType().bitsGT(VT)) { 3264 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 3265 } 3266 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3267 Mask.zext(VT.getSizeInBits()); 3268 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3269 X, DAG.getConstant(Mask, VT)); 3270 } 3271 3272 // fold (zext (load x)) -> (zext (truncate (zextload x))) 3273 if (ISD::isNON_EXTLoad(N0.getNode()) && 3274 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3275 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 3276 bool DoXform = true; 3277 SmallVector<SDNode*, 4> SetCCs; 3278 if (!N0.hasOneUse()) 3279 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 3280 if (DoXform) { 3281 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3282 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 3283 LN0->getChain(), 3284 LN0->getBasePtr(), LN0->getSrcValue(), 3285 LN0->getSrcValueOffset(), 3286 N0.getValueType(), 3287 LN0->isVolatile(), LN0->getAlignment()); 3288 CombineTo(N, ExtLoad); 3289 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3290 N0.getValueType(), ExtLoad); 3291 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3292 3293 // Extend SetCC uses if necessary. 3294 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3295 SDNode *SetCC = SetCCs[i]; 3296 SmallVector<SDValue, 4> Ops; 3297 3298 for (unsigned j = 0; j != 2; ++j) { 3299 SDValue SOp = SetCC->getOperand(j); 3300 if (SOp == Trunc) 3301 Ops.push_back(ExtLoad); 3302 else 3303 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, 3304 N->getDebugLoc(), VT, SOp)); 3305 } 3306 3307 Ops.push_back(SetCC->getOperand(2)); 3308 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3309 SetCC->getValueType(0), 3310 &Ops[0], Ops.size())); 3311 } 3312 3313 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3314 } 3315 } 3316 3317 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 3318 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 3319 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3320 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3321 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3322 EVT MemVT = LN0->getMemoryVT(); 3323 if ((!LegalOperations && !LN0->isVolatile()) || 3324 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) { 3325 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 3326 LN0->getChain(), 3327 LN0->getBasePtr(), LN0->getSrcValue(), 3328 LN0->getSrcValueOffset(), MemVT, 3329 LN0->isVolatile(), LN0->getAlignment()); 3330 CombineTo(N, ExtLoad); 3331 CombineTo(N0.getNode(), 3332 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(), 3333 ExtLoad), 3334 ExtLoad.getValue(1)); 3335 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3336 } 3337 } 3338 3339 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3340 if (N0.getOpcode() == ISD::SETCC) { 3341 SDValue SCC = 3342 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3343 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3344 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3345 if (SCC.getNode()) return SCC; 3346 } 3347 3348 // (zext (shl (zext x), cst)) -> (shl (zext x), cst) 3349 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && 3350 isa<ConstantSDNode>(N0.getOperand(1)) && 3351 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && 3352 N0.hasOneUse()) { 3353 if (N0.getOpcode() == ISD::SHL) { 3354 // If the original shl may be shifting out bits, do not perform this 3355 // transformation. 3356 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3357 unsigned KnownZeroBits = N0.getOperand(0).getValueType().getSizeInBits() - 3358 N0.getOperand(0).getOperand(0).getValueType().getSizeInBits(); 3359 if (ShAmt > KnownZeroBits) 3360 return SDValue(); 3361 } 3362 DebugLoc dl = N->getDebugLoc(); 3363 return DAG.getNode(N0.getOpcode(), dl, VT, 3364 DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0.getOperand(0)), 3365 DAG.getNode(ISD::ZERO_EXTEND, dl, 3366 N0.getOperand(1).getValueType(), 3367 N0.getOperand(1))); 3368 } 3369 3370 return SDValue(); 3371} 3372 3373SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 3374 SDValue N0 = N->getOperand(0); 3375 EVT VT = N->getValueType(0); 3376 3377 // fold (aext c1) -> c1 3378 if (isa<ConstantSDNode>(N0)) 3379 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0); 3380 // fold (aext (aext x)) -> (aext x) 3381 // fold (aext (zext x)) -> (zext x) 3382 // fold (aext (sext x)) -> (sext x) 3383 if (N0.getOpcode() == ISD::ANY_EXTEND || 3384 N0.getOpcode() == ISD::ZERO_EXTEND || 3385 N0.getOpcode() == ISD::SIGN_EXTEND) 3386 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0)); 3387 3388 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 3389 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 3390 if (N0.getOpcode() == ISD::TRUNCATE) { 3391 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3392 if (NarrowLoad.getNode()) { 3393 if (NarrowLoad.getNode() != N0.getNode()) 3394 CombineTo(N0.getNode(), NarrowLoad); 3395 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 3396 } 3397 } 3398 3399 // fold (aext (truncate x)) 3400 if (N0.getOpcode() == ISD::TRUNCATE) { 3401 SDValue TruncOp = N0.getOperand(0); 3402 if (TruncOp.getValueType() == VT) 3403 return TruncOp; // x iff x size == zext size. 3404 if (TruncOp.getValueType().bitsGT(VT)) 3405 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp); 3406 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp); 3407 } 3408 3409 // Fold (aext (and (trunc x), cst)) -> (and x, cst) 3410 // if the trunc is not free. 3411 if (N0.getOpcode() == ISD::AND && 3412 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3413 N0.getOperand(1).getOpcode() == ISD::Constant && 3414 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 3415 N0.getValueType())) { 3416 SDValue X = N0.getOperand(0).getOperand(0); 3417 if (X.getValueType().bitsLT(VT)) { 3418 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X); 3419 } else if (X.getValueType().bitsGT(VT)) { 3420 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X); 3421 } 3422 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3423 Mask.zext(VT.getSizeInBits()); 3424 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3425 X, DAG.getConstant(Mask, VT)); 3426 } 3427 3428 // fold (aext (load x)) -> (aext (truncate (extload x))) 3429 if (ISD::isNON_EXTLoad(N0.getNode()) && 3430 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3431 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 3432 bool DoXform = true; 3433 SmallVector<SDNode*, 4> SetCCs; 3434 if (!N0.hasOneUse()) 3435 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI); 3436 if (DoXform) { 3437 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3438 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 3439 LN0->getChain(), 3440 LN0->getBasePtr(), LN0->getSrcValue(), 3441 LN0->getSrcValueOffset(), 3442 N0.getValueType(), 3443 LN0->isVolatile(), LN0->getAlignment()); 3444 CombineTo(N, ExtLoad); 3445 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3446 N0.getValueType(), ExtLoad); 3447 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3448 3449 // Extend SetCC uses if necessary. 3450 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3451 SDNode *SetCC = SetCCs[i]; 3452 SmallVector<SDValue, 4> Ops; 3453 3454 for (unsigned j = 0; j != 2; ++j) { 3455 SDValue SOp = SetCC->getOperand(j); 3456 if (SOp == Trunc) 3457 Ops.push_back(ExtLoad); 3458 else 3459 Ops.push_back(DAG.getNode(ISD::ANY_EXTEND, 3460 N->getDebugLoc(), VT, SOp)); 3461 } 3462 3463 Ops.push_back(SetCC->getOperand(2)); 3464 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3465 SetCC->getValueType(0), 3466 &Ops[0], Ops.size())); 3467 } 3468 3469 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3470 } 3471 } 3472 3473 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 3474 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 3475 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 3476 if (N0.getOpcode() == ISD::LOAD && 3477 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3478 N0.hasOneUse()) { 3479 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3480 EVT MemVT = LN0->getMemoryVT(); 3481 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(), 3482 VT, LN0->getChain(), LN0->getBasePtr(), 3483 LN0->getSrcValue(), 3484 LN0->getSrcValueOffset(), MemVT, 3485 LN0->isVolatile(), LN0->getAlignment()); 3486 CombineTo(N, ExtLoad); 3487 CombineTo(N0.getNode(), 3488 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3489 N0.getValueType(), ExtLoad), 3490 ExtLoad.getValue(1)); 3491 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3492 } 3493 3494 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3495 if (N0.getOpcode() == ISD::SETCC) { 3496 SDValue SCC = 3497 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3498 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3499 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3500 if (SCC.getNode()) 3501 return SCC; 3502 } 3503 3504 return SDValue(); 3505} 3506 3507/// GetDemandedBits - See if the specified operand can be simplified with the 3508/// knowledge that only the bits specified by Mask are used. If so, return the 3509/// simpler operand, otherwise return a null SDValue. 3510SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 3511 switch (V.getOpcode()) { 3512 default: break; 3513 case ISD::OR: 3514 case ISD::XOR: 3515 // If the LHS or RHS don't contribute bits to the or, drop them. 3516 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 3517 return V.getOperand(1); 3518 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 3519 return V.getOperand(0); 3520 break; 3521 case ISD::SRL: 3522 // Only look at single-use SRLs. 3523 if (!V.getNode()->hasOneUse()) 3524 break; 3525 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 3526 // See if we can recursively simplify the LHS. 3527 unsigned Amt = RHSC->getZExtValue(); 3528 3529 // Watch out for shift count overflow though. 3530 if (Amt >= Mask.getBitWidth()) break; 3531 APInt NewMask = Mask << Amt; 3532 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 3533 if (SimplifyLHS.getNode()) 3534 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(), 3535 SimplifyLHS, V.getOperand(1)); 3536 } 3537 } 3538 return SDValue(); 3539} 3540 3541/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 3542/// bits and then truncated to a narrower type and where N is a multiple 3543/// of number of bits of the narrower type, transform it to a narrower load 3544/// from address + N / num of bits of new type. If the result is to be 3545/// extended, also fold the extension to form a extending load. 3546SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 3547 unsigned Opc = N->getOpcode(); 3548 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 3549 SDValue N0 = N->getOperand(0); 3550 EVT VT = N->getValueType(0); 3551 EVT ExtVT = VT; 3552 3553 // This transformation isn't valid for vector loads. 3554 if (VT.isVector()) 3555 return SDValue(); 3556 3557 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then 3558 // extended to VT. 3559 if (Opc == ISD::SIGN_EXTEND_INREG) { 3560 ExtType = ISD::SEXTLOAD; 3561 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3562 if (LegalOperations && !TLI.isLoadExtLegal(ISD::SEXTLOAD, ExtVT)) 3563 return SDValue(); 3564 } 3565 3566 unsigned EVTBits = ExtVT.getSizeInBits(); 3567 unsigned ShAmt = 0; 3568 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse() && ExtVT.isRound()) { 3569 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3570 ShAmt = N01->getZExtValue(); 3571 // Is the shift amount a multiple of size of VT? 3572 if ((ShAmt & (EVTBits-1)) == 0) { 3573 N0 = N0.getOperand(0); 3574 // Is the load width a multiple of size of VT? 3575 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0) 3576 return SDValue(); 3577 } 3578 } 3579 } 3580 3581 // Do not generate loads of non-round integer types since these can 3582 // be expensive (and would be wrong if the type is not byte sized). 3583 if (isa<LoadSDNode>(N0) && N0.hasOneUse() && ExtVT.isRound() && 3584 cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() > EVTBits && 3585 // Do not change the width of a volatile load. 3586 !cast<LoadSDNode>(N0)->isVolatile()) { 3587 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3588 EVT PtrType = N0.getOperand(1).getValueType(); 3589 3590 // For big endian targets, we need to adjust the offset to the pointer to 3591 // load the correct bytes. 3592 if (TLI.isBigEndian()) { 3593 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 3594 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits(); 3595 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 3596 } 3597 3598 uint64_t PtrOff = ShAmt / 8; 3599 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 3600 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), 3601 PtrType, LN0->getBasePtr(), 3602 DAG.getConstant(PtrOff, PtrType)); 3603 AddToWorkList(NewPtr.getNode()); 3604 3605 SDValue Load = (ExtType == ISD::NON_EXTLOAD) 3606 ? DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr, 3607 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3608 LN0->isVolatile(), NewAlign) 3609 : DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(), NewPtr, 3610 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3611 ExtVT, LN0->isVolatile(), NewAlign); 3612 3613 // Replace the old load's chain with the new load's chain. 3614 WorkListRemover DeadNodes(*this); 3615 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), 3616 &DeadNodes); 3617 3618 // Return the new loaded value. 3619 return Load; 3620 } 3621 3622 return SDValue(); 3623} 3624 3625SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 3626 SDValue N0 = N->getOperand(0); 3627 SDValue N1 = N->getOperand(1); 3628 EVT VT = N->getValueType(0); 3629 EVT EVT = cast<VTSDNode>(N1)->getVT(); 3630 unsigned VTBits = VT.getScalarType().getSizeInBits(); 3631 unsigned EVTBits = EVT.getScalarType().getSizeInBits(); 3632 3633 // fold (sext_in_reg c1) -> c1 3634 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 3635 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1); 3636 3637 // If the input is already sign extended, just drop the extension. 3638 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1) 3639 return N0; 3640 3641 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 3642 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 3643 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 3644 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 3645 N0.getOperand(0), N1); 3646 } 3647 3648 // fold (sext_in_reg (sext x)) -> (sext x) 3649 // fold (sext_in_reg (aext x)) -> (sext x) 3650 // if x is small enough. 3651 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 3652 SDValue N00 = N0.getOperand(0); 3653 if (N00.getValueType().getScalarType().getSizeInBits() < EVTBits) 3654 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1); 3655 } 3656 3657 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 3658 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 3659 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT); 3660 3661 // fold operands of sext_in_reg based on knowledge that the top bits are not 3662 // demanded. 3663 if (SimplifyDemandedBits(SDValue(N, 0))) 3664 return SDValue(N, 0); 3665 3666 // fold (sext_in_reg (load x)) -> (smaller sextload x) 3667 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 3668 SDValue NarrowLoad = ReduceLoadWidth(N); 3669 if (NarrowLoad.getNode()) 3670 return NarrowLoad; 3671 3672 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24) 3673 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible. 3674 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 3675 if (N0.getOpcode() == ISD::SRL) { 3676 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 3677 if (ShAmt->getZExtValue()+EVTBits <= VTBits) { 3678 // We can turn this into an SRA iff the input to the SRL is already sign 3679 // extended enough. 3680 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 3681 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits) 3682 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, 3683 N0.getOperand(0), N0.getOperand(1)); 3684 } 3685 } 3686 3687 // fold (sext_inreg (extload x)) -> (sextload x) 3688 if (ISD::isEXTLoad(N0.getNode()) && 3689 ISD::isUNINDEXEDLoad(N0.getNode()) && 3690 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3691 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3692 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 3693 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3694 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3695 LN0->getChain(), 3696 LN0->getBasePtr(), LN0->getSrcValue(), 3697 LN0->getSrcValueOffset(), EVT, 3698 LN0->isVolatile(), LN0->getAlignment()); 3699 CombineTo(N, ExtLoad); 3700 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 3701 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3702 } 3703 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 3704 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3705 N0.hasOneUse() && 3706 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3707 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3708 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 3709 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3710 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3711 LN0->getChain(), 3712 LN0->getBasePtr(), LN0->getSrcValue(), 3713 LN0->getSrcValueOffset(), EVT, 3714 LN0->isVolatile(), LN0->getAlignment()); 3715 CombineTo(N, ExtLoad); 3716 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 3717 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3718 } 3719 return SDValue(); 3720} 3721 3722SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 3723 SDValue N0 = N->getOperand(0); 3724 EVT VT = N->getValueType(0); 3725 3726 // noop truncate 3727 if (N0.getValueType() == N->getValueType(0)) 3728 return N0; 3729 // fold (truncate c1) -> c1 3730 if (isa<ConstantSDNode>(N0)) 3731 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0); 3732 // fold (truncate (truncate x)) -> (truncate x) 3733 if (N0.getOpcode() == ISD::TRUNCATE) 3734 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 3735 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 3736 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| 3737 N0.getOpcode() == ISD::ANY_EXTEND) { 3738 if (N0.getOperand(0).getValueType().bitsLT(VT)) 3739 // if the source is smaller than the dest, we still need an extend 3740 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 3741 N0.getOperand(0)); 3742 else if (N0.getOperand(0).getValueType().bitsGT(VT)) 3743 // if the source is larger than the dest, than we just need the truncate 3744 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 3745 else 3746 // if the source and dest are the same type, we can drop both the extend 3747 // and the truncate. 3748 return N0.getOperand(0); 3749 } 3750 3751 // See if we can simplify the input to this truncate through knowledge that 3752 // only the low bits are being used. For example "trunc (or (shl x, 8), y)" 3753 // -> trunc y 3754 SDValue Shorter = 3755 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 3756 VT.getSizeInBits())); 3757 if (Shorter.getNode()) 3758 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter); 3759 3760 // fold (truncate (load x)) -> (smaller load x) 3761 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 3762 return ReduceLoadWidth(N); 3763} 3764 3765static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 3766 SDValue Elt = N->getOperand(i); 3767 if (Elt.getOpcode() != ISD::MERGE_VALUES) 3768 return Elt.getNode(); 3769 return Elt.getOperand(Elt.getResNo()).getNode(); 3770} 3771 3772/// CombineConsecutiveLoads - build_pair (load, load) -> load 3773/// if load locations are consecutive. 3774SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) { 3775 assert(N->getOpcode() == ISD::BUILD_PAIR); 3776 3777 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0)); 3778 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1)); 3779 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse()) 3780 return SDValue(); 3781 EVT LD1VT = LD1->getValueType(0); 3782 3783 if (ISD::isNON_EXTLoad(LD2) && 3784 LD2->hasOneUse() && 3785 // If both are volatile this would reduce the number of volatile loads. 3786 // If one is volatile it might be ok, but play conservative and bail out. 3787 !LD1->isVolatile() && 3788 !LD2->isVolatile() && 3789 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) { 3790 unsigned Align = LD1->getAlignment(); 3791 unsigned NewAlign = TLI.getTargetData()-> 3792 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 3793 3794 if (NewAlign <= Align && 3795 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) 3796 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(), 3797 LD1->getBasePtr(), LD1->getSrcValue(), 3798 LD1->getSrcValueOffset(), false, Align); 3799 } 3800 3801 return SDValue(); 3802} 3803 3804SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) { 3805 SDValue N0 = N->getOperand(0); 3806 EVT VT = N->getValueType(0); 3807 3808 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 3809 // Only do this before legalize, since afterward the target may be depending 3810 // on the bitconvert. 3811 // First check to see if this is all constant. 3812 if (!LegalTypes && 3813 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 3814 VT.isVector()) { 3815 bool isSimple = true; 3816 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 3817 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 3818 N0.getOperand(i).getOpcode() != ISD::Constant && 3819 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 3820 isSimple = false; 3821 break; 3822 } 3823 3824 EVT DestEltVT = N->getValueType(0).getVectorElementType(); 3825 assert(!DestEltVT.isVector() && 3826 "Element type of vector ValueType must not be vector!"); 3827 if (isSimple) 3828 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.getNode(), DestEltVT); 3829 } 3830 3831 // If the input is a constant, let getNode fold it. 3832 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 3833 SDValue Res = DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, N0); 3834 if (Res.getNode() != N) { 3835 if (!LegalOperations || 3836 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT)) 3837 return Res; 3838 3839 // Folding it resulted in an illegal node, and it's too late to 3840 // do that. Clean up the old node and forego the transformation. 3841 // Ideally this won't happen very often, because instcombine 3842 // and the earlier dagcombine runs (where illegal nodes are 3843 // permitted) should have folded most of them already. 3844 DAG.DeleteNode(Res.getNode()); 3845 } 3846 } 3847 3848 // (conv (conv x, t1), t2) -> (conv x, t2) 3849 if (N0.getOpcode() == ISD::BIT_CONVERT) 3850 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, 3851 N0.getOperand(0)); 3852 3853 // fold (conv (load x)) -> (load (conv*)x) 3854 // If the resultant load doesn't need a higher alignment than the original! 3855 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 3856 // Do not change the width of a volatile load. 3857 !cast<LoadSDNode>(N0)->isVolatile() && 3858 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) { 3859 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3860 unsigned Align = TLI.getTargetData()-> 3861 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 3862 unsigned OrigAlign = LN0->getAlignment(); 3863 3864 if (Align <= OrigAlign) { 3865 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(), 3866 LN0->getBasePtr(), 3867 LN0->getSrcValue(), LN0->getSrcValueOffset(), 3868 LN0->isVolatile(), OrigAlign); 3869 AddToWorkList(N); 3870 CombineTo(N0.getNode(), 3871 DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 3872 N0.getValueType(), Load), 3873 Load.getValue(1)); 3874 return Load; 3875 } 3876 } 3877 3878 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit) 3879 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit)) 3880 // This often reduces constant pool loads. 3881 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && 3882 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) { 3883 SDValue NewConv = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), VT, 3884 N0.getOperand(0)); 3885 AddToWorkList(NewConv.getNode()); 3886 3887 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3888 if (N0.getOpcode() == ISD::FNEG) 3889 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 3890 NewConv, DAG.getConstant(SignBit, VT)); 3891 assert(N0.getOpcode() == ISD::FABS); 3892 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3893 NewConv, DAG.getConstant(~SignBit, VT)); 3894 } 3895 3896 // fold (bitconvert (fcopysign cst, x)) -> 3897 // (or (and (bitconvert x), sign), (and cst, (not sign))) 3898 // Note that we don't handle (copysign x, cst) because this can always be 3899 // folded to an fneg or fabs. 3900 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 3901 isa<ConstantFPSDNode>(N0.getOperand(0)) && 3902 VT.isInteger() && !VT.isVector()) { 3903 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 3904 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth); 3905 if (TLI.isTypeLegal(IntXVT) || !LegalTypes) { 3906 SDValue X = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 3907 IntXVT, N0.getOperand(1)); 3908 AddToWorkList(X.getNode()); 3909 3910 // If X has a different width than the result/lhs, sext it or truncate it. 3911 unsigned VTWidth = VT.getSizeInBits(); 3912 if (OrigXWidth < VTWidth) { 3913 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X); 3914 AddToWorkList(X.getNode()); 3915 } else if (OrigXWidth > VTWidth) { 3916 // To get the sign bit in the right place, we have to shift it right 3917 // before truncating. 3918 X = DAG.getNode(ISD::SRL, X.getDebugLoc(), 3919 X.getValueType(), X, 3920 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 3921 AddToWorkList(X.getNode()); 3922 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 3923 AddToWorkList(X.getNode()); 3924 } 3925 3926 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3927 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT, 3928 X, DAG.getConstant(SignBit, VT)); 3929 AddToWorkList(X.getNode()); 3930 3931 SDValue Cst = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 3932 VT, N0.getOperand(0)); 3933 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT, 3934 Cst, DAG.getConstant(~SignBit, VT)); 3935 AddToWorkList(Cst.getNode()); 3936 3937 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst); 3938 } 3939 } 3940 3941 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 3942 if (N0.getOpcode() == ISD::BUILD_PAIR) { 3943 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT); 3944 if (CombineLD.getNode()) 3945 return CombineLD; 3946 } 3947 3948 return SDValue(); 3949} 3950 3951SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 3952 EVT VT = N->getValueType(0); 3953 return CombineConsecutiveLoads(N, VT); 3954} 3955 3956/// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector 3957/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 3958/// destination element value type. 3959SDValue DAGCombiner:: 3960ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) { 3961 EVT SrcEltVT = BV->getValueType(0).getVectorElementType(); 3962 3963 // If this is already the right type, we're done. 3964 if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 3965 3966 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 3967 unsigned DstBitSize = DstEltVT.getSizeInBits(); 3968 3969 // If this is a conversion of N elements of one type to N elements of another 3970 // type, convert each element. This handles FP<->INT cases. 3971 if (SrcBitSize == DstBitSize) { 3972 SmallVector<SDValue, 8> Ops; 3973 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3974 SDValue Op = BV->getOperand(i); 3975 // If the vector element type is not legal, the BUILD_VECTOR operands 3976 // are promoted and implicitly truncated. Make that explicit here. 3977 if (Op.getValueType() != SrcEltVT) 3978 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op); 3979 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, BV->getDebugLoc(), 3980 DstEltVT, Op)); 3981 AddToWorkList(Ops.back().getNode()); 3982 } 3983 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 3984 BV->getValueType(0).getVectorNumElements()); 3985 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 3986 &Ops[0], Ops.size()); 3987 } 3988 3989 // Otherwise, we're growing or shrinking the elements. To avoid having to 3990 // handle annoying details of growing/shrinking FP values, we convert them to 3991 // int first. 3992 if (SrcEltVT.isFloatingPoint()) { 3993 // Convert the input float vector to a int vector where the elements are the 3994 // same sizes. 3995 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 3996 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits()); 3997 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode(); 3998 SrcEltVT = IntVT; 3999 } 4000 4001 // Now we know the input is an integer vector. If the output is a FP type, 4002 // convert to integer first, then to FP of the right size. 4003 if (DstEltVT.isFloatingPoint()) { 4004 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 4005 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits()); 4006 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).getNode(); 4007 4008 // Next, convert to FP elements of the same size. 4009 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT); 4010 } 4011 4012 // Okay, we know the src/dst types are both integers of differing types. 4013 // Handling growing first. 4014 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 4015 if (SrcBitSize < DstBitSize) { 4016 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 4017 4018 SmallVector<SDValue, 8> Ops; 4019 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 4020 i += NumInputsPerOutput) { 4021 bool isLE = TLI.isLittleEndian(); 4022 APInt NewBits = APInt(DstBitSize, 0); 4023 bool EltIsUndef = true; 4024 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 4025 // Shift the previously computed bits over. 4026 NewBits <<= SrcBitSize; 4027 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 4028 if (Op.getOpcode() == ISD::UNDEF) continue; 4029 EltIsUndef = false; 4030 4031 NewBits |= (APInt(cast<ConstantSDNode>(Op)->getAPIntValue()). 4032 zextOrTrunc(SrcBitSize).zext(DstBitSize)); 4033 } 4034 4035 if (EltIsUndef) 4036 Ops.push_back(DAG.getUNDEF(DstEltVT)); 4037 else 4038 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 4039 } 4040 4041 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size()); 4042 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 4043 &Ops[0], Ops.size()); 4044 } 4045 4046 // Finally, this must be the case where we are shrinking elements: each input 4047 // turns into multiple outputs. 4048 bool isS2V = ISD::isScalarToVector(BV); 4049 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 4050 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 4051 NumOutputsPerInput*BV->getNumOperands()); 4052 SmallVector<SDValue, 8> Ops; 4053 4054 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 4055 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 4056 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 4057 Ops.push_back(DAG.getUNDEF(DstEltVT)); 4058 continue; 4059 } 4060 4061 APInt OpVal = APInt(cast<ConstantSDNode>(BV->getOperand(i))-> 4062 getAPIntValue()).zextOrTrunc(SrcBitSize); 4063 4064 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 4065 APInt ThisVal = APInt(OpVal).trunc(DstBitSize); 4066 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 4067 if (isS2V && i == 0 && j == 0 && APInt(ThisVal).zext(SrcBitSize) == OpVal) 4068 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 4069 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 4070 Ops[0]); 4071 OpVal = OpVal.lshr(DstBitSize); 4072 } 4073 4074 // For big endian targets, swap the order of the pieces of each element. 4075 if (TLI.isBigEndian()) 4076 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 4077 } 4078 4079 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 4080 &Ops[0], Ops.size()); 4081} 4082 4083SDValue DAGCombiner::visitFADD(SDNode *N) { 4084 SDValue N0 = N->getOperand(0); 4085 SDValue N1 = N->getOperand(1); 4086 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4087 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4088 EVT VT = N->getValueType(0); 4089 4090 // fold vector ops 4091 if (VT.isVector()) { 4092 SDValue FoldedVOp = SimplifyVBinOp(N); 4093 if (FoldedVOp.getNode()) return FoldedVOp; 4094 } 4095 4096 // fold (fadd c1, c2) -> (fadd c1, c2) 4097 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4098 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1); 4099 // canonicalize constant to RHS 4100 if (N0CFP && !N1CFP) 4101 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0); 4102 // fold (fadd A, 0) -> A 4103 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4104 return N0; 4105 // fold (fadd A, (fneg B)) -> (fsub A, B) 4106 if (isNegatibleForFree(N1, LegalOperations) == 2) 4107 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, 4108 GetNegatedExpression(N1, DAG, LegalOperations)); 4109 // fold (fadd (fneg A), B) -> (fsub B, A) 4110 if (isNegatibleForFree(N0, LegalOperations) == 2) 4111 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1, 4112 GetNegatedExpression(N0, DAG, LegalOperations)); 4113 4114 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 4115 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 4116 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 4117 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0), 4118 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 4119 N0.getOperand(1), N1)); 4120 4121 return SDValue(); 4122} 4123 4124SDValue DAGCombiner::visitFSUB(SDNode *N) { 4125 SDValue N0 = N->getOperand(0); 4126 SDValue N1 = N->getOperand(1); 4127 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4128 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4129 EVT VT = N->getValueType(0); 4130 4131 // fold vector ops 4132 if (VT.isVector()) { 4133 SDValue FoldedVOp = SimplifyVBinOp(N); 4134 if (FoldedVOp.getNode()) return FoldedVOp; 4135 } 4136 4137 // fold (fsub c1, c2) -> c1-c2 4138 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4139 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1); 4140 // fold (fsub A, 0) -> A 4141 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4142 return N0; 4143 // fold (fsub 0, B) -> -B 4144 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { 4145 if (isNegatibleForFree(N1, LegalOperations)) 4146 return GetNegatedExpression(N1, DAG, LegalOperations); 4147 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4148 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1); 4149 } 4150 // fold (fsub A, (fneg B)) -> (fadd A, B) 4151 if (isNegatibleForFree(N1, LegalOperations)) 4152 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, 4153 GetNegatedExpression(N1, DAG, LegalOperations)); 4154 4155 return SDValue(); 4156} 4157 4158SDValue DAGCombiner::visitFMUL(SDNode *N) { 4159 SDValue N0 = N->getOperand(0); 4160 SDValue N1 = N->getOperand(1); 4161 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4162 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4163 EVT VT = N->getValueType(0); 4164 4165 // fold vector ops 4166 if (VT.isVector()) { 4167 SDValue FoldedVOp = SimplifyVBinOp(N); 4168 if (FoldedVOp.getNode()) return FoldedVOp; 4169 } 4170 4171 // fold (fmul c1, c2) -> c1*c2 4172 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4173 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1); 4174 // canonicalize constant to RHS 4175 if (N0CFP && !N1CFP) 4176 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0); 4177 // fold (fmul A, 0) -> 0 4178 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4179 return N1; 4180 // fold (fmul A, 0) -> 0, vector edition. 4181 if (UnsafeFPMath && ISD::isBuildVectorAllZeros(N1.getNode())) 4182 return N1; 4183 // fold (fmul X, 2.0) -> (fadd X, X) 4184 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 4185 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0); 4186 // fold (fmul X, -1.0) -> (fneg X) 4187 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 4188 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4189 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0); 4190 4191 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y) 4192 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 4193 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 4194 // Both can be negated for free, check to see if at least one is cheaper 4195 // negated. 4196 if (LHSNeg == 2 || RHSNeg == 2) 4197 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 4198 GetNegatedExpression(N0, DAG, LegalOperations), 4199 GetNegatedExpression(N1, DAG, LegalOperations)); 4200 } 4201 } 4202 4203 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 4204 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 4205 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 4206 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0), 4207 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 4208 N0.getOperand(1), N1)); 4209 4210 return SDValue(); 4211} 4212 4213SDValue DAGCombiner::visitFDIV(SDNode *N) { 4214 SDValue N0 = N->getOperand(0); 4215 SDValue N1 = N->getOperand(1); 4216 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4217 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4218 EVT VT = N->getValueType(0); 4219 4220 // fold vector ops 4221 if (VT.isVector()) { 4222 SDValue FoldedVOp = SimplifyVBinOp(N); 4223 if (FoldedVOp.getNode()) return FoldedVOp; 4224 } 4225 4226 // fold (fdiv c1, c2) -> c1/c2 4227 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4228 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1); 4229 4230 4231 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y) 4232 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 4233 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 4234 // Both can be negated for free, check to see if at least one is cheaper 4235 // negated. 4236 if (LHSNeg == 2 || RHSNeg == 2) 4237 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, 4238 GetNegatedExpression(N0, DAG, LegalOperations), 4239 GetNegatedExpression(N1, DAG, LegalOperations)); 4240 } 4241 } 4242 4243 return SDValue(); 4244} 4245 4246SDValue DAGCombiner::visitFREM(SDNode *N) { 4247 SDValue N0 = N->getOperand(0); 4248 SDValue N1 = N->getOperand(1); 4249 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4250 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4251 EVT VT = N->getValueType(0); 4252 4253 // fold (frem c1, c2) -> fmod(c1,c2) 4254 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4255 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1); 4256 4257 return SDValue(); 4258} 4259 4260SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 4261 SDValue N0 = N->getOperand(0); 4262 SDValue N1 = N->getOperand(1); 4263 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4264 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4265 EVT VT = N->getValueType(0); 4266 4267 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 4268 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1); 4269 4270 if (N1CFP) { 4271 const APFloat& V = N1CFP->getValueAPF(); 4272 // copysign(x, c1) -> fabs(x) iff ispos(c1) 4273 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 4274 if (!V.isNegative()) { 4275 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) 4276 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4277 } else { 4278 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4279 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, 4280 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0)); 4281 } 4282 } 4283 4284 // copysign(fabs(x), y) -> copysign(x, y) 4285 // copysign(fneg(x), y) -> copysign(x, y) 4286 // copysign(copysign(x,z), y) -> copysign(x, y) 4287 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 4288 N0.getOpcode() == ISD::FCOPYSIGN) 4289 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4290 N0.getOperand(0), N1); 4291 4292 // copysign(x, abs(y)) -> abs(x) 4293 if (N1.getOpcode() == ISD::FABS) 4294 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4295 4296 // copysign(x, copysign(y,z)) -> copysign(x, z) 4297 if (N1.getOpcode() == ISD::FCOPYSIGN) 4298 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4299 N0, N1.getOperand(1)); 4300 4301 // copysign(x, fp_extend(y)) -> copysign(x, y) 4302 // copysign(x, fp_round(y)) -> copysign(x, y) 4303 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 4304 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4305 N0, N1.getOperand(0)); 4306 4307 return SDValue(); 4308} 4309 4310SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 4311 SDValue N0 = N->getOperand(0); 4312 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4313 EVT VT = N->getValueType(0); 4314 EVT OpVT = N0.getValueType(); 4315 4316 // fold (sint_to_fp c1) -> c1fp 4317 if (N0C && OpVT != MVT::ppcf128) 4318 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 4319 4320 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 4321 // but UINT_TO_FP is legal on this target, try to convert. 4322 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && 4323 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { 4324 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 4325 if (DAG.SignBitIsZero(N0)) 4326 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 4327 } 4328 4329 return SDValue(); 4330} 4331 4332SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 4333 SDValue N0 = N->getOperand(0); 4334 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4335 EVT VT = N->getValueType(0); 4336 EVT OpVT = N0.getValueType(); 4337 4338 // fold (uint_to_fp c1) -> c1fp 4339 if (N0C && OpVT != MVT::ppcf128) 4340 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 4341 4342 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 4343 // but SINT_TO_FP is legal on this target, try to convert. 4344 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && 4345 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { 4346 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 4347 if (DAG.SignBitIsZero(N0)) 4348 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 4349 } 4350 4351 return SDValue(); 4352} 4353 4354SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 4355 SDValue N0 = N->getOperand(0); 4356 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4357 EVT VT = N->getValueType(0); 4358 4359 // fold (fp_to_sint c1fp) -> c1 4360 if (N0CFP) 4361 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0); 4362 4363 return SDValue(); 4364} 4365 4366SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 4367 SDValue N0 = N->getOperand(0); 4368 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4369 EVT VT = N->getValueType(0); 4370 4371 // fold (fp_to_uint c1fp) -> c1 4372 if (N0CFP && VT != MVT::ppcf128) 4373 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0); 4374 4375 return SDValue(); 4376} 4377 4378SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 4379 SDValue N0 = N->getOperand(0); 4380 SDValue N1 = N->getOperand(1); 4381 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4382 EVT VT = N->getValueType(0); 4383 4384 // fold (fp_round c1fp) -> c1fp 4385 if (N0CFP && N0.getValueType() != MVT::ppcf128) 4386 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1); 4387 4388 // fold (fp_round (fp_extend x)) -> x 4389 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 4390 return N0.getOperand(0); 4391 4392 // fold (fp_round (fp_round x)) -> (fp_round x) 4393 if (N0.getOpcode() == ISD::FP_ROUND) { 4394 // This is a value preserving truncation if both round's are. 4395 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 4396 N0.getNode()->getConstantOperandVal(1) == 1; 4397 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0), 4398 DAG.getIntPtrConstant(IsTrunc)); 4399 } 4400 4401 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 4402 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { 4403 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT, 4404 N0.getOperand(0), N1); 4405 AddToWorkList(Tmp.getNode()); 4406 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4407 Tmp, N0.getOperand(1)); 4408 } 4409 4410 return SDValue(); 4411} 4412 4413SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 4414 SDValue N0 = N->getOperand(0); 4415 EVT VT = N->getValueType(0); 4416 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 4417 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4418 4419 // fold (fp_round_inreg c1fp) -> c1fp 4420 if (N0CFP && (TLI.isTypeLegal(EVT) || !LegalTypes)) { 4421 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT); 4422 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round); 4423 } 4424 4425 return SDValue(); 4426} 4427 4428SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 4429 SDValue N0 = N->getOperand(0); 4430 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4431 EVT VT = N->getValueType(0); 4432 4433 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 4434 if (N->hasOneUse() && 4435 N->use_begin()->getOpcode() == ISD::FP_ROUND) 4436 return SDValue(); 4437 4438 // fold (fp_extend c1fp) -> c1fp 4439 if (N0CFP && VT != MVT::ppcf128) 4440 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0); 4441 4442 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 4443 // value of X. 4444 if (N0.getOpcode() == ISD::FP_ROUND 4445 && N0.getNode()->getConstantOperandVal(1) == 1) { 4446 SDValue In = N0.getOperand(0); 4447 if (In.getValueType() == VT) return In; 4448 if (VT.bitsLT(In.getValueType())) 4449 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, 4450 In, N0.getOperand(1)); 4451 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In); 4452 } 4453 4454 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 4455 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 4456 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4457 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 4458 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4459 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 4460 LN0->getChain(), 4461 LN0->getBasePtr(), LN0->getSrcValue(), 4462 LN0->getSrcValueOffset(), 4463 N0.getValueType(), 4464 LN0->isVolatile(), LN0->getAlignment()); 4465 CombineTo(N, ExtLoad); 4466 CombineTo(N0.getNode(), 4467 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), 4468 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)), 4469 ExtLoad.getValue(1)); 4470 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4471 } 4472 4473 return SDValue(); 4474} 4475 4476SDValue DAGCombiner::visitFNEG(SDNode *N) { 4477 SDValue N0 = N->getOperand(0); 4478 EVT VT = N->getValueType(0); 4479 4480 if (isNegatibleForFree(N0, LegalOperations)) 4481 return GetNegatedExpression(N0, DAG, LegalOperations); 4482 4483 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 4484 // constant pool values. 4485 if (N0.getOpcode() == ISD::BIT_CONVERT && 4486 !VT.isVector() && 4487 N0.getNode()->hasOneUse() && 4488 N0.getOperand(0).getValueType().isInteger()) { 4489 SDValue Int = N0.getOperand(0); 4490 EVT IntVT = Int.getValueType(); 4491 if (IntVT.isInteger() && !IntVT.isVector()) { 4492 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int, 4493 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 4494 AddToWorkList(Int.getNode()); 4495 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), 4496 VT, Int); 4497 } 4498 } 4499 4500 return SDValue(); 4501} 4502 4503SDValue DAGCombiner::visitFABS(SDNode *N) { 4504 SDValue N0 = N->getOperand(0); 4505 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4506 EVT VT = N->getValueType(0); 4507 4508 // fold (fabs c1) -> fabs(c1) 4509 if (N0CFP && VT != MVT::ppcf128) 4510 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4511 // fold (fabs (fabs x)) -> (fabs x) 4512 if (N0.getOpcode() == ISD::FABS) 4513 return N->getOperand(0); 4514 // fold (fabs (fneg x)) -> (fabs x) 4515 // fold (fabs (fcopysign x, y)) -> (fabs x) 4516 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 4517 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0)); 4518 4519 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 4520 // constant pool values. 4521 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() && 4522 N0.getOperand(0).getValueType().isInteger() && 4523 !N0.getOperand(0).getValueType().isVector()) { 4524 SDValue Int = N0.getOperand(0); 4525 EVT IntVT = Int.getValueType(); 4526 if (IntVT.isInteger() && !IntVT.isVector()) { 4527 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int, 4528 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 4529 AddToWorkList(Int.getNode()); 4530 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), 4531 N->getValueType(0), Int); 4532 } 4533 } 4534 4535 return SDValue(); 4536} 4537 4538SDValue DAGCombiner::visitBRCOND(SDNode *N) { 4539 SDValue Chain = N->getOperand(0); 4540 SDValue N1 = N->getOperand(1); 4541 SDValue N2 = N->getOperand(2); 4542 4543 // If N is a constant we could fold this into a fallthrough or unconditional 4544 // branch. However that doesn't happen very often in normal code, because 4545 // Instcombine/SimplifyCFG should have handled the available opportunities. 4546 // If we did this folding here, it would be necessary to update the 4547 // MachineBasicBlock CFG, which is awkward. 4548 4549 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 4550 // on the target. 4551 if (N1.getOpcode() == ISD::SETCC && 4552 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) { 4553 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 4554 Chain, N1.getOperand(2), 4555 N1.getOperand(0), N1.getOperand(1), N2); 4556 } 4557 4558 SDNode *Trunc = 0; 4559 if (N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) { 4560 // Look pass truncate. 4561 Trunc = N1.getNode(); 4562 N1 = N1.getOperand(0); 4563 } 4564 4565 if (N1.hasOneUse() && N1.getOpcode() == ISD::SRL) { 4566 // Match this pattern so that we can generate simpler code: 4567 // 4568 // %a = ... 4569 // %b = and i32 %a, 2 4570 // %c = srl i32 %b, 1 4571 // brcond i32 %c ... 4572 // 4573 // into 4574 // 4575 // %a = ... 4576 // %b = and i32 %a, 2 4577 // %c = setcc eq %b, 0 4578 // brcond %c ... 4579 // 4580 // This applies only when the AND constant value has one bit set and the 4581 // SRL constant is equal to the log2 of the AND constant. The back-end is 4582 // smart enough to convert the result into a TEST/JMP sequence. 4583 SDValue Op0 = N1.getOperand(0); 4584 SDValue Op1 = N1.getOperand(1); 4585 4586 if (Op0.getOpcode() == ISD::AND && 4587 Op1.getOpcode() == ISD::Constant) { 4588 SDValue AndOp1 = Op0.getOperand(1); 4589 4590 if (AndOp1.getOpcode() == ISD::Constant) { 4591 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue(); 4592 4593 if (AndConst.isPowerOf2() && 4594 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) { 4595 SDValue SetCC = 4596 DAG.getSetCC(N->getDebugLoc(), 4597 TLI.getSetCCResultType(Op0.getValueType()), 4598 Op0, DAG.getConstant(0, Op0.getValueType()), 4599 ISD::SETNE); 4600 4601 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 4602 MVT::Other, Chain, SetCC, N2); 4603 // Don't add the new BRCond into the worklist or else SimplifySelectCC 4604 // will convert it back to (X & C1) >> C2. 4605 CombineTo(N, NewBRCond, false); 4606 // Truncate is dead. 4607 if (Trunc) { 4608 removeFromWorkList(Trunc); 4609 DAG.DeleteNode(Trunc); 4610 } 4611 // Replace the uses of SRL with SETCC 4612 DAG.ReplaceAllUsesOfValueWith(N1, SetCC); 4613 removeFromWorkList(N1.getNode()); 4614 DAG.DeleteNode(N1.getNode()); 4615 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4616 } 4617 } 4618 } 4619 } 4620 4621 return SDValue(); 4622} 4623 4624// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 4625// 4626SDValue DAGCombiner::visitBR_CC(SDNode *N) { 4627 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 4628 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 4629 4630 // If N is a constant we could fold this into a fallthrough or unconditional 4631 // branch. However that doesn't happen very often in normal code, because 4632 // Instcombine/SimplifyCFG should have handled the available opportunities. 4633 // If we did this folding here, it would be necessary to update the 4634 // MachineBasicBlock CFG, which is awkward. 4635 4636 // Use SimplifySetCC to simplify SETCC's. 4637 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()), 4638 CondLHS, CondRHS, CC->get(), N->getDebugLoc(), 4639 false); 4640 if (Simp.getNode()) AddToWorkList(Simp.getNode()); 4641 4642 // fold to a simpler setcc 4643 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) 4644 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 4645 N->getOperand(0), Simp.getOperand(2), 4646 Simp.getOperand(0), Simp.getOperand(1), 4647 N->getOperand(4)); 4648 4649 return SDValue(); 4650} 4651 4652/// CombineToPreIndexedLoadStore - Try turning a load / store into a 4653/// pre-indexed load / store when the base pointer is an add or subtract 4654/// and it has other uses besides the load / store. After the 4655/// transformation, the new indexed load / store has effectively folded 4656/// the add / subtract in and all of its other uses are redirected to the 4657/// new load / store. 4658bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 4659 if (!LegalOperations) 4660 return false; 4661 4662 bool isLoad = true; 4663 SDValue Ptr; 4664 EVT VT; 4665 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4666 if (LD->isIndexed()) 4667 return false; 4668 VT = LD->getMemoryVT(); 4669 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 4670 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 4671 return false; 4672 Ptr = LD->getBasePtr(); 4673 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4674 if (ST->isIndexed()) 4675 return false; 4676 VT = ST->getMemoryVT(); 4677 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 4678 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 4679 return false; 4680 Ptr = ST->getBasePtr(); 4681 isLoad = false; 4682 } else { 4683 return false; 4684 } 4685 4686 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 4687 // out. There is no reason to make this a preinc/predec. 4688 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 4689 Ptr.getNode()->hasOneUse()) 4690 return false; 4691 4692 // Ask the target to do addressing mode selection. 4693 SDValue BasePtr; 4694 SDValue Offset; 4695 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4696 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 4697 return false; 4698 // Don't create a indexed load / store with zero offset. 4699 if (isa<ConstantSDNode>(Offset) && 4700 cast<ConstantSDNode>(Offset)->isNullValue()) 4701 return false; 4702 4703 // Try turning it into a pre-indexed load / store except when: 4704 // 1) The new base ptr is a frame index. 4705 // 2) If N is a store and the new base ptr is either the same as or is a 4706 // predecessor of the value being stored. 4707 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 4708 // that would create a cycle. 4709 // 4) All uses are load / store ops that use it as old base ptr. 4710 4711 // Check #1. Preinc'ing a frame index would require copying the stack pointer 4712 // (plus the implicit offset) to a register to preinc anyway. 4713 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 4714 return false; 4715 4716 // Check #2. 4717 if (!isLoad) { 4718 SDValue Val = cast<StoreSDNode>(N)->getValue(); 4719 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode())) 4720 return false; 4721 } 4722 4723 // Now check for #3 and #4. 4724 bool RealUse = false; 4725 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 4726 E = Ptr.getNode()->use_end(); I != E; ++I) { 4727 SDNode *Use = *I; 4728 if (Use == N) 4729 continue; 4730 if (Use->isPredecessorOf(N)) 4731 return false; 4732 4733 if (!((Use->getOpcode() == ISD::LOAD && 4734 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 4735 (Use->getOpcode() == ISD::STORE && 4736 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))) 4737 RealUse = true; 4738 } 4739 4740 if (!RealUse) 4741 return false; 4742 4743 SDValue Result; 4744 if (isLoad) 4745 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 4746 BasePtr, Offset, AM); 4747 else 4748 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 4749 BasePtr, Offset, AM); 4750 ++PreIndexedNodes; 4751 ++NodesCombined; 4752 DEBUG(dbgs() << "\nReplacing.4 "; 4753 N->dump(&DAG); 4754 dbgs() << "\nWith: "; 4755 Result.getNode()->dump(&DAG); 4756 dbgs() << '\n'); 4757 WorkListRemover DeadNodes(*this); 4758 if (isLoad) { 4759 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 4760 &DeadNodes); 4761 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 4762 &DeadNodes); 4763 } else { 4764 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 4765 &DeadNodes); 4766 } 4767 4768 // Finally, since the node is now dead, remove it from the graph. 4769 DAG.DeleteNode(N); 4770 4771 // Replace the uses of Ptr with uses of the updated base value. 4772 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 4773 &DeadNodes); 4774 removeFromWorkList(Ptr.getNode()); 4775 DAG.DeleteNode(Ptr.getNode()); 4776 4777 return true; 4778} 4779 4780/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 4781/// add / sub of the base pointer node into a post-indexed load / store. 4782/// The transformation folded the add / subtract into the new indexed 4783/// load / store effectively and all of its uses are redirected to the 4784/// new load / store. 4785bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 4786 if (!LegalOperations) 4787 return false; 4788 4789 bool isLoad = true; 4790 SDValue Ptr; 4791 EVT VT; 4792 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4793 if (LD->isIndexed()) 4794 return false; 4795 VT = LD->getMemoryVT(); 4796 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 4797 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 4798 return false; 4799 Ptr = LD->getBasePtr(); 4800 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4801 if (ST->isIndexed()) 4802 return false; 4803 VT = ST->getMemoryVT(); 4804 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 4805 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 4806 return false; 4807 Ptr = ST->getBasePtr(); 4808 isLoad = false; 4809 } else { 4810 return false; 4811 } 4812 4813 if (Ptr.getNode()->hasOneUse()) 4814 return false; 4815 4816 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 4817 E = Ptr.getNode()->use_end(); I != E; ++I) { 4818 SDNode *Op = *I; 4819 if (Op == N || 4820 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 4821 continue; 4822 4823 SDValue BasePtr; 4824 SDValue Offset; 4825 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4826 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 4827 if (Ptr == Offset && Op->getOpcode() == ISD::ADD) 4828 std::swap(BasePtr, Offset); 4829 if (Ptr != BasePtr) 4830 continue; 4831 // Don't create a indexed load / store with zero offset. 4832 if (isa<ConstantSDNode>(Offset) && 4833 cast<ConstantSDNode>(Offset)->isNullValue()) 4834 continue; 4835 4836 // Try turning it into a post-indexed load / store except when 4837 // 1) All uses are load / store ops that use it as base ptr. 4838 // 2) Op must be independent of N, i.e. Op is neither a predecessor 4839 // nor a successor of N. Otherwise, if Op is folded that would 4840 // create a cycle. 4841 4842 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 4843 continue; 4844 4845 // Check for #1. 4846 bool TryNext = false; 4847 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), 4848 EE = BasePtr.getNode()->use_end(); II != EE; ++II) { 4849 SDNode *Use = *II; 4850 if (Use == Ptr.getNode()) 4851 continue; 4852 4853 // If all the uses are load / store addresses, then don't do the 4854 // transformation. 4855 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 4856 bool RealUse = false; 4857 for (SDNode::use_iterator III = Use->use_begin(), 4858 EEE = Use->use_end(); III != EEE; ++III) { 4859 SDNode *UseUse = *III; 4860 if (!((UseUse->getOpcode() == ISD::LOAD && 4861 cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) || 4862 (UseUse->getOpcode() == ISD::STORE && 4863 cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use))) 4864 RealUse = true; 4865 } 4866 4867 if (!RealUse) { 4868 TryNext = true; 4869 break; 4870 } 4871 } 4872 } 4873 4874 if (TryNext) 4875 continue; 4876 4877 // Check for #2 4878 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 4879 SDValue Result = isLoad 4880 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 4881 BasePtr, Offset, AM) 4882 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 4883 BasePtr, Offset, AM); 4884 ++PostIndexedNodes; 4885 ++NodesCombined; 4886 DEBUG(dbgs() << "\nReplacing.5 "; 4887 N->dump(&DAG); 4888 dbgs() << "\nWith: "; 4889 Result.getNode()->dump(&DAG); 4890 dbgs() << '\n'); 4891 WorkListRemover DeadNodes(*this); 4892 if (isLoad) { 4893 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 4894 &DeadNodes); 4895 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 4896 &DeadNodes); 4897 } else { 4898 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 4899 &DeadNodes); 4900 } 4901 4902 // Finally, since the node is now dead, remove it from the graph. 4903 DAG.DeleteNode(N); 4904 4905 // Replace the uses of Use with uses of the updated base value. 4906 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 4907 Result.getValue(isLoad ? 1 : 0), 4908 &DeadNodes); 4909 removeFromWorkList(Op); 4910 DAG.DeleteNode(Op); 4911 return true; 4912 } 4913 } 4914 } 4915 4916 return false; 4917} 4918 4919SDValue DAGCombiner::visitLOAD(SDNode *N) { 4920 LoadSDNode *LD = cast<LoadSDNode>(N); 4921 SDValue Chain = LD->getChain(); 4922 SDValue Ptr = LD->getBasePtr(); 4923 4924 // Try to infer better alignment information than the load already has. 4925 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) { 4926 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 4927 if (Align > LD->getAlignment()) 4928 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(), 4929 LD->getValueType(0), 4930 Chain, Ptr, LD->getSrcValue(), 4931 LD->getSrcValueOffset(), LD->getMemoryVT(), 4932 LD->isVolatile(), Align); 4933 } 4934 } 4935 4936 // If load is not volatile and there are no uses of the loaded value (and 4937 // the updated indexed value in case of indexed loads), change uses of the 4938 // chain value into uses of the chain input (i.e. delete the dead load). 4939 if (!LD->isVolatile()) { 4940 if (N->getValueType(1) == MVT::Other) { 4941 // Unindexed loads. 4942 if (N->hasNUsesOfValue(0, 0)) { 4943 // It's not safe to use the two value CombineTo variant here. e.g. 4944 // v1, chain2 = load chain1, loc 4945 // v2, chain3 = load chain2, loc 4946 // v3 = add v2, c 4947 // Now we replace use of chain2 with chain1. This makes the second load 4948 // isomorphic to the one we are deleting, and thus makes this load live. 4949 DEBUG(dbgs() << "\nReplacing.6 "; 4950 N->dump(&DAG); 4951 dbgs() << "\nWith chain: "; 4952 Chain.getNode()->dump(&DAG); 4953 dbgs() << "\n"); 4954 WorkListRemover DeadNodes(*this); 4955 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes); 4956 4957 if (N->use_empty()) { 4958 removeFromWorkList(N); 4959 DAG.DeleteNode(N); 4960 } 4961 4962 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4963 } 4964 } else { 4965 // Indexed loads. 4966 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 4967 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 4968 SDValue Undef = DAG.getUNDEF(N->getValueType(0)); 4969 DEBUG(dbgs() << "\nReplacing.6 "; 4970 N->dump(&DAG); 4971 dbgs() << "\nWith: "; 4972 Undef.getNode()->dump(&DAG); 4973 dbgs() << " and 2 other values\n"); 4974 WorkListRemover DeadNodes(*this); 4975 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes); 4976 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 4977 DAG.getUNDEF(N->getValueType(1)), 4978 &DeadNodes); 4979 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes); 4980 removeFromWorkList(N); 4981 DAG.DeleteNode(N); 4982 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4983 } 4984 } 4985 } 4986 4987 // If this load is directly stored, replace the load value with the stored 4988 // value. 4989 // TODO: Handle store large -> read small portion. 4990 // TODO: Handle TRUNCSTORE/LOADEXT 4991 if (LD->getExtensionType() == ISD::NON_EXTLOAD && 4992 !LD->isVolatile()) { 4993 if (ISD::isNON_TRUNCStore(Chain.getNode())) { 4994 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 4995 if (PrevST->getBasePtr() == Ptr && 4996 PrevST->getValue().getValueType() == N->getValueType(0)) 4997 return CombineTo(N, Chain.getOperand(1), Chain); 4998 } 4999 } 5000 5001 if (CombinerAA) { 5002 // Walk up chain skipping non-aliasing memory nodes. 5003 SDValue BetterChain = FindBetterChain(N, Chain); 5004 5005 // If there is a better chain. 5006 if (Chain != BetterChain) { 5007 SDValue ReplLoad; 5008 5009 // Replace the chain to void dependency. 5010 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 5011 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(), 5012 BetterChain, Ptr, 5013 LD->getSrcValue(), LD->getSrcValueOffset(), 5014 LD->isVolatile(), LD->getAlignment()); 5015 } else { 5016 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(), 5017 LD->getValueType(0), 5018 BetterChain, Ptr, LD->getSrcValue(), 5019 LD->getSrcValueOffset(), 5020 LD->getMemoryVT(), 5021 LD->isVolatile(), 5022 LD->getAlignment()); 5023 } 5024 5025 // Create token factor to keep old chain connected. 5026 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 5027 MVT::Other, Chain, ReplLoad.getValue(1)); 5028 5029 // Make sure the new and old chains are cleaned up. 5030 AddToWorkList(Token.getNode()); 5031 5032 // Replace uses with load result and token factor. Don't add users 5033 // to work list. 5034 return CombineTo(N, ReplLoad.getValue(0), Token, false); 5035 } 5036 } 5037 5038 // Try transforming N to an indexed load. 5039 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 5040 return SDValue(N, 0); 5041 5042 return SDValue(); 5043} 5044 5045 5046/// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is 5047/// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some 5048/// of the loaded bits, try narrowing the load and store if it would end up 5049/// being a win for performance or code size. 5050SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) { 5051 StoreSDNode *ST = cast<StoreSDNode>(N); 5052 if (ST->isVolatile()) 5053 return SDValue(); 5054 5055 SDValue Chain = ST->getChain(); 5056 SDValue Value = ST->getValue(); 5057 SDValue Ptr = ST->getBasePtr(); 5058 EVT VT = Value.getValueType(); 5059 5060 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse()) 5061 return SDValue(); 5062 5063 unsigned Opc = Value.getOpcode(); 5064 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) || 5065 Value.getOperand(1).getOpcode() != ISD::Constant) 5066 return SDValue(); 5067 5068 SDValue N0 = Value.getOperand(0); 5069 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse()) { 5070 LoadSDNode *LD = cast<LoadSDNode>(N0); 5071 if (LD->getBasePtr() != Ptr) 5072 return SDValue(); 5073 5074 // Find the type to narrow it the load / op / store to. 5075 SDValue N1 = Value.getOperand(1); 5076 unsigned BitWidth = N1.getValueSizeInBits(); 5077 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue(); 5078 if (Opc == ISD::AND) 5079 Imm ^= APInt::getAllOnesValue(BitWidth); 5080 if (Imm == 0 || Imm.isAllOnesValue()) 5081 return SDValue(); 5082 unsigned ShAmt = Imm.countTrailingZeros(); 5083 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1; 5084 unsigned NewBW = NextPowerOf2(MSB - ShAmt); 5085 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 5086 while (NewBW < BitWidth && 5087 !(TLI.isOperationLegalOrCustom(Opc, NewVT) && 5088 TLI.isNarrowingProfitable(VT, NewVT))) { 5089 NewBW = NextPowerOf2(NewBW); 5090 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 5091 } 5092 if (NewBW >= BitWidth) 5093 return SDValue(); 5094 5095 // If the lsb changed does not start at the type bitwidth boundary, 5096 // start at the previous one. 5097 if (ShAmt % NewBW) 5098 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW; 5099 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW); 5100 if ((Imm & Mask) == Imm) { 5101 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW); 5102 if (Opc == ISD::AND) 5103 NewImm ^= APInt::getAllOnesValue(NewBW); 5104 uint64_t PtrOff = ShAmt / 8; 5105 // For big endian targets, we need to adjust the offset to the pointer to 5106 // load the correct bytes. 5107 if (TLI.isBigEndian()) 5108 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff; 5109 5110 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff); 5111 if (NewAlign < 5112 TLI.getTargetData()->getABITypeAlignment(NewVT.getTypeForEVT(*DAG.getContext()))) 5113 return SDValue(); 5114 5115 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(), 5116 Ptr.getValueType(), Ptr, 5117 DAG.getConstant(PtrOff, Ptr.getValueType())); 5118 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(), 5119 LD->getChain(), NewPtr, 5120 LD->getSrcValue(), LD->getSrcValueOffset(), 5121 LD->isVolatile(), NewAlign); 5122 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD, 5123 DAG.getConstant(NewImm, NewVT)); 5124 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(), 5125 NewVal, NewPtr, 5126 ST->getSrcValue(), ST->getSrcValueOffset(), 5127 false, NewAlign); 5128 5129 AddToWorkList(NewPtr.getNode()); 5130 AddToWorkList(NewLD.getNode()); 5131 AddToWorkList(NewVal.getNode()); 5132 WorkListRemover DeadNodes(*this); 5133 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1), 5134 &DeadNodes); 5135 ++OpsNarrowed; 5136 return NewST; 5137 } 5138 } 5139 5140 return SDValue(); 5141} 5142 5143SDValue DAGCombiner::visitSTORE(SDNode *N) { 5144 StoreSDNode *ST = cast<StoreSDNode>(N); 5145 SDValue Chain = ST->getChain(); 5146 SDValue Value = ST->getValue(); 5147 SDValue Ptr = ST->getBasePtr(); 5148 5149 // Try to infer better alignment information than the store already has. 5150 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) { 5151 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 5152 if (Align > ST->getAlignment()) 5153 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value, 5154 Ptr, ST->getSrcValue(), 5155 ST->getSrcValueOffset(), ST->getMemoryVT(), 5156 ST->isVolatile(), Align); 5157 } 5158 } 5159 5160 // If this is a store of a bit convert, store the input value if the 5161 // resultant store does not need a higher alignment than the original. 5162 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() && 5163 ST->isUnindexed()) { 5164 unsigned OrigAlign = ST->getAlignment(); 5165 EVT SVT = Value.getOperand(0).getValueType(); 5166 unsigned Align = TLI.getTargetData()-> 5167 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext())); 5168 if (Align <= OrigAlign && 5169 ((!LegalOperations && !ST->isVolatile()) || 5170 TLI.isOperationLegalOrCustom(ISD::STORE, SVT))) 5171 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0), 5172 Ptr, ST->getSrcValue(), 5173 ST->getSrcValueOffset(), ST->isVolatile(), OrigAlign); 5174 } 5175 5176 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 5177 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 5178 // NOTE: If the original store is volatile, this transform must not increase 5179 // the number of stores. For example, on x86-32 an f64 can be stored in one 5180 // processor operation but an i64 (which is not legal) requires two. So the 5181 // transform should not be done in this case. 5182 if (Value.getOpcode() != ISD::TargetConstantFP) { 5183 SDValue Tmp; 5184 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) { 5185 default: llvm_unreachable("Unknown FP type"); 5186 case MVT::f80: // We don't do this for these yet. 5187 case MVT::f128: 5188 case MVT::ppcf128: 5189 break; 5190 case MVT::f32: 5191 if (((TLI.isTypeLegal(MVT::i32) || !LegalTypes) && !LegalOperations && 5192 !ST->isVolatile()) || 5193 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 5194 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 5195 bitcastToAPInt().getZExtValue(), MVT::i32); 5196 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 5197 Ptr, ST->getSrcValue(), 5198 ST->getSrcValueOffset(), ST->isVolatile(), 5199 ST->getAlignment()); 5200 } 5201 break; 5202 case MVT::f64: 5203 if (((TLI.isTypeLegal(MVT::i64) || !LegalTypes) && !LegalOperations && 5204 !ST->isVolatile()) || 5205 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) { 5206 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 5207 getZExtValue(), MVT::i64); 5208 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 5209 Ptr, ST->getSrcValue(), 5210 ST->getSrcValueOffset(), ST->isVolatile(), 5211 ST->getAlignment()); 5212 } else if (!ST->isVolatile() && 5213 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 5214 // Many FP stores are not made apparent until after legalize, e.g. for 5215 // argument passing. Since this is so common, custom legalize the 5216 // 64-bit integer store into two 32-bit stores. 5217 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); 5218 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 5219 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 5220 if (TLI.isBigEndian()) std::swap(Lo, Hi); 5221 5222 int SVOffset = ST->getSrcValueOffset(); 5223 unsigned Alignment = ST->getAlignment(); 5224 bool isVolatile = ST->isVolatile(); 5225 5226 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo, 5227 Ptr, ST->getSrcValue(), 5228 ST->getSrcValueOffset(), 5229 isVolatile, ST->getAlignment()); 5230 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr, 5231 DAG.getConstant(4, Ptr.getValueType())); 5232 SVOffset += 4; 5233 Alignment = MinAlign(Alignment, 4U); 5234 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi, 5235 Ptr, ST->getSrcValue(), 5236 SVOffset, isVolatile, Alignment); 5237 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 5238 St0, St1); 5239 } 5240 5241 break; 5242 } 5243 } 5244 } 5245 5246 if (CombinerAA) { 5247 // Walk up chain skipping non-aliasing memory nodes. 5248 SDValue BetterChain = FindBetterChain(N, Chain); 5249 5250 // If there is a better chain. 5251 if (Chain != BetterChain) { 5252 SDValue ReplStore; 5253 5254 // Replace the chain to avoid dependency. 5255 if (ST->isTruncatingStore()) { 5256 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr, 5257 ST->getSrcValue(),ST->getSrcValueOffset(), 5258 ST->getMemoryVT(), 5259 ST->isVolatile(), ST->getAlignment()); 5260 } else { 5261 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr, 5262 ST->getSrcValue(), ST->getSrcValueOffset(), 5263 ST->isVolatile(), ST->getAlignment()); 5264 } 5265 5266 // Create token to keep both nodes around. 5267 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 5268 MVT::Other, Chain, ReplStore); 5269 5270 // Make sure the new and old chains are cleaned up. 5271 AddToWorkList(Token.getNode()); 5272 5273 // Don't add users to work list. 5274 return CombineTo(N, Token, false); 5275 } 5276 } 5277 5278 // Try transforming N to an indexed store. 5279 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 5280 return SDValue(N, 0); 5281 5282 // FIXME: is there such a thing as a truncating indexed store? 5283 if (ST->isTruncatingStore() && ST->isUnindexed() && 5284 Value.getValueType().isInteger()) { 5285 // See if we can simplify the input to this truncstore with knowledge that 5286 // only the low bits are being used. For example: 5287 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 5288 SDValue Shorter = 5289 GetDemandedBits(Value, 5290 APInt::getLowBitsSet(Value.getValueSizeInBits(), 5291 ST->getMemoryVT().getSizeInBits())); 5292 AddToWorkList(Value.getNode()); 5293 if (Shorter.getNode()) 5294 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter, 5295 Ptr, ST->getSrcValue(), 5296 ST->getSrcValueOffset(), ST->getMemoryVT(), 5297 ST->isVolatile(), ST->getAlignment()); 5298 5299 // Otherwise, see if we can simplify the operation with 5300 // SimplifyDemandedBits, which only works if the value has a single use. 5301 if (SimplifyDemandedBits(Value, 5302 APInt::getLowBitsSet( 5303 Value.getValueType().getScalarType().getSizeInBits(), 5304 ST->getMemoryVT().getSizeInBits()))) 5305 return SDValue(N, 0); 5306 } 5307 5308 // If this is a load followed by a store to the same location, then the store 5309 // is dead/noop. 5310 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 5311 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 5312 ST->isUnindexed() && !ST->isVolatile() && 5313 // There can't be any side effects between the load and store, such as 5314 // a call or store. 5315 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 5316 // The store is dead, remove it. 5317 return Chain; 5318 } 5319 } 5320 5321 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 5322 // truncating store. We can do this even if this is already a truncstore. 5323 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 5324 && Value.getNode()->hasOneUse() && ST->isUnindexed() && 5325 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 5326 ST->getMemoryVT())) { 5327 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0), 5328 Ptr, ST->getSrcValue(), 5329 ST->getSrcValueOffset(), ST->getMemoryVT(), 5330 ST->isVolatile(), ST->getAlignment()); 5331 } 5332 5333 return ReduceLoadOpStoreWidth(N); 5334} 5335 5336SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 5337 SDValue InVec = N->getOperand(0); 5338 SDValue InVal = N->getOperand(1); 5339 SDValue EltNo = N->getOperand(2); 5340 5341 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 5342 // vector with the inserted element. 5343 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 5344 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5345 SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(), 5346 InVec.getNode()->op_end()); 5347 if (Elt < Ops.size()) 5348 Ops[Elt] = InVal; 5349 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5350 InVec.getValueType(), &Ops[0], Ops.size()); 5351 } 5352 // If the invec is an UNDEF and if EltNo is a constant, create a new 5353 // BUILD_VECTOR with undef elements and the inserted element. 5354 if (!LegalOperations && InVec.getOpcode() == ISD::UNDEF && 5355 isa<ConstantSDNode>(EltNo)) { 5356 EVT VT = InVec.getValueType(); 5357 EVT EltVT = VT.getVectorElementType(); 5358 unsigned NElts = VT.getVectorNumElements(); 5359 SmallVector<SDValue, 8> Ops(NElts, DAG.getUNDEF(EltVT)); 5360 5361 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5362 if (Elt < Ops.size()) 5363 Ops[Elt] = InVal; 5364 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5365 InVec.getValueType(), &Ops[0], Ops.size()); 5366 } 5367 return SDValue(); 5368} 5369 5370SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 5371 // (vextract (scalar_to_vector val, 0) -> val 5372 SDValue InVec = N->getOperand(0); 5373 5374 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 5375 // If the operand is wider than the vector element type then it is implicitly 5376 // truncated. Make that explicit here. 5377 EVT EltVT = InVec.getValueType().getVectorElementType(); 5378 SDValue InOp = InVec.getOperand(0); 5379 if (InOp.getValueType() != EltVT) 5380 return DAG.getNode(ISD::TRUNCATE, InVec.getDebugLoc(), EltVT, InOp); 5381 return InOp; 5382 } 5383 5384 // Perform only after legalization to ensure build_vector / vector_shuffle 5385 // optimizations have already been done. 5386 if (!LegalOperations) return SDValue(); 5387 5388 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 5389 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 5390 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 5391 SDValue EltNo = N->getOperand(1); 5392 5393 if (isa<ConstantSDNode>(EltNo)) { 5394 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5395 bool NewLoad = false; 5396 bool BCNumEltsChanged = false; 5397 EVT VT = InVec.getValueType(); 5398 EVT ExtVT = VT.getVectorElementType(); 5399 EVT LVT = ExtVT; 5400 5401 if (InVec.getOpcode() == ISD::BIT_CONVERT) { 5402 EVT BCVT = InVec.getOperand(0).getValueType(); 5403 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType())) 5404 return SDValue(); 5405 if (VT.getVectorNumElements() != BCVT.getVectorNumElements()) 5406 BCNumEltsChanged = true; 5407 InVec = InVec.getOperand(0); 5408 ExtVT = BCVT.getVectorElementType(); 5409 NewLoad = true; 5410 } 5411 5412 LoadSDNode *LN0 = NULL; 5413 const ShuffleVectorSDNode *SVN = NULL; 5414 if (ISD::isNormalLoad(InVec.getNode())) { 5415 LN0 = cast<LoadSDNode>(InVec); 5416 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 5417 InVec.getOperand(0).getValueType() == ExtVT && 5418 ISD::isNormalLoad(InVec.getOperand(0).getNode())) { 5419 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 5420 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) { 5421 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 5422 // => 5423 // (load $addr+1*size) 5424 5425 // If the bit convert changed the number of elements, it is unsafe 5426 // to examine the mask. 5427 if (BCNumEltsChanged) 5428 return SDValue(); 5429 5430 // Select the input vector, guarding against out of range extract vector. 5431 unsigned NumElems = VT.getVectorNumElements(); 5432 int Idx = (Elt > NumElems) ? -1 : SVN->getMaskElt(Elt); 5433 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 5434 5435 if (InVec.getOpcode() == ISD::BIT_CONVERT) 5436 InVec = InVec.getOperand(0); 5437 if (ISD::isNormalLoad(InVec.getNode())) { 5438 LN0 = cast<LoadSDNode>(InVec); 5439 Elt = (Idx < (int)NumElems) ? Idx : Idx - NumElems; 5440 } 5441 } 5442 5443 if (!LN0 || !LN0->hasOneUse() || LN0->isVolatile()) 5444 return SDValue(); 5445 5446 unsigned Align = LN0->getAlignment(); 5447 if (NewLoad) { 5448 // Check the resultant load doesn't need a higher alignment than the 5449 // original load. 5450 unsigned NewAlign = 5451 TLI.getTargetData()->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext())); 5452 5453 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT)) 5454 return SDValue(); 5455 5456 Align = NewAlign; 5457 } 5458 5459 SDValue NewPtr = LN0->getBasePtr(); 5460 if (Elt) { 5461 unsigned PtrOff = LVT.getSizeInBits() * Elt / 8; 5462 EVT PtrType = NewPtr.getValueType(); 5463 if (TLI.isBigEndian()) 5464 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 5465 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr, 5466 DAG.getConstant(PtrOff, PtrType)); 5467 } 5468 5469 return DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr, 5470 LN0->getSrcValue(), LN0->getSrcValueOffset(), 5471 LN0->isVolatile(), Align); 5472 } 5473 5474 return SDValue(); 5475} 5476 5477SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 5478 unsigned NumInScalars = N->getNumOperands(); 5479 EVT VT = N->getValueType(0); 5480 5481 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 5482 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 5483 // at most two distinct vectors, turn this into a shuffle node. 5484 SDValue VecIn1, VecIn2; 5485 for (unsigned i = 0; i != NumInScalars; ++i) { 5486 // Ignore undef inputs. 5487 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 5488 5489 // If this input is something other than a EXTRACT_VECTOR_ELT with a 5490 // constant index, bail out. 5491 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 5492 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 5493 VecIn1 = VecIn2 = SDValue(0, 0); 5494 break; 5495 } 5496 5497 // If the input vector type disagrees with the result of the build_vector, 5498 // we can't make a shuffle. 5499 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 5500 if (ExtractedFromVec.getValueType() != VT) { 5501 VecIn1 = VecIn2 = SDValue(0, 0); 5502 break; 5503 } 5504 5505 // Otherwise, remember this. We allow up to two distinct input vectors. 5506 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 5507 continue; 5508 5509 if (VecIn1.getNode() == 0) { 5510 VecIn1 = ExtractedFromVec; 5511 } else if (VecIn2.getNode() == 0) { 5512 VecIn2 = ExtractedFromVec; 5513 } else { 5514 // Too many inputs. 5515 VecIn1 = VecIn2 = SDValue(0, 0); 5516 break; 5517 } 5518 } 5519 5520 // If everything is good, we can make a shuffle operation. 5521 if (VecIn1.getNode()) { 5522 SmallVector<int, 8> Mask; 5523 for (unsigned i = 0; i != NumInScalars; ++i) { 5524 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 5525 Mask.push_back(-1); 5526 continue; 5527 } 5528 5529 // If extracting from the first vector, just use the index directly. 5530 SDValue Extract = N->getOperand(i); 5531 SDValue ExtVal = Extract.getOperand(1); 5532 if (Extract.getOperand(0) == VecIn1) { 5533 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 5534 if (ExtIndex > VT.getVectorNumElements()) 5535 return SDValue(); 5536 5537 Mask.push_back(ExtIndex); 5538 continue; 5539 } 5540 5541 // Otherwise, use InIdx + VecSize 5542 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 5543 Mask.push_back(Idx+NumInScalars); 5544 } 5545 5546 // Add count and size info. 5547 if (!TLI.isTypeLegal(VT) && LegalTypes) 5548 return SDValue(); 5549 5550 // Return the new VECTOR_SHUFFLE node. 5551 SDValue Ops[2]; 5552 Ops[0] = VecIn1; 5553 Ops[1] = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT); 5554 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]); 5555 } 5556 5557 return SDValue(); 5558} 5559 5560SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 5561 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 5562 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 5563 // inputs come from at most two distinct vectors, turn this into a shuffle 5564 // node. 5565 5566 // If we only have one input vector, we don't need to do any concatenation. 5567 if (N->getNumOperands() == 1) 5568 return N->getOperand(0); 5569 5570 return SDValue(); 5571} 5572 5573SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 5574 return SDValue(); 5575 5576 EVT VT = N->getValueType(0); 5577 unsigned NumElts = VT.getVectorNumElements(); 5578 5579 SDValue N0 = N->getOperand(0); 5580 5581 assert(N0.getValueType().getVectorNumElements() == NumElts && 5582 "Vector shuffle must be normalized in DAG"); 5583 5584 // FIXME: implement canonicalizations from DAG.getVectorShuffle() 5585 5586 // If it is a splat, check if the argument vector is a build_vector with 5587 // all scalar elements the same. 5588 if (cast<ShuffleVectorSDNode>(N)->isSplat()) { 5589 SDNode *V = N0.getNode(); 5590 5591 5592 // If this is a bit convert that changes the element type of the vector but 5593 // not the number of vector elements, look through it. Be careful not to 5594 // look though conversions that change things like v4f32 to v2f64. 5595 if (V->getOpcode() == ISD::BIT_CONVERT) { 5596 SDValue ConvInput = V->getOperand(0); 5597 if (ConvInput.getValueType().isVector() && 5598 ConvInput.getValueType().getVectorNumElements() == NumElts) 5599 V = ConvInput.getNode(); 5600 } 5601 5602 if (V->getOpcode() == ISD::BUILD_VECTOR) { 5603 unsigned NumElems = V->getNumOperands(); 5604 unsigned BaseIdx = cast<ShuffleVectorSDNode>(N)->getSplatIndex(); 5605 if (NumElems > BaseIdx) { 5606 SDValue Base; 5607 bool AllSame = true; 5608 for (unsigned i = 0; i != NumElems; ++i) { 5609 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 5610 Base = V->getOperand(i); 5611 break; 5612 } 5613 } 5614 // Splat of <u, u, u, u>, return <u, u, u, u> 5615 if (!Base.getNode()) 5616 return N0; 5617 for (unsigned i = 0; i != NumElems; ++i) { 5618 if (V->getOperand(i) != Base) { 5619 AllSame = false; 5620 break; 5621 } 5622 } 5623 // Splat of <x, x, x, x>, return <x, x, x, x> 5624 if (AllSame) 5625 return N0; 5626 } 5627 } 5628 } 5629 return SDValue(); 5630} 5631 5632/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 5633/// an AND to a vector_shuffle with the destination vector and a zero vector. 5634/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 5635/// vector_shuffle V, Zero, <0, 4, 2, 4> 5636SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 5637 EVT VT = N->getValueType(0); 5638 DebugLoc dl = N->getDebugLoc(); 5639 SDValue LHS = N->getOperand(0); 5640 SDValue RHS = N->getOperand(1); 5641 if (N->getOpcode() == ISD::AND) { 5642 if (RHS.getOpcode() == ISD::BIT_CONVERT) 5643 RHS = RHS.getOperand(0); 5644 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 5645 SmallVector<int, 8> Indices; 5646 unsigned NumElts = RHS.getNumOperands(); 5647 for (unsigned i = 0; i != NumElts; ++i) { 5648 SDValue Elt = RHS.getOperand(i); 5649 if (!isa<ConstantSDNode>(Elt)) 5650 return SDValue(); 5651 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 5652 Indices.push_back(i); 5653 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 5654 Indices.push_back(NumElts); 5655 else 5656 return SDValue(); 5657 } 5658 5659 // Let's see if the target supports this vector_shuffle. 5660 EVT RVT = RHS.getValueType(); 5661 if (!TLI.isVectorClearMaskLegal(Indices, RVT)) 5662 return SDValue(); 5663 5664 // Return the new VECTOR_SHUFFLE node. 5665 EVT EltVT = RVT.getVectorElementType(); 5666 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(), 5667 DAG.getConstant(0, EltVT)); 5668 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5669 RVT, &ZeroOps[0], ZeroOps.size()); 5670 LHS = DAG.getNode(ISD::BIT_CONVERT, dl, RVT, LHS); 5671 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]); 5672 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Shuf); 5673 } 5674 } 5675 5676 return SDValue(); 5677} 5678 5679/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 5680SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 5681 // After legalize, the target may be depending on adds and other 5682 // binary ops to provide legal ways to construct constants or other 5683 // things. Simplifying them may result in a loss of legality. 5684 if (LegalOperations) return SDValue(); 5685 5686 EVT VT = N->getValueType(0); 5687 assert(VT.isVector() && "SimplifyVBinOp only works on vectors!"); 5688 5689 EVT EltType = VT.getVectorElementType(); 5690 SDValue LHS = N->getOperand(0); 5691 SDValue RHS = N->getOperand(1); 5692 SDValue Shuffle = XformToShuffleWithZero(N); 5693 if (Shuffle.getNode()) return Shuffle; 5694 5695 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 5696 // this operation. 5697 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 5698 RHS.getOpcode() == ISD::BUILD_VECTOR) { 5699 SmallVector<SDValue, 8> Ops; 5700 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 5701 SDValue LHSOp = LHS.getOperand(i); 5702 SDValue RHSOp = RHS.getOperand(i); 5703 // If these two elements can't be folded, bail out. 5704 if ((LHSOp.getOpcode() != ISD::UNDEF && 5705 LHSOp.getOpcode() != ISD::Constant && 5706 LHSOp.getOpcode() != ISD::ConstantFP) || 5707 (RHSOp.getOpcode() != ISD::UNDEF && 5708 RHSOp.getOpcode() != ISD::Constant && 5709 RHSOp.getOpcode() != ISD::ConstantFP)) 5710 break; 5711 5712 // Can't fold divide by zero. 5713 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 5714 N->getOpcode() == ISD::FDIV) { 5715 if ((RHSOp.getOpcode() == ISD::Constant && 5716 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) || 5717 (RHSOp.getOpcode() == ISD::ConstantFP && 5718 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero())) 5719 break; 5720 } 5721 5722 Ops.push_back(DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), 5723 EltType, LHSOp, RHSOp)); 5724 AddToWorkList(Ops.back().getNode()); 5725 assert((Ops.back().getOpcode() == ISD::UNDEF || 5726 Ops.back().getOpcode() == ISD::Constant || 5727 Ops.back().getOpcode() == ISD::ConstantFP) && 5728 "Scalar binop didn't fold!"); 5729 } 5730 5731 if (Ops.size() == LHS.getNumOperands()) { 5732 EVT VT = LHS.getValueType(); 5733 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 5734 &Ops[0], Ops.size()); 5735 } 5736 } 5737 5738 return SDValue(); 5739} 5740 5741SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0, 5742 SDValue N1, SDValue N2){ 5743 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 5744 5745 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2, 5746 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 5747 5748 // If we got a simplified select_cc node back from SimplifySelectCC, then 5749 // break it down into a new SETCC node, and a new SELECT node, and then return 5750 // the SELECT node, since we were called with a SELECT node. 5751 if (SCC.getNode()) { 5752 // Check to see if we got a select_cc back (to turn into setcc/select). 5753 // Otherwise, just return whatever node we got back, like fabs. 5754 if (SCC.getOpcode() == ISD::SELECT_CC) { 5755 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(), 5756 N0.getValueType(), 5757 SCC.getOperand(0), SCC.getOperand(1), 5758 SCC.getOperand(4)); 5759 AddToWorkList(SETCC.getNode()); 5760 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(), 5761 SCC.getOperand(2), SCC.getOperand(3), SETCC); 5762 } 5763 5764 return SCC; 5765 } 5766 return SDValue(); 5767} 5768 5769/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 5770/// are the two values being selected between, see if we can simplify the 5771/// select. Callers of this should assume that TheSelect is deleted if this 5772/// returns true. As such, they should return the appropriate thing (e.g. the 5773/// node) back to the top-level of the DAG combiner loop to avoid it being 5774/// looked at. 5775bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 5776 SDValue RHS) { 5777 5778 // If this is a select from two identical things, try to pull the operation 5779 // through the select. 5780 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 5781 // If this is a load and the token chain is identical, replace the select 5782 // of two loads with a load through a select of the address to load from. 5783 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 5784 // constants have been dropped into the constant pool. 5785 if (LHS.getOpcode() == ISD::LOAD && 5786 // Do not let this transformation reduce the number of volatile loads. 5787 !cast<LoadSDNode>(LHS)->isVolatile() && 5788 !cast<LoadSDNode>(RHS)->isVolatile() && 5789 // Token chains must be identical. 5790 LHS.getOperand(0) == RHS.getOperand(0)) { 5791 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 5792 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 5793 5794 // If this is an EXTLOAD, the VT's must match. 5795 if (LLD->getMemoryVT() == RLD->getMemoryVT()) { 5796 // FIXME: this discards src value information. This is 5797 // over-conservative. It would be beneficial to be able to remember 5798 // both potential memory locations. Since we are discarding 5799 // src value info, don't do the transformation if the memory 5800 // locations are not in the default address space. 5801 unsigned LLDAddrSpace = 0, RLDAddrSpace = 0; 5802 if (const Value *LLDVal = LLD->getMemOperand()->getValue()) { 5803 if (const PointerType *PT = dyn_cast<PointerType>(LLDVal->getType())) 5804 LLDAddrSpace = PT->getAddressSpace(); 5805 } 5806 if (const Value *RLDVal = RLD->getMemOperand()->getValue()) { 5807 if (const PointerType *PT = dyn_cast<PointerType>(RLDVal->getType())) 5808 RLDAddrSpace = PT->getAddressSpace(); 5809 } 5810 SDValue Addr; 5811 if (LLDAddrSpace == 0 && RLDAddrSpace == 0) { 5812 if (TheSelect->getOpcode() == ISD::SELECT) { 5813 // Check that the condition doesn't reach either load. If so, folding 5814 // this will induce a cycle into the DAG. 5815 if ((!LLD->hasAnyUseOfValue(1) || 5816 !LLD->isPredecessorOf(TheSelect->getOperand(0).getNode())) && 5817 (!RLD->hasAnyUseOfValue(1) || 5818 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()))) { 5819 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(), 5820 LLD->getBasePtr().getValueType(), 5821 TheSelect->getOperand(0), LLD->getBasePtr(), 5822 RLD->getBasePtr()); 5823 } 5824 } else { 5825 // Check that the condition doesn't reach either load. If so, folding 5826 // this will induce a cycle into the DAG. 5827 if ((!LLD->hasAnyUseOfValue(1) || 5828 (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5829 !LLD->isPredecessorOf(TheSelect->getOperand(1).getNode()))) && 5830 (!RLD->hasAnyUseOfValue(1) || 5831 (!RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5832 !RLD->isPredecessorOf(TheSelect->getOperand(1).getNode())))) { 5833 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(), 5834 LLD->getBasePtr().getValueType(), 5835 TheSelect->getOperand(0), 5836 TheSelect->getOperand(1), 5837 LLD->getBasePtr(), RLD->getBasePtr(), 5838 TheSelect->getOperand(4)); 5839 } 5840 } 5841 } 5842 5843 if (Addr.getNode()) { 5844 SDValue Load; 5845 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) { 5846 Load = DAG.getLoad(TheSelect->getValueType(0), 5847 TheSelect->getDebugLoc(), 5848 LLD->getChain(), 5849 Addr, 0, 0, 5850 LLD->isVolatile(), 5851 LLD->getAlignment()); 5852 } else { 5853 Load = DAG.getExtLoad(LLD->getExtensionType(), 5854 TheSelect->getDebugLoc(), 5855 TheSelect->getValueType(0), 5856 LLD->getChain(), Addr, 0, 0, 5857 LLD->getMemoryVT(), 5858 LLD->isVolatile(), 5859 LLD->getAlignment()); 5860 } 5861 5862 // Users of the select now use the result of the load. 5863 CombineTo(TheSelect, Load); 5864 5865 // Users of the old loads now use the new load's chain. We know the 5866 // old-load value is dead now. 5867 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); 5868 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); 5869 return true; 5870 } 5871 } 5872 } 5873 } 5874 5875 return false; 5876} 5877 5878/// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3 5879/// where 'cond' is the comparison specified by CC. 5880SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, 5881 SDValue N2, SDValue N3, 5882 ISD::CondCode CC, bool NotExtCompare) { 5883 // (x ? y : y) -> y. 5884 if (N2 == N3) return N2; 5885 5886 EVT VT = N2.getValueType(); 5887 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 5888 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 5889 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); 5890 5891 // Determine if the condition we're dealing with is constant 5892 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 5893 N0, N1, CC, DL, false); 5894 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 5895 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode()); 5896 5897 // fold select_cc true, x, y -> x 5898 if (SCCC && !SCCC->isNullValue()) 5899 return N2; 5900 // fold select_cc false, x, y -> y 5901 if (SCCC && SCCC->isNullValue()) 5902 return N3; 5903 5904 // Check to see if we can simplify the select into an fabs node 5905 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 5906 // Allow either -0.0 or 0.0 5907 if (CFP->getValueAPF().isZero()) { 5908 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 5909 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 5910 N0 == N2 && N3.getOpcode() == ISD::FNEG && 5911 N2 == N3.getOperand(0)) 5912 return DAG.getNode(ISD::FABS, DL, VT, N0); 5913 5914 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 5915 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 5916 N0 == N3 && N2.getOpcode() == ISD::FNEG && 5917 N2.getOperand(0) == N3) 5918 return DAG.getNode(ISD::FABS, DL, VT, N3); 5919 } 5920 } 5921 5922 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)" 5923 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0 5924 // in it. This is a win when the constant is not otherwise available because 5925 // it replaces two constant pool loads with one. We only do this if the FP 5926 // type is known to be legal, because if it isn't, then we are before legalize 5927 // types an we want the other legalization to happen first (e.g. to avoid 5928 // messing with soft float) and if the ConstantFP is not legal, because if 5929 // it is legal, we may not need to store the FP constant in a constant pool. 5930 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2)) 5931 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) { 5932 if (TLI.isTypeLegal(N2.getValueType()) && 5933 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) != 5934 TargetLowering::Legal) && 5935 // If both constants have multiple uses, then we won't need to do an 5936 // extra load, they are likely around in registers for other users. 5937 (TV->hasOneUse() || FV->hasOneUse())) { 5938 Constant *Elts[] = { 5939 const_cast<ConstantFP*>(FV->getConstantFPValue()), 5940 const_cast<ConstantFP*>(TV->getConstantFPValue()) 5941 }; 5942 const Type *FPTy = Elts[0]->getType(); 5943 const TargetData &TD = *TLI.getTargetData(); 5944 5945 // Create a ConstantArray of the two constants. 5946 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts, 2); 5947 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(), 5948 TD.getPrefTypeAlignment(FPTy)); 5949 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 5950 5951 // Get the offsets to the 0 and 1 element of the array so that we can 5952 // select between them. 5953 SDValue Zero = DAG.getIntPtrConstant(0); 5954 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType()); 5955 SDValue One = DAG.getIntPtrConstant(EltSize); 5956 5957 SDValue Cond = DAG.getSetCC(DL, 5958 TLI.getSetCCResultType(N0.getValueType()), 5959 N0, N1, CC); 5960 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(), 5961 Cond, One, Zero); 5962 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx, 5963 CstOffset); 5964 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx, 5965 PseudoSourceValue::getConstantPool(), 0, false, 5966 Alignment); 5967 5968 } 5969 } 5970 5971 // Check to see if we can perform the "gzip trick", transforming 5972 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A) 5973 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 5974 N0.getValueType().isInteger() && 5975 N2.getValueType().isInteger() && 5976 (N1C->isNullValue() || // (a < 0) ? b : 0 5977 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 5978 EVT XType = N0.getValueType(); 5979 EVT AType = N2.getValueType(); 5980 if (XType.bitsGE(AType)) { 5981 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 5982 // single-bit constant. 5983 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 5984 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 5985 ShCtV = XType.getSizeInBits()-ShCtV-1; 5986 SDValue ShCt = DAG.getConstant(ShCtV, getShiftAmountTy()); 5987 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), 5988 XType, N0, ShCt); 5989 AddToWorkList(Shift.getNode()); 5990 5991 if (XType.bitsGT(AType)) { 5992 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 5993 AddToWorkList(Shift.getNode()); 5994 } 5995 5996 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 5997 } 5998 5999 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), 6000 XType, N0, 6001 DAG.getConstant(XType.getSizeInBits()-1, 6002 getShiftAmountTy())); 6003 AddToWorkList(Shift.getNode()); 6004 6005 if (XType.bitsGT(AType)) { 6006 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 6007 AddToWorkList(Shift.getNode()); 6008 } 6009 6010 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 6011 } 6012 } 6013 6014 // fold select C, 16, 0 -> shl C, 4 6015 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 6016 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) { 6017 6018 // If the caller doesn't want us to simplify this into a zext of a compare, 6019 // don't do it. 6020 if (NotExtCompare && N2C->getAPIntValue() == 1) 6021 return SDValue(); 6022 6023 // Get a SetCC of the condition 6024 // FIXME: Should probably make sure that setcc is legal if we ever have a 6025 // target where it isn't. 6026 SDValue Temp, SCC; 6027 // cast from setcc result type to select result type 6028 if (LegalTypes) { 6029 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()), 6030 N0, N1, CC); 6031 if (N2.getValueType().bitsLT(SCC.getValueType())) 6032 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType()); 6033 else 6034 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 6035 N2.getValueType(), SCC); 6036 } else { 6037 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC); 6038 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 6039 N2.getValueType(), SCC); 6040 } 6041 6042 AddToWorkList(SCC.getNode()); 6043 AddToWorkList(Temp.getNode()); 6044 6045 if (N2C->getAPIntValue() == 1) 6046 return Temp; 6047 6048 // shl setcc result by log2 n2c 6049 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp, 6050 DAG.getConstant(N2C->getAPIntValue().logBase2(), 6051 getShiftAmountTy())); 6052 } 6053 6054 // Check to see if this is the equivalent of setcc 6055 // FIXME: Turn all of these into setcc if setcc if setcc is legal 6056 // otherwise, go ahead with the folds. 6057 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 6058 EVT XType = N0.getValueType(); 6059 if (!LegalOperations || 6060 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) { 6061 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC); 6062 if (Res.getValueType() != VT) 6063 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res); 6064 return Res; 6065 } 6066 6067 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X)))) 6068 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 6069 (!LegalOperations || 6070 TLI.isOperationLegal(ISD::CTLZ, XType))) { 6071 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0); 6072 return DAG.getNode(ISD::SRL, DL, XType, Ctlz, 6073 DAG.getConstant(Log2_32(XType.getSizeInBits()), 6074 getShiftAmountTy())); 6075 } 6076 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1)) 6077 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 6078 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(), 6079 XType, DAG.getConstant(0, XType), N0); 6080 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType); 6081 return DAG.getNode(ISD::SRL, DL, XType, 6082 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0), 6083 DAG.getConstant(XType.getSizeInBits()-1, 6084 getShiftAmountTy())); 6085 } 6086 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1)) 6087 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 6088 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0, 6089 DAG.getConstant(XType.getSizeInBits()-1, 6090 getShiftAmountTy())); 6091 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType)); 6092 } 6093 } 6094 6095 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 6096 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 6097 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 6098 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) && 6099 N2.getOperand(0) == N1 && N0.getValueType().isInteger()) { 6100 EVT XType = N0.getValueType(); 6101 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, N0, 6102 DAG.getConstant(XType.getSizeInBits()-1, 6103 getShiftAmountTy())); 6104 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), XType, 6105 N0, Shift); 6106 AddToWorkList(Shift.getNode()); 6107 AddToWorkList(Add.getNode()); 6108 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 6109 } 6110 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X -> 6111 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 6112 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT && 6113 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) { 6114 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 6115 EVT XType = N0.getValueType(); 6116 if (SubC->isNullValue() && XType.isInteger()) { 6117 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, 6118 N0, 6119 DAG.getConstant(XType.getSizeInBits()-1, 6120 getShiftAmountTy())); 6121 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), 6122 XType, N0, Shift); 6123 AddToWorkList(Shift.getNode()); 6124 AddToWorkList(Add.getNode()); 6125 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 6126 } 6127 } 6128 } 6129 6130 return SDValue(); 6131} 6132 6133/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 6134SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0, 6135 SDValue N1, ISD::CondCode Cond, 6136 DebugLoc DL, bool foldBooleans) { 6137 TargetLowering::DAGCombinerInfo 6138 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 6139 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL); 6140} 6141 6142/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 6143/// return a DAG expression to select that will generate the same value by 6144/// multiplying by a magic number. See: 6145/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 6146SDValue DAGCombiner::BuildSDIV(SDNode *N) { 6147 std::vector<SDNode*> Built; 6148 SDValue S = TLI.BuildSDIV(N, DAG, &Built); 6149 6150 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 6151 ii != ee; ++ii) 6152 AddToWorkList(*ii); 6153 return S; 6154} 6155 6156/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 6157/// return a DAG expression to select that will generate the same value by 6158/// multiplying by a magic number. See: 6159/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 6160SDValue DAGCombiner::BuildUDIV(SDNode *N) { 6161 std::vector<SDNode*> Built; 6162 SDValue S = TLI.BuildUDIV(N, DAG, &Built); 6163 6164 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 6165 ii != ee; ++ii) 6166 AddToWorkList(*ii); 6167 return S; 6168} 6169 6170/// FindBaseOffset - Return true if base is a frame index, which is known not 6171// to alias with anything but itself. Provides base object and offset as results. 6172static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset, 6173 GlobalValue *&GV, void *&CV) { 6174 // Assume it is a primitive operation. 6175 Base = Ptr; Offset = 0; GV = 0; CV = 0; 6176 6177 // If it's an adding a simple constant then integrate the offset. 6178 if (Base.getOpcode() == ISD::ADD) { 6179 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 6180 Base = Base.getOperand(0); 6181 Offset += C->getZExtValue(); 6182 } 6183 } 6184 6185 // Return the underlying GlobalValue, and update the Offset. Return false 6186 // for GlobalAddressSDNode since the same GlobalAddress may be represented 6187 // by multiple nodes with different offsets. 6188 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) { 6189 GV = G->getGlobal(); 6190 Offset += G->getOffset(); 6191 return false; 6192 } 6193 6194 // Return the underlying Constant value, and update the Offset. Return false 6195 // for ConstantSDNodes since the same constant pool entry may be represented 6196 // by multiple nodes with different offsets. 6197 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) { 6198 CV = C->isMachineConstantPoolEntry() ? (void *)C->getMachineCPVal() 6199 : (void *)C->getConstVal(); 6200 Offset += C->getOffset(); 6201 return false; 6202 } 6203 // If it's any of the following then it can't alias with anything but itself. 6204 return isa<FrameIndexSDNode>(Base); 6205} 6206 6207/// isAlias - Return true if there is any possibility that the two addresses 6208/// overlap. 6209bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, 6210 const Value *SrcValue1, int SrcValueOffset1, 6211 unsigned SrcValueAlign1, 6212 SDValue Ptr2, int64_t Size2, 6213 const Value *SrcValue2, int SrcValueOffset2, 6214 unsigned SrcValueAlign2) const { 6215 // If they are the same then they must be aliases. 6216 if (Ptr1 == Ptr2) return true; 6217 6218 // Gather base node and offset information. 6219 SDValue Base1, Base2; 6220 int64_t Offset1, Offset2; 6221 GlobalValue *GV1, *GV2; 6222 void *CV1, *CV2; 6223 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1); 6224 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2); 6225 6226 // If they have a same base address then check to see if they overlap. 6227 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2))) 6228 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 6229 6230 // If we know what the bases are, and they aren't identical, then we know they 6231 // cannot alias. 6232 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2)) 6233 return false; 6234 6235 // If we know required SrcValue1 and SrcValue2 have relatively large alignment 6236 // compared to the size and offset of the access, we may be able to prove they 6237 // do not alias. This check is conservative for now to catch cases created by 6238 // splitting vector types. 6239 if ((SrcValueAlign1 == SrcValueAlign2) && 6240 (SrcValueOffset1 != SrcValueOffset2) && 6241 (Size1 == Size2) && (SrcValueAlign1 > Size1)) { 6242 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1; 6243 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1; 6244 6245 // There is no overlap between these relatively aligned accesses of similar 6246 // size, return no alias. 6247 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1) 6248 return false; 6249 } 6250 6251 if (CombinerGlobalAA) { 6252 // Use alias analysis information. 6253 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 6254 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 6255 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 6256 AliasAnalysis::AliasResult AAResult = 6257 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2); 6258 if (AAResult == AliasAnalysis::NoAlias) 6259 return false; 6260 } 6261 6262 // Otherwise we have to assume they alias. 6263 return true; 6264} 6265 6266/// FindAliasInfo - Extracts the relevant alias information from the memory 6267/// node. Returns true if the operand was a load. 6268bool DAGCombiner::FindAliasInfo(SDNode *N, 6269 SDValue &Ptr, int64_t &Size, 6270 const Value *&SrcValue, 6271 int &SrcValueOffset, 6272 unsigned &SrcValueAlign) const { 6273 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 6274 Ptr = LD->getBasePtr(); 6275 Size = LD->getMemoryVT().getSizeInBits() >> 3; 6276 SrcValue = LD->getSrcValue(); 6277 SrcValueOffset = LD->getSrcValueOffset(); 6278 SrcValueAlign = LD->getOriginalAlignment(); 6279 return true; 6280 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 6281 Ptr = ST->getBasePtr(); 6282 Size = ST->getMemoryVT().getSizeInBits() >> 3; 6283 SrcValue = ST->getSrcValue(); 6284 SrcValueOffset = ST->getSrcValueOffset(); 6285 SrcValueAlign = ST->getOriginalAlignment(); 6286 } else { 6287 llvm_unreachable("FindAliasInfo expected a memory operand"); 6288 } 6289 6290 return false; 6291} 6292 6293/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 6294/// looking for aliasing nodes and adding them to the Aliases vector. 6295void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 6296 SmallVector<SDValue, 8> &Aliases) { 6297 SmallVector<SDValue, 8> Chains; // List of chains to visit. 6298 SmallPtrSet<SDNode *, 16> Visited; // Visited node set. 6299 6300 // Get alias information for node. 6301 SDValue Ptr; 6302 int64_t Size; 6303 const Value *SrcValue; 6304 int SrcValueOffset; 6305 unsigned SrcValueAlign; 6306 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset, 6307 SrcValueAlign); 6308 6309 // Starting off. 6310 Chains.push_back(OriginalChain); 6311 unsigned Depth = 0; 6312 6313 // Look at each chain and determine if it is an alias. If so, add it to the 6314 // aliases list. If not, then continue up the chain looking for the next 6315 // candidate. 6316 while (!Chains.empty()) { 6317 SDValue Chain = Chains.back(); 6318 Chains.pop_back(); 6319 6320 // For TokenFactor nodes, look at each operand and only continue up the 6321 // chain until we find two aliases. If we've seen two aliases, assume we'll 6322 // find more and revert to original chain since the xform is unlikely to be 6323 // profitable. 6324 // 6325 // FIXME: The depth check could be made to return the last non-aliasing 6326 // chain we found before we hit a tokenfactor rather than the original 6327 // chain. 6328 if (Depth > 6 || Aliases.size() == 2) { 6329 Aliases.clear(); 6330 Aliases.push_back(OriginalChain); 6331 break; 6332 } 6333 6334 // Don't bother if we've been before. 6335 if (!Visited.insert(Chain.getNode())) 6336 continue; 6337 6338 switch (Chain.getOpcode()) { 6339 case ISD::EntryToken: 6340 // Entry token is ideal chain operand, but handled in FindBetterChain. 6341 break; 6342 6343 case ISD::LOAD: 6344 case ISD::STORE: { 6345 // Get alias information for Chain. 6346 SDValue OpPtr; 6347 int64_t OpSize; 6348 const Value *OpSrcValue; 6349 int OpSrcValueOffset; 6350 unsigned OpSrcValueAlign; 6351 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, 6352 OpSrcValue, OpSrcValueOffset, 6353 OpSrcValueAlign); 6354 6355 // If chain is alias then stop here. 6356 if (!(IsLoad && IsOpLoad) && 6357 isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign, 6358 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset, 6359 OpSrcValueAlign)) { 6360 Aliases.push_back(Chain); 6361 } else { 6362 // Look further up the chain. 6363 Chains.push_back(Chain.getOperand(0)); 6364 ++Depth; 6365 } 6366 break; 6367 } 6368 6369 case ISD::TokenFactor: 6370 // We have to check each of the operands of the token factor for "small" 6371 // token factors, so we queue them up. Adding the operands to the queue 6372 // (stack) in reverse order maintains the original order and increases the 6373 // likelihood that getNode will find a matching token factor (CSE.) 6374 if (Chain.getNumOperands() > 16) { 6375 Aliases.push_back(Chain); 6376 break; 6377 } 6378 for (unsigned n = Chain.getNumOperands(); n;) 6379 Chains.push_back(Chain.getOperand(--n)); 6380 ++Depth; 6381 break; 6382 6383 default: 6384 // For all other instructions we will just have to take what we can get. 6385 Aliases.push_back(Chain); 6386 break; 6387 } 6388 } 6389} 6390 6391/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 6392/// for a better chain (aliasing node.) 6393SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 6394 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 6395 6396 // Accumulate all the aliases to this node. 6397 GatherAllAliases(N, OldChain, Aliases); 6398 6399 if (Aliases.size() == 0) { 6400 // If no operands then chain to entry token. 6401 return DAG.getEntryNode(); 6402 } else if (Aliases.size() == 1) { 6403 // If a single operand then chain to it. We don't need to revisit it. 6404 return Aliases[0]; 6405 } 6406 6407 // Construct a custom tailored token factor. 6408 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 6409 &Aliases[0], Aliases.size()); 6410} 6411 6412// SelectionDAG::Combine - This is the entry point for the file. 6413// 6414void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, 6415 CodeGenOpt::Level OptLevel) { 6416 /// run - This is the main entry point to this class. 6417 /// 6418 DAGCombiner(*this, AA, OptLevel).Run(Level); 6419} 6420