/external/llvm/lib/Target/Mips/InstPrinter/ |
H A D | MipsInstPrinter.h | 33 enum CondCode { enum in namespace:llvm::Mips 73 const char *MipsFCCToString(Mips::CondCode CC);
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/external/llvm/lib/Target/X86/ |
H A D | X86InstrInfo.h | 32 enum CondCode { enum in namespace:llvm::X86 63 unsigned GetCondBranchFromCond(CondCode CC); 67 unsigned getSETFromCond(CondCode CC, bool HasMemoryOperand = false); 71 unsigned getCMovFromCond(CondCode CC, unsigned RegBytes, 75 CondCode getCondFromCMovOpc(unsigned Opc); 79 CondCode GetOppositeBranchCondition(CondCode CC);
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H A D | X86ISelLowering.cpp | 3631 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86 3634 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP, 12843 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC, 12904 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B; 12912 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point 12914 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0, 12999 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); 13063 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); 13306 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 13334 X86::CondCode CCod 13490 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue(); local 13623 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue(); local [all...] |
/external/llvm/lib/Target/XCore/ |
H A D | XCoreInstrInfo.cpp | 38 enum CondCode { enum in namespace:llvm::XCore 137 static XCore::CondCode GetCondFromBranchOpc(unsigned BrOpc) 150 static inline unsigned GetCondBranchFromCond(XCore::CondCode CC) 161 static inline XCore::CondCode GetOppositeBranchCondition(XCore::CondCode CC) 221 XCore::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode()); 243 XCore::CondCode BranchCode = GetCondFromBranchOpc(SecondLastOpc); 297 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); 306 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); 420 Cond[0].setImm(GetOppositeBranchCondition((XCore::CondCode)Con [all...] |
/external/llvm/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 766 /// ISD::CondCode enum - These are ordered carefully to make the bitfields 779 enum CondCode { enum in namespace:llvm::ISD 812 inline bool isSignedIntSetCC(CondCode Code) { 818 inline bool isUnsignedIntSetCC(CondCode Code) { 825 inline bool isTrueWhenEqual(CondCode Cond) { 833 inline unsigned getUnorderedFlavor(CondCode Cond) { 839 CondCode getSetCCInverse(CondCode Operation, bool isInteger); 843 CondCode getSetCCSwappedOperands(CondCode Operatio [all...] |
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelDAGToDAG.cpp | 128 SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDLoc dl); 1932 ISD::CondCode CC, SDLoc dl) { 2029 static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) { 2060 static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert) { 2092 static unsigned int getVCmpInst(MVT VecVT, ISD::CondCode CC, 2203 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get(); 2649 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get(); 2812 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get(); 2835 SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC, dl); local 2836 SDValue Ops[] = { getI32Imm(PCC), CondCode, [all...] |
/external/llvm/lib/Target/AArch64/AsmParser/ |
H A D | AArch64AsmParser.cpp | 58 AArch64CC::CondCode parseCondCodeString(StringRef Cond); 198 AArch64CC::CondCode Code; 246 struct CondCodeOp CondCode; member in union:__anon10646::AArch64Operand::__anon10647 277 CondCode = o.CondCode; 339 AArch64CC::CondCode getCondCode() const { 341 return CondCode.Code; 1595 CreateCondCode(AArch64CC::CondCode Code, SMLoc S, SMLoc E, MCContext &Ctx) { 1597 Op->CondCode.Code = Code; 2206 AArch64CC::CondCode AArch64AsmParse [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | ARMBaseInstrInfo.cpp | 1872 unsigned CondCode = MI->getOperand(3).getImm(); local 1874 NewMI.addImm(ARMCC::getOppositeCondition(ARMCC::CondCodes(CondCode))); 1876 NewMI.addImm(CondCode);
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H A D | ARMISelLowering.cpp | 259 const ISD::CondCode Cond; 1217 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) { 1234 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode, argument 1240 case ISD::SETOEQ: CondCode = ARMCC::EQ; break; 1242 case ISD::SETOGT: CondCode = ARMCC::GT; break; 1244 case ISD::SETOGE: CondCode = ARMCC::GE; break; 1245 case ISD::SETOLT: CondCode = ARMCC::MI; break; 1246 case ISD::SETOLE: CondCode = ARMCC::LS; break; 1247 case ISD::SETONE: CondCode 3189 ARMCC::CondCodes CondCode = IntCCToARMCC(CC); local 3381 checkVSELConstraints(ISD::CondCode CC, ARMCC::CondCodes &CondCode, bool &swpCmpOps, bool &swpVselOps) argument 3490 ARMCC::CondCodes CondCode = IntCCToARMCC(CC); local 3504 ARMCC::CondCodes CondCode, CondCode2; local 3675 ARMCC::CondCodes CondCode = IntCCToARMCC(CC); local 3723 ARMCC::CondCodes CondCode, CondCode2; local [all...] |
/external/mesa3d/src/gallium/drivers/nv50/codegen/ |
H A D | nv50_ir.h | 168 enum CondCode enum in namespace:nv50_ir 587 bool compare(CondCode cc, float fval) const; 629 bool setPredicate(CondCode ccode, Value *); 679 CondCode cc; 826 void setCondition(CondCode cond) { setCond = cond; } 827 CondCode getCondition() const { return setCond; } 830 CondCode setCond;
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 929 unsigned CondCode = MI->getOperand(3).getImm(); local 942 BuildMI(MBB, DL, TII->get(AArch64::Bcc)).addImm(CondCode).addMBB(TrueBB); 994 static AArch64CC::CondCode changeIntCCToAArch64CC(ISD::CondCode CC) { 1022 static void changeFPCCToAArch64CC(ISD::CondCode CC, argument 1023 AArch64CC::CondCode &CondCode, 1024 AArch64CC::CondCode &CondCode2) { 1031 CondCode = AArch64CC::EQ; 1035 CondCode 1086 changeVectorFPCCToAArch64CC(ISD::CondCode CC, AArch64CC::CondCode &CondCode, AArch64CC::CondCode &CondCode2, bool &Invert) argument 1110 changeFPCCToAArch64CC(getSetCCInverse(CC, false), CondCode, CondCode2); local [all...] |
/external/llvm/lib/Target/AArch64/Utils/ |
H A D | AArch64BaseInfo.h | 192 enum CondCode { // Meaning (integer) Meaning (floating-point) enum in namespace:llvm::AArch64CC 213 inline static const char *getCondCodeName(CondCode Code) { 235 inline static CondCode getInvertedCondCode(CondCode Code) { 238 return static_cast<CondCode>(static_cast<unsigned>(Code) ^ 0x1); 245 inline static unsigned getNZCVToSatisfyCondCode(CondCode Code) {
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