Searched defs:RA (Results 1 - 25 of 26) sorted by relevance

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/external/llvm/lib/MC/
H A DMCSubtargetInfo.cpp44 const MCReadAdvanceEntry *RA,
55 ReadAdvanceTable = RA;
38 InitMCSubtargetInfo(StringRef TT, StringRef C, StringRef FS, ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetFeatureKV> PD, const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC, const unsigned *FP) argument
/external/clang/test/CodeGenCXX/
H A Ddevirtualize-virtual-function-calls-final.cpp179 struct RA { struct in namespace:Test9
187 struct RC final : public RA {
212 return static_cast<RA*>(x)->f();
225 return -static_cast<RA&>(*x);
/external/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.cpp105 unsigned RA = (TheTriple.getArch() == Triple::x86_64) local
110 InitX86MCRegisterInfo(X, RA,
113 RA);
/external/clang/test/Layout/
H A Dms-x86-alias-avoidance-padding.cpp301 struct RA {}; struct
306 struct RX0 : RB, RA {};
307 struct RX1 : RA, RB {};
308 struct RX2 : RA { char a; };
309 struct RX3 : RA { RB a; };
310 struct RX4 { RA a; char b; };
311 struct RX5 { RA a; RB b; };
313 struct RX7 : virtual RW { RA a; };
314 struct RX8 : RA, virtual RW {};
326 // CHECK-NEXT: 1 | struct RA (bas
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H A Dms-x86-pack-and-align.cpp430 struct RA {}; struct
441 struct __declspec(align(8)) RB2 : virtual RA {
445 struct __declspec(align(8)) RB3 : virtual RA {
476 // CHECK-NEXT: 1028 | struct RA (virtual base) (empty)
484 // CHECK-NEXT: 2052 | struct RA (virtual base) (empty)
519 // CHECK-X64-NEXT: 1028 | struct RA (virtual base) (empty)
527 // CHECK-X64-NEXT: 2052 | struct RA (virtual base) (empty)
/external/llvm/lib/Target/PowerPC/MCTargetDesc/
H A DPPCMCTargetDesc.cpp59 unsigned RA = isPPC64 ? PPC::LR8 : PPC::LR; local
62 InitPPCMCRegisterInfo(X, RA, Flavour, Flavour);
/external/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp438 BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn)).addReg(Mips::RA);
615 unsigned RA = Subtarget.isGP64bit() ? Mips::RA_64 : Mips::RA; local
629 BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), RA)
H A DMipsISelLowering.cpp2002 unsigned RA = ABI.IsN64() ? Mips::RA_64 : Mips::RA; local
2005 // Return RA, which contains the return address. Mark it an implicit live-in.
2006 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT));
/external/llvm/lib/Transforms/IPO/
H A DDeadArgumentElimination.cpp153 void MarkValue(const RetOrArg &RA, Liveness L,
155 void MarkLive(const RetOrArg &RA);
157 void PropagateLiveness(const RetOrArg &RA);
663 /// MarkValue - This function marks the liveness of RA depending on L. If L is
665 /// such that RA will be marked live if any use in MaybeLiveUses gets marked
667 void DAE::MarkValue(const RetOrArg &RA, Liveness L, argument
670 case Live: MarkLive(RA); break;
677 Uses.insert(std::make_pair(*UI, RA));
702 void DAE::MarkLive(const RetOrArg &RA) { argument
703 if (LiveFunctions.count(RA
715 PropagateLiveness(const RetOrArg &RA) argument
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H A DMergeFunctions.cpp445 Attribute RA = *RI; local
446 if (LA < RA)
448 if (RA < LA)
548 const ConstantArray *RA = cast<ConstantArray>(R); local
555 cast<Constant>(RA->getOperand(i))))
/external/llvm/lib/Transforms/InstCombine/
H A DInstCombineSimplifyDemanded.cpp764 APInt RA = Rem->getValue().abs(); local
765 if (RA.isPowerOf2()) {
766 if (DemandedMask.ult(RA)) // srem won't affect demanded bits
769 APInt LowBits = RA - 1;
/external/libpcap/
H A Dtokdefs.h90 RA = 308, enumerator in enum:yytokentype
211 #define RA 308 macro
H A Dgrammar.c397 RA = 308, enumerator in enum:yytokentype
518 #define RA 308 macro
1034 "ADDR4", "RA", "TA", "LINK", "GEQ", "LEQ", "NEQ", "ID", "EID", "HID",
/external/llvm/include/llvm/MC/
H A DMCRegisterInfo.h244 void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA, argument
259 RAReg = RA;
/external/deqp/framework/common/
H A DtcuTexture.hpp51 RA, enumerator in enum:tcu::TextureFormat::ChannelOrder
H A DtcuTextureUtil.cpp1232 static const TextureSwizzle RA = {{ TextureSwizzle::CHANNEL_0, TextureSwizzle::CHANNEL_ZERO, TextureSwizzle::CHANNEL_ZERO, TextureSwizzle::CHANNEL_3 }}; local
1248 case TextureFormat::RA: swizzle = &RA; break;
H A DtcuTexture.cpp192 case TextureFormat::RA: return 2;
401 static const TextureSwizzle RA = {{ TextureSwizzle::CHANNEL_0, TextureSwizzle::CHANNEL_ZERO, TextureSwizzle::CHANNEL_ZERO, TextureSwizzle::CHANNEL_1 }}; local
418 case TextureFormat::RA: return RA;
448 static const TextureSwizzle RA = {{ TextureSwizzle::CHANNEL_0, TextureSwizzle::CHANNEL_3, TextureSwizzle::CHANNEL_LAST, TextureSwizzle::CHANNEL_LAST }}; local
465 case TextureFormat::RA: return RA;
3347 "RA",
/external/llvm/lib/Analysis/
H A DScalarEvolution.cpp511 const Argument *RA = cast<Argument>(RV); local
512 unsigned LArgNo = LA->getArgNo(), RArgNo = RA->getArgNo();
546 const APInt &RA = RC->getValue()->getValue(); local
547 unsigned LBitWidth = LA.getBitWidth(), RBitWidth = RA.getBitWidth();
550 return LA.ult(RA) ? -1 : 1;
555 const SCEVAddRecExpr *RA = cast<SCEVAddRecExpr>(RHS); local
558 const Loop *LLoop = LA->getLoop(), *RLoop = RA->getLoop();
567 unsigned LNumOps = LA->getNumOperands(), RNumOps = RA->getNumOperands();
573 long X = compare(LA->getOperand(i), RA->getOperand(i));
4356 const SCEV *RA
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H A DValueTracking.cpp1252 APInt RA = Rem->getValue().abs(); local
1253 if (RA.isPowerOf2()) {
1254 APInt LowBits = RA - 1;
1290 APInt RA = Rem->getValue(); local
1291 if (RA.isPowerOf2()) {
1292 APInt LowBits = (RA - 1);
/external/pcre/dist/sljit/
H A DsljitNativeTILEGX_64.c77 #define RA 55 macro
1212 FAIL_IF(ST_ADD(ADDR_TMP_mapped, RA, -8));
1283 FAIL_IF(LD(RA, ADDR_TMP_mapped));
1333 return JR(RA);
1612 return ADD(reg_map[dst], RA, ZERO);
1615 return emit_op_mem(compiler, WORD_DATA, RA, dst, dstw);
1625 FAIL_IF(ADD(RA, reg_map[src], ZERO));
1628 FAIL_IF(emit_op_mem(compiler, WORD_DATA | LOAD_DATA, RA, src, srcw));
1631 FAIL_IF(load_immediate(compiler, RA, srcw));
1633 return JR(RA);
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/external/llvm/lib/Transforms/Scalar/
H A DLoopStrengthReduce.cpp537 const APInt &RA = RC->getValue()->getValue(); local
540 if (RA.isAllOnesValue())
543 if (RA == 1)
552 const APInt &RA = RC->getValue()->getValue(); local
553 if (LA.srem(RA) != 0)
555 return SE.getConstant(LA.sdiv(RA));
/external/clang/lib/CodeGen/
H A DItaniumCXXABI.cpp229 const ReturnAdjustment &RA) override;
1536 const ReturnAdjustment &RA) {
1537 return performTypeAdjustment(CGF, Ret, RA.NonVirtual,
1538 RA.Virtual.Itanium.VBaseOffsetOffset,
1535 performReturnAdjustment(CodeGenFunction &CGF, llvm::Value *Ret, const ReturnAdjustment &RA) argument
H A DMicrosoftCXXABI.cpp270 const ReturnAdjustment &RA) override;
1859 const ReturnAdjustment &RA) {
1860 if (RA.isEmpty())
1865 if (RA.Virtual.Microsoft.VBIndex) {
1866 assert(RA.Virtual.Microsoft.VBIndex > 0);
1871 GetVBaseOffsetFromVBPtr(CGF, V, RA.Virtual.Microsoft.VBPtrOffset,
1872 IntSize * RA.Virtual.Microsoft.VBIndex, &VBPtr);
1876 if (RA.NonVirtual)
1877 V = CGF.Builder.CreateConstInBoundsGEP1_32(CGF.Int8Ty, V, RA.NonVirtual);
1858 performReturnAdjustment(CodeGenFunction &CGF, llvm::Value *Ret, const ReturnAdjustment &RA) argument
/external/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp2324 const APInt &RA = Rem->getAPIntValue().abs(); local
2325 if (RA.isPowerOf2()) {
2326 APInt LowBits = RA - 1;
2348 const APInt &RA = Rem->getAPIntValue(); local
2349 if (RA.isPowerOf2()) {
2350 APInt LowBits = (RA - 1);
/external/valgrind/VEX/priv/
H A Dguest_ppc_toIR.c344 /* Extract RA (1st source register) field, instr[20:16] */
3880 * If (RA) >= (RB), or if an attempt is made to perform the division
5570 /* NB: does not reject the case where RA is in the range of
5591 /* NB: does not reject the case where RA is in the range of
18543 UInt RA = IFIELD( theInstr, 16, 5 ); local
18546 DIP("tabortwc. %d,%d,%d\n", TO, RA, RB);
18553 UInt RA = IFIELD( theInstr, 16, 5 ); local
18556 DIP("tabortdc. %d,%d,%d\n", TO, RA, RB);
18563 UInt RA = IFIELD( theInstr, 16, 5 ); local
18566 DIP("tabortwci. %d,%d,%d\n", TO, RA, S
18573 UInt RA = IFIELD( theInstr, 16, 5 ); local
18582 UInt RA = IFIELD( theInstr, 16, 5 ); local
18590 UInt RA = IFIELD( theInstr, 16, 5 ); local
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