/external/llvm/include/llvm/CodeGen/ |
H A D | SelectionDAGNodes.h | 766 const SDValue &Op2) { 772 Ops[2].setInitial(Op2); 780 const SDValue &Op2, const SDValue &Op3) { 786 Ops[2].setInitial(Op2); 1932 // In the both nodes address is Op1, mask is Op2:
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/external/llvm/include/llvm/IR/ |
H A D | PatternMatch.h | 1246 m_Intrinsic(const T0 &Op0, const T1 &Op1, const T2 &Op2) { argument 1247 return m_CombineAnd(m_Intrinsic<IntrID>(Op0, Op1), m_Argument<2>(Op2)); 1253 m_Intrinsic(const T0 &Op0, const T1 &Op1, const T2 &Op2, const T3 &Op3) { argument 1254 return m_CombineAnd(m_Intrinsic<IntrID>(Op0, Op1, Op2), m_Argument<3>(Op3));
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/external/llvm/lib/AsmParser/ |
H A D | LLParser.cpp | 4605 BasicBlock *Op1, *Op2; 4619 ParseTypeAndBasicBlock(Op2, Loc2, PFS)) 4622 Inst = BranchInst::Create(Op1, Op2, Op0); 4944 Value *Op0, *Op1, *Op2; 4949 ParseTypeAndValue(Op2, PFS)) 4952 if (const char *Reason = SelectInst::areInvalidOperands(Op0, Op1, Op2)) 4955 Inst = SelectInst::Create(Op0, Op1, Op2); 4998 Value *Op0, *Op1, *Op2; 5003 ParseTypeAndValue(Op2, PFS)) 5006 if (!InsertElementInst::isValidOperands(Op0, Op1, Op2)) [all...] |
/external/llvm/lib/Analysis/ |
H A D | CFLAliasAnalysis.cpp | 290 auto *Op2 = Inst.getOperand(1); local 292 Output.push_back(Edge(&Inst, Op2, EdgeType::Assign, AttrNone));
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/external/llvm/lib/Target/ARM/ |
H A D | ARMFastISel.cpp | 119 unsigned Op2, bool Op2IsKill); 340 unsigned Op2, bool Op2IsKill) { 348 Op2 = constrainOperandRegClass(II, Op1, 3); 355 .addReg(Op2, Op2IsKill * RegState::Kill)); 360 .addReg(Op2, Op2IsKill * RegState::Kill)); 1823 unsigned Op2 = getRegForValue(I->getOperand(1)); local 1824 if (Op2 == 0) return false; 1829 .addReg(Op1).addReg(Op2)); 336 fastEmitInst_rrr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, unsigned Op2, bool Op2IsKill) argument
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | FastISel.cpp | 1767 bool Op1IsKill, unsigned Op2, 1774 Op2 = constrainOperandRegClass(II, Op2, II.getNumDefs() + 2); 1780 .addReg(Op2, getKillRegState(Op2IsKill)); 1785 .addReg(Op2, getKillRegState(Op2IsKill)); 1764 fastEmitInst_rrr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, unsigned Op2, bool Op2IsKill) argument
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H A D | TargetLowering.cpp | 2642 SDValue TargetLowering::BuildExactSDIV(SDValue Op1, SDValue Op2, SDLoc dl, argument 2644 ConstantSDNode *C = cast<ConstantSDNode>(Op2); 2663 Op2 = DAG.getConstant(xn, Op1.getValueType()); 2664 return DAG.getNode(ISD::MUL, dl, Op1.getValueType(), Op1, Op2);
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H A D | LegalizeFloatTypes.cpp | 1913 SDValue Op2 = GetPromotedFloat(N->getOperand(2)); local 1915 return DAG.getNode(N->getOpcode(), SDLoc(N), NVT, Op0, Op1, Op2);
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H A D | LegalizeVectorTypes.cpp | 148 SDValue Op2 = GetScalarizedVector(N->getOperand(2)); local 150 Op0.getValueType(), Op0, Op1, Op2);
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/external/llvm/lib/Bitcode/Reader/ |
H A D | BitcodeReader.cpp | 2382 Constant *Op2 = nullptr; local 2387 Op2 = ValueList.getConstantFwdRef(Record[3], IdxTy); 2389 Op2 = ValueList.getConstantFwdRef(Record[2], Type::getInt32Ty(Context)); 2390 if (!Op2) 2392 V = ConstantExpr::getInsertElement(Op0, Op1, Op2); 2403 Constant *Op2 = ValueList.getConstantFwdRef(Record[2], ShufTy); local 2404 V = ConstantExpr::getShuffleVector(Op0, Op1, Op2); 2417 Constant *Op2 = ValueList.getConstantFwdRef(Record[3], ShufTy); local 2418 V = ConstantExpr::getShuffleVector(Op0, Op1, Op2);
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelDAGToDAG.cpp | 2749 Op2 = N->getOperand(SVN->getMaskElt(1) < 2 ? 0 : 1); local 2761 std::swap(Op1, Op2); 2769 if (Op1 == Op2 && DM[0] == 0 && DM[1] == 0 && 2784 SDValue Ops[] = { Op1, Op2, DMV }; 3328 SDNode *Op2 = User->getOperand(2).getNode(); 3329 if (!Op2->isMachineOpcode()) 3332 if (Op2->getMachineOpcode() != PPC::LI && 3333 Op2->getMachineOpcode() != PPC::LI8) 3336 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op2->getOperand(0));
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/external/llvm/lib/CodeGen/ |
H A D | RegisterCoalescer.cpp | 656 unsigned Op1, Op2, NewDstIdx; local 657 if (!TII->findCommutedOpIndices(DefMI, Op1, Op2)) 660 NewDstIdx = Op2; 661 else if (Op2 == UseOpIdx)
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/external/llvm/lib/Transforms/InstCombine/ |
H A D | InstCombineCompares.cpp | 3121 Value *Op1 = nullptr, *Op2 = nullptr; local 3128 Op2 = ConstantExpr::getICmp(I.getPredicate(), C, RHSC); 3129 CI = dyn_cast<ConstantInt>(Op2); 3140 if (Op1 && Op2) 3142 else if (Op1 || Op2) { 3149 // Otherwise Op2 is constant and try replacing select with first 3158 if (!Op2) 3159 Op2 = Builder->CreateICmp(I.getPredicate(), LHSI->getOperand(2), 3161 return SelectInst::Create(LHSI->getOperand(0), Op1, Op2);
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H A D | InstructionCombining.cpp | 1347 GetElementPtrInst *Op2 = dyn_cast<GetElementPtrInst>(*I); local 1348 if (!Op2 || Op1->getNumOperands() != Op2->getNumOperands()) 1352 if (Op2 == &GEP) 1359 if (Op1->getOperand(J)->getType() != Op2->getOperand(J)->getType()) 1362 if (Op1->getOperand(J) != Op2->getOperand(J)) {
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/external/llvm/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 5878 ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[Idx + 1]); local 5881 // Adjust only if Op1 and Op2 are GPRs. 5882 if (Op1.isReg() && Op2.isReg() && MRC.contains(Op1.getReg()) && 5883 MRC.contains(Op2.getReg())) { 5885 unsigned Reg2 = Op2.getReg(); 5891 Error(Op2.getStartLoc(), isLoad 5899 ARMOperand::CreateReg(NewReg, Op1.getStartLoc(), Op2.getEndLoc()); 5939 ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[2]); local 5941 if (Op2.isReg() && Op3.isReg() && Op2 5948 ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[2]); local [all...] |
/external/llvm/lib/Target/Mips/ |
H A D | MipsSEISelLowering.cpp | 1014 SDValue Op2 = N->getOperand(2); local 1018 if (Op1 == Op0Op0 && Op2 == Op0Op1) 1020 Ty, Op1, Op2); 1021 else if (Op1 == Op0Op1 && Op2 == Op0Op0) 1023 Ty, Op1, Op2);
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/external/llvm/lib/Transforms/Vectorize/ |
H A D | LoopVectorize.cpp | 5053 Value *Op2 = I->getOperand(1); local 5056 if (isa<ConstantInt>(Op2)) { 5057 ConstantInt *CInt = cast<ConstantInt>(Op2); 5061 } else if (isa<ConstantVector>(Op2) || isa<ConstantDataVector>(Op2)) { 5063 Constant *SplatValue = cast<Constant>(Op2)->getSplatValue();
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/external/pdfium/core/src/fxcodec/lcms2/lcms2-2.6/src/ |
H A D | cmsopt.c | 139 cmsBool _Remove2Op(cmsPipeline* Lut, cmsStageSignature Op1, cmsStageSignature Op2) argument 153 if ((*pt1) ->Implements == Op1 && (*pt2) ->Implements == Op2) {
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/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.cpp | 1807 SDValue Op2 = Op->getOperand(2); local 1813 Op2 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op2); 1814 SDValue Select = DAG.getNode(ISD::SELECT, DL, MVT::i32, Op0, Op1, Op2);
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/external/llvm/lib/Target/AArch64/AsmParser/ |
H A D | AArch64AsmParser.cpp | 3619 AArch64Operand &Op2 = static_cast<AArch64Operand &>(*Operands[2]); local 3621 if (Op2.isReg() && Op3.isImm()) { 3628 Op2.getReg())) {
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/external/llvm/lib/Target/X86/ |
H A D | X86ISelDAGToDAG.cpp | 2824 SDValue Op0, Op1, Op2, Op3, Op4; local 2830 if (!SelectAddr(nullptr, Op, Op0, Op1, Op2, Op3, Op4)) 2837 OutOps.push_back(Op2);
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H A D | X86ISelLowering.cpp | 13411 SDValue Op2 = Op.getOperand(2); local 13431 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2); 13451 !isa<ConstantFPSDNode>(Op1) && !isa<ConstantFPSDNode>(Op2)) { 13458 SDValue VOp2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op2); 13469 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2); 13492 if ((isAllOnes(Op1) || isAllOnes(Op2)) && 13494 SDValue Y = isAllOnes(Op2) ? Op1 : Op2; 13524 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2); 13626 (isAllOnes(Op1) || isAllOnes(Op2)) [all...] |
/external/llvm/include/llvm/Target/ |
H A D | TargetLowering.h | 2667 SDValue BuildExactSDIV(SDValue Op1, SDValue Op2, SDLoc dl,
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/external/llvm/lib/IR/ |
H A D | Instructions.cpp | 62 const char *SelectInst::areInvalidOperands(Value *Op0, Value *Op1, Value *Op2) { argument 63 if (Op1->getType() != Op2->getType())
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.cpp | 1045 SDValue Op1 = Op.getOperand(1), Op2 = Op.getOperand(2); local 1051 SDValue X2 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v2i32, Op2);
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