Searched refs:reg (Results 26 - 50 of 148) sorted by relevance

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/art/runtime/
H A Dquick_exception_handler.cc195 static VRegKind GetVRegKind(uint16_t reg, const std::vector<int32_t>& kinds) { argument
196 return static_cast<VRegKind>(kinds.at(reg * 2));
224 for (uint16_t reg = 0; reg < num_regs; ++reg) {
225 VRegKind kind = GetVRegKind(reg, kinds);
228 new_frame->SetVReg(reg, kDeadValue);
231 new_frame->SetVReg(reg, kinds.at((reg * 2) + 1));
238 if (GetVReg(m, reg, kin
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H A Dcheck_reference_map_visitor.h75 int reg = registers[i]; local
76 CHECK(reg < m->GetCodeItem()->registers_size_);
78 dex_register_map.GetDexRegisterLocation(reg, number_of_dex_registers, code_info);
112 int reg = registers[i]; local
113 CHECK(reg < m->GetCodeItem()->registers_size_);
114 CHECK((*((ref_bitmap) + reg / 8) >> (reg % 8) ) & 0x01)
/art/compiler/dex/
H A Dreg_storage.h100 static const uint16_t kHighRegNumMask = 0x001f; // 0..31 for high reg
108 constexpr RegStorage(RegStorageKind rs_kind, int reg) argument
112 kValid | rs_kind | (reg & kRegTypeMask)) {
120 << "High reg must be in 0..31: " << high_reg, false)
127 // We do not provide a general operator overload for equality of reg storage, as this is
184 static constexpr bool IsFloat(uint16_t reg) { argument
185 return ((reg & kFloatingPoint) == kFloatingPoint);
188 static constexpr bool IsDouble(uint16_t reg) { argument
189 return (reg & (kFloatingPoint | k64BitMask)) == (kFloatingPoint | k64Bits);
192 static constexpr bool IsSingle(uint16_t reg) { argument
196 Is32Bit(uint16_t reg) argument
200 Is64Bit(uint16_t reg) argument
204 Is64BitSolo(uint16_t reg) argument
215 SetReg(int reg) argument
222 SetLowReg(int reg) argument
251 SetHighReg(int reg) argument
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H A Dreg_location.h53 RegStorage reg; // Encoded physical registers. member in struct:art::RegLocation
/art/disassembler/
H A Ddisassembler_arm64.cc44 const vixl::CPURegister& reg) {
46 if (reg.IsRegister() && reg.Is64Bits()) {
47 if (reg.code() == TR) {
50 } else if (reg.code() == LR) {
57 Disassembler::AppendRegisterNameToOutput(instr, reg);
42 AppendRegisterNameToOutput( const vixl::Instruction* instr, const vixl::CPURegister& reg) argument
/art/compiler/utils/mips64/
H A Dmanaged_register_mips64.cc44 std::ostream& operator<<(std::ostream& os, const Mips64ManagedRegister& reg) { argument
45 reg.Print(os);
/art/compiler/utils/x86/
H A Dmanaged_register_x86.cc41 RegisterPair reg; // Used to verify that the enum is in sync. member in struct:art::x86::RegisterPairDescriptor
53 std::ostream& operator<<(std::ostream& os, const RegisterPair& reg) { argument
54 if (reg == kNoRegisterPair) {
57 os << X86ManagedRegister::FromRegisterPair(reg);
84 CHECK_EQ(r, kRegisterPairs[r].reg);
93 CHECK_EQ(r, kRegisterPairs[r].reg);
114 std::ostream& operator<<(std::ostream& os, const X86ManagedRegister& reg) { argument
115 reg.Print(os);
H A Dmanaged_register_x86.h46 std::ostream& operator<<(std::ostream& os, const RegisterPair& reg);
208 X86ManagedRegister reg(reg_id);
209 CHECK(reg.IsValidManagedRegister());
210 return reg;
214 std::ostream& operator<<(std::ostream& os, const X86ManagedRegister& reg);
219 x86::X86ManagedRegister reg(id_);
220 CHECK(reg.IsNoRegister() || reg.IsValidManagedRegister());
221 return reg;
/art/runtime/arch/x86/
H A Dasm_support_x86.S84 #define CFI_DEF_CFA(reg,size) .cfi_def_cfa reg,size
85 #define CFI_DEF_CFA_REGISTER(reg) .cfi_def_cfa_register reg
86 #define CFI_RESTORE(reg) .cfi_restore reg
87 #define CFI_REL_OFFSET(reg,size) .cfi_rel_offset reg,size
95 #define CFI_DEF_CFA(reg,size)
96 #define CFI_DEF_CFA_REGISTER(reg)
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H A Dcontext_x86.cc76 void X86Context::SetGPR(uint32_t reg, uintptr_t value) { argument
77 CHECK_LT(reg, static_cast<uint32_t>(kNumberOfCpuRegisters));
78 DCHECK(IsAccessibleGPR(reg));
79 CHECK_NE(gprs_[reg], &gZero);
80 *gprs_[reg] = value;
83 void X86Context::SetFPR(uint32_t reg, uintptr_t value) { argument
84 CHECK_LT(reg, static_cast<uint32_t>(kNumberOfFloatRegisters));
85 DCHECK(IsAccessibleFPR(reg));
86 CHECK_NE(fprs_[reg], reinterpret_cast<const uint32_t*>(&gZero));
87 *fprs_[reg]
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/art/runtime/arch/arm64/
H A Dcontext_arm64.cc60 void Arm64Context::SetGPR(uint32_t reg, uintptr_t value) { argument
61 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfXRegisters));
62 DCHECK_NE(reg, static_cast<uint32_t>(XZR));
63 DCHECK(IsAccessibleGPR(reg));
64 DCHECK_NE(gprs_[reg], &gZero); // Can't overwrite this static value since they are never reset.
65 *gprs_[reg] = value;
68 void Arm64Context::SetFPR(uint32_t reg, uintptr_t value) { argument
69 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfDRegisters));
70 DCHECK(IsAccessibleFPR(reg));
71 DCHECK_NE(fprs_[reg],
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/art/compiler/dex/quick/arm64/
H A Dint_arm64.cc64 OpRegReg(kOpCmp, rl_src1.reg, rl_src2.reg);
65 NewLIR4(kA64Csinc4rrrc, rl_result.reg.GetReg(), rwzr, rwzr, kArmCondEq);
66 NewLIR4(kA64Csneg4rrrc, rl_result.reg.GetReg(), rl_result.reg.GetReg(),
67 rl_result.reg.GetReg(), kArmCondGe);
93 OpRegRegReg(op, rl_result.reg, rl_src1.reg, As64BitReg(rl_shift.reg));
196 OpRegImm(kOpCmp, rl_src.reg,
268 OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target) argument
940 OpPcRelLoad(RegStorage reg, LIR* target) argument
1025 OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) argument
1423 ExtractReg(uint32_t reg_mask, int* reg) argument
1450 int reg = *reg1 + first_bit_set; local
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/art/compiler/utils/x86_64/
H A Dmanaged_register_x86_64.cc40 RegisterPair reg; // Used to verify that the enum is in sync. member in struct:art::x86_64::RegisterPairDescriptor
52 std::ostream& operator<<(std::ostream& os, const RegisterPair& reg) { argument
53 os << X86_64ManagedRegister::FromRegisterPair(reg);
79 CHECK_EQ(r, kRegisterPairs[r].reg);
88 CHECK_EQ(r, kRegisterPairs[r].reg);
109 std::ostream& operator<<(std::ostream& os, const X86_64ManagedRegister& reg) { argument
110 reg.Print(os);
H A Dmanaged_register_x86_64.h45 std::ostream& operator<<(std::ostream& os, const RegisterPair& reg);
194 X86_64ManagedRegister reg(reg_id);
195 CHECK(reg.IsValidManagedRegister());
196 return reg;
200 std::ostream& operator<<(std::ostream& os, const X86_64ManagedRegister& reg);
205 x86_64::X86_64ManagedRegister reg(id_);
206 CHECK(reg.IsNoRegister() || reg.IsValidManagedRegister());
207 return reg;
H A Dassembler_x86_64.h95 bool IsRegister(CpuRegister reg) const {
97 && ((encoding_[0] & 0x07) == reg.LowBits()) // Register codes match.
98 && (reg.NeedsRex() == ((rex_ & 1) != 0)); // REX.000B bits match.
154 explicit Operand(CpuRegister reg) : rex_(0), length_(0), fixup_(nullptr) { SetModRM(3, reg); } argument
313 void call(CpuRegister reg);
317 void pushq(CpuRegister reg);
321 void popq(CpuRegister reg);
473 void xchgl(CpuRegister reg, const Address& address);
477 void cmpl(CpuRegister reg, cons
615 LockCmpxchgl(const Address& address, CpuRegister reg) argument
619 LockCmpxchgq(const Address& address, CpuRegister reg) argument
837 EmitRegisterOperand(uint8_t rm, uint8_t reg) argument
843 EmitXmmRegisterOperand(uint8_t rm, XmmRegister reg) argument
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/art/runtime/arch/arm/
H A Dcontext_arm.cc60 void ArmContext::SetGPR(uint32_t reg, uintptr_t value) { argument
61 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCoreRegisters));
62 DCHECK(IsAccessibleGPR(reg));
63 DCHECK_NE(gprs_[reg], &gZero); // Can't overwrite this static value since they are never reset.
64 *gprs_[reg] = value;
67 void ArmContext::SetFPR(uint32_t reg, uintptr_t value) { argument
68 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfSRegisters));
69 DCHECK(IsAccessibleFPR(reg));
70 DCHECK_NE(fprs_[reg], &gZero); // Can't overwrite this static value since they are never reset.
71 *fprs_[reg]
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/art/runtime/arch/mips64/
H A Dcontext_mips64.cc58 void Mips64Context::SetGPR(uint32_t reg, uintptr_t value) { argument
59 CHECK_LT(reg, static_cast<uint32_t>(kNumberOfGpuRegisters));
60 DCHECK(IsAccessibleGPR(reg));
61 CHECK_NE(gprs_[reg], &gZero); // Can't overwrite this static value since they are never reset.
62 *gprs_[reg] = value;
65 void Mips64Context::SetFPR(uint32_t reg, uintptr_t value) { argument
66 CHECK_LT(reg, static_cast<uint32_t>(kNumberOfFpuRegisters));
67 DCHECK(IsAccessibleFPR(reg));
68 CHECK_NE(fprs_[reg], &gZero); // Can't overwrite this static value since they are never reset.
69 *fprs_[reg]
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/art/runtime/arch/x86_64/
H A Dcontext_x86_64.cc89 void X86_64Context::SetGPR(uint32_t reg, uintptr_t value) { argument
90 CHECK_LT(reg, static_cast<uint32_t>(kNumberOfCpuRegisters));
91 DCHECK(IsAccessibleGPR(reg));
92 CHECK_NE(gprs_[reg], &gZero);
93 *gprs_[reg] = value;
96 void X86_64Context::SetFPR(uint32_t reg, uintptr_t value) { argument
97 CHECK_LT(reg, static_cast<uint32_t>(kNumberOfFloatRegisters));
98 DCHECK(IsAccessibleFPR(reg));
99 CHECK_NE(fprs_[reg], reinterpret_cast<const uint64_t*>(&gZero));
100 *fprs_[reg]
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/art/compiler/utils/mips/
H A Dmanaged_register_mips.h45 std::ostream& operator<<(std::ostream& os, const RegisterPair& reg);
211 MipsManagedRegister reg(reg_id);
212 CHECK(reg.IsValidManagedRegister());
213 return reg;
217 std::ostream& operator<<(std::ostream& os, const MipsManagedRegister& reg);
222 mips::MipsManagedRegister reg(id_);
223 CHECK(reg.IsNoRegister() || reg.IsValidManagedRegister());
224 return reg;
H A Dmanaged_register_mips.cc92 std::ostream& operator<<(std::ostream& os, const MipsManagedRegister& reg) { argument
93 reg.Print(os);
97 std::ostream& operator<<(std::ostream& os, const RegisterPair& reg) { argument
98 os << MipsManagedRegister::FromRegisterPair(reg);
/art/compiler/dex/quick/mips/
H A Dfp_mips.cc68 NewLIR3(op, rl_result.reg.GetReg(), rl_src1.reg.GetReg(), rl_src2.reg.GetReg());
114 NewLIR3(op, rl_result.reg.GetReg(), rl_src1.reg.GetReg(), rl_src2.reg.GetReg());
176 NewLIR2(op, rl_result.reg.GetReg(), rl_src.reg.GetReg());
184 // Get the reg storage for a wide FP. Is either a solo or a pair. Base is Mips-counted, e.g., even
267 NewLIR2(kMipsFnegs, rl_result.reg
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/art/compiler/dex/quick/
H A Dgen_common.cc191 void Mir2Lir::GenDivZeroCheck(RegStorage reg) { argument
192 LIR* branch = OpCmpImmBranch(kCondEq, reg, 0, nullptr);
269 LIR* Mir2Lir::GenNullCheck(RegStorage reg) { argument
284 LIR* branch = OpCmpImmBranch(kCondEq, reg, 0, nullptr);
334 void Mir2Lir::ForceImplicitNullCheck(RegStorage reg, int opt_flags) { argument
343 LIR* load = Load32Disp(reg, 0, tmp);
394 OpCmpImmBranch(cond, rl_src1.reg, mir_graph_->ConstantValue(rl_src2), taken);
404 OpCmpImmBranch(cond, rl_src1.reg, 0, taken);
410 OpCmpBranch(cond, rl_src1.reg, rl_src2.reg, take
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H A Dgen_invoke.cc254 // For Mips, when the 1st arg is integral, then remaining arg are passed in core reg.
261 // For Mips, when the 1st arg is integral, then remaining arg are passed in core reg.
271 // For Mips, when the 1st arg is integral, then remaining arg are passed in core reg.
278 // For Mips, when the 1st arg is integral, then remaining arg are passed in core reg.
407 rl_src.reg = TargetReg(kArg0, kRef);
418 StoreBaseDisp(TargetPtrReg(kSp), 0, rl_src.reg, kWord, kNotVolatile);
442 // get reg corresponding to input
443 RegStorage reg = in_to_reg_storage_mapping_.GetReg(i); local
448 if (t_loc->wide && reg.Valid() && !reg
469 StoreRefDisp(TargetPtrReg(kSp), offset, reg, kNotVolatile); local
471 StoreBaseDisp(TargetPtrReg(kSp), offset, reg, t_loc->wide ? k64 : k32, kNotVolatile); local
678 GenImplicitNullCheck(RegStorage reg, int opt_flags) argument
798 RegStorage reg = in_to_reg_storage_mapping.GetReg(i); local
841 RegStorage reg = in_to_reg_storage_mapping.GetReg(i); local
851 LoadBaseDisp(TargetPtrReg(kSp), out_offset, reg, k32, kNotVolatile); local
855 LoadBaseDisp(TargetPtrReg(kSp), SRegOffset(rl_arg.s_reg_low + 1), reg, k32, local
857 StoreBaseDisp(TargetPtrReg(kSp), high_offset, reg, k32, kNotVolatile); local
859 LoadBaseDisp(TargetPtrReg(kSp), SRegOffset(rl_arg.s_reg_low), reg, k32, kNotVolatile); local
862 StoreBaseDisp(TargetPtrReg(kSp), low_offset, reg, k32, kNotVolatile); local
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H A Dmir_to_lir-inl.h145 inline void Mir2Lir::SetupRegMask(ResourceMask* mask, int reg) { argument
146 DCHECK_EQ((reg & ~RegStorage::kRegValMask), 0);
147 DCHECK_LT(static_cast<size_t>(reg), reginfo_map_.size());
148 DCHECK(reginfo_map_[reg] != nullptr) << "No info for 0x" << reg;
149 *mask = mask->Union(reginfo_map_[reg]->DefUseMask());
155 inline void Mir2Lir::ClearRegMask(ResourceMask* mask, int reg) { argument
156 DCHECK_EQ((reg & ~RegStorage::kRegValMask), 0);
157 DCHECK_LT(static_cast<size_t>(reg), reginfo_map_.size());
158 DCHECK(reginfo_map_[reg] !
262 GetRegInfo(RegStorage reg) argument
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/art/compiler/utils/arm64/
H A Dmanaged_register_arm64.h208 Arm64ManagedRegister reg(reg_id);
209 CHECK(reg.IsValidManagedRegister());
210 return reg;
214 std::ostream& operator<<(std::ostream& os, const Arm64ManagedRegister& reg);
219 arm64::Arm64ManagedRegister reg(id_);
220 CHECK(reg.IsNoRegister() || reg.IsValidManagedRegister());
221 return reg;

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