Searched refs:OpInfo (Results 1 - 25 of 43) sorted by relevance

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/external/llvm/lib/MC/
H A DMCInstrAnalysis.cpp16 Info->get(Inst.getOpcode()).OpInfo[0].OperandType != MCOI::OPERAND_PCREL)
/external/mesa3d/src/gallium/drivers/nv50/codegen/
H A Dnv50_ir_target.h139 struct OpInfo struct in class:nv50_ir::Target
141 OpInfo *variants;
161 inline const OpInfo& getOpInfo(const Instruction *) const;
162 inline const OpInfo& getOpInfo(const operation) const;
210 OpInfo opInfo[OP_LAST + 1];
213 const Target::OpInfo& Target::getOpInfo(const Instruction *insn) const
218 const Target::OpInfo& Target::getOpInfo(const operation op) const
/external/llvm/include/llvm/Bitcode/
H A DBitCodes.h179 void Add(const BitCodeAbbrevOp &OpInfo) { argument
180 OperandList.push_back(OpInfo);
/external/llvm/utils/TableGen/
H A DAsmWriterInst.cpp174 CGIOperandList::OperandInfo OpInfo = CGI.Operands[OpNo]; local
176 unsigned MIOp = OpInfo.MIOperandNo;
177 Operands.push_back(AsmWriterOperand(OpInfo.PrinterMethodName,
H A DAsmMatcherEmitter.cpp1573 const CGIOperandList::OperandInfo &OpInfo = ResultInst->Operands[i]; local
1577 if (OpInfo.MINumOperands == 1)
1578 TiedOp = OpInfo.getTiedRegister();
1585 int SrcOperand = findAsmOperandNamed(OpInfo.Name);
1586 if (OpInfo.Name.empty() || SrcOperand == -1) {
1597 unsigned NumOperands = OpInfo.MINumOperands;
1606 AsmOperands[SrcOperand+AI].SrcOpName == OpInfo.Name &&
1622 const CGIOperandList::OperandInfo *OpInfo = &ResultInst->Operands[i]; local
1626 if (OpInfo->MINumOperands == 1)
1627 TiedOp = OpInfo
[all...]
H A DFixedLenDecoderEmitter.cpp451 const OperandInfo &OpInfo) const;
1036 const OperandInfo &OpInfo) const {
1037 const std::string &Decoder = OpInfo.Decoder;
1039 if (OpInfo.numFields() != 1)
1042 for (const EncodingField &EF : OpInfo) {
1044 if (OpInfo.numFields() != 1) o << '|';
1047 if (OpInfo.numFields() != 1 || EF.Offset != 0)
1838 OperandInfo OpInfo(Decoder);
1839 OpInfo.addField(bitStart, bitWidth, 0);
1841 NumberedInsnOperands[Name].push_back(OpInfo);
[all...]
H A DInstrInfoEmitter.cpp58 const OperandInfoMapTy &OpInfo,
467 const OperandInfoMapTy &OpInfo,
547 OS << "OperandInfo" << OpInfo.find(OperandInfo)->second;
464 emitRecord(const CodeGenInstruction &Inst, unsigned Num, Record *InstrInfo, std::map<std::vector<Record*>, unsigned> &EmittedLists, const OperandInfoMapTy &OpInfo, raw_ostream &OS) argument
/external/llvm/include/llvm/MC/
H A DMCInstrDesc.h152 const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands member in class:llvm::MCInstrDesc
163 (OpInfo[OpNum].Constraints & (1 << Constraint))) {
165 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
637 if (OpInfo[i].isPredicate())
/external/llvm/lib/Target/R600/
H A DSIInstrInfo.h255 const MCOperandInfo &OpInfo = get(Opcode).OpInfo[OpNo]; local
257 if (OpInfo.RegClass == -1) {
259 assert(OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE);
263 return RI.getRegClass(OpInfo.RegClass)->getSize();
H A DSIInstrInfo.cpp1185 const MCOperandInfo &OpInfo = get(MI->getOpcode()).OpInfo[OpNo];
1189 if (OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE)
1192 if (OpInfo.RegClass < 0)
1195 unsigned OpSize = RI.getRegClass(OpInfo.RegClass)->getSize();
1197 return RI.opCanUseLiteralConstant(OpInfo.OperandType);
1199 return RI.opCanUseInlineConstant(OpInfo.OperandType);
1280 int RegClass = Desc.OpInfo[i].RegClass;
1282 switch (Desc.OpInfo[i].OperandType) {
1441 Desc.OpInfo[OpN
[all...]
H A DSIFoldOperands.cpp258 UseDesc.OpInfo[Use.getOperandNo()].RegClass == -1)
/external/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp2275 AsmOperandInfo &OpInfo = ConstraintOperands.back(); local
2278 if (OpInfo.multipleAlternatives.size() > maCount)
2279 maCount = OpInfo.multipleAlternatives.size();
2281 OpInfo.ConstraintVT = MVT::Other;
2284 switch (OpInfo.Type) {
2287 if (OpInfo.isIndirect) {
2288 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2297 OpInfo.ConstraintVT = getSimpleValueType(STy->getElementType(ResNo));
2300 OpInfo.ConstraintVT = getSimpleValueType(CS.getType());
2305 OpInfo
2366 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex]; local
2414 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex]; local
2556 ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo, const TargetLowering &TLI, SDValue Op, SelectionDAG *DAG) argument
2607 ComputeConstraintToUse(AsmOperandInfo &OpInfo, SDValue Op, SelectionDAG *DAG) const argument
[all...]
H A DSelectionDAGBuilder.cpp6185 /// OpInfo describes the operand.
6190 SDISelAsmOperandInfo &OpInfo) {
6200 OpInfo.ConstraintCode,
6201 OpInfo.ConstraintVT);
6204 if (OpInfo.ConstraintVT != MVT::Other) {
6208 if (OpInfo.Type == InlineAsm::isInput &&
6209 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
6214 if (RegVT.getSizeInBits() == OpInfo.CallOperand.getValueSizeInBits()) {
6215 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6216 RegVT, OpInfo
[all...]
/external/llvm/lib/Target/R600/MCTargetDesc/
H A DSIMCCodeEmitter.cpp81 unsigned OpType = Desc.OpInfo[OpNo].OperandType;
204 int RCID = Desc.OpInfo[i].RegClass;
276 int RCID = Desc.OpInfo[OpNo].RegClass;
/external/clang/lib/CodeGen/
H A DCGExprComplex.cpp826 BinOpInfo OpInfo; local
831 OpInfo.Ty = E->getComputationResultType();
832 QualType ComplexElementTy = cast<ComplexType>(OpInfo.Ty)->getElementType();
839 OpInfo.RHS = ComplexPairTy(CGF.EmitScalarExpr(E->getRHS()), nullptr);
842 .hasSameUnqualifiedType(OpInfo.Ty, E->getRHS()->getType()));
843 OpInfo.RHS = Visit(E->getRHS());
851 OpInfo.LHS = EmitComplexToComplexCast(LHSVal, LHSTy, OpInfo.Ty);
859 OpInfo.LHS = ComplexPairTy(LHSVal, nullptr);
861 OpInfo
[all...]
H A DCGExprScalar.cpp2106 BinOpInfo OpInfo; local
2113 OpInfo.RHS = Visit(E->getRHS());
2114 OpInfo.Ty = E->getComputationResultType();
2115 OpInfo.Opcode = E->getOpcode();
2116 OpInfo.FPContractable = false;
2117 OpInfo.E = E;
2130 switch (OpInfo.Opcode) {
2156 llvm::Value *amt = CGF.EmitToMemory(EmitScalarConversion(OpInfo.RHS,
2167 OpInfo.LHS = EmitLoadOfLValue(LHSLV, E->getExprLoc());
2168 OpInfo
[all...]
/external/llvm/lib/Analysis/
H A DCostModel.cpp125 TargetTransformInfo::OperandValueKind OpInfo = local
130 OpInfo = TargetTransformInfo::OK_NonUniformConstantValue;
132 OpInfo = TargetTransformInfo::OK_UniformConstantValue;
135 return OpInfo;
/external/llvm/lib/Target/AArch64/
H A DAArch64DeadRegisterDefinitionsPass.cpp99 switch (MI.getDesc().OpInfo[i].RegClass) {
/external/lldb/source/Plugins/Disassembler/llvm/
H A DDisassemblerLLVMC.h118 int OpInfo(uint64_t PC,
H A DDisassemblerLLVMC.cpp769 return static_cast<DisassemblerLLVMC*>(disassembler)->OpInfo (pc,
788 int DisassemblerLLVMC::OpInfo (uint64_t PC, function in class:DisassemblerLLVMC
/external/llvm/lib/Target/ARM/
H A DThumb2SizeReduction.cpp728 if (i < NumOps && MCID.OpInfo[i].isOptionalDef())
730 if (SkipPred && MCID.OpInfo[i].isPredicate())
764 if (MCID.OpInfo[i].isPredicate())
774 !MCID.OpInfo[i].isPredicate()) {
824 if (i < NumOps && MCID.OpInfo[i].isOptionalDef())
834 bool isPred = (i < NumOps && MCID.OpInfo[i].isPredicate());
/external/llvm/lib/Target/R600/InstPrinter/
H A DAMDGPUInstPrinter.cpp306 int RCID = Desc.OpInfo[OpNo].RegClass;
315 } else if (Desc.OpInfo[OpNo].OperandType == MCOI::OPERAND_IMMEDIATE) {
329 const MCRegisterClass &ImmRC = MRI.getRegClass(Desc.OpInfo[OpNo].RegClass);
/external/llvm/lib/CodeGen/
H A DTargetSchedule.cpp212 && !DefMI->getDesc().OpInfo[DefOperIdx].isOptionalDef()
H A DTargetInstrInfo.cpp49 short RegClass = MCID.OpInfo[OpNum].RegClass;
50 if (MCID.OpInfo[OpNum].isLookupPtrRegClass())
227 if (MCID.OpInfo[i].isPredicate()) {
/external/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCTargetDesc.cpp368 if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType!=MCOI::OPERAND_PCREL)

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