| /art/compiler/dex/quick/arm/ |
| H A D | int_arm.cc | 50 LIR* ArmMir2Lir::OpIT(ConditionCode ccode, const char* guide) { argument
55 ArmConditionCode code = ArmConditionEncoding(ccode);
167 int64_t val, ConditionCode ccode) {
178 if (val == 0 && (ccode == kCondEq || ccode == kCondNe)) {
182 OpCondBranch(ccode, taken);
186 switch (ccode) {
189 OpCmpImmBranch(kCondNe, high_reg, val_hi, (ccode == kCondEq) ? not_taken : taken);
194 ccode = kCondUlt;
199 ccode
166 GenFusedLongCmpImmBranch(BasicBlock* bb, RegLocation rl_src1, int64_t val, ConditionCode ccode) argument
251 ConditionCode ccode = mir->meta.ccode; local
322 ConditionCode ccode = mir->meta.ccode; local
[all...] |
| H A D | fp_arm.cc | 264 ConditionCode ccode = mir->meta.ccode; local
265 switch (ccode) {
271 ccode = kCondMi;
276 ccode = kCondLs;
281 ccode = kCondHi;
286 ccode = kCondUge;
290 LOG(FATAL) << "Unexpected ccode: " << ccode;
292 OpCondBranch(ccode, targe
[all...] |
| H A D | target_arm.cc | 243 ArmConditionCode ArmMir2Lir::ArmConditionEncoding(ConditionCode ccode) { argument
245 switch (ccode) {
265 LOG(FATAL) << "Bad condition code " << ccode;
|
| H A D | codegen_arm.h | 285 ConditionCode ccode);
|
| /art/compiler/dex/quick/arm64/ |
| H A D | fp_arm64.cc | 247 ConditionCode ccode = mir->meta.ccode; local
248 switch (ccode) {
254 ccode = kCondMi;
259 ccode = kCondLs;
264 ccode = kCondHi;
269 ccode = kCondUge;
273 LOG(FATAL) << "Unexpected ccode: " << ccode;
275 OpCondBranch(ccode, targe
[all...] |
| H A D | int_arm64.cc | 40 LIR* Arm64Mir2Lir::OpIT(ConditionCode ccode, const char* guide) { argument
41 UNUSED(ccode, guide);
99 void Arm64Mir2Lir::GenSelect(int32_t true_val, int32_t false_val, ConditionCode ccode, argument
105 ccode = NegateComparison(ccode);
109 ArmConditionCode code = ArmConditionEncoding(ccode);
203 GenSelect(mir->dalvikInsn.vB, mir->dalvikInsn.vC, mir->meta.ccode, rl_result.reg,
218 rl_true.reg.GetReg(), rl_false.reg.GetReg(), ArmConditionEncoding(mir->meta.ccode));
229 ConditionCode ccode = mir->meta.ccode; local
[all...] |
| H A D | target_arm64.cc | 190 ArmConditionCode Arm64Mir2Lir::ArmConditionEncoding(ConditionCode ccode) { argument
192 switch (ccode) {
212 LOG(FATAL) << "Bad condition code " << ccode;
|
| /art/compiler/dex/quick/x86/ |
| H A D | fp_x86.cc | 532 ConditionCode ccode = mir->meta.ccode; local
533 switch (ccode) {
551 ccode = kCondUlt;
558 ccode = kCondLs;
565 ccode = kCondHi;
572 ccode = kCondUge;
575 LOG(FATAL) << "Unexpected ccode: " << ccode;
577 OpCondBranch(ccode, take
[all...] |
| H A D | int_x86.cc | 281 ConditionCode ccode = mir->meta.ccode; local
300 * For ccode == kCondEq:
339 ConditionCode cc = true_zero_case ? NegateComparison(ccode) : ccode;
358 * For ccode == kCondEq:
376 OpCondRegReg(kOpCmov, NegateComparison(ccode), rl_result.reg, rl_false.reg);
378 OpCondRegReg(kOpCmov, ccode, rl_result.reg, rl_true.reg);
381 OpCondRegReg(kOpCmov, ccode, rl_result.reg, rl_true.reg);
392 ConditionCode ccode local
451 GenFusedLongCmpImmBranch(BasicBlock* bb, RegLocation rl_src1, int64_t val, ConditionCode ccode) argument
[all...] |
| H A D | codegen_x86.h | 498 int64_t val, ConditionCode ccode);
|
| /art/compiler/dex/ |
| H A D | mir_optimization.cc | 237 static_assert(ConditionCodeForIfCcZ(Instruction::IF_EQZ) == kCondEq, "if_eqz ccode");
238 static_assert(ConditionCodeForIfCcZ(Instruction::IF_NEZ) == kCondNe, "if_nez ccode");
239 static_assert(ConditionCodeForIfCcZ(Instruction::IF_LTZ) == kCondLt, "if_ltz ccode");
240 static_assert(ConditionCodeForIfCcZ(Instruction::IF_GEZ) == kCondGe, "if_gez ccode");
241 static_assert(ConditionCodeForIfCcZ(Instruction::IF_GTZ) == kCondGt, "if_gtz ccode");
242 static_assert(ConditionCodeForIfCcZ(Instruction::IF_LEZ) == kCondLe, "if_lez ccode");
553 mir_next->meta.ccode = ConditionCodeForIfCcZ(mir_next->dalvikInsn.opcode);
646 mir->meta.ccode = ConditionCodeForIfCcZ(mir->dalvikInsn.opcode);
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| H A D | mir_graph.h | 344 ConditionCode ccode; member in union:art::MIR::__anon8
|