Searched refs:count (Results 1 - 25 of 144) sorted by path

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/art/cmdline/detail/
H A Dcmdline_parse_argument_detail.h155 size_t local_blank_count = std::count(s.begin(), s.end(), '_');
156 size_t local_token_count = std::count(s.begin(), s.end(), ' ');
/art/compiler/dex/
H A Dglobal_value_numbering_test.cc140 void DoPrepareIFields(const IFieldDef* defs, size_t count) { argument
142 cu_.mir_graph->ifield_lowering_infos_.reserve(count);
143 for (size_t i = 0u; i != count; ++i) {
155 template <size_t count>
156 void PrepareIFields(const IFieldDef (&defs)[count]) {
157 DoPrepareIFields(defs, count);
160 void DoPrepareSFields(const SFieldDef* defs, size_t count) { argument
162 cu_.mir_graph->sfield_lowering_infos_.reserve(count);
163 for (size_t i = 0u; i != count; ++i) {
178 template <size_t count>
183 DoPrepareBasicBlocks(const BBDef* defs, size_t count) argument
230 DoPrepareMIRs(const MIRDef* defs, size_t count) argument
279 DoPrepareVregToSsaMapExit(BasicBlockId bb_id, const int32_t* map, size_t count) argument
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H A Dgvn_dead_code_elimination.cc314 int count = old_data->wide_def ? 2 : 1; local
315 for (int v_reg = old_data->vreg_def, end = old_data->vreg_def + count; v_reg != end; ++v_reg) {
332 int count = data->wide_def ? 2 : 1; local
333 for (int v_reg = data->vreg_def, end = data->vreg_def + count; v_reg != end; ++v_reg) {
865 for (size_t i = 0, count = vreg_chains_.NumMIRs() - change; i != count; ++i) {
987 int count = data->wide_def ? 2 : 1; local
988 for (int v_reg = data->vreg_def, end = data->vreg_def + count; v_reg != end; ++v_reg) {
H A Dgvn_dead_code_elimination_test.cc143 void DoPrepareIFields(const IFieldDef* defs, size_t count) { argument
145 cu_.mir_graph->ifield_lowering_infos_.reserve(count);
146 for (size_t i = 0u; i != count; ++i) {
160 template <size_t count>
161 void PrepareIFields(const IFieldDef (&defs)[count]) {
162 DoPrepareIFields(defs, count);
165 void DoPrepareSFields(const SFieldDef* defs, size_t count) { argument
167 cu_.mir_graph->sfield_lowering_infos_.reserve(count);
168 for (size_t i = 0u; i != count; ++i) {
185 template <size_t count>
190 DoPrepareBasicBlocks(const BBDef* defs, size_t count) argument
258 DoPrepareMIRs(const MIRDef* defs, size_t count) argument
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H A Dlocal_value_numbering.cc243 } else if (it->second.store_loc_set.count(location) != 0u) {
262 if (values->store_loc_set.count(location) != 0u) {
515 if (lvn != least_entries_lvn && (lvn->*set_ptr).count(key) == 0u) {
645 if (lvn->non_aliasing_refs_.count(entry) == 0u &&
646 lvn->escaped_refs_.count(entry) == 0u) {
659 if (entry.field_id == kNoValue && escaped_refs_.count(entry.base) != 0u) {
669 escaped_refs_.count(entry.base) != 0u) {
676 if (escaped_refs_.count(entry.base) != 0u) {
1061 if (escaped_refs_.count(reg) == 0u) {
1117 if (gvn_->CanModify() && null_checked_.count(bas
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H A Dlocal_value_numbering.h109 DCHECK_EQ(map->count(s_reg), 0u);
126 DCHECK_EQ(sreg_wide_value_map_.count(s_reg), 0u);
132 DCHECK_EQ(sreg_wide_value_map_.count(s_reg), 0u);
138 DCHECK_EQ(sreg_value_map_.count(s_reg), 0u);
145 DCHECK_EQ(sreg_value_map_.count(s_reg), 0u);
H A Dlocal_value_numbering_test.cc94 void DoPrepareIFields(const IFieldDef* defs, size_t count) { argument
96 cu_.mir_graph->ifield_lowering_infos_.reserve(count);
97 for (size_t i = 0u; i != count; ++i) {
109 template <size_t count>
110 void PrepareIFields(const IFieldDef (&defs)[count]) {
111 DoPrepareIFields(defs, count);
114 void DoPrepareSFields(const SFieldDef* defs, size_t count) { argument
116 cu_.mir_graph->sfield_lowering_infos_.reserve(count);
117 for (size_t i = 0u; i != count; ++i) {
132 template <size_t count>
137 DoPrepareMIRs(const MIRDef* defs, size_t count) argument
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H A Dmir_analysis.cc1044 float count = stats->dex_instructions; local
1045 stats->math_ratio = stats->math_ops / count;
1046 stats->fp_ratio = stats->fp_ops / count;
1047 stats->branch_ratio = stats->branch_ops / count;
1048 stats->array_ratio = stats->array_ops / count;
1049 stats->heavyweight_ratio = stats->heavyweight_ops / count;
1408 const size_t count = invoke_map.size(); local
1409 method_lowering_infos_.reserve(count);
1410 for (size_t pos = 0u; pos != count; ++pos) {
1425 method_lowering_infos_.data(), count);
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H A Dmir_field_info.cc34 MirIFieldLoweringInfo* field_infos, size_t count) {
37 DCHECK_NE(count, 0u);
38 for (auto it = field_infos, end = field_infos + count; it != end; ++it) {
57 for (auto it = field_infos, end = field_infos + count; it != end; ++it) {
97 MirSFieldLoweringInfo* field_infos, size_t count) {
100 DCHECK_NE(count, 0u);
101 for (auto it = field_infos, end = field_infos + count; it != end; ++it) {
122 for (auto it = field_infos, end = field_infos + count; it != end; ++it) {
32 Resolve(CompilerDriver* compiler_driver, const DexCompilationUnit* mUnit, MirIFieldLoweringInfo* field_infos, size_t count) argument
95 Resolve(CompilerDriver* compiler_driver, const DexCompilationUnit* mUnit, MirSFieldLoweringInfo* field_infos, size_t count) argument
H A Dmir_field_info.h137 MirIFieldLoweringInfo* field_infos, size_t count)
194 MirSFieldLoweringInfo* field_infos, size_t count)
H A Dmir_graph.cc1838 // Even if the code item is null, we still count non-zero value so that
1847 // If the current code item was not counted yet, count it now.
2363 DCHECK_EQ(mir_graph->catches_.count(start_offset), 1u);
H A Dmir_graph.h533 size_t num_arg_words; // Note: word count, not arg count.
747 void DumpRegLocTable(RegLocation* table, int count);
1213 * @brief Get use count weight for a given block.
H A Dmir_graph_test.cc60 void DoPrepareBasicBlocks(const BBDef* defs, size_t count) { argument
63 ASSERT_LT(3u, count); // null, entry, exit and at least one bytecode block.
67 for (size_t i = 0u; i != count; ++i) {
94 ASSERT_EQ(count, cu_.mir_graph->block_list_.size());
105 template <size_t count>
106 void PrepareBasicBlocks(const BBDef (&defs)[count]) {
107 DoPrepareBasicBlocks(defs, count);
127 void DoCheckOrder(const BasicBlockId* ids, size_t count) { argument
128 ASSERT_EQ(count, cu_.mir_graph->GetTopologicalSortOrder().size());
129 for (size_t i = 0; i != count;
139 DoCheckLoopEnds(const uint16_t* ends, size_t count) argument
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H A Dmir_method_info.cc36 MirMethodLoweringInfo* method_infos, size_t count) {
39 DCHECK_NE(count, 0u);
40 for (auto it = method_infos, end = method_infos + count; it != end; ++it) {
74 for (auto it = method_infos, end = method_infos + count; it != end; ++it) {
34 Resolve(CompilerDriver* compiler_driver, const DexCompilationUnit* mUnit, MirMethodLoweringInfo* method_infos, size_t count) argument
H A Dmir_method_info.h101 MirMethodLoweringInfo* method_infos, size_t count)
H A Dmir_optimization_test.cc99 void DoPrepareBasicBlocks(const BBDef* defs, size_t count) { argument
102 ASSERT_LT(3u, count); // null, entry, exit and at least one bytecode block.
106 for (size_t i = 0u; i != count; ++i) {
133 ASSERT_EQ(count, cu_.mir_graph->block_list_.size());
140 template <size_t count>
141 void PrepareBasicBlocks(const BBDef (&defs)[count]) {
142 DoPrepareBasicBlocks(defs, count);
252 void DoPrepareMethods(const MethodDef* defs, size_t count) { argument
254 cu_.mir_graph->method_lowering_infos_.reserve(count);
255 for (size_t i = 0u; i != count;
281 DoPrepareMIRs(const MIRDef* defs, size_t count) argument
355 DoPrepareSFields(const SFieldDef* defs, size_t count) argument
405 DoPrepareIFields(const IFieldDef* defs, size_t count) argument
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/art/compiler/dex/quick/arm/
H A Dcodegen_arm.h219 LIR* OpVldm(RegStorage r_base, int count);
220 LIR* OpVstm(RegStorage r_base, int count);
345 int GenDalvikArgsBulkCopy(CallInfo* info, int first, int count) OVERRIDE;
H A Dint_arm.cc1127 LIR* ArmMir2Lir::OpVldm(RegStorage r_base, int count) { argument
1128 return NewLIR3(kThumb2Vldms, r_base.GetReg(), rs_fr0.GetReg(), count);
1131 LIR* ArmMir2Lir::OpVstm(RegStorage r_base, int count) { argument
1132 return NewLIR3(kThumb2Vstms, r_base.GetReg(), rs_fr0.GetReg(), count);
H A Dtarget_arm.cc321 static char* DecodeFPCSRegList(int count, int base, char* buf, size_t buf_size) { argument
323 for (int i = 1; i < count; i++) {
979 int ArmMir2Lir::GenDalvikArgsBulkCopy(CallInfo* info, int first, int count) { argument
981 return Mir2Lir::GenDalvikArgsBulkCopy(info, first, count);
987 return count;
H A Dutility_arm.cc413 LOG(FATAL) << "Unexpected encoding operand count";
1280 if (core_counts[p_map_idx].count == 1) {
1281 core_counts[p_map_idx].count = 0;
1283 core_counts[p_map_idx].count *= 3;
/art/compiler/dex/quick/arm64/
H A Dcodegen_arm64.h222 LIR* OpVldm(RegStorage r_base, int count) OVERRIDE;
223 LIR* OpVstm(RegStorage r_base, int count) OVERRIDE;
411 int GenDalvikArgsBulkCopy(CallInfo* info, int first, int count) OVERRIDE;
H A Dint_arm64.cc966 LIR* Arm64Mir2Lir::OpVldm(RegStorage r_base, int count) { argument
967 UNUSED(r_base, count);
972 LIR* Arm64Mir2Lir::OpVstm(RegStorage r_base, int count) { argument
973 UNUSED(r_base, count);
1678 // instruction-count wise than the complicated code below.
H A Dtarget_arm64.cc877 int Arm64Mir2Lir::GenDalvikArgsBulkCopy(CallInfo* /*info*/, int /*first*/, int count) { argument
882 return count;
/art/compiler/dex/quick/
H A Dgen_invoke.cc733 * @param count the number of remaining arguments we can handle.
737 int Mir2Lir::GenDalvikArgsBulkCopy(CallInfo* info, int first, int count) { argument
738 // call is pretty expensive, let's use it if count is big.
739 if (count > 16) {
747 count * 4, false);
748 count = 0;
750 return count;
992 // Location of count
/art/compiler/dex/quick/mips/
H A Dcodegen_mips.h216 LIR* OpVldm(RegStorage r_base, int count);
217 LIR* OpVstm(RegStorage r_base, int count);

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