| 681652d8e8a33bc07c5c082a71aea13d0f15e0a0 |
|
23-Jul-2015 |
Mingyao Yang <mingyao@google.com> |
HDeoptimize should hold values live in env.
Values that are not live in compiled code anymore may still be needed in
interpreter, due to code motion, etc.
(cherry-picked from commit 718493c6c3c8e380663cb8a94e57ce160a6c473f)
Bug: 22665511
Change-Id: I8b85833c5c462f8fe36f86d6026a51b07563995a
|
| 0a23d74dc2751440822960eab218be4cb8843647 |
|
07-May-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Add a parent environment to HEnvironment.
This code has no functionality change. It adds a placeholder
for chaining inlined frames.
Change-Id: I5ec57335af76ee406052345b947aad98a6a4423a
|
| db216f4d49ea1561a74261c29f1264952232728a |
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05-May-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Relax the only one back-edge restriction.
The rule is in the way for better register allocation, as
it creates an artificial join point between multiple paths.
Change-Id: Ia4392890f95bcea56d143138f28ddce6c572ad58
|
| fbda5f3e1378f07ae202f62da625ee43a063a052 |
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29-Apr-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Find better split positions in the register allocator.
In a standard if/else control flow graph, this avoids
doing a move in one branch if the other branch decided
to move an interval.
This also needs a new register hint kind, which is what
was the location of the interval at the predecessor block.
Change-Id: I18b78264587b4d693540fbb5e014d12df2add3e2
|
| 579026039080252878106118645ed70706f4838e |
|
21-Apr-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Add synthesize uses at back edge.
This reduces the cost of linearizing the graph (hence removing
the notion of back edge). Since linear scan allocates/spills registers
based on next use, adding a use at a back edge ensures we do count
for loop uses.
Change-Id: Idaa882cb120edbdd08ca6bff142d326a8245bd14
|
| 4ed947a58de87d19d0609be773207c905ccb0f7f |
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27-Apr-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Dissociate uses with environment uses.
They are most of the times in the way when iterating. They
also complicate the logic of (future) back edge uses.
Change-Id: I152595d9913073fe901b267ca623fa0fe7432484
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| 241a486267bdb59b32fe4c8db370eb936068fb39 |
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16-Apr-2015 |
David Brazdil <dbrazdil@google.com> |
ART: Replace expensive calls to Covers in reg alloc
LiveInterval::Covers is implemented as a linear-time search over
liveness ranges and can therefore be rather expensive and should be
avoided unless necessary. This patch replaces calls to Covers when
searching for a sibling with the cheaper IsDefinedAt call.
Change-Id: I93fc73529c15a518335f4cbdc3a0def52d9501e5
|
| 0d9f17de8f21a10702de1510b73e89d07b3b9bbf |
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15-Apr-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Move the linear order to the HGraph.
Bug found by Zheng Xu: SsaLivenessAnalysis being a stack allocated
object, we should not refer to it in later phases of the compiler.
Specifically, the code generator was using the linear order, which
was stored in the liveness analysis object.
Change-Id: I574641f522b7b86fc43f3914166108efc72edb3b
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| d8126bef62df7f40f2e6abc74004f52e664daf45 |
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27-Mar-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Fix locations at environment uses.
We were too agressive in not recording environment uses
when the instruction was not of type object. We have to
record the use to the use list of an interval, but it should
not affect the live ranges of that interval.
Change-Id: Id16fb7cc06f14083766d408a345837793583b6ea
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| f01d34445953e6b9c9b13de1dd32a5c0ee5abab5 |
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27-Mar-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Implement a proper solution for temps.
We used to play some trickery when updating locations of temps. This
change creates a proper use of the temp, and use it for updating
its location.
Change-Id: I53e9447b87a55137a3a79841db21ad3864854825
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| 46e2a3915aa68c77426b71e95b9f3658250646b7 |
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16-Mar-2015 |
David Brazdil <dbrazdil@google.com> |
ART: Boolean simplifier
The optimization recognizes the negation pattern generated by 'javac'
and replaces it with a single condition. To this end, boolean values
are now consistently assumed to be represented by an integer.
This is a first optimization which deletes blocks from the HGraph and
does so by replacing the corresponding entries with null. Hence,
existing code can continue indexing the list of blocks with the block
ID, but must check for null when iterating over the list.
Change-Id: I7779da69cfa925c6521938ad0bcc11bc52335583
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| 915b9d0c13bb5091875d868fbfa551d7b65d7477 |
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11-Mar-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Tweak liveness when instructions are used in environments.
Instructions remain live when debuggable, but only instructions
with object types remain live when non-debuggable.
Enable StackVisitor::GetThisObject for optimizing.
Change-Id: Id87b2cbf33a02450059acc9993995782e5f28987
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| 5b8e6a594b827f7dc88b2e3d895e08f5b3f22446 |
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25-Feb-2015 |
David Brazdil <dbrazdil@google.com> |
ART: Cache last returned range in LiveInterval::Covers
Optimizing spends ~10% of compilation time in the register allocator.
One of the frequently called methods is LiveInterval::Covers which
has linear complexity w.r.t. the number of gaps in liveness intervals.
This patch leverages the fact that the register allocator calls Covers
with non-decreasing position values and caches the last returned
result to start the iteration closer to the result the next time the
method is invoked. Stats from compiling the framework show that this
optimization reduces the average number of iterations needed to find
the result by 40%.
Change-Id: I4dd26b900879d5e1d03818ebc1e117cc6a53053c
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| da02afe615191a19eae9a039786c4c4fc20dbfff |
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11-Feb-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Support hints for register pairs.
Change-Id: Ia49dc5bf3e9a2bd481425bfe7fbeea9feb66c8e6
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| c0572a451944f78397619dec34a38c36c11e9d2a |
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06-Feb-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Optimize leaf methods.
Avoid suspend checks and stack changes when not needed.
Change-Id: I0fdb31e8c631e99091b818874a558c9aa04b1628
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| ed59619b370ef23ffbb25d1d01f615e60a9262b6 |
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23-Jan-2015 |
David Brazdil <dbrazdil@google.com> |
Optimizing: Speed up HEnvironment use removal
Removal of use records from HEnvironment vregs involved iterating over
potentially large linked lists which made compilation of huge methods
very slow. This patch turns use lists into doubly-linked lists, stores
pointers to the relevant nodes inside HEnvironment and subsequently
turns the removals into constant-time operations.
Change-Id: I0e1d4d782fd624e7b8075af75d4adf0a0634a1ee
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| 840e5461a85f8908f51e7f6cd562a9129ff0e7ce |
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07-Jan-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Implement double and float support for arm in register allocator.
The basic approach is:
- An instruction that needs two registers gets two intervals.
- When allocating the low part, we also allocate the high part.
- When splitting a low (or high) interval, we also split the high
(or low) equivalent.
- Allocation follows the (S/D register) requirement that low
registers are always even and the high equivalent is low + 1.
Change-Id: I06a5148e05a2ffc7e7555d08e871ed007b4c2797
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| a8eed3acbc39c71ec22dc2943e71eaa07c6507dd |
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24-Nov-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Revert "Revert "Fix the computation of linear ordering.""
PS2 fixes the obvious typos/wrong refactoring.
This reverts commit e50fa5887b1342b845826197d81950e26753fc9c.
Change-Id: I22f81d63a12cf01aafd61535abc2399d936d49c2
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| e50fa5887b1342b845826197d81950e26753fc9c |
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24-Nov-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Revert "Fix the computation of linear ordering."
Build is broken.
This reverts commit 3054a90063d379ab8c9e5a42a7daf0d644b48b07.
Change-Id: I259bc2bd6a58e30391b8176f3db5fdb5c07e4d6d
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| 3054a90063d379ab8c9e5a42a7daf0d644b48b07 |
|
21-Nov-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Fix the computation of linear ordering.
The register allocator makes assumptions on the order, and
we ended up not computing the right one. The algorithm worked
fine when the loop header is the block branching to the exit,
but in the presence of breaks or do/while, it was incorrect.
Change-Id: Iad0a89872cd3f7b7a8b2bdf560f0d03493f93ba5
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| 277ccbd200ea43590dfc06a93ae184a765327ad0 |
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04-Nov-2014 |
Andreas Gampe <agampe@google.com> |
ART: More warnings
Enable -Wno-conversion-null, -Wredundant-decls and -Wshadow in general,
and -Wunused-but-set-parameter for GCC builds.
Change-Id: I81bbdd762213444673c65d85edae594a523836e5
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| 296bd60423e0630d8152b99fb7afb20fbff5a18a |
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07-Oct-2014 |
Mingyao Yang <mingyao@google.com> |
Some improvement to reg alloc.
Change-Id: If579a37791278500a7e5bc763f144c241f261920
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| 102cbed1e52b7c5f09458b44903fe97bb3e14d5f |
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15-Oct-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Implement register allocator for floating point registers.
Also:
- Fix misuses of emitting the rex prefix in the x86_64 assembler.
- Fix movaps code generation in the x86_64 assembler.
Change-Id: Ib6dcf6e7c4a9c43368cfc46b02ba50f69ae69cbe
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| 56b9ee6fe1d6880c5fca0e7feb28b25a1ded2e2f |
|
09-Oct-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Stop converting from Location to ManagedRegister.
Now the source of truth is the Location object that knows
which register (core, pair, fpu) it needs to refer to.
Change-Id: I62401343d7479ecfb24b5ed161ec7829cda5a0b1
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| 01ef345767ea609417fc511e42007705c9667546 |
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01-Oct-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Add trivial register hints to the register allocator.
- Add hints for phis, same as first input, and expected registers.
- Make the if instruction accept non-condition instructions.
Change-Id: I34fa68393f0d0c19c68128f017b7a05be556fbe5
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| 8ddb00ca935733f5d3b07816e5bb33d6cabe6ec4 |
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29-Sep-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Improve detection of lifetime holes.
The check concluding that the next use was in a successor
was too conservative: two blocks following each other
in terms of liveness are not necessarily predecessor/sucessor.
Change-Id: Ideec98046c812aa5fb63781141b5fde24c706d6d
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| 8a16d97fb8f031822b206e65f9109a071da40563 |
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11-Sep-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Fix valgrind errors.
For now just stack allocate the code generator. Will think
about cleaning up the root problem later (CodeGenerator being an
arena object).
Change-Id: I161a6f61c5f27ea88851b446f3c1e12ee9c594d7
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| e77493c7217efdd1a0ecef521a6845a13da0305b |
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21-Aug-2014 |
Ian Rogers <irogers@google.com> |
Make common BitVector operations inline-able.
Change-Id: Ie25de4fae56c6712539f04172c42e3eff57df7ca
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| e50383288a75244255d3ecedcc79ffe9caf774cb |
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04-Jul-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Support fields in optimizing compiler.
- Required support for temporaries, to be only used by baseline compiler.
- Also fixed a few invalid assumptions around locations and instructions
that don't need materialization. These instructions should not have an Out.
Change-Id: Idc4a30dd95dd18015137300d36bec55fc024cf62
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| 31d76b42ef5165351499da3f8ee0ac147428c5ed |
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09-Jun-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Plug code generator into liveness analysis.
Also implement spill slot support.
Change-Id: If5e28811e9fbbf3842a258772c633318a2f4fafc
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| ec7e4727e99aa1416398ac5a684f5024817a25c7 |
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06-Jun-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Fix some bugs in graph construction/simplification methods.
Also fix a brano during SSA construction. The code should
not have been commented out. Added a test to cover what the code
intends.
Change-Id: Ia00ae79dcf75eb0d412f07649d73e7f94dbfb6f0
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| ffddfdf6fec0b9d98a692e27242eecb15af5ead2 |
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03-Jun-2014 |
Tim Murray <timmurray@google.com> |
DO NOT MERGE
Merge ART from AOSP to lmp-preview-dev.
Change-Id: I0f578733a4b8756fd780d4a052ad69b746f687a9
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| a7062e05e6048c7f817d784a5b94e3122e25b1ec |
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22-May-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Add a linear scan register allocator to the optimizing compiler.
This is a "by-the-book" implementation. It currently only deals
with allocating registers, with no hint optimizations.
The changes remaining to make it functional are:
- Allocate spill slots.
- Resolution and placements of Move instructions.
- Connect it to the code generator.
Change-Id: Ie0b2f6ba1b98da85425be721ce4afecd6b4012a4
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| a5b8fde2d2bc3167078694fad417fddfe442a6fd |
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23-May-2014 |
Vladimir Marko <vmarko@google.com> |
Rewrite BitVector index iterator.
The BitVector::Iterator was not iterating over the bits but
rather over indexes of the set bits. Therefore, we rename it
to IndexIterator and provide a BitVector::Indexes() to get
a container-style interface with begin() and end() for range
based for loops.
Also, simplify InsertPhiNodes where the tmp_blocks isn't
needed since the phi_nodes and input_blocks cannot lose any
blocks in subsequent iterations, so we can do the Union()
directly in those bit vectors and we need to repeat the loop
only if we have new input_blocks, rather than on phi_nodes
change. And move the temporary bit vectors to scoped arena.
Change-Id: I6cb87a2f60724eeef67c6aaa34b36ed5acde6d43
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| ddb311fdeca82ca628fed694c4702f463b5c4927 |
|
16-May-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Build live ranges in preparation for register allocation.
Change-Id: I7ae24afaa4e49276136bf34f4ba7d62db7f28c01
|
| 0d3f578909d0d1ea072ca68d78301b6fb7a44451 |
|
14-May-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Linearize the graph before creating live ranges.
Change-Id: I02eb5671e3304ab062286131745c1366448aff58
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| f635e63318447ca04731b265a86a573c9ed1737c |
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14-May-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Add a compilation tracing mechanism to the new compiler.
Code mostly imported from: https://android-review.googlesource.com/#/c/81653/.
Change-Id: I150fe942be0fb270e03fabb19032180f7a065d13
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| 622d9c31febd950255b36a48b47e1f630197c5fe |
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12-May-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Add loop recognition and CFG simplifications in new compiler.
We do three simplifications:
- Split critical edges, for code generation from SSA (new).
- Ensure one back edge per loop, to simplify loop recognition (new).
- Ensure only one pre header for a loop, to simplify SSA creation (existing).
Change-Id: I9bfccd4b236a00486a261078627b091c8a68be33
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| 804d09372cc3d80d537da1489da4a45e0e19aa5d |
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02-May-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Build live-in, live-out and kill sets for each block.
This information will be used when computing live ranges of
instructions.
Change-Id: I345ee833c1ccb4a8e725c7976453f6d58d350d74
|