/external/clang/test/Parser/ |
H A D | cxx-using-declaration.cpp | 4 int VA; member in namespace:A 9 using A::VA; 15 VA = 1;
|
/external/clang/test/Preprocessor/ |
H A D | macro_paste_bad.c | 32 #define VA __VA_ ## ARGS__ macro 33 int VA; // expected-warning {{__VA_ARGS__ can only appear in the expansion of a C99 variadic macro}} variable
|
/external/skia/src/sfnt/ |
H A D | SkOTTable_OS_2.h | 31 struct VA : SkOTTableOS2_VA { } vA; struct in union:SkOTTableOS2::Version 45 SK_COMPILE_ASSERT(sizeof(SkOTTableOS2::Version::VA) == 68, sizeof_SkOTTableOS2__VA_not_68);
|
/external/clang/test/CXX/special/class.dtor/ |
H A D | p3-0x.cpp | 140 struct VA { struct 142 virtual ~VA() {} 145 struct VB : VA 149 struct TVB : VA
|
/external/llvm/lib/Target/BPF/ |
H A D | BPFISelLowering.cpp | 210 for (auto &VA : ArgLocs) { 211 if (VA.isRegLoc()) { 213 EVT RegVT = VA.getLocVT(); 222 RegInfo.addLiveIn(VA.getLocReg(), VReg); 228 if (VA.getLocInfo() == CCValAssign::SExt) 230 DAG.getValueType(VA.getValVT())); 231 else if (VA.getLocInfo() == CCValAssign::ZExt) 233 DAG.getValueType(VA.getValVT())); 235 if (VA.getLocInfo() != CCValAssign::Full) 236 ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA 312 CCValAssign &VA = ArgLocs[i]; local 415 CCValAssign &VA = RVLocs[i]; local [all...] |
/external/llvm/tools/llvm-readobj/ |
H A D | ARMWinEHPrinter.cpp | 187 Decoder::getSectionContaining(const COFFObjectFile &COFF, uint64_t VA) { argument 192 if (VA >= Address && (VA - Address) <= Size) 199 uint64_t VA, bool FunctionOnly) { 212 if (Address == VA) 518 uint64_t FunctionAddress, uint64_t VA) { 524 uint64_t Offset = VA - SectionVA; 198 getSymbol(const COFFObjectFile &COFF, uint64_t VA, bool FunctionOnly) argument
|
/external/mksh/src/ |
H A D | shf.c | 774 #define VA(type) va_arg(args, type) macro 823 tmp = VA(int); 884 lnum = (long)VA(ssize_t); 886 lnum = VA(long); 888 lnum = (long)(short)VA(int); 890 lnum = (long)VA(int); 897 lnum = VA(size_t); 899 lnum = VA(unsigned long); 901 lnum = (unsigned long)(unsigned short)VA(int); 903 lnum = (unsigned long)VA(unsigne [all...] |
/external/llvm/lib/Transforms/InstCombine/ |
H A D | InstCombinePHI.cpp | 876 Value *VA = PN.getIncomingValue(i); local 882 PN.setIncomingValue(j, VA);
|
/external/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelLowering.cpp | 454 CCValAssign &VA = ArgLocs[i]; local 455 if (VA.isRegLoc()) { 457 EVT RegVT = VA.getLocVT(); 469 RegInfo.addLiveIn(VA.getLocReg(), VReg); 475 if (VA.getLocInfo() == CCValAssign::SExt) 477 DAG.getValueType(VA.getValVT())); 478 else if (VA.getLocInfo() == CCValAssign::ZExt) 480 DAG.getValueType(VA.getValVT())); 482 if (VA.getLocInfo() != CCValAssign::Full) 483 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA 550 CCValAssign &VA = RVLocs[i]; local 606 CCValAssign &VA = ArgLocs[i]; local [all...] |
/external/llvm/lib/Target/Mips/ |
H A D | MipsFastISel.cpp | 960 CCValAssign &VA = ArgLocs[i]; local 961 const Value *ArgVal = CLI.OutVals[VA.getValNo()]; 962 MVT ArgVT = OutVTs[VA.getValNo()]; 967 VA.convertToReg(Mips::F12); 969 VA.convertToReg(Mips::D6); 974 VA.convertToReg(Mips::F14); 976 VA.convertToReg(Mips::D7); 980 if (((ArgVT == MVT::i32) || (ArgVT == MVT::f32)) && VA.isMemLoc()) { 981 switch (VA.getLocMemOffset()) { 983 VA [all...] |
H A D | MipsISelLowering.cpp | 2593 CCValAssign &VA = ArgLocs[i]; local 2594 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT(); 2611 VA); 2617 switch (VA.getLocInfo()) { 2621 if (VA.isRegLoc()) { 2633 unsigned LocRegLo = VA.getLocReg(); 2666 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 2668 ISD::SHL, DL, VA.getLocVT(), Arg, 2669 DAG.getConstant(LocSizeInBits - ValSizeInBits, VA 2782 CCValAssign &VA = RVLocs[i]; local 2832 UnpackFromArgumentSlot(SDValue Val, const CCValAssign &VA, EVT ArgVT, SDLoc DL, SelectionDAG &DAG) argument 2924 CCValAssign &VA = ArgLocs[i]; local 3087 CCValAssign &VA = RVLocs[i]; local 3567 copyByValRegs( SDValue Chain, SDLoc DL, std::vector<SDValue> &OutChains, SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags, SmallVectorImpl<SDValue> &InVals, const Argument *FuncArg, unsigned FirstReg, unsigned LastReg, const CCValAssign &VA, MipsCCState &State) const argument [all...] |
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCFastISel.cpp | 1261 CCValAssign &VA = ArgLocs[I]; local 1262 MVT ArgVT = ArgVTs[VA.getValNo()]; 1267 !VA.isRegLoc() || VA.needsCustom()) 1271 if (VA.getLocInfo() == CCValAssign::BCvt) 1299 CCValAssign &VA = ArgLocs[I]; local 1300 unsigned Arg = ArgRegs[VA.getValNo()]; 1301 MVT ArgVT = ArgVTs[VA.getValNo()]; 1304 switch (VA.getLocInfo()) { 1310 MVT DestVT = VA 1373 CCValAssign &VA = RVLocs[0]; local 1597 CCValAssign &VA = ValLocs[0]; local 1617 CCValAssign &VA = ValLocs[i]; local [all...] |
H A D | PPCISelLowering.cpp | 2655 CCValAssign &VA = ArgLocs[i]; local 2658 if (VA.isRegLoc()) { 2660 EVT ValVT = VA.getValVT(); 2699 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 2709 assert(VA.isMemLoc()); 2711 unsigned ArgSize = VA.getLocVT().getStoreSize(); 2712 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(), 2717 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, 4106 CCValAssign &VA = RVLocs[i]; local 4107 assert(VA 4401 CCValAssign &VA = ArgLocs[i]; local 5555 CCValAssign &VA = RVLocs[i]; local [all...] |
/external/llvm/lib/Target/R600/ |
H A D | R600ISelLowering.cpp | 1661 CCValAssign &VA = ArgLocs[i]; local 1664 EVT MemVT = VA.getLocVT(); 1671 unsigned Reg = MF.addLiveIn(VA.getLocReg(), &AMDGPU::R600_Reg128RegClass); 1701 unsigned PartOffset = VA.getLocMemOffset(); 1702 unsigned Offset = 36 + VA.getLocMemOffset();
|
H A D | SIISelLowering.cpp | 513 CCValAssign &VA = ArgLocs[ArgIdx++]; local 514 MVT VT = VA.getLocVT(); 516 if (VA.isMemLoc()) { 519 const unsigned Offset = 36 + VA.getLocMemOffset(); 540 assert(VA.isRegLoc() && "Parameter must be in a register!"); 542 unsigned Reg = VA.getLocReg();
|
/external/llvm/lib/Target/XCore/ |
H A D | XCoreISelLowering.cpp | 1078 const CCValAssign &VA = RVLocs[i]; local 1079 if (VA.isRegLoc()) { 1080 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getValVT(), 1085 assert(VA.isMemLoc()); 1086 ResultMemLocs.push_back(std::make_pair(VA.getLocMemOffset(), 1156 CCValAssign &VA = ArgLocs[i]; local 1160 switch (VA.getLocInfo()) { 1164 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 1167 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA 1321 CCValAssign &VA = ArgLocs[i]; local 1495 CCValAssign &VA = RVLocs[i]; local 1523 CCValAssign &VA = RVLocs[i]; local [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | ARMFastISel.cpp | 1895 CCValAssign &VA = ArgLocs[i]; local 1896 MVT ArgVT = ArgVTs[VA.getValNo()]; 1903 if (VA.isRegLoc() && !VA.needsCustom()) { 1905 } else if (VA.needsCustom()) { 1907 if (VA.getLocVT() != MVT::f64 || 1909 !VA.isRegLoc() || !ArgLocs[++i].isRegLoc()) 1945 CCValAssign &VA = ArgLocs[i]; local 1946 const Value *ArgVal = Args[VA.getValNo()]; 1947 unsigned Arg = ArgRegs[VA [all...] |
H A D | ARMISelLowering.cpp | 1345 CCValAssign VA = RVLocs[i]; local 1350 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i32 && 1357 if (VA.needsCustom()) { 1359 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, 1363 VA = RVLocs[++i]; // skip ahead to next loc 1364 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, 1372 if (VA.getLocVT() == MVT::v2f64) { 1377 VA = RVLocs[++i]; // skip ahead to next loc 1378 Lo = DAG.getCopyFromReg(Chain, dl, VA 1414 LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg, SDLoc dl, SelectionDAG &DAG, const CCValAssign &VA, ISD::ArgFlagsTy Flags) const argument 1427 PassF64ArgInRegs(SDLoc dl, SelectionDAG &DAG, SDValue Chain, SDValue &Arg, RegsToPassVector &RegsToPass, CCValAssign &VA, CCValAssign &NextVA, SDValue &StackPtr, SmallVectorImpl<SDValue> &MemOpChains, ISD::ArgFlagsTy Flags) const argument 1527 CCValAssign &VA = ArgLocs[i]; local 2097 CCValAssign &VA = ArgLocs[i]; local 2204 CCValAssign &VA = RVLocs[i]; local 2796 GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA, SDValue &Root, SelectionDAG &DAG, SDLoc dl) const argument 2957 CCValAssign &VA = ArgLocs[i]; local 2983 CCValAssign &VA = ArgLocs[i]; local [all...] |
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.cpp | 349 CCValAssign &VA = RVLocs[i]; local 351 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag); 355 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 461 CCValAssign &VA = ArgLocs[i]; local 462 if (VA.isMemLoc()) { 485 CCValAssign &VA = ArgLocs[i]; local 490 switch (VA.getLocInfo()) { 497 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 500 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA 871 CCValAssign &VA = ArgLocs[i]; local [all...] |
/external/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 206 CCValAssign &VA = RVLocs[i]; local 207 assert(VA.isRegLoc() && "Can only return in registers!"); 209 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), 214 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 268 CCValAssign &VA = RVLocs[i]; local 269 assert(VA.isRegLoc() && "Can only return in registers!"); 273 switch (VA.getLocInfo()) { 276 OutVal = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), OutVal); 279 OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA 360 CCValAssign &VA = ArgLocs[i]; local 560 CCValAssign &VA = ArgLocs[i]; local 748 CCValAssign &VA = ArgLocs[i]; local 1010 const CCValAssign &VA = ArgLocs[i]; local 1271 CCValAssign &VA = RVLocs[i]; local [all...] |
/external/llvm/lib/Target/X86/ |
H A D | X86FastISel.cpp | 1001 CCValAssign &VA = ValLocs[0]; 1004 if (VA.getLocInfo() != CCValAssign::Full) 1007 if (!VA.isRegLoc()) 1012 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) 1015 unsigned SrcReg = Reg + VA.getValNo(); 1017 EVT DstVT = VA.getValVT(); 1041 unsigned DstReg = VA.getLocReg(); 1050 RetRegs.push_back(VA.getLocReg()); 2915 CCValAssign const &VA local 3137 CCValAssign &VA = RVLocs[i]; local [all...] |
H A D | X86ISelLowering.cpp | 1893 CCValAssign &VA = RVLocs[i]; local 1894 assert(VA.isRegLoc() && "Can only return in registers!"); 1899 if (VA.getLocInfo() == CCValAssign::SExt) 1900 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy); 1901 else if (VA.getLocInfo() == CCValAssign::ZExt) 1902 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy); 1903 else if (VA.getLocInfo() == CCValAssign::AExt) 1904 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy); 1905 else if (VA.getLocInfo() == CCValAssign::BCvt) 1906 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA 2065 CCValAssign &VA = RVLocs[i]; local 2188 LowerMemArgument(SDValue Chain, CallingConv::ID CallConv, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, const CCValAssign &VA, MachineFrameInfo *MFI, unsigned i) const argument 2315 CCValAssign &VA = ArgLocs[i]; local 2624 LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg, SDLoc dl, SelectionDAG &DAG, const CCValAssign &VA, ISD::ArgFlagsTy Flags) const argument 2797 CCValAssign &VA = ArgLocs[i]; local 2935 CCValAssign &VA = ArgLocs[i]; local 3359 CCValAssign &VA = RVLocs[i]; local 3420 CCValAssign &VA = ArgLocs[i]; local 3449 CCValAssign &VA = ArgLocs[i]; local [all...] |
/external/llvm/lib/Target/AArch64/ |
H A D | AArch64FastISel.cpp | 2944 CCValAssign &VA = ArgLocs[i]; local 2945 const Value *ArgVal = CLI.OutVals[VA.getValNo()]; 2946 MVT ArgVT = OutVTs[VA.getValNo()]; 2953 switch (VA.getLocInfo()) { 2957 MVT DestVT = VA.getLocVT(); 2967 MVT DestVT = VA.getLocVT(); 2979 if (VA.isRegLoc() && !VA.needsCustom()) { 2981 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg); 2982 CLI.OutRegs.push_back(VA [all...] |
H A D | AArch64ISelLowering.cpp | 2096 CCValAssign &VA = ArgLocs[i]; local 2108 MFI->CreateFixedObject(8 * NumRegs, VA.getLocMemOffset(), false); 2115 if (VA.isRegLoc()) { 2117 EVT RegVT = VA.getLocVT(); 2138 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 2144 switch (VA.getLocInfo()) { 2150 ArgValue = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), ArgValue); 2163 } else { // VA.isRegLoc() 2164 assert(VA.isMemLoc() && "CCValAssign is neither reg nor mem"); 2165 unsigned ArgOffset = VA 2338 CCValAssign VA = RVLocs[i]; local 2671 CCValAssign &VA = ArgLocs[i]; local 2923 CCValAssign &VA = RVLocs[i]; local [all...] |
/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelLowering.cpp | 647 // Value is a value that has been passed to us in the location described by VA 648 // (and so has type VA.getLocVT()). Convert Value to VA.getValVT(), chaining 651 CCValAssign &VA, SDValue Chain, 655 if (VA.getLocInfo() == CCValAssign::SExt) 656 Value = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Value, 657 DAG.getValueType(VA.getValVT())); 658 else if (VA.getLocInfo() == CCValAssign::ZExt) 659 Value = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Value, 660 DAG.getValueType(VA 650 convertLocVTToValVT(SelectionDAG &DAG, SDLoc DL, CCValAssign &VA, SDValue Chain, SDValue Value) argument 675 convertValVTToLocVT(SelectionDAG &DAG, SDLoc DL, CCValAssign &VA, SDValue Value) argument 713 CCValAssign &VA = ArgLocs[I]; local 814 CCValAssign &VA = ArgLocs[I]; local 865 CCValAssign &VA = ArgLocs[I]; local 971 CCValAssign &VA = RetLocs[I]; local 1009 CCValAssign &VA = RetLocs[I]; local [all...] |