/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | AMDILNIDevice.cpp | 65 mHWBits.set(AMDGPUDeviceInfo::FMA);
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H A D | AMDILEvergreenDevice.cpp | 133 mHWBits.set(AMDGPUDeviceInfo::FMA); 147 mSWBits.set(AMDGPUDeviceInfo::FMA); 164 mSWBits.set(AMDGPUDeviceInfo::FMA);
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H A D | AMDILDeviceInfo.h | 46 FMA = 0xC, // Use HW FMA or SW FMA. enumerator in enum:llvm::AMDGPUDeviceInfo::Caps
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H A D | AMDIL7XXDevice.cpp | 104 mSWBits.set(AMDGPUDeviceInfo::FMA);
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/external/llvm/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 234 /// FMA - Perform a * b + c with no intermediate rounding step. 235 FMA, enumerator in enum:llvm::ISD::NodeType
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H A D | BasicTTIImpl.h | 617 ISD = ISD::FMA; 620 ISD = ISD::FMA; 653 // If we can't lower fmuladd into an FMA estimate the cost as a floating
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/external/llvm/test/tools/llvm-readobj/ARM/ |
H A D | attribute-2.s | 37 @CHECK-OBJ-NEXT: Description: NEONv2+FMA
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/external/llvm/lib/Target/R600/ |
H A D | SIISelLowering.cpp | 621 // free fneg'd operands. As long as we have fast FMA (controlled by 1137 SDValue Fma0 = DAG.getNode(ISD::FMA, SL, MVT::f64, NegDivScale0, Rcp, One); 1139 SDValue Fma1 = DAG.getNode(ISD::FMA, SL, MVT::f64, Rcp, Fma0, Rcp); 1141 SDValue Fma2 = DAG.getNode(ISD::FMA, SL, MVT::f64, NegDivScale0, Fma1, One); 1145 SDValue Fma3 = DAG.getNode(ISD::FMA, SL, MVT::f64, Fma1, Fma2, Fma1); 1148 SDValue Fma4 = DAG.getNode(ISD::FMA, SL, MVT::f64,
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H A D | AMDGPUISelLowering.cpp | 374 setOperationAction(ISD::FMA, VT, Expand); 2217 SDValue Fma = DAG.getNode(ISD::FMA, SL, MVT::f64, FloorMul, K1, Trunc);
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAGDumper.cpp | 190 case ISD::FMA: return "fma";
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H A D | DAGCombiner.cpp | 1351 case ISD::FMA: return visitFMA(N); 7090 if (N0.getOpcode() == ISD::FMA && 7101 if (N1->getOpcode() == ISD::FMA && 7334 // FADD -> FMA combines: 7337 (!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FMA, VT))) { 7340 // Don't form FMA if we are preferring FMAD. 7342 = performFaddFmulCombines(ISD::FMA, 7350 // to combine into FMA, arrange such nodes accordingly. 7357 return DAG.getNode(ISD::FMA, SDLoc(N), VT, 7369 return DAG.getNode(ISD::FMA, SDLo [all...] |
H A D | LegalizeVectorOps.cpp | 319 case ISD::FMA:
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H A D | LegalizeFloatTypes.cpp | 84 case ISD::FMA: R = SoftenFloatRes_FMA(N); break; 900 case ISD::FMA: ExpandFloatRes_FMA(N, Lo, Hi); break; 1761 case ISD::FMA: // FMA is same as FMAD
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H A D | LegalizeVectorTypes.cpp | 128 case ISD::FMA: 673 case ISD::FMA: 1817 case ISD::FMA:
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H A D | LegalizeDAG.cpp | 3407 case ISD::FMA: 4223 case ISD::FMA: {
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H A D | SelectionDAGBuilder.cpp | 5031 setValue(&I, DAG.getNode(ISD::FMA, sdl, 5041 setValue(&I, DAG.getNode(ISD::FMA, sdl,
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/external/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 1518 setOperationAction(ISD::FMA , MVT::f128, Expand); 1523 setOperationAction(ISD::FMA , MVT::f64, Expand); 1528 setOperationAction(ISD::FMA , MVT::f32, Expand);
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/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelLowering.cpp | 279 setOperationAction(ISD::FMA, MVT::f32, Legal); 280 setOperationAction(ISD::FMA, MVT::f64, Legal); 281 setOperationAction(ISD::FMA, MVT::f128, Expand);
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/external/llvm/lib/Target/Mips/ |
H A D | MipsSEISelLowering.cpp | 315 setOperationAction(ISD::FMA, Ty, Legal); 1859 return DAG.getNode(ISD::FMA, SDLoc(Op), Op->getValueType(0),
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H A D | MipsISelLowering.cpp | 351 setOperationAction(ISD::FMA, MVT::f32, Expand); 352 setOperationAction(ISD::FMA, MVT::f64, Expand);
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 167 setOperationAction(ISD::FMA , MVT::f64, Legal); 173 setOperationAction(ISD::FMA , MVT::f32, Legal); 512 setOperationAction(ISD::FMA, MVT::v4f32, Legal); 555 setOperationAction(ISD::FMA, MVT::v2f64, Legal); 1052 assert(VT.isFloatingPoint() && "Non-floating-point FMA?"); 6084 Value = DAG.getNode(ISD::FMA, dl, MVT::v4f64, Value, FPHalfs, FPHalfs); 7311 Value = DAG.getNode(ISD::FMA, dl, MVT::v4f64, Value, FPHalfs, FPHalfs); 7525 Value = DAG.getNode(ISD::FMA, dl, MVT::v4f64, Value, FPHalfs, FPHalfs);
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 167 setOperationAction(ISD::FMA, MVT::f128, Expand); 294 setOperationAction(ISD::FMA, MVT::f16, Promote); 341 setOperationAction(ISD::FMA, MVT::v4f16, Expand); 372 setOperationAction(ISD::FMA, MVT::v8f16, Expand); 527 setOperationAction(ISD::FMA, MVT::v1f64, Expand); 6565 /// Not profitable if I and it's user can form a FMA instruction 6585 isOperationLegalOrCustom(ISD::FMA, VT) &&
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/external/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 480 setOperationAction(ISD::FMA, MVT::v2f64, Expand); 548 // NEON only has FMA instructions as of VFP4. 550 setOperationAction(ISD::FMA, MVT::v2f32, Expand); 551 setOperationAction(ISD::FMA, MVT::v4f32, Expand); 596 setOperationAction(ISD::FMA, MVT::f64, Expand); 873 setOperationAction(ISD::FMA, MVT::f64, Expand); 874 setOperationAction(ISD::FMA, MVT::f32, Expand);
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/external/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 614 // We don't support FMA. 615 setOperationAction(ISD::FMA, MVT::f64, Expand); 616 setOperationAction(ISD::FMA, MVT::f32, Expand); 649 setOperationAction(ISD::FMA, MVT::f80, Expand); 693 setOperationAction(ISD::FMA, VT, Expand); 1108 setOperationAction(ISD::FMA, MVT::v8f32, Legal); 1109 setOperationAction(ISD::FMA, MVT::v4f64, Legal); 1110 setOperationAction(ISD::FMA, MVT::v4f32, Legal); 1111 setOperationAction(ISD::FMA, MVT::v2f64, Legal); 1112 setOperationAction(ISD::FMA, MV [all...] |
/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.cpp | 53 cl::desc("NVPTX Specific: FMA contraction (0: don't do it" 3891 // which guarantees that the FMA will not increase register pressure at node N. 3923 return DAG.getNode(ISD::FMA, SDLoc(N), VT,
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