Searched defs:Subtarget (Results 51 - 75 of 81) sorted by relevance

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/external/mesa3d/src/gallium/drivers/radeon/
H A DAMDILISelDAGToDAG.cpp37 // Subtarget - Keep a pointer to the AMDGPU Subtarget around so that we can
39 const AMDGPUSubtarget &Subtarget; member in class:__anon13646::AMDGPUDAGToDAGISel
89 : SelectionDAGISel(TM), Subtarget(TM.getSubtarget<AMDGPUSubtarget>())
/external/llvm/lib/Target/X86/
H A DX86RegisterInfo.cpp160 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>(); local
164 if (Subtarget.isTarget64BitLP64())
168 if (Subtarget.isTarget64BitLP64())
172 if (Subtarget.isTarget64BitLP64())
176 if (Subtarget.isTarget64BitLP64())
231 const X86Subtarget &Subtarget = MF->getSubtarget<X86Subtarget>(); local
232 bool HasSSE = Subtarget.hasSSE1();
233 bool HasAVX = Subtarget.hasAVX();
234 bool HasAVX512 = Subtarget.hasAVX512();
312 const X86Subtarget &Subtarget local
626 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>(); local
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H A DX86MCInstLower.cpp399 static unsigned getRetOpcode(const X86Subtarget &Subtarget) { argument
400 return Subtarget.is64Bit() ? X86::RETQ : X86::RETL;
545 const X86Subtarget &Subtarget = AsmPrinter.getSubtarget(); local
546 unsigned ReturnReg = Subtarget.is64Bit() ? X86::RAX : X86::EAX;
548 OutMI.setOpcode(getRetOpcode(Subtarget));
844 assert(Subtarget->is64Bit() && "Statepoint currently only supports X86-64");
848 EmitNops(*OutStreamer, PatchBytes, Subtarget->is64Bit(),
934 assert(Subtarget->is64Bit() && "Patchpoint currently only supports X86-64");
984 EmitNops(*OutStreamer, NumBytes - EncodedBytes, Subtarget->is64Bit(),
1215 EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget)));
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H A DX86FastISel.cpp49 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
51 const X86Subtarget *Subtarget; member in class:__anon12378::final
64 Subtarget = &funcInfo.MF->getSubtarget<X86Subtarget>();
65 X86ScalarSSEf64 = Subtarget->hasSSE2();
66 X86ScalarSSEf32 = Subtarget->hasSSE1();
136 return Subtarget->getInstrInfo();
375 Opc = Subtarget->hasAVX() ? X86::VMOVSSrm : X86::MOVSSrm;
384 Opc = Subtarget->hasAVX() ? X86::VMOVSDrm : X86::MOVSDrm;
396 Opc = Subtarget->hasAVX() ? X86::VMOVAPSrm : X86::MOVAPSrm;
398 Opc = Subtarget
1158 X86ChooseCmpOpcode(EVT VT, const X86Subtarget *Subtarget) argument
2810 computeBytesPoppedByCallee(const X86Subtarget *Subtarget, CallingConv::ID CC, ImmutableCallSite *CS) argument
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H A DX86ISelDAGToDAG.cpp154 const X86Subtarget *Subtarget; member in class:__anon12385::final
174 Subtarget = &MF.getSubtarget<X86Subtarget>();
387 return Subtarget->getInstrInfo();
550 ((N->getOpcode() == X86ISD::CALL && !Subtarget->callRegIndirect()) ||
553 (Subtarget->is64Bit() ||
658 if (Subtarget->isTargetCygMing()) {
697 if (Subtarget->is64Bit()) {
723 Subtarget->isTargetLinux())
750 if (Subtarget->is64Bit() && N.getOpcode() == X86ISD::WrapperRIP &&
802 if (!Subtarget
1850 getAtomicLoadArithTargetConstant(SelectionDAG *CurDAG, SDLoc dl, enum AtomicOpc &Op, MVT NVT, SDValue Val, const X86Subtarget *Subtarget) argument
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/external/llvm/lib/Target/AArch64/
H A DAArch64FrameLowering.cpp283 const AArch64Subtarget &Subtarget = MF.getSubtarget<AArch64Subtarget>(); local
284 const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
285 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
542 const AArch64Subtarget &Subtarget = MF.getSubtarget<AArch64Subtarget>(); local
543 const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
544 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
H A DAArch64LoadStoreOptimizer.cpp88 const AArch64Subtarget *Subtarget; member in struct:__anon12018::AArch64LoadStoreOpt
627 if (!Subtarget->isLittleEndian())
655 if ((ExtDestMI == Rt2MI) == Subtarget->isLittleEndian()) {
1529 bool ProfitableArch = Subtarget->isCortexA57();
1534 return ProfitableArch && !Subtarget->requiresStrictAlign();
1538 Subtarget = &static_cast<const AArch64Subtarget &>(Fn.getSubtarget());
1539 TII = static_cast<const AArch64InstrInfo *>(Subtarget->getInstrInfo());
1540 TRI = Subtarget->getRegisterInfo();
H A DAArch64ISelDAGToDAG.cpp38 /// Subtarget - Keep a pointer to the AArch64Subtarget around so that we can
40 const AArch64Subtarget *Subtarget; member in class:__anon12015::AArch64DAGToDAGISel
47 : SelectionDAGISel(tm, OptLevel), Subtarget(nullptr),
56 Subtarget = &MF.getSubtarget<AArch64Subtarget>();
2234 Subtarget->getFeatureBits(),
2268 Subtarget->getFeatureBits(),
2293 Subtarget->getFeatureBits(),
H A DAArch64FastISel.cpp105 /// Subtarget - Keep a pointer to the AArch64Subtarget around so that we can
107 const AArch64Subtarget *Subtarget; member in class:__anon12012::final
251 Subtarget =
309 return Subtarget->isTargetDarwin() ? CC_AArch64_DarwinPCS : CC_AArch64_AAPCS;
375 if (Subtarget->isTargetMachO() && TM.getCodeModel() == CodeModel::Large) {
418 if (TM.getCodeModel() != CodeModel::Small && !Subtarget->isTargetMachO())
421 unsigned char OpFlags = Subtarget->ClassifyGlobalReference(GV, TM);
2828 if (VT.isFloatingPoint() && !Subtarget->hasFPARMv8())
2832 (!Subtarget->hasNEON() || !Subtarget
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/external/llvm/lib/Target/Mips/
H A DMipsSEFrameLowering.cpp75 const MipsSubtarget &Subtarget; member in class:__anon12246::ExpandPseudo
83 Subtarget(static_cast<const MipsSubtarget &>(MF.getSubtarget())),
84 TII(*static_cast<const MipsSEInstrInfo *>(Subtarget.getInstrInfo())),
85 RegInfo(*Subtarget.getRegisterInfo()) {}
283 if ((Subtarget.isABI_FPXX() && !Subtarget.hasMTHC1()) ||
284 (FP64 && !Subtarget.useOddSPReg())) {
292 assert(Subtarget.isGP64bit() || Subtarget.hasMTHC1() ||
293 !Subtarget
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H A DMipsFastISel.cpp74 /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
77 const MipsSubtarget *Subtarget; member in class:__anon12239::final
191 Subtarget(&funcInfo.MF->getSubtarget<MipsSubtarget>()),
192 TII(*Subtarget->getInstrInfo()), TLI(*Subtarget->getTargetLowering()) {
195 bool ISASupported = !Subtarget->hasMips32r6() && Subtarget->hasMips32();
199 UnsupportedFPMode = Subtarget->isFP64bit();
1186 if (ArgSize < 8 && !Subtarget->isLittle())
1347 if (Subtarget
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H A DMipsSEISelLowering.cpp44 if (Subtarget.isGP64bit())
47 if (Subtarget.hasDSP() || Subtarget.hasMSA()) {
59 if (Subtarget.hasDSP()) {
83 if (Subtarget.hasDSPR2())
86 if (Subtarget.hasMSA()) {
102 if (!Subtarget.useSoftFloat()) {
106 if (!Subtarget.isSingleFloat()) {
107 if (Subtarget.isFP64bit())
119 if (Subtarget
528 performADDECombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument
548 performANDCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument
663 performORCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument
783 performSUBECombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument
848 performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty, SelectionDAG &DAG, const MipsSubtarget &Subtarget) argument
873 performSHLCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument
896 performSRACombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument
942 performSRLCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument
1040 performXORCombine(SDNode *N, SelectionDAG &DAG, const MipsSubtarget &Subtarget) argument
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/external/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.cpp103 const PPCSubtarget &Subtarget = MF->getSubtarget<PPCSubtarget>(); local
105 if (Subtarget.hasVSX())
107 if (Subtarget.hasAltivec())
112 if (Subtarget.isDarwinABI())
114 ? (Subtarget.hasAltivec() ? CSR_Darwin64_Altivec_SaveList
116 : (Subtarget.hasAltivec() ? CSR_Darwin32_Altivec_SaveList
123 ? (Subtarget.hasAltivec()
127 : (Subtarget.hasAltivec() ? CSR_SVR432_Altivec_SaveList
134 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); local
136 if (Subtarget
167 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); local
293 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); local
329 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); local
443 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); local
469 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); local
514 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); local
557 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); local
601 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); local
651 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); local
677 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); local
699 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); local
759 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); local
903 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); local
990 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); local
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H A DPPCAsmPrinter.cpp71 const PPCSubtarget *Subtarget; member in class:__anon12277::PPCAsmPrinter
102 Subtarget = &MF.getSubtarget<PPCSubtarget>();
173 if (!Subtarget->isDarwin())
289 if (!Subtarget->isDarwin())
394 int TOCSaveOffset = Subtarget->isELFv2ABI() ? 24 : 40;
403 if (!Subtarget->isELFv2ABI()) {
464 ((Subtarget->isPPC64() && MI->getOperand(0).getReg() == PPC::X3) ||
465 (!Subtarget->isPPC64() && MI->getOperand(0).getReg() == PPC::R3)) &&
468 ((Subtarget->isPPC64() && MI->getOperand(1).getReg() == PPC::X3) ||
469 (!Subtarget
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H A DPPCFastISel.cpp2342 const PPCSubtarget &Subtarget = FuncInfo.MF->getSubtarget<PPCSubtarget>(); local
2343 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI())
/external/llvm/lib/CodeGen/
H A DRegAllocPBQP.cpp760 const TargetSubtargetInfo &Subtarget = MF.getSubtarget(); local
767 ConstraintsRoot->addConstraint(Subtarget.getCustomPBQPConstraints());
/external/llvm/lib/Target/ARM/
H A DARMAsmPrinter.cpp92 (Subtarget->isTargetELF()
106 Subtarget = &MF.getSubtarget<ARMSubtarget>();
139 if (Subtarget->isTargetCOFF()) {
544 (Subtarget->isTargetAEABI() || Subtarget->isTargetGNUAEABI()))
559 const ARMSubtarget *Subtarget) {
563 if (Subtarget->hasV8Ops())
565 else if (Subtarget->hasV7Ops()) {
566 if (Subtarget->isMClass() && Subtarget
558 getArchForCPU(StringRef CPU, const ARMSubtarget *Subtarget) argument
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H A DARMFastISel.cpp77 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
79 const ARMSubtarget *Subtarget; member in class:__anon12087::final
94 Subtarget(
97 TM(funcInfo.MF->getTarget()), TII(*Subtarget->getInstrInfo()),
98 TLI(*Subtarget->getTargetLowering()) {
489 if (!Subtarget->hasVFP2()) return false;
517 if (Subtarget->hasV6T2Ops() && isUInt<16>(CI->getZExtValue())) {
529 if (VT == MVT::i32 && Subtarget->hasV6T2Ops() && CI->isNegative()) {
546 if (Subtarget->useMovt(*FuncInfo.MF))
584 bool IsIndirect = Subtarget
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H A DARMISelDAGToDAG.cpp64 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
66 const ARMSubtarget *Subtarget; member in class:__anon12092::ARMDAGToDAGISel
74 Subtarget = &MF.getSubtarget<ARMSubtarget>();
340 if (!Subtarget->hasV6T2Ops())
343 bool isThumb2 = Subtarget->isThumb();
432 if (!Subtarget->isCortexA7() && !Subtarget->isCortexA8() &&
433 !Subtarget->isCortexA9() && !Subtarget->isSwift())
474 if (!Subtarget
3459 getMClassRegisterMask(StringRef Reg, StringRef Flags, bool IsRead, const ARMSubtarget *Subtarget) argument
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H A DARMBaseInstrInfo.cpp97 Subtarget(STI) {
122 if (Subtarget.isThumb2() || Subtarget.hasVFP2())
662 const ARMSubtarget &Subtarget) const {
663 unsigned Opc = Subtarget.isThumb()
664 ? (Subtarget.isMClass() ? ARM::t2MRS_M : ARM::t2MRS_AR)
672 if (Subtarget.isMClass())
683 const ARMSubtarget &Subtarget) const {
684 unsigned Opc = Subtarget.isThumb()
685 ? (Subtarget
3462 adjustDefLatency(const ARMSubtarget &Subtarget, const MachineInstr *DefMI, const MCInstrDesc *DefMCID, unsigned DefAlign) argument
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/external/llvm/lib/Target/NVPTX/
H A DNVPTXISelDAGToDAG.cpp60 Subtarget = &static_cast<const NVPTXSubtarget &>(MF.getSubtarget());
102 const NVPTXTargetLowering *TL = Subtarget->getTargetLowering();
549 static bool canLowerToLDG(MemSDNode *N, const NVPTXSubtarget &Subtarget, argument
562 if (!Subtarget.hasLDG() || CodeAddrSpace != NVPTX::PTXLdStInstCode::GLOBAL ||
676 if (canLowerToLDG(LD, *Subtarget, codeAddrSpace, MF)) {
914 if (canLowerToLDG(MemSD, *Subtarget, CodeAddrSpace, MF)) {
/external/llvm/lib/Target/SystemZ/
H A DSystemZISelDAGToDAG.cpp133 const SystemZSubtarget *Subtarget; member in class:__anon12321::SystemZDAGToDAGISel
145 return Subtarget->getInstrInfo();
336 Subtarget = &MF.getSubtarget<SystemZSubtarget>();
948 if (Subtarget->hasHighWord())
961 if (Subtarget->hasMiscellaneousExtensions())
964 if (VT == MVT::i32 && Subtarget->hasHighWord()) {
1017 if (Subtarget->hasMiscellaneousExtensions())
/external/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelDAGToDAG.cpp42 // Subtarget - Keep a pointer to the AMDGPU Subtarget around so that we can
44 const AMDGPUSubtarget *Subtarget; member in class:__anon12039::AMDGPUDAGToDAGISel
162 Subtarget = &static_cast<const AMDGPUSubtarget &>(MF.getSubtarget());
187 Subtarget->getInstrInfo()->get(N->getMachineOpcode());
195 return Subtarget->getRegisterInfo()->getRegClass(RegClass);
200 Subtarget->getRegisterInfo()->getRegClass(RCID);
204 return Subtarget->getRegisterInfo()->getSubClassWithSubReg(SuperRC,
265 if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS ||
325 Subtarget
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/external/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp73 const XCoreSubtarget &Subtarget)
74 : TargetLowering(TM), TM(TM), Subtarget(Subtarget) {
80 computeRegisterProperties(Subtarget.getRegisterInfo());
816 const TargetRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
862 const TargetRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
1556 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
72 XCoreTargetLowering(const TargetMachine &TM, const XCoreSubtarget &Subtarget) argument
/external/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp199 if (Subtarget->is64Bit())
374 if (Subtarget->is64Bit())
682 Subtarget->getStackPointerBias());
707 if (Subtarget->is64Bit())
975 const SparcRegisterInfo *TRI = Subtarget->getRegisterInfo();
1189 unsigned StackOffset = Offset + Subtarget->getStackPointerBias() + 128;
1242 Subtarget->getStackPointerBias() +
1286 const SparcRegisterInfo *TRI = Subtarget->getRegisterInfo();
1426 : TargetLowering(TM), Subtarget(&STI) {
1442 if (Subtarget
2507 LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget) argument
2538 getFRAMEADDR(uint64_t depth, SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget) argument
2577 LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget) argument
2586 LowerRETURNADDR(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, const SparcSubtarget *Subtarget) argument
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