/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.cpp | 4278 EVT ResVT = N->getValueType(0); local 4281 assert(ResVT.isVector() && "Vector load must have vector type"); 4286 assert(ResVT.isSimple() && "Can only handle simple types"); 4287 switch (ResVT.getSimpleVT().SimpleTy) { 4309 TD.getPrefTypeAlignment(ResVT.getTypeForEVT(*DAG.getContext())); 4319 EVT EltVT = ResVT.getVectorElementType(); 4320 unsigned NumElts = ResVT.getVectorNumElements(); 4365 Res = DAG.getNode(ISD::TRUNCATE, DL, ResVT.getVectorElementType(), Res); 4371 SDValue BuildVec = DAG.getNode(ISD::BUILD_VECTOR, DL, ResVT, ScalarRes); 4394 EVT ResVT local [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeVectorTypes.cpp | 1505 EVT ResVT = N->getValueType(0); local 1511 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(), 1517 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi); 1955 EVT ResVT = N->getValueType(0); local 1961 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(), 1967 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi); 3261 EVT ResVT = EVT::getVectorVT(*DAG.getContext(), local 3265 ISD::EXTRACT_SUBVECTOR, dl, ResVT, WideSETCC,
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H A D | LegalizeIntegerTypes.cpp | 182 EVT ResVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); local 184 N->getMemoryVT(), ResVT,
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H A D | DAGCombiner.cpp | 10325 EVT ResVT = Use->getValueType(0); local 10326 const TargetRegisterClass *ResRC = TLI.getRegClassFor(ResVT.getSimpleVT()); 10329 if (ArgRC == ResRC || !TLI.isOperationLegal(ISD::LOAD, ResVT)) 10343 ResVT.getTypeForEVT(*DAG->getContext())); 10349 if (!TLI.isOperationLegal(ISD::LOAD, ResVT))
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/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelLowering.cpp | 2648 EVT ResVT = Op.getValueType(); 2654 return DAG.getLoad(ResVT, DL, LoadN->getChain(), LoadN->getBasePtr(), 2657 if (InVT == MVT::i32 && ResVT == MVT::f32) { 2673 if (InVT == MVT::f32 && ResVT == MVT::i32) { 4534 // producing a result of type ResVT. Op is a possibly bitcast version 4538 SDValue SystemZTargetLowering::combineExtract(SDLoc DL, EVT ResVT, EVT VecVT, 4564 return DAG.getUNDEF(ResVT); 4594 EVT VT = MVT::getIntegerVT(ResVT.getSizeInBits()); 4596 if (VT != ResVT) { 4598 Op = DAG.getNode(ISD::BITCAST, DL, ResVT, O [all...] |
/external/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 8487 EVT ResVT = N->getValueType(0); local 8488 if (!ResVT.isVector() || TLI.isTypeLegal(ResVT)) 8495 if (!ResVT.isSimple() || !SrcVT.isSimple()) 8513 unsigned NumElements = ResVT.getVectorNumElements(); 8516 ResVT.getVectorElementType(), NumElements / 2); 8529 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi); 9510 EVT ResVT = N->getValueType(0); 9514 if (ResVT.getSizeInBits() != CmpVT.getSizeInBits()) 9523 return DAG.getNode(ISD::VSELECT, SDLoc(N), ResVT, SetC 9535 EVT ResVT = N->getValueType(0); local [all...] |
/external/llvm/lib/Target/X86/ |
H A D | X86FastISel.cpp | 3199 EVT ResVT = VA.getValVT(); local 3200 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64; 3201 unsigned MemSize = ResVT.getSizeInBits()/8; 3206 Opc = ResVT == MVT::f32 ? X86::MOVSSrm : X86::MOVSDrm;
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H A D | X86ISelLowering.h | 889 bool isExtractSubvectorCheap(EVT ResVT, unsigned Index) const override;
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H A D | X86ISelLowering.cpp | 4190 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT, argument 4192 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT)) 4195 return (Index == 0 || Index == ResVT.getVectorNumElements()); 6616 MVT ResVT = Op.getSimpleValueType(); 6618 assert((ResVT.is256BitVector() || 6619 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide"); 6623 unsigned NumElems = ResVT.getVectorNumElements(); 6624 if (ResVT.is256BitVector()) 6625 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl); 6628 MVT HalfVT = MVT::getVectorVT(ResVT [all...] |
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelDAGToDAG.cpp | 2365 EVT ResVT = VecVT.changeVectorElementTypeToInteger(); local 2367 SDValue VCmp(CurDAG->getMachineNode(VCmpInst, dl, ResVT, LHS, RHS), 0); 2370 ResVT, VCmp, VCmp); 2373 return CurDAG->SelectNodeTo(N, VCmpInst, ResVT, LHS, RHS);
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H A D | PPCISelLowering.cpp | 6031 EVT ResVT = Op.getValueType(); local 6048 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV); 6051 return DAG.getNode(PPCISD::FSEL, dl, ResVT, 6060 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV); 6068 return DAG.getNode(PPCISD::FSEL, dl, ResVT, 6081 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); 6084 return DAG.getNode(PPCISD::FSEL, dl, ResVT, 6091 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); 6097 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); 6103 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cm [all...] |
/external/llvm/include/llvm/Target/ |
H A D | TargetLowering.h | 1715 virtual bool isExtractSubvectorCheap(EVT ResVT, unsigned Index) const {
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