Searched refs:Sched (Results 1 - 25 of 26) sorted by relevance

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/external/llvm/lib/Target/PowerPC/
H A DPPCHazardRecognizers.cpp68 if (!PredMCID || PredMCID->getSchedClass() != PPC::Sched::IIC_SprMTSPR)
97 case PPC::Sched::IIC_IntDivW:
98 case PPC::Sched::IIC_IntDivD:
99 case PPC::Sched::IIC_LdStLoadUpd:
100 case PPC::Sched::IIC_LdStLDU:
101 case PPC::Sched::IIC_LdStLFDU:
102 case PPC::Sched::IIC_LdStLFDUX:
103 case PPC::Sched::IIC_LdStLHA:
104 case PPC::Sched::IIC_LdStLHAU:
105 case PPC::Sched
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H A DPPCISelLowering.h480 Sched::Preference getSchedulingPreference(SDNode *N) const override;
H A DPPCISelLowering.cpp917 setSchedulingPreference(Sched::Source);
919 setSchedulingPreference(Sched::Hybrid);
11580 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
11584 return Sched::ILP;
/external/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.cpp1792 if (SchedClass == Hexagon::Sched::M_tc_3or4x_SLOT23)
2004 case Hexagon::Sched::ALU32_2op_tc_1_SLOT0123:
2005 case Hexagon::Sched::ALU32_3op_tc_1_SLOT0123:
2006 case Hexagon::Sched::ALU32_ADDI_tc_1_SLOT0123:
2007 case Hexagon::Sched::ALU64_tc_1_SLOT23:
2008 case Hexagon::Sched::EXTENDER_tc_1_SLOT0123:
2009 case Hexagon::Sched::S_2op_tc_1_SLOT23:
2010 case Hexagon::Sched::S_3op_tc_1_SLOT23:
2011 case Hexagon::Sched::V2LDST_tc_ld_SLOT01:
2012 case Hexagon::Sched
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H A DHexagonISelLowering.cpp1531 setSchedulingPreference(Sched::VLIW);
1533 setSchedulingPreference(Sched::Source);
/external/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCInstrInfo.cpp596 case Hexagon::Sched::ALU32_3op_tc_2_SLOT0123:
597 case Hexagon::Sched::ALU64_tc_2_SLOT23:
598 case Hexagon::Sched::ALU64_tc_3x_SLOT23:
599 case Hexagon::Sched::M_tc_2_SLOT23:
600 case Hexagon::Sched::M_tc_3x_SLOT23:
601 case Hexagon::Sched::S_2op_tc_2_SLOT23:
602 case Hexagon::Sched::S_3op_tc_2_SLOT23:
603 case Hexagon::Sched::S_3op_tc_3x_SLOT23:
/external/llvm/include/llvm/CodeGen/
H A DScheduleDAG.h309 Sched::Preference SchedulingPref; // Scheduling preference.
335 SchedulingPref(Sched::None), isDepthCurrent(false),
351 SchedulingPref(Sched::None), isDepthCurrent(false),
366 SchedulingPref(Sched::None), isDepthCurrent(false),
/external/llvm/include/llvm/Target/
H A DTargetLowering.h66 namespace Sched { namespace in namespace:llvm
367 Sched::Preference getSchedulingPreference() const {
374 virtual Sched::Preference getSchedulingPreference(SDNode *) const {
375 return Sched::None;
1213 void setSchedulingPreference(Sched::Preference Pref) {
1826 Sched::Preference SchedPreferenceInfo;
/external/llvm/lib/Target/ARM/
H A DARMISelLowering.h399 Sched::Preference getSchedulingPreference(SDNode *N) const override;
H A DARMISelLowering.cpp1025 setSchedulingPreference(Sched::RegPressure);
1027 setSchedulingPreference(Sched::Hybrid);
1277 Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
1280 return Sched::RegPressure;
1287 return Sched::ILP;
1291 return Sched::RegPressure;
1299 return Sched::RegPressure;
1302 return Sched::ILP;
1304 return Sched::RegPressure;
/external/mesa3d/src/gallium/drivers/radeon/
H A DR600ISelLowering.cpp50 setSchedulingPreference(Sched::VLIW);
H A DAMDILISelLowering.cpp226 setSchedulingPreference(Sched::RegPressure);
/external/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGISel.cpp308 TLI->getSchedulingPreference() == Sched::Source)
310 if (TLI->getSchedulingPreference() == Sched::RegPressure)
312 if (TLI->getSchedulingPreference() == Sched::Hybrid)
314 if (TLI->getSchedulingPreference() == Sched::VLIW)
316 assert(TLI->getSchedulingPreference() == Sched::ILP &&
H A DScheduleDAGRRList.cpp2362 bool LStall = (!checkPref || left->SchedulingPref == Sched::ILP) &&
2364 bool RStall = (!checkPref || right->SchedulingPref == Sched::ILP) &&
2380 if (!checkPref || (left->SchedulingPref == Sched::ILP ||
2381 right->SchedulingPref == Sched::ILP)) {
H A DScheduleDAGSDNodes.cpp83 SU->SchedulingPref = Sched::None;
/external/llvm/lib/Target/AMDGPU/
H A DR600InstrInfo.cpp182 return (get(Opcode).getSchedClass() == AMDGPU::Sched::TransALU);
190 return (get(Opcode).getSchedClass() == AMDGPU::Sched::VecALU);
H A DR600ISelLowering.cpp190 setSchedulingPreference(Sched::Source);
H A DSIISelLowering.cpp288 setSchedulingPreference(Sched::RegPressure);
H A DAMDGPUISelLowering.cpp384 setSchedulingPreference(Sched::RegPressure);
/external/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp104 setSchedulingPreference(Sched::RegPressure);
/external/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp747 SchedPreferenceInfo = Sched::ILP;
/external/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp84 setSchedulingPreference(Sched::Source);
/external/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp133 setSchedulingPreference(Sched::RegPressure);
135 setSchedulingPreference(Sched::Source);
/external/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp123 setSchedulingPreference(Sched::RegPressure);
/external/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp89 setSchedulingPreference(Sched::ILP);
91 setSchedulingPreference(Sched::ILP);
93 setSchedulingPreference(Sched::RegPressure);
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