| 9d4ab9a663d4088ec553edaae0eeafb746d2490d |
|
11-Feb-2013 |
Brian Paul <brianp@vmware.com> |
mesa: pass context parameter to gl_renderbuffer::Delete()
We sometimes need a rendering context when deleting renderbuffers.
Pass it explicitly instead of trying to grab a current context
(which might be NULL). The next patch will make use of this.
Note: this is a candidate for the stable branches.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
(cherry picked from commit c73245882c7ff1277b190b97f093f7b423a22f10)
Conflicts:
src/mesa/swrast/s_renderbuffer.c
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| dca04373c2efb177dbb7dca3ad2b57cb36b2ebe6 |
|
30-Aug-2012 |
Brian Paul <brianp@vmware.com> |
mesa: fix-up and use _mesa_delete_renderbuffer()
_mesa_delete_renderbuffer() should free the mutex (though that may be a
no-op) and then free the renderbuffer object itself. Subclasses of
gl_renderbuffer can use this function too.
Reviewed-by: José Fonseca <jfonseca@vmware.com>
(cherry picked from commit 8472bb4508515cf0f717344ef5cc863b6e97e56a)
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 68da5dfc2c2e9c0aca47431076be0cd43406d4aa |
|
30-Aug-2012 |
Paul Berry <stereotype441@gmail.com> |
intel: Add map_stencil_as_y_tiled to intel_region_get_aligned_offset.
This patch modifies intel_region_get_aligned_offset() to make the
appropriate calculation when the blorp engine sets up a W-tiled
stencil buffer using a Y-tiled SURFACE_STATE.
Acked-by: Eric Anholt <eric@anholt.net>
(cherry picked from commit b760c9913dcff848a2aa0e60abeb48e596ae8fee)
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 96fd94ba9421c7c3072988f999ee869534f2bc2a |
|
30-Aug-2012 |
Paul Berry <stereotype441@gmail.com> |
intel: Add map_stencil_as_y_tiled to intel_region_get_tile_masks.
When the blorp engine is performing a blit from one stencil buffer to
another, it sets up the surface state for these buffers as Y-tiled, so
it needs to be able to force intel_region_get_tile_masks() to return
the appropriate masks for a Y-tiled region.
Acked-by: Eric Anholt <eric@anholt.net>
(cherry picked from commit 50dec7fc2d5ba813aaa822596d124098a22db301)
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| d47a6ada9ca9670c60fc141fabadf40c63031c08 |
|
24-Aug-2012 |
Brian Paul <brianp@vmware.com> |
mesa: add texture target field to ChooseTextureFormat() driver hook
This will let us choose the actual hardware format depending on the
type of texture.
v2: fixup radeon, nouveau, intel and swrast drivers too
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 6b56140b4bafcef8bea5ca67cb31023a533c3bd4 |
|
27-Jul-2012 |
Chad Versace <chad.versace@linux.intel.com> |
i965: Mark needed downsamples for msaa winsys buffers
Add function intel_renderbuffer_set_needs_downsample. It is a no-op
except on multisample winsys buffers shared with DRI2.
Mark the needed downsamples with the new function at two locations:
- Immediately after drawing is complete.
- After blitting.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 4eba67285fb6b5d2dd4927e8dc4b3e2945435309 |
|
20-Jul-2012 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Refactor creation of hiz and mcs miptrees
Move the logic for creating the ancillary hiz and mcs miptress for winsys
and non-texture renderbuffers from intel_alloc_renderbuffer_storage to
intel_miptree_create_for_renderbuffer. Let's try to isolate complex
miptree logic to intel_mipmap_tree.c.
Without this refactor, code duplication would be required along the
intel_process_dri2_buffer codepath in order to create the mcs miptree.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| e2f2376e884225705e2369caee4a8c4e90e938f3 |
|
12-Jul-2012 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Set num samples for winsys renderbuffers
Add a new param, num_samples, to intel_create_renderbuffer and
intel_create_private_renderbuffer.
No multisample GL config is yet advertised, so the value of num_samples is
currently 0. For server-owned winsys buffers, gl_renderbuffer::NumSamples
is not yet used.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com> (v1)
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 53fa28f7b1f21251a3807abf1f234f52beff0256 |
|
11-Jul-2012 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Refactor quantize_num_samples
Rename quantize_num_samples to intel_quantize_num_samples and change the
first param from struct intel_context* to struct intel_screen*. The
function will later be used by intelCreateBuffer, which is not bound to
any context but is bound to a screen.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com> (v1)
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| c18806cebf107d03751b11cc8866062c3822a56f |
|
27-Jul-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/msaa: Allow GL_SAMPLES to be set to 1 prior to Gen6.
This patch allows GL_SAMPLES to be set to either 0 or 1 on i965
platforms that don't support MSAA (those prior to Gen6). Setting
GL_SAMPLES=1 has the same effect as setting it to 0 on these platforms
(because MSAA is unsupported), but is distinguishable via the GL API.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=50165
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| c738ea1191cd1b5a0dc60b0e6d05fd918083e961 |
|
18-Jul-2012 |
Paul Berry <stereotype441@gmail.com> |
intel: Make more consistent use of _mesa_is_{user,winsys}_fbo()
A lot of code was still differentiating between between winsys and
user fbos by testing the fbo's name against zero. This converts
everything in the i915 and 965 drivers over to use _mesa_is_user_fbo()
and _mesa_is_winsys_fbo().
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 497bf5dd2b36c7d0c8ae23d2bf039c91b97140fc |
|
18-Jul-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/msaa: Switch on 8x MSAA for Gen7.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 9bbf7c139bb02fe9fc3822bf2ca9ac5963d0d5af |
|
04-Jul-2012 |
Eric Anholt <eric@anholt.net> |
intel: Remove dead intel_framebuffer_has_hiz().
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 433ff3e16e8e090fd3a1bf427e61f3e5971a5740 |
|
04-Jul-2012 |
Eric Anholt <eric@anholt.net> |
intel: Add a function for creating a private window system buffer.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| ccae1b1cd7b89102a9d9bfc29eb1e7e48aad8969 |
|
03-Jul-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/msaa: Allocate MCS buffer when CMS MSAA is in use.
To implement Gen7's CMS MSAA layout, we need an extra buffer, the MCS
(Multisample Control Surface) buffer. This patch introduces code for
allocating and deallocating the buffer, and storing a pointer to it in
the intel_mipmap_tree struct.
No functional change, since the CMS layout is not enabled yet.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| ab014adaed14a9ca213447dc913d0dce7906be56 |
|
10-May-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/msaa: Enable 4x MSAA on Gen7.
Basic 4x MSAA support now works on Gen7. This patch enables it.
As with Gen6, MSAA support is still fairly preliminary. In
particular, the following are not yet supported:
- 8x oversampling (Gen7 has hardware support for this, but we do not
yet expose it).
- Fully general blits between MSAA and non-MSAA buffers.
- Formats other than RGBA8, DEPTH24, and STENCIL8.
- Centrold interpolation.
- Coverage parameters (glSampleCoverage, GL_SAMPLE_ALPHA_TO_COVERAGE,
GL_SAMPLE_ALPHA_TO_ONE, GL_SAMPLE_COVERAGE, GL_SAMPLE_COVERAGE_VALUE,
GL_SAMPLE_COVERAGE_INVERT).
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 19e9b24626c2b9d7abef054d57bb2a52106c545b |
|
30-Apr-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/gen6: Initial implementation of MSAA.
This patch enables MSAA for Gen6, by modifying intel_mipmap_tree to
understand multisampled buffers, adapting the rendering pipeline setup
to enable multisampled rendering, and adding multisample resolve
operations to brw_blorp_blit.cpp. Some preparation work is also
included for Gen7, but it is not yet enabled.
MSAA support is still fairly preliminary. In particular, the
following are not yet supported:
- Fully general blits between MSAA and non-MSAA buffers.
- Formats other than RGBA8, DEPTH24, and STENCIL8.
- Centroid interpolation.
- Coverage parameters (glSampleCoverage, GL_SAMPLE_ALPHA_TO_COVERAGE,
GL_SAMPLE_ALPHA_TO_ONE, GL_SAMPLE_COVERAGE, GL_SAMPLE_COVERAGE_VALUE,
GL_SAMPLE_COVERAGE_INVERT).
Fixes piglit tests "EXT_framebuffer_multisample/accuracy" on
i965/Gen6.
v2:
- In intel_alloc_renderbuffer_storage(), quantize the requested number
of samples to the next higher sample count supported by the
hardware. This ensures that a query of GL_SAMPLES will return the
correct value. It also ensures that MSAA is fully disabled on Gen7
for now (since Gen7 MSAA support doesn't work yet).
- When reading from a non-MSAA surface, ensure that s_is_zero is true
so that we won't try to read from a nonexistent sample.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 506d70be21cd3469118de89297cba0c0f709c1ae |
|
30-Apr-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/gen6+: Add code to perform blits on the render path ("blorp").
This patch expands the "blorp" component to be able to perform blits
as well as HiZ resolves. The new blitting code is located in
brw_blorp_blit.cpp. This includes the necessary fragment shader code
to look up pixels in the source buffer (which is configured as a
texture) and output them to the destination buffer (which is
configured as the render target).
Most of the time the fragment shader code is simple and
straightforward, since it merely has to apply a coordinate offset,
read from the texture, and write to the render target. However, in
the case of blitting stencil buffers, things are more complicated,
since the GPU stores stencil data using W tiling, and W tiling is not
supported for textures or render targets. So, we set up the stencil
buffers as Y tiled, and emit fragment shader code that adjusts the
coordinates to account for the difference between W and Y tiling.
Furthermore, since a rectangular region in W tiling does not
necessarily correspond to a rectangular region in Y tiling, we widen
the rectangle primitive to the nearest tile boundary and have the
fragment shader "kill" any pixels that don't fall inside the actual
desired destination rectangle.
All of this is a necessary prerequisite for implementing MSAA, since
we'll need to be able to blit between multisample color, depth, and
stencil buffers and their non-multisampled counterparts, and none of
the existing blitting mechanisms support multisampling.
In addition, the new blitting code should speed up operations where we
previously fell back to software rasterization, such as blitting of
stencil buffers. The current fallback sequence is: first we try to do
a blit using the hardware blitting engine. If that fails we try to do
a blit using the render path. If that also fails then we do the blit
using a meta-op (which may or may not fall back to software
rasterization).
Note that blitting using the render path has some limitations at the
moment: it only supports a few formats, and it doesn't support
clipping or scissoring. These limitations will be addressed in future
patch series.
v2:
- Add the code that configures the WM program to
gen{6,7}_emit_wm_config() and gen7_emit_ps_config() rather than
creating separate ...enable() functions.
- Call intel_prepare_render before determining which miptrees we are
blitting from/to, because it may cause miptrees to be reallocated.
- Allow the blit to mirror X and/or Y coordinates.
- Disable blorp blits on Gen7 for now, since they aren't working yet.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 3ec0e55b63db3c1067f3bbf4563beb3b98a19288 |
|
15-Apr-2012 |
Paul Berry <stereotype441@gmail.com> |
i965: Fix mipmap offsets for HiZ and separate stencil buffers.
When rendering to a miplevel other than 0 within a color, depth,
stencil, or HiZ buffer, we need to tell the GPU to render to an offset
within the buffer, so that the data is written into the correct
miplevel. We do this using a coarse offset (in pages), and a fine
adjustment (the so-called "tile_x" and "tile_y" values, which are
measured in pixels).
We have always computed the coarse offset and fine adjustment using
intel_renderbuffer_tile_offsets() function. This worked fine for
color and combined depth/stencil buffers, but failed to work properly
when HiZ and separate stencil were in use. It failed to work because
there is only one set of fine adjustment controls shared by the HiZ,
depth, and stencil buffers, so we need to choose tile_x and tile_y
values that are compatible with the tiling of all three buffers, and
then compute separate coarse offsets for each buffer.
This patch fixes the HiZ and separate stencil case by replacing the
call to intel_renderbuffer_tile_offsets() with calls to two functions:
intel_region_get_tile_masks(), which determines how much of the
adjustment can be performed using offsets and how much can be
performed using tile_x and tile_y, and
intel_region_get_aligned_offset(), which computes the coarse offset.
intel_region_get_tile_offsets() is still used for color renderbuffers,
so to avoid code duplication, I've re-worked it to use
intel_region_get_tile_masks() and intel_region_get_aligned_offset().
On i965 Gen6, fixes piglit tests
"texturing/depthstencil-render-miplevels 1024 X" where X is one of
(depth, depth_and_stencil, depth_stencil_single_binding, depth_x,
depth_x_and_stencil, stencil, stencil_and_depth, stencil_and_depth_x).
On i965 Gen7, the variants of
"texturing/depthstencil-render-miplevels" that contain a stencil
buffer still fail, due to another problem: Gen7 seems to ignore the 3
LSB's of the tile_y adjustment (and possibly also tile_x).
v2: Removed spurious comments. Added assertions to check
preconditions of intel_region_get_aligned_offset().
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| b7406404aba1817d5a87714f97a108a755943452 |
|
23-Apr-2012 |
Eric Anholt <eric@anholt.net> |
intel: Return success when asked to allocate a 0-width/height renderbuffer.
It seems silly that GL lets you allocate these given that they're
framebuffer attachment incomplete, but the webgl conformance tests
actually go looking to see if the getters on 0-width/height
depth/stencil renderbuffers return good values. By failing out here,
they all got smashed to 0, which turned out to be correct for all the
getters they tested except for GL_RENDERBUFFER_INTERNAL_FORMAT. Now,
by succeeding but not making a miptree, that one also returns the
expected value.
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| e2dce7f7ee3e7da9cbb0bb33307ecd79e824426d |
|
10-Feb-2012 |
Eric Anholt <eric@anholt.net> |
intel: Fix rendering from textures after RenderTexture().
There's a serious trap for drivers: RenderTexture() does not indicate
that the texture is currently bound to the draw buffer, despite
FinishRenderTexture() signaling that the texture is just now being
unbound from the draw buffer.
We were acting as if RenderTexture() *was* the start of rendering and
that we could make texturing incoherent with the current contents of
the renderbuffer. This caused intel oglconform sRGB
Mipmap.1D_textures to fail, because we got a call to TexImage() and
thus RenderTexture() on a texture bound to a framebuffer that wasn't
the draw buffer, so we skipped validating the new image into the
texture object used for rendering.
We can't (easily) make RenderTexture() indicate the start of drawing,
because both our driver and gallium are using it as the moment to set
up the renderbuffer wrapper used for things like MapRenderbuffer().
Instead, postpone the setup of the workaround render target miptree
until update_renderbuffer time, so that we no longer need to skip
validation of miptrees used as render targets. As a bonus, this
should make GL_NV_texture_barrier possible.
(This also fixes a regression in the gen4 small-mipmap rendering since
3b38b33c1648b07e75dc4d8340758171e109c598, which switched
set_draw_offset from image->mt to irb->mt but didn't move the irb->mt
replacement up before set_draw_offset).
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=44961
NOTE: This is a candidate for the 8.0 branch.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 308c6be802fc8d7cd470316ace717aa7bb6b2a08 |
|
10-Feb-2012 |
Eric Anholt <eric@anholt.net> |
intel: Improve the fallback debug for framebuffer status checks.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 87b4c9b322dabeba7c9a9d02e9efefd2c89e6625 |
|
01-Feb-2012 |
Ian Romanick <ian.d.romanick@intel.com> |
intel: FBOs with texture border are unsupported
FBOs differ from textures in a significant way. With textures, we can
strip the border and get correct rendering except when the application
fetches texels outside [0,1].
With an FBO, the pixel at (0,0) is in the border. The
ARB_framebuffer_object spec says:
"If the attached image is a texture image, then the window
coordinates (x[w], y[w]) correspond to the texel (i, j, k), from
figure 3.10 as follows:
i = (x[w] - b)
j = (y[w] - b)
k = (layer - b)
where <b> is the texture image's border width..."
Since the border doesn't exist, we can never render any pixels in the
correct location. Just mark these FBOs FRAMEBUFFER_UNSUPPORTED.
NOTE: This is a candidate for the 8.0 branch.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=42336
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 796f44d77906342e5912e7da6bdba1ba86bab9f0 |
|
20-Jan-2012 |
Eric Anholt <eric@anholt.net> |
intel: Pass the gl_renderbuffer to render_target_supported() vtable method.
I'm going to want to go looking at it for an integer texture fix.
NOTE: This is a candidate for the 8.0 branch.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 7cac88679bb600f35694e91859c4682c04c32f7a |
|
20-Jan-2012 |
Eric Anholt <eric@anholt.net> |
intel: Make a renderbuffer wrapping a texture have the same _BaseFormat.
Otherwise, when you asked for the _BaseFormat of an rb wrapping a
GL_RGB texture, you got GL_RGBA because that's what we were storing
the texture data as.
NOTE: This is a candidate for the 8.0 branch.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| b73f5df6483b2e37235b258f705944321ee617f5 |
|
20-Jan-2012 |
Eric Anholt <eric@anholt.net> |
intel: Simplify intel_renderbuffer_update_wrapper() by passing in the image.
NOTE: This is a candidate for the 8.0 branch.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 74484c5d411788c855cf91a2017d763d6a8fb4f2 |
|
20-Jan-2012 |
Eric Anholt <eric@anholt.net> |
intel: Drop intel_wrap_miptree().
Most of this function was just calling
intel_renderbuffer_update_wrapper(), which was called immediately
afterwards in the only caller.
NOTE: This is a candidate for the 8.0 branch.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 42e9936ce6bcac9f863b2f85978489e4f804e927 |
|
25-Jan-2012 |
Eric Anholt <eric@anholt.net> |
intel: Fix accum buffer mapping since the swrast rework.
A pure swrast-allocated buffer gets an irb of NULL, so we segfaulted
in the clear-accum test. Just look at the swrast renderbuffer pointer
for handling swrast rbs.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 1839a7fc9faae81d32ffc0cdc908b933f4524e28 |
|
16-Jan-2012 |
Brian Paul <brianp@vmware.com> |
intel: remove intel_span_supports_format()
It always returned True.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 9f8ed9d66298e2dc5dff508e3ea723469fe06d93 |
|
16-Jan-2012 |
Brian Paul <brianp@vmware.com> |
intel: derive intel_renderbuffer from swrast_renderbuffer
Drivers that rely on swrast need to do this, as with swrast_texture_image.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 924de7dc96f4607cb3d833637b5f69f4b9e2a6d0 |
|
16-Jan-2012 |
Brian Paul <brianp@vmware.com> |
intel: use intel_rb_format() to get renderbuffer format
This will make future changes cleaner and less invasive.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 7a36345f70a0b8ac2d480bb52eb2c74c2be5a978 |
|
16-Jan-2012 |
Brian Paul <brianp@vmware.com> |
mesa: rename gl_renderbuffer::Data to Buffer
To better indicate that this pointer to the malloc'd memory.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| f9874feef4d8952df5054bd8e8f4e0deda4ef44f |
|
16-Jan-2012 |
Brian Paul <brianp@vmware.com> |
mesa: remove gl_renderbuffer::DataType
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 1e1b5cb01a10e39d01923e3c7e989c44210950cd |
|
16-Jan-2012 |
Brian Paul <brianp@vmware.com> |
mesa: remove gl_renderbuffer:RowStride field
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 41869c49421141807ab71cabca4c8a07611f6a64 |
|
16-Jan-2012 |
Brian Paul <brianp@vmware.com> |
intel: remove most of the span Get/PutRow code
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| ba5252e590782a77b8a46d9c0ec4691cf8da6298 |
|
19-Jan-2012 |
Chad Versace <chad.versace@linux.intel.com> |
intel/gen6: Some framebuffers having separate depthstencil should be unsupported
When the framebuffer has separate depth and stencil buffers, and HiZ is
not enabled on the depth buffer, mark the framebuffer as unsupported. This
happens when trying to create a framebuffer with Z16/S8 because we haven't
enabled HiZ on Z16 yet.
Fixes gles2conform test stencil8.
Note: This is a candiate for the 8.0 branch.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=44948
Reviewed-and-tested-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed--by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 062a4b601edaaea193397bd5d86fea11ceec04f4 |
|
12-Jan-2012 |
Brian Paul <brianp@vmware.com> |
intel: move declaration before code
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 6dbdc0395698de929e23b4ec1ab399e64ecfd264 |
|
07-Jan-2012 |
Brian Paul <brianp@vmware.com> |
intel: fix mapping of malloc'd renderbuffers
This fixes accum buffer operations. The accumulation buffer is the
only malloc-based renderbuffer for the intel drivers.
v2: apply x/y offset to returned pointer
NOTE: This is a candidate for the 8.0 branch.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 56b57aa360a8bad0c4b68fbdf7c64ac33f9e7661 |
|
29-Dec-2011 |
Brian Paul <brianp@vmware.com> |
mesa: rework ctx->Driver.CopyTexSubImage() parameters
Replace target, level parameters with gl_texture_image.
Add gl_renderbuffer parameter to indicate source buffer for the copy.
This removes some redundant code in the drivers to find the source
renderbuffer and the destination texture image (which we already had
in _mesa_CopyTexSubImage).
Signed-off-by: Brian Paul <brianp@vmware.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 6a1e19d0f63cb086e43505522cb72b0183da9b11 |
|
17-Dec-2011 |
Eric Anholt <eric@anholt.net> |
intel: Drop the batchbuffer flush on glRenderbufferStorage().
There's nothing batchbuffer-related here. State updates by the caller
will trigger re-emitting of any new hardware state.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 2529fde36ee29bf5789bb8a0234d3c60bd38f511 |
|
16-Dec-2011 |
Eric Anholt <eric@anholt.net> |
intel: Drop the batchbuffer flush on glFramebufferRenderbuffer().
There should be nothing special about this call compared to other
callers of intel_draw_buffer().
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 0c498467104e361e50bbb95adf2b2c0e799591dc |
|
08-Dec-2011 |
Eric Anholt <eric@anholt.net> |
intel: Stop creating the wrapped depth irb.
All the operations were just trying to get at irb->wrapped_depth->mt,
which is the same as irb->mt now.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| fdf18b323156098ba5fb2881aa1a7888d2e0667f |
|
15-Dec-2011 |
Eric Anholt <eric@anholt.net> |
i965: Properly demote the depth mt format for fake packed depth/stencil.
gen7 only supports the non-packed formats, even if you associate a
real separate stencil buffer -- otherwise it's as if the depth test
always fails.
This requires a little bit of care in the match_texture_image case,
since the miptree format no longer matches the texture image format.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 0b8b6c7e974930daf12e97fb8f0b2a2cc29396d9 |
|
08-Dec-2011 |
Eric Anholt <eric@anholt.net> |
intel: Stop creating the wrapped stencil irb.
There were only two places it was really used at this point, which was
in the batchbuffer emit of the separate stencil packets for gen6/7.
Just write in the ->stencil_mt reference in those two places and ditch
all this flailing around with allocation and refcounts.
v2: Fix separate stencil on gen7.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 7eb0aa398b9c0f7d8a224f2a4952f7875067e917 |
|
08-Dec-2011 |
Eric Anholt <eric@anholt.net> |
intel: Simplify and touch up the FBO completeness test.
Now that we have miptrees for everything, we can more easily test for
!has_separate_stencil completeness. Also, test for whether the
stencil rb is the wrong kind of format for separate stencil, or if we
are trying to do packed to different images of a single miptree.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 950310e7a363413bd87ce6e670a7b913fbddfbff |
|
08-Dec-2011 |
Eric Anholt <eric@anholt.net> |
intel: Remove another renderbuffer allocation path.
Now there's the thing that CALLOCs and sets up window system vtable,
and the thing that CALLOCs and sets up user renderbuffer vtable. The
user renderbuffer vtable gets replaced later by
intel_renderbuffer_update_wrapper for wrapped renderbuffers (things
with name == ~0).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| a91c31668fce46545570571468fefca216fcf881 |
|
08-Dec-2011 |
Eric Anholt <eric@anholt.net> |
intel: Make the separate stencil RB storage path match texture more.
There were too many things making intel_renderbuffer *s and tweaking
their bits.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| f22068d5be7c829d3768154845ef3c5a2986fed4 |
|
08-Dec-2011 |
Eric Anholt <eric@anholt.net> |
intel: Move S8 width/height alignment to miptree creation.
We were doing it in the caller in the renderbuffer code, but it was
missed in the separate stencil creation for textures. Apparently our
testing was using renderbuffers or pre-aligned sizes.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 8967f750953ca94aa36e3a8ed703a61f1b434f64 |
|
07-Dec-2011 |
Eric Anholt <eric@anholt.net> |
intel: Drop check for wrapped_depth in RB mapping.
This used to be needed because irb->mt would be unset for fake packed
depth/stencil, but no longer.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| faa44bc2f64eb2dfa36b553c06c9bf5fe53ed502 |
|
13-Dec-2011 |
Eric Anholt <eric@anholt.net> |
intel: Fix uninitialized values in debug output for renderbuffer mapping.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 96159c37e3e8c966dba7cf7fe70875372dd12293 |
|
30-Nov-2011 |
Eric Anholt <eric@anholt.net> |
intel: Rely on miptree mapping for all renderbuffer maps.
Now that all RBs have miptrees, and miptree mapping covered these last
two code paths, consistently use them.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 2d2bfd1f2643b93caf76087b6ac04544af52ee63 |
|
30-Nov-2011 |
Eric Anholt <eric@anholt.net> |
intel: Handle MapRenderbuffer of fake packed depth/stencil using miptree maps.
This gets the same performance win as the miptree maps did, and
removes a pile of code duplication.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| e0d67a3a8b4ec73df7e6f818989480a3dd1ee706 |
|
30-Nov-2011 |
Eric Anholt <eric@anholt.net> |
intel: Track miptrees for fake packed depth/stencil renderbuffers.
Right now the fake packed d/s RBs are creating two sub-renderbuffers
with their own storage, and the hardware setup and the mapping code
have been explicitly referencing them. By setting miptrees on them,
we'll be able to make our renderbuffer code for fake packed
depth/stencil more consistent with all our other renderbuffers.
The interesting new behavior here is that there is now a mt with a
non-depthstencil format (X8Z24) that has a stencil_mt field
associated. This looks like it should be safe, and we'll need to be
able to do this for floating point depth/stencil as well.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| b48c3bca87b30003f9e117d299011380e743aec9 |
|
29-Nov-2011 |
Eric Anholt <eric@anholt.net> |
intel: Move separate-stencil s8 mapping logic to intel_miptree_map.
We're going to want to reuse this logic in mapping of fake packed
miptrees wrapping separate depth/stencil miptrees.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 3d798abc818326a377bbbdaac29058ac7b41e1a0 |
|
15-Nov-2011 |
Eric Anholt <eric@anholt.net> |
intel: Improve debug output for begin/finish render texture.
I've never seen a use for the thread ID value, but knowing the format
being rendered is kind of a big deal.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 05ab8fc13461aa9d6612d75c899dac20de067da6 |
|
15-Nov-2011 |
Eric Anholt <eric@anholt.net> |
intel: Remove duplicate test for texture attachment completeness.
We are already testing this if appropriate in
intel_validate_framebuffer (FBO completeness), so no need to avoid
attaching the texture to the renderbuffer here.
This causes MESA_FORMAT_R11_G11_B10_FLOAT to now be renderable as a texture
attachment on i965.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 925356c8c0b21998a1f53f042269818c19163385 |
|
15-Nov-2011 |
Eric Anholt <eric@anholt.net> |
i965: Don't require spans (swrast) support to consider a format FBO complete.
We don't want to go writing GetRow/PutRow for every format required by
GL 3.0, when it's very hard to get those functions called, and in
every case we want to make swrast do direct mapping through
MapRenderbuffer anyway.
This causes MESA_FORMAT_R11_G11_B10_FLOAT to be considered complete on gen6.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 6661b7596f3b26a773ccde79f018179713b6b6e0 |
|
15-Nov-2011 |
Eric Anholt <eric@anholt.net> |
intel: Add the context to the render_target_supported() vtbl method.
We're going to want to provide different answers per chipset
generation.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| b18875d441ca4b7b1a4098659fb4298a4bf265f6 |
|
17-Nov-2011 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Use separate stencil whenever possible
For depthstencil renderbuffers, we were using separate stencil only if the
hardware required it. Since the performance gains from HiZ is so high, we
should always use separate stencil if the hardware supports it.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 293e9a7ccfeb64efd54464658518e4ded054a13c |
|
16-Nov-2011 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Enable HiZ for texture renderbuffers
When a depth texture is first attached to framebuffer, allocate a HiZ
miptree for it.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| b264698d30d3c789bbe1fc64fd72c731f342877a |
|
16-Nov-2011 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Resolve buffers in intel_map_renderbuffer()
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 1383e56bd916f9fc4357a6224aac4e8c691303cb |
|
17-Nov-2011 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Add resolve functions for renderbuffers
Add the following functions:
intel_renderbuffer_resolve_hiz
intel_renderbuffer_resolve_depth
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| a2e44b0813e956440c451c107cf5564b56cbe98e |
|
17-Nov-2011 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Replace intel_mipmap_tree::hiz_region with a miptree [v2]
This is required to correctly implement HiZ for mipmapped and
multi-layered textures.
v2: Accomodate refcount fixes in intel_process_dri2_buffer_*() that were
introduced in v2 of commit
intel: Replace intel_renderbuffer::region with a miptree [v2]
Reviewed-by: Eric Anholt <eric@anholt>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 3eb12dfaeed03f77e31943eea164acb03e86bbc9 |
|
16-Nov-2011 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Replace intel_texture_image::stencil_irb with intel_mipmap_tree::stencil_mt [v3]
For depthstencil textures using separate stencil, we embedded a stencil
buffer in intel_texture_image. The intention was that the embedded stencil
buffer would be the golden copy of the texture's stencil bits. When
necessary, we scattered/gathered the stencil bits between the texture
miptree and the embedded stencil buffer.
This approach had a serious deficiency for mipmapped or multi-layer
textures. Any given moment the embedded stencil buffer was consistent with
exactly one miptree slice, the most recent one to be scattered. This
permitted tests of type A to pass, but broke tests of type B.
Test A:
1. Create a depthstencil texture.
2. Upload data into (level=x1,layer=y1).
3. Read and test stencil data at (level=x1, layer=y1).
4. Upload data into (level=x2,layer=y2).
5. Read and test stencil data at (level=x2, layer=y2).
Test B:
1. Create a depthstencil texture.
2. Upload data into (level=x1,layer=y1).
3. Upload data into (level=x2,layer=y2).
4. Read and test stencil data at (level=x1, layer=y1).
5. Read and test stencil data at (level=x2, layer=y2).
v2:
Only allocate stencil miptree if intel->must_use_separate_stencil,
because we don't make the conversion from must_use_separate_stencil to
has_separate_stencil until commit
intel: Use separate stencil whenever possible
v3:
Don't call ChooseNewTexture in intel_renderbuffer_wrap_miptree() in
order to determine the renderbuffer format. Instead, pass the format as
a param to that function.
CC: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| c80b31fdee1fa96b8d45ad2537ecdb5b9151973e |
|
16-Nov-2011 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Refactor intel_render_texture() [v2]
This is in preparation for properly implementing glFramebufferTexture*()
for mipmapped depthstencil textures. The FIXME comments deleted by this
patch give a rough explanation of what was broken.
This refactor does the following:
- In intel_update_wrapper() and intel_wrap_texture(), change the
parameters to prepare to remove functions' dependency on
gl_texture_image.
- Move the call to intel_renderbuffer_set_draw_offsets() from
intel_render_texture() into intel_udpate_wrapper().
Each time I encounter those functions, I dislike their vague names.
(Update which wrapper? What is wrapped? What is the wrapper?). So, while
I was mucking around, I also renamed the functions.
v2:
In addition to the ``GLenum internal_format`` parameter to
intel_wrap_miptree(), add a ``gl_format format`` parameter. This
removes the need to recalculate for the true format from
internal_format with ChooseNewTextureFormat, which was just weird.
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 3b38b33c1648b07e75dc4d8340758171e109c598 |
|
15-Nov-2011 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Remove unneeded params from intel_renderbuffer_set_draw_offset()
Since the renderbuffer tracks the miptree level and layer that it wraps,
the 'tex_image' and 'zoffset' params are no longer needed to calculate the draw
offsets.
Not only are they no longer needed, but their presence would prevent
calculating the renderbuffer draw offsets in situations where there were
no texture image. Such situations will occur during the HiZ meta-op and
during scatter/gather of separate stencil textures.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 24da7335b22432ef4c2d57cab86e4b8fbe8733d5 |
|
15-Nov-2011 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Track the miptree layer wrapped by a renderbuffer [v2]
TODO: Make v2 for kwg.
Add two fields to intel_renderbuffer:
mt_level
mt_layer
Multiple renderbuffers may simultaneously wrap a single texture and each
provide a different view into that texture. [Consider
glFramebufferTextureLayer()]. The new fields indicate which slice of the
miptree is wrapped by the renderbuffer.
The buffer resolve operations, to be introduced in the future, require
these fields in order to resolve the correct slice in the miptree.
To add the fields, it was necessary to replace the type of some function
parameters from gl_texture_image to gl_renderbuffer_attachment.
v2: [kwg] Replace confusing condition `CubeMapFace > 0` with the more
sensible `Target == GL_TEXTURE_CUBE_MAP`.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| da2816a45e6e3a33246a341fee72e6f893f315d9 |
|
16-Nov-2011 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Replace intel_renderbuffer::region with a miptree [v3]
Essentially, this patch just globally substitutes `irb->region` with
`irb->mt->region` and then does some minor cleanups to avoid segfaults
and other problems.
This is in preparation for
1. Fixing scatter/gather for mipmapped separate stencil textures.
2. Supporting HiZ for mipmapped depth textures.
As a nice benefit, this lays down some preliminary groundwork for easily
texturing from any renderbuffer, even those of the window system.
A future commit will replace intel_mipmap_tree::hiz_region with a miptree.
v2:
- Return early in intel_process_dri2_buffer_*() if region allocation
fails.
- Fix double semicolon.
- Fix miptree reference leaks in the following functions:
intel_process_dri2_buffer_with_separate_stencil()
intel_image_target_renderbuffer_storage()
v3:
- [anholt] Fix check for hiz allocation failure. Replace
``if (!irb->mt)` with ``if(!irb->mt->hiz_region)``.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| c3c7cbd15418293208034e8970d626b5998abd4b |
|
14-Nov-2011 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Move inline functions from intel_fbo.h to .c
Move the following inline functions:
intel_get_rb_region
intel_framebuffer_has_hiz
A future commit will replace the renderbuffer's region with a miptree.
This small refactor will eliminate the need for intel_fbo.h to include
intel_mipmap_tree.h on that commit. I'd like to avoid the situation where
each header transitively includes every other header.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 7e9b3c098c58af49a809afbc17d508f23eab21c2 |
|
14-Nov-2011 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Temporarily disable HiZ for textures
A great refactor thrashing begins after this commit for HiZ and separate
stencil. Removing code for texture HiZ will make that refactoring easier,
because then we don't have to maintain that code during the refactor.
To disable HiZ for textures, I've removed the hook in
intel_update_wrapper() that allocates a HiZ buffer when attaching a depth
texture to a framebuffer.
HiZ was broken for textures anyway, so there's no regression here.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 190aec75a4362b56b9b311975a777c56e8e6c67d |
|
17-Nov-2011 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Always gather stencil buffer in intel_map_renderbuffer_separate_s8z24()
The function gathered the stencil buffer into the depth buffer only when
the map mode contained the read bit. But we must do the gather even if the
map mode is write-only. If we do not, then, when the depth buffer's stencil
bits are scattered into the stencil buffer by intel_unmap_renderbuffer(),
some of the scattered stencil bits would be invalid.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| dc4c3a31c64aae2c3d76ccbd5bf54d04a1d5d041 |
|
15-Nov-2011 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Simplify stencil detiling arithmetic
When calculating the y offset needed for detiling window system stencil
buffers, replace the term
region->height * 2 + region->height % 2 - 1
with
rb->Height - 1 .
The two terms are incidentally equivalent due to some out-of-date,
incorrect code in the Intel DRI2 glue for DDX. (See
intel_process_dri2_buffer_with_separate_stencil(), line ``buffer_height /=
2;``).
Note: This is a candidate for the 7.11 branch (only the intel_span.c hunk).
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| cc502aa9419a6fb127b264dbb131c786281cb8c7 |
|
14-Nov-2011 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Fix intel_map_renderbuffer() for depthstencil buffers with separate stencil
For a depthstencil buffer with separate stencil,
intel_renderbuffer::region is null. (The regions are kept in hidden depth
and stencil buffers). Since the region is null, intel_map_renderbuffer()
assumed there was no data and returned a null map pointer, which in turn
was dereferenced (!) by MapRenderbuffer's caller.
This patch fixes intel_map_renderbuffer() to map the hidden depth buffer
through the GTT and return that as the mapped pointer. Also, the stencil
bits are scattered and gathered when needed.
Fixes the following Piglit tests on gen7:
fbo/fbo-readpixels-depth-formats
hiz/hiz-depth-read-fbo-d24s8
hiz/hiz-stencil-read-fbo-d24s8
EXT_packed_depth_stencil/fbo-clear-formats
EXT_packed_depth_stencil/fbo-depth-GL_DEPTH24_STENCIL8-blit
EXT_packed_depth_stencil/fbo-depth-GL_DEPTH24_STENCIL8-drawpixels
EXT_packed_depth_stencil/fbo-depth-GL_DEPTH24_STENCIL8-readpixels
EXT_packed_depth_stencil/fbo-depthstencil-GL_DEPTH24_STENCIL8-readpixels-24_8
EXT_packed_depth_stencil/fbo-depthstencil-GL_DEPTH24_STENCIL8-readpixels-FLOAT-and-USHORT
EXT_packed_depth_stencil/fbo-stencil-GL_DEPTH24_STENCIL8-readpixels
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 5365ba19db8e9d714604bb63f037800ba2ff2f4d |
|
11-Nov-2011 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Fix software detiling of system stencil buffers
If a window system stencil buffer had a region with odd height, then the
calculated y offset needed for software detiling was off by one. The bug
existed in intel_{map,unmap}_renderbuffer_s8() and in the intel_span.c
accessors.
Fixes the following Piglit tests on gen7:
general/depthstencil-default_fb-readpixels-24_8
general/depthstencil-default_fb-readpixels-FLOAT-and-USHORT
Fixes SIGABRT in the following Piglit tests on gen7:
general/depthstencil-default_fb-blit
general/depthstencil-default_fb-copypixels
general/depthstencil-default_fb-drawpixels-24_8
general/depthstencil-default_fb-drawpixels-FLOAT-and-USHORT
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 87d6b359745b6b2c94d1c852ce27e2879d4bec56 |
|
10-Nov-2011 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Fix intel_unmap_renderbuffer_s8()
When gathering the temporary buffer's pixles into the gem buffer, we had
the two buffers juxtaposed. Oops.
Fixes the following Piglit tests on gen7:
general/GL_SELECT - alpha-test enabled
general/GL_SELECT - depth-test enabled
general/GL_SELECT - no test function
general/GL_SELECT - scissor-test enabled
general/GL_SELECT - stencil-test enabled
Fixes SIGABRT in Piglit tests EXT_framebuffer_object/fbo-stencil-* on
gen7.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| f911cac7a7a8ebcad711587200c7f66ab61d1ccf |
|
09-Nov-2011 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Refactor intel_map_renderbuffer()
The function already implements 3 cases (map through GTT, blit to
a temporary, and detile stencil buffer to temporary), and a 4th will be
added soon: scatter/gather for depthstencil buffers using separate
stencil. For sanity's sake, this factors each case out into its own
function.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| eab201bad4d4f250ca9318a228d1c71561daee1a |
|
19-Oct-2011 |
Eric Anholt <eric@anholt.net> |
i965/gen6: Improve glReadPixels() performance by blitting to a linear temp.
The readpixels microbenchmark in mesa-demos goes from 47Mpix/sec at
1000x1000 to 450Mpix/sec. The 10x10 sizes stay about the same.
Reviewed-by: Brian Paul <brianp@vmware.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 92054cd94e2188c9f4d56ddf9377c5aeb8a4e64e |
|
11-Oct-2011 |
Eric Anholt <eric@anholt.net> |
intel: Add an implementation of MapRenderbuffer.
v2: Add separate stencil S8 W-tile swizzling/deswizzling. Tested for
the swizzling case with env INTEL_SEPARATE_STENCIL=1 INTEL_HIZ=1
./bin/hiz-depth-stencil-test-fbo-d24-s8
v3: Apply Chad's fix for S8 window system buffers.
Reviewed-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 6b341662b3bbde7e86b3b9184266412da1b27977 |
|
01-Nov-2011 |
Eric Anholt <eric@anholt.net> |
intel: Improve the debug info for renderbuffer allocation.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 2e5a1a254ed81b1d3efa6064f48183eefac784d0 |
|
07-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
intel: Convert from GLboolean to 'bool' from stdbool.h.
I initially produced the patch using this bash command:
for file in {intel,i915,i965}/*.{c,cpp,h}; do [ ! -h $file ] && sed -i
's/GLboolean/bool/g' $file && sed -i 's/GL_TRUE/true/g' $file && sed -i
's/GL_FALSE/false/g' $file; done
Then I manually added #include <stdbool.h> to fix compilation errors,
and converted a few functions back to GLboolean that were used in core
Mesa's function pointer table to avoid "incompatible pointer" warnings.
Finally, I cleaned up some whitespace issues introduced by the change.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chad Versace <chad@chad-versace.us>
Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| fd99cd0e10849205749aad580fea8c970fb46a31 |
|
29-Sep-2011 |
Eric Anholt <eric@anholt.net> |
intel: Add a helper function for getting miptree size from a texture image.
With 1D array textures, we no longer agree between the GL information
about width/height/depth of a texture and how we lay out a miptree.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| b07c78bfe94c17e6fccba70923b03a29c751fde1 |
|
29-Sep-2011 |
Eric Anholt <eric@anholt.net> |
intel: Consolidate texture validation copy code, and reuse it correctly.
The path for ->Data was failing to be called for the FBO draw offset
fallback, and also had mismatched compressed texture support code.
This drops the intel_prepare_render() in the blit path. We aren't
copying to/from a GL_FRONT buffer, so it doesn't matter.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| db3ada6055814a4bd5aa95fc9505fc101864391d |
|
22-Sep-2011 |
Eric Anholt <eric@anholt.net> |
intel: Drop the "intel" argument to intel_miptree_release().
We don't have it in the other refcounting functions, and it was
totally unused.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 19cfe1e035fdaf03b7a3560c47f1b8d59a221902 |
|
21-Sep-2011 |
Eric Anholt <eric@anholt.net> |
intel: Drop some extra equality checks on reference/release functions.
_mesa_reference_renderbuffer already short-circuits equality, and
intel_miptree_release does nothing on NULL.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| fa2c886863492cc3eeee6d2059ae24edc1cb2bff |
|
17-Sep-2011 |
Brian Paul <brianp@vmware.com> |
intel: make intel_texture_image a subclass of swrast_texture_image
We need to subclass swrast_texture_image because if we use swrast for
fallback rendering, we'll need to have swrast_texture_image objects.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| bd817215c893cda4f23cb0ad207478ad3935e65c |
|
26-Aug-2011 |
Ian Romanick <ian.d.romanick@intel.com> |
intel: Silence "warning: unused parameter ‘target’"
The GLenum target parameter was not used in intel_copy_texsubimage, so
remove it. Also remove the GLenum internalFormat parameter. Each
caller just copied this out of the intel_texture_image that is already
passed to intel_copy_texsubimage.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 17fa6772d7e223f940dd8ec4e4f6cf8cab9a03c7 |
|
26-Aug-2011 |
Ian Romanick <ian.d.romanick@intel.com> |
intel: Silence "warning: unused parameter ‘fb’"
The gl_framebuffer was not used in intel_draw_buffer, so remove it.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 9fe197c62611815ebe74248033271ad9fd07ae06 |
|
21-Aug-2011 |
Chia-I Wu <olv@lunarg.com> |
intel: add support for __DRI_IMAGE_FORMAT_ABGR8888
It maps to MESA_FORMAT_RGBA8888_REV. Surfaces of the format can only be
sampled from but not render to.
Only i915 is tested.
Reviewed-by: Eric Anholt <eric@anholt.net>
[olv: add a check in intel_image_target_renderbuffer_storage]
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 7dae1aaf142999e3cfeafb13d30abda667d66d87 |
|
15-Jul-2011 |
Brian Paul <brianp@vmware.com> |
intel: use new gl_texture_image:Face, Level fields
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 0f1aae3ae7cef051f87dae056c46fcfd0afaab20 |
|
02-Aug-2011 |
Eric Anholt <eric@anholt.net> |
intel: Fix unused variable warning.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| f73caddd3339d284556036d031ab30ce8057a510 |
|
26-Jul-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Remove the now unused intel_renderbuffer::draw_offset field.
The previous commit removed the last use of this field.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 15c0bc5eefc89bec537e412c02965f201fb1c011 |
|
26-Jul-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Check actual tile offsets in Gen4 miptree workaround.
The purpose of the (irb->draw_offset & 4095) != 0 check was to ensure
that we don't have XYy offsets into a tile, since Gen4 hardware doesn't
support that. However, it's insufficient: there are cases where
draw_offset & 4095 is 0 but we still have a Y-offset. This leads to an
assertion failure in brw_update_renderbuffer_surface with tile_y != 0.
Instead, simply call intel_renderbuffer_tile_offsets to compute the
actual X/Y offsets and check if either are non-zero. This makes both
the workaround and the assertion check the same things.
Fixes piglit test fbo-generatemipmap-formats, and should also fix
bugs #34009 and #39487.
NOTE: This is a candidate for stable release branches.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34009
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=39487
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Chad Versace <chad@chad-versace.us>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| f7dbcba280e4397cadb14f230aa925b4143cdde4 |
|
18-Jul-2011 |
Chad Versace <chad@chad-versace.us> |
intel: Fix stencil buffer to be W tiled
Until now, the stencil buffer was allocated as a Y tiled buffer, because
in several locations the PRM states that it is. However, it is actually
W tiled. From the PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section
4.5.2.1 W-Major Format:
W-Major Tile Format is used for separate stencil.
The GTT is incapable of W fencing, so we allocate the stencil buffer with
I915_TILING_NONE and decode the tile's layout in software.
This fix touches the following portions of code:
- In intel_allocate_renderbuffer_storage(), allocate the stencil
buffer with I915_TILING_NONE.
- In intel_verify_dri2_has_hiz(), verify that the stencil buffer is
not tiled.
- In the stencil buffer's span functions, the tile's layout must be
decoded in software.
This commit mutually depends on the xf86-video-intel commit
dri: Do not tile stencil buffer
Author: Chad Versace <chad@chad-versace.us>
Date: Mon Jul 18 00:38:00 2011 -0700
On Gen6 with separate stencil enabled, fixes the following Piglit tests:
bugs/fdo23670-drawpix_stencil
general/stencil-drawpixels
spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX16-copypixels
spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX16-drawpixels
spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX16-readpixels
spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX1-copypixels
spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX1-drawpixels
spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX1-readpixels
spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX4-copypixels
spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX4-drawpixels
spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX4-readpixels
spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX8-copypixels
spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX8-drawpixels
spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX8-readpixels
spec/EXT_packed_depth_stencil/fbo-stencil-GL_DEPTH24_STENCIL8-copypixels
spec/EXT_packed_depth_stencil/fbo-stencil-GL_DEPTH24_STENCIL8-readpixels
spec/EXT_packed_depth_stencil/readpixels-24_8
Note: This is a candidate for the 7.11 branch.
Signed-off-by: Chad Versace <chad@chad-versace.us>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 8cf2741d2b05fd9f41eca35f0f43e6e0684d57f2 |
|
12-Jul-2011 |
Eric Anholt <eric@anholt.net> |
intel: Clarify the depthRb == stencilRb logic.
Reviewed-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 007c2d6cd2f6b206564689ac12a3e51aaae242bc |
|
29-Jun-2011 |
Eric Anholt <eric@anholt.net> |
intel: Remove gratuitous context checks in intel_delete_renderbuffer().
Even if we don't have a current context, if we're freeing the rb we
should free its region (and BO). The renderbuffer unreference checks
appear to be just cargo-cult from the region unreference code.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=30217
Reviewed-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| c7ef5e8498550e6ed4d609641ca6deb932882485 |
|
29-Jun-2011 |
Eric Anholt <eric@anholt.net> |
intel: Remove now trivial intel_renderbuffer_set_{hiz_,}region().
As a result of this cleanup, a bug in
intel_process_dri2_buffer_no_separate_stencil() became quite apparent.
We were associating the NULL pointer after an unreference with the
STENCIL attachment -- clarify the logic and attach the right region.
Reviewed-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| b904321ed018c661271fb1fc3eefd1af0ec61c7f |
|
29-Jun-2011 |
Eric Anholt <eric@anholt.net> |
intel: Rely on intel_region_reference()'s support of *dst != NULL.
Reviewed-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 97f263c229784a55014b32e8b3e420e58f8bc851 |
|
23-Jun-2011 |
Chad Versace <chad@chad-versace.us> |
intel: Change framebuffer validation criteria
Since all infrastructure is now in place to support packed
depth/stencil renderbuffers when using separate stencil, there is no
need for special cases when separate stencil is enabled.
Signed-off-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| e357ae949465d0304adb704df5d860ee678390e7 |
|
23-Jun-2011 |
Chad Versace <chad@chad-versace.us> |
intel: In intel_update_wrapper, support s8z24 textures when using separate stencil
Also, in order to coerce intel_update_tex_wrapper_regions() to
allocate the hiz region, alter intel_update_tex_wrapper_regions() to
examine the renderbuffer format instead of the texture image format.
Signed-off-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| bffae4c9cd7df044cdbeeed1de257d720f1e76ac |
|
23-Jun-2011 |
Chad Versace <chad@chad-versace.us> |
intel: Factor region updates out of intel_update_wrapper
... and into new function intel_update_tex_wrapper_regions.
This prevents code duplication in the next commit.
Also add a note explaining that the hiz region is broken for mipmapped
depth textures.
Signed-off-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 5cd4d8551778e1b371397ad4a1144a1c0b9f436f |
|
22-Jun-2011 |
Chad Versace <chad@chad-versace.us> |
intel: Declare some functions in intel_fbo.c as non-static
... because they will be needed by intel_tex_image_s8z24_create_renderbuffers.
Redeclared functions are:
intel_alloc_renderbuffer_storage
intel_renderbuffer_set_draw_offsets
Signed-off-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 8869a2623775a4879ac310d7073f184b7d45eed1 |
|
21-Jun-2011 |
Chad Versace <chad@chad-versace.us> |
intel: Change signature of intel_create_wrapped_renderbuffer
Redeclare as non-static because
intel_tex_image_s8z24_create_renderbuffers will use it.
Remove the 'wrapper' parameter, because there is no wrapper for
intel_texture_image.depth_rb and stencil_rb.
Signed-off-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 3db27d4a4aee9f311a447778ce94007415f2637f |
|
17-Jun-2011 |
Chad Versace <chad@chad-versace.us> |
intel: Allocate s8_z24 non-texture renderbuffers when using separate stencil
Now all infrastructure is in place to support s8_z24 non-texture
renderbuffers for gen7.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 36e05c6870fc466053b4f54edd890e19d5ac9dcf |
|
15-Jun-2011 |
Chad Versace <chad@chad-versace.us> |
intel: Unobfuscate intel_alloc_renderbuffer_storage
Hiz buffer allocation can only occur if the 'else' branch has been taken,
so move the hiz buffer allocation into the 'else' branch.
Having the hiz buffer allocation dangling outside of the if-tree was just
damn confusing.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 39d0e3632a4ccb10f2ce6578151e854ba52d3c0e |
|
16-Jun-2011 |
Chad Versace <chad@chad-versace.us> |
intel: Add fields to intel_renderbuffer for unwrapping packed depth/stencil buffers
Add the following fields:
intel_renderbuffer.wrapped_depth;
intel_renderbuffer.wrapped_stencil
If the intel_context is using separate stencil and the renderbuffer has
a packed depth/stencil format, then wrapped_depth and wrapped_stencil are
the real renderbuffers.
Alter the following functions to accomodate the wrapped buffers:
intel_delete_renderbuffer
intel_draw_buffer
intel_get_renderbuffer
intel_renderbuffer_map
intel_renderbuffer_unmap
Subsequent commits allocate renderbuffer storage for wrapped_depth and
wrapped_stencil.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| f94fef83db10f0c9327bd3dd43510ad31c94d82a |
|
09-Jun-2011 |
Eric Anholt <eric@anholt.net> |
intel: Drop the cpp argument to intel_miptree_create().
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 6dcc398ac0837025cf60b4d6a056fa3b0a16466f |
|
09-Jun-2011 |
Eric Anholt <eric@anholt.net> |
intel: Calculate compress_byte in intel_miptree_create.
One less argument and thing to get wrong.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 9c5fdbb721147f7304faaa8960f5b64e25a8f673 |
|
09-Jun-2011 |
Eric Anholt <eric@anholt.net> |
intel: Use the gl_format to get the base_format for miptree create.
One less argument to this insanely long function call.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 9a523a48af05118424714f0a34ca3dda6861186a |
|
09-Jun-2011 |
Eric Anholt <eric@anholt.net> |
intel: Drop the internal_format field of the mipmap tree.
This has been replaced with the gl_format now.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| d5809115b568d8b74f47316607dce0730964517a |
|
09-Jun-2011 |
Eric Anholt <eric@anholt.net> |
intel: Add the MESA_FORMAT as a field of the miptree.
We only had internal_format before, which is way more irritating to
work with.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| d29117752f10d9bcb61e7b26064a872017a64ebe |
|
01-Jun-2011 |
Eric Anholt <eric@anholt.net> |
intel: Clean up intel_render_texture with a rename and a helper function.
The "newImage" isn't particularly new -- it might be the same texture
that was attached to the same attachment point before. This function
also gets called when just rebinding back to an FBO with a texture
attachment.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| b17aab5753a6d14c9e757bedb186963b2dae8823 |
|
31-May-2011 |
Eric Anholt <eric@anholt.net> |
intel: Move the draw_x/draw_y to the renderbuffer where it belongs.
It was originally located in the region because the tracking of
depth/color buffers was on the regions, and getting back to the irb
would have been tricky. Now, we're keying off of the renderbuffer in
more places, which means we can move these fields where they belong.
This could fix potential rendering failure with a single texture
having multiple images attached to different renderbuffers across
shareCtx (as far as I can tell, this was the only failure we could
cause, since anything else should trigger intel_render_texture in
between, for example a BindFramebuffer).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 4fa01d705f0b795a5df30127925ced8e0522631f |
|
14-Jun-2011 |
Brian Paul <brianp@vmware.com> |
dri: include swrast.h, not s_texrender.h
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 755f2e2ae597df9208523b0996bbdabf3db463b0 |
|
13-Jun-2011 |
Brian Paul <brianp@vmware.com> |
mesa: move texrender.c to swrast
This stuff is really for software rendering, it's not core Mesa.
A small step toward pushing the FetchTexel() stuff down into swrast.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 84294fe26ca5860c34e6541f633be4d093ab57f2 |
|
31-May-2011 |
Chad Versace <chad@chad-versace.us> |
intel: Add function intel_renderbuffer_set_hiz_region()
It's the analog of intel_renderbuffer_set_region(), but for the hiz region
of course.
CC: Ian Romanick <idr@freedesktop.org>
CC: Kristian Høgsberg <krh@bitplanet.net>
Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| e7bcfadc2255e3417e03676837d248f4976419e2 |
|
23-May-2011 |
Chad Versace <chad@chad-versace.us> |
intel: Change FBO validation criteria to accomodate hiz and seprate stencil
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| c270f1a628a625ccc9f6d931f2921e3d92c31818 |
|
23-May-2011 |
Chad Versace <chad@chad-versace.us> |
intel: Add hiz_region to intel_mipmap_tree
When a texture is attached to multiple FBO's, a separate renderbuffer
wrapper is created for each attachment. This necessitates storing the hiz
region for these renderbuffers in the texture itself instead of the
renderbuffer wrapper.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 6ed829fe5063f61f1ab2fcb39a441e17d89e622c |
|
23-May-2011 |
Chad Versace <chad@chad-versace.us> |
intel: Refactor the wrapping of textures with renderbuffers
Before this commit, the renderbuffer's region was updated in
intel_renderbuffer_texture(). This commit moves the update into
intel_update_wrapper(), which is a more logical location for updates.
This is in preparation for the next commit, which allocates and
updates the texture's hiz region in intel_update_wrapper(). Having the two
region updates located in the same function makes good form.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 7c0e6d9bbc11f7802c81df048eb721b5e15e8ece |
|
23-May-2011 |
Chad Versace <chad@chad-versace.us> |
intel: Add hiz_region to intel_renderbuffer
A hiz surface must be supplied to the hardware when rendering to a depth
buffer with hiz. There are three potential places to store that surface:
1. Allocate a larger intel_region for the depthbuffer, and let the
region's tail be the hiz surface.
2. Allocate a separate intel_region for hiz, and store it as
brw_context state.
3. Allocate a separate intel_region for hiz, and store it in
intel_renderbuffer.
We choose method 3.
Method 1 has not been chosen due to future complications it might cause
when requesting a DRI drawable's depth buffer attachment from X.
Method 2 has not been chosen because storing the hiz region apart from
the depth region makes lazy hiz/depth resolves difficult to implement.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 1a1411e09b23fce9977f7926dba4f1f0c8f3c5ec |
|
23-May-2011 |
Chad Versace <chad@chad-versace.us> |
intel: Allocate region for separate stencil buffer
... in intel_alloc_renderbuffer_storage(). The stencil buffer has quirky
pitch requirements, so its region allocation is a special case.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| cd3568c329cff16333455fa2228a7c27b261cf05 |
|
16-Apr-2011 |
Eric Anholt <eric@anholt.net> |
intel: Use _mesa_base_tex_format for FBO texture attachments.
The _mesa_base_fbo_format variant doesn't handle some texture
internalformats, such as "3".
Fixes:
fbo-blending-formats.
fbo-alphatest-formats
EXT_texture_sRGB/fbo-alphatest-formats
Reviewed-by: Brian Paul <brianp@vmware.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| c0ad70ae31ee5501281b434d56e389fc92b13a3a |
|
05-Feb-2011 |
Neil Roberts <neil@linux.intel.com> |
intel: Try using glCopyTexSubImage2D in _mesa_meta_BlitFramebuffer
In the case where glBlitFramebuffer is being used to copy to a texture
without scaling it is faster if we can use the hardware to do a blit
rather than having to do a texture render. In most of the drivers
glCopyTexSubImage2D will use a blit so this patch makes it check for
when glBlitFramebuffer is doing a simple copy and then divert to
glCopyTexSubImage2D.
This was originally proposed as an extension to the common meta-ops.
However, it was rejected as using the BLT is only advantageous for Intel
hardware.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=33934
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 8d68a90e225d831a395ba788e425cb717eec1f9a |
|
10-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
intel: use pwrite for batch
It's faster. Not only is the memcpy more efficiently performed in the
kernel (making up for the system call overhead), but by not using mmap
we remove the greater overhead of tracking the vma of every batch.
And it means we can read back from the batch buffer without incurring
the cost of a uncached read through the GTT.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| d53c8380bf1ed2897979f67fdb675074169b0465 |
|
12-Jan-2011 |
Eric Anholt <eric@anholt.net> |
i915: Fix compiler warning from sw fallback removal change.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| c0cdae03685056e170c25da7d46aed959176d652 |
|
11-Jan-2011 |
Eric Anholt <eric@anholt.net> |
i965: Use a new miptree to avoid software fallbacks due to drawing offset.
When attaching a small mipmap level to an FBO, the original gen4
didn't have the bits to support rendering to it. Instead of falling
back, just blit it to a new little miptree just for it, and let it get
revalidated into the stack later just like any other new teximage.
Bug #30365.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 45a56e4730a74a012ad712fd9b6013d900b04742 |
|
09-Jan-2011 |
Vinson Lee <vlee@vmware.com> |
intel: Include mfeatures.h in files that perform feature tests.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 29c4f95cbcad29d52bf3b6c875840b38b8823e4c |
|
08-Jan-2011 |
Eric Anholt <eric@anholt.net> |
intel: Make renderbuffer tiling choice match texture tiling choice.
There really shouldn't be any difference between the two for us.
Fixes a bug where Z16 renderbuffers would be untiled on gen6, likely
leading to hangs.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 8f593597fc100b496db368b2b988e1d2ec58b612 |
|
08-Jan-2011 |
Eric Anholt <eric@anholt.net> |
intel: Use the _BaseFormat from MESA_FORMAT_* in renderbuffer setup.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| a7bf7230564ac282cc957207224d16f322fa73d8 |
|
08-Jan-2011 |
Eric Anholt <eric@anholt.net> |
intel: Add a vtbl hook for determining if a format is renderable.
By relying on just intel_span_supports_format, some formats that
aren't supported pre-gen4 were not reporting FBO incomplete. And we
also complained in stderr when it happened on i915 because draw_region
gets called before framebuffer completeness validation.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 5dbb856e960f9448ec4e322f936f5f6763ee77e2 |
|
04-Jan-2011 |
Eric Anholt <eric@anholt.net> |
intel: Merge our choosetexformat fallbacks into core.
We now share the type/format -> MESA_FORMAT_* mappings with software
mesa, and the core supports most of the fallbacks hardware drivers
will want.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| b7b2791c6bea6ad0db76fdad9a217aa1efffea93 |
|
04-Jan-2011 |
Eric Anholt <eric@anholt.net> |
intel: When validating an FBO's combined depth/stencil, use the given FBO.
We were looking at the current draw buffer instead to see whether the
depth/stencil combination matched. So you'd get told your framebuffer
was complete, until you bound it and went to draw and we decided that
it was incomplete.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 0ea49380e20bdf76cd0e434d3d431ca9f526f1f1 |
|
04-Jan-2011 |
Eric Anholt <eric@anholt.net> |
intel: Fix segfaults from trying to use _ColorDrawBuffers in FBO validation.
The _ColorDrawBuffers is a piece of computed state that gets for the
current draw/read buffers at _mesa_update_state time. However, this
function actually gets used for non-current draw/read buffers when
checking if an FBO is complete from the driver's perspective. So,
instead of trying to just look at the attachment points that are
currently referenced by glDrawBuffers, look at all attachment points
to see if they're driver-supported formats. This appears to actually
be more in line with the intent of the spec, too.
Fixes a segfault in my upcoming fbo-clear-formats piglit test, and
hopefully bug #30278
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 8b9570e685f010745e2dfb1bff00d555e2e5f6ba |
|
21-Dec-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
intel: Check for unsupported texture when finishing using as a render target
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=32541
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| be72efb4f29180fdaf0935f8739f230fe5ea6317 |
|
10-Dec-2010 |
Eric Anholt <eric@anholt.net> |
intel: Just use ChooseTextureFormat for renderbuffer format choice.
One less place to forget to put your new MESA_FORMAT support in.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| e339b669a14f37698b842c0c51c1f5e4001ef12f |
|
10-Dec-2010 |
Eric Anholt <eric@anholt.net> |
intel: Add a couple of helper functions to reduce rb code duplication.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 78a340fd487c56468ace7347a53f95a0c751c419 |
|
24-Nov-2010 |
Ian Romanick <ian.d.romanick@intel.com> |
i915: Disallow alpha, red, RG, and sRGB as render targets
Fixes bugzilla #31832
NOTE: This is a candidate for the 7.9 branch.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| f9995b30756140724f41daf963fa06167912be7f |
|
12-Oct-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
Drop GLcontext typedef and use struct gl_context instead
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| c77cd9ec10f7c6ad2927740e15900591d1ff388a |
|
20-Nov-2009 |
Ian Romanick <ian.d.romanick@intel.com> |
i965: Enable GL_ARB_texture_rg
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 72b368ae69bc037681ab4e458296c07cb04349be |
|
30-Sep-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
i965: always set tiling for fbo depth buffer on sandybridge
Sandybridge requires depth buffer must be tiling.
Fix 'fbo_firecube' demo.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 934fde4f5a63ff7c3c29c21e9e67cce3c2564788 |
|
25-Sep-2010 |
Eric Anholt <eric@anholt.net> |
intel: Fix segfault on INTEL_DEBUG=fbo with unsupported framebuffers.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 1946b81e700fbb266294b8c1cb0d29ced84bf647 |
|
25-Sep-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for rendering to SARGB8 FBOs.
Tested with fbo-generatemipmap-formats GL_EXT_texture_srgb. The test
still fails on SLA8, though.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 836803df794be7a2ae3be0fc047e882d49ab22bb |
|
24-Sep-2010 |
Eric Anholt <eric@anholt.net> |
intel: Corresponding FinishRenderTexture debug to BeginRenderTexture.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 17eace581d25a626a7d75d9d1205d012cbb14a6e |
|
23-Sep-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
dri: Pass the __DRIscreen and the __DRIscreen private back to image lookup
We will typically have a current context when we need to lookup the image,
but the lookup implementation don't need it so drop it.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| bda941e1b895547d680b68eaf28ae2db11e6149f |
|
25-Aug-2010 |
Nick Bowler <nbowler@draconx.ca> |
intel: Merge identical cases in switch statement.
Signed-off-by: Nick Bowler <nbowler@draconx.ca>
Signed-off-by: Brian Paul <brianp@vmware.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 9087ba128089ed0dc00e6eb38f37126fb7557d3b |
|
04-Jun-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
intel: Take an intel_screen pointer in intel_alloc_region_* functions
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 84178547dfaa27ca298ad1755d1ce686036a8550 |
|
17-Jun-2010 |
Vinson Lee <vlee@vmware.com> |
intel: Remove unnecessary headers.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 178414eba402f9087ea505e7ef19f1becdd7a36d |
|
11-Jun-2010 |
Eric Anholt <eric@anholt.net> |
i965: Remove caching of surface state objects.
It turns out that computing a 56 byte key to look up a 20-byte object
out of a hash table was some sort of a bad idea. Whoops.
before:
[ # ] backend test min(s) median(s) stddev. count
[ 0] gl firefox-talos-gfx 37.799 38.203 0.39% 6/6
after:
[ 0] gl firefox-talos-gfx 34.761 34.784 0.17% 5/6
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 638342858894293246400d95a90d153c7f66719a |
|
25-May-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for GL_ALPHA framebuffer objects.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| c4775a27e3aaa2006b98f225387499b79bc609ef |
|
10-May-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
intel: Drop intelFlush()
Now that intel_flush() deosn't use the needs_mi_flush argument, we can
finally drop one of the two flush functions.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| ce914fff0817cb3c25a2d715f8435c6b6d6fbcdd |
|
05-May-2010 |
Eric Anholt <eric@anholt.net> |
i965: When an RB gets a new region, clear the old from the state cache.
This prevents memory usage explosion in blender due to the state cache
hanging on to old fake frontbuffer regions. Sigh at blender still
using frontbuffer rendering.
Bug #24119.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 362c1bf75eb74de5b4655c481b74f79718ed4a34 |
|
17-Mar-2010 |
Eric Anholt <eric@anholt.net> |
intel: Replace mt->pitch with mt->region->pitch.
The pitch is not really an inherent part of the miptree, since it's
not part of any of the layout calculations, and it's dictated by the
libdrm-allocated region pitch now.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| da011faf48155a5c02ebc1fe1fa20a4f54b8c657 |
|
17-Mar-2010 |
Eric Anholt <eric@anholt.net> |
intel: Rely on allocated region pitch for the miptree pitch.
Bug #26966: 945 miptree pitch disagreement with libdrm.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| bb35000b4b6dfe60048b2f5d60bc102c4a7fd791 |
|
05-Mar-2010 |
Eric Anholt <eric@anholt.net> |
intel: Remove non-kernel-exec-fencing support.
Shaves 60k off the driver from removing the broken spans code. This
means we now require 2.6.29, which seems fair given that it's a year
old and we've removed support for non-KMS already in the last release
of 2D.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| af3f1bb26980537522a1586fef3fc3c208b44ebc |
|
02-Mar-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
intel: Set InternalFormat for renderbuffers created from an EGLImage
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 10e79627414bc2bbc72d68ed25fb9999948a294f |
|
12-Feb-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
intel: Implement GL_OES_EGL_image entrypoints
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| b76164dcedad257f37af57358b102e14fdea8381 |
|
20-Feb-2010 |
Vinson Lee <vlee@vmware.com> |
intel: Silence compiler format warnings.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 32f2fd1c5d6088692551c80352b7d6fa35b0cd09 |
|
19-Feb-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
Replace _mesa_malloc, _mesa_calloc and _mesa_free with plain libc versions
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| d282128ff68cc58bc3f5b808031c5fe7325bd69b |
|
02-Jan-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
intel: Remove struct intel_framebuffer
With the vsync fields no longer relevant and by refactoring the code
to no longer use color_rb[0-1] we can just use struct gl_framebuffer
directly.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| a0996447559bd251ef7f089165405fcdefe79cc5 |
|
29-Dec-2009 |
Eric Anholt <eric@anholt.net> |
intel: Fix false positives in checking for non-packed depth/stencil RB.
The wine d3d9 visual.c testcase was tripping over this and failing.
Presumably it's binding a packed depth/stencil texture to both
stencil and depth attachment points, and we make a new renderbuffer
wrapper for each in that case.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 089144e4e525883995d609af5040b2355043945e |
|
29-Dec-2009 |
Eric Anholt <eric@anholt.net> |
intel: Allow binding a stencil but not a depth buffer.
Wine's d3d9 visual.c testcase tries this a lot, so I've added some
piglit tests (fbo-nodepth-test, fbo-nostencil-test, fbo-stencil-only)
and enabled it.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| e4df8d32b510a3f00c12477985818c9d42a0b178 |
|
28-Dec-2009 |
Eric Anholt <eric@anholt.net> |
intel: Improve INTEL_DEBUG=fbo output.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 5727147f894137f194d8efc7adb81b80a9b5acd7 |
|
22-Dec-2009 |
Eric Anholt <eric@anholt.net> |
intel: Remove unused stored values reported by clang.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| cbdeb33209e782f011984a4b93cc0d36f567462e |
|
09-Dec-2009 |
Ian Romanick <ian.d.romanick@intel.com> |
intel: Make RGB renderbuffers use XRGB8888 like we do for RGB system buffers.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 430876cd3a70d3b701d136b825518140888f96c8 |
|
09-Dec-2009 |
Ian Romanick <ian.d.romanick@intel.com> |
intel: name in intel_create_renderbuffer was always 0, remove
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 0f01674a584ea6df96acf91d7cd3b8a9b48ee65e |
|
09-Dec-2009 |
Ian Romanick <ian.d.romanick@intel.com> |
intel: Use texformat accessor to get bytes-per-pixel
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 4eee46efcb7e1f737b7115caf48ddb3b77408626 |
|
09-Dec-2009 |
Ian Romanick <ian.d.romanick@intel.com> |
intel: softwareBuffer in intel_alloc_renderbuffer_storage was always false, remove
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 3078bd136d6ee1d9ad16b4c834cad23b005304a4 |
|
08-Dec-2009 |
Ian Romanick <ian.d.romanick@intel.com> |
intel: Axe intel_renderbuffer::texformat
Since the texformat branch merge, the value of intel_renderbuffer::texformat
is just a copy of gl_renderbuffer::Format.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 539a14a1dd5a0d277b193d9cd2d06423ed98dc8a |
|
09-Dec-2009 |
Eric Anholt <eric@anholt.net> |
intel: Flush the render/texture cache when finishing render to texture.
Back when we were flushing the entire batch at BindFramebuffer, the kernel
would notice the domain transition when someone went to texture from it and
flush for us. We no longer do the batch flushing every time, so we get to
do aggressive flushing until we move batchbuffer handling to libdrm.
Fixes piglit fbo-flushing. Bug #25377. No noticeable performance loss
on cairo-gl (so this is better than batch flushing).
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| bb64c9bcdf9962c4f74d71f49307de1da4c3392b |
|
08-Dec-2009 |
Ian Romanick <ian.d.romanick@intel.com> |
Revert "intel: Make RGB renderbuffers use XRGB8888 like we do for RGB system buffers."
This reverts commit 4598942b1b88a2a7d5af7febae7e79eedf00e385.
XRGB8888 doesn't work as intended. Revert this for now, and we'll revisit it
for 7.8 or something.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 4598942b1b88a2a7d5af7febae7e79eedf00e385 |
|
02-Dec-2009 |
Eric Anholt <eric@anholt.net> |
intel: Make RGB renderbuffers use XRGB8888 like we do for RGB system buffers.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 75bdbdd90b15c8704d87ca195a364ff6a42edbb1 |
|
04-Nov-2009 |
Eric Anholt <eric@anholt.net> |
intel: Don't validate in a texture image used as a render target.
Otherwise, we could lose track of rendering to that image, which could
easily happen during mipmap generation.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 409469fb70682cd819ab405e0f92a4659381cfbe |
|
30-Oct-2009 |
Brian Paul <brianp@vmware.com> |
intel: fix up some XRGB breakage
We weren't choosing the right XRGB span functions for reading the
framebuffer. XRGB formats still aren't turned on yet though.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 4a253431abf43a0638afb43605b44a8742b72a60 |
|
30-Oct-2009 |
Brian Paul <brianp@vmware.com> |
intel: update intel_create_renderbuffer(format), add XRGB support
Pass a gl_format to intel_create_renderbuffer() instead of GLenum.
Add cases for MESA_FORMAT_XRGB8888 textures and renderbuffers.
However, we don't yet create any renderbuffers or textures with that
format. It seems the default alpha value is zero instead of one.
Need to investigate that first.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 1f196b786d6bd0c6a5dbdc638574ff716cc3d4de |
|
29-Oct-2009 |
Brian Paul <brianp@vmware.com> |
Merge branch 'texformat-rework'
Conflicts:
src/mesa/drivers/dri/radeon/radeon_fbo.c
src/mesa/drivers/dri/s3v/s3v_tex.c
src/mesa/drivers/dri/s3v/s3v_xmesa.c
src/mesa/drivers/dri/trident/trident_context.c
src/mesa/main/debug.c
src/mesa/main/mipmap.c
src/mesa/main/texformat.c
src/mesa/main/texgetimage.c
|
| 0ea575d721821262a862ceef010db9b1a8b4a6d9 |
|
29-Oct-2009 |
Brian Paul <brianp@vmware.com> |
Merge branch 'mesa_7_6_branch'
|
| c0a61c8442af3cfa810098d34bf6a21d11a5d720 |
|
28-Oct-2009 |
Vinson Lee <vlee@vmware.com> |
intel: Fix memory leak in case of renderbuffer bad format
Signed-off-by: Brian Paul <brianp@vmware.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 49d402e275cdaf46de8db5a475dfe00509141195 |
|
23-Oct-2009 |
Eric Anholt <eric@anholt.net> |
Merge remote branch 'origin/mesa_7_6_branch'
Conflicts:
src/mesa/drivers/dri/intel/intel_fbo.c
src/mesa/drivers/dri/intel/intel_mipmap_tree.c
src/mesa/drivers/dri/intel/intel_mipmap_tree.h
src/mesa/drivers/dri/intel/intel_tex_copy.c
src/mesa/drivers/dri/intel/intel_tex_image.c
|
| 2d17dbfb5346b6d75e87c839148cbe125bf5cd6d |
|
09-Jul-2009 |
Eric Anholt <eric@anholt.net> |
intel: Keep track of x,y offsets in miptrees and use them for blitting.
By just using offsets, we confused the hardware's tiling calculations,
resulting in failures in miptree validation and blit clears.
Fixes piglit fbo-clearmipmap.
Bug #23552. (automatic mipmap generation)
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 68d94a608a6d46156a567b8f0e011ac58054975e |
|
22-Oct-2009 |
Brian Paul <brianp@vmware.com> |
intel: use MESA_FORMAT_S8_Z24 format and avoid z24s8/s8z24 conversions
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| e6594a22f298833eeb6881795b24d03d2fd8e898 |
|
13-Oct-2009 |
Brian Paul <brianp@vmware.com> |
intel: pass zslice to intel_miptree_image_offset()
This lets us get rid of intel_miptree_depth_offsets() and simplify all
of the calling code.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 45e76d2665b38ba3787548310efc59e969124c01 |
|
09-Oct-2009 |
Brian Paul <brianp@vmware.com> |
mesa: remove a bunch of gl_renderbuffer fields
_ActualFormat is replaced by Format (MESA_FORMAT_x).
ColorEncoding, ComponentType, RedBits, GreenBits, BlueBits, etc. are
all replaced by MESA_FORMAT_x queries.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 3e34a2a2b97e7c93955deedb7c12b73bccd6662d |
|
06-Oct-2009 |
Brian Paul <brianp@vmware.com> |
drivers: don't include texformat.h
And remove other unneeded #includes while we're at it.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 1f7c914ad0beea8a29c1a171c7cd1a12f2efe0fa |
|
01-Oct-2009 |
Brian Paul <brianp@vmware.com> |
mesa: replace gl_texture_format with gl_format
Now gl_texture_image::TexFormat is a simple MESA_FORMAT_x enum.
ctx->Driver.ChooseTexture format also returns a MESA_FORMAT_x.
gl_texture_format will go away next.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| ddffe4546a81216cde4376ee49cbaa021f4d04bb |
|
28-Sep-2009 |
Brian Paul <brianp@vmware.com> |
drivers: use more mesa format functions
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 4de8e2123ebeb50db252b2bb57fb167058fa4683 |
|
20-Sep-2009 |
Brian Paul <brianp@vmware.com> |
mesa: rename functions to be more consistant with rest of mesa
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 8cb389ce354944a69418ca1d402791eef8fbf239 |
|
10-Aug-2009 |
Brian Paul <brianp@vmware.com> |
intel: use new _mesa_meta_blit_framebuffer() function
The previous version of framebuffer blit was a quick hack. The new meta
version works pretty well.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 862488075c5537b0613753b0d14c267527fc6199 |
|
03-Jul-2009 |
Jakob Bornecrantz <jakob@vmware.com> |
Merge branch 'mesa_7_5_branch'
Conflicts:
src/mesa/main/dlist.c
src/mesa/vbo/vbo_save_api.c
|
| 94e1117c9ba259665cd8e790369dcd4c789a2f93 |
|
03-Jul-2009 |
Michel Dänzer <daenzer@vmware.com> |
intel: Also update stencil bits in intel_update_wrapper().
Fixes assertion failure when binding depth/stencil texture to FBO stencil
attachment.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 1ba96651e12b3c74fb9c8f5a61b183ef36a27b1e |
|
03-Jun-2009 |
Eric Anholt <eric@anholt.net> |
intel: Add support for tiled textures.
This is about a 30% performance win in OA with high settings on my GM45,
and experiments with 915GM indicate that it'll be around a 20% win there.
Currently, 915-class hardware is seriously hurt by the fact that we use
fence regs to control the tiling even for 3D instructions that could live
without them, so we spend a bunch of time waiting on previous rendering in
order to pull fences off. Thus, the texture_tiling driconf option defaults
off there for now.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| e78a6aa2b94683faa8d43a39aa68d806b14f8833 |
|
20-May-2009 |
Eric Anholt <eric@anholt.net> |
intel: Fall back on any rendering to texture with no miptree.
Fixes segfault on an fbo.c negative test for FBO with texture width/height
of 0. Previously we just tested for border != 0 to work around this
segfault.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 8bba183b9eeb162661a287bf2e118c6dd419dd24 |
|
20-May-2009 |
Eric Anholt <eric@anholt.net> |
intel: Mark the FBO as incomplete if there's no intel_renderbuffer for it.
This happens to rendering with textures with a border, which had resulted
in a segfault on dereferencing the irb.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 2c30fd84dfa052949a117c78d932b58c1f88b446 |
|
10-Apr-2009 |
Eric Anholt <eric@anholt.net> |
intel: Add support for argb1555, argb4444 FBOs and fix rgb565 fbo readpixels.
Also enable them all regardless of screen bpp, as 32 bpp what I've been
testing against, and haven't been able to detect any screen bpp-specific
troubles with them.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| ee41bb2ed01b9480e5370d67257334b81ec0c90e |
|
06-Mar-2009 |
Brian Paul <brianp@vmware.com> |
i965: fix screen depth test in intel_validate_framebuffer)_
front_region may be null.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 4f8ed56d168e9175e76bc42d8b924c7bcaa59dea |
|
27-Feb-2009 |
Brian Paul <brianp@vmware.com> |
intel: no-op the intel_finish_render_texture() function
It doesn't have to do anything. See comments for more details.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| f77b720cde981d441e482bbbd68115634b3041ce |
|
27-Feb-2009 |
Brian Paul <brianp@vmware.com> |
intel: check texture formats in intel_validate_framebuffer()
We can't render into any texture format; only certain formats.
Check that render-to-texture's format is renderable in the
intel_validate_framebuffer()
There seems to be a bug somewhere that causes rendering to rgb565 textures
to be corrupted so disallow that for now. This will be revisted.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 119f34e2a52d7e074ea51d49acf6c11d83142ccc |
|
26-Feb-2009 |
Eric Anholt <eric@anholt.net> |
intel: Fix up x8r8g8b8 renderbuffer format so that alpha=1 spans code happens.
I was lured into a false sense of security by the fact that the spans code was
already there, and a bunch of tests didn't catch the problem. oglconform's
mask.c did, though.
Bug #19970.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 40dd024be618d805b3744e15d25e115018641324 |
|
18-Feb-2009 |
Eric Anholt <eric@anholt.net> |
intel: tell libdrm whether we want a cpu-ready or gpu-ready BO for regions.
This lets us avoid allocing new buffers for renderbuffers, finalized miptrees,
and PBO-uploaded textures when there's an unreferenced but still active one
cached, while also avoiding CPU waits for batchbuffers and CPU-uploaded
textures. The size of BOs allocated for a desktop running current GL
cairogears on i915 is cut in half with this.
Note that this means we require libdrm 2.4.5.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| bd944ef78397fd96dc2b239f542066643b06274a |
|
29-Jan-2009 |
Brian Paul <brianp@vmware.com> |
intel: remove unused RenderToTexture field
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| d332a74e772eb60cf3cef33cafad997436fd9e93 |
|
29-Jan-2009 |
Brian Paul <brianp@vmware.com> |
intel: remove unused #includes
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 5c38801f8e36fdb4a16ed33c26454b98f3519465 |
|
29-Jan-2009 |
Brian Paul <brianp@vmware.com> |
intel: formatting clean-ups
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 65d39a9eed9ae60944dd3c5db392a382c5946cbc |
|
27-Jan-2009 |
Eric Anholt <eric@anholt.net> |
intel: clean up more pf mess.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 6d2e1f6a2cd25107ad9bd88b1decd05fc8000f78 |
|
22-Jan-2009 |
Brian Paul <brianp@vmware.com> |
intel: add GL_EXT_framebuffer blit extension
This functionality is required by GL_ARB_framebuffer_object.
For now, implement it in terms of glCopyPixels(). This will need to be
revisted though.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| f8a7e497acf17cfdefe401815c7063aaf39d4200 |
|
22-Jan-2009 |
Brian Paul <brianp@vmware.com> |
intel: remove/disable the "paired depth/stencil" code
We only allow combined depth+stencil renderbuffers so the complicated code
for splitting and combining separate depth and stencil buffers is no longer
needed.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 3abf67c6b1e1510427fc608983fdeaec88f6077c |
|
22-Jan-2009 |
Brian Paul <brianp@vmware.com> |
intel: remove unneeded call to ctx->Driver.DepthRange()
The preceeding call to intel_draw_buffer() does that.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 71b78149bdb3d0d92b004aed29edcf9ea1a440a8 |
|
22-Jan-2009 |
Brian Paul <brianp@vmware.com> |
i965: disallow separate depth/stencil renderbuffers
Take advantage of the GL_FRAMEBUFFER_UNSUPPORTED feature to disallow separate
depth and stencil renderbuffers; only allow combined depth/stencil buffers.
Next up: remove/simplify a bunch of the depth/stencil renderbuffer code.
Also: restore the previously disabled GL_DEPTH_COMPONENT16 case
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 3c98d3cf32e1828b116173f97dc6d4d4a609951c |
|
20-Jan-2009 |
Brian Paul <brianp@vmware.com> |
intel: plug in stub intel_validate_framebuffer() function
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| f8b00806d8263f2ff09f175e0801379c0b9e9b2c |
|
22-Jan-2009 |
Brian Paul <brianp@vmware.com> |
intel: inline some renderbuffer functions
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| b5da7feee03abd7ca52312476bd75d28d1afddf4 |
|
14-Jan-2009 |
Owain G. Ainsworth <oga@openbsd.org> |
Remove intel pageflipping support in its entirety.
It's been broken and deprecated for a while, so it's time to die. This has the
wonderful benefit of cleaning up the code a fair amount; making it marginally
less twisty.
I'm unsure if the for loops in IntelWindowMoved are still needed.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 947d1c5b2a70c0eafa4c408b47607574a2908468 |
|
15-Jan-2009 |
Brian Paul <brianp@vmware.com> |
i965: asst. fixes, work-arounds for FBOs and render to texture
OpenGL allows mixing and matching depth and stencil renderbuffers in
framebuffer objects while the hardware really only supports interleaved
depth/stencil buffers. This makes for some tricky buffer management.
An extra wrinkle is the situation where the user allocates a 16bpp depth
texture or renderbuffer then tries to render to it along with a stencil
buffer. We'd have to promote the 16bpp Z values to 24-bit Z values and
mix in the stencil values to setup the depth/stencil renderbuffer.
There's no support for that now, so always allocate 32bpp depth textures/
renderbuffers for now.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| c7f43543af8a0bf95750eb6d332fdede07d104ea |
|
15-Jan-2009 |
Brian Paul <brianp@vmware.com> |
i965: fix incorrect renderbuffer DataType assignment
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 8b661a5d33604fd3706cb1825236d72ae2949598 |
|
07-Dec-2008 |
Eric Anholt <eric@anholt.net> |
intel: Fall back on rendering to a texture attachment with a border.
Fixes a segfault in oglconform fbo.c test.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| c5945c2d173b77ace00e6fc225097a6afddecfa3 |
|
25-Sep-2008 |
Eric Anholt <eric@anholt.net> |
intel: Fix clears to depth_stencil texture attachments.
Broken by 0adfd1021035e90995a25ec5f20b736e55075d92, showed up as an assertion
failure in a software fallback in the shadowtex demo when we failed to
recognize the texture format.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| ecadb51bbcb972a79f3ed79e65a7986b9396e757 |
|
18-Sep-2008 |
Brian Paul <brian.paul@tungstengraphics.com> |
mesa: added "main/" prefix to includes, remove some -I paths from Makefile.template
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 8db761409dadc2e899d4e7107eff3aa07b07aa11 |
|
13-Sep-2008 |
Eric Anholt <eric@anholt.net> |
intel: Add a width field to regions, and use it for making miptrees in TFP.
Otherwise, we would use the pitch as width of the texture, and compiz would
render the pitch padding on the right hand side.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| f75843a517bd188639e6866db2a7b04de3524e16 |
|
24-Aug-2008 |
Dave Airlie <airlied@linux.ie> |
Revert "Revert "Merge branch 'drm-gem'""
This reverts commit 7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a |
|
24-Aug-2008 |
Dave Airlie <airlied@linux.ie> |
Revert "Merge branch 'drm-gem'"
This reverts commit 53675e5c05c0598b7ea206d5c27dbcae786a2c03.
Conflicts:
src/mesa/drivers/dri/i965/brw_wm_surface_state.c
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 902e401a384a8213d1239aae42bc2b7071ad6bd8 |
|
27-Jul-2008 |
Eric Anholt <eric@anholt.net> |
intel: Don't return a renderbuffer with alpha when just GL_RGB is requested.
Fixes oglconform rbGetterFuncs testcase. The span code for this mode hasn't
actually been tested.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 2e3714380027252ba17a11f23eae851d3f77ab02 |
|
23-Jul-2008 |
Eric Anholt <eric@anholt.net> |
intel: Add a little span cache to spead up readpixels by cutting syscalls.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| d2d5abfaeb46fc7b4d4267a6c9e92420fc9b5334 |
|
23-Jul-2008 |
Eric Anholt <eric@anholt.net> |
intel-gem: Use pread/pwrite for span access.
This will avoid clflushing entire buffers for small acesses, such as those
commonly used by regression tests.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 2e841880cfc1006a2818d4a8bfefd21136dc39a9 |
|
11-Jul-2008 |
Eric Anholt <eric@anholt.net> |
drm-gem: Use new GEM ioctls for tiling state, and support new swizzle modes.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
|
| 19f585a3cf65887e249d630fe43e83e7e7618dfa |
|
02-Jul-2008 |
Eric Anholt <eric@anholt.net> |
intel-gem: Fix Y-tiling span setup.
The boolean that the server gives us for whether the region is tiled was
getting used as the enum for what tiling mode. Instead, guess the correct
tiling in screen setup.
Also, fix the Y-tiling pitch setup. The pitch to the next tile in Y is
32 scanlines, not 8.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
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| 537bbe6dec780f6f85838fe7e6036579c509f8a6 |
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06-May-2008 |
Keith Packard <keithp@keithp.com> |
[intel-GEM] Add tiling support to swrast.
Accessing tiled surfaces without using the fence registers requires that
software deal with the address swizzling itself.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
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| f94d317d7aea8043b179a0ba64308606375500d7 |
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14-Mar-2008 |
Xiang, Haihao <haihao.xiang@intel.com> |
intel: fix abort issue with shadowtex demo when use
DEPTH_STENCIL texture. (bug#14952).
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
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| c741d287ecce1bd95d4e024d60e274abfcfbe22f |
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15-Feb-2008 |
Eric Anholt <eric@anholt.net> |
[intel] Allow attIndex to be negative to avoid defeating the >= 0 check.
Otherwise, we would go wildly out of bounds if passed -1 (no renderbuffer), such
as while doing LOCK_HARDWARE with glDrawBuffer(GL_NONE).
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
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| e131c46b20241737ceba4856dbe01dcca6dd2c03 |
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09-Jan-2008 |
Kristian Høgsberg <krh@temari.boston.redhat.com> |
[intel] Simplify intelCreateBuffer() a bit.
Drop a bunch of unused arguments from intel_create_renderbuffer() and
introduce intel_renderbuffer_set_region() to set the region for
a renderbuffer.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
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| 601a6b872c33bfe3cb4ea03a5a8ba5ebe92dedaf |
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07-Jan-2008 |
Brian <brian.paul@tungstengraphics.com> |
Replace gl_framebuffer's _ColorDrawBufferMask with _ColorDrawBufferIndexes
Each array element is now a BUFFER_x token rather than a BUFFER_BIT_x bitmask.
The number of active color buffers is specified by _NumColorDrawBuffers.
This builds on the previous DrawBuffer changes and will help with drivers
implementing GL_ARB_draw_buffers.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
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| bea6b5fe5aa3138cec8d057766ae48da4aa57dee |
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20-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[965] Enable EXT_framebuffer_object.
To do so, merge the remainnig necessary code from the buffers, blit, span, and
screen code to shared, and replace it with those.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
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| 7c71ef3a3d0cf2620525f468960cdc76a0fb0d33 |
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12-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[intel] Move bufmgr back to context instead of screen, fixing glthreads.
Putting the bufmgr in the screen is not thread-safe since the emit_reloc
changes. It also led to a significant performance hit from pthread usage
for the attempted thread-safety (up to 12% of a cpu spent on refcounting
protection in single-threaded 965). The motivation had been to allow
multi-context bufmgr sharing in classic mode, but it wasn't worth the cost.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
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| 77a5bcaff43df8d54e0e0ef833726e4b41d7eb36 |
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07-Nov-2007 |
Eric Anholt <eric@anholt.net> |
[intel] Move over files that will be shared with 965-fbo work.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_fbo.c
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