/external/clang/test/SemaCXX/ |
H A D | cxx11-call-to-deleted-constructor.cpp | 10 template <class VT, unsigned int ROWS = 0, unsigned int COLS = 0> 14 typedef VT value_type; 18 template <class VT, unsigned int SIZE> using Vector = Matrix<VT, SIZE, 1>; 20 template <class VT> 21 using RGBValue = Vector<VT, 3>; 24 template <class VT> class Matrix<VT, 0, 0> { // expected-note {{passing argument to parameter here}} 26 typedef VT value_type;
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/external/llvm/lib/Target/X86/Utils/ |
H A D | X86ShuffleDecode.h | 39 void DecodeMOVSLDUPMask(MVT VT, SmallVectorImpl<int> &ShuffleMask); 41 void DecodeMOVSHDUPMask(MVT VT, SmallVectorImpl<int> &ShuffleMask); 43 void DecodeMOVDDUPMask(MVT VT, SmallVectorImpl<int> &ShuffleMask); 45 void DecodePSLLDQMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask); 47 void DecodePSRLDQMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask); 49 void DecodePALIGNRMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask); 51 void DecodePSHUFMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask); 53 void DecodePSHUFHWMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask); 58 void DecodePSWAPMask(MVT VT, SmallVectorImpl<int> &ShuffleMask); 60 /// DecodeSHUFPMask - This decodes the shuffle masks for shufp*. VT indicate [all...] |
H A D | X86ShuffleDecode.cpp | 66 void DecodeMOVSLDUPMask(MVT VT, SmallVectorImpl<int> &ShuffleMask) { argument 67 unsigned NumElts = VT.getVectorNumElements(); 74 void DecodeMOVSHDUPMask(MVT VT, SmallVectorImpl<int> &ShuffleMask) { argument 75 unsigned NumElts = VT.getVectorNumElements(); 82 void DecodeMOVDDUPMask(MVT VT, SmallVectorImpl<int> &ShuffleMask) { argument 83 unsigned VectorSizeInBits = VT.getSizeInBits(); 84 unsigned ScalarSizeInBits = VT.getScalarSizeInBits(); 85 unsigned NumElts = VT.getVectorNumElements(); 96 void DecodePSLLDQMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) { argument 97 unsigned VectorSizeInBits = VT 110 DecodePSRLDQMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) argument 125 DecodePALIGNRMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) argument 146 DecodePSHUFMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) argument 163 DecodePSHUFHWMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) argument 179 DecodePSHUFLWMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) argument 195 DecodePSWAPMask(MVT VT, SmallVectorImpl<int> &ShuffleMask) argument 208 DecodeSHUFPMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) argument 230 DecodeUNPCKHMask(MVT VT, SmallVectorImpl<int> &ShuffleMask) argument 250 DecodeUNPCKLMask(MVT VT, SmallVectorImpl<int> &ShuffleMask) argument 270 decodeVSHUF64x2FamilyMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) argument 287 DecodeVPERM2X128Mask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) argument 448 DecodeZeroMoveLowMask(MVT VT, SmallVectorImpl<int> &ShuffleMask) argument 455 DecodeScalarMoveMask(MVT VT, bool IsLoad, SmallVectorImpl<int> &Mask) argument 553 DecodeVPERMVMask(const Constant *C, MVT VT, SmallVectorImpl<int> &ShuffleMask) argument 586 DecodeVPERMV3Mask(const Constant *C, MVT VT, SmallVectorImpl<int> &ShuffleMask) argument [all...] |
/external/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelDAGToDAG.cpp | 1021 EVT VT = N->getValueType(0); local 1036 return CurDAG->getMachineNode(Opc, dl, VT, Ops); 1043 EVT VT = LD->getMemoryVT(); 1055 if (VT == MVT::i64) 1057 else if (VT == MVT::i32) { 1069 } else if (VT == MVT::i16) { 1082 } else if (VT == MVT::i8) { 1095 } else if (VT == MVT::f16) { 1097 } else if (VT == MVT::f32) { 1099 } else if (VT 1137 EVT VT = N->getValueType(0); local 1158 EVT VT = N->getValueType(0); local 1190 EVT VT = N->getOperand(2)->getValueType(0); local 1206 EVT VT = N->getOperand(2)->getValueType(0); local 1234 EVT VT = V64Reg.getValueType(); local 1250 EVT VT = V128Reg.getValueType(); local 1262 EVT VT = N->getValueType(0); local 1302 EVT VT = N->getValueType(0); local 1358 EVT VT = N->getOperand(2)->getValueType(0); local 1388 EVT VT = N->getOperand(2)->getValueType(0); local 1428 EVT VT = N->getValueType(0); local 1563 EVT VT = N->getValueType(0); local 1693 isBitfieldDstMask(uint64_t DstMask, APInt BitsToBeInserted, unsigned NumberOfIgnoredHighBits, EVT VT) argument 1918 EVT VT = Op.getValueType(); local 1982 EVT VT = N->getValueType(0); local 2042 EVT VT = OrOpd1->getValueType(0); local 2085 EVT VT = N->getValueType(0); local 2319 EVT VT = Node->getValueType(0); local [all...] |
H A D | AArch64ISelLowering.cpp | 218 for (MVT VT : MVT::vector_valuetypes()) { 219 setOperationAction(ISD::ROTL, VT, Expand); 220 setOperationAction(ISD::ROTR, VT, Expand); 240 for (MVT VT : MVT::vector_valuetypes()) { 241 setOperationAction(ISD::SDIVREM, VT, Expand); 242 setOperationAction(ISD::UDIVREM, VT, Expand); 430 for (MVT VT : MVT::fp_valuetypes()) { 431 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand); 432 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand); 433 setLoadExtAction(ISD::EXTLOAD, VT, MV 631 addTypeForNEON(EVT VT, EVT PromotedBitwiseVT) argument 715 addDRTypeForNEON(MVT VT) argument 720 addQRTypeForNEON(MVT VT) argument 757 EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT(); local 777 MVT VT = Op.getOperand(1).getValueType().getSimpleVT(); local 800 allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace, unsigned Align, bool *Fast) const argument 1178 EVT VT = LHS.getValueType(); local 1438 EVT VT = RHS.getValueType(); local 1725 EVT VT = Op.getValueType(); local 1850 EVT VT = Op.getValueType(); local 1915 EVT VT = Op.getValueType(); local 2054 EVT VT = N->getValueType(0); local 2086 EVT VT = N->getValueType(0); local 2144 EVT VT = Op.getValueType(); local 3710 EVT VT = Op.getValueType(); local 3801 EVT VT = Op.getValueType(); local 3828 EVT VT = Op.getValueType(); local 4002 EVT VT = TVal.getValueType(); local 4009 EVT VT = TVal.getValueType(); local 4283 EVT VT = Op.getValueType(); local 4346 EVT VT = Op.getValueType(); local 4359 getRegisterByName(const char* RegName, EVT VT, SelectionDAG &DAG) const argument 4376 EVT VT = Op.getValueType(); local 4397 EVT VT = Op.getValueType(); local 4455 EVT VT = Op.getValueType(); local 4801 EVT VT = V64Reg.getValueType(); local 4821 EVT VT = V128Reg.getValueType(); local 4836 EVT VT = Op.getValueType(); local 5027 isSingletonEXTMask(ArrayRef<int> M, EVT VT, unsigned &Imm) argument 5058 isEXTMask(ArrayRef<int> M, EVT VT, bool &ReverseEXT, unsigned &Imm) argument 5100 isREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) argument 5127 isZIPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) argument 5141 isUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) argument 5154 isTRNMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) argument 5168 isZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) argument 5185 isUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) argument 5204 isTRN_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) argument 5254 isConcatMask(ArrayRef<int> Mask, EVT VT, bool SplitLHS) argument 5276 EVT VT = Op.getValueType(); local 5340 EVT VT = OpLHS.getValueType(); local 5486 EVT VT = Op.getValueType(); local 5640 EVT VT = BVN->getValueType(0); local 5666 EVT VT = Op.getValueType(); local 5792 EVT VT = N->getValueType(0); local 5865 EVT VT = Op.getValueType(); local 5960 EVT VT = Op.getValueType(); local 5981 EVT VT = Op.getValueType(); local 6359 EVT VT = Op.getOperand(0).getValueType(); local 6393 EVT VT = Op.getOperand(0).getValueType(); local 6426 EVT VT = Op.getOperand(0).getValueType(); local 6513 isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) argument 6524 isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, int64_t &Cnt) argument 6534 EVT VT = Op.getValueType(); local 6581 EmitVectorComparison(SDValue LHS, SDValue RHS, AArch64CC::CondCode CC, bool NoNans, EVT VT, SDLoc dl, SelectionDAG &DAG) argument 6878 EVT VT = getValueType(DL, User->getOperand(0)->getType()); local 7300 EVT VT = N->getValueType(0); local 7339 EVT VT = N->getValueType(0); local 7380 EVT VT = N->getValueType(0); local 7430 EVT VT = N->getValueType(0); local 7489 EVT VT = N->getValueType(0); local 7718 EVT VT = N->getValueType(0); local 7756 EVT VT = N->getValueType(0); local 7807 EVT VT = N->getValueType(0); local 7893 EVT VT = N->getValueType(0); local 8198 EVT VT = Op->getValueType(0); local 8539 EVT VT = StVal.getValueType(); local 8616 EVT VT = StVal.getValueType(); local 8667 EVT VT = N->getValueType(0); local 9764 EVT VT; local 9785 EVT VT; local [all...] |
H A D | AArch64FastISel.cpp | 140 bool isTypeLegal(Type *Ty, MVT &VT); 141 bool isTypeSupported(Type *Ty, MVT &VT, bool IsVectorAllowed = false); 145 bool simplifyAddress(Address &Addr, MVT VT); 185 unsigned emitLoad(MVT VT, MVT ResultVT, Address Addr, bool WantZExt = true, 187 bool emitStore(MVT VT, unsigned SrcReg, Address Addr, 194 unsigned emitAdd_ri_(MVT VT, unsigned Op0, bool Op0IsKill, int64_t Imm); 231 unsigned materializeInt(const ConstantInt *CI, MVT VT); 232 unsigned materializeFP(const ConstantFP *CFP, MVT VT); 286 static unsigned getImplicitScaleFactor(MVT VT) { argument 287 switch (VT 336 materializeInt(const ConstantInt *CI, MVT VT) argument 353 materializeFP(const ConstantFP *CFP, MVT VT) argument 482 MVT VT; local 909 isTypeLegal(Type *Ty, MVT &VT) argument 930 isTypeSupported(Type *Ty, MVT &VT, bool IsVectorAllowed) argument 956 simplifyAddress(Address &Addr, MVT VT) argument 1486 emitAdd_ri_(MVT VT, unsigned Op0, bool Op0IsKill, int64_t Imm) argument 1603 MVT VT = std::max(MVT::i32, RetVT.SimpleTy); local 1706 emitLoad(MVT VT, MVT RetVT, Address Addr, bool WantZExt, MachineMemOperand *MMO) argument 1844 MVT VT; local 1870 MVT VT; local 1899 MVT VT; local 1993 emitStore(MVT VT, unsigned SrcReg, Address Addr, MachineMemOperand *MMO) argument 2062 MVT VT; local 2155 MVT VT; local 2558 MVT VT; local 2865 MVT VT = TLI.getSimpleValueType(DL, Arg.getType()); local 3075 MVT VT; local 3169 MVT VT; local 3436 MVT VT; local 3469 MVT VT; local 3496 MVT VT; local 4474 MVT VT; local 4495 MVT VT; local 4504 MVT VT; local 4715 MVT VT; local 4818 MVT VT = TLI.getPointerTy(DL); local [all...] |
/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | AMDGPUISelLowering.cpp | 106 EVT VT = Op.getValueType(); local 113 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1)); 115 return DAG.getNode(ISD::FABS, DL, VT, Op.getOperand(1)); 119 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1)); 121 return DAG.getNode(AMDGPUISD::MAD, DL, VT, Op.getOperand(1), 124 return DAG.getNode(AMDGPUISD::FMAX, DL, VT, Op.getOperand(1), 127 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1), 130 return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1), 133 return DAG.getNode(AMDGPUISD::FMIN, DL, VT, Op.getOperand(1), 136 return DAG.getNode(AMDGPUISD::SMIN, DL, VT, O 154 EVT VT = Op.getValueType(); local 167 EVT VT = Op.getValueType(); local 184 EVT VT = Op.getValueType(); local [all...] |
H A D | SIRegisterInfo.cpp | 53 MVT VT) const 55 switch(VT.SimpleTy) {
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H A D | R600ISelLowering.cpp | 277 EVT VT = Op.getValueType(); local 284 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass, Reg, VT); 288 return LowerImplicitParameter(DAG, VT, DL, 0); 290 return LowerImplicitParameter(DAG, VT, DL, 1); 292 return LowerImplicitParameter(DAG, VT, DL, 2); 294 return LowerImplicitParameter(DAG, VT, DL, 3); 296 return LowerImplicitParameter(DAG, VT, DL, 4); 298 return LowerImplicitParameter(DAG, VT, DL, 5); 300 return LowerImplicitParameter(DAG, VT, DL, 6); 302 return LowerImplicitParameter(DAG, VT, D 357 LowerImplicitParameter(SelectionDAG &DAG, EVT VT, DebugLoc DL, unsigned DwordOffset) const argument 377 EVT VT = Op.getValueType(); local 390 EVT VT = Op.getValueType(); local [all...] |
H A D | SIRegisterInfo.h | 48 virtual const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const;
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H A D | AMDILISelLowering.cpp | 106 MVT::SimpleValueType VT = (MVT::SimpleValueType)types[x]; local 110 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Custom); 111 setOperationAction(ISD::SUBE, VT, Expand); 112 setOperationAction(ISD::SUBC, VT, Expand); 113 setOperationAction(ISD::ADDE, VT, Expand); 114 setOperationAction(ISD::ADDC, VT, Expand); 115 setOperationAction(ISD::BRCOND, VT, Custom); 116 setOperationAction(ISD::BR_JT, VT, Expand); 117 setOperationAction(ISD::BRIND, VT, Expand); 119 setOperationAction(ISD::SREM, VT, Expan 127 MVT::SimpleValueType VT = (MVT::SimpleValueType)FloatTypes[x]; local 142 MVT::SimpleValueType VT = (MVT::SimpleValueType)IntTypes[x]; local 163 MVT::SimpleValueType VT = (MVT::SimpleValueType)VectorTypes[ii]; local 356 EVT VT = Op.getValueType(); local [all...] |
/external/llvm/lib/CodeGen/ |
H A D | CallingConvLower.cpp | 75 MVT ArgVT = Ins[i].VT; 93 MVT VT = Outs[i].VT; local 95 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)) 107 MVT VT = Outs[i].VT; local 109 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)) { 112 << EVT(VT) 160 MVT VT = Ins[i].VT; local 173 AnalyzeCallResult(MVT VT, CCAssignFn Fn) argument 183 isValueTypeInRegForCC(CallingConv::ID CC, MVT VT) argument 193 getRemainingRegParmsForType(SmallVectorImpl<MCPhysReg> &Regs, MVT VT, CCAssignFn Fn) argument [all...] |
H A D | TargetLoweringBase.cpp | 656 RTLIB::Libcall RTLIB::getATOMIC(unsigned Opc, MVT VT) { argument 659 switch (VT.SimpleTy) { \ 774 for (MVT VT : MVT::all_valuetypes()) { 778 setIndexedLoadAction(IM, VT, Expand); 779 setIndexedStoreAction(IM, VT, Expand); 783 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Expand); 786 setOperationAction(ISD::FGETSIGN, VT, Expand); 787 setOperationAction(ISD::CONCAT_VECTORS, VT, Expand); 788 setOperationAction(ISD::FMINNUM, VT, Expand); 789 setOperationAction(ISD::FMAXNUM, VT, Expan 1033 getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT, TargetLoweringBase *TLI) argument 1273 MVT VT = (MVT::SimpleValueType) i; local 1385 getVectorTypeBreakdown(LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const argument 1463 EVT VT = ValueVTs[j]; local 1508 allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace, unsigned Alignment, bool *Fast) const argument [all...] |
/external/llvm/include/llvm/CodeGen/ |
H A D | ValueTypes.h | 41 bool operator==(EVT VT) const { 42 return !(*this != VT); 44 bool operator!=(EVT VT) const { 45 if (V.SimpleTy != VT.V.SimpleTy) 48 return LLVMTy != VT.LLVMTy; 69 /// length, where each element is of type VT. 70 static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements) { argument 71 MVT M = MVT::getVectorVT(VT.V, NumElements); 74 return getExtendedVectorVT(Context, VT, NumElements); 88 "Simple vector VT no [all...] |
H A D | SelectionDAG.h | 56 SDVTListNode(const FoldingSetNodeIDRef ID, const EVT *VT, unsigned int Num) : argument 57 FastID(ID), VTs(VT), NumVTs(Num) { 421 SDVTList getVTList(EVT VT); 430 SDValue getConstant(uint64_t Val, SDLoc DL, EVT VT, bool isTarget = false, 432 SDValue getConstant(const APInt &Val, SDLoc DL, EVT VT, bool isTarget = false, 434 SDValue getConstant(const ConstantInt &Val, SDLoc DL, EVT VT, 437 SDValue getTargetConstant(uint64_t Val, SDLoc DL, EVT VT, argument 439 return getConstant(Val, DL, VT, true, isOpaque); 441 SDValue getTargetConstant(const APInt &Val, SDLoc DL, EVT VT, argument 443 return getConstant(Val, DL, VT, tru 445 getTargetConstant(const ConstantInt &Val, SDLoc DL, EVT VT, bool isOpaque = false) argument 456 getTargetConstantFP(double Val, SDLoc DL, EVT VT) argument 459 getTargetConstantFP(const APFloat& Val, SDLoc DL, EVT VT) argument 462 getTargetConstantFP(const ConstantFP &Val, SDLoc DL, EVT VT) argument 468 getTargetGlobalAddress(const GlobalValue *GV, SDLoc DL, EVT VT, int64_t offset = 0, unsigned char TargetFlags = 0) argument 474 getTargetFrameIndex(int FI, EVT VT) argument 479 getTargetJumpTable(int JTI, EVT VT, unsigned char TargetFlags = 0) argument 485 getTargetConstantPool(const Constant *C, EVT VT, unsigned Align = 0, int Offset = 0, unsigned char TargetFlags = 0) argument 493 getTargetConstantPool(MachineConstantPoolValue *C, EVT VT, unsigned Align = 0, int Offset = 0, unsigned char TargetFlags=0) argument 517 getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset = 0, unsigned char TargetFlags = 0) argument 548 getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT) argument 557 getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT, SDValue Glue) argument 578 getVectorShuffle(EVT VT, SDLoc dl, SDValue N1, SDValue N2, ArrayRef<int> MaskElts) argument 660 getUNDEF(EVT VT) argument 665 getGLOBAL_OFFSET_TABLE(EVT VT) argument 727 getSetCC(SDLoc DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond) argument 740 getSelect(SDLoc DL, EVT VT, SDValue Cond, SDValue LHS, SDValue RHS) argument 1111 EVTToAPFloatSemantics(EVT VT) argument [all...] |
/external/llvm/include/llvm/Target/ |
H A D | TargetLowering.h | 207 getPreferredVectorAction(EVT VT) const { 209 if (VT.getVectorNumElements() == 1) 225 shouldExpandBuildVectorWithShuffles(EVT /* VT */, 234 virtual bool isIntDivCheap(EVT VT, AttributeSet Attr) const { argument 329 virtual bool enableAggressiveFMAFusion(EVT VT) const { 335 EVT VT) const; 380 virtual const TargetRegisterClass *getRegClassFor(MVT VT) const { 381 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy]; 393 virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const { 394 const TargetRegisterClass *RC = RepRegClassForVT[VT 428 setTypeAction(MVT VT, LegalizeTypeAction Action) argument [all...] |
/external/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUISelLowering.cpp | 47 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) { argument 48 unsigned StoreSize = VT.getStoreSizeInBits(); 57 EVT AMDGPUTargetLowering::getEquivalentLoadRegType(LLVMContext &Ctx, EVT VT) { argument 58 unsigned StoreSize = VT.getStoreSizeInBits(); 184 for (MVT VT : MVT::integer_valuetypes()) { 185 setLoadExtAction(ISD::EXTLOAD, MVT::i64, VT, Expand); 186 setLoadExtAction(ISD::SEXTLOAD, MVT::i64, VT, Expand); 187 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, VT, Expand); 190 for (MVT VT : MVT::integer_vector_valuetypes()) { 191 setLoadExtAction(ISD::EXTLOAD, VT, MV 696 EVT VT = EVT::getEVT(InitTy); local 704 EVT VT = EVT::getEVT(CFP->getType()); local 753 EVT VT = EVT::getEVT(InitTy); local 870 EVT VT = Op.getValueType(); local 897 EVT VT = Op.getValueType(); local 1059 EVT VT = Op.getValueType(); local 1071 EVT VT = Op.getValueType(); local 1084 CombineFMinMaxLegacy(SDLoc DL, EVT VT, SDValue LHS, SDValue RHS, SDValue True, SDValue False, SDValue CC, DAGCombinerInfo &DCI) const argument 1205 EVT VT = Op.getValueType(); local 1273 EVT VT = Value.getValueType(); local 1352 EVT VT = Val.getValueType(); local 1407 EVT VT = Op.getValueType(); local 1548 EVT VT = Op.getValueType(); local 1651 EVT VT = Op.getValueType(); local 1723 EVT VT = Op.getValueType(); local 1843 EVT VT = Op.getValueType(); local 1903 EVT VT = Op.getValueType(); local 2126 EVT VT = Op.getValueType(); local 2273 MVT VT = Op.getSimpleValueType(); local 2300 EVT VT = Op.getValueType(); local 2307 EVT VT = Op.getValueType(); local 2320 EVT VT = Op.getValueType(); local 2361 EVT VT = Value.getValueType(); local 2421 EVT VT = N->getValueType(0); local 2477 EVT VT = N->getValueType(0); local 2598 EVT VT; local 2740 EVT VT = Operand.getValueType(); local 2757 EVT VT = Operand.getValueType(); local [all...] |
H A D | R600RegisterInfo.h | 38 const TargetRegisterClass *getCFGStructurizerRegClass(MVT VT) const;
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAG.cpp | 80 bool ConstantFPSDNode::isValueValidForType(EVT VT, argument 82 assert(VT.isFloatingPoint() && "Can only convert between FP types"); 87 (void) Val2.convert(SelectionDAG::EVTToAPFloatSemantics(VT), 705 EVT VT = N->getValueType(0); local 707 assert(!VT.isVector() && (VT.isInteger() || VT.isFloatingPoint()) && 712 assert(N->getOperand(0).getValueType().isInteger() == VT.isInteger() && 714 assert(VT.getSizeInBits() == 2 * N->getOperand(0).getValueSizeInBits() && 780 EVT VT local 1011 getAnyExtOrTrunc(SDValue Op, SDLoc DL, EVT VT) argument 1017 getSExtOrTrunc(SDValue Op, SDLoc DL, EVT VT) argument 1023 getZExtOrTrunc(SDValue Op, SDLoc DL, EVT VT) argument 1029 getBoolExtOrTrunc(SDValue Op, SDLoc SL, EVT VT, EVT OpVT) argument 1038 getZeroExtendInReg(SDValue Op, SDLoc DL, EVT VT) argument 1050 getAnyExtendVectorInReg(SDValue Op, SDLoc DL, EVT VT) argument 1060 getSignExtendVectorInReg(SDValue Op, SDLoc DL, EVT VT) argument 1070 getZeroExtendVectorInReg(SDValue Op, SDLoc DL, EVT VT) argument 1082 getNOT(SDLoc DL, SDValue Val, EVT VT) argument 1089 getLogicalNOT(SDLoc DL, SDValue Val, EVT VT) argument 1105 getConstant(uint64_t Val, SDLoc DL, EVT VT, bool isT, bool isO) argument 1114 getConstant(const APInt &Val, SDLoc DL, EVT VT, bool isT, bool isO) argument 1120 getConstant(const ConstantInt &Val, SDLoc DL, EVT VT, bool isT, bool isO) argument 1219 getConstantFP(const APFloat& V, SDLoc DL, EVT VT, bool isTarget) argument 1224 getConstantFP(const ConstantFP& V, SDLoc DL, EVT VT, bool isTarget) argument 1259 getConstantFP(double Val, SDLoc DL, EVT VT, bool isTarget) argument 1277 getGlobalAddress(const GlobalValue *GV, SDLoc DL, EVT VT, int64_t Offset, bool isTargetGA, unsigned char TargetFlags) argument 1313 getFrameIndex(int FI, EVT VT, bool isTarget) argument 1328 getJumpTable(int JTI, EVT VT, bool isTarget, unsigned char TargetFlags) argument 1348 getConstantPool(const Constant *C, EVT VT, unsigned Alignment, int Offset, bool isTarget, unsigned char TargetFlags) argument 1375 getConstantPool(MachineConstantPoolValue *C, EVT VT, unsigned Alignment, int Offset, bool isTarget, unsigned char TargetFlags) argument 1401 getTargetIndex(int Index, EVT VT, int64_t Offset, unsigned char TargetFlags) argument 1433 getValueType(EVT VT) argument 1447 getExternalSymbol(const char *Sym, EVT VT) argument 1455 getMCSymbol(MCSymbol *Sym, EVT VT) argument 1464 getTargetExternalSymbol(const char *Sym, EVT VT, unsigned char TargetFlags) argument 1496 getVectorShuffle(EVT VT, SDLoc dl, SDValue N1, SDValue N2, const int *Mask) argument 1665 MVT VT = SV.getSimpleValueType(0); local 1674 getConvertRndSat(EVT VT, SDLoc dl, SDValue Val, SDValue DTy, SDValue STy, SDValue Rnd, SDValue Sat, ISD::CvtCode Code) argument 1699 getRegister(unsigned RegNo, EVT VT) argument 1744 getBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset, bool isTarget, unsigned char TargetFlags) argument 1800 getBitcast(EVT VT, SDValue V) argument 1808 getAddrSpaceCast(SDLoc dl, EVT VT, SDValue Ptr, unsigned SrcAS, unsigned DestAS) argument 1842 EVT VT = Node->getValueType(0); local 1891 CreateStackTemporary(EVT VT, unsigned minAlign) argument 1917 FoldSetCC(EVT VT, SDValue N1, SDValue N2, ISD::CondCode Cond, SDLoc dl) argument 2283 EVT VT = LD->getMemoryVT(); local 2348 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); local 2524 EVT VT = Op.getValueType(); local 2848 getNode(unsigned Opcode, SDLoc DL, EVT VT) argument 2863 getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue Operand) argument 3225 FoldConstantArithmetic(unsigned Opcode, SDLoc DL, EVT VT, const ConstantSDNode *Cst1, const ConstantSDNode *Cst2) argument 3238 FoldConstantArithmetic(unsigned Opcode, SDLoc DL, EVT VT, SDNode *Cst1, SDNode *Cst2) argument 3307 FoldConstantVectorArithmetic(unsigned Opcode, SDLoc DL, EVT VT, ArrayRef<SDValue> Ops, const SDNodeFlags *Flags) argument 3401 getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, SDValue N2, const SDNodeFlags *Flags) argument 3895 getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, SDValue N2, SDValue N3) argument 4002 getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, SDValue N2, SDValue N3, SDValue N4) argument 4009 getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, SDValue N2, SDValue N3, SDValue N4, SDValue N5) argument 4040 getMemsetValue(SDValue Value, EVT VT, SelectionDAG &DAG, SDLoc dl) argument 4083 getMemsetStringVal(EVT VT, SDLoc dl, SelectionDAG &DAG, const TargetLowering &TLI, StringRef Str) argument 4128 EVT VT = Base.getValueType(); local 4174 EVT VT = TLI.getOptimalMemOpType(Size, DstAlign, SrcAlign, local 4329 EVT VT = MemOps[i]; local 4431 EVT VT = MemOps[i]; local 4446 EVT VT = MemOps[i]; local 4528 EVT VT = MemOps[i]; local 4904 EVT VT = Val.getValueType(); local 4912 getAtomic(unsigned Opcode, SDLoc dl, EVT MemVT, EVT VT, SDValue Chain, SDValue Ptr, MachineMemOperand *MMO, AtomicOrdering Ordering, SynchronizationScope SynchScope) argument 5039 getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, SDValue Offset, MachinePointerInfo PtrInfo, EVT MemVT, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const AAMDNodes &AAInfo, const MDNode *Ranges) argument 5072 getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, SDValue Offset, EVT MemVT, MachineMemOperand *MMO) argument 5120 getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const AAMDNodes &AAInfo, const MDNode *Ranges) argument 5133 getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachineMemOperand *MMO) argument 5141 getExtLoad(ISD::LoadExtType ExtType, SDLoc dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const AAMDNodes &AAInfo) argument 5154 getExtLoad(ISD::LoadExtType ExtType, SDLoc dl, EVT VT, SDValue Chain, SDValue Ptr, EVT MemVT, MachineMemOperand *MMO) argument 5205 EVT VT = Val.getValueType(); local 5258 EVT VT = Val.getValueType(); local 5325 getMaskedLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, SDValue Mask, SDValue Src0, EVT MemVT, MachineMemOperand *MMO, ISD::LoadExtType ExtTy) argument 5357 EVT VT = Val.getValueType(); local 5380 getMaskedGather(SDVTList VTs, EVT VT, SDLoc dl, ArrayRef<SDValue> Ops, MachineMemOperand *MMO) argument 5405 getMaskedScatter(SDVTList VTs, EVT VT, SDLoc dl, ArrayRef<SDValue> Ops, MachineMemOperand *MMO) argument 5428 getVAArg(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, SDValue SV, unsigned Align) argument 5436 getNode(unsigned Opcode, SDLoc DL, EVT VT, ArrayRef<SDUse> Ops) argument 5452 getNode(unsigned Opcode, SDLoc DL, EVT VT, ArrayRef<SDValue> Ops, const SDNodeFlags *Flags) argument 5623 getVTList(EVT VT) argument 5829 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT) argument 5835 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT, SDValue Op1) argument 5842 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT, SDValue Op1, SDValue Op2) argument 5850 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT, SDValue Op1, SDValue Op2, SDValue Op3) argument 5858 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT, ArrayRef<SDValue> Ops) argument 6050 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT) argument 6056 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT, SDValue Op1) argument 6063 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT, SDValue Op1, SDValue Op2) argument 6071 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT, SDValue Op1, SDValue Op2, SDValue Op3) argument 6079 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT, ArrayRef<SDValue> Ops) argument 6209 getTargetExtractSubreg(int SRIdx, SDLoc DL, EVT VT, SDValue Operand) argument 6220 getTargetInsertSubreg(int SRIdx, SDLoc DL, EVT VT, SDValue Operand, SDValue Subreg) argument 6720 GlobalAddressSDNode(unsigned Opc, unsigned Order, DebugLoc DL, const GlobalValue *GA, EVT VT, int64_t o, unsigned char TF) argument 6727 AddrSpaceCastSDNode(unsigned Order, DebugLoc dl, EVT VT, SDValue X, unsigned SrcAS, unsigned DestAS) argument 6781 getValueTypeList(EVT VT) argument 6939 EVT VT = N->getValueType(0); local 7138 EVT VT = Op.getValueType(); local 7169 EVT VT = getValueType(0); local 7293 isSplatMask(const int *Mask, EVT VT) argument [all...] |
H A D | LegalizeVectorOps.cpp | 402 MVT VT = Op.getSimpleValueType(); local 405 MVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT); 424 if ((VT.isFloatingPoint() && NVT.isFloatingPoint()) || 425 (VT.isVector() && VT.getVectorElementType().isFloatingPoint() && 427 return DAG.getNode(ISD::FP_ROUND, dl, VT, Op, DAG.getIntPtrConstant(0, dl)); 429 return DAG.getNode(ISD::BITCAST, dl, VT, Op); 435 EVT VT = Op.getOperand(0).getValueType(); local 447 EVT NVT = VT.widenIntegerVectorElementType(*DAG.getContext()); 471 EVT VT local 731 EVT VT = Op.getValueType(); local 786 EVT VT = Op.getValueType(); local 809 EVT VT = Op.getValueType(); local 832 EVT VT = Op.getValueType(); local 856 EVT VT = Op.getValueType(); local 885 EVT VT = Op.getValueType(); local 908 EVT VT = Op.getValueType(); local 935 EVT VT = Mask.getValueType(); local 974 EVT VT = Op.getOperand(0).getValueType(); local 1026 EVT VT = Op.getValueType(); local [all...] |
H A D | DAGCombiner.cpp | 339 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 348 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT); 484 /// if the specified VT is legal. 485 bool isTypeLegal(const EVT &VT) { argument 487 return TLI.isTypeLegal(VT); 491 EVT getSetCCResultType(EVT VT) const { 492 return TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT); 826 EVT VT = N0.getValueType(); local 831 if (SDValue OpNode = DAG.FoldConstantArithmetic(Opc, DL, VT, L, R)) 832 return DAG.getNode(Opc, DL, VT, N 947 EVT VT = Load->getValueType(0); local 1641 EVT VT = N0.getValueType(); local 1794 EVT VT = N0.getValueType(); local 1853 tryFoldToZero(SDLoc DL, const TargetLowering &TLI, EVT VT, SelectionDAG &DAG, bool LegalOperations, bool LegalTypes) argument 1866 EVT VT = N0.getValueType(); local 1973 EVT VT = N0.getValueType(); local 2013 EVT VT = N0.getValueType(); local 2230 EVT VT = N->getValueType(0); local 2329 EVT VT = N->getValueType(0); local 2395 EVT VT = N->getValueType(0); local 2477 EVT VT = N->getValueType(0); local 2518 EVT VT = N->getValueType(0); local 2687 EVT VT = N0.getValueType(); local 2712 EVT VT = N0.getValueType(); local 2867 EVT VT = N1.getValueType(); local 3014 EVT VT = N1.getValueType(); local 3120 EVT VT = Vector->getValueType(0); local 3577 EVT VT = N1.getValueType(); local 3674 EVT VT = N1.getValueType(); local 3958 EVT VT = Shifted.getValueType(); local 3973 EVT VT = LHS.getValueType(); local 4082 EVT VT = N0.getValueType(); local 4357 EVT VT = N0.getValueType(); local 4570 EVT VT = N0.getValueType(); local 4717 EVT VT = N0.getValueType(); local 4917 EVT VT = N->getValueType(0); local 4930 EVT VT = N->getValueType(0); local 4940 EVT VT = N->getValueType(0); local 4950 EVT VT = N->getValueType(0); local 4960 EVT VT = N->getValueType(0); local 4970 EVT VT = N->getValueType(0); local 4980 combineMinNumMaxNum(SDLoc DL, EVT VT, SDValue LHS, SDValue RHS, SDValue True, SDValue False, ISD::CondCode CC, const TargetLowering &TLI, SelectionDAG &DAG) argument 5019 EVT VT = N->getValueType(0); local 5223 EVT VT = N->getValueType(0); local 5498 EVT VT = N->getValueType(0); local 5595 EVT VT = LHS.getValueType(); local 5614 EVT VT = N->getValueType(0); local 5730 EVT VT = N->getValueType(0); local 5961 EVT VT = N->getValueType(0); local 6220 EVT VT = N->getValueType(0); local 6525 EVT VT = N->getValueType(0); local 6727 EVT VT = N->getValueType(0); local 6893 EVT VT = N->getValueType(0); local 7000 EVT VT = N->getValueType(0); local 7014 EVT VT = N->getValueType(0); local 7217 CombineConsecutiveLoads(SDNode *N, EVT VT) argument 7256 EVT VT = N->getValueType(0); local 7521 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, local 7596 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size()); local 7603 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, local 7634 EVT VT = N->getValueType(0); local 7817 EVT VT = N->getValueType(0); local 8081 EVT VT = N->getValueType(0); local 8164 EVT VT = N->getValueType(0); local 8313 EVT VT = N->getValueType(0); local 8378 EVT VT = N->getValueType(0); local 8482 EVT VT = N->getValueType(0); local 8643 EVT VT = N->getValueType(0); local 8753 EVT VT = N->getValueType(0); local 8815 EVT VT = N->getValueType(0); local 8862 EVT VT = N->getValueType(0); local 8916 EVT VT = N->getValueType(0); local 8957 EVT VT = N->getValueType(0); local 9000 EVT VT = N->getValueType(0); local 9011 EVT VT = N->getValueType(0); local 9024 EVT VT = N->getValueType(0); local 9075 EVT VT = N->getValueType(0); local 9091 EVT VT = N->getValueType(0); local 9141 EVT VT = N->getValueType(0); local 9152 EVT VT = N->getValueType(0); local 9163 EVT VT = N->getValueType(0); local 9175 EVT VT = N->getValueType(0); local 9234 EVT VT = N->getValueType(0); local 9255 EVT VT = N->getValueType(0); local 9275 EVT VT = N->getValueType(0); local 9497 EVT VT; local 9548 EVT VT; local 9774 EVT VT; local 10745 EVT VT = Value.getValueType(); local 10873 EVT VT = LD->getMemoryVT(); local 12157 EVT VT = InVec.getValueType(); local 12354 EVT VT = N->getValueType(0); local 12525 EVT VT = N->getValueType(0); local 12705 EVT VT = N->getValueType(0); local 12763 EVT VT = N->getValueType(0); local 13056 EVT VT = V.getValueType(); local 13122 EVT VT = SVN->getValueType(0); local 13142 EVT VT = N->getValueType(0); local 13204 EVT VT = N->getValueType(0); local 13576 EVT VT = N->getValueType(0); local 13611 EVT VT = N->getValueType(0); local 13659 EVT VT = N->getValueType(0); local 13778 EVT VT = N->getValueType(0); local 14223 SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, SDLoc DL, bool foldBooleans) argument 14310 EVT VT = Op.getValueType(); local 14346 EVT VT = Arg.getValueType(); local 14383 EVT VT = Arg.getValueType(); local [all...] |
H A D | TargetLowering.cpp | 123 void TargetLowering::softenSetCCOperands(SelectionDAG &DAG, EVT VT, argument 127 assert((VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128) 136 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : 137 (VT == MVT::f64) ? RTLIB::OEQ_F64 : RTLIB::OEQ_F128; 141 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : 142 (VT == MVT::f64) ? RTLIB::UNE_F64 : RTLIB::UNE_F128; 146 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : 147 (VT 316 EVT VT = Op.getValueType(); local 552 EVT VT = Op.getValueType(); local 567 EVT VT = Op.getValueType(); local 643 EVT VT = Op.getValueType(); local 690 EVT VT = Op.getValueType(); local 707 EVT VT = Op.getValueType(); local 767 EVT VT = Op.getValueType(); local 1054 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); local 1258 SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, bool foldBooleans, DAGCombinerInfo &DCI, SDLoc dl) const argument 2748 EVT VT = N->getValueType(0); local 2812 EVT VT = N->getValueType(0); local 2895 EVT VT = N->getValueType(0); local 2998 EVT VT = Node->getOperand(0).getValueType(); local [all...] |
H A D | LegalizeDAG.cpp | 70 EVT getSetCCResultType(EVT VT) const { 71 return TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT); 105 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, SDLoc dl, 109 bool LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC, 217 SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, SDLoc dl, argument 220 unsigned NumMaskElts = VT.getVectorNumElements(); 257 EVT VT = CFP->getValueType(0); local 260 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion"); 262 (VT 301 EVT VT = CP->getValueType(0); local 321 EVT VT = Val.getValueType(); local 448 EVT VT = LD->getValueType(0); local 610 EVT VT = Tmp1.getValueType(); local 747 MVT VT = Value.getSimpleValueType(); local [all...] |
/external/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 139 for (MVT VT : MVT::integer_valuetypes()) 140 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); 279 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) { 280 setOperationAction(ISD::MULHS, VT, Expand); 281 setOperationAction(ISD::MULHU, VT, Expand); 282 setOperationAction(ISD::SDIV, VT, Expand); 283 setOperationAction(ISD::UDIV, VT, Expand); 284 setOperationAction(ISD::SREM, VT, Expand); 285 setOperationAction(ISD::UREM, VT, Expand); 288 setOperationAction(ISD::ADDC, VT, Custo 2015 allowsMisalignedMemoryAccesses(EVT VT, unsigned, unsigned, bool *Fast) const argument 2360 getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT, ISD::NodeType ExtendKind) const argument 3007 EVT VT = getPointerTy(DAG.getDataLayout()); local 3038 getMOVL(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1, SDValue V2) argument 3927 getTargetShuffleNode(unsigned Opc, SDLoc dl, MVT VT, SDValue V1, unsigned TargetMask, SelectionDAG &DAG) argument 3942 getTargetShuffleNode(unsigned Opc, SDLoc dl, MVT VT, SDValue V1, SDValue V2, SelectionDAG &DAG) argument 4250 MVT VT = N->getSimpleValueType(0); local 4268 MVT VT = N->getSimpleValueType(0); local 4353 getConstVector(ArrayRef<int> Values, MVT VT, SelectionDAG &DAG, SDLoc dl, bool IsMask = false) argument 4437 EVT VT = Vec.getValueType(); local 4648 Concat128BitVectors(SDValue V1, SDValue V2, EVT VT, unsigned NumElems, SelectionDAG &DAG, SDLoc dl) argument 4655 Concat256BitVectors(SDValue V1, SDValue V2, EVT VT, unsigned NumElems, SelectionDAG &DAG, SDLoc dl) argument 4666 getOnesVector(EVT VT, const X86Subtarget *Subtarget, SelectionDAG &DAG, SDLoc dl) argument 4693 getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1, SDValue V2) argument 4705 getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1, SDValue V2) argument 4724 MVT VT = V2.getSimpleValueType(); local 4741 getTargetShuffleMask(SDNode *N, MVT VT, SmallVectorImpl<int> &Mask, bool &IsUnary) argument 4802 MVT VT = MaskNode.getSimpleValueType(); local 5030 EVT VT = V.getValueType(); local 5223 MVT VT = V1.getSimpleValueType(); local 5294 getVShift(bool isLeft, EVT VT, SDValue SrcOp, unsigned NumBits, SelectionDAG &DAG, const TargetLowering &TLI, SDLoc dl) argument 5308 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) argument 5390 EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts, SDLoc &DL, SelectionDAG &DAG, bool isAfterLegalize) argument 5692 MVT VT = Op.getSimpleValueType(); local 5774 MVT VT = local 5782 MVT VT = Op.getSimpleValueType(); local 5882 EVT VT = N->getValueType(0); local 5996 EVT VT = V0.getValueType(); local 6034 MVT VT = BV->getSimpleValueType(0); local 6137 MVT VT = BV->getSimpleValueType(0); local 6274 MVT VT = Op.getSimpleValueType(); local [all...] |
/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelDAGToDAG.cpp | 156 void getAddressOperands(const SystemZAddressingMode &AM, EVT VT, 158 void getAddressOperands(const SystemZAddressingMode &AM, EVT VT, 281 // Return an undefined value of type VT. 282 SDValue getUNDEF(SDLoc DL, EVT VT) const; 284 // Convert N to VT, if it isn't already. 285 SDValue convertTo(SDLoc DL, EVT VT, SDValue N) const; 594 EVT VT, SDValue &Base, 599 Base = CurDAG->getRegister(0, VT); 603 Base = CurDAG->getTargetFrameIndex(FrameIndex, VT); 604 } else if (Base.getValueType() != VT) { 593 getAddressOperands(const SystemZAddressingMode &AM, EVT VT, SDValue &Base, SDValue &Disp) const argument 618 getAddressOperands(const SystemZAddressingMode &AM, EVT VT, SDValue &Base, SDValue &Disp, SDValue &Index) const argument 896 convertTo(SDLoc DL, EVT VT, SDValue N) const argument 908 EVT VT = N->getValueType(0); local 983 EVT VT = N->getValueType(0); local 1035 EVT VT = Node->getValueType(0); local 1054 EVT VT = N->getValueType(0); local 1094 EVT VT = Vec.getValueType(); local 1250 EVT VT = Node->getValueType(0); local [all...] |