| /external/llvm/lib/Target/AMDGPU/ |
| H A D | SIFrameLowering.cpp | 100 MRI.addLiveIn(PreloadedScratchWaveOffsetReg);
101 MBB.addLiveIn(PreloadedScratchWaveOffsetReg);
104 MRI.addLiveIn(PreloadedPrivateBufferReg);
105 MBB.addLiveIn(PreloadedPrivateBufferReg);
219 OtherBB.addLiveIn(ScratchRsrcReg);
220 OtherBB.addLiveIn(ScratchWaveOffsetReg);
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| H A D | SIMachineFunctionInfo.cpp | 165 BI->addLiveIn(LaneVGPR);
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| H A D | SIISelLowering.cpp | 657 MF.addLiveIn(PrivateSegmentBufferReg, &AMDGPU::SReg_128RegClass);
663 MF.addLiveIn(DispatchPtrReg, &AMDGPU::SReg_64RegClass);
669 MF.addLiveIn(InputPtrReg, &AMDGPU::SReg_64RegClass);
722 Reg = MF.addLiveIn(Reg, &AMDGPU::SReg_64RegClass);
730 Reg = MF.addLiveIn(Reg, RC);
743 Reg = MF.addLiveIn(Reg, RC);
766 MF.addLiveIn(Reg, &AMDGPU::SReg_32RegClass);
773 MF.addLiveIn(Reg, &AMDGPU::SReg_32RegClass);
779 MF.addLiveIn(Reg, &AMDGPU::SReg_32RegClass);
785 MF.addLiveIn(Re
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| H A D | SIAssignInterpRegs.cpp | 128 MRI.addLiveIn(physReg, virtReg);
129 MF->front().addLiveIn(physReg);
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| H A D | AMDGPUISelLowering.cpp | 321 MRI.addLiveIn(Reg, VirtualRegister);
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| /external/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyRegStackify.cpp | 227 MF.getRegInfo().addLiveIn(WebAssembly::EXPR_STACK);
229 MBB.addLiveIn(WebAssembly::EXPR_STACK);
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| /external/dexmaker/src/dx/java/com/android/dx/ssa/back/ |
| H A D | LivenessAnalyzer.java | 219 blockN.addLiveIn(regV);
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| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonCFGOptimizer.cpp | 219 LayoutSucc->addLiveIn(NewLI);
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| /external/llvm/lib/Target/Mips/ |
| H A D | Mips16FrameLowering.cpp | 131 EntryBlock->addLiveIn(Reg);
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| H A D | MipsSEISelDAGToDAG.cpp | 149 MF.getRegInfo().addLiveIn(Mips::T9_64);
150 MBB.addLiveIn(Mips::T9_64);
177 MF.getRegInfo().addLiveIn(Mips::T9);
178 MBB.addLiveIn(Mips::T9);
212 MF.getRegInfo().addLiveIn(Mips::V0);
213 MBB.addLiveIn(Mips::V0);
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| H A D | MipsSEFrameLowering.cpp | 487 MBB.addLiveIn(ABI.GetEhDataReg(I));
575 MBB.addLiveIn(Mips::COP013);
589 MBB.addLiveIn(Mips::COP014);
600 MBB.addLiveIn(Mips::COP012);
790 EntryBlock->addLiveIn(Reg);
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| /external/llvm/lib/Target/MSP430/ |
| H A D | MSP430FrameLowering.cpp | 78 I->addLiveIn(MSP430::FP);
200 MBB.addLiveIn(Reg);
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| /external/llvm/include/llvm/CodeGen/ |
| H A D | MachineBasicBlock.h | 345 void addLiveIn(MCPhysReg PhysReg, LaneBitmask LaneMask = ~0u) { function in class:llvm::MachineBasicBlock
348 void addLiveIn(const RegisterMaskPair &RegMaskPair) { function in class:llvm::MachineBasicBlock
353 /// this than repeatedly calling isLiveIn before calling addLiveIn for every
360 unsigned addLiveIn(MCPhysReg PhysReg, const TargetRegisterClass *RC);
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| H A D | MachineFunction.h | 351 /// addLiveIn - Add the specified physical register as a live-in value and
353 unsigned addLiveIn(unsigned PReg, const TargetRegisterClass *RC);
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| /external/llvm/lib/Target/SystemZ/ |
| H A D | SystemZFrameLowering.cpp | 121 MBB.addLiveIn(GPR64);
205 MBB.addLiveIn(Reg);
384 I->addLiveIn(SystemZ::R11D);
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| /external/llvm/lib/CodeGen/ |
| H A D | MachineRegisterInfo.cpp | 389 EntryMBB->addLiveIn(LiveIns[i].first);
393 EntryMBB->addLiveIn(LiveIns[i].first);
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| H A D | VirtRegMap.cpp | 280 MBB->addLiveIn(PhysReg, LaneMask);
310 MBB->addLiveIn(PhysReg);
317 // each MBB's LiveIns set before calling addLiveIn on them.
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| H A D | CallingConvLower.cpp | 246 unsigned VReg = MF.addLiveIn(PReg, RC);
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| H A D | MachineBasicBlock.cpp | 375 MachineBasicBlock::addLiveIn(MCPhysReg PhysReg, const TargetRegisterClass *RC) { function in class:MachineBasicBlock
402 addLiveIn(PhysReg);
861 NMBB->addLiveIn(LI);
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| H A D | MachineFunction.cpp | 466 unsigned MachineFunction::addLiveIn(unsigned PReg, function in class:MachineFunction
484 MRI.addLiveIn(PReg, VReg);
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| /external/llvm/lib/Target/Sparc/ |
| H A D | SparcFrameLowering.cpp | 342 MBB->addLiveIn(reg - SP::I0_I1 + SP::O0_O1);
348 MBB->addLiveIn(reg - SP::I0 + SP::O0);
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| /external/llvm/lib/Target/X86/ |
| H A D | X86FrameLowering.cpp | 1016 MBB.addLiveIn(Establisher);
1086 EveryMBB.addLiveIn(MachineFramePtr);
1221 MBB.addLiveIn(Establisher);
1880 MBB.addLiveIn(Reg);
1893 MBB.addLiveIn(Reg);
2085 allocMBB->addLiveIn(LI);
2086 checkMBB->addLiveIn(LI);
2090 allocMBB->addLiveIn(IsLP64 ? X86::R10 : X86::R10D);
2357 stackCheckMBB->addLiveIn(LI);
2358 incStackMBB->addLiveIn(L
[all...] |
| /external/llvm/lib/Target/XCore/ |
| H A D | XCoreFrameLowering.cpp | 262 MBB.addLiveIn(XCore::LR);
287 MBB.addLiveIn(SpillList[i].Reg);
438 MBB.addLiveIn(Reg);
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| /external/llvm/lib/Target/ARM/ |
| H A D | ARMFrameLowering.cpp | 925 MBB.addLiveIn(Reg);
1143 MBB.addLiveIn(SupReg);
1161 MBB.addLiveIn(SupReg);
1173 MBB.addLiveIn(SupReg);
1182 MBB.addLiveIn(NextReg);
1898 PredBB->addLiveIn(LI);
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| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64FrameLowering.cpp | 790 MBB.addLiveIn(Reg1);
791 MBB.addLiveIn(Reg2);
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