Searched defs:opcode (Results 1 - 22 of 22) sorted by relevance

/art/tools/dexfuzz/src/dexfuzz/rawdex/
H A DOpcodeInfo.java27 public final Opcode opcode; field in class:OpcodeInfo
35 public OpcodeInfo(Opcode opcode, String name, int opcodeValue, AbstractFormat fmt) { argument
36 this.opcode = opcode;
H A DInstruction.java117 // Remember the offset, so after reading the opcode, we can read the whole
123 Log.errorAndQuit("Couldn't find OpcodeInfo for opcode with value: "
170 int opcode = (firstCodeWord & 0xff);
172 if (opcode == 0x0 && upperBits != 0x0) {
193 return opcode;
300 public static OpcodeInfo getOpcodeInfo(Opcode opcode) { argument
301 return opcode_map_by_enum.get(opcode);
308 private static void addOpcodeInfo(Opcode opcode, String name, argument
310 OpcodeInfo info = new OpcodeInfo(opcode, name, opcodeValue, fmt);
311 if (opcode
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H A DOpcode.java277 public static boolean isBetween(Opcode opcode, Opcode opcode1, Opcode opcode2) { argument
278 return (opcode.ordinal() >= opcode1.ordinal() && opcode.ordinal() <= opcode2.ordinal());
/art/disassembler/
H A Ddisassembler_mips.cc419 std::string opcode; local
425 opcode = StringPrintf("op=%d fn=%d", op, function);
429 opcode = gMipsInstructions[i].name;
466 case 0: opcode += ".s"; break;
467 case 1: opcode += ".d"; break;
468 case 4: opcode += ".w"; break;
469 case 5: opcode += ".l"; break;
470 case 6: opcode += ".ps"; break;
471 default: opcode += ".?"; break;
567 << StringPrintf(": %08x\t%-7s ", instruction, opcode
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H A Ddisassembler_arm.cc252 std::string opcode; local
260 opcode = "bkpt";
267 opcode = (((instruction >> 5) & 1) ? "blx" : "bx");
274 opcode = kDataProcessingOperations[op];
313 opcode = StringPrintf("%s%s", (l ? "ldr" : "str"), (b ? "b" : ""));
343 opcode = StringPrintf("%s%c%c", (l ? "ldm" : "stm"), (u ? 'i' : 'd'), (p ? 'b' : 'a'));
350 opcode = (bl ? "bl" : "b");
357 opcode = "???";
360 opcode += kConditionCodeNames[cond];
361 opcode
503 std::ostringstream opcode; local
1603 std::ostringstream opcode; local
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/art/runtime/
H A Ddex_instruction.cc71 #define INSTRUCTION_SIZE(opcode, c, p, format, r, i, a, v) \
72 ((opcode == NOP) ? -1 : \
101 Code opcode = static_cast<Code>(insn & 0xFF); local
102 return FlagsOf(opcode) & Instruction::kContinue;
164 const char* opcode = kInstructionNames[Opcode()]; local
166 case k10x: os << opcode; break; local
167 case k12x: os << StringPrintf("%s v%d, v%d", opcode, VRegA_12x(), VRegB_12x()); break;
168 case k11n: os << StringPrintf("%s v%d, #%+d", opcode, VRegA_11n(), VRegB_11n()); break;
169 case k11x: os << StringPrintf("%s v%d", opcode, VRegA_11x()); break;
170 case k10t: os << StringPrintf("%s %+d", opcode, VRegA_10
387 os << opcode << " {"; local
404 os << opcode << " {"; local
418 os << opcode << " {"; local
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H A Ddex_instruction_utils.h54 constexpr bool IsInstructionDirectConst(Instruction::Code opcode) { argument
55 return Instruction::CONST_4 <= opcode && opcode <= Instruction::CONST_WIDE_HIGH16;
58 constexpr bool IsInstructionConstWide(Instruction::Code opcode) { argument
59 return Instruction::CONST_WIDE_16 <= opcode && opcode <= Instruction::CONST_WIDE_HIGH16;
62 constexpr bool IsInstructionReturn(Instruction::Code opcode) { argument
63 return Instruction::RETURN_VOID <= opcode && opcode <= Instruction::RETURN_OBJECT;
66 constexpr bool IsInstructionInvoke(Instruction::Code opcode) { argument
71 IsInstructionQuickInvoke(Instruction::Code opcode) argument
76 IsInstructionInvokeStatic(Instruction::Code opcode) argument
80 IsInstructionGoto(Instruction::Code opcode) argument
84 IsInstructionIfCc(Instruction::Code opcode) argument
88 IsInstructionIfCcZ(Instruction::Code opcode) argument
139 IsInvokeInstructionRange(Instruction::Code opcode) argument
146 InvokeInstructionType(Instruction::Code opcode) argument
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H A Ddex_file_verifier.cc1148 uint8_t opcode = *(ptr_++); local
1149 switch (opcode) {
1164 ErrorStringPrintf("Bad reg_num for opcode %x", opcode);
1187 ErrorStringPrintf("Bad reg_num for opcode %x", opcode);
1195 ErrorStringPrintf("Bad reg_num for opcode %x", opcode);
H A Ddex_instruction.h83 #define INSTRUCTION_ENUM(opcode, cname, p, f, r, i, a, v) cname = opcode,
150 kStore = 0x0080000, // store opcode
151 kLoad = 0x0100000, // load opcode
155 kExperimental = 0x1000000, // is an experimental opcode
240 // Returns the name of this instruction's opcode.
245 // Returns the name of the given opcode.
246 static const char* Name(Code opcode) { argument
247 return kInstructionNames[opcode];
409 // TODO(iam): Make this name more consistent with GetAllArgs25x by including the opcode forma
428 SetOpcode(Code opcode) argument
459 FormatOf(Code opcode) argument
464 IndexTypeOf(Code opcode) argument
469 FlagsOf(Code opcode) argument
474 VerifyFlagsOf(Code opcode) argument
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H A Ddex_file.cc908 uint8_t opcode = *stream++; local
909 switch (opcode) {
937 if (opcode == DBG_START_LOCAL_EXTENDED) {
993 address += (opcode - DBG_FIRST_SPECIAL) / DBG_LINE_RANGE;
1018 uint8_t opcode = *stream++; local
1019 switch (opcode) {
1055 int adjopcode = opcode - DBG_FIRST_SPECIAL;
/art/compiler/debug/dwarf/
H A Ddebug_line_opcode_writer.h30 // * Choose the most compact encoding of a given opcode.
161 // Compact address and line opcode.
180 int opcode = kOpcodeBase + (delta_line - kLineBase) + local
182 if (opcode > UINT8_MAX) {
185 opcode -= (kLineRange * const_advance);
186 if (opcode <= UINT8_MAX) {
191 // Still use the opcode to do line advance and copy.
192 opcode = kOpcodeBase + (delta_line - kLineBase);
195 DCHECK(kOpcodeBase <= opcode && opcode <
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/art/runtime/arch/x86/
H A Dfault_handler_x86.cc102 uint8_t opcode = *pc++; local
113 switch (opcode) {
134 opcode = *pc++;
143 if (x86_64 && opcode >= 0x40 && opcode <= 0x4f) {
144 opcode = *pc++;
147 if (opcode == 0x0f) {
148 // Two byte opcode
150 opcode = *pc++;
156 switch (opcode) {
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/art/runtime/quick/
H A Dinline_method_analyser.h199 InlineMethodOpcode opcode; member in struct:art::InlineMethod
224 static constexpr bool IsInstructionIGet(Instruction::Code opcode) { argument
225 return Instruction::IGET <= opcode && opcode <= Instruction::IGET_SHORT;
228 static constexpr bool IsInstructionIPut(Instruction::Code opcode) { argument
229 return Instruction::IPUT <= opcode && opcode <= Instruction::IPUT_SHORT;
232 static constexpr uint16_t IGetVariant(Instruction::Code opcode) { argument
233 return opcode - Instruction::IGET;
236 static constexpr uint16_t IPutVariant(Instruction::Code opcode) { argument
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H A Dinline_method_analyser.cc60 template <Instruction::Code opcode> bool Opcode();
112 template <Instruction::Code opcode>
114 return instruction_->Opcode() == opcode;
391 result->opcode = kInlineOpConstructor;
468 Instruction::Code opcode = instruction->Opcode(); local
470 switch (opcode) {
473 result->opcode = kInlineOpNop;
549 result->opcode = kInlineOpReturnArg;
586 result->opcode = kInlineOpNonWideConst;
599 Instruction::Code opcode local
664 Instruction::Code opcode = instruction->Opcode(); local
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/art/compiler/optimizing/
H A Dinstruction_builder.cc643 static InvokeType GetInvokeTypeFromOpCode(Instruction::Code opcode) { argument
644 switch (opcode) {
663 LOG(FATAL) << "Unexpected invoke opcode: " << opcode;
H A Dcode_generator_arm.cc3969 Opcode opcode) {
3972 CanEncodeConstantAsImmediate(constant->AsConstant(), opcode)) {
3979 Opcode opcode) {
3982 return CanEncodeConstantAsImmediate(Low32Bits(value), opcode) &&
3983 CanEncodeConstantAsImmediate(High32Bits(value), opcode);
3985 return CanEncodeConstantAsImmediate(Low32Bits(value), opcode);
3989 bool LocationsBuilderARM::CanEncodeConstantAsImmediate(uint32_t value, Opcode opcode) { argument
3992 if (assembler->ShifterOperandCanHold(kNoRegister, kNoRegister, opcode, value, &so)) {
3996 switch (opcode) {
5748 void LocationsBuilderARM::HandleBitwiseOperation(HBinaryOperation* instruction, Opcode opcode) { argument
3968 ArmEncodableConstantOrRegister(HInstruction* constant, Opcode opcode) argument
3978 CanEncodeConstantAsImmediate(HConstant* input_cst, Opcode opcode) argument
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/art/compiler/utils/arm/
H A Dassembler_arm.h886 Opcode opcode,
892 Opcode opcode,
895 return ShifterOperandCanHold(rd, rn, opcode, immediate, kCcDontCare, shifter_op);
890 ShifterOperandCanHold(Register rd, Register rn, Opcode opcode, uint32_t immediate, ShifterOperand* shifter_op) argument
H A Dassembler_arm32.cc58 Opcode opcode ATTRIBUTE_UNUSED,
575 Opcode opcode,
584 static_cast<int32_t>(opcode) << kOpcodeShift |
675 Shift opcode,
685 static_cast<int32_t>(opcode) << kShiftShift |
692 Shift opcode,
702 static_cast<int32_t>(opcode) << kShiftShift |
811 void Arm32Assembler::EmitMulOp(Condition cond, int32_t opcode, argument
819 int32_t encoding = opcode |
1135 void Arm32Assembler::EmitVFPsss(Condition cond, int32_t opcode, argument
573 EmitType01(Condition cond, int type, Opcode opcode, SetCc set_cc, Register rn, Register rd, const ShifterOperand& so) argument
674 EmitShiftImmediate(Condition cond, Shift opcode, Register rd, Register rm, const ShifterOperand& so) argument
691 EmitShiftRegister(Condition cond, Shift opcode, Register rd, Register rm, const ShifterOperand& so) argument
1153 EmitVFPddd(Condition cond, int32_t opcode, DRegister dd, DRegister dn, DRegister dm) argument
1171 EmitVFPsd(Condition cond, int32_t opcode, SRegister sd, DRegister dm) argument
1186 EmitVFPds(Condition cond, int32_t opcode, DRegister dd, SRegister sm) argument
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H A Dassembler_thumb2.cc515 Opcode opcode,
523 switch (opcode) {
1176 Opcode opcode,
1186 if ((opcode == ADD || opcode == SUB) && rn == SP && so.IsImmediate() && set_cc != kCcSet) {
1192 } else if (!IsHighRegister(rd) && opcode == ADD) {
1200 (opcode == CMP) ||
1201 (opcode == MOV && set_cc != kCcSet) ||
1202 ((opcode == ADD) && (rn == rd) && set_cc != kCcSet);
1209 // There are high register instructions available for this opcode
513 ShifterOperandCanHold(Register rd ATTRIBUTE_UNUSED, Register rn ATTRIBUTE_UNUSED, Opcode opcode, uint32_t immediate, SetCc set_cc, ShifterOperand* shifter_op) argument
1175 Is32BitDataProcessing(Condition cond, Opcode opcode, SetCc set_cc, Register rn, Register rd, const ShifterOperand& so) argument
1338 Emit32BitDataProcessing(Condition cond ATTRIBUTE_UNUSED, Opcode opcode, SetCc set_cc, Register rn, Register rd, const ShifterOperand& so) argument
1425 Emit16BitDataProcessing(Condition cond, Opcode opcode, SetCc set_cc, Register rn, Register rd, const ShifterOperand& so) argument
1616 Emit16BitAddSub(Condition cond, Opcode opcode, SetCc set_cc, Register rn, Register rd, const ShifterOperand& so) argument
1776 EmitDataProcessing(Condition cond, Opcode opcode, SetCc set_cc, Register rn, Register rd, const ShifterOperand& so) argument
1801 uint16_t opcode = 0; local
1822 uint16_t opcode = 0; local
1851 uint16_t opcode = 0; local
1868 uint16_t opcode = 0; local
3044 EmitVFPsss(Condition cond, int32_t opcode, SRegister sd, SRegister sn, SRegister sm) argument
3062 EmitVFPddd(Condition cond, int32_t opcode, DRegister dd, DRegister dn, DRegister dm) argument
3080 EmitVFPsd(Condition cond, int32_t opcode, SRegister sd, DRegister dm) argument
3095 EmitVFPds(Condition cond, int32_t opcode, DRegister dd, SRegister sm) argument
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/art/compiler/utils/mips/
H A Dassembler_mips.cc125 void MipsAssembler::EmitR(int opcode, Register rs, Register rt, Register rd, int shamt, int funct) { argument
129 uint32_t encoding = static_cast<uint32_t>(opcode) << kOpcodeShift |
138 void MipsAssembler::EmitI(int opcode, Register rs, Register rt, uint16_t imm) { argument
141 uint32_t encoding = static_cast<uint32_t>(opcode) << kOpcodeShift |
148 void MipsAssembler::EmitI21(int opcode, Register rs, uint32_t imm21) { argument
151 uint32_t encoding = static_cast<uint32_t>(opcode) << kOpcodeShift |
157 void MipsAssembler::EmitI26(int opcode, uint32_t imm26) { argument
159 uint32_t encoding = static_cast<uint32_t>(opcode) << kOpcodeShift | imm26;
163 void MipsAssembler::EmitFR(int opcode, int fmt, FRegister ft, FRegister fs, FRegister fd, argument
168 uint32_t encoding = static_cast<uint32_t>(opcode) << kOpcodeShif
177 EmitFI(int opcode, int fmt, FRegister ft, uint16_t imm) argument
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/art/compiler/utils/mips64/
H A Dassembler_mips64.cc91 void Mips64Assembler::EmitR(int opcode, GpuRegister rs, GpuRegister rt, GpuRegister rd, argument
96 uint32_t encoding = static_cast<uint32_t>(opcode) << kOpcodeShift |
105 void Mips64Assembler::EmitRsd(int opcode, GpuRegister rs, GpuRegister rd, argument
109 uint32_t encoding = static_cast<uint32_t>(opcode) << kOpcodeShift |
118 void Mips64Assembler::EmitRtd(int opcode, GpuRegister rt, GpuRegister rd, argument
122 uint32_t encoding = static_cast<uint32_t>(opcode) << kOpcodeShift |
131 void Mips64Assembler::EmitI(int opcode, GpuRegister rs, GpuRegister rt, uint16_t imm) { argument
134 uint32_t encoding = static_cast<uint32_t>(opcode) << kOpcodeShift |
141 void Mips64Assembler::EmitI21(int opcode, GpuRegister rs, uint32_t imm21) { argument
144 uint32_t encoding = static_cast<uint32_t>(opcode) << kOpcodeShif
150 EmitI26(int opcode, uint32_t imm26) argument
156 EmitFR(int opcode, int fmt, FpuRegister ft, FpuRegister fs, FpuRegister fd, int funct) argument
170 EmitFI(int opcode, int fmt, FpuRegister ft, uint16_t imm) argument
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/art/runtime/verifier/
H A Dmethod_verifier.cc958 Instruction::Code opcode = inst->Opcode(); local
959 switch (opcode) {
1202 Fail(VERIFY_ERROR_BAD_CLASS_HARD) << "unexpected opcode " << inst->Name();
1207 Fail(VERIFY_ERROR_BAD_CLASS_HARD) << "opcode only expected at runtime " << inst->Name();
1332 // Make sure the array-data is marked as an opcode. This ensures that it was reached when
1445 // Make sure the switch data is marked as an opcode. This ensures that it was reached when
1943 Instruction::Code opcode = ret_inst->Opcode(); local
1945 switch (opcode) {
1961 LOG(FATAL) << "Unknown return opcode " << opcode;
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