| /external/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 52 /// AssertSext, AssertZext - These nodes record if a register contains a
57 AssertSext, AssertZext, enumerator in enum:llvm::ISD::NodeType
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeIntegerTypes.cpp | 54 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
177 return DAG.getNode(ISD::AssertZext, SDLoc(N),
431 ISD::AssertZext : ISD::AssertSext, dl, NVT, Res,
1308 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
1870 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi,
1874 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT));
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| H A D | SelectionDAGDumper.cpp | 86 case ISD::AssertZext: return "AssertZext";
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| H A D | TargetLowering.cpp | 1051 case ISD::AssertZext: {
1052 // AssertZext demands all of the high bits, plus any of the low bits
1612 if (Op0.getOpcode() == ISD::AssertZext &&
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| H A D | SelectionDAGBuilder.cpp | 110 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
255 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
700 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
4238 case ISD::AssertZext:
7226 AssertOp = ISD::AssertZext;
7484 AssertOp = ISD::AssertZext;
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| H A D | SelectionDAG.cpp | 2347 case ISD::AssertZext: {
2538 case ISD::AssertZext:
3579 case ISD::AssertZext: {
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| H A D | SelectionDAGISel.cpp | 2625 case ISD::AssertZext:
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| H A D | LegalizeDAG.cpp | 1002 Result = DAG.getNode(ISD::AssertZext, dl,
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| H A D | DAGCombiner.cpp | 984 case ISD::AssertZext:
985 return DAG.getNode(ISD::AssertZext, dl, PVT,
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| /external/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 706 Arg = DAG.getNode(ISD::AssertZext, DL, Arg.getValueType(), Arg,
1020 return DAG.getNode(ISD::AssertZext, SL, MVT::i32, TFI,
1142 return DAG.getNode(ISD::AssertZext, SL, MVT::i32, Param,
2281 if (Op.getOpcode() == ISD::AssertZext)
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| /external/llvm/lib/Target/BPF/ |
| H A D | BPFISelLowering.cpp | 230 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue,
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| /external/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 474 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
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| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelDAGToDAG.cpp | 1516 case ISD::AssertZext:
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| /external/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 2863 Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val,
2924 Val = DAG.getNode(ISD::AssertZext, DL, LocVT, Val, DAG.getValueType(ValVT));
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| /external/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 635 Arg = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Arg,
1357 RV = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), RV,
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| /external/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 3200 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
10552 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
10555 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
10558 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
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| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 3030 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
4340 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
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| /external/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 811 Value = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Value,
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| /external/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 2743 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
11497 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11512 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11653 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 9207 case ISD::AssertZext: {
|