/external/swiftshader/third_party/LLVM/include/llvm/MC/ |
H A D | MCInstrAnalysis.h | 31 virtual bool isBranch(const MCInst &Inst) const { 32 return Info->get(Inst.getOpcode()).isBranch(); 35 virtual bool isConditionalBranch(const MCInst &Inst) const { 36 return Info->get(Inst.getOpcode()).isBranch(); 39 virtual bool isUnconditionalBranch(const MCInst &Inst) const { 40 return Info->get(Inst.getOpcode()).isUnconditionalBranch(); 43 virtual bool isIndirectBranch(const MCInst &Inst) const { 44 return Info->get(Inst.getOpcode()).isIndirectBranch(); 47 virtual bool isCall(const MCInst &Inst) const { 48 return Info->get(Inst [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/X86/ |
H A D | X86GenInstrInfo.inc | 4184 { 0, 0, 0, 0, 0, "PHI", 0|(1<<MCID::Pseudo)|(1<<MCID::Variadic)|(1<<MCID::UnmodeledSideEffects), 0x0ULL, NULL, NULL, 0 }, // Inst #0 = PHI
4185 { 1, 0, 0, 0, 0, "INLINEASM", 0|(1<<MCID::Pseudo)|(1<<MCID::Variadic), 0x0ULL, NULL, NULL, 0 }, // Inst #1 = INLINEASM
4186 { 2, 1, 0, 0, 0, "PROLOG_LABEL", 0|(1<<MCID::Pseudo)|(1<<MCID::NotDuplicable)|(1<<MCID::UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo2 }, // Inst #2 = PROLOG_LABEL
4187 { 3, 1, 0, 0, 0, "EH_LABEL", 0|(1<<MCID::Pseudo)|(1<<MCID::NotDuplicable)|(1<<MCID::UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo2 }, // Inst #3 = EH_LABEL
4188 { 4, 1, 0, 0, 0, "GC_LABEL", 0|(1<<MCID::Pseudo)|(1<<MCID::NotDuplicable)|(1<<MCID::UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo2 }, // Inst #4 = GC_LABEL
4189 { 5, 0, 0, 0, 0, "KILL", 0|(1<<MCID::Pseudo)|(1<<MCID::Variadic), 0x0ULL, NULL, NULL, 0 }, // Inst #5 = KILL
4190 { 6, 3, 1, 0, 0, "EXTRACT_SUBREG", 0|(1<<MCID::Pseudo), 0x0ULL, NULL, NULL, OperandInfo3 }, // Inst #6 = EXTRACT_SUBREG
4191 { 7, 4, 1, 0, 0, "INSERT_SUBREG", 0|(1<<MCID::Pseudo), 0x0ULL, NULL, NULL, OperandInfo4 }, // Inst #7 = INSERT_SUBREG
4192 { 8, 1, 1, 0, 0, "IMPLICIT_DEF", 0|(1<<MCID::Pseudo)|(1<<MCID::Rematerializable)|(1<<MCID::CheapAsAMove), 0x0ULL, NULL, NULL, OperandInfo5 }, // Inst #8 = IMPLICIT_DEF
4193 { 9, 4, 1, 0, 0, "SUBREG_TO_REG", 0|(1<<MCID::Pseudo), 0x0ULL, NULL, NULL, OperandInfo6 }, // Inst # [all...] |
/external/llvm/lib/MC/ |
H A D | MCInstrAnalysis.cpp | 13 bool MCInstrAnalysis::evaluateBranch(const MCInst &Inst, uint64_t Addr, argument 15 if (Inst.getNumOperands() == 0 || 16 Info->get(Inst.getOpcode()).OpInfo[0].OperandType != MCOI::OPERAND_PCREL) 19 int64_t Imm = Inst.getOperand(0).getImm();
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/external/swiftshader/third_party/LLVM/lib/MC/ |
H A D | MCInstrAnalysis.cpp | 13 uint64_t MCInstrAnalysis::evaluateBranch(const MCInst &Inst, uint64_t Addr, argument 15 if (Inst.getNumOperands() == 0 || 16 Info->get(Inst.getOpcode()).OpInfo[0].OperandType != MCOI::OPERAND_PCREL) 19 int64_t Imm = Inst.getOperand(0).getImm();
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/external/llvm/include/llvm/MC/ |
H A D | MCInstrAnalysis.h | 34 virtual bool isBranch(const MCInst &Inst) const { 35 return Info->get(Inst.getOpcode()).isBranch(); 38 virtual bool isConditionalBranch(const MCInst &Inst) const { 39 return Info->get(Inst.getOpcode()).isConditionalBranch(); 42 virtual bool isUnconditionalBranch(const MCInst &Inst) const { 43 return Info->get(Inst.getOpcode()).isUnconditionalBranch(); 46 virtual bool isIndirectBranch(const MCInst &Inst) const { 47 return Info->get(Inst.getOpcode()).isIndirectBranch(); 50 virtual bool isCall(const MCInst &Inst) const { 51 return Info->get(Inst [all...] |
H A D | MCInstBuilder.h | 23 MCInst Inst; member in class:llvm::MCInstBuilder 28 Inst.setOpcode(Opcode); 33 Inst.addOperand(MCOperand::createReg(Reg)); 39 Inst.addOperand(MCOperand::createImm(Val)); 45 Inst.addOperand(MCOperand::createFPImm(Val)); 51 Inst.addOperand(MCOperand::createExpr(Val)); 57 Inst.addOperand(MCOperand::createInst(Val)); 63 Inst.addOperand(Op); 68 return Inst;
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/external/llvm/lib/Target/XCore/Disassembler/ |
H A D | XCoreDisassembler.cpp | 76 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst, 81 static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst, 86 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val, 89 static DecodeStatus DecodeNegImmOperand(MCInst &Inst, unsigned Val, 92 static DecodeStatus Decode2RInstruction(MCInst &Inst, 97 static DecodeStatus Decode2RImmInstruction(MCInst &Inst, 102 static DecodeStatus DecodeR2RInstruction(MCInst &Inst, 107 static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst, 112 static DecodeStatus DecodeRUSInstruction(MCInst &Inst, 117 static DecodeStatus DecodeRUSBitpInstruction(MCInst &Inst, 199 DecodeGRRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 211 DecodeRRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 223 DecodeBitpOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 234 DecodeNegImmOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 275 Decode2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 345 Decode2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 358 Decode2RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 371 DecodeR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 384 Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 398 DecodeRUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 411 DecodeRUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 424 DecodeRUSSrcDstBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 438 DecodeL2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 509 DecodeL2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 523 DecodeLR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 537 Decode3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 550 Decode3RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 563 Decode2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 576 Decode2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 589 DecodeL3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 603 DecodeL3RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 618 DecodeL2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 632 DecodeL2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 646 DecodeL6RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 666 DecodeL5RInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 680 DecodeL5RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 700 DecodeL4RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 719 DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument [all...] |
/external/llvm/lib/Target/AArch64/ |
H A D | AArch64AddressTypePromotion.cpp | 108 /// - Inst is used only once (no need to insert truncate). 109 /// - Inst has only one operand that will require a sext operation (we do 111 bool shouldGetThrough(const Instruction *Inst); 119 bool canGetThrough(const Instruction *Inst); 156 bool AArch64AddressTypePromotion::canGetThrough(const Instruction *Inst) { argument 157 if (isa<SExtInst>(Inst)) 160 const BinaryOperator *BinOp = dyn_cast<BinaryOperator>(Inst); 166 if (isa<TruncInst>(Inst) && isa<SExtInst>(Inst->getOperand(0))) { 167 const Instruction *Opnd = cast<Instruction>(Inst 179 shouldGetThrough(const Instruction *Inst) argument 208 shouldSExtOperand(const Instruction *Inst, int OpIdx) argument 390 << *Inst << '\\n'); local 439 const Instruction *Inst = dyn_cast<GetElementPtrInst>(U); local 450 Instruction *Inst = SExt; local [all...] |
/external/swiftshader/third_party/LLVM/lib/Transforms/Scalar/ |
H A D | EarlyCSE.cpp | 47 Instruction *Inst; member in struct:__anon18925::SimpleValue 49 SimpleValue(Instruction *I) : Inst(I) { 50 assert((isSentinel() || canHandle(I)) && "Inst can't be handled!"); 54 return Inst == DenseMapInfo<Instruction*>::getEmptyKey() || 55 Inst == DenseMapInfo<Instruction*>::getTombstoneKey(); 58 static bool canHandle(Instruction *Inst) { argument 60 if (CallInst *CI = dyn_cast<CallInst>(Inst)) 62 return isa<CastInst>(Inst) || isa<BinaryOperator>(Inst) || 63 isa<GetElementPtrInst>(Inst) || is 90 Instruction *Inst = Val.Inst; local 140 Instruction *Inst; member in struct:__anon18926::CallValue 151 canHandle(Instruction *Inst) argument 182 Instruction *Inst = Val.Inst; local 318 Instruction *Inst = I++; local 423 << *Inst << '\\n'); local [all...] |
H A D | Sink.cpp | 56 bool AllUsesDominatedByBlock(Instruction *Inst, BasicBlock *BB) const; 71 bool Sinking::AllUsesDominatedByBlock(Instruction *Inst, argument 77 for (Value::use_iterator I = Inst->use_begin(), 78 E = Inst->use_end(); I != E; ++I) { 134 Instruction *Inst = I; // The instruction to sink. local 142 if (isa<DbgInfoIntrinsic>(Inst)) 145 if (SinkInstruction(Inst, Stores)) 154 static bool isSafeToMove(Instruction *Inst, AliasAnalysis *AA, argument 157 if (Inst->mayWriteToMemory()) { 158 Stores.insert(Inst); 178 SinkInstruction(Instruction *Inst, SmallPtrSet<Instruction *, 8> &Stores) argument [all...] |
/external/llvm/lib/Analysis/ |
H A D | CFLGraph.h | 225 void visitReturnInst(ReturnInst &Inst) { argument 226 if (auto RetVal = Inst.getReturnValue()) { 234 void visitPtrToIntInst(PtrToIntInst &Inst) { argument 235 auto *Ptr = Inst.getOperand(0); 239 void visitIntToPtrInst(IntToPtrInst &Inst) { argument 240 auto *Ptr = &Inst; 244 void visitCastInst(CastInst &Inst) { argument 245 auto *Src = Inst.getOperand(0); 246 addAssignEdge(Src, &Inst); 249 void visitBinaryOperator(BinaryOperator &Inst) { argument 256 visitAtomicCmpXchgInst(AtomicCmpXchgInst &Inst) argument 262 visitAtomicRMWInst(AtomicRMWInst &Inst) argument 268 visitPHINode(PHINode &Inst) argument 273 visitGetElementPtrInst(GetElementPtrInst &Inst) argument 278 visitSelectInst(SelectInst &Inst) argument 290 visitAllocaInst(AllocaInst &Inst) argument 292 visitLoadInst(LoadInst &Inst) argument 298 visitStoreInst(StoreInst &Inst) argument 304 visitVAArgInst(VAArgInst &Inst) argument 363 auto Inst = CS.getInstruction(); local 419 visitExtractElementInst(ExtractElementInst &Inst) argument 425 visitInsertElementInst(InsertElementInst &Inst) argument 432 visitLandingPadInst(LandingPadInst &Inst) argument 439 visitInsertValueInst(InsertValueInst &Inst) argument 446 visitExtractValueInst(ExtractValueInst &Inst) argument 451 visitShuffleVectorInst(ShuffleVectorInst &Inst) argument 476 hasUsefulEdges(Instruction *Inst) argument 499 addInstructionToGraph(GetEdgesVisitor &Visitor, Instruction &Inst) argument [all...] |
H A D | OrderedBasicBlock.cpp | 37 const Instruction *Inst = nullptr; local 49 Inst = cast<Instruction>(II); 50 NumberedInsts[Inst] = NextInstPos++; 51 if (Inst == A || Inst == B) 56 assert((Inst == A || Inst == B) && "Should find A or B"); 58 return Inst == A;
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/external/swiftshader/third_party/LLVM/utils/TableGen/ |
H A D | InstrInfoEmitter.cpp | 52 InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) { argument 55 for (unsigned i = 0, e = Inst.Operands.size(); i != e; ++i) { 64 DagInit *MIOI = Inst.Operands[i].MIOperandInfo; 68 OperandList.push_back(Inst.Operands[i]); 70 for (unsigned j = 0, e = Inst.Operands[i].MINumOperands; j != e; ++j) { 71 OperandList.push_back(Inst.Operands[i]); 101 if (Inst.Operands[i].Rec->isSubClassOf("PredicateOperand")) 106 if (Inst.Operands[i].Rec->isSubClassOf("OptionalDefOperand")) 113 Inst.Operands[i].Constraints[j]; 126 assert(!Inst 186 Record *Inst = (*II)->TheDef; local 252 emitRecord(const CodeGenInstruction &Inst, unsigned Num, Record *InstrInfo, std::map<std::vector<Record*>, unsigned> &EmittedLists, const OperandInfoMapTy &OpInfo, raw_ostream &OS) argument [all...] |
/external/llvm/lib/Target/SystemZ/Disassembler/ |
H A D | SystemZDisassembler.cpp | 77 static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo, argument 83 Inst.addOperand(MCOperand::createReg(RegNo)); 87 static DecodeStatus DecodeGR32BitRegisterClass(MCInst &Inst, uint64_t RegNo, 90 return decodeRegisterClass(Inst, RegNo, SystemZMC::GR32Regs, 16); 93 static DecodeStatus DecodeGRH32BitRegisterClass(MCInst &Inst, uint64_t RegNo, 96 return decodeRegisterClass(Inst, RegNo, SystemZMC::GRH32Regs, 16); 99 static DecodeStatus DecodeGR64BitRegisterClass(MCInst &Inst, uint64_t RegNo, 102 return decodeRegisterClass(Inst, RegNo, SystemZMC::GR64Regs, 16); 105 static DecodeStatus DecodeGR128BitRegisterClass(MCInst &Inst, uint64_t RegNo, 108 return decodeRegisterClass(Inst, RegN [all...] |
/external/swiftshader/third_party/LLVM/lib/MC/MCDisassembler/ |
H A D | EDOperand.cpp | 28 Inst(inst), 127 uint8_t operandType = Inst.ThisInstInfo->operandTypes[OpIndex]; 138 result = Inst.Inst->getOperand(MCOpIndex).getImm(); 142 unsigned reg = Inst.Inst->getOperand(MCOpIndex).getReg(); 147 int64_t displacement = Inst.Inst->getOperand(MCOpIndex).getImm(); 162 unsigned baseReg = Inst.Inst [all...] |
/external/llvm/lib/Transforms/Scalar/ |
H A D | Sink.cpp | 37 static bool AllUsesDominatedByBlock(Instruction *Inst, BasicBlock *BB, argument 43 for (Use &U : Inst->uses()) { 60 static bool isSafeToMove(Instruction *Inst, AliasAnalysis &AA, argument 63 if (Inst->mayWriteToMemory()) { 64 Stores.insert(Inst); 68 if (LoadInst *L = dyn_cast<LoadInst>(Inst)) { 75 if (isa<TerminatorInst>(Inst) || isa<PHINode>(Inst) || Inst->isEHPad() || 76 Inst 95 IsAcceptableTarget(Instruction *Inst, BasicBlock *SuccToSinkTo, DominatorTree &DT, LoopInfo &LI) argument 139 SinkInstruction(Instruction *Inst, SmallPtrSetImpl<Instruction *> &Stores, DominatorTree &DT, LoopInfo &LI, AAResults &AA) argument 218 Instruction *Inst = &*I; // The instruction to sink. local [all...] |
H A D | EarlyCSE.cpp | 55 Instruction *Inst; member in struct:__anon13341::SimpleValue 57 SimpleValue(Instruction *I) : Inst(I) { 58 assert((isSentinel() || canHandle(I)) && "Inst can't be handled!"); 62 return Inst == DenseMapInfo<Instruction *>::getEmptyKey() || 63 Inst == DenseMapInfo<Instruction *>::getTombstoneKey(); 66 static bool canHandle(Instruction *Inst) { argument 68 if (CallInst *CI = dyn_cast<CallInst>(Inst)) 70 return isa<CastInst>(Inst) || isa<BinaryOperator>(Inst) || 71 isa<GetElementPtrInst>(Inst) || is 93 Instruction *Inst = Val.Inst; local 184 Instruction *Inst; member in struct:__anon13342::CallValue 195 canHandle(Instruction *Inst) argument 222 Instruction *Inst = Val.Inst; local 290 LoadValue(Instruction *Inst, unsigned Generation, unsigned MatchingId, bool IsAtomic, bool IsInvariant) argument 386 ParseMemoryInst(Instruction *Inst, const TargetTransformInfo &TTI) argument 476 Instruction *Inst; member in class:__anon13343::EarlyCSE::ParseMemoryInst 481 getOrCreateResult(Value *Inst, Type *ExpectedType) const argument 545 Instruction *Inst = &*I++; local 756 << " due to: " << *Inst << '\\n'); local [all...] |
/external/llvm/lib/CodeGen/GlobalISel/ |
H A D | IRTranslator.cpp | 64 bool IRTranslator::translateBinaryOp(unsigned Opcode, const Instruction &Inst) { argument 69 unsigned Op0 = getOrCreateVReg(*Inst.getOperand(0)); 70 unsigned Op1 = getOrCreateVReg(*Inst.getOperand(1)); 71 unsigned Res = getOrCreateVReg(Inst); 72 MIRBuilder.buildInstr(Opcode, Inst.getType(), Res, Op0, Op1); 76 bool IRTranslator::translateReturn(const Instruction &Inst) { argument 77 assert(isa<ReturnInst>(Inst) && "Return expected"); 78 const Value *Ret = cast<ReturnInst>(Inst).getReturnValue(); 85 bool IRTranslator::translateBr(const Instruction &Inst) { argument 86 assert(isa<BranchInst>(Inst) 102 translate(const Instruction &Inst) argument [all...] |
/external/swiftshader/third_party/LLVM/tools/llvm-objdump/ |
H A D | MCFunction.cpp | 55 MCInst Inst; local 56 if (DisAsm->getInstruction(Inst, Size, Region, Index, DebugOut, nulls())){ 57 Instructions.push_back(MCDecodedInst(Index, Size, Inst)); 58 if (Ana->isBranch(Inst)) { 59 uint64_t targ = Ana->evaluateBranch(Inst, Index, Size); 72 } else if (Ana->isReturn(Inst)) { 76 } else if (Ana->isCall(Inst)) { 77 uint64_t targ = Ana->evaluateBranch(Inst, Index, Size); 116 const MCDecodedInst &Inst = BB.getInsts().back(); local 118 if (Ana->isBranch(Inst [all...] |
/external/llvm/lib/Target/Mips/Disassembler/ |
H A D | MipsDisassembler.cpp | 71 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 76 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 81 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 86 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 91 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, 96 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 101 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 106 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 111 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 116 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 403 DecodeUImmWithOffset(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder) argument 1126 DecodeCPU16RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1135 DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1148 DecodeGPRMM16RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1159 DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1170 DecodeGPRMM16MovePRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1181 DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1192 DecodePtrRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1202 DecodeDSPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1209 DecodeFGR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1221 DecodeFGR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1233 DecodeCCRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1244 DecodeFCCRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1255 DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1266 DecodeMem(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1288 DecodeMemEVA(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1309 DecodeLoadByte9(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1327 DecodeLoadByte15(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1345 DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1362 DecodeCacheOpMM(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1379 DecodePrefeOpMM(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1396 DecodeCacheeOp_CacheOpR6(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1413 DecodeStoreEvaOpMM(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1431 DecodeSyncI(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1446 DecodeSynciR6(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1461 DecodeMSA128Mem(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1507 DecodeMemMMImm4(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1565 DecodeMemMMSPImm5Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1581 DecodeMemMMGPImm7Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1597 DecodeMemMMReglistImm4Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1622 DecodeMemMMImm9(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1643 DecodeMemMMImm12(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1679 DecodeMemMMImm16(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1697 DecodeFMem(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1715 DecodeFMemMMR2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1733 DecodeFMem2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1751 DecodeFMem3(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1769 DecodeFMemCop2R6(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1787 DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1803 DecodeSpecial3LlSc(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1825 DecodeHWRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1836 DecodeAFGR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1849 DecodeACC64DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1861 DecodeHI32DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1873 DecodeLO32DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1885 DecodeMSA128BRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1897 DecodeMSA128HRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1909 DecodeMSA128WRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1921 DecodeMSA128DRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1933 DecodeMSACtrlRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1945 DecodeCOP0RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1957 DecodeCOP2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1969 DecodeBranchTarget(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder) argument 1978 DecodeBranchTarget1SImm16(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder) argument 1987 DecodeJumpTarget(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1997 DecodeBranchTarget21(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder) argument 2007 DecodeBranchTarget21MM(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder) argument 2017 DecodeBranchTarget26(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder) argument 2027 DecodeBranchTarget7MM(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder) argument 2036 DecodeBranchTarget10MM(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder) argument 2045 DecodeBranchTargetMM(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder) argument 2054 DecodeBranchTarget26MM(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder) argument 2064 DecodeJumpTargetMM(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2073 DecodeAddiur2Simm7(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder) argument 2086 DecodeLi16Imm(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder) argument 2097 DecodePOOL16BEncodedField(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder) argument 2106 DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder) argument 2116 DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder) argument 2124 DecodeInsSize(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2135 DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2141 DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2147 DecodeSimm9SP(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2161 DecodeANDI16Imm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2200 DecodeRegListOperand16(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2224 DecodeMovePRegPair(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2269 DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument [all...] |
/external/llvm/lib/Target/Lanai/MCTargetDesc/ |
H A D | LanaiMCCodeEmitter.cpp | 52 uint64_t getBinaryCodeForInstr(const MCInst &Inst, 58 unsigned getMachineOpValue(const MCInst &Inst, const MCOperand &MCOp, 62 unsigned getRiMemoryOpValue(const MCInst &Inst, unsigned OpNo, 66 unsigned getRrMemoryOpValue(const MCInst &Inst, unsigned OpNo, 70 unsigned getSplsOpValue(const MCInst &Inst, unsigned OpNo, 74 unsigned getBranchTargetOpValue(const MCInst &Inst, unsigned OpNo, 78 unsigned getCallTargetOpValue(const MCInst &Inst, unsigned OpNo, 82 void encodeInstruction(const MCInst &Inst, raw_ostream &Ostream, 86 unsigned adjustPqBitsRmAndRrm(const MCInst &Inst, unsigned Value, 89 unsigned adjustPqBitsSpls(const MCInst &Inst, unsigne 112 getMachineOpValue( const MCInst &Inst, const MCOperand &MCOp, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &SubtargetInfo) const argument 138 adjustPqBits(const MCInst &Inst, unsigned Value, unsigned PBitShift, unsigned QBitShift) argument 164 adjustPqBitsRmAndRrm(const MCInst &Inst, unsigned Value, const MCSubtargetInfo &STI) const argument 170 adjustPqBitsSpls(const MCInst &Inst, unsigned Value, const MCSubtargetInfo &STI) const argument 175 encodeInstruction( const MCInst &Inst, raw_ostream &Ostream, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &SubtargetInfo) const argument 188 getRiMemoryOpValue( const MCInst &Inst, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &SubtargetInfo) const argument 220 getRrMemoryOpValue( const MCInst &Inst, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &SubtargetInfo) const argument 259 getSplsOpValue(const MCInst &Inst, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &SubtargetInfo) const argument 291 getCallTargetOpValue( const MCInst &Inst, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &SubtargetInfo) const argument 304 getBranchTargetOpValue( const MCInst &Inst, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &SubtargetInfo) const argument [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/ARM/Disassembler/ |
H A D | ARMDisassembler.cpp | 106 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 108 static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, 111 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 113 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 115 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 117 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 119 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 121 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 123 static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, 127 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigne 851 DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 862 DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 868 DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 875 DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 905 DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 922 DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 943 DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 953 DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 961 DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 976 DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 987 DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 1001 DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 1010 DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 1019 DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 1056 DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 1091 DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 1126 DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 1143 DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 1160 DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 1181 DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1336 DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1439 DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 1480 DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1591 DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1620 DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1705 DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1745 DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1785 DecodeT2MOVTWInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1809 DecodeArmMOVTWInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1835 DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1863 DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 1883 DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 1902 DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 1908 DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1932 DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 1938 DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 1955 DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2204 DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2454 DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2493 DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2529 DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2564 DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2617 DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2662 DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2681 DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 2687 DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 2693 DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 2699 DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 2705 DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2736 DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder) argument 2760 DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 2766 DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 2772 DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 2778 DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 2793 DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 2807 DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 2817 DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 2825 DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 2842 DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2897 DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 2906 DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 2921 DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val, uint64_t Address, const void *Decoder) argument 2936 DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 2949 DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 2980 DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3010 DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3025 DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder) argument 3036 DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder) argument 3061 DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder) argument 3072 DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3085 DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3094 DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3104 DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3120 DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3162 DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3194 DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3200 DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3206 DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3226 DecodeMSRMask(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3233 DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3256 DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3283 DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3308 DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3336 DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3361 DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3386 DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3445 DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3503 DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3570 DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3634 DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3704 DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3768 DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3842 DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3907 DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3933 DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3959 DecodeIT(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3986 DecodeT2LDRDPreInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4023 DecodeT2STRDPreInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4057 DecodeT2Adr(llvm::MCInst &Inst, uint32_t Insn, uint64_t Address, const void *Decoder) argument 4072 DecodeT2ShifterImmOperand(llvm::MCInst &Inst, uint32_t Val, uint64_t Address, const void *Decoder) argument [all...] |
/external/llvm/lib/Target/ARM/Disassembler/ |
H A D | ARMDisassembler.cpp | 141 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 143 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, 146 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst, 149 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 151 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 153 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 155 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 157 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 159 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 161 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigne 881 DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 892 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 905 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 919 DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 931 DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 946 DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 976 DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1001 DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1022 DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1037 DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1045 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1060 DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1080 DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1101 DecodeDPairSpacedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1113 DecodePredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 1127 DecodeCCOutOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 1136 DecodeSORegImmOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 1173 DecodeSORegRegOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 1208 DecodeRegListOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 1245 DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 1269 DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 1294 DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 1321 DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1471 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1576 DecodeSORegMemOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 1620 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1811 DecodeRFEInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1840 DecodeQADDInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1863 DecodeMemMultipleWritebackInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1955 DecodeHINTInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1977 DecodeCPSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2024 DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2066 DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2090 DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2117 DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2145 DecodeTSTInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2166 DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2194 DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 2214 DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 2234 DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 2254 DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 2260 DecodeT2BInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2287 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2313 DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 2330 DecodeVLDInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2604 DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2617 DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2632 DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2645 DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2655 DecodeVSTInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2926 DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2973 DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3021 DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3056 DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3109 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3154 DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3173 DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3179 DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3185 DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3191 DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3197 DecodeTBLInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3233 DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder) argument 3257 DecodeThumbBROperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3265 DecodeT2BROperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3273 DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3281 DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3296 DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3310 DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3320 DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3328 DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3356 DecodeT2LoadShift(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3438 DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, uint64_t Address, const void* Decoder) argument 3522 DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, uint64_t Address, const void* Decoder) argument 3602 DecodeT2LoadT(MCInst &Inst, unsigned Insn, uint64_t Address, const void* Decoder) argument 3641 DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, uint64_t Address, const void* Decoder) argument 3694 DecodeT2Imm8S4(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3708 DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3723 DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, uint64_t Address, const void *Decoder) argument 3738 DecodeT2Imm8(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3751 DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3797 DecodeT2LdStPre(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3858 DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3884 DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder) argument 3895 DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder) argument 3920 DecodeThumbCPS(MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder) argument 3931 DecodePostIdxReg(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3944 DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3968 DecodeCoprocessor(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3984 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4000 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4042 DecodeT2SOImm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 4074 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 4082 DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 4105 DecodeMemBarrierOption(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 4114 DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 4123 DecodeMSRMask(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 4204 DecodeBankedReg(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 4227 DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4248 DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4273 DecodeLDRPreImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4298 DecodeLDRPreReg(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4326 DecodeSTRPreImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4351 DecodeSTRPreReg(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4376 DecodeVLD1LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4443 DecodeVST1LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4509 DecodeVLD2LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4576 DecodeVST2LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4640 DecodeVLD3LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4710 DecodeVST3LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4774 DecodeVLD4LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4855 DecodeVST4LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4927 DecodeVMOVSRR(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4953 DecodeVMOVRRS(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4979 DecodeIT(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4999 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 5036 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 5070 DecodeT2Adr(MCInst &Inst, uint32_t Insn, uint64_t Address, const void *Decoder) argument 5085 DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, uint64_t Address, const void *Decoder) argument 5096 DecodeSwap(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 5123 DecodeVCVTD(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 5182 DecodeVCVTQ(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 5241 DecodeLDR(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 5268 DecoderForMRRC2AndMCRR2(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument [all...] |
/external/llvm/lib/Transforms/ObjCARC/ |
H A D | DependencyAnalysis.h | 62 Depends(DependenceKind Flavor, Instruction *Inst, const Value *Arg, 67 bool CanUse(const Instruction *Inst, const Value *Ptr, ProvenanceAnalysis &PA, 72 bool CanAlterRefCount(const Instruction *Inst, const Value *Ptr, 75 /// Returns true if we can not conservatively prove that Inst can not decrement 77 bool CanDecrementRefCount(const Instruction *Inst, const Value *Ptr, 80 static inline bool CanDecrementRefCount(const Instruction *Inst, argument 83 return CanDecrementRefCount(Inst, Ptr, PA, GetARCInstKind(Inst));
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/external/llvm/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 192 bool validatetLDMRegList(const MCInst &Inst, const OperandVector &Operands, 194 bool validatetSTMRegList(const MCInst &Inst, const OperandVector &Operands, 351 void cvtThumbMultiply(MCInst &Inst, const OperandVector &); 352 void cvtThumbBranches(MCInst &Inst, const OperandVector &); 354 bool validateInstruction(MCInst &Inst, const OperandVector &Ops); 355 bool processInstruction(MCInst &Inst, const OperandVector &Ops, MCStreamer &Out); 396 unsigned checkTargetMatchPredicate(MCInst &Inst) override; 1739 void addExpr(MCInst &Inst, const MCExpr *Expr) const { argument 1742 Inst.addOperand(MCOperand::createImm(0)); 1744 Inst 1749 addARMBranchTargetOperands(MCInst &Inst, unsigned N) const argument 1754 addThumbBranchTargetOperands(MCInst &Inst, unsigned N) const argument 1759 addCondCodeOperands(MCInst &Inst, unsigned N) const argument 1766 addCoprocNumOperands(MCInst &Inst, unsigned N) const argument 1771 addCoprocRegOperands(MCInst &Inst, unsigned N) const argument 1776 addCoprocOptionOperands(MCInst &Inst, unsigned N) const argument 1781 addITMaskOperands(MCInst &Inst, unsigned N) const argument 1786 addITCondCodeOperands(MCInst &Inst, unsigned N) const argument 1791 addCCOutOperands(MCInst &Inst, unsigned N) const argument 1796 addRegOperands(MCInst &Inst, unsigned N) const argument 1801 addRegShiftedRegOperands(MCInst &Inst, unsigned N) const argument 1811 addRegShiftedImmOperands(MCInst &Inst, unsigned N) const argument 1822 addShifterImmOperands(MCInst &Inst, unsigned N) const argument 1828 addRegListOperands(MCInst &Inst, unsigned N) const argument 1836 addDPRRegListOperands(MCInst &Inst, unsigned N) const argument 1840 addSPRRegListOperands(MCInst &Inst, unsigned N) const argument 1844 addRotImmOperands(MCInst &Inst, unsigned N) const argument 1850 addModImmOperands(MCInst &Inst, unsigned N) const argument 1860 addModImmNotOperands(MCInst &Inst, unsigned N) const argument 1867 addModImmNegOperands(MCInst &Inst, unsigned N) const argument 1874 addBitfieldOperands(MCInst &Inst, unsigned N) const argument 1885 addImmOperands(MCInst &Inst, unsigned N) const argument 1890 addFBits16Operands(MCInst &Inst, unsigned N) const argument 1896 addFBits32Operands(MCInst &Inst, unsigned N) const argument 1902 addFPImmOperands(MCInst &Inst, unsigned N) const argument 1909 addImm8s4Operands(MCInst &Inst, unsigned N) const argument 1917 addImm0_1020s4Operands(MCInst &Inst, unsigned N) const argument 1925 addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const argument 1933 addImm0_508s4Operands(MCInst &Inst, unsigned N) const argument 1941 addImm1_16Operands(MCInst &Inst, unsigned N) const argument 1949 addImm1_32Operands(MCInst &Inst, unsigned N) const argument 1957 addImmThumbSROperands(MCInst &Inst, unsigned N) const argument 1966 addPKHASRImmOperands(MCInst &Inst, unsigned N) const argument 1975 addT2SOImmNotOperands(MCInst &Inst, unsigned N) const argument 1983 addT2SOImmNegOperands(MCInst &Inst, unsigned N) const argument 1991 addImm0_4095NegOperands(MCInst &Inst, unsigned N) const argument 1999 addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const argument 2010 addThumbMemPCOperands(MCInst &Inst, unsigned N) const argument 2031 addMemBarrierOptOperands(MCInst &Inst, unsigned N) const argument 2036 addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const argument 2041 addMemNoOffsetOperands(MCInst &Inst, unsigned N) const argument 2046 addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const argument 2052 addAdrLabelOperands(MCInst &Inst, unsigned N) const argument 2068 addAlignedMemoryOperands(MCInst &Inst, unsigned N) const argument 2074 addDupAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const argument 2078 addAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const argument 2082 addAlignedMemory16Operands(MCInst &Inst, unsigned N) const argument 2086 addDupAlignedMemory16Operands(MCInst &Inst, unsigned N) const argument 2090 addAlignedMemory32Operands(MCInst &Inst, unsigned N) const argument 2094 addDupAlignedMemory32Operands(MCInst &Inst, unsigned N) const argument 2098 addAlignedMemory64Operands(MCInst &Inst, unsigned N) const argument 2102 addDupAlignedMemory64Operands(MCInst &Inst, unsigned N) const argument 2106 addAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const argument 2110 addDupAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const argument 2114 addAlignedMemory64or128or256Operands(MCInst &Inst, unsigned N) const argument 2118 addAddrMode2Operands(MCInst &Inst, unsigned N) const argument 2373 addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const argument 2380 addMemThumbSPIOperands(MCInst &Inst, unsigned N) const argument 2387 addPostIdxImm8Operands(MCInst &Inst, unsigned N) const argument 2398 addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const argument 2410 addPostIdxRegOperands(MCInst &Inst, unsigned N) const argument 2416 addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const argument 2427 addMSRMaskOperands(MCInst &Inst, unsigned N) const argument 2432 addBankedRegOperands(MCInst &Inst, unsigned N) const argument 2437 addProcIFlagsOperands(MCInst &Inst, unsigned N) const argument 2442 addVecListOperands(MCInst &Inst, unsigned N) const argument 2447 addVecListIndexedOperands(MCInst &Inst, unsigned N) const argument 2453 addVectorIndex8Operands(MCInst &Inst, unsigned N) const argument 2458 addVectorIndex16Operands(MCInst &Inst, unsigned N) const argument 2463 addVectorIndex32Operands(MCInst &Inst, unsigned N) const argument 2468 addNEONi8splatOperands(MCInst &Inst, unsigned N) const argument 2476 addNEONi16splatOperands(MCInst &Inst, unsigned N) const argument 2485 addNEONi16splatNotOperands(MCInst &Inst, unsigned N) const argument 2494 addNEONi32splatOperands(MCInst &Inst, unsigned N) const argument 2503 addNEONi32splatNotOperands(MCInst &Inst, unsigned N) const argument 2512 addNEONinvByteReplicateOperands(MCInst &Inst, unsigned N) const argument 2525 addNEONi32vmovOperands(MCInst &Inst, unsigned N) const argument 2539 addNEONvmovByteReplicateOperands(MCInst &Inst, unsigned N) const argument 2552 addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const argument 2566 addNEONi64splatOperands(MCInst &Inst, unsigned N) const argument 4757 cvtThumbMultiply(MCInst &Inst, const OperandVector &Operands) argument 4773 cvtThumbBranches(MCInst &Inst, const OperandVector &Operands) argument 5782 RequiresVFPRegListValidation(StringRef Inst, bool &AcceptSinglePrecisionOnly, bool &AcceptDoublePrecisionOnly) argument 6101 checkLowRegisterList(const MCInst &Inst, unsigned OpNo, unsigned Reg, unsigned HiReg, bool &containsReg) argument 6118 listContainsReg(const MCInst &Inst, unsigned OpNo, unsigned Reg) argument 6129 instIsBreakpoint(const MCInst &Inst) argument 6137 validatetLDMRegList(const MCInst &Inst, const OperandVector &Operands, unsigned ListNo, bool IsARPop) argument 6160 validatetSTMRegList(const MCInst &Inst, const OperandVector &Operands, unsigned ListNo) argument 6182 validateInstruction(MCInst &Inst, const OperandVector &Operands) argument 6822 processInstruction(MCInst &Inst, const OperandVector &Operands, MCStreamer &Out) argument 8748 checkTargetMatchPredicate(MCInst &Inst) argument 8812 MCInst Inst; local [all...] |