Searched refs:v2i16 (Results 1 - 24 of 24) sorted by relevance

/external/clang/test/CodeGen/
H A Dppc64-vector.c3 typedef short v2i16 __attribute__((vector_size (4))); typedef
13 v2i16 test_v2i16(v2i16 x)
H A Dbuiltins-mips.c12 typedef short v2i16 __attribute__ ((vector_size(4))); typedef
17 v2i16 v2i16_r, v2i16_a, v2i16_b, v2i16_c;
352 v2i16_a = (v2i16) {0xffff, 0x2468};
353 v2i16_b = (v2i16) {0x1234, 0x1111};
356 v2i16_a = (v2i16) {0xffff, 0x2468};
357 v2i16_b = (v2i16) {0x1234, 0x1111};
392 v2i16_b = (v2i16) {0xffff, 0x1555};
393 v2i16_c = (v2i16) {0x1234, 0x3322};
397 v2i16_b = (v2i16) {0xffff, 0x1555};
398 v2i16_c = (v2i16) {
[all...]
H A Dsystemz-abi-vector.c16 typedef __attribute__((vector_size(4))) short v2i16; typedef
70 v2i16 pass_v2i16(v2i16 arg) { return arg; }
H A Dx86_32-arguments-darwin.c217 typedef unsigned short v2i16 __attribute__((__vector_size__(4))); typedef
221 v2i16 f54(v2i16 arg) { return arg+arg; }
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
H A DValueTypes.h59 v2i16 = 17, // 2 x i16 enumerator in enum:llvm::MVT::SimpleValueType
195 case v2i16:
233 case v2i16:
259 case v2i16: return 32;
346 if (NumElements == 2) return MVT::v2i16;
/external/llvm/include/llvm/CodeGen/
H A DMachineValueType.h79 v2i16 = 31, // 2 x i16
234 return (SimpleTy == MVT::v4i8 || SimpleTy == MVT::v2i16 ||
335 case v2i16:
413 case v2i16:
463 case v2i16:
615 if (NumElements == 2) return MVT::v2i16;
/external/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp224 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 },
227 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 },
248 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i16, 4 },
251 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 4 },
265 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f32, 1 },
268 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f32, 1 },
279 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f64, 2 },
282 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f64, 2 },
H A DAArch64ISelLowering.cpp418 // load, floating-point truncating stores, or v2i32->v2i16 truncating store.
599 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Expand);
2099 case MVT::v2i16:
8051 // (v4i16 (concat_vectors (v2i16 (truncate (v2i64))),
8052 // (v2i16 (truncate (v2i64)))))
/external/swiftshader/third_party/LLVM/lib/VMCore/
H A DValueTypes.cpp125 case MVT::v2i16: return "v2i16";
172 case MVT::v2i16: return VectorType::get(Type::getInt16Ty(Context), 2);
/external/llvm/lib/IR/
H A DValueTypes.cpp163 case MVT::v2i16: return "v2i16";
241 case MVT::v2i16: return VectorType::get(Type::getInt16Ty(Context), 2);
/external/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp134 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 },
135 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 },
166 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i16, 3 },
167 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 3 },
H A DARMISelLowering.cpp634 for (MVT Ty : {MVT::v8i8, MVT::v4i8, MVT::v2i8, MVT::v4i16, MVT::v2i16,
6517 case MVT::v2i16:
/external/mesa3d/src/gallium/drivers/radeon/
H A DAMDILISelLowering.cpp59 (int)MVT::v2i16,
87 (int)MVT::v2i16,
209 setOperationAction(ISD::UDIV, MVT::v2i16, Expand);
666 if (OVT == MVT::v2i16) {
/external/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp239 } else if (LocVT == MVT::v4i8 || LocVT == MVT::v2i16) {
406 } else if (LocVT == MVT::v4i8 || LocVT == MVT::v2i16) {
1264 if (LHSVT == MVT::v2i16) {
1308 if (OpVT == MVT::v2i16) {
1312 SDValue TR = DAG.getNode(ISD::TRUNCATE, DL, MVT::v2i16, SL);
1742 addRegisterClass(MVT::v2i16, &Hexagon::IntRegsRegClass);
1923 promoteLdStType(MVT::v2i16, MVT::i32);
1976 MVT::v4i8, MVT::v8i8, MVT::v2i16, MVT::v4i16, MVT::v1i32,
1993 setOperationAction(ISD::SETCC, MVT::v2i16, Custom);
1994 setOperationAction(ISD::VSELECT, MVT::v2i16, Custo
[all...]
/external/llvm/utils/TableGen/
H A DCodeGenTarget.cpp91 case MVT::v2i16: return "MVT::v2i16";
/external/swiftshader/third_party/LLVM/utils/TableGen/
H A DCodeGenTarget.cpp74 case MVT::v2i16: return "MVT::v2i16";
/external/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp60 MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8};
84 setOperationAction(ISD::MUL, MVT::v2i16, Legal);
878 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
935 if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget.hasDSPR2()))
947 if (((Ty != MVT::v2i16) || !Subtarget.hasDSPR2()) && (Ty != MVT::v4i8))
954 bool IsV216 = (Ty == MVT::v2i16);
974 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
1026 } else if ((Ty == MVT::v2i16) || (Ty == MVT::v4i8)) {
/external/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp133 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Expand);
134 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Expand);
135 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i16, Expand);
184 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom);
200 setTruncStoreAction(MVT::v2i64, MVT::v2i16, Expand);
H A DR600ISelLowering.cpp155 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Expand);
H A DSIISelLowering.cpp122 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
/external/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp65 case MVT::v2i16:
1928 case MVT::v2i16:
4302 case MVT::v2i16:
/external/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp593 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 5 },
H A DX86ISelLowering.cpp798 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom);
908 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom);
917 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
924 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
1206 setTruncStoreAction(MVT::v2i64, MVT::v2i16, Legal);
1260 setLoadExtAction(ISD::EXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
[all...]
/external/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp653 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);

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