Searched defs:RA (Results 1 - 25 of 48) sorted by relevance

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/external/llvm/lib/Target/Hexagon/
H A DHexagonRDF.cpp19 bool HexagonRegisterAliasInfo::covers(RegisterRef RA, RegisterRef RB) const { argument
20 if (RA == RB)
23 if (TargetRegisterInfo::isVirtualRegister(RA.Reg) &&
26 if (RA.Reg == RB.Reg) {
27 if (RA.Sub == 0)
34 return RegisterAliasInfo::covers(RA, RB);
H A DRDFDeadCode.cpp77 for (NodeAddr<RefNode*> RA : IA.Addr->members(DFG)) {
78 if (!LiveNodes.count(RA.Id))
79 WorkQ.push_back(RA.Id);
124 auto RA = DFG.addr<RefNode*>(N); local
125 if (DFG.IsDef(RA))
126 processDef(RA, WorkQ);
128 processUse(RA, WorkQ);
134 auto RA = DFG.addr<RefNode*>(N); local
135 dbgs() << PrintNode<RefNode*>(RA, DFG) << "\n";
148 for (NodeAddr<RefNode*> RA
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H A DRDFLiveness.cpp533 for (NodeAddr<RefNode*> RA : IA.Addr->members(DFG))
534 NBMap.insert(std::make_pair(RA.Id, BB));
728 // shadow associated with RA. If it is not, then RR is "restricted" to RA,
729 // and so it can be considered a value specific to RA. This is important
732 bool Liveness::isRestricted(NodeAddr<InstrNode*> IA, NodeAddr<RefNode*> RA, argument
734 NodeId Start = RA.Id;
735 for (NodeAddr<RefNode*> TA = DFG.getNextShadow(IA, RA);
747 RegisterRef Liveness::getRestrictedRegRef(NodeAddr<RefNode*> RA) const {
748 assert(DFG.IsRef<NodeAttrs::Use>(RA));
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/external/llvm/lib/MC/
H A DMCSubtargetInfo.cpp43 const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA,
47 ReadAdvanceTable(RA), Stages(IS), OperandCycles(OC), ForwardingPaths(FP) {
39 MCSubtargetInfo( const Triple &TT, StringRef C, StringRef FS, ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetFeatureKV> PD, const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC, const unsigned *FP) argument
/external/llvm/lib/Target/
H A DTargetSubtargetInfo.cpp24 const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA,
26 : MCSubtargetInfo(TT, CPU, FS, PF, PD, ProcSched, WPR, WL, RA, IS, OC, FP) {
20 TargetSubtargetInfo( const Triple &TT, StringRef CPU, StringRef FS, ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetFeatureKV> PD, const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC, const unsigned *FP) argument
/external/clang/test/CodeGenCXX/
H A Ddevirtualize-virtual-function-calls-final.cpp179 struct RA { struct in namespace:Test9
187 struct RC final : public RA {
212 return static_cast<RA*>(x)->f();
225 return -static_cast<RA&>(*x);
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/MCTargetDesc/
H A DPPCMCTargetDesc.cpp46 unsigned RA = isPPC64 ? PPC::LR8 : PPC::LR; local
49 InitPPCMCRegisterInfo(X, RA, Flavour, Flavour);
/external/clang/test/Layout/
H A Dms-x86-alias-avoidance-padding.cpp301 struct RA {}; struct
306 struct RX0 : RB, RA {};
307 struct RX1 : RA, RB {};
308 struct RX2 : RA { char a; };
309 struct RX3 : RA { RB a; };
310 struct RX4 { RA a; char b; };
311 struct RX5 { RA a; RB b; };
313 struct RX7 : virtual RW { RA a; };
314 struct RX8 : RA, virtual RW {};
326 // CHECK-NEXT: 1 | struct RA (bas
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H A Dms-x86-pack-and-align.cpp414 struct RA {}; struct
425 struct __declspec(align(8)) RB2 : virtual RA {
429 struct __declspec(align(8)) RB3 : virtual RA {
460 // CHECK-NEXT: 1028 | struct RA (virtual base) (empty)
468 // CHECK-NEXT: 2052 | struct RA (virtual base) (empty)
501 // CHECK-X64-NEXT: 1028 | struct RA (virtual base) (empty)
509 // CHECK-X64-NEXT: 2052 | struct RA (virtual base) (empty)
/external/llvm/lib/Target/PowerPC/MCTargetDesc/
H A DPPCMCTargetDesc.cpp57 unsigned RA = isPPC64 ? PPC::LR8 : PPC::LR; local
60 InitPPCMCRegisterInfo(X, RA, Flavour, Flavour);
/external/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.cpp147 unsigned RA = (TT.getArch() == Triple::x86_64) local
152 InitX86MCRegisterInfo(X, RA, X86_MC::getDwarfRegFlavour(TT, false),
153 X86_MC::getDwarfRegFlavour(TT, true), RA);
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/Disassembler/
H A DMBlazeDisassembler.cpp526 unsigned RA = getRA(insn); local
536 if (RD == UNSUPPORTED || RA == UNSUPPORTED || RB == UNSUPPORTED)
540 instr.addOperand(MCOperand::CreateReg(RA));
544 if (RD == UNSUPPORTED || RA == UNSUPPORTED || RB == UNSUPPORTED)
547 instr.addOperand(MCOperand::CreateReg(RA));
562 if (RA == UNSUPPORTED)
565 instr.addOperand(MCOperand::CreateReg(RA));
578 if (RD == UNSUPPORTED || RA == UNSUPPORTED)
581 instr.addOperand(MCOperand::CreateReg(RA));
595 if (RA
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/external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.cpp288 unsigned RA = (TheTriple.getArch() == Triple::x86_64) local
293 InitX86MCRegisterInfo(X, RA,
/external/llvm/lib/Transforms/IPO/
H A DDeadArgumentElimination.cpp598 /// MarkValue - This function marks the liveness of RA depending on L. If L is
600 /// such that RA will be marked live if any use in MaybeLiveUses gets marked
602 void DeadArgumentEliminationPass::MarkValue(const RetOrArg &RA, Liveness L, argument
605 case Live: MarkLive(RA); break;
611 Uses.insert(std::make_pair(MaybeLiveUse, RA));
637 void DeadArgumentEliminationPass::MarkLive(const RetOrArg &RA) { argument
638 if (LiveFunctions.count(RA.F))
641 if (!LiveValues.insert(RA).second)
645 << RA.getDescription() << " live\n");
646 PropagateLiveness(RA);
651 PropagateLiveness(const RetOrArg &RA) argument
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/external/swiftshader/third_party/LLVM/include/llvm/MC/
H A DMCRegisterInfo.h154 void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA, argument
158 RAReg = RA;
/external/swiftshader/third_party/LLVM/lib/Transforms/InstCombine/
H A DInstCombineSimplifyDemanded.cpp688 APInt RA = Rem->getValue().abs(); local
689 if (RA.isPowerOf2()) {
690 if (DemandedMask.ult(RA)) // srem won't affect demanded bits
693 APInt LowBits = RA - 1;
/external/swiftshader/third_party/subzero/src/
H A DIceInstMIPS32.cpp325 InstMIPS32Ret::InstMIPS32Ret(Cfg *Func, Variable *RA, Variable *Source) argument
327 addSource(RA);
428 auto *RA = llvm::cast<Variable>(getSrc(0)); local
429 assert(RA->hasReg());
430 assert(RA->getRegNum() == RegMIPS32::Reg_RA);
435 RA->emit(Func);
611 auto *RA = llvm::cast<Variable>(getSrc(0)); local
612 assert(RA->hasReg());
613 assert(RA->getRegNum() == RegMIPS32::Reg_RA);
614 (void)RA;
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/external/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp528 BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn)).addReg(Mips::RA);
712 unsigned RA = Subtarget.isGP64bit() ? Mips::RA_64 : Mips::RA; local
726 BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), RA)
/external/llvm/lib/Transforms/InstCombine/
H A DInstCombineSimplifyDemanded.cpp679 APInt RA = Rem->getValue().abs(); local
680 if (RA.isPowerOf2()) {
681 if (DemandedMask.ult(RA)) // srem won't affect demanded bits
684 APInt LowBits = RA - 1;
/external/skia/third_party/lua/src/
H A Dlvm.c489 #define RA(i) (base+GETARG_A(i)) macro
553 ra = RA(i);
659 ra = RA(i); /* 'luav_concat' may invoke TMs and move the stack */
800 ra = RA(i);
849 ra = RA(i); /* previous call may change the stack */
/external/swiftshader/third_party/LLVM/lib/Transforms/IPO/
H A DDeadArgumentElimination.cpp145 void MarkValue(const RetOrArg &RA, Liveness L,
147 void MarkLive(const RetOrArg &RA);
149 void PropagateLiveness(const RetOrArg &RA);
571 /// MarkValue - This function marks the liveness of RA depending on L. If L is
573 /// such that RA will be marked live if any use in MaybeLiveUses gets marked
575 void DAE::MarkValue(const RetOrArg &RA, Liveness L, argument
578 case Live: MarkLive(RA); break;
585 Uses.insert(std::make_pair(*UI, RA));
610 void DAE::MarkLive(const RetOrArg &RA) { argument
611 if (LiveFunctions.count(RA
623 PropagateLiveness(const RetOrArg &RA) argument
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/external/syslinux/com32/lua/src/
H A Dlvm.c512 #define RA(i) (base+GETARG_A(i)) macro
576 ra = RA(i);
682 ra = RA(i); /* 'luav_concat' may invoke TMs and move the stack */
823 ra = RA(i);
872 ra = RA(i); /* previous call may change the stack */
/external/libpcap/
H A Dgrammar.h98 RA = 308, enumerator in enum:yytokentype
220 #define RA 308 macro
/external/llvm/include/llvm/MC/
H A DMCRegisterInfo.h245 void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA, argument
260 RAReg = RA;
/external/swiftshader/third_party/LLVM/lib/Analysis/
H A DValueTracking.cpp469 APInt RA = Rem->getValue().abs(); local
470 if (RA.isPowerOf2()) {
471 APInt LowBits = RA - 1;
512 APInt RA = Rem->getValue(); local
513 if (RA.isPowerOf2()) {
514 APInt LowBits = (RA - 1);

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