Searched defs:SubReg (Results 1 - 25 of 28) sorted by relevance

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/external/swiftshader/third_party/LLVM/lib/Target/Mips/
H A DMipsExpandPseudo.cpp92 const unsigned* SubReg = local
97 BuildMI(MBB, I, dl, Mtc1Tdd, *SubReg).addReg(LoReg);
98 BuildMI(MBB, I, dl, Mtc1Tdd, *(SubReg + 1)).addReg(HiReg);
108 const unsigned* SubReg = TM.getRegisterInfo()->getSubRegisters(SrcReg); local
110 BuildMI(MBB, I, dl, Mfc1Tdd, DstReg).addReg(*(SubReg + N));
/external/llvm/lib/Target/AMDGPU/
H A DSIFixSGPRCopies.cpp200 unsigned SubReg = CopyUse.getOperand(1).getSubReg(); local
201 if (SubReg != AMDGPU::NoSubRegister)
H A DR600OptimizeVectorRegisters.cpp193 unsigned SubReg = (*It).first; local
200 .addReg(SubReg)
202 UpdatedRegToChan[SubReg] = Chan;
H A DSILowerControlFlow.cpp600 unsigned SubReg = TRI->getSubReg(VecReg, AMDGPU::sub0); local
601 if (!SubReg)
602 SubReg = VecReg;
605 const TargetRegisterClass *RC = TRI->getPhysRegClass(SubReg);
608 int BaseRegIdx = TRI->getHWRegIndex(SubReg);
H A DSIRegisterInfo.cpp464 unsigned SubReg = NumSubRegs > 1 ? local
477 .addReg(SubReg, getDefRegState(!IsStore))
522 // SubReg carries the "Kill" flag when SubReg == SuperReg.
525 unsigned SubReg = getPhysRegSubReg(SuperReg, local
535 .addReg(SubReg, getKillRegState(IsKill))
546 .addReg(SubReg, SubKillState);
590 unsigned SubReg = getPhysRegSubReg(MI->getOperand(0).getReg(), local
598 SubReg)
622 TII->get(AMDGPU::V_READFIRSTLANE_B32), SubReg)
[all...]
H A DAMDGPUISelDAGToDAG.cpp1419 unsigned SubReg = Is32 ? AMDGPU::sub0 : AMDGPU::sub0_sub1; local
1421 = CurDAG->getTargetExtractSubreg(SubReg, SL, VT, SDValue(CmpSwap, 0));
H A DSIInstrInfo.cpp1008 unsigned SubReg = Src0.getSubReg(); local
1015 Src1.setSubReg(SubReg);
1910 unsigned SubReg = MRI.createVirtualRegister(SubRC);
1913 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), SubReg)
1915 return SubReg;
1927 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), SubReg)
1930 return SubReg;
1950 unsigned SubReg = buildExtractSubReg(MII, MRI, Op, SuperRC,
1952 return MachineOperand::CreateReg(SubReg, false);
2023 if ((Op.getReg() != SGPRUsed.Reg || Op.getSubReg() != SGPRUsed.SubReg)
[all...]
/external/llvm/lib/CodeGen/
H A DLiveRangeCalc.cpp65 unsigned SubReg = MO.getSubReg(); local
66 if (LI.hasSubRanges() || (SubReg != 0 && TrackSubRegs)) {
67 LaneBitmask Mask = SubReg != 0 ? TRI.getSubRegIndexLaneMask(SubReg)
175 unsigned SubReg = MO.getSubReg(); local
176 if (SubReg != 0) {
177 LaneBitmask SubRegMask = TRI.getSubRegIndexLaneMask(SubReg);
H A DLiveRangeEdit.cpp227 unsigned SubReg = MO.getSubReg(); local
228 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubReg);
H A DMachineInstrBundle.cpp188 unsigned SubReg = *SubRegs; local
189 if (LocalDefSet.insert(SubReg).second)
190 LocalDefs.push_back(SubReg);
H A DVirtRegMap.cpp319 // Sort and unique MBB LiveIns as we've not checked if SubReg/PhysReg were in
405 unsigned SubReg = MO.getSubReg(); local
406 if (SubReg != 0) {
441 PhysReg = TRI->getSubReg(PhysReg, SubReg);
442 assert(PhysReg && "Invalid SubReg for physical register");
H A DDetectDeadLanes.cpp180 unsigned SubReg = MI.getOperand(2).getImm(); local
181 SrcSubIdx = TRI.composeSubRegIndices(SubReg, SrcSubIdx);
430 unsigned SubReg = MO.getSubReg(); local
453 if (SubReg == 0)
456 UsedLanes |= TRI->getSubRegIndexLaneMask(SubReg);
463 unsigned SubReg = MO.getSubReg(); local
464 LaneBitmask Mask = TRI->getSubRegIndexLaneMask(SubReg);
H A DLiveVariables.cpp198 unsigned SubReg = *SubRegs; local
199 MachineInstr *Def = PhysRegDef[SubReg];
204 LastDefReg = SubReg;
252 unsigned SubReg = *SubRegs; local
253 if (Processed.count(SubReg))
255 if (PartDefRegs.count(SubReg))
259 LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg,
262 PhysRegDef[SubReg] = LastPartialDef;
263 for (MCSubRegIterator SS(SubReg, TRI); SS.isValid(); ++SS)
291 unsigned SubReg local
340 unsigned SubReg = *SubRegs; local
371 unsigned SubReg = *SubRegs; local
453 unsigned SubReg = *SubRegs; local
475 unsigned SubReg = *SubRegs; local
493 unsigned SubReg = *SubRegs; local
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H A DPeepholeOptimizer.cpp160 bool findNextSource(unsigned Reg, unsigned SubReg,
225 ValueTrackerResult(unsigned Reg, unsigned SubReg) : Inst(nullptr) { argument
226 addSource(Reg, SubReg);
256 assert(Idx < getNumSources() && "SubReg source out of index");
257 return RegSrcs[Idx].SubReg;
606 /// for the value defined by \p Reg and \p SubReg.
613 /// share the same register file as \p Reg and \p SubReg. The client should
616 bool PeepholeOptimizer::findNextSource(unsigned Reg, unsigned SubReg, argument
627 TargetInstrInfo::RegSubRegPair CurSrcPair(Reg, SubReg);
638 ValueTracker ValTracker(CurSrcPair.Reg, CurSrcPair.SubReg, *MR
1261 unsigned Reg, SubReg, CopyDefReg, CopyDefSubReg; local
[all...]
H A DLiveIntervalAnalysis.cpp522 unsigned SubReg = MO.getSubReg(); local
523 if (SubReg != 0) {
524 LaneBitmask LaneMask = TRI->getSubRegIndexLaneMask(SubReg);
956 unsigned SubReg = MO.getSubReg(); local
957 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubReg);
1319 unsigned SubReg = MO.getSubReg(); local
1320 if (SubReg != 0 && LaneMask != 0
1321 && (TRI.getSubRegIndexLaneMask(SubReg) & LaneMask) == 0)
1421 unsigned SubReg = MO.getSubReg(); local
1422 LaneBitmask Mask = TRI->getSubRegIndexLaneMask(SubReg);
[all...]
H A DScheduleDAGInstrs.cpp409 unsigned SubReg = MO.getSubReg(); local
410 if (SubReg == 0)
412 return TRI->getSubRegIndexLaneMask(SubReg);
H A DRegisterCoalescer.cpp1250 unsigned SubReg = MO.getSubReg(); local
1251 if (SubReg == 0 || MO.isUndef())
1257 addUndefFlag(*DstInt, UseIdx, MO, SubReg);
/external/llvm/lib/Target/AArch64/
H A DAArch64AdvSIMDScalarPass.cpp112 static bool isGPR64(unsigned Reg, unsigned SubReg, argument
114 if (SubReg)
121 static bool isFPR64(unsigned Reg, unsigned SubReg, argument
125 SubReg == 0) ||
127 SubReg == AArch64::dsub);
129 return (AArch64::FPR64RegClass.contains(Reg) && SubReg == 0) ||
130 (AArch64::FPR128RegClass.contains(Reg) && SubReg == AArch64::dsub);
137 unsigned &SubReg) {
138 SubReg = 0;
146 SubReg
135 getSrcFromCopy(MachineInstr *MI, const MachineRegisterInfo *MRI, unsigned &SubReg) argument
253 unsigned SubReg; local
[all...]
/external/llvm/lib/Target/ARM/
H A DARMBaseRegisterInfo.cpp785 unsigned SubReg,
783 shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC) const argument
H A DARMAsmPrinter.cpp380 unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ? local
382 O << ARMInstPrinter::getRegisterName(SubReg);
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
H A DMachineOperand.h60 /// SubReg - Subregister number, only valid for MO_Register. A value of 0
62 unsigned char SubReg; member in class:llvm::MachineOperand
228 return (unsigned)SubReg;
297 SubReg = (unsigned char)subReg;
301 /// subregister Reg:SubReg. Take any existing SubReg index into account,
308 /// Reg, taking any existing SubReg into account. For instance,
493 unsigned SubReg = 0,
506 Op.SubReg = SubReg;
[all...]
/external/swiftshader/third_party/LLVM/utils/TableGen/
H A DCodeGenRegisters.cpp41 CodeGenRegister *SubReg; member in struct:__anon20414::Orphan
44 : SubReg(r), First(a), Second(b) {}
128 if (Orphans[j].SubReg == R2)
129 Orphans[j].SubReg = 0;
136 if (!O.SubReg)
139 O.SubReg;
/external/llvm/include/llvm/Target/
H A DTargetInstrInfo.h356 /// Used to give some type checking when modeling Reg:SubReg.
359 unsigned SubReg; member in struct:llvm::TargetInstrInfo::RegSubRegPair
360 RegSubRegPair(unsigned Reg = 0, unsigned SubReg = 0)
361 : Reg(Reg), SubReg(SubReg) {}
368 RegSubRegPairAndIdx(unsigned Reg = 0, unsigned SubReg = 0,
370 : RegSubRegPair(Reg, SubReg), SubIdx(SubIdx) {}
376 /// the list is modeled as <Reg:SubReg, SubIdx>.
1504 std::make_pair(Val.Reg, Val.SubReg);
1510 RegInfo::isEqual(LHS.SubReg, RH
[all...]
/external/llvm/lib/CodeGen/MIRParser/
H A DMIParser.cpp124 bool parseSubRegisterIndex(unsigned &SubReg);
873 bool MIParser::parseSubRegisterIndex(unsigned &SubReg) { argument
879 SubReg = getSubRegIndex(Name);
880 if (!SubReg)
961 unsigned SubReg = 0; local
963 if (parseSubRegisterIndex(SubReg))
992 Flags & RegState::EarlyClobber, SubReg, Flags & RegState::Debug,
/external/llvm/utils/TableGen/
H A DCodeGenRegisters.cpp306 // Compute the inverse SubReg -> Idx map.
418 const CodeGenRegister *SubReg = I->second; local
419 const CodeGenRegister::SuperRegList &Leads = SubReg->LeadingSuperRegs;
495 // Topological signature computed from SubIdx, TopoId(SubReg).
1790 CodeGenRegister *SubReg = S->second; local
1793 if (SubReg->getSubRegs().size() != 0)

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