Searched refs:MVT (Results 26 - 50 of 261) sorted by relevance

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/external/llvm/include/llvm/CodeGen/
H A DValueTypes.h30 /// a MVT can represent.
33 MVT V;
37 LLVM_CONSTEXPR EVT() : V(MVT::INVALID_SIMPLE_VALUE_TYPE), LLVMTy(nullptr) {}
38 LLVM_CONSTEXPR EVT(MVT::SimpleValueType SVT) : V(SVT), LLVMTy(nullptr) {}
39 LLVM_CONSTEXPR EVT(MVT S) : V(S), LLVMTy(nullptr) {}
56 return MVT::getFloatingPointVT(BitWidth);
62 MVT M = MVT::getIntegerVT(BitWidth);
71 MVT M = MVT
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/external/llvm/lib/Target/NVPTX/
H A DNVPTXISelDAGToDAG.cpp608 MVT::i64, GlobalVal));
704 MVT SimpleVT = LoadedVT.getSimpleVT();
722 MVT ScalarVT = SimpleVT.getScalarType();
739 MVT::SimpleValueType TargetVT = LD->getSimpleValueType(0).SimpleTy;
743 case MVT::i8:
746 case MVT::i16:
749 case MVT::i32:
752 case MVT::i64:
755 case MVT::f32:
758 case MVT
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/external/swiftshader/third_party/LLVM/lib/Target/Alpha/
H A DAlphaISelLowering.cpp54 addRegisterClass(MVT::i64, Alpha::GPRCRegisterClass);
55 addRegisterClass(MVT::f64, Alpha::F8RCRegisterClass);
56 addRegisterClass(MVT::f32, Alpha::F4RCRegisterClass);
59 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
61 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
62 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
64 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
65 setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Expand);
67 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
68 setLoadExtAction(ISD::SEXTLOAD, MVT
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/external/swiftshader/third_party/LLVM/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp49 addRegisterClass(MVT::i32, SystemZ::GR32RegisterClass);
50 addRegisterClass(MVT::i64, SystemZ::GR64RegisterClass);
51 addRegisterClass(MVT::v2i32,SystemZ::GR64PRegisterClass);
52 addRegisterClass(MVT::v2i64,SystemZ::GR128RegisterClass);
55 addRegisterClass(MVT::f32, SystemZ::FP32RegisterClass);
56 addRegisterClass(MVT::f64, SystemZ::FP64RegisterClass);
63 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
64 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
65 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
67 setLoadExtAction(ISD::SEXTLOAD, MVT
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/external/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp139 bool isTypeLegal(Type *Ty, MVT &VT);
140 bool isTypeSupported(Type *Ty, MVT &VT, bool IsVectorAllowed = false);
144 bool simplifyAddress(Address &Addr, MVT VT);
153 bool optimizeIntExtLoad(const Instruction *I, MVT RetVT, MVT SrcVT);
158 unsigned emitAddSub(bool UseAdd, MVT RetVT, const Value *LHS,
161 unsigned emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg,
164 unsigned emitAddSub_ri(bool UseAdd, MVT RetVT, unsigned LHSReg,
167 unsigned emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg,
172 unsigned emitAddSub_rx(bool UseAdd, MVT RetV
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/external/swiftshader/third_party/LLVM/lib/Target/X86/
H A DX86GenDAGISel.inc24 /*13*/ OPC_CheckChild1Type, MVT::v4f32,
60 /*94*/ OPC_CheckChild1Type, MVT::v2f64,
95 /*172*/ OPC_CheckChild1Type, MVT::v2i64,
116 /*218*/ OPC_CheckChild1Type, MVT::v8f32,
134 /*258*/ OPC_CheckChild1Type, MVT::v4f64,
152 /*298*/ OPC_CheckChild1Type, MVT::i32,
163 /*322*/ OPC_CheckChild1Type, MVT::i64,
190 /*376*/ OPC_CheckType, MVT::i8,
192 /*379*/ OPC_CheckType, MVT::i8,
203 1/*#VTs*/, MVT
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H A DX86GenFastISel.inc26 unsigned FastEmit_ISD_ANY_EXTEND_MVT_i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
28 case MVT::i32: return FastEmit_ISD_ANY_EXTEND_MVT_i8_MVT_i32_r(Op0, Op0IsKill);
29 case MVT::i64: return FastEmit_ISD_ANY_EXTEND_MVT_i8_MVT_i64_r(Op0, Op0IsKill);
34 unsigned FastEmit_ISD_ANY_EXTEND_MVT_i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
35 if (RetVT.SimpleTy != MVT::i64)
40 unsigned FastEmit_ISD_ANY_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
42 case MVT::i8: return FastEmit_ISD_ANY_EXTEND_MVT_i8_r(RetVT, Op0, Op0IsKill);
43 case MVT::i16: return FastEmit_ISD_ANY_EXTEND_MVT_i16_r(RetVT, Op0, Op0IsKill);
50 unsigned FastEmit_ISD_BITCAST_MVT_i32_r(MVT RetV
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/external/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp502 if (OpVT == MVT::f16) {
503 if (RetVT == MVT::f32)
505 } else if (OpVT == MVT::f32) {
506 if (RetVT == MVT::f64)
508 if (RetVT == MVT::f128)
510 if (RetVT == MVT::ppcf128)
512 } else if (OpVT == MVT::f64) {
513 if (RetVT == MVT::f128)
515 else if (RetVT == MVT::ppcf128)
525 if (RetVT == MVT
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/external/swiftshader/third_party/LLVM/lib/Target/XCore/
H A DXCoreISelDAGToDAG.cpp55 return CurDAG->getTargetConstant(Imm, MVT::i32);
94 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
95 Offset = CurDAG->getTargetConstant(0, MVT::i32);
104 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
105 Offset = CurDAG->getTargetConstant(CN->getSExtValue(), MVT::i32);
116 Offset = CurDAG->getTargetConstant(0, MVT::i32);
126 Offset = CurDAG->getTargetConstant(CN->getSExtValue(), MVT::i32);
137 Offset = CurDAG->getTargetConstant(0, MVT::i32);
147 Offset = CurDAG->getTargetConstant(CN->getSExtValue(), MVT::i32);
165 MVT
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/external/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp78 MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize());
135 addRegisterClass(MVT::i8, &X86::GR8RegClass);
136 addRegisterClass(MVT::i16, &X86::GR16RegClass);
137 addRegisterClass(MVT::i32, &X86::GR32RegClass);
139 addRegisterClass(MVT::i64, &X86::GR64RegClass);
141 for (MVT VT : MVT::integer_valuetypes())
142 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
145 setTruncStoreAction(MVT
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/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp64 return CurDAG->getTargetConstant(Imm, MVT::i32);
70 return CurDAG->getTargetConstant(Imm, MVT::i64);
241 if (PPCLowering.getPointerTy() == MVT::i32) {
264 if (N->getValueType(0) == MVT::i32)
278 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
288 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) {
336 if (N->getValueType(0) != MVT::i32)
438 return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops, 5);
451 if (LHS.getValueType() == MVT::i32) {
457 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT
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/external/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp77 addRegisterClass(MVT::i32, &XCore::GRRegsRegClass);
91 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
92 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
93 setOperationAction(ISD::ADDC, MVT::i32, Expand);
94 setOperationAction(ISD::ADDE, MVT::i32, Expand);
95 setOperationAction(ISD::SUBC, MVT::i32, Expand);
96 setOperationAction(ISD::SUBE, MVT::i32, Expand);
99 setOperationAction(ISD::ADD, MVT::i64, Custom);
100 setOperationAction(ISD::SUB, MVT::i64, Custom);
101 setOperationAction(ISD::SMUL_LOHI, MVT
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H A DXCoreISelDAGToDAG.cpp50 return CurDAG->getTargetConstant(Imm, dl, MVT::i32);
91 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
92 Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32);
101 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
103 MVT::i32);
120 Reg = CurDAG->getRegister(XCore::CP, MVT::i32);
123 Reg = CurDAG->getRegister(XCore::DP, MVT::i32);
143 MVT::i32, MskSize));
150 SDNode *node = CurDAG->getMachineNode(XCore::LDWCP_lru6, dl, MVT::i32,
151 MVT
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/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
H A DFastISel.h157 virtual unsigned FastEmit_(MVT VT,
158 MVT RetVT,
165 virtual unsigned FastEmit_r(MVT VT,
166 MVT RetVT,
174 virtual unsigned FastEmit_rr(MVT VT,
175 MVT RetVT,
184 virtual unsigned FastEmit_ri(MVT VT,
185 MVT RetVT,
194 virtual unsigned FastEmit_rf(MVT VT,
195 MVT RetV
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H A DCallingConvLower.h61 MVT ValVT;
64 MVT LocVT;
67 static CCValAssign getReg(unsigned ValNo, MVT ValVT,
68 unsigned RegNo, MVT LocVT,
81 static CCValAssign getCustomReg(unsigned ValNo, MVT ValVT,
82 unsigned RegNo, MVT LocVT,
90 static CCValAssign getMem(unsigned ValNo, MVT ValVT,
91 unsigned Offset, MVT LocVT,
104 static CCValAssign getCustomMem(unsigned ValNo, MVT ValVT,
105 unsigned Offset, MVT LocV
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/external/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp39 static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT,
40 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
52 static bool CC_Sparc_Assign_Split_64(unsigned &ValNo, MVT &ValVT,
53 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
80 static bool CC_Sparc_Assign_Ret_Split_64(unsigned &ValNo, MVT &ValVT,
81 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
104 static bool CC_Sparc64_Full(unsigned &ValNo, MVT &ValVT,
105 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
107 assert((LocVT == MVT::f32 || LocVT == MVT
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/external/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp114 unsigned fastEmit_i(MVT Ty, MVT RetTy, unsigned Opc, uint64_t Imm) override;
146 bool isTypeLegal(Type *Ty, MVT &VT);
147 bool isLoadTypeLegal(Type *Ty, MVT &VT);
157 bool PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
160 bool PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr);
164 bool PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
166 unsigned PPCMaterializeFP(const ConstantFP *CFP, MVT VT);
167 unsigned PPCMaterializeGV(const GlobalValue *GV, MVT V
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H A DPPCISelLowering.cpp82 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
84 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
85 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
89 for (MVT VT : MVT::integer_valuetypes()) {
90 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
91 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
94 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
97 setIndexedLoadAction(ISD::PRE_INC, MVT
7039 BuildIntrinsicOp(unsigned IID, SDValue Op, SelectionDAG &DAG, const SDLoc &dl, EVT DestVT = MVT::Other) argument
7048 BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS, SelectionDAG &DAG, const SDLoc &dl, EVT DestVT = MVT::Other) argument
7058 BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1, SDValue Op2, SelectionDAG &DAG, const SDLoc &dl, EVT DestVT = MVT::Other) argument
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/
H A DARMSelectionDAGInfo.cpp52 EVT VT = MVT::i32;
67 DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
68 DAG.getConstant(SrcOff, MVT::i32)),
74 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
79 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
80 DAG.getConstant(DstOff, MVT::i32)),
85 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
98 VT = MVT::i16;
101 VT = MVT::i8;
106 DAG.getNode(ISD::ADD, dl, MVT
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/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/
H A DMBlazeISelLowering.cpp38 static bool CC_MBlaze_AssignReg(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
65 addRegisterClass(MVT::i32, MBlaze::GPRRegisterClass);
67 addRegisterClass(MVT::f32, MBlaze::GPRRegisterClass);
68 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
72 setOperationAction(ISD::FREM, MVT::f32, Expand);
73 setOperationAction(ISD::FMA, MVT::f32, Expand);
74 setOperationAction(ISD::UINT_TO_FP, MVT::i8, Expand);
75 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Expand);
76 setOperationAction(ISD::UINT_TO_FP, MVT
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/external/swiftshader/third_party/LLVM/lib/Target/Blackfin/
H A DBlackfinISelLowering.cpp50 addRegisterClass(MVT::i32, BF::DRegisterClass);
51 addRegisterClass(MVT::i16, BF::D16RegisterClass);
56 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
57 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
58 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
60 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
61 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
63 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
64 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
65 setOperationAction(ISD::BR_CC, MVT
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/external/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAG.cpp118 return CurDAG->getTargetConstant(bitPos, DL, MVT::i32);
144 return CurDAG->getTargetConstant(-Imm, DL, MVT::i32);
151 return CurDAG->getTargetConstant(Imm - 1, DL, MVT::i8);
156 return CurDAG->getTargetConstant(Imm - 1, DL, MVT::i32);
162 return CurDAG->getTargetConstant(Imm - 1, DL, MVT::i32);
167 return CurDAG->getTargetConstant(Imm - 2, DL, MVT::i32);
172 return CurDAG->getTargetConstant(Imm - 3, DL, MVT::i32);
256 case MVT::i8:
262 case MVT::i16:
268 case MVT
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/external/llvm/lib/Target/ARM/
H A DARMCallingConv.h28 static bool f64AssignAPCS(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
58 static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
64 if (LocVT == MVT::v2f64 &&
71 static bool f64AssignAAPCS(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
112 static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
118 if (LocVT == MVT
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/external/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFastISel.cpp100 MVT::SimpleValueType getSimpleType(Type *Ty) {
103 MVT::INVALID_SIMPLE_VALUE_TYPE;
105 MVT::SimpleValueType getLegalType(MVT::SimpleValueType VT) {
107 case MVT::i1:
108 case MVT::i8:
109 case MVT::i16:
110 return MVT::i32;
111 case MVT::i32:
112 case MVT
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/external/swiftshader/third_party/LLVM/lib/Target/PTX/
H A DPTXISelDAGToDAG.cpp95 SDValue PredOp = CurDAG->getTargetConstant(PTXPredicate::Normal, MVT::i32);
99 assert(Pred.getValueType() == MVT::i1);
103 return CurDAG->getMachineNode(PTX::BRAdp, dl, MVT::Other, Ops, 4);
114 assert(VT.isSimple() && "READ_PARAM only implemented for MVT types");
116 MVT Type = VT.getSimpleVT();
118 if (Type == MVT::i1)
120 else if (Type == MVT::i16)
122 else if (Type == MVT::i32)
124 else if (Type == MVT::i64)
126 else if (Type == MVT
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1234567891011