/external/llvm/lib/Target/AArch64/InstPrinter/ |
H A D | AArch64InstPrinter.cpp | 69 const MCOperand &Op2 = MI->getOperand(2); local 74 if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) { 110 if (Op2.isImm() && Op3.isImm()) { 113 int64_t immr = Op2.getImm(); 144 if (Op2.getImm() > Op3.getImm()) { 147 << ", #" << (Is64Bit ? 64 : 32) - Op2.getImm() << ", #" << Op3.getImm() + 1; 155 << ", #" << Op2.getImm() << ", #" << Op3.getImm() - Op2.getImm() + 1; 162 const MCOperand &Op2 local 738 const MCOperand &Op2 = MI->getOperand(3); local [all...] |
/external/llvm/lib/Transforms/Scalar/ |
H A D | NaryReassociate.cpp | 159 // Tries to match Op1 and Op2 by using V. 160 bool matchTernaryOp(BinaryOperator *I, Value *V, Value *&Op1, Value *&Op2); 498 Value *&Op2) { 501 return match(V, m_Add(m_Value(Op1), m_Value(Op2))); 503 return match(V, m_Mul(m_Value(Op1), m_Value(Op2))); 497 matchTernaryOp(BinaryOperator *I, Value *V, Value *&Op1, Value *&Op2) argument
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H A D | LoopRerollPass.cpp | 1342 Value *Op2 = RootInst->getOperand(j); local 1348 if (Instruction *Op2I = dyn_cast<Instruction>(Op2)) 1352 DenseMap<Value *, Value *>::iterator BMI = BaseMap.find(Op2); 1354 Op2 = BMI->second; 1357 if (DRS.Roots[Iter-1] == (Instruction*) Op2) { 1358 Op2 = DRS.BaseInst; 1364 if (BaseInst->getOperand(Swapped ? unsigned(!j) : j) != Op2) { 1371 BaseInst->getOperand(!j) == Op2) {
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H A D | Scalarizer.cpp | 405 Scatterer Op2 = scatter(&SI, SI.getOperand(2)); local 407 assert(Op2.size() == NumElems && "Mismatched select"); 415 Res[I] = Builder.CreateSelect(Op0[I], Op1[I], Op2[I], 420 Res[I] = Builder.CreateSelect(Op0, Op1[I], Op2[I],
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/external/swiftshader/third_party/LLVM/lib/Target/PTX/ |
H A D | PTXInstrInfo.h | 121 SDValue Op1, SDValue Op2);
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H A D | PTXISelLowering.cpp | 151 SDValue Op2 = Op.getOperand(2); local 166 return DAG.getNode(ISD::SETCC, dl, MVT::i1, Op0, Op1, Op2);
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H A D | PTXInstrInfo.cpp | 329 DebugLoc dl, EVT VT, SDValue Op1, SDValue Op2) { 332 SDValue ops[] = { Op1, Op2, predReg, predOp }; 328 GetPTXMachineNode(SelectionDAG *DAG, unsigned Opcode, DebugLoc dl, EVT VT, SDValue Op1, SDValue Op2) argument
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/external/llvm/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 918 CondCode getSetCCOrOperation(CondCode Op1, CondCode Op2, bool isInteger); 923 CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, bool isInteger);
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonPeephole.cpp | 286 MachineOperand Op2 = MI.getOperand(S2); local 287 ChangeOpInto(MI.getOperand(S1), Op2);
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/external/spirv-llvm/lib/SPIRV/libSPIRV/ |
H A D | SPIRVInstruction.h | 614 SPIRVId Op2 = Ops[1]; local 617 if (getValue(Op1)->isForward() || getValue(Op2)->isForward()) 621 op2Ty = getValueType(Op2)->getVectorComponentType(); 623 getValueType(Op2)->getVectorComponentCount() && 628 op2Ty = getValueType(Op2); 632 assert(getValueType(Op1)== getValueType(Op2) && 894 auto Op2 = Ops[1]; local 897 if (getValue(Op1)->isForward() || getValue(Op2)->isForward()) 902 op2Ty = getValueType(Op2)->getVectorComponentType(); 905 getValueType(Op2) 987 SPIRVId Op2; member in class:SPIRV::SPIRVSelect [all...] |
H A D | SPIRVUtil.h | 404 getVec(T Op1, T Op2) { argument 407 V.push_back(Op2); 413 getVec(T Op1, T Op2, T Op3) { argument 416 V.push_back(Op2);
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H A D | SPIRVModule.cpp | 1000 SPIRVValue *Op1, SPIRVValue *Op2, SPIRVBasicBlock *BB){ 1002 getVec(Op1->getId(), Op2->getId()), BB, this), BB); 1058 SPIRVValue *Op1, SPIRVValue *Op2, SPIRVBasicBlock *BB) { 1060 TheType, getId(), getVec(Op1->getId(), Op2->getId()), BB, this), BB); 1080 SPIRVValue *Op2, SPIRVBasicBlock *BB) { 1082 Op1->getId(), Op2->getId(), BB), BB); 999 addBinaryInst(Op TheOpCode, SPIRVType *Type, SPIRVValue *Op1, SPIRVValue *Op2, SPIRVBasicBlock *BB) argument 1057 addCmpInst(Op TheOpCode, SPIRVType *TheType, SPIRVValue *Op1, SPIRVValue *Op2, SPIRVBasicBlock *BB) argument 1079 addSelectInst(SPIRVValue *Condition, SPIRVValue *Op1, SPIRVValue *Op2, SPIRVBasicBlock *BB) argument
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/external/llvm/lib/Analysis/ |
H A D | ConstantFolding.cpp | 1708 if (auto *Op2 = dyn_cast<ConstantFP>(Operands[1])) { 1709 if (Op2->getType() != Op1->getType()) 1712 double Op2V = getValueAsDouble(Op2); 1718 const APFloat &V2 = Op2->getValueAPF(); 1725 const APFloat &C2 = Op2->getValueAPF(); 1731 const APFloat &C2 = Op2->getValueAPF(); 1764 if (auto *Op2 = dyn_cast<ConstantInt>(Operands[1])) { 1778 Res = Op1->getValue().sadd_ov(Op2->getValue(), Overflow); 1781 Res = Op1->getValue().uadd_ov(Op2->getValue(), Overflow); 1784 Res = Op1->getValue().ssub_ov(Op2 [all...] |
H A D | CFLGraph.h | 251 auto *Op2 = Inst.getOperand(1); local 253 addAssignEdge(Op2, &Inst);
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/external/llvm/lib/Target/X86/ |
H A D | X86OptimizeLEAs.cpp | 368 const MachineOperand &Op2 = MI2.getOperand(N2 + X86::AddrDisp); local 370 assert(isSimilarDispOp(Op1, Op2) && 378 return Op1.isImm() ? Op1.getImm() - Op2.getImm() 379 : Op1.getOffset() - Op2.getOffset();
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/external/swiftshader/third_party/LLVM/include/llvm/Analysis/ |
H A D | ScalarEvolution.h | 573 const SCEV *getAddExpr(const SCEV *Op0, const SCEV *Op1, const SCEV *Op2, argument 578 Ops.push_back(Op2); 591 const SCEV *getMulExpr(const SCEV *Op0, const SCEV *Op1, const SCEV *Op2, argument 596 Ops.push_back(Op2);
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/external/swiftshader/third_party/LLVM/lib/Analysis/ |
H A D | ConstantFolding.cpp | 1337 if (ConstantFP *Op2 = dyn_cast<ConstantFP>(Operands[1])) { 1338 if (Op2->getType() != Op1->getType()) 1342 (double)Op2->getValueAPF().convertToFloat(): 1343 Op2->getValueAPF().convertToDouble(); 1366 if (ConstantInt *Op2 = dyn_cast<ConstantInt>(Operands[1])) { 1380 Res = Op1->getValue().sadd_ov(Op2->getValue(), Overflow); 1383 Res = Op1->getValue().uadd_ov(Op2->getValue(), Overflow); 1386 Res = Op1->getValue().ssub_ov(Op2->getValue(), Overflow); 1389 Res = Op1->getValue().usub_ov(Op2->getValue(), Overflow); 1392 Res = Op1->getValue().smul_ov(Op2 [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
H A D | MipsISelDAGToDAG.cpp | 246 SDValue Op2 = Node->getOperand(1); local 251 SDNode *Mul = CurDAG->getMachineNode(Op, dl, MVT::Glue, Op1, Op2);
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/external/llvm/lib/Target/X86/AsmParser/ |
H A D | X86AsmParser.cpp | 176 ICToken Op2 = OperandStack.pop_back_val(); local 183 Val = Op1.second + Op2.second; 187 Val = Op1.second - Op2.second; 191 assert (Op1.first == IC_IMM && Op2.first == IC_IMM && 193 Val = Op1.second * Op2.second; 197 assert (Op1.first == IC_IMM && Op2.first == IC_IMM && 199 assert (Op2.second != 0 && "Division by zero!"); 200 Val = Op1.second / Op2.second; 204 assert (Op1.first == IC_IMM && Op2.first == IC_IMM && 206 Val = Op1.second | Op2 [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAG.cpp | 291 ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2, argument 293 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 297 unsigned Op = Op1 | Op2; // Combine all of the condition bits. 311 ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2, argument 313 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 318 ISD::CondCode Result = ISD::CondCode(Op1 & Op2); 839 SDValue Op1, SDValue Op2, 844 SDValue Ops[] = { Op1, Op2 }; 5746 SDNode *SelectionDAG::UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2) { argument 5750 if (Op1 == N->getOperand(0) && Op2 838 FindModifiedNodeSlot(SDNode *N, SDValue Op1, SDValue Op2, void *&InsertPos) argument 5775 UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3) argument 5781 UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3, SDValue Op4) argument 5788 UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3, SDValue Op4, SDValue Op5) argument 5851 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT, SDValue Op1, SDValue Op2) argument 5859 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT, SDValue Op1, SDValue Op2, SDValue Op3) argument 5907 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2, SDValue Op1, SDValue Op2) argument 5915 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3) argument 5924 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2, EVT VT3, SDValue Op1, SDValue Op2, SDValue Op3) argument 6051 getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT, SDValue Op1, SDValue Op2) argument 6058 getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT, SDValue Op1, SDValue Op2, SDValue Op3) argument 6085 getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT1, EVT VT2, SDValue Op1, SDValue Op2) argument 6093 getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT1, EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3) argument 6108 getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT1, EVT VT2, EVT VT3, SDValue Op1, SDValue Op2) argument 6116 getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT1, EVT VT2, EVT VT3, SDValue Op1, SDValue Op2, SDValue Op3) argument [all...] |
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAG.cpp | 262 ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2, argument 264 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 268 unsigned Op = Op1 | Op2; // Combine all of the condition bits. 286 ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2, argument 288 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 293 ISD::CondCode Result = ISD::CondCode(Op1 & Op2); 717 SDValue Op1, SDValue Op2, 722 SDValue Ops[] = { Op1, Op2 }; 4701 SDNode *SelectionDAG::UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2) { argument 4705 if (Op1 == N->getOperand(0) && Op2 716 FindModifiedNodeSlot(SDNode *N, SDValue Op1, SDValue Op2, void *&InsertPos) argument 4730 UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3) argument 4736 UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3, SDValue Op4) argument 4743 UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3, SDValue Op4, SDValue Op5) argument 4813 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT, SDValue Op1, SDValue Op2) argument 4821 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT, SDValue Op1, SDValue Op2, SDValue Op3) argument 4871 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2, SDValue Op1, SDValue Op2) argument 4879 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3) argument 4888 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2, EVT VT3, SDValue Op1, SDValue Op2, SDValue Op3) argument 5017 getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT, SDValue Op1, SDValue Op2) argument 5025 getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT, SDValue Op1, SDValue Op2, SDValue Op3) argument 5054 getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2, SDValue Op1, SDValue Op2) argument 5062 getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3) argument 5079 getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2, EVT VT3, SDValue Op1, SDValue Op2) argument 5088 getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2, EVT VT3, SDValue Op1, SDValue Op2, SDValue Op3) argument [all...] |
H A D | SelectionDAGBuilder.cpp | 1854 SDValue Op2 = DAG.getNode(ISD::EHSELECTION, getCurDebugLoc(), VTs, Ops, 2); local 1855 Chain = Op2.getValue(1); 1856 Op2 = DAG.getSExtOrTrunc(Op2, getCurDebugLoc(), MVT::i32); 1859 Ops[1] = Op2; 2542 SDValue Op2 = getValue(I.getOperand(1)); local 2544 Op2.getValueType(), Op2)); 2553 SDValue Op2 = getValue(I.getOperand(1)); local 2555 Op1.getValueType(), Op1, Op2)); 2560 SDValue Op2 = getValue(I.getOperand(1)); local 2592 SDValue Op2 = getValue(I.getOperand(1)); local 2613 SDValue Op2 = getValue(I.getOperand(1)); local 2627 SDValue Op2 = getValue(I.getOperand(1)); local 3604 SDValue Op2 = getValue(I.getArgOperand(1)); local 4488 SDValue Op2 = getValue(I.getArgOperand(1)); local 4504 SDValue Op2 = getValue(I.getArgOperand(1)); local 4521 SDValue Op2 = getValue(I.getArgOperand(1)); local [all...] |
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
H A D | FastISel.h | 264 unsigned Op2, bool Op2IsKill);
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/external/swiftshader/third_party/LLVM/lib/AsmParser/ |
H A D | LLParser.cpp | 3058 BasicBlock *Op1, *Op2; 3072 ParseTypeAndBasicBlock(Op2, Loc2, PFS)) 3075 Inst = BranchInst::Create(Op1, Op2, Op0); 3383 Value *Op0, *Op1, *Op2; 3388 ParseTypeAndValue(Op2, PFS)) 3391 if (const char *Reason = SelectInst::areInvalidOperands(Op0, Op1, Op2)) 3394 Inst = SelectInst::Create(Op0, Op1, Op2); 3437 Value *Op0, *Op1, *Op2; 3442 ParseTypeAndValue(Op2, PFS)) 3445 if (!InsertElementInst::isValidOperands(Op0, Op1, Op2)) [all...] |
/external/llvm/include/llvm/Analysis/ |
H A D | ScalarEvolution.h | 1207 const SCEV *getAddExpr(const SCEV *Op0, const SCEV *Op1, const SCEV *Op2, argument 1209 SmallVector<const SCEV *, 3> Ops = {Op0, Op1, Op2}; 1219 const SCEV *getMulExpr(const SCEV *Op0, const SCEV *Op1, const SCEV *Op2, argument 1221 SmallVector<const SCEV *, 3> Ops = {Op0, Op1, Op2};
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