Searched refs:RetVT (Results 1 - 25 of 28) sorted by relevance

12

/external/swiftshader/third_party/LLVM/lib/Target/X86/
H A DX86GenFastISel.inc26 unsigned FastEmit_ISD_ANY_EXTEND_MVT_i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
27 switch (RetVT.SimpleTy) {
34 unsigned FastEmit_ISD_ANY_EXTEND_MVT_i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
35 if (RetVT.SimpleTy != MVT::i64)
40 unsigned FastEmit_ISD_ANY_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
42 case MVT::i8: return FastEmit_ISD_ANY_EXTEND_MVT_i8_r(RetVT, Op0, Op0IsKill);
43 case MVT::i16: return FastEmit_ISD_ANY_EXTEND_MVT_i16_r(RetVT, Op0, Op0IsKill);
50 unsigned FastEmit_ISD_BITCAST_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
51 if (RetVT.SimpleTy != MVT::f32)
80 unsigned FastEmit_ISD_BITCAST_MVT_i64_r(MVT RetVT, unsigne
[all...]
/external/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp153 bool optimizeIntExtLoad(const Instruction *I, MVT RetVT, MVT SrcVT);
158 unsigned emitAddSub(bool UseAdd, MVT RetVT, const Value *LHS,
161 unsigned emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg,
164 unsigned emitAddSub_ri(bool UseAdd, MVT RetVT, unsigned LHSReg,
167 unsigned emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg,
172 unsigned emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg,
181 bool emitICmp(MVT RetVT, const Value *LHS, const Value *RHS, bool IsZExt);
182 bool emitICmp_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, uint64_t Imm);
183 bool emitFCmp(MVT RetVT, const Value *LHS, const Value *RHS);
190 unsigned emitAdd(MVT RetVT, cons
1081 emitAddSub(bool UseAdd, MVT RetVT, const Value *LHS, const Value *RHS, bool SetFlags, bool WantResult, bool IsZExt) argument
1235 emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg, bool LHSIsKill, unsigned RHSReg, bool RHSIsKill, bool SetFlags, bool WantResult) argument
1269 emitAddSub_ri(bool UseAdd, MVT RetVT, unsigned LHSReg, bool LHSIsKill, uint64_t Imm, bool SetFlags, bool WantResult) argument
1314 emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg, bool LHSIsKill, unsigned RHSReg, bool RHSIsKill, AArch64_AM::ShiftExtendType ShiftType, uint64_t ShiftImm, bool SetFlags, bool WantResult) argument
1355 emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg, bool LHSIsKill, unsigned RHSReg, bool RHSIsKill, AArch64_AM::ShiftExtendType ExtType, uint64_t ShiftImm, bool SetFlags, bool WantResult) argument
1420 emitICmp(MVT RetVT, const Value *LHS, const Value *RHS, bool IsZExt) argument
1426 emitICmp_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, uint64_t Imm) argument
1432 emitFCmp(MVT RetVT, const Value *LHS, const Value *RHS) argument
1467 emitAdd(MVT RetVT, const Value *LHS, const Value *RHS, bool SetFlags, bool WantResult, bool IsZExt) argument
1497 emitSub(MVT RetVT, const Value *LHS, const Value *RHS, bool SetFlags, bool WantResult, bool IsZExt) argument
1503 emitSubs_rr(MVT RetVT, unsigned LHSReg, bool LHSIsKill, unsigned RHSReg, bool RHSIsKill, bool WantResult) argument
1510 emitSubs_rs(MVT RetVT, unsigned LHSReg, bool LHSIsKill, unsigned RHSReg, bool RHSIsKill, AArch64_AM::ShiftExtendType ShiftType, uint64_t ShiftImm, bool WantResult) argument
1520 emitLogicalOp(unsigned ISDOpc, MVT RetVT, const Value *LHS, const Value *RHS) argument
1604 emitLogicalOp_ri(unsigned ISDOpc, MVT RetVT, unsigned LHSReg, bool LHSIsKill, uint64_t Imm) argument
1650 emitLogicalOp_rs(unsigned ISDOpc, MVT RetVT, unsigned LHSReg, bool LHSIsKill, unsigned RHSReg, bool RHSIsKill, uint64_t ShiftImm) argument
1693 emitAnd_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, uint64_t Imm) argument
1698 emitLoad(MVT VT, MVT RetVT, Address Addr, bool WantZExt, MachineMemOperand *MMO) argument
1921 MVT RetVT = VT; local
3021 finishCall(CallLoweringInfo &CLI, MVT RetVT, unsigned NumBytes) argument
3252 MVT RetVT; local
3416 MVT RetVT; local
3868 emitMul_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) argument
3888 emitSMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) argument
3898 emitUMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) argument
3908 emitLSL_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill, unsigned Op1Reg, bool Op1IsKill) argument
3934 emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0, bool Op0IsKill, uint64_t Shift, bool IsZExt) argument
4014 emitLSR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill, unsigned Op1Reg, bool Op1IsKill) argument
4041 emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0, bool Op0IsKill, uint64_t Shift, bool IsZExt) argument
4135 emitASR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill, unsigned Op1Reg, bool Op1IsKill) argument
4162 emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0, bool Op0IsKill, uint64_t Shift, bool IsZExt) argument
4353 optimizeIntExtLoad(const Instruction *I, MVT RetVT, MVT SrcVT) argument
4409 MVT RetVT; local
4580 MVT RetVT; local
4669 MVT RetVT, SrcVT; local
4710 MVT RetVT; local
[all...]
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
H A DRuntimeLibcalls.h306 Libcall getFPEXT(EVT OpVT, EVT RetVT);
310 Libcall getFPROUND(EVT OpVT, EVT RetVT);
314 Libcall getFPTOSINT(EVT OpVT, EVT RetVT);
318 Libcall getFPTOUINT(EVT OpVT, EVT RetVT);
322 Libcall getSINTTOFP(EVT OpVT, EVT RetVT);
326 Libcall getUINTTOFP(EVT OpVT, EVT RetVT);
H A DFastISel.h158 MVT RetVT,
166 MVT RetVT,
175 MVT RetVT,
185 MVT RetVT,
195 MVT RetVT,
205 MVT RetVT,
224 MVT RetVT,
232 MVT RetVT,
312 unsigned FastEmitInst_extractsubreg(MVT RetVT,
/external/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp501 RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) { argument
503 if (RetVT == MVT::f32)
506 if (RetVT == MVT::f64)
508 if (RetVT == MVT::f128)
510 if (RetVT == MVT::ppcf128)
513 if (RetVT == MVT::f128)
515 else if (RetVT == MVT::ppcf128)
524 RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) { argument
525 if (RetVT == MVT::f16) {
536 } else if (RetVT
559 getFPTOSINT(EVT OpVT, EVT RetVT) argument
601 getFPTOUINT(EVT OpVT, EVT RetVT) argument
643 getSINTTOFP(EVT OpVT, EVT RetVT) argument
683 getUINTTOFP(EVT OpVT, EVT RetVT) argument
[all...]
/external/llvm/include/llvm/CodeGen/
H A DRuntimeLibcalls.h481 Libcall getFPEXT(EVT OpVT, EVT RetVT);
485 Libcall getFPROUND(EVT OpVT, EVT RetVT);
489 Libcall getFPTOSINT(EVT OpVT, EVT RetVT);
493 Libcall getFPTOUINT(EVT OpVT, EVT RetVT);
497 Libcall getSINTTOFP(EVT OpVT, EVT RetVT);
501 Libcall getUINTTOFP(EVT OpVT, EVT RetVT);
H A DFastISel.h341 virtual unsigned fastEmit_(MVT VT, MVT RetVT, unsigned Opcode);
345 virtual unsigned fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0,
350 virtual unsigned fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0,
356 virtual unsigned fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0,
362 virtual unsigned fastEmit_rf(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0,
368 virtual unsigned fastEmit_rri(MVT VT, MVT RetVT, unsigned Opcode,
382 virtual unsigned fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t Imm);
387 virtual unsigned fastEmit_f(MVT VT, MVT RetVT, unsigned Opcode,
446 unsigned fastEmitInst_extractsubreg(MVT RetVT, unsigned Op0, bool Op0IsKill,
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp338 RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) { argument
340 if (RetVT == MVT::f64)
349 RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) { argument
350 if (RetVT == MVT::f32) {
357 } else if (RetVT == MVT::f64) {
369 RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) { argument
371 if (RetVT == MVT::i8)
373 if (RetVT == MVT::i16)
375 if (RetVT == MVT::i32)
377 if (RetVT
412 getFPTOUINT(EVT OpVT, EVT RetVT) argument
455 getSINTTOFP(EVT OpVT, EVT RetVT) argument
489 getUINTTOFP(EVT OpVT, EVT RetVT) argument
[all...]
H A DLegalizeFloatTypes.cpp680 EVT RetVT = TLI.getCmpLibcallReturnType(); local
682 NewLHS = MakeLibCall(LC1, RetVT, Ops, 2, false/*sign irrelevant*/, dl);
683 NewRHS = DAG.getConstant(0, RetVT);
686 SDValue Tmp = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(RetVT),
688 NewLHS = MakeLibCall(LC2, RetVT, Ops, 2, false/*sign irrelevant*/, dl);
689 NewLHS = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(RetVT), NewLHS,
H A DLegalizeTypes.cpp1038 /// returning a result of type RetVT.
1039 SDValue DAGTypeLegalizer::MakeLibCall(RTLIB::Libcall LC, EVT RetVT, argument
1056 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
H A DLegalizeVectorTypes.cpp2188 EVT RetVT = WidenEltVT; local
2190 return RetVT;
2204 RetVT = MemVT;
2220 if (RetVT.getSizeInBits() < MemVTWidth || MemVT == WidenVT)
2225 return RetVT;
H A DFastISel.cpp1297 unsigned FastISel::FastEmitInst_extractsubreg(MVT RetVT, argument
1300 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
H A DLegalizeTypes.h160 SDValue MakeLibCall(RTLIB::Libcall LC, EVT RetVT,
H A DLegalizeDAG.cpp117 SDValue ExpandLibCall(RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops,
2236 /// and returning a result of type RetVT.
2237 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, EVT RetVT,
2254 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2404 EVT RetVT = Node->getValueType(0);
2405 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2419 SDValue FIPtr = DAG.CreateStackTemporary(RetVT);
2442 SDValue Rem = DAG.getLoad(RetVT, dl, LastCALLSEQ_END, FIPtr,
/external/llvm/utils/TableGen/
H A DFastISelEmitter.cpp512 MVT::SimpleValueType RetVT = MVT::isVoid;
513 if (InstPatNode->getNumTypes()) RetVT = InstPatNode->getType(0);
514 MVT::SimpleValueType VT = RetVT;
587 [RetVT].count(PredicateCheck)) {
591 SimplePatternsCheck[Operands][OpcodeName][VT][RetVT].insert(
596 SimplePatterns[Operands][OpcodeName][VT][RetVT].insert(
713 MVT::SimpleValueType RetVT = RI->first;
719 << "_" << getLegalCName(getName(RetVT)) << "_";
725 emitInstructionCode(OS, Operands, PM, getName(RetVT));
733 OS << "(MVT RetVT";
[all...]
/external/swiftshader/third_party/LLVM/utils/TableGen/
H A DFastISelEmitter.cpp488 MVT::SimpleValueType RetVT = MVT::isVoid;
489 if (InstPatNode->getNumTypes()) RetVT = InstPatNode->getType(0);
490 MVT::SimpleValueType VT = RetVT;
547 if (SimplePatterns[Operands][OpcodeName][VT][RetVT].count(PredicateCheck))
551 SimplePatterns[Operands][OpcodeName][VT][RetVT][PredicateCheck] = Memo;
601 MVT::SimpleValueType RetVT = RI->first;
608 << "_" << getLegalCName(getName(RetVT)) << "_";
649 OS << "extractsubreg(" << getName(RetVT);
669 OS << "(MVT RetVT";
673 OS << ") {\nswitch (RetVT
[all...]
/external/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp188 bool finishCall(MVT RetVT, CallLoweringInfo &CLI, unsigned &NumBytes);
1393 bool PPCFastISel::finishCall(MVT RetVT, CallLoweringInfo &CLI, unsigned &NumBytes) { argument
1404 if (RetVT != MVT::isVoid) {
1407 CCInfo.AnalyzeCallResult(RetVT, RetCC_PPC64_ELF_FIS);
1417 if (RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32)
1423 if (RetVT == CopyVT) {
1433 ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
1441 } else if (RetVT
1480 MVT RetVT; local
[all...]
/external/llvm/lib/Target/ARM/
H A DARMFastISel.cpp200 bool FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
2016 bool ARMFastISel::FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs, argument
2026 if (RetVT != MVT::isVoid) {
2029 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, isVarArg));
2032 if (RVLocs.size() == 2 && RetVT == MVT::f64) {
2053 if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
2192 MVT RetVT; local
2194 RetVT
2300 MVT RetVT; local
[all...]
/external/llvm/lib/Target/X86/
H A DX86FastISel.cpp119 bool X86FastEmitCMoveSelect(MVT RetVT, const Instruction *I);
121 bool X86FastEmitSSESelect(MVT RetVT, const Instruction *I);
123 bool X86FastEmitPseudoSelect(MVT RetVT, const Instruction *I);
276 MVT RetVT; local
280 if (!isTypeLegal(RetTy, RetVT))
283 if (RetVT != MVT::i32 && RetVT != MVT::i64)
1936 bool X86FastISel::X86FastEmitCMoveSelect(MVT RetVT, const Instruction *I) { argument
1942 if (RetVT < MVT::i16 || RetVT > MV
2056 X86FastEmitSSESelect(MVT RetVT, const Instruction *I) argument
2160 X86FastEmitPseudoSelect(MVT RetVT, const Instruction *I) argument
2225 MVT RetVT; local
[all...]
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
H A DARMFastISel.cpp143 virtual unsigned FastEmitInst_extractsubreg(MVT RetVT,
199 bool FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
461 unsigned ARMFastISel::FastEmitInst_extractsubreg(MVT RetVT, argument
464 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
1668 bool ARMFastISel::FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs, argument
1678 if (RetVT != MVT::isVoid) {
1681 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true));
1684 if (RVLocs.size() == 2 && RetVT == MVT::f64) {
1804 MVT RetVT; local
1806 RetVT
1902 MVT RetVT; local
[all...]
/external/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp153 unsigned emitLogicalOp(unsigned ISDOpc, MVT RetVT, const Value *LHS,
197 bool finishCall(CallLoweringInfo &CLI, MVT RetVT, unsigned NumBytes);
246 unsigned MipsFastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT, argument
1220 bool MipsFastISel::finishCall(CallLoweringInfo &CLI, MVT RetVT, argument
1224 if (RetVT != MVT::isVoid) {
1227 CCInfo.AnalyzeCallResult(RetVT, RetCC_Mips);
1235 if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
1275 MVT RetVT;
1706 MVT RetVT; local
[all...]
/external/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFastISel.cpp948 EVT RetVT = TLI.getValueType(DL, I->getType()); local
949 if (!VT.isSimple() || !RetVT.isSimple())
952 if (VT == RetVT) {
958 unsigned Reg = fastEmit_ISD_BITCAST_r(VT.getSimpleVT(), RetVT.getSimpleVT(),
/external/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp113 SDValue ExpandLibCall(RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops,
1988 /// and returning a result of type RetVT.
1989 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, EVT RetVT,
2006 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2110 EVT RetVT = Node->getValueType(0);
2111 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2126 SDValue FIPtr = DAG.CreateStackTemporary(RetVT);
2145 SDValue Rem = DAG.getLoad(RetVT, dl, CallInfo.second, FIPtr,
2215 EVT RetVT = Node->getValueType(0);
2216 Type *RetTy = RetVT
[all...]
H A DTargetLowering.cpp115 /// result of type RetVT.
117 TargetLowering::makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, argument
138 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
140 bool signExtend = shouldSignExtendTypeInLibCall(RetVT, isSigned);
253 EVT RetVT = getCmpLibcallReturnType(); local
255 NewLHS = makeLibCall(DAG, LC1, RetVT, Ops, false /*sign irrelevant*/,
257 NewRHS = DAG.getConstant(0, dl, RetVT);
266 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), RetVT),
268 NewLHS = makeLibCall(DAG, LC2, RetVT, Ops, false/*sign irrelevant*/,
272 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), RetVT),
[all...]
H A DLegalizeVectorTypes.cpp3410 EVT RetVT = WidenEltVT; local
3412 return RetVT;
3429 RetVT = MemVT;
3445 if (RetVT.getSizeInBits() < MemVTWidth || MemVT == WidenVT)
3450 return RetVT;

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