/external/llvm/lib/Target/AMDGPU/ |
H A D | SIFrameLowering.cpp | 102 MRI.addLiveIn(FlatScratchInitReg); 103 MBB.addLiveIn(FlatScratchInitReg); 136 MRI.addLiveIn(PreloadedScratchWaveOffsetReg); 137 MBB.addLiveIn(PreloadedScratchWaveOffsetReg); 140 MRI.addLiveIn(PreloadedPrivateBufferReg); 141 MBB.addLiveIn(PreloadedPrivateBufferReg); 269 OtherBB.addLiveIn(ScratchRsrcReg); 270 OtherBB.addLiveIn(ScratchWaveOffsetReg); 314 MF.getRegInfo().addLiveIn(WorkGroupIDSGPR); 315 MBB.addLiveIn(WorkGroupIDSGP [all...] |
H A D | SIISelLowering.cpp | 701 MF.addLiveIn(PrivateSegmentBufferReg, &AMDGPU::SReg_128RegClass); 707 MF.addLiveIn(DispatchPtrReg, &AMDGPU::SReg_64RegClass); 713 MF.addLiveIn(QueuePtrReg, &AMDGPU::SReg_64RegClass); 719 MF.addLiveIn(InputPtrReg, &AMDGPU::SReg_64RegClass); 725 MF.addLiveIn(FlatScratchInitReg, &AMDGPU::SReg_64RegClass); 778 Reg = MF.addLiveIn(Reg, &AMDGPU::SReg_64RegClass); 786 Reg = MF.addLiveIn(Reg, RC); 799 Reg = MF.addLiveIn(Reg, RC); 822 MF.addLiveIn(Reg, &AMDGPU::SReg_32RegClass); 828 MF.addLiveIn(Re [all...] |
H A D | SILowerControlFlow.cpp | 426 LoopBB.addLiveIn(Val->getReg()); 432 RemainderBB.addLiveIn(Reg); 437 LoopBB.addLiveIn(Src->getReg()); 440 LoopBB.addLiveIn(IdxReg.getReg());
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H A D | SIMachineFunctionInfo.cpp | 218 BI->addLiveIn(LaneVGPR);
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64ExpandPseudoInsts.cpp | 594 MBB->addLiveIn(*I); 627 LoadCmpBB->addLiveIn(Addr.getReg()); 628 LoadCmpBB->addLiveIn(Dest.getReg()); 629 LoadCmpBB->addLiveIn(Desired.getReg()); 648 StoreBB->addLiveIn(Addr.getReg()); 649 StoreBB->addLiveIn(New.getReg()); 706 LoadCmpBB->addLiveIn(Addr.getReg()); 707 LoadCmpBB->addLiveIn(DestLo.getReg()); 708 LoadCmpBB->addLiveIn(DestHi.getReg()); 709 LoadCmpBB->addLiveIn(DesiredL [all...] |
H A D | AArch64CallLowering.cpp | 84 MIRBuilder.getMBB().addLiveIn(VA.getLocReg());
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H A D | AArch64RedundantCopyElimination.cpp | 158 MBB->addLiveIn(TargetReg);
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/external/swiftshader/third_party/LLVM/lib/Target/XCore/ |
H A D | XCoreFrameLowering.cpp | 130 MBB.addLiveIn(XCore::LR); 158 MBB.addLiveIn(XCore::LR); 175 MBB.addLiveIn(XCore::R10); 293 MBB.addLiveIn(it->getReg());
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/external/swiftshader/third_party/LLVM/lib/CodeGen/ |
H A D | MachineRegisterInfo.cpp | 237 EntryMBB->addLiveIn(LiveIns[i].first); 241 EntryMBB->addLiveIn(LiveIns[i].first);
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/external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
H A D | MSP430FrameLowering.cpp | 76 I->addLiveIn(MSP430::FPW); 198 MBB.addLiveIn(Reg);
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/external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
H A D | SystemZFrameLowering.cpp | 136 I->addLiveIn(SystemZ::R11D); 280 MBB.addLiveIn(Reg); 290 MBB.addLiveIn(Reg);
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonCFGOptimizer.cpp | 224 LayoutSucc->addLiveIn(NewLI);
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/external/llvm/lib/Target/Mips/ |
H A D | Mips16FrameLowering.cpp | 130 EntryBlock->addLiveIn(Reg);
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H A D | MipsSEISelDAGToDAG.cpp | 150 MF.getRegInfo().addLiveIn(Mips::T9_64); 151 MBB.addLiveIn(Mips::T9_64); 178 MF.getRegInfo().addLiveIn(Mips::T9); 179 MBB.addLiveIn(Mips::T9); 213 MF.getRegInfo().addLiveIn(Mips::V0); 214 MBB.addLiveIn(Mips::V0);
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/external/llvm/lib/Target/MSP430/ |
H A D | MSP430FrameLowering.cpp | 77 I->addLiveIn(MSP430::FP); 199 MBB.addLiveIn(Reg);
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/external/llvm/include/llvm/CodeGen/ |
H A D | MachineBasicBlock.h | 288 void addLiveIn(MCPhysReg PhysReg, LaneBitmask LaneMask = ~0u) { function in class:llvm::MachineBasicBlock 291 void addLiveIn(const RegisterMaskPair &RegMaskPair) { function in class:llvm::MachineBasicBlock 296 /// this than repeatedly calling isLiveIn before calling addLiveIn for every 303 unsigned addLiveIn(MCPhysReg PhysReg, const TargetRegisterClass *RC);
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/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZFrameLowering.cpp | 127 MBB.addLiveIn(GPR64); 211 MBB.addLiveIn(Reg); 404 I->addLiveIn(SystemZ::R11D);
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/external/llvm/lib/CodeGen/ |
H A D | ImplicitNullChecks.cpp | 547 MBB->addLiveIn(Reg); 555 NC.getNotNullSucc()->addLiveIn(MO.getReg());
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H A D | MachineRegisterInfo.cpp | 419 EntryMBB->addLiveIn(LiveIns[i].first); 423 EntryMBB->addLiveIn(LiveIns[i].first);
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H A D | VirtRegMap.cpp | 283 MBB->addLiveIn(PhysReg, LaneMask); 313 MBB->addLiveIn(PhysReg); 320 // each MBB's LiveIns set before calling addLiveIn on them.
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/external/llvm/lib/Target/Sparc/ |
H A D | SparcFrameLowering.cpp | 342 MBB->addLiveIn(reg - SP::I0_I1 + SP::O0_O1); 348 MBB->addLiveIn(reg - SP::I0 + SP::O0);
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/external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
H A D | AlphaInstrInfo.cpp | 353 RegInfo.addLiveIn(Alpha::R29); 378 RegInfo.addLiveIn(Alpha::R26);
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/external/swiftshader/third_party/LLVM/lib/Target/X86/ |
H A D | X86FrameLowering.cpp | 745 I->addLiveIn(FramePtr); 1175 MBB.addLiveIn(Reg); 1195 MBB.addLiveIn(Reg); 1357 allocMBB->addLiveIn(*i); 1358 checkMBB->addLiveIn(*i); 1361 restoreR10MBB->addLiveIn(*i); 1365 allocMBB->addLiveIn(X86::R10); 1366 restoreR10MBB->addLiveIn(X86::RAX);
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/external/llvm/lib/Target/ARM/ |
H A D | ARMExpandPseudoInsts.cpp | 757 MBB->addLiveIn(*I); 804 LoadCmpBB->addLiveIn(Addr.getReg()); 805 LoadCmpBB->addLiveIn(Dest.getReg()); 806 LoadCmpBB->addLiveIn(Desired.getReg()); 832 StoreBB->addLiveIn(Addr.getReg()); 833 StoreBB->addLiveIn(New.getReg()); 918 LoadCmpBB->addLiveIn(Addr.getReg()); 919 LoadCmpBB->addLiveIn(Dest.getReg()); 920 LoadCmpBB->addLiveIn(Desired.getReg()); 955 StoreBB->addLiveIn(Add [all...] |
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
H A D | MachineRegisterInfo.h | 299 /// addLiveIn/Out - Add the specified register as a live in/out. Note that it 301 void addLiveIn(unsigned Reg, unsigned vreg = 0) { function in class:llvm::MachineRegisterInfo
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