Searched defs:MO (Results 151 - 175 of 253) sorted by relevance

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/external/swiftshader/third_party/LLVM/lib/CodeGen/
H A DPostRASchedulerList.cpp179 bool ToggleKillFlag(MachineInstr *MI, MachineOperand &MO);
399 MachineOperand &MO) {
401 if (!MO.isKill()) {
402 MO.setIsKill(true);
406 // If MO itself is live, clear the kill flag...
407 if (KillIndices[MO.getReg()] != ~0u) {
408 MO.setIsKill(false);
412 // If any subreg of MO is live, then create an imp-def for that
413 // subreg and keep MO marked as killed.
414 MO
398 ToggleKillFlag(MachineInstr *MI, MachineOperand &MO) argument
457 MachineOperand &MO = MI->getOperand(i); local
479 MachineOperand &MO = MI->getOperand(i); local
515 MachineOperand &MO = MI->getOperand(i); local
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H A DPrologEpilogInserter.cpp832 MachineOperand &MO = MI->getOperand(i); local
833 unsigned Reg = MO.getReg();
H A DScheduleDAGInstrs.cpp165 const MachineOperand &MO = ExitMI->getOperand(i); local
166 if (!MO.isReg() || MO.isDef()) continue;
167 unsigned Reg = MO.getReg();
257 const MachineOperand &MO = MI->getOperand(j); local
258 if (!MO.isReg()) continue;
259 unsigned Reg = MO.getReg();
273 SDep::Kind Kind = MO.isUse() ? SDep::Anti : SDep::Output;
280 (Kind != SDep::Output || !MO.isDead() ||
291 (Kind != SDep::Output || !MO
602 const MachineOperand &MO = DefMI->getOperand(DefIdx); local
618 const MachineOperand &MO = UseMI->getOperand(i); local
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H A DMachineBasicBlock.cpp441 MachineOperand &MO = MI->getOperand(i); local
442 if (MO.getMBB() == fromMBB)
443 MO.setMBB(this);
H A DRegAllocFast.cpp191 /// isLastUseOfLocalReg - Return true if MO is the only remaining reference to
194 bool RAFast::isLastUseOfLocalReg(MachineOperand &MO) { argument
195 // Check for non-debug uses or defs following MO.
197 MachineOperand *Next = &MO;
204 if (StackSlotForVirtReg[MO.getReg()] != -1)
207 // Check that the use/def chain has exactly one operand - MO.
208 return &MRI->reg_nodbg_begin(MO.getReg()).getOperand() == &MO;
214 MachineOperand &MO = LR.LastUse->getOperand(LR.LastOpNum);
215 if (MO
324 usePhysReg(MachineOperand &MO) argument
583 MachineOperand &MO = MI->getOperand(OpNum); local
628 MachineOperand &MO = MI->getOperand(OpNum); local
654 MachineOperand &MO = MI->getOperand(i); local
670 MachineOperand &MO = MI->getOperand(i); local
687 MachineOperand &MO = MI->getOperand(i); local
719 MachineOperand &MO = MI->getOperand(i); local
814 MachineOperand &MO = MI->getOperand(i); local
879 MachineOperand &MO = MI->getOperand(i); local
929 MachineOperand &MO = MI->getOperand(i); local
949 MachineOperand &MO = MI->getOperand(i); local
979 MachineOperand &MO = MI->getOperand(i); local
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H A DShrinkWrapping.cpp417 const MachineOperand &MO = I->getOperand(opInx); local
418 if (! (MO.isReg() && (MO.isUse() || MO.isDef())))
420 unsigned MOReg = MO.getReg();
H A DStackSlotColoring.cpp189 MachineOperand &MO = MI->getOperand(i); local
190 if (!MO.isFI())
192 int FI = MO.getIndex();
457 MachineOperand &MO = MI->getOperand(j); local
458 if (MO.isFI() && MO.getIndex() != SS)
472 MachineOperand &MO = MI->getOperand(i); local
473 if (!MO.isFI())
475 int FI = MO.getIndex();
478 MO
509 MachineOperand &MO = MII->getOperand(i); local
571 MachineOperand &MO = MII->getOperand(i); local
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H A DStrongPHIElimination.cpp226 MachineOperand &MO = *OI; local
227 if (MO.isReg() && MO.isUse() && MO.getReg() == Reg)
228 return &MO;
535 const MachineOperand &MO = *I; local
541 if (!MO.isReg() || !MO.isDef())
544 unsigned DestReg = MO.getReg();
H A DTailDuplication.cpp416 MachineOperand &MO = NewMI->getOperand(i); local
417 if (!MO.isReg())
419 unsigned Reg = MO.getReg();
422 if (MO.isDef()) {
425 MO.setReg(NewReg);
432 MO.setReg(VI->second);
454 MachineOperand &MO = II->getOperand(i+1); local
455 if (MO.getMBB() == FromBB) {
469 MachineOperand &MO = II->getOperand(i+1); local
470 if (MO
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H A DVirtRegRewriter.cpp67 /// Note that operands may be added, so the MO reference is no longer valid.
68 static void substitutePhysReg(MachineOperand &MO, unsigned Reg, argument
70 if (MO.getSubReg()) {
71 MO.substPhysReg(Reg, TRI);
77 MachineInstr &MI = *MO.getParent();
78 if (MO.isUse() && !MO.isUndef() &&
79 (MO.isKill() || MI.isRegTiedToDefOperand(&MO-&MI.getOperand(0))))
82 MO
547 MachineOperand &MO = MI.getOperand(i); local
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/external/swiftshader/third_party/LLVM/lib/Target/PTX/
H A DPTXAsmPrinter.cpp543 MCOperand PTXAsmPrinter::GetSymbolRef(const MachineOperand &MO, argument
550 MCOperand PTXAsmPrinter::lowerOperand(const MachineOperand &MO) { argument
555 switch (MO.getType()) {
563 RegSymbolName = MFI->getRegisterName(MO.getReg());
569 MCOp = MCOperand::CreateImm(MO.getImm());
573 MO.getMBB()->getSymbol(), OutContext));
576 MCOp = GetSymbolRef(MO, Mang->getSymbol(MO.getGlobal()));
579 MCOp = GetSymbolRef(MO, GetExternalSymbolSymbol(MO
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H A DPTXInstrInfo.cpp164 const MachineOperand &MO = MI->getOperand(0); local
166 if (!MO.isReg() || RI.getRegClass(MO.getReg()) != &PTX::RegPredRegClass)
169 Pred.push_back(MO);
/external/llvm/lib/CodeGen/GlobalISel/
H A DRegBankSelect.cpp107 MachineOperand &MO, const RegisterBankInfo::ValueMapping &ValMapping,
116 unsigned Src = MO.getReg();
121 if (MO.isDef())
155 const MachineOperand &MO,
157 assert(MO.isReg() && "We should only repair register operand");
161 const RegisterBank *CurRegBank = RBI->getRegBank(MO.getReg(), *MRI, *TRI);
162 // If MO does not have a register bank, we should have just been
179 if (MO.isDef())
194 RegisterBankInfo::getSizeInBits(MO.getReg(), *MRI, *TRI));
227 RegBankSelect::RepairingPlacement &RepairPt, const MachineOperand &MO,
106 repairReg( MachineOperand &MO, const RegisterBankInfo::ValueMapping &ValMapping, RegBankSelect::RepairingPlacement &RepairPt, const iterator_range<SmallVectorImpl<unsigned>::const_iterator> &NewVRegs) argument
154 getRepairCost( const MachineOperand &MO, const RegisterBankInfo::ValueMapping &ValMapping) const argument
226 tryAvoidingSplit( RegBankSelect::RepairingPlacement &RepairPt, const MachineOperand &MO, const RegisterBankInfo::ValueMapping &ValMapping) const argument
367 const MachineOperand &MO = MI.getOperand(OpIdx); local
483 MachineOperand &MO = MI.getOperand(OpIdx); local
576 const MachineOperand &MO = MI.getOperand(OpIdx); local
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/external/llvm/lib/CodeGen/
H A DLiveVariables.cpp215 MachineOperand &MO = LastDef->getOperand(i); local
216 if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
218 unsigned DefReg = MO.getReg();
376 MachineOperand *MO = PhysRegDef[Reg]->findRegisterDefOperand(SubReg); local
377 if (MO) {
379 assert(!MO->isDead());
403 MachineOperand *MO = local
405 bool NeedEC = MO
422 HandleRegMask(const MachineOperand &MO) argument
516 MachineOperand &MO = MI.getOperand(i); local
693 MachineOperand &MO = MI.getOperand(i); local
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H A DRegAllocFast.cpp220 /// isLastUseOfLocalReg - Return true if MO is the only remaining reference to
223 bool RAFast::isLastUseOfLocalReg(MachineOperand &MO) { argument
226 if (StackSlotForVirtReg[MO.getReg()] != -1)
229 // Check that the use/def chain has exactly one operand - MO.
230 MachineRegisterInfo::reg_nodbg_iterator I = MRI->reg_nodbg_begin(MO.getReg());
231 if (&*I != &MO)
239 MachineOperand &MO = LR.LastUse->getOperand(LR.LastOpNum);
240 if (MO.isUse() && !LR.LastUse->isRegTiedToDefOperand(LR.LastOpNum)) {
241 if (MO.getReg() == LR.PhysReg)
242 MO
348 usePhysReg(MachineOperand &MO) argument
641 MachineOperand &MO = MI.getOperand(OpNum); local
686 MachineOperand &MO = MI->getOperand(OpNum); local
719 MachineOperand &MO = MI->getOperand(i); local
735 MachineOperand &MO = MI->getOperand(i); local
749 MachineOperand &MO = MI->getOperand(i); local
774 MachineOperand &MO = MI->getOperand(i); local
790 MachineOperand &MO = MI->getOperand(i); local
864 MachineOperand &MO = MI->getOperand(i); local
931 MachineOperand &MO = MI->getOperand(i); local
986 MachineOperand &MO = MI->getOperand(i); local
1004 MachineOperand &MO = MI->getOperand(i); local
1034 MachineOperand &MO = MI->getOperand(i); local
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H A DStackColoring.cpp431 const MachineOperand &MO = MI.getOperand(0); local
432 int Slot = MO.getIndex();
467 for (const MachineOperand &MO : MI.operands()) {
468 if (!MO.isFI())
470 int Slot = MO.getIndex();
545 for (const MachineOperand &MO : MI.operands()) {
546 if (!MO.isFI())
548 int Slot = MO.getIndex();
868 for (MachineOperand &MO : I.operands()) {
869 if (!MO
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H A DTailDuplicator.cpp343 MachineOperand &MO = NewMI->getOperand(i); local
344 if (!MO.isReg())
346 unsigned Reg = MO.getReg();
349 if (MO.isDef()) {
352 MO.setReg(NewReg);
383 MO.setReg(VI->second.Reg);
386 MO.setSubReg(TRI->composeSubRegIndices(MO.getSubReg(),
401 MO.setReg(NewReg);
409 MO
435 MachineOperand &MO = II->getOperand(i + 1); local
450 MachineOperand &MO = II->getOperand(i + 1); local
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/external/llvm/lib/Target/AMDGPU/
H A DR600ControlFlowFinalizer.cpp287 const MachineOperand &MO = *I; local
288 if (!MO.isReg())
290 if (MO.isDef()) {
291 unsigned Reg = MO.getReg();
299 if (MO.isUse()) {
300 unsigned Reg = MO.getReg();
413 for (MachineOperand &MO : BI->operands()) {
414 if (MO.isReg() && MO.isInternalRead())
415 MO
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/external/llvm/lib/Target/ARM/
H A DThumb2SizeReduction.cpp274 for (const MachineOperand &MO : CPSRDef->operands()) {
275 if (!MO.isReg() || MO.isUndef() || MO.isUse())
277 unsigned Reg = MO.getReg();
283 for (const MachineOperand &MO : Use->operands()) {
284 if (!MO.isReg() || MO.isUndef() || MO.isDef())
286 unsigned Reg = MO
354 const MachineOperand &MO = MI->getOperand(i); local
832 const MachineOperand &MO = MI->getOperand(i); local
903 const MachineOperand &MO = MI->getOperand(i); local
1041 MachineOperand *MO = BundleMI->findRegisterDefOperand(ARM::CPSR); local
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/external/llvm/lib/Target/Hexagon/
H A DHexagonStoreWidening.cpp108 const MachineOperand &MO = MI->getOperand(0); local
109 assert(MO.isReg() && "Expecting register operand");
110 return MO.getReg();
121 const MachineOperand &MO = MI->getOperand(1); local
122 assert(MO.isImm() && "Expecting immediate offset");
123 return MO.getImm();
/external/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.cpp361 const MachineOperand &MO = Instr.getOperand(IO); local
362 if (MO.isRegMask() && MO.clobbersPhysReg(Lanai::SR)) {
366 if (!MO.isReg() || MO.getReg() != Lanai::SR)
368 if (MO.isDef()) {
475 const MachineOperand &MO = MI->getOperand(i); local
477 if (MO.isFI() || MO.isCPI() || MO
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/external/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsMCCodeEmitter.cpp273 const MCOperand &MO = MI.getOperand(OpNo); local
276 if (MO.isImm()) return MO.getImm() >> 2;
278 assert(MO.isExpr() &&
282 MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
296 const MCOperand &MO = MI.getOperand(OpNo); local
299 if (MO.isImm()) return MO.getImm() >> 1;
301 assert(MO.isExpr() &&
305 MO
319 const MCOperand &MO = MI.getOperand(OpNo); local
343 const MCOperand &MO = MI.getOperand(OpNo); local
365 const MCOperand &MO = MI.getOperand(OpNo); local
387 const MCOperand &MO = MI.getOperand(OpNo); local
410 const MCOperand &MO = MI.getOperand(OpNo); local
433 const MCOperand &MO = MI.getOperand(OpNo); local
456 const MCOperand &MO = MI.getOperand(OpNo); local
478 const MCOperand &MO = MI.getOperand(OpNo); local
502 const MCOperand &MO = MI.getOperand(OpNo); local
521 const MCOperand &MO = MI.getOperand(OpNo); local
539 const MCOperand &MO = MI.getOperand(OpNo); local
557 const MCOperand &MO = MI.getOperand(OpNo); local
576 const MCOperand &MO = MI.getOperand(OpNo); local
590 const MCOperand &MO = MI.getOperand(OpNo); local
604 const MCOperand &MO = MI.getOperand(OpNo); local
760 getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
984 const MCOperand &MO = MI.getOperand(OpNo); local
1006 const MCOperand &MO = MI.getOperand(OpNo); local
1029 const MCOperand &MO = MI.getOperand(OpNo); local
1038 const MCOperand &MO = MI.getOperand(OpNo); local
1133 const MCOperand &MO = MI.getOperand(OpNo); local
[all...]
/external/llvm/lib/Target/Mips/
H A DMipsDelaySlotFiller.cpp301 const MachineOperand &MO = Filler->getOperand(I); local
304 if (!MO.isReg() || !MO.isDef() || !(R = MO.getReg()))
391 const MachineOperand &MO = MI.getOperand(I); local
393 if (MO.isReg() && MO.getReg())
394 HasHazard |= checkRegDefsUses(NewDefs, NewUses, MO.getReg(), MO.isDef());
/external/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp127 const MachineOperand &MO = MI.getOperand(i); local
128 if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
1461 const MachineOperand &MO = MI.getOperand(i);
1464 if (MO.isReg()) {
1465 if (MO.isDef() && RC->contains(MO.getReg())) {
1466 Pred.push_back(MO);
1469 } else if (MO
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/external/llvm/lib/Target/WebAssembly/
H A DWebAssemblyRegStackify.cpp97 const MachineOperand &MO = MI.getOperand(CalleeOpNo); local
98 if (MO.isGlobal()) {
99 const Constant *GV = MO.getGlobal();
282 for (const MachineOperand &MO : Def->operands()) {
283 if (!MO.isReg() || MO.isUndef())
285 unsigned Reg = MO.getReg();
288 if (MO.isDead() && Insert->definesRegister(Reg) &&
312 (MO.isDef() || Def->definesRegister(Reg)) ?
389 const MachineOperand &MO local
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