Searched defs:dst1 (Results 51 - 74 of 74) sorted by relevance

123

/external/v8/src/compiler/ia32/
H A Dcode-generator-ia32.cc2494 Operand dst1 = g.HighOperand(destination); local
2496 __ Move(dst1, Immediate(upper));
2576 Operand dst1 = g.ToOperand(destination); local
2577 __ push(dst1);
2619 Operand dst1 = g.HighOperand(destination); local
2624 __ pop(dst1);
/external/v8/src/compiler/x87/
H A Dcode-generator-x87.cc2620 Operand dst1 = g.HighOperand(destination); local
2622 __ Move(dst1, Immediate(upper));
2692 Operand dst1 = g.ToOperand(destination); local
2693 __ push(dst1);
/external/vixl/test/aarch32/
H A Dtest-assembler-aarch32.cc5357 uint32_t dst1[4] = {0x00000000, 0x00000000, 0x00000000, 0x00000000}; local
5364 __ Mov(r0, reinterpret_cast<uintptr_t>(dst1));
5384 ASSERT_EQUAL_32(0x12345678, dst1[0]);
5385 ASSERT_EQUAL_32(0x09abcdef, dst1[1]);
5386 ASSERT_EQUAL_32(0xc001c0de, dst1[2]);
5387 ASSERT_EQUAL_32(0xdeadbeef, dst1[3]);
5450 uint32_t dst1[4] = {0x00000000, 0x00000000, 0x00000000, 0x00000000}; local
5461 __ Mov(r9, reinterpret_cast<uintptr_t>(dst1 + 3));
5476 ASSERT_EQUAL_32(reinterpret_cast<uintptr_t>(dst1 + 1), r9);
5489 ASSERT_EQUAL_32(0x33333333, dst1[
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/external/webp/src/dsp/
H A Denc_msa.c176 v4i32 dst0, dst1; local
197 DOTP_SH2_SW(tmp0, tmp1, tmp2, tmp3, dst0, dst1);
198 dst0 = dst0 + dst1;
H A Dlossless_enc_sse2.c401 const __m128i dst1 = _mm_unpackhi_epi16(in_lo, ff); local
406 _mm_storeu_si128((__m128i*)&dst[4], dst1);
421 const __m128i dst1 = _mm_unpackhi_epi16(pack, ff); local
423 _mm_storeu_si128((__m128i*)&dst[4], dst1);
H A Ddec_sse2.c152 __m128i dst0, dst1, dst2, dst3; local
156 dst1 = _mm_loadl_epi64((__m128i*)(dst + 1 * BPS));
162 dst1 = _mm_cvtsi32_si128(WebPMemToUint32(dst + 1 * BPS));
168 dst1 = _mm_unpacklo_epi8(dst1, zero);
173 dst1 = _mm_add_epi16(dst1, T1);
178 dst1 = _mm_packus_epi16(dst1, dst1);
217 __m128i dst1 = _mm_cvtsi32_si128(WebPMemToUint32(dst + 1 * BPS)); local
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/external/libyuv/files/source/
H A Drow_msa.cc291 v16u8 dst0, dst1, dst2, dst3; local
298 VSHF_B2_UB(src1, src1, src0, src0, shuffler, shuffler, dst1, dst0);
299 ST_UB4(dst0, dst1, dst2, dst3, dst, 16);
308 v16u8 dst0, dst1, dst2, dst3; local
315 VSHF_B2_UB(src1, src1, src0, src0, shuffler, shuffler, dst1, dst0);
316 ST_UB4(dst0, dst1, dst2, dst3, dst, 16);
477 v16u8 src0, src1, src2, src3, src4, dst0, dst1, dst2; local
511 dst1 = (v16u8)__msa_vshf_b(shuffler1, (v16i8)reg3, (v16i8)reg1);
513 ST_UB2(dst0, dst1, rgb_buf, 16);
643 v16u8 src0, src1, src2, src3, dst0, dst1; local
663 v16u8 vec0, vec1, dst0, dst1; local
690 v16u8 src0, src1, src2, src3, dst0, dst1; local
708 v16u8 src0, src1, src2, src3, dst0, dst1; local
728 v16u8 vec0, vec1, dst0, dst1; local
755 v16u8 src0, src1, src2, src3, dst0, dst1; local
827 v16u8 dst0, dst1; local
937 v16u8 src0, src1, src2, src3, dst0, dst1, dst2; local
961 v16u8 src0, src1, src2, src3, dst0, dst1, dst2; local
1085 v16u8 src0, src1, src2, src3, reg0, reg1, reg2, reg3, dst0, dst1; local
1196 v16u8 src0, src1, src2, src3, dst0, dst1; local
1217 v16u8 src0, src1, src2, src3, dst0, dst1; local
1235 v16u8 src0, src1, dst0, dst1; local
1347 v16u8 src0, src1, dst0, dst1; local
1407 v16u8 src0, src1, vec0, vec1, dst0, dst1; local
1432 v16u8 src0, src1, dst0, dst1, vec0, vec1, vec2, vec3, vec4, vec5; local
1477 v16u8 dst0, dst1, dst2, dst3; local
1507 v16u8 dst0, dst1, dst2, dst3; local
1554 v16u8 res0, res1, res2, res3, dst0, dst1, dst2, dst3; local
1599 v16u8 dst0, dst1, dst2, dst3; local
1624 v16u8 dst0, dst1, dst2, dst3; local
2225 v16u8 src0, src1, res0, res1, dst0, dst1; local
2298 v16u8 src0, src1, res0, res1, dst0, dst1; local
2335 v16u8 src0, src1, vec0, dst0, dst1, dst2, dst3; local
2363 v16u8 src0, src1, src2, src3, dst0, dst1; local
2385 v16u8 reg0, reg1, dst0, dst1, dst2, dst3; local
2497 v16u8 dst0, dst1; local
2565 v16u8 dst0, dst1, vec0, vec1, vec2, vec3; local
2599 v16u8 dst0, dst1; local
2632 v16u8 dst0, dst1, vec0, vec1, vec2, vec3; local
2664 v16u8 src0, src1, src2, dst0, dst1; local
2727 v16u8 src0, res0, res1, res2, res3, res4, dst0, dst1, dst2, dst3; local
2779 v16u8 src0, vec0, vec1, vec2, vec3, dst0, dst1, dst2, dst3; local
2865 v16u8 src0, src1, src2, src3, dst0, dst1; local
2930 v16u8 src0, src1, src2, src3, src4, dst0, dst1, dst2; local
2958 v16u8 src0, src1, dst0, dst1; local
[all...]
/external/vixl/src/aarch64/
H A Dmacro-assembler-aarch64.cc1967 const CPURegister& dst1,
1973 VIXL_ASSERT(!AreAliased(dst0, dst1, dst2, dst3));
1974 VIXL_ASSERT(AreSameSizeAndType(dst0, dst1, dst2, dst3));
1977 int count = 1 + dst1.IsValid() + dst2.IsValid() + dst3.IsValid();
1981 PopHelper(count, size, dst0, dst1, dst2, dst3);
2033 const CPURegister& dst1 = registers.PopLowestIndex(); local
2034 if (dst1.IsValid()) {
2035 Ldp(dst0, dst1, MemOperand(StackPointer(), offset));
2122 const CPURegister& dst1,
2131 VIXL_ASSERT(AreSameSizeAndType(dst0, dst1, dst
1966 Pop(const CPURegister& dst0, const CPURegister& dst1, const CPURegister& dst2, const CPURegister& dst3) argument
2119 PopHelper(int count, int size, const CPURegister& dst0, const CPURegister& dst1, const CPURegister& dst2, const CPURegister& dst3) argument
2342 const CPURegister& dst1 = registers.PopLowestIndex(); local
[all...]
H A Dlogic-aarch64.cc428 LogicVRegister dst1,
431 dst1.ClearForWrite(vform);
436 dst1.ReadUintFromMem(vform, i, addr1);
445 LogicVRegister dst1,
449 dst1.ClearForWrite(vform);
452 dst1.ReadUintFromMem(vform, index, addr1);
458 LogicVRegister dst1,
461 dst1.ClearForWrite(vform);
465 dst1.ReadUintFromMem(vform, i, addr);
472 LogicVRegister dst1,
427 ld2(VectorFormat vform, LogicVRegister dst1, LogicVRegister dst2, uint64_t addr1) argument
444 ld2(VectorFormat vform, LogicVRegister dst1, LogicVRegister dst2, int index, uint64_t addr1) argument
457 ld2r(VectorFormat vform, LogicVRegister dst1, LogicVRegister dst2, uint64_t addr) argument
471 ld3(VectorFormat vform, LogicVRegister dst1, LogicVRegister dst2, LogicVRegister dst3, uint64_t addr1) argument
493 ld3(VectorFormat vform, LogicVRegister dst1, LogicVRegister dst2, LogicVRegister dst3, int index, uint64_t addr1) argument
510 ld3r(VectorFormat vform, LogicVRegister dst1, LogicVRegister dst2, LogicVRegister dst3, uint64_t addr) argument
528 ld4(VectorFormat vform, LogicVRegister dst1, LogicVRegister dst2, LogicVRegister dst3, LogicVRegister dst4, uint64_t addr1) argument
555 ld4(VectorFormat vform, LogicVRegister dst1, LogicVRegister dst2, LogicVRegister dst3, LogicVRegister dst4, int index, uint64_t addr1) argument
576 ld4r(VectorFormat vform, LogicVRegister dst1, LogicVRegister dst2, LogicVRegister dst3, LogicVRegister dst4, uint64_t addr) argument
[all...]
/external/dng_sdk/source/
H A Ddng_image_writer.cpp2927 uint8 *dst1 = temp + rowIncrement; local
2929 uint8 *dst1 = temp; local
2937 dst1 [col] = src [1];
2951 uint8 *dst1 = temp + rowIncrement; local
2958 dst1 [col] = src [1];
2974 uint8 *dst1 = temp + rowIncrement; local
2980 uint8 *dst1 = temp + rowIncrement * 2; local
2988 dst1 [col] = src [1];
/external/v8/src/arm/
H A Dsimulator-arm.cc4979 uint8_t src1[16], src2[16], dst1[16], dst2[16]; local
4983 dst1[i * 2] = src1[i];
4984 dst1[i * 2 + 1] = src2[i];
4988 set_q_register(Vd, dst1);
4993 uint16_t src1[8], src2[8], dst1[8], dst2[8]; local
4997 dst1[i] = src1[i / 2];
4998 dst1[i + 1] = src2[i / 2];
5002 set_q_register(Vd, dst1);
5007 uint32_t src1[4], src2[4], dst1[4], dst2[4]; local
5011 dst1[
[all...]
H A Dassembler-arm.cc2113 void Assembler::ldrd(Register dst1, Register dst2, argument
2116 DCHECK(!dst1.is(lr)); // r14.
2117 DCHECK_EQ(0, dst1.code() % 2);
2118 DCHECK_EQ(dst1.code() + 1, dst2.code());
2119 addrmod3(cond | B7 | B6 | B4, dst1, src);
2908 void Assembler::vmov(const Register dst1, argument
2917 DCHECK(!dst1.is(pc) && !dst2.is(pc));
2921 dst1.code()*B12 | 0xB*B8 | m*B5 | B4 | vm);
/external/mesa3d/src/mesa/state_tracker/
H A Dst_glsl_to_tgsi.cpp506 st_dst_reg dst, st_dst_reg dst1,
645 st_dst_reg dst, st_dst_reg dst1,
660 num_reladdr += dst1.reladdr != NULL || dst1.reladdr2;
678 if (dst1.reladdr) {
679 emit_arl(ir, address_reg, *dst1.reladdr);
690 inst->dst[1] = dst1;
773 /* select the writemask for dst0 or dst1 */
644 emit_asm(ir_instruction *ir, unsigned op, st_dst_reg dst, st_dst_reg dst1, st_src_reg src0, st_src_reg src1, st_src_reg src2, st_src_reg src3) argument
/external/v8/src/arm64/
H A Dmacro-assembler-arm64.cc895 void MacroAssembler::Pop(const CPURegister& dst0, const CPURegister& dst1, argument
899 DCHECK(!AreAliased(dst0, dst1, dst2, dst3));
900 DCHECK(AreSameSizeAndType(dst0, dst1, dst2, dst3));
903 int count = 1 + dst1.IsValid() + dst2.IsValid() + dst3.IsValid();
906 PopHelper(count, size, dst0, dst1, dst2, dst3);
911 void MacroAssembler::Pop(const CPURegister& dst0, const CPURegister& dst1, argument
917 DCHECK(!AreAliased(dst0, dst1, dst2, dst3, dst4, dst5, dst6, dst7));
918 DCHECK(AreSameSizeAndType(dst0, dst1, dst2, dst3, dst4, dst5, dst6, dst7));
924 PopHelper(4, size, dst0, dst1, dst2, dst3);
1021 const CPURegister& dst1 local
1155 PopHelper(int count, int size, const CPURegister& dst0, const CPURegister& dst1, const CPURegister& dst2, const CPURegister& dst3) argument
1269 PeekPair(const CPURegister& dst1, const CPURegister& dst2, int offset) argument
2705 const CPURegister& dst1 = saved_fp_regs.PopHighestIndex(); local
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/external/v8/src/s390/
H A Dmacro-assembler-s390.cc4699 void MacroAssembler::LoadMultipleP(Register dst1, Register dst2, argument
4703 lmg(dst1, dst2, mem);
4706 lm(dst1, dst2, mem);
4709 lmy(dst1, dst2, mem);
4729 void MacroAssembler::LoadMultipleW(Register dst1, Register dst2, argument
4732 lm(dst1, dst2, mem);
4735 lmy(dst1, dst2, mem);
/external/valgrind/VEX/priv/
H A Dguest_x86_toIR.c1837 IRTemp dst1 = newTemp(ty); local
1863 helper_ADC( size, dst1, dst0, src,
1865 putIReg(size, gregOfRM(rm), mkexpr(dst1));
1868 helper_SBB( size, dst1, dst0, src,
1870 putIReg(size, gregOfRM(rm), mkexpr(dst1));
1872 assign( dst1, binop(mkSizedOp(ty,op8), mkexpr(dst0), mkexpr(src)) );
1876 setFlags_DEP1(op8, dst1, ty);
1878 putIReg(size, gregOfRM(rm), mkexpr(dst1));
1892 helper_ADC( size, dst1, dst0, src,
1894 putIReg(size, gregOfRM(rm), mkexpr(dst1));
1950 IRTemp dst1 = newTemp(ty); local
2153 IRTemp dst1 = newTemp(ty); local
2291 IRTemp dst1 = newTemp(ty); local
2402 IRTemp dst1 = newTemp(ty); local
2813 IRTemp dst1, src, dst0; local
[all...]
H A Dguest_s390_toIR.c7220 IRTemp dst1 = newTemp(Ity_D32); local
7297 assign(dst1, binop(Iop_F32toD32, irrm, mkexpr(src1)));
7298 put_dpr_w0(0, mkexpr(dst1)); /* put the result in FPR 0,2 */
H A Dguest_amd64_toIR.c2989 IRTemp dst1 = newTemp(ty); local
3036 helper_ADC( size, dst1, dst0, src,
3038 putIRegG(size, pfx, rm, mkexpr(dst1));
3041 helper_SBB( size, dst1, dst0, src,
3043 putIRegG(size, pfx, rm, mkexpr(dst1));
3046 helper_ADCX_ADOX( True/*isADCX*/, size, dst1, dst0, src );
3047 putIRegG(size, pfx, rm, mkexpr(dst1));
3050 helper_ADCX_ADOX( False/*!isADCX*/, size, dst1, dst0, src );
3051 putIRegG(size, pfx, rm, mkexpr(dst1));
3053 assign( dst1, bino
3139 IRTemp dst1 = newTemp(ty); local
3369 IRTemp dst1 = newTemp(ty); local
3520 IRTemp dst1 = newTemp(ty); local
3634 IRTemp dst1 = newTemp(ty); local
4116 IRTemp dst1, src, dst0; local
[all...]
/external/robolectric/v3/runtime/
H A Dandroid-all-4.1.2_r1-robolectric-0.jarMETA-INF/ META-INF/MANIFEST.MF android/ android/accessibilityservice/ android/accessibilityservice/AccessibilityService$1.class ...
H A Dandroid-all-4.2.2_r1.2-robolectric-0.jarMETA-INF/ META-INF/MANIFEST.MF android/ android/accessibilityservice/ android/accessibilityservice/AccessibilityService$1.class ...
H A Dandroid-all-4.3_r2-robolectric-0.jarMETA-INF/ META-INF/MANIFEST.MF android/ android/accessibilityservice/ android/accessibilityservice/AccessibilityService$1.class ...
H A Dandroid-all-4.4_r1-robolectric-1.jarMETA-INF/ META-INF/MANIFEST.MF com/ com/google/ com/google/android/ com/google/android/collect/ ...
H A Dandroid-all-5.0.0_r2-robolectric-1.jarMETA-INF/ META-INF/MANIFEST.MF com/ com/google/ com/google/android/ com/google/android/collect/ ...
H A Dandroid-all-5.1.1_r9-robolectric-1.jarMETA-INF/ META-INF/MANIFEST.MF com/ com/google/ com/google/android/ com/google/android/collect/ ...

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