Searched defs:ib (Results 151 - 175 of 230) sorted by relevance

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/external/mesa3d/src/mesa/tnl/
H A Dt_draw.c341 const struct _mesa_index_buffer *ib,
350 if (!ib) {
355 if (_mesa_is_bufferobj(ib->obj) &&
356 !_mesa_bufferobj_mapped(ib->obj, MAP_INTERNAL)) {
358 bo[*nr_bo] = ib->obj;
360 ptr = ctx->Driver.MapBufferRange(ctx, (GLsizeiptr) ib->ptr,
361 ib->count * vbo_sizeof_ib_type(ib->type),
362 GL_MAP_READ_BIT, ib->obj,
364 assert(ib
340 bind_indices( struct gl_context *ctx, const struct _mesa_index_buffer *ib, struct gl_buffer_object **bo, GLuint *nr_bo) argument
421 _tnl_draw_prims(struct gl_context *ctx, const struct _mesa_prim *prim, GLuint nr_prims, const struct _mesa_index_buffer *ib, GLboolean index_bounds_valid, GLuint min_index, GLuint max_index, struct gl_transform_feedback_object *tfb_vertcount, unsigned stream, struct gl_buffer_object *indirect) argument
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/external/mesa3d/src/mesa/vbo/
H A Dvbo_minmax_index.c238 const struct _mesa_index_buffer *ib,
243 const GLuint restartIndex = _mesa_primitive_restart_index(ctx, ib->type);
244 const int index_size = vbo_sizeof_ib_type(ib->type);
248 indices = (char *) ib->ptr + prim->start * index_size;
249 if (_mesa_is_bufferobj(ib->obj)) {
250 GLsizeiptr size = MIN2(count * index_size, ib->obj->Size);
252 if (vbo_get_minmax_cached(ib->obj, ib->type, (GLintptr) indices, count,
257 GL_MAP_READ_BIT, ib->obj,
261 switch (ib
236 vbo_get_minmax_index(struct gl_context *ctx, const struct _mesa_prim *prim, const struct _mesa_index_buffer *ib, GLuint *min_index, GLuint *max_index, const GLuint count) argument
349 vbo_get_minmax_indices(struct gl_context *ctx, const struct _mesa_prim *prims, const struct _mesa_index_buffer *ib, GLuint *min_index, GLuint *max_index, GLuint nr_prims) argument
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H A Dvbo_primitive_restart.c166 const struct _mesa_index_buffer *ib,
178 GLuint restart_index = _mesa_primitive_restart_index(ctx, ib->type);
182 GLboolean map_ib = ib->obj->Name && !ib->obj->Mappings[MAP_INTERNAL].Pointer;
210 new_ib = *ib;
214 ib = &new_ib;
223 ctx->Driver.MapBufferRange(ctx, 0, ib->obj->Size, GL_MAP_READ_BIT,
224 ib->obj, MAP_INTERNAL);
227 ptr = ADD_POINTERS(ib->obj->Mappings[MAP_INTERNAL].Pointer, ib
163 vbo_sw_primitive_restart(struct gl_context *ctx, const struct _mesa_prim *prims, GLuint nr_prims, const struct _mesa_index_buffer *ib, struct gl_buffer_object *indirect) argument
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H A Dvbo_split_copy.c58 const struct _mesa_index_buffer *ib; member in struct:copy_context
146 const struct _mesa_index_buffer *ib,
156 printf(" IB: %p\n", (void*) ib);
473 if (_mesa_is_bufferobj(copy->ib->obj) &&
474 !_mesa_bufferobj_mapped(copy->ib->obj, MAP_INTERNAL))
475 ctx->Driver.MapBufferRange(ctx, 0, copy->ib->obj->Size, GL_MAP_READ_BIT,
476 copy->ib->obj, MAP_INTERNAL);
479 ADD_POINTERS(copy->ib->obj->Mappings[MAP_INTERNAL].Pointer,
480 copy->ib->ptr);
482 switch (copy->ib
142 dump_draw_info(struct gl_context *ctx, const struct gl_vertex_array **arrays, const struct _mesa_prim *prims, GLuint nr_prims, const struct _mesa_index_buffer *ib, GLuint min_index, GLuint max_index) argument
595 vbo_split_copy( struct gl_context *ctx, const struct gl_vertex_array *arrays[], const struct _mesa_prim *prim, GLuint nr_prims, const struct _mesa_index_buffer *ib, vbo_draw_func draw, const struct split_limits *limits ) argument
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/external/swiftshader/third_party/LLVM/lib/CodeGen/
H A DSpillPlacement.cpp229 unsigned ib = bundles->getBundle(I->Number, 0); local
230 activate(ib);
231 nodes[ib].addBias(Freq * Bias[I->Entry], 1);
250 unsigned ib = bundles->getBundle(*I, 0); local
252 activate(ib);
254 nodes[ib].addBias(-Freq, 1);
263 unsigned ib = bundles->getBundle(Number, 0); local
267 if (ib == ob)
269 activate(ib);
271 if (nodes[ib]
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/MCTargetDesc/
H A DARMAddressingModes.h68 ib, enumerator in enum:llvm::ARM_AM::AMSubMode
77 case ARM_AM::ib: return "ib";
/external/syslinux/gpxe/src/net/infiniband/
H A Dib_srp.c67 struct ib_srp_parameters *ib; member in struct:ib_srp_root_path
151 memcpy ( &rp->ib->sgid, &ibdev->gid, sizeof ( rp->ib->sgid ) );
153 return ib_srp_parse_byte_string ( rp_comp, rp->ib->sgid.u.bytes,
154 ( sizeof ( rp->ib->sgid ) |
188 memcpy ( &port_id->hca_guid, &rp->ib->sgid.u.half[1],
205 return ib_srp_parse_byte_string ( rp_comp, rp->ib->dgid.u.bytes,
206 ( sizeof ( rp->ib->dgid ) |
223 rp->ib->pkey = pkey;
236 return ib_srp_parse_byte_string ( rp_comp, rp->ib
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/external/drm_gralloc/
H A Dgralloc_drm_intel.c205 struct intel_buffer *ib = (struct intel_buffer *) bo; local
211 pitches[0] = ib->base.handle->stride;
212 handles[0] = ib->base.fb_handle;
214 switch(ib->base.handle->format) {
223 pitches[0] * ib->base.handle->height;
225 pitches[2] * ib->base.handle->height/2;
235 pitches[0] * ib->base.handle->height;
343 struct intel_buffer *ib; local
345 ib = calloc(1, sizeof(*ib));
401 struct intel_buffer *ib = (struct intel_buffer *) bo; local
412 struct intel_buffer *ib = (struct intel_buffer *) bo; local
429 struct intel_buffer *ib = (struct intel_buffer *) bo; local
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/external/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMAddressingModes.h69 ib, enumerator in enum:llvm::ARM_AM::AMSubMode
78 case ARM_AM::ib: return "ib";
/external/mesa3d/src/gallium/drivers/etnaviv/
H A Detnaviv_state.c443 etna_set_index_buffer(struct pipe_context *pctx, const struct pipe_index_buffer *ib) argument
448 if (ib) {
449 pipe_resource_reference(&ctx->index_buffer.ib.buffer, ib->buffer);
450 memcpy(&ctx->index_buffer.ib, ib, sizeof(ctx->index_buffer.ib));
451 ctrl = translate_index_size(ctx->index_buffer.ib.index_size);
453 pipe_resource_reference(&ctx->index_buffer.ib.buffer, NULL);
457 if (ctx->index_buffer.ib
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H A Detnaviv_context.h47 struct pipe_index_buffer ib; member in struct:etna_index_buffer
/external/mesa3d/src/gallium/drivers/freedreno/
H A Dfreedreno_state.c231 const struct pipe_index_buffer *ib)
235 if (ib) {
236 pipe_resource_reference(&ctx->indexbuf.buffer, ib->buffer);
237 ctx->indexbuf.index_size = ib->index_size;
238 ctx->indexbuf.offset = ib->offset;
239 ctx->indexbuf.user_buffer = ib->user_buffer;
230 fd_set_index_buffer(struct pipe_context *pctx, const struct pipe_index_buffer *ib) argument
/external/mesa3d/src/gallium/drivers/ilo/core/
H A Dilo_builder_3d_top.h415 const struct ilo_state_index_buffer *ib)
430 dw0 |= ib->ib[0];
437 if (ib->vma) {
438 ilo_builder_batch_reloc(builder, pos + 1, ib->vma->bo,
439 ib->vma->bo_offset + ib->ib[1], 0);
440 ilo_builder_batch_reloc(builder, pos + 2, ib->vma->bo,
441 ib
413 gen6_3DSTATE_INDEX_BUFFER(struct ilo_builder *builder, const struct ilo_state_vf *vf, const struct ilo_state_index_buffer *ib) argument
449 gen8_3DSTATE_INDEX_BUFFER(struct ilo_builder *builder, const struct ilo_state_vf *vf, const struct ilo_state_index_buffer *ib) argument
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H A Dilo_state_vf.c616 index_buffer_set_gen8_3DSTATE_INDEX_BUFFER(struct ilo_state_index_buffer *ib, argument
627 STATIC_ASSERT(ARRAY_SIZE(ib->ib) >= 3);
629 ib->ib[0] = info->format << GEN8_IB_DW1_FORMAT__SHIFT;
630 ib->ib[1] = info->offset;
631 ib->ib[2] = size;
633 ib
989 ilo_state_index_buffer_set_info(struct ilo_state_index_buffer *ib, const struct ilo_dev *dev, const struct ilo_state_index_buffer_info *info) argument
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/external/mesa3d/src/gallium/drivers/svga/
H A Dsvga_draw.c461 unsigned max_index, struct pipe_resource *ib,
534 if (ib) {
535 struct svga_buffer *sbuf = svga_buffer(ib);
540 ib_handle = svga_buffer_handle(svga, ib);
636 if (ib != svga->state.hw_draw.ib ||
647 pipe_resource_reference(&svga->state.hw_draw.ib, ib);
686 svga->state.hw_draw.ib != NULL) {
692 pipe_resource_reference(&svga->state.hw_draw.ib, NUL
457 draw_vgpu10(struct svga_hwtnl *hwtnl, const SVGA3dPrimitiveRange *range, unsigned vcount, unsigned min_index, unsigned max_index, struct pipe_resource *ib, unsigned start_instance, unsigned instance_count) argument
764 check_draw_params(struct svga_hwtnl *hwtnl, const SVGA3dPrimitiveRange *range, unsigned min_index, unsigned max_index, struct pipe_resource *ib) argument
909 svga_hwtnl_prim(struct svga_hwtnl *hwtnl, const SVGA3dPrimitiveRange * range, unsigned vcount, unsigned min_index, unsigned max_index, struct pipe_resource *ib, unsigned start_instance, unsigned instance_count) argument
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/external/mesa3d/src/gallium/winsys/amdgpu/drm/
H A Damdgpu_cs.h80 struct amdgpu_cs_ib_info ib[IB_NUM]; member in struct:amdgpu_cs_context
182 amdgpu_cs_from_ib(struct amdgpu_ib *ib) argument
184 switch (ib->ib_type) {
186 return get_container(ib, struct amdgpu_cs, main);
188 return get_container(ib, struct amdgpu_cs, const_ib);
190 return get_container(ib, struct amdgpu_cs, const_preamble_ib);
H A Damdgpu_cs.c462 static bool amdgpu_ib_new_buffer(struct amdgpu_winsys *ws, struct amdgpu_ib *ib) argument
474 if (amdgpu_cs_has_chaining(amdgpu_cs_from_ib(ib)))
475 buffer_size = 4 *util_next_power_of_two(ib->max_ib_size);
477 buffer_size = 4 *util_next_power_of_two(4 * ib->max_ib_size);
481 switch (ib->ib_type) {
508 pb_reference(&ib->big_ib_buffer, pb);
511 ib->ib_mapped = mapped;
512 ib->used_ib_space = 0;
546 struct amdgpu_ib *ib = NULL; local
547 struct amdgpu_cs_ib_info *info = &cs->csc->ib[ib_typ
602 amdgpu_ib_finalize(struct amdgpu_ib *ib) argument
789 struct amdgpu_ib *ib = amdgpu_ib(rcs); local
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/external/mesa3d/src/mesa/drivers/dri/nouveau/
H A Dnouveau_vbo_t.c55 vbo_init_arrays(struct gl_context *ctx, const struct _mesa_index_buffer *ib, argument
62 if (ib)
63 nouveau_init_array(&render->ib, 0, 0, ib->count, ib->type,
64 ib->obj, ib->ptr, GL_TRUE, ctx);
78 vbo_deinit_arrays(struct gl_context *ctx, const struct _mesa_index_buffer *ib, argument
84 if (ib)
85 nouveau_cleanup_array(&render->ib);
230 vbo_maybe_split(struct gl_context *ctx, const struct gl_vertex_array **arrays, const struct _mesa_prim *prims, GLuint nr_prims, const struct _mesa_index_buffer *ib, GLuint min_index, GLuint max_index) argument
358 vbo_draw_vbo(struct gl_context *ctx, const struct gl_vertex_array **arrays, const struct _mesa_prim *prims, GLuint nr_prims, const struct _mesa_index_buffer *ib, GLuint min_index, GLuint max_index) argument
408 vbo_draw_imm(struct gl_context *ctx, const struct gl_vertex_array **arrays, const struct _mesa_prim *prims, GLuint nr_prims, const struct _mesa_index_buffer *ib, GLuint min_index, GLuint max_index) argument
453 vbo_render_prims(struct gl_context *ctx, const struct _mesa_prim *prims, GLuint nr_prims, const struct _mesa_index_buffer *ib, GLboolean index_bounds_valid, GLuint min_index, GLuint max_index, struct gl_transform_feedback_object *tfb_vertcount, unsigned stream, struct gl_buffer_object *indirect) argument
491 vbo_check_render_prims(struct gl_context *ctx, const struct _mesa_prim *prims, GLuint nr_prims, const struct _mesa_index_buffer *ib, GLboolean index_bounds_valid, GLuint min_index, GLuint max_index, struct gl_transform_feedback_object *tfb_vertcount, unsigned stream, struct gl_buffer_object *indirect) argument
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/external/e2fsprogs/e2fsck/
H A Dpass1b.c109 intptr_t ia, ib; local
112 ib = (intptr_t)b;
114 return (ia-ib);
/external/libvpx/libvpx/vp8/encoder/
H A Dencodemb.c143 static void optimize_b(MACROBLOCK *mb, int ib, int type, ENTROPY_CONTEXT *a, argument
176 b = &mb->block[ib];
177 d = &mb->e_mbd.block[ib];
/external/libvpx/libvpx/vp9/common/
H A Dvp9_blockd.h220 const MACROBLOCKD *xd, int ib) {
226 return intra_mode_to_tx_type_lookup[get_y_mode(mi, ib)];
219 get_tx_type_4x4(PLANE_TYPE plane_type, const MACROBLOCKD *xd, int ib) argument
/external/mesa3d/src/amd/vulkan/winsys/amdgpu/
H A Dradv_amdgpu_cs.c41 struct amdgpu_cs_ib_info ib; member in struct:radv_amdgpu_cs
188 cs->ib.ib_mc_address = radv_amdgpu_winsys_bo(cs->ib_buffer)->va;
191 cs->ib_size_ptr = &cs->ib.size;
192 cs->ib.size = 0;
221 /* The total ib size cannot exceed limit_dws dwords. */
327 cs->ib.ib_mc_address = radv_amdgpu_winsys_bo(cs->ib_buffer)->va;
328 cs->ib_size_ptr = &cs->ib.size;
329 cs->ib.size = 0;
409 parent->base.buf[parent->base.cdw++] = child->ib.ib_mc_address;
410 parent->base.buf[parent->base.cdw++] = child->ib
667 struct amdgpu_cs_ib_info ib = {0}; local
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/external/mesa3d/src/gallium/drivers/radeonsi/
H A Dsi_state_draw.c535 const struct pipe_index_buffer *ib)
568 if (ib->index_size != sctx->last_index_size) {
572 switch (ib->index_size) {
591 sctx->last_index_size = ib->index_size;
594 index_max_size = (ib->buffer->width0 - ib->offset) /
595 ib->index_size;
596 index_va = r600_resource(ib->buffer)->gpu_address + ib->offset;
599 (struct r600_resource *)ib
533 si_emit_draw_packets(struct si_context *sctx, const struct pipe_draw_info *info, const struct pipe_index_buffer *ib) argument
1004 struct pipe_index_buffer ib = {}; local
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/external/mesa3d/src/gallium/drivers/vc4/kernel/
H A Dvc4_validate.c248 struct drm_gem_cma_object *ib; local
265 ib = vc4_use_handle(exec, 0);
266 if (!ib)
269 if (offset > ib->base.size ||
270 (ib->base.size - offset) / index_size < length) {
272 offset, length, index_size, ib->base.size);
276 *(uint32_t *)(validated + 5) = ib->paddr + offset;
/external/mesa3d/src/gallium/drivers/vc4/
H A Dvc4_state.c306 const struct pipe_index_buffer *ib)
310 if (ib) {
311 pipe_resource_reference(&vc4->indexbuf.buffer, ib->buffer);
312 vc4->indexbuf.index_size = ib->index_size;
313 vc4->indexbuf.offset = ib->offset;
314 vc4->indexbuf.user_buffer = ib->user_buffer;
305 vc4_set_index_buffer(struct pipe_context *pctx, const struct pipe_index_buffer *ib) argument

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