| /external/clang/test/CodeGen/ |
| H A D | BasicInstrs.c | 6 unsigned int udiv(unsigned int X, unsigned int Y) { function
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| /external/llvm/test/MC/ARM/ |
| H A D | thumbv8m.s | 55 // CHECK: udiv r1, r2, r3 @ encoding: [0xb2,0xfb,0xf3,0xf1]
56 udiv r1, r2, r3 label
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| /external/swiftshader/third_party/LLVM/lib/Support/ |
| H A D | ConstantRange.cpp | 593 ConstantRange::udiv(const ConstantRange &RHS) const { function in class:ConstantRange
599 APInt Lower = getUnsignedMin().udiv(RHS.getUnsignedMax());
611 APInt Upper = getUnsignedMax().udiv(RHS_umin) + 1;
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| /external/llvm/lib/IR/ |
| H A D | ConstantRange.cpp | 796 ConstantRange::udiv(const ConstantRange &RHS) const { function in class:ConstantRange
802 APInt Lower = getUnsignedMin().udiv(RHS.getUnsignedMax());
814 APInt Upper = getUnsignedMax().udiv(RHS_umin) + 1;
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| /external/vixl/src/aarch64/ |
| H A D | assembler-aarch64.cc | 906 void Assembler::udiv(const Register& rd, function in class:vixl::aarch64::Assembler
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| /external/swiftshader/src/Shader/ |
| H A D | ShaderCore.cpp | 754 void ShaderCore::udiv(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) function in class:sw::ShaderCore
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| /external/v8/src/arm64/ |
| H A D | assembler-arm64.cc | 1531 void Assembler::udiv(const Register& rd, function in class:v8::internal::Assembler
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| /external/v8/src/arm/ |
| H A D | assembler-arm.cc | 1688 void Assembler::udiv(Register dst, Register src1, Register src2, function in class:v8::internal::Assembler
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| /external/vixl/src/aarch32/ |
| H A D | assembler-aarch32.cc | 13024 void Assembler::udiv(Condition cond, Register rd, Register rn, Register rm) { function in class:vixl::aarch32::Assembler
13044 Delegate(kUdiv, &Assembler::udiv, cond, rd, rn, rm);
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| H A D | assembler-aarch32.h | 3600 void udiv(Condition cond, Register rd, Register rn, Register rm);
3601 void udiv(Register rd, Register rn, Register rm) { udiv(al, rd, rn, rm); } function in class:vixl::aarch32::Assembler
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| H A D | disasm-aarch32.cc | 3363 void Disassembler::udiv(Condition cond, Register rd, Register rn, Register rm) { function in class:vixl::aarch32::Disassembler
22583 udiv(CurrentCond(),
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