/external/swiftshader/third_party/LLVM/lib/CodeGen/ |
H A D | MachineSSAUpdater.cpp | 324 MachineBasicBlock *Pred) { 326 PHI->addOperand(MachineOperand::CreateMBB(Pred)); 323 AddPHIOperand(MachineInstr *PHI, unsigned Val, MachineBasicBlock *Pred) argument
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/external/llvm/lib/CodeGen/GlobalISel/ |
H A D | RegBankSelect.cpp | 606 MachineBasicBlock &Pred = *MI.getOperand(OpIdx + 1).getMBB(); local 610 MachineBasicBlock::iterator It = Pred.getLastNonDebugInstr(); 611 for (auto Begin = Pred.begin(); It != Begin && It->isTerminator(); --It) 615 addInsertPoint(Pred, *MI.getParent()); 618 // At this point, we can insert in Pred. 620 // - If It is invalid, Pred is empty and we can insert in Pred 623 if (It == Pred.end()) 624 addInsertPoint(Pred, /*Beginning*/ false);
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | ScheduleDAGFast.cpp | 309 const SDep &Pred = LoadPreds[i]; local 310 RemovePred(SU, Pred); 312 AddPred(LoadSU, Pred); 316 const SDep &Pred = NodePreds[i]; local 317 RemovePred(SU, Pred); 318 AddPred(NewSU, Pred);
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/external/llvm/lib/Target/ARM/ |
H A D | Thumb2InstrInfo.cpp | 225 ARMCC::CondCodes Pred, unsigned PredReg, 231 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); 248 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); 255 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); 264 .addImm((unsigned)Pred).addReg(PredReg).addReg(0) 275 .addImm((unsigned)Pred).addReg(PredReg).addReg(0) 221 emitT2RegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags) argument
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H A D | ARMBaseRegisterInfo.cpp | 414 ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const { 425 .addImm(0).addImm(Pred).addReg(PredReg) 762 ARMCC::CondCodes Pred = (PIdx == -1) local 772 Offset, Pred, PredReg, TII); 776 Offset, Pred, PredReg, TII); 411 emitLoadConstPool( MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const argument
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H A D | ARMBaseInstrInfo.cpp | 156 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI.getOperand(NumOps - 1).getImm(); local 171 .addImm(Pred) 183 .addImm(Pred) 191 .addImm(Pred) 205 .addImm(Pred) 213 .addImm(Pred) 227 .addImm(Pred); 234 .addImm(Pred); 243 .addImm(Pred); 250 .addImm(Pred); 1710 MachineBasicBlock *Pred = *MBB.pred_begin(); local 1997 emitARMRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags) argument [all...] |
/external/llvm/lib/Target/Mips/ |
H A D | MipsAsmPrinter.cpp | 398 const MachineBasicBlock *Pred = *MBB->pred_begin(); local 402 if (const BasicBlock *bb = Pred->getBasicBlock()) 419 if (!Pred->isLayoutSuccessor(MBB)) 423 if (Pred->empty()) 428 MachineBasicBlock::const_iterator I = Pred->end(); 429 while (I != Pred->begin() && !(--I)->isTerminator()) ;
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H A D | MipsDelaySlotFiller.cpp | 265 /// Examine Pred and see if it is possible to insert an instruction into 267 bool examinePred(MachineBasicBlock &Pred, const MachineBasicBlock &Succ, 845 bool Filler::examinePred(MachineBasicBlock &Pred, const MachineBasicBlock &Succ, argument 849 getBranch(Pred, Succ); 859 RegDU.addLiveOut(Pred, Succ); 862 BrMap[&Pred] = P.second;
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/external/llvm/lib/Transforms/Scalar/ |
H A D | EarlyCSE.cpp | 107 CmpInst::Predicate Pred = CI->getPredicate(); local 110 Pred = CI->getSwappedPredicate(); 112 return hash_combine(Inst->getOpcode(), Pred, LHS, RHS); 512 if (BasicBlock *Pred = BB->getSinglePredecessor()) 513 if (auto *BI = dyn_cast<BranchInst>(Pred->getTerminator())) 528 BasicBlockEdge(Pred, BB))) {
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H A D | DeadStoreElimination.cpp | 573 BasicBlock *Pred = *I; local 574 if (Pred == BB) continue; 575 TerminatorInst *PredTI = Pred->getTerminator(); 579 if (DT->isReachableFromEntry(Pred)) 580 Blocks.push_back(Pred);
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H A D | GuardWidening.cpp | 434 CmpInst::Predicate Pred; 436 SubsetIntersect.getEquivalentICmp(Pred, NewRHSAP)) { 439 Result = new ICmpInst(InsertPt, Pred, LHS, NewRHS, "wide.chk");
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/external/swiftshader/third_party/llvm-subzero/include/llvm/ADT/ |
H A D | STLExtras.h | 294 PredicateT Pred; member in struct:llvm::filter_iterator::PayloadType 301 while (this->I != Payload->End && !Payload->Pred(*this->I)) 307 filter_iterator(WrappedIteratorT Begin, WrappedIteratorT End, PredicateT Pred) argument 309 Payload(PayloadType{std::move(End), std::move(Pred)}) { 340 make_filter_range(RangeT &&Range, PredicateT Pred) { argument 345 std::move(Pred)),
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/external/llvm/lib/Transforms/Utils/ |
H A D | SimplifyCFG.cpp | 149 BasicBlock *Pred, 740 TerminatorInst *TI, BasicBlock *Pred, IRBuilder<> &Builder) { 741 Value *PredVal = isValueEqualityComparison(Pred->getTerminator()); 753 // Find out information about when control will move from Pred to TI's block. 756 GetValueEqualityComparisonCases(Pred->getTerminator(), PredCases); 764 // If TI's block is the default block from Pred's comparison, potentially 784 DEBUG(dbgs() << "Threading pred instr: " << *Pred->getTerminator() 798 DEBUG(dbgs() << "Threading pred instr: " << *Pred->getTerminator() 868 DEBUG(dbgs() << "Threading pred instr: " << *Pred->getTerminator() 951 BasicBlock *Pred local 739 SimplifyEqualityComparisonWithOnlyPredecessor( TerminatorInst *TI, BasicBlock *Pred, IRBuilder<> &Builder) argument 3158 BasicBlock *Pred = BB->getSinglePredecessor(); local 3431 BasicBlock *Pred = *PI++; local 3466 BasicBlock *Pred = *PI++; local 3683 BasicBlock *Pred = UncondBranchPreds.pop_back_val(); local 3685 << "INTO UNCOND BRANCH PRED: " << *Pred); local 4215 BasicBlock *Pred = SI->getParent(); local 4788 BasicBlock *Pred = *PI; local [all...] |
H A D | SSAUpdater.cpp | 274 static void AddPHIOperand(PHINode *PHI, Value *Val, BasicBlock *Pred) { argument 275 PHI->addIncoming(Val, Pred);
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/external/swiftshader/third_party/LLVM/lib/Analysis/ |
H A D | MemoryDependenceAnalysis.cpp | 1066 BasicBlock *Pred = *PI; local 1067 PredList.push_back(std::make_pair(Pred, Pointer)); 1072 PredPointer.PHITranslateValue(BB, Pred, 0); 1082 InsertRes = Visited.insert(std::make_pair(Pred, PredPtrVal)); 1112 BasicBlock *Pred = PredList[i].first; local 1135 isLoad, Pred, 1138 NonLocalDepResult Entry(Pred, MemDepResult::getUnknown(), PredPtrVal);
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/external/swiftshader/third_party/LLVM/lib/Transforms/Scalar/ |
H A D | JumpThreading.cpp | 1069 BasicBlock *Pred = PredValues[i].second; local 1070 if (!SeenPreds.insert(Pred)) 1075 if (isa<IndirectBrInst>(Pred->getTerminator())) 1099 PredToDestList.push_back(std::make_pair(Pred, DestBB)); 1120 BasicBlock *Pred = PredToDestList[i].first; local 1125 TerminatorInst *PredTI = Pred->getTerminator(); 1128 PredsToFactor.push_back(Pred);
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/external/swiftshader/third_party/LLVM/lib/Transforms/Utils/ |
H A D | SimplifyCFG.cpp | 61 BasicBlock *Pred, 550 BasicBlock *Pred, 552 Value *PredVal = isValueEqualityComparison(Pred->getTerminator()); 559 // Find out information about when control will move from Pred to TI's block. 561 BasicBlock *PredDef = GetValueEqualityComparisonCases(Pred->getTerminator(), 570 // If TI's block is the default block from Pred's comparison, potentially 590 DEBUG(dbgs() << "Threading pred instr: " << *Pred->getTerminator() 603 DEBUG(dbgs() << "Threading pred instr: " << *Pred->getTerminator() 652 DEBUG(dbgs() << "Threading pred instr: " << *Pred->getTerminator() 693 BasicBlock *Pred local 549 SimplifyEqualityComparisonWithOnlyPredecessor(TerminatorInst *TI, BasicBlock *Pred, IRBuilder<> &Builder) argument 1956 BasicBlock *Pred = BB->getSinglePredecessor(); local 2209 BasicBlock *Pred = UncondBranchPreds.pop_back_val(); local 2211 << "INTO UNCOND BRANCH PRED: " << *Pred); local 2248 BasicBlock *Pred = Preds.back(); local [all...] |
H A D | SSAUpdater.cpp | 308 static void AddPHIOperand(PHINode *PHI, Value *Val, BasicBlock *Pred) { argument 309 PHI->addIncoming(Val, Pred);
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
H A D | ARMISelDAGToDAG.cpp | 1602 SDValue Pred = getAL(CurDAG); local 1617 Ops.push_back(Pred); 1631 const SDValue OpsA[] = { MemAddr, Align, Reg0, ImplDef, Pred, Reg0, Chain }; 1647 Ops.push_back(Pred); 1720 SDValue Pred = getAL(CurDAG); local 1760 Ops.push_back(Pred); 1786 const SDValue OpsA[] = { MemAddr, Align, Reg0, RegSeq, Pred, Reg0, Chain }; 1804 Ops.push_back(Pred); 1876 SDValue Pred = getAL(CurDAG); local 1907 Ops.push_back(Pred); 1972 SDValue Pred = getAL(CurDAG); local 2426 SDValue Pred = getAL(CurDAG); local 2658 SDValue Pred = getAL(CurDAG); local 2677 SDValue Pred = getAL(CurDAG); local 2696 SDValue Pred = getAL(CurDAG); local [all...] |
H A D | ARMBaseInstrInfo.cpp | 158 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm(); local 174 .addImm(Pred).addReg(0).addReg(0); 181 .addImm(Pred).addReg(0).addReg(0); 186 .addImm(Pred).addReg(0).addReg(0); 197 .addImm(Pred).addReg(0).addReg(0); 202 .addImm(Pred).addReg(0).addReg(0); 212 .addReg(WBReg).addImm(0).addImm(Pred); 216 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred); 223 .addReg(BaseReg).addImm(0).addImm(Pred); 227 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred); 1509 emitARMRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags) argument [all...] |
/external/clang/include/clang/StaticAnalyzer/Core/ |
H A D | CheckerManager.h | 292 ExplodedNode *Pred, 298 ExplodedNode *Pred, 303 ExplodedNodeSet &Dst, ExplodedNode *Pred,
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonGenPredicate.cpp | 408 Register Pred = getPredRegFor(GPR); local 409 MIB.addReg(Pred.R, 0, Pred.S);
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/external/clang/lib/StaticAnalyzer/Core/ |
H A D | BugReporterVisitors.cpp | 451 const ExplodedNode *Pred, 464 if (isInitializationOfVar(Pred, VR)) { 465 StoreSite = Pred; 472 if (Optional<PostInitializer> PIP = Pred->getLocationAs<PostInitializer>()) { 475 StoreSite = Pred; 481 // (1) Succ has this binding and Pred does not, i.e. this is 489 if (Pred->getState()->getSVal(R) == V) { 812 const ExplodedNode *Pred, 827 if (!Pred->getState()->isNull(V).isConstrainedTrue()) { 450 VisitNode(const ExplodedNode *Succ, const ExplodedNode *Pred, BugReporterContext &BRC, BugReport &BR) argument 811 VisitNode(const ExplodedNode *Succ, const ExplodedNode *Pred, BugReporterContext &BRC, BugReport &BR) argument
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/external/llvm/lib/Transforms/ObjCARC/ |
H A D | ObjCARCOpts.cpp | 310 void addPred(BasicBlock *Pred) { Preds.push_back(Pred); } argument 1241 BasicBlock *Pred = *PI; local 1242 if (InvokeInst *II = dyn_cast<InvokeInst>(&Pred->back())) 1334 const BasicBlock *Pred = *PI; local 1335 DenseMap<const BasicBlock *, BBState>::iterator I = BBStates.find(Pred); 1340 Pred = *PI; 1341 I = BBStates.find(Pred);
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/external/llvm/utils/TableGen/ |
H A D | DAGISelMatcher.cpp | 98 : Matcher(CheckPredicate), Pred(pred.getOrigPatFragRecord()) {} 101 return TreePredicateFn(Pred);
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