/external/mesa3d/src/mesa/swrast/ |
H A D | s_blit.c | 674 GLubyte *src1 = srcMap + srcY1 * srcRowStride + srcXpos * bpp; local 679 src1, srcBuffer1); 683 _mesa_unpack_rgba_row(readFormat, srcWidth, src1, srcBuffer1);
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/external/opencv/cxcore/src/ |
H A D | cxdxt.cpp | 1661 const int* src1 = (const int*)_src1; 1669 t0 = src0[i]; t1 = src1[i]; 1679 t0 = src1[i]; t1 = src1[i+1]; 1691 t0 = src1[i]; t1 = src1[i+1]; 1693 t0 = src1[i+2]; t1 = src1[i+3]; 2460 const datatype* src1 = src + (n-1)*src_step; \ 2471 src += src_step, src1 [all...] |
/external/v8/src/ia32/ |
H A D | assembler-ia32.cc | 2747 void Assembler::vfmasd(byte op, XMMRegister dst, XMMRegister src1, argument 2751 emit_vex_prefix(src1, kLIG, k66, k0F38, kW1); 2757 void Assembler::vfmass(byte op, XMMRegister dst, XMMRegister src1, argument 2761 emit_vex_prefix(src1, kLIG, k66, k0F38, kW0); 2767 void Assembler::vsd(byte op, XMMRegister dst, XMMRegister src1, argument 2771 emit_vex_prefix(src1, kLIG, kF2, k0F, kWIG); 2777 void Assembler::vss(byte op, XMMRegister dst, XMMRegister src1, argument 2781 emit_vex_prefix(src1, kLIG, kF3, k0F, kWIG); 2787 void Assembler::vps(byte op, XMMRegister dst, XMMRegister src1, argument 2791 emit_vex_prefix(src1, kL12 2797 vpd(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2) argument [all...] |
/external/llvm/lib/Target/AMDGPU/ |
H A D | R600InstrInfo.cpp | 254 AMDGPU::OpName::src1, 265 {AMDGPU::OpName::src1, AMDGPU::OpName::src1_sel}, 318 {AMDGPU::OpName::src1, AMDGPU::OpName::src1_sel}, 549 //Todo : support shared src0 - src1 operand 1284 MIB.addReg(Src1Reg) // $src1 1326 OPERAND_CASE(AMDGPU::OpName::src1) 1352 getOperandIdx(MI->getOpcode(), getSlotedOps(AMDGPU::OpName::src1, Slot)));
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H A D | R600Packetizer.cpp | 135 AMDGPU::OpName::src1,
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H A D | SIInstrInfo.cpp | 959 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::src1); 972 // src0. Make sure we can use the src0 as src1. 1047 int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1); 1054 // operand src1 in 2 and 3 operand instructions. 1240 MachineOperand *Src1 = getNamedOperand(UseMI, AMDGPU::OpName::src1); 1434 const MachineOperand *Src1 = getNamedOperand(MI, AMDGPU::OpName::src1); 1653 int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1); 1766 ErrInfo = "v_div_scale_{f32|f64} require src0 = src1 or src2"; 2054 int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1); 2073 // their legality. If src1 i [all...] |
/external/v8/src/crankshaft/mips/ |
H A D | lithium-codegen-mips.cc | 774 Register src1, const Operand& src2) { 808 __ Branch(&skip, NegateCondition(condition), src1, src2); 822 __ Call(entry, RelocInfo::RUNTIME_ENTRY, condition, src1, src2); 833 __ Branch(&jump_table_.last().label, condition, src1, src2); 838 DeoptimizeReason deopt_reason, Register src1, 843 DeoptimizeIf(condition, instr, deopt_reason, bailout_type, src1, src2); 1847 Register src1, 1857 NegateCondition(condition), src1, src2); 1859 __ Branch(chunk_->GetAssemblyLabel(left_block), condition, src1, src2); 1861 __ Branch(chunk_->GetAssemblyLabel(left_block), condition, src1, src 771 DeoptimizeIf(Condition condition, LInstruction* instr, DeoptimizeReason deopt_reason, Deoptimizer::BailoutType bailout_type, Register src1, const Operand& src2) argument 837 DeoptimizeIf(Condition condition, LInstruction* instr, DeoptimizeReason deopt_reason, Register src1, const Operand& src2) argument 1845 EmitBranch(InstrType instr, Condition condition, Register src1, const Operand& src2) argument 1868 EmitBranchF(InstrType instr, Condition condition, FPURegister src1, FPURegister src2) argument 1893 EmitTrueBranch(InstrType instr, Condition condition, Register src1, const Operand& src2) argument 1901 EmitFalseBranch(InstrType instr, Condition condition, Register src1, const Operand& src2) argument 1909 EmitFalseBranchF(InstrType instr, Condition condition, FPURegister src1, FPURegister src2) argument [all...] |
/external/v8/src/crankshaft/mips64/ |
H A D | lithium-codegen-mips64.cc | 762 Register src1, const Operand& src2) { 796 __ Branch(&skip, NegateCondition(condition), src1, src2); 810 __ Call(entry, RelocInfo::RUNTIME_ENTRY, condition, src1, src2); 822 __ Branch(&jump_table_.last()->label, condition, src1, src2); 827 DeoptimizeReason deopt_reason, Register src1, 832 DeoptimizeIf(condition, instr, deopt_reason, bailout_type, src1, src2); 1968 Register src1, 1978 NegateCondition(condition), src1, src2); 1980 __ Branch(chunk_->GetAssemblyLabel(left_block), condition, src1, src2); 1982 __ Branch(chunk_->GetAssemblyLabel(left_block), condition, src1, src 759 DeoptimizeIf(Condition condition, LInstruction* instr, DeoptimizeReason deopt_reason, Deoptimizer::BailoutType bailout_type, Register src1, const Operand& src2) argument 826 DeoptimizeIf(Condition condition, LInstruction* instr, DeoptimizeReason deopt_reason, Register src1, const Operand& src2) argument 1966 EmitBranch(InstrType instr, Condition condition, Register src1, const Operand& src2) argument 1989 EmitBranchF(InstrType instr, Condition condition, FPURegister src1, FPURegister src2) argument 2014 EmitTrueBranch(InstrType instr, Condition condition, Register src1, const Operand& src2) argument 2022 EmitFalseBranch(InstrType instr, Condition condition, Register src1, const Operand& src2) argument 2030 EmitFalseBranchF(InstrType instr, Condition condition, FPURegister src1, FPURegister src2) argument [all...] |
/external/deqp/modules/gles31/functional/ |
H A D | es31fBasicComputeShaderTests.cpp | 721 std::ostringstream src1; 722 src1 << glslVersionDeclaration << "\n" 738 const ShaderProgram program1 (m_context.getRenderContext(), ProgramSources() << ComputeSource(src1.str())); 1388 std::ostringstream src1; 1389 src1 << glslVersionDeclaration << "\n" 1401 const ShaderProgram program1 (m_context.getRenderContext(), ProgramSources() << ComputeSource(src1.str()));
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/external/libdrm/intel/ |
H A D | intel_decode.c | 871 char dst[100], src0[100], src1[100]; local 875 i915_get_instruction_src1(ctx->data, i, src1); 878 op_name, dst, src0, src1); 887 char dst[100], src0[100], src1[100], src2[100]; local 891 i915_get_instruction_src1(ctx->data, i, src1); 895 op_name, dst, src0, src1, src2);
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/external/mesa3d/src/gallium/drivers/nouveau/codegen/ |
H A D | nv50_ir_emit_gk110.cpp | 1306 const int src1 = (i->predSrc == 1) ? 2 : 1; // if predSrc == 1, !srcExists(2) local 1310 srcId(i, src1, 23); 1324 if (i->srcExists(src1) && i->src(src1).getFile() == FILE_IMMEDIATE) { 1860 const int src1 = (i->predSrc == 1) ? 2 : 1; // if predSrc == 1, !srcExists(2) local 1863 srcId(i, src1, 10);
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H A D | nv50_ir_emit_nvc0.cpp | 1344 const int src1 = (i->predSrc == 1) ? 2 : 1; // if predSrc == 1, !srcExists(2) local 1346 if (i->srcExists(src1) && i->src(src1).getFile() == FILE_IMMEDIATE) { 1363 srcId(i, src1, 26); 1391 const int src1 = (i->predSrc == 1) ? 2 : 1; // if predSrc == 1, !srcExists(2) local 1395 srcId(i, src1, 26); 1608 const int src1 = (i->predSrc == 1) ? 2 : 1; // if predSrc == 1, !srcExists(2) local 1611 srcId(i, src1, 20);
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/external/webp/src/dsp/ |
H A D | enc_sse2.c | 300 const __m128i src1 = _mm_loadl_epi64((const __m128i*)&src[1 * BPS]); local 308 const __m128i src_0 = _mm_unpacklo_epi16(src0, src1); 345 const __m128i src1 = _mm_loadl_epi64((const __m128i*)&src[1 * BPS]); local 349 const __m128i src_1 = _mm_unpacklo_epi8(src1, zero); 391 const __m128i src1 = _mm_loadl_epi64((__m128i*)&in[1 * 16]); local 394 const __m128i A01 = _mm_unpacklo_epi16(src0, src1); // A0 A1 | ...
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/external/icu/icu4c/source/test/cintltst/ |
H A D | idnatest.c | 652 const UChar* src1 = data[i]; local 653 int32_t src1Len = u_strlen(src1); 662 dest1Len = uidna_toASCII(src1, src1Len, dest1, dest1Len,UIDNA_DEFAULT, &ps, &status);
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/external/libvpx/libvpx/third_party/libyuv/include/libyuv/ |
H A D | planar_functions.h | 436 // and 255 means 1% src0 and 99% src1. 439 const uint8* src1, int src_stride1,
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/external/libyuv/files/include/libyuv/ |
H A D | planar_functions.h | 671 // and 255 means 1% src0 and 99% src1. 675 const uint8* src1,
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/external/mesa3d/src/intel/vulkan/ |
H A D | anv_blorp.c | 392 flip_coords(unsigned *src0, unsigned *src1, unsigned *dst0, unsigned *dst1) argument 395 if (*src0 > *src1) { 397 *src0 = *src1; 398 *src1 = tmp;
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/external/mesa3d/src/mesa/drivers/dri/i965/ |
H A D | brw_fs.h | 443 struct brw_reg src1);
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H A D | brw_inst.h | 661 BRW_IA1_ADDR_IMM(src1, 105, 96, 121, 104, 96) 694 BRW_IA16_ADDR_IMM(src1, 105, 96, 121, 104, 100)
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/external/v8/src/s390/ |
H A D | code-stubs-s390.h | 416 // src1 and src2 will be cloberred. 419 // - src1: higher (exponent) part of the double value. 425 static void DoubleIs32BitInteger(MacroAssembler* masm, Register src1,
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/external/mesa3d/src/gallium/state_trackers/nine/ |
H A D | nine_shader.c | 774 struct ureg_src src1, INT idx) 784 ureg_TEX(tx->ureg, dst, target, src0, src1); 786 ureg_TXP(tx->ureg, dst, target, src0, src1); 790 ureg_TEX(tx->ureg, dst, target, ureg_src(tmp), src1); 1588 struct ureg_src src1 = tx_src_param(tx, &tx->insn.src[1]); local 1590 ureg_ADD(ureg, dst, src0, ureg_negate(src1)); 2735 struct ureg_src src1 = tx_src_param(tx, &tx->insn.src[1]); local 2751 /* dest.r = src0.r + D3DTSS_BUMPENVMAT00(stage n) * src1.r */ 2753 NINE_APPLY_SWIZZLE(src1, X), NINE_APPLY_SWIZZLE(src0, X)); 2754 /* dest.r = dest.r + D3DTSS_BUMPENVMAT10(stage n) * src1 772 TEX_with_ps1x_projection(struct shader_translator *tx, struct ureg_dst dst, unsigned target, struct ureg_src src0, struct ureg_src src1, INT idx) argument [all...] |
/external/boringssl/src/crypto/perlasm/ |
H A D | x86_64-xlate.pl | 1081 my ($dst,$src1,$src2,$rxb)=@_; 1085 $rxb&=~(0x01<<5) if($src1>=8);
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/external/protobuf/gtest/test/ |
H A D | gtest_unittest.cc | 855 const std::string src1(""); 856 const String dest1 = src1; 877 const String src1(""); 878 const std::string dest1 = src1; 896 const ::string src1(""); 897 const String dest1 = src1; 918 const String src1(""); 919 const ::string dest1 = src1;
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/external/swiftshader/src/OpenGL/compiler/ |
H A D | OutputASM.cpp | 2049 Instruction *OutputASM::emit(sw::Shader::Opcode op, TIntermTyped *dst, TIntermNode *src0, TIntermNode *src1, TIntermNode *src2, TIntermNode *src3, TIntermNode *src4) argument 2051 return emit(op, dst, 0, src0, 0, src1, 0, src2, 0, src3, 0, src4, 0); 2054 Instruction *OutputASM::emit(sw::Shader::Opcode op, TIntermTyped *dst, int dstIndex, TIntermNode *src0, int index0, TIntermNode *src1, int index1, argument 2071 source(instruction->src[1], src1, index1); 2135 void OutputASM::emitBinary(sw::Shader::Opcode op, TIntermTyped *dst, TIntermNode *src0, TIntermNode *src1, TIntermNode *src2) argument 2139 emit(op, dst, index, src0, index, src1, index, src2, index); 2143 void OutputASM::emitAssign(sw::Shader::Opcode op, TIntermTyped *result, TIntermTyped *lhs, TIntermTyped *src0, TIntermTyped *src1) argument 2145 emitBinary(op, result, src0, src1);
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/external/valgrind/VEX/priv/ |
H A D | host_mips_defs.h | 550 HReg src1; member in struct:__anon28398::__anon28399::__anon28422 651 extern MIPSInstr *MIPSInstr_FpTernary ( MIPSFpOp op, HReg dst, HReg src1,
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