Searched refs:src1 (Results 51 - 75 of 339) sorted by relevance

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/external/libvpx/libvpx/vpx_dsp/mips/
H A D	sad_msa.c	27 uint32_t src0, src1, src2, src3, ref0, ref1, ref2, ref3; local 34 LW4(src_ptr, src_stride, src0, src1, src2, src3); 39 INSERT_W4_UB(src0, src1, src2, src3, src); 53 v16u8 src0, src1, src2, src3, ref0, ref1, ref2, ref3; local 57 LD_UB4(src, src_stride, src0, src1, src2, src3); 62 PCKEV_D4_UB(src1, src0, src3, src2, ref1, ref0, ref3, ref2, src0, src1, 64 sad += SAD_UB2_UH(src0, src1, ref0, ref1); 74 v16u8 src0, src1, ref0, ref1; local 78 LD_UB2(src, src_stride, src0, src1); 98 v16u8 src0, src1, ref0, ref1; local 135 v16u8 src0, src1, src2, src3; local 166 uint32_t src0, src1, src2, src3; local 207 v16u8 src0, src1, src2, src3; local 290 uint32_t src0, src1, src2, src3; local 371 v16u8 src0, src1, src2, src3; local 542 uint32_t src0, src1, src2, src3; local 603 v16u8 src0, src1, src2, src3; local 719 v16u8 src0, src1, ref0, ref1; local 763 v16u8 src0, src1, src2, src3; local 826 uint32_t src0, src1, src2, src3, ref0, ref1, ref2, ref3; local 855 v16u8 src0, src1, src2, src3, ref0, ref1, ref2, ref3; local 879 v16u8 src0, src1, src2, src3, ref0, ref1, ref2, ref3; local 914 v16u8 src0, src1, src2, src3, src4, src5, src6, src7; local 950 v16u8 src0, src1, src2, src3; local [all...]
H A D	vpx_convolve8_avg_vert_msa.c	21 v16i8 src0, src1, src2, src3, src4, src5, src6, src7, src8, src9, src10; local 33 LD_SB7(src, src_stride, src0, src1, src2, src3, src4, src5, src6); 36 ILVR_B4_SB(src1, src0, src3, src2, src5, src4, src2, src1, src10_r, src32_r, 78 v16i8 src0, src1, src2, src3, src4, src5, src6, src7, src8, src9, src10; local 89 LD_SB7(src, src_stride, src0, src1, src2, src3, src4, src5, src6); 92 XORI_B7_128_SB(src0, src1, src2, src3, src4, src5, src6); 93 ILVR_B4_SB(src1, src0, src3, src2, src5, src4, src2, src1, src10_r, src32_r, 137 v16i8 src0, src1, src local 252 v16i8 src0, src1, src2, src3, src4; local 287 v16i8 src0, src1, src2, src3, src4, src5, src6, src7, src8, src87_r; local 334 v16u8 src0, src1, src2, src3, src4; local 360 v16u8 src0, src1, src2, src3, src4, src5, src6, src7, src8; local 420 v16u8 src0, src1, src2, src3, src4, dst0, dst1, dst2, dst3, filt0; local 469 v16u8 src0, src1, src2, src3, src4, src5, src6, src7, src8, src9; local 540 v16u8 src0, src1, src2, src3, src4, src5; local [all...]
H A D	vpx_convolve8_avg_horiz_msa.c	20 v16i8 src0, src1, src2, src3, filt0, filt1, filt2, filt3; local 36 LD_SB4(src, src_stride, src0, src1, src2, src3); 37 XORI_B4_128_SB(src0, src1, src2, src3); 38 HORIZ_8TAP_4WID_4VECS_FILT(src0, src1, src2, src3, mask0, mask1, mask2, mask3, 54 v16i8 src0, src1, src2, src3, filt0, filt1, filt2, filt3; local 70 LD_SB4(src, src_stride, src0, src1, src2, src3); 71 XORI_B4_128_SB(src0, src1, src2, src3); 77 HORIZ_8TAP_4WID_4VECS_FILT(src0, src1, src2, src3, mask0, mask1, mask2, mask3, 79 LD_SB4(src, src_stride, src0, src1, src2, src3); 80 XORI_B4_128_SB(src0, src1, src 110 v16i8 src0, src1, src2, src3, filt0, filt1, filt2, filt3; local 148 v16i8 src0, src1, src2, src3, filt0, filt1, filt2, filt3; local 202 v16i8 src0, src1, src2, src3, filt0, filt1, filt2, filt3; local 257 v16i8 src0, src1, src2, src3, filt0, filt1, filt2, filt3; local 317 v16i8 src0, src1, src2, src3, mask; local 343 v16i8 src0, src1, src2, src3, src4, src5, src6, src7, mask; local 387 v16i8 src0, src1, src2, src3, mask; local 413 v16i8 src0, src1, src2, src3, mask; local 494 v16i8 src0, src1, src2, src3, src4, src5, src6, src7, mask; local 561 v16i8 src0, src1, src2, src3, src4, src5, src6, src7, mask; local 610 v16i8 src0, src1, src2, src3, src4, src5, src6, src7, mask; local [all...]
H A D	vpx_convolve_avg_msa.c	18 v16u8 src0, src1, src2, src3; local 23 LD_UB4(src, src_stride, src0, src1, src2, src3); 28 AVER_UB4_UB(src0, dst0, src1, dst1, src2, dst2, src3, dst3, dst0, dst1, 40 LD_UB2(src, src_stride, src0, src1); 45 AVER_UB2_UB(src0, dst0, src1, dst1, dst0, dst1); 61 v16u8 src0, src1, src2, src3; local 65 LD_UB4(src, src_stride, src0, src1, src2, src3); 69 AVER_UB4_UB(src0, dst0, src1, dst1, src2, dst2, src3, dst3, dst0, dst1, 84 v16u8 src0, src1, src2, src3, src4, src5, src6, src7; local 88 LD_UB8(src, src_stride, src0, src1, src 105 v16u8 src0, src1, src2, src3, src4, src5, src6, src7; local 146 v16u8 src0, src1, src2, src3, src4, src5, src6, src7; local [all...]
H A D	subtract_msa.c	17 uint32_t src0, src1, src2, src3; local 24 LW4(src_ptr, src_stride, src0, src1, src2, src3); 26 INSERT_W4_SB(src0, src1, src2, src3, src); 37 uint64_t src0, src1, pred0, pred1; local 44 LD2(src_ptr, src_stride, src0, src1); 49 INSERT_D2_SB(src0, src1, src); 62 v16i8 src0, src1, src2, src3, src4, src5, src6, src7; local 68 LD_SB8(src, src_stride, src0, src1, src2, src3, src4, src5, src6, src7); 80 ILVRL_B2_UB(src1, pred1, src_l0, src_l1); 121 v16i8 src0, src1, src local 183 v16i8 src0, src1, src2, src3, src4, src5, src6, src7; local [all...]
/external/webp/src/dsp/
H A D	rescaler_msa.c	124 v4u32 src0, src1, src2, src3; local 126 LD_UW4(frow, 4, src0, src1, src2, src3); 127 CALC_MULT_FIX_16(src0, src1, src2, src3, scale, shift, out); 137 v4u32 src0, src1, src2; local 138 LD_UW3(frow, 4, src0, src1, src2); 140 CALC_MULT_FIX_4(src1, scale, shift, val1_m); 148 v4u32 src0, src1; local 149 LD_UW2(frow, 4, src0, src1); 151 CALC_MULT_FIX_4(src1, scale, shift, val1_m); 275 v4u32 src0, src1, src local 295 v4u32 src0, src1, src2, frac0, frac1, frac2; local 313 v4u32 src0, src1, frac0, frac1; local 360 v4u32 src0, src1, src2, src3; local 374 v4u32 src0, src1, src2; local 386 v4u32 src0, src1; local [all...]
H A D	ssim.c	63 static double SSIMGetClipped_C(const uint8_t* src1, int stride1, argument 74 src1 += ymin * stride1; 76 for (y = ymin; y <= ymax; ++y, src1 += stride1, src2 += stride2) { 80 const uint32_t s1 = src1[x]; 93 static double SSIMGet_C(const uint8_t* src1, int stride1, argument 97 for (y = 0; y <= 2 * VP8_SSIM_KERNEL; ++y, src1 += stride1, src2 += stride2) { 100 const uint32_t s1 = src1[x]; 117 static uint32_t AccumulateSSE_C(const uint8_t* src1, argument 123 const int32_t diff = src1[i] - src2[i];
H A D	ssim_sse2.c	45 static uint32_t AccumulateSSE_SSE2(const uint8_t* src1, argument 54 __m128i a0 = _mm_loadu_si128((const __m128i*)&src1[i]); 58 const __m128i a1 = _mm_loadu_si128((const __m128i*)&src1[i]); 64 a0 = _mm_loadu_si128((const __m128i*)&src1[i]); 77 const int32_t diff = src1[i] - src2[i]; 108 const __m128i a0 = _mm_loadl_epi64((const __m128i*)src1); \ 121 src1 += stride1; \ 125 static double SSIMGet_SSE2(const uint8_t* src1, int stride1, argument
/external/mesa3d/src/compiler/nir/
H A D	nir_opcodes.py	47 Constant expressions are formed from the variables src0, src1, ..., 130 def reduce_(src0, src1): 131 return reduce_expr.format(src0=src0, src1=src1) 133 src1 = prereduce("src0.y") 137 final(reduce_(src0, src1))) 139 final(reduce_(reduce_(src0, src1), src2))) 141 final(reduce_(reduce_(src0, src1), reduce_(src2, src3)))) 361 def reduce_(src0, src1): 362 return reduce_expr.format(src0=src0, src1 [all...]
H A D	nir_instr_set.c	95 nir_phi_src *src1 = *(nir_phi_src **)data1; local 97 return src1->pred - src2->pred; 205 nir_srcs_equal(nir_src src1, nir_src src2) argument 207 if (src1.is_ssa) { 209 return src1.ssa == src2.ssa; 217 if ((src1.reg.indirect == NULL) != (src2.reg.indirect == NULL)) 220 if (src1.reg.indirect) { 221 if (!nir_srcs_equal(*src1.reg.indirect, *src2.reg.indirect)) 225 return src1.reg.reg == src2.reg.reg && 226 src1 232 nir_alu_srcs_equal(const nir_alu_instr *alu1, const nir_alu_instr *alu2, unsigned src1, unsigned src2) argument [all...]
/external/mesa3d/src/mesa/drivers/dri/i965/
H A D	brw_fs_surface_builder.h	48 const fs_reg &src0, const fs_reg &src1, 64 const fs_reg &src0, const fs_reg &src1, 84 const fs_reg &src0, const fs_reg &src1,
H A D	brw_fs_builder.h	304 const src_reg &src1) const 312 fix_math_operand(src1))); 315 return emit(instruction(opcode, dispatch_width(), dst, src0, src1)); 325 const src_reg &src1, const src_reg &src2) const 334 fix_3src_operand(src1), 339 src0, src1, src2)); 379 * conditional mod evaluates to true, otherwise select \p src1. 385 const src_reg &src1, brw_conditional_mod mod) const 390 fix_unsigned_negate(src1))); 429 op(const dst_reg &dst, const src_reg &src0, const src_reg &src1) cons 324 emit(enum opcode opcode, const dst_reg &dst, const src_reg &src0, const src_reg &src1, const src_reg &src2) const argument 384 emit_minmax(const dst_reg &dst, const src_reg &src0, const src_reg &src1, brw_conditional_mod mod) const argument 507 CMP(const dst_reg &dst, const src_reg &src0, const src_reg &src1, brw_conditional_mod condition) const argument [all...]
H A D	brw_vec4_surface_builder.h	47 const src_reg &src0, const src_reg &src1, 63 const src_reg &src0, const src_reg &src1,
H A D	test_vec4_cmod_propagation.cpp	148 src_reg src1 = src_reg(v, glsl_type::float_type); local 153 bld.ADD(dest, src0, src1); 158 * 0: add dest.x src0.xxxx src1.xxxx 162 * 0: add.ge.f0 dest.x src0.xxxx src1.xxxx 184 src_reg src1 = src_reg(v, glsl_type::float_type); local 188 bld.ADD(dest, src0, src1); 193 * 0: add dest.x src0 src1 290 src_reg src1 = src_reg(v, glsl_type::float_type); local 293 bld.ADD(dest, src0, src1); 299 * 0: add dest src0 src1 330 src_reg src1 = src_reg(v, glsl_type::float_type); local 369 src_reg src1 = src_reg(v, glsl_type::float_type); local 372 bld.ADD(offset(dest, 8, 2), src0, src1); local 411 src_reg src1 = src_reg(v, glsl_type::float_type); local 452 src_reg src1 = src_reg(v, glsl_type::float_type); local 488 src_reg src1 = src_reg(v, glsl_type::float_type); local 524 src_reg src1 = src_reg(v, glsl_type::int_type); local 597 src_reg src1 = src_reg(v, glsl_type::vec4_type); local 631 src_reg src1 = src_reg(v, glsl_type::vec4_type); local 668 src_reg src1 = src_reg(v, glsl_type::vec4_type); local 710 src_reg src1 = src_reg(v, glsl_type::vec4_type); local 793 src_reg src1 = src_reg(v, glsl_type::vec4_type); local [all...]
/external/mesa3d/src/gallium/auxiliary/gallivm/
H A D	lp_bld_tgsi_aos.c	480 LLVMValueRef src0, src1, src2; local 536 src1 = lp_build_emit_fetch(&bld->bld_base, inst, 1, LP_CHAN_ALL); 537 dst0 = lp_build_mul(&bld->bld_base.base, src0, src1); 542 src1 = lp_build_emit_fetch(&bld->bld_base, inst, 1, LP_CHAN_ALL); 543 dst0 = lp_build_add(&bld->bld_base.base, src0, src1); 559 src1 = lp_build_emit_fetch(&bld->bld_base, inst, 1, LP_CHAN_ALL); 560 dst0 = lp_build_min(&bld->bld_base.base, src0, src1); 565 src1 = lp_build_emit_fetch(&bld->bld_base, inst, 1, LP_CHAN_ALL); 566 dst0 = lp_build_max(&bld->bld_base.base, src0, src1); 572 src1 [all...]
/external/avb/libavb/
H A D	avb_sysdeps_posix.c	33 int avb_memcmp(const void* src1, const void* src2, size_t n) { argument 34 return memcmp(src1, src2, n);
/external/skia/tests/
H A D	CPlusPlusEleven.cpp	29 Moveable src1; Moveable dst1(std::move(src1)); local
/external/skqp/tests/
H A D	CPlusPlusEleven.cpp	29 Moveable src1; Moveable dst1(std::move(src1)); local
/external/swiftshader/src/Shader/
H A D	PixelProgram.cpp	112 const Src &src1 = instruction->src[1]; local 146 if(src1.type != Shader::PARAMETER_VOID) s1 = fetchRegister(src1); 281 case Shader::OPCODE_M4X4: M4X4(d, s0, src1); break; 282 case Shader::OPCODE_M4X3: M4X3(d, s0, src1); break; 283 case Shader::OPCODE_M3X4: M3X4(d, s0, src1); break; 284 case Shader::OPCODE_M3X3: M3X3(d, s0, src1); break; 285 case Shader::OPCODE_M3X2: M3X2(d, s0, src1); break; 286 case Shader::OPCODE_TEX: TEX(d, s0, src1, project, bias); break; 287 case Shader::OPCODE_TEXLDD: TEXGRAD(d, s0, src1, s 1061 M3X2(Vector4f &dst, Vector4f &src0, const Src &src1) argument 1070 M3X3(Vector4f &dst, Vector4f &src0, const Src &src1) argument 1081 M3X4(Vector4f &dst, Vector4f &src0, const Src &src1) argument 1094 M4X3(Vector4f &dst, Vector4f &src0, const Src &src1) argument 1105 M4X4(Vector4f &dst, Vector4f &src0, const Src &src1) argument 1118 TEX(Vector4f &dst, Vector4f &src0, const Src &src1, bool project, bool bias) argument 1136 TEXOFFSET(Vector4f &dst, Vector4f &src0, const Src &src1, Vector4f &offset) argument 1141 TEXLODOFFSET(Vector4f &dst, Vector4f &src0, const Src &src1, Vector4f &offset, Float4 &lod) argument 1146 TEXBIAS(Vector4f &dst, Vector4f &src0, const Src &src1, Float4 &bias) argument 1151 TEXOFFSETBIAS(Vector4f &dst, Vector4f &src0, const Src &src1, Vector4f &offset, Float4 &bias) argument 1156 TEXELFETCH(Vector4f &dst, Vector4f &src0, const Src& src1, Float4 &lod) argument 1161 TEXELFETCHOFFSET(Vector4f &dst, Vector4f &src0, const Src& src1, Vector4f &offset, Float4 &lod) argument 1166 TEXGRAD(Vector4f &dst, Vector4f &src0, const Src& src1, Vector4f &dsx, Vector4f &dsy) argument 1171 TEXGRADOFFSET(Vector4f &dst, Vector4f &src0, const Src& src1, Vector4f &dsx, Vector4f &dsy, Vector4f &offset) argument 1176 TEXLOD(Vector4f &dst, Vector4f &src0, const Src &src1, Float4 &lod) argument 1181 TEXSIZE(Vector4f &dst, Float4 &lod, const Src &src1) argument 1257 BREAKC(Vector4f &src0, Vector4f &src1, Control control) argument [all...]
/external/mesa3d/src/gallium/drivers/ilo/shader/
H A D	toy_compiler.h	259 struct toy_src src1, 271 inst->src[1] = src1; 284 struct toy_src src1) 286 return tc_add3(tc, opcode, dst, src0, src1, tsrc_null()); 331 struct toy_src src1) \ 334 dst, src0, src1); \ 342 struct toy_src src1, \ 346 dst, src0, src1, src2); \ 354 struct toy_src src1, \ 359 dst, src0, src1); \ 256 tc_add3(struct toy_compiler *tc, unsigned opcode, struct toy_dst dst, struct toy_src src0, struct toy_src src1, struct toy_src src2) argument 281 tc_add2(struct toy_compiler *tc, int opcode, struct toy_dst dst, struct toy_src src0, struct toy_src src1) argument [all...]
/external/v8/src/arm/
H A D	macro-assembler-arm.h	152 void Mls(Register dst, Register src1, Register src2, Register srcA, 154 void And(Register dst, Register src1, const Operand& src2, 337 void Push(Register src1, Register src2, Condition cond = al) { argument 338 if (src1.code() > src2.code()) { 339 stm(db_w, sp, src1.bit() | src2.bit(), cond); 341 str(src1, MemOperand(sp, 4, NegPreIndex), cond); 347 void Push(Register src1, Register src2, Register src3, Condition cond = al) { argument 348 if (src1.code() > src2.code()) { 350 stm(db_w, sp, src1.bit() | src2.bit() | src3.bit(), cond); 352 stm(db_w, sp, src1 362 Push(Register src1, Register src2, Register src3, Register src4, Condition cond = al) argument 389 Push(Register src1, Register src2, Register src3, Register src4, Register src5, Condition cond = al) argument 418 Pop(Register src1, Register src2, Condition cond = al) argument 429 Pop(Register src1, Register src2, Register src3, Condition cond = al) argument 445 Pop(Register src1, Register src2, Register src3, Register src4, Condition cond = al) argument [all...]
H A D	assembler-arm.cc	1509 void Assembler::and_(Register dst, Register src1, const Operand& src2, argument 1511 addrmod1(cond | AND | s, src1, dst, src2); 1515 void Assembler::eor(Register dst, Register src1, const Operand& src2, argument 1517 addrmod1(cond | EOR | s, src1, dst, src2); 1521 void Assembler::sub(Register dst, Register src1, const Operand& src2, argument 1523 addrmod1(cond | SUB | s, src1, dst, src2); 1527 void Assembler::rsb(Register dst, Register src1, const Operand& src2, argument 1529 addrmod1(cond | RSB | s, src1, dst, src2); 1533 void Assembler::add(Register dst, Register src1, const Operand& src2, argument 1535 addrmod1(cond | ADD | s, src1, ds 1539 adc(Register dst, Register src1, const Operand& src2, SBit s, Condition cond) argument 1545 sbc(Register dst, Register src1, const Operand& src2, SBit s, Condition cond) argument 1551 rsc(Register dst, Register src1, const Operand& src2, SBit s, Condition cond) argument 1557 tst(Register src1, const Operand& src2, Condition cond) argument 1562 teq(Register src1, const Operand& src2, Condition cond) argument 1567 cmp(Register src1, const Operand& src2, Condition cond) argument 1579 cmn(Register src1, const Operand& src2, Condition cond) argument 1584 orr(Register dst, Register src1, const Operand& src2, SBit s, Condition cond) argument 1650 bic(Register dst, Register src1, const Operand& src2, SBit s, Condition cond) argument 1662 mla(Register dst, Register src1, Register src2, Register srcA, SBit s, Condition cond) argument 1670 mls(Register dst, Register src1, Register src2, Register srcA, Condition cond) argument 1679 sdiv(Register dst, Register src1, Register src2, Condition cond) argument 1688 udiv(Register dst, Register src1, Register src2, Condition cond) argument 1697 mul(Register dst, Register src1, Register src2, SBit s, Condition cond) argument 1705 smmla(Register dst, Register src1, Register src2, Register srcA, Condition cond) argument 1713 smmul(Register dst, Register src1, Register src2, Condition cond) argument 1721 smlal(Register dstL, Register dstH, Register src1, Register src2, SBit s, Condition cond) argument 1734 smull(Register dstL, Register dstH, Register src1, Register src2, SBit s, Condition cond) argument 1747 umlal(Register dstL, Register dstH, Register src1, Register src2, SBit s, Condition cond) argument 1760 umull(Register dstL, Register dstH, Register src1, Register src2, SBit s, Condition cond) argument 1875 pkhbt(Register dst, Register src1, const Operand& src2, Condition cond ) argument 1894 pkhtb(Register dst, Register src1, const Operand& src2, Condition cond) argument 1926 sxtab(Register dst, Register src1, Register src2, int rotate, Condition cond) argument 1952 sxtah(Register dst, Register src1, Register src2, int rotate, Condition cond) argument 1978 uxtab(Register dst, Register src1, Register src2, int rotate, Condition cond) argument 2016 uxtah(Register dst, Register src1, Register src2, int rotate, Condition cond) argument 2123 strd(Register src1, Register src2, const MemOperand& dst, Condition cond) argument 2139 strex(Register src1, Register src2, Register dst, Condition cond) argument 2155 strexb(Register src1, Register src2, Register dst, Condition cond) argument 2171 strexh(Register src1, Register src2, Register dst, Condition cond) argument 2891 vmov(const DwVfpRegister dst, const Register src1, const Register src2, const Condition cond) argument 3228 vadd(const DwVfpRegister dst, const DwVfpRegister src1, const DwVfpRegister src2, const Condition cond) argument 3251 vadd(const SwVfpRegister dst, const SwVfpRegister src1, const SwVfpRegister src2, const Condition cond) argument 3269 vsub(const DwVfpRegister dst, const DwVfpRegister src1, const DwVfpRegister src2, const Condition cond) argument 3292 vsub(const SwVfpRegister dst, const SwVfpRegister src1, const SwVfpRegister src2, const Condition cond) argument 3310 vmul(const DwVfpRegister dst, const DwVfpRegister src1, const DwVfpRegister src2, const Condition cond) argument 3333 vmul(const SwVfpRegister dst, const SwVfpRegister src1, const SwVfpRegister src2, const Condition cond) argument 3351 vmla(const DwVfpRegister dst, const DwVfpRegister src1, const DwVfpRegister src2, const Condition cond) argument 3372 vmla(const SwVfpRegister dst, const SwVfpRegister src1, const SwVfpRegister src2, const Condition cond) argument 3388 vmls(const DwVfpRegister dst, const DwVfpRegister src1, const DwVfpRegister src2, const Condition cond) argument 3409 vmls(const SwVfpRegister dst, const SwVfpRegister src1, const SwVfpRegister src2, const Condition cond) argument 3425 vdiv(const DwVfpRegister dst, const DwVfpRegister src1, const DwVfpRegister src2, const Condition cond) argument 3448 vdiv(const SwVfpRegister dst, const SwVfpRegister src1, const SwVfpRegister src2, const Condition cond) argument 3466 vcmp(const DwVfpRegister src1, const DwVfpRegister src2, const Condition cond) argument 3484 vcmp(const SwVfpRegister src1, const SwVfpRegister src2, const Condition cond) argument 3499 vcmp(const DwVfpRegister src1, const double src2, const Condition cond) argument 3514 vcmp(const SwVfpRegister src1, const float src2, const Condition cond) argument 3527 vmaxnm(const DwVfpRegister dst, const DwVfpRegister src1, const DwVfpRegister src2) argument 3543 vmaxnm(const SwVfpRegister dst, const SwVfpRegister src1, const SwVfpRegister src2) argument 3559 vminnm(const DwVfpRegister dst, const DwVfpRegister src1, const DwVfpRegister src2) argument 3575 vminnm(const SwVfpRegister dst, const SwVfpRegister src1, const SwVfpRegister src2) argument 3591 vsel(Condition cond, const DwVfpRegister dst, const DwVfpRegister src1, const DwVfpRegister src2) argument 3623 vsel(Condition cond, const SwVfpRegister dst, const SwVfpRegister src1, const SwVfpRegister src2) argument 4121 veor(DwVfpRegister dst, DwVfpRegister src1, DwVfpRegister src2) argument 4138 EncodeNeonBinaryBitwiseOp(BinaryBitwiseOp op, const QwNeonRegister dst, const QwNeonRegister src1, const QwNeonRegister src2) argument 4182 vand(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4190 vbsl(QwNeonRegister dst, const QwNeonRegister src1, const QwNeonRegister src2) argument 4198 veor(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4206 vorr(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4227 EncodeNeonBinOp(FPBinOp op, QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4289 EncodeNeonBinOp(IntegerBinOp op, NeonDataType dt, const QwNeonRegister dst, const QwNeonRegister src1, const QwNeonRegister src2) argument 4344 EncodeNeonBinOp(IntegerBinOp op, NeonSize size, const QwNeonRegister dst, const QwNeonRegister src1, const QwNeonRegister src2) argument 4353 vadd(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4361 vadd(NeonSize size, QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4369 vqadd(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4377 vsub(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4385 vsub(NeonSize size, QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4393 vqsub(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4401 vmul(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4409 vmul(NeonSize size, QwNeonRegister dst, const QwNeonRegister src1, const QwNeonRegister src2) argument 4417 vmin(const QwNeonRegister dst, const QwNeonRegister src1, const QwNeonRegister src2) argument 4425 vmin(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4433 vmax(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4441 vmax(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4516 vrecps(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4524 vrsqrts(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4532 vtst(NeonSize size, QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4540 vceq(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4548 vceq(NeonSize size, QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4556 vcge(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4564 vcge(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4572 vcgt(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4580 vcgt(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4588 vext(QwNeonRegister dst, const QwNeonRegister src1, const QwNeonRegister src2, int bytes) argument [all...]
/external/v8/src/s390/
H A D	macro-assembler-s390.h	258 void Add32(Register dst, Register src1, Register src2); 259 void AddP(Register dst, Register src1, Register src2); 260 void AddP_ExtendSrc(Register dst, Register src1, Register src2); 272 void AddLogical32(Register dst, Register src1, Register src2); 275 void AddLogicalWithCarry32(Register dst, Register src1, Register src2); 299 void Sub32(Register dst, Register src1, Register src2); 300 void SubP(Register dst, Register src1, Register src2); 301 void SubP_ExtendSrc(Register dst, Register src1, Register src2); 313 void SubLogical32(Register dst, Register src1, Register src2); 315 void SubLogicalWithBorrow32(Register dst, Register src1, Registe 594 Push(Register src1, Register src2) argument 601 Push(Register src1, Register src2, Register src3) argument 609 Push(Register src1, Register src2, Register src3, Register src4) argument 618 Push(Register src1, Register src2, Register src3, Register src4, Register src5) argument 642 Pop(Register src1, Register src2) argument 649 Pop(Register src1, Register src2, Register src3) argument 657 Pop(Register src1, Register src2, Register src3, Register src4) argument 666 Pop(Register src1, Register src2, Register src3, Register src4, Register src5) argument [all...]
/external/pcre/dist2/src/sljit/
H A D	sljitNativeX86_common.c	594 sljit_s32 src1, sljit_sw src1w, 600 sljit_s32 src1, sljit_sw src1w, 1483 sljit_s32 src1, sljit_sw src1w, 1489 EMIT_MOV(compiler, TMP_REG1, 0, src1, src1w); 1501 if (dst == src1 && dstw == src1w) { 1536 if (src1 & SLJIT_IMM) { 1549 inst = emit_x86_instruction(compiler, 1, dst, dstw, src1, src1w); 1553 else if (FAST_IS_REG(src1)) { 1554 inst = emit_x86_instruction(compiler, 1, src1, src1w, dst, dstw); 1559 EMIT_MOV(compiler, TMP_REG1, 0, src1, src1 1480 emit_cum_binary(struct sljit_compiler *compiler, sljit_u8 op_rm, sljit_u8 op_mr, sljit_u8 op_imm, sljit_u8 op_eax_imm, sljit_s32 dst, sljit_sw dstw, sljit_s32 src1, sljit_sw src1w, sljit_s32 src2, sljit_sw src2w) argument 1596 emit_non_cum_binary(struct sljit_compiler *compiler, sljit_u8 op_rm, sljit_u8 op_mr, sljit_u8 op_imm, sljit_u8 op_eax_imm, sljit_s32 dst, sljit_sw dstw, sljit_s32 src1, sljit_sw src1w, sljit_s32 src2, sljit_sw src2w) argument 1678 emit_mul(struct sljit_compiler *compiler, sljit_s32 dst, sljit_sw dstw, sljit_s32 src1, sljit_sw src1w, sljit_s32 src2, sljit_sw src2w) argument 1808 emit_lea_binary(struct sljit_compiler *compiler, sljit_s32 keep_flags, sljit_s32 dst, sljit_sw dstw, sljit_s32 src1, sljit_sw src1w, sljit_s32 src2, sljit_sw src2w) argument 1867 emit_cmp_binary(struct sljit_compiler *compiler, sljit_s32 src1, sljit_sw src1w, sljit_s32 src2, sljit_sw src2w) argument 1918 emit_test_binary(struct sljit_compiler *compiler, sljit_s32 src1, sljit_sw src1w, sljit_s32 src2, sljit_sw src2w) argument 2028 emit_shift(struct sljit_compiler *compiler, sljit_u8 mode, sljit_s32 dst, sljit_sw dstw, sljit_s32 src1, sljit_sw src1w, sljit_s32 src2, sljit_sw src2w) argument 2117 emit_shift_with_flags(struct sljit_compiler *compiler, sljit_u8 mode, sljit_s32 set_flags, sljit_s32 dst, sljit_sw dstw, sljit_s32 src1, sljit_sw src1w, sljit_s32 src2, sljit_sw src2w) argument 2152 sljit_emit_op2(struct sljit_compiler *compiler, sljit_s32 op, sljit_s32 dst, sljit_sw dstw, sljit_s32 src1, sljit_sw src1w, sljit_s32 src2, sljit_sw src2w) argument 2405 sljit_emit_fop1_cmp(struct sljit_compiler *compiler, sljit_s32 op, sljit_s32 src1, sljit_sw src1w, sljit_s32 src2, sljit_sw src2w) argument 2483 sljit_emit_fop2(struct sljit_compiler *compiler, sljit_s32 op, sljit_s32 dst, sljit_sw dstw, sljit_s32 src1, sljit_sw src1w, sljit_s32 src2, sljit_sw src2w) argument [all...]
/external/libyuv/files/source/
H A D	rotate_msa.cc	84 v16u8 src0, src1, src2, src3, dst0, dst1, dst2, dst3, vec0, vec1, vec2, vec3; local 92 src1 = (v16u8)__msa_ld_b((v16i8*)s, 0); 98 ILVRL_B(src0, src1, src2, src3, vec0, vec1, vec2, vec3); 102 src1 = (v16u8)__msa_ld_b((v16i8*)s, 0); 108 ILVRL_B(src0, src1, src2, src3, vec0, vec1, vec2, vec3); 114 src1 = (v16u8)__msa_ld_b((v16i8*)s, 0); 120 ILVRL_B(src0, src1, src2, src3, vec0, vec1, vec2, vec3); 124 src1 = (v16u8)__msa_ld_b((v16i8*)s, 0); 130 ILVRL_B(src0, src1, src2, src3, vec0, vec1, vec2, vec3); 165 v16u8 src0, src1, src local [all...]

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Indexes created Sun Aug 12 02:23:12 CEST 2018