/external/mesa3d/src/gallium/drivers/svga/ |
H A D | svga_state_vdecl.c | 73 unsigned int offset = vb->buffer_offset + ve[i].src_offset; 112 + ve[i].src_offset
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/external/mesa3d/src/gallium/tests/graw/ |
H A D | fs-fragcoord.c | 59 ve[0].src_offset = Offset(struct vertex, position); 61 ve[1].src_offset = Offset(struct vertex, color);
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H A D | fs-frontface.c | 81 ve[0].src_offset = Offset(struct vertex, position); 83 ve[1].src_offset = Offset(struct vertex, color);
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H A D | fs-write-z.c | 85 ve[0].src_offset = Offset(struct vertex, position); 87 ve[1].src_offset = Offset(struct vertex, color);
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H A D | occlusion-query.c | 86 ve[0].src_offset = Offset(struct vertex, position); 88 ve[1].src_offset = Offset(struct vertex, color);
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H A D | quad-tex.c | 48 ve[0].src_offset = Offset(struct vertex, position); 50 ve[1].src_offset = Offset(struct vertex, color);
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H A D | tex-srgb.c | 64 ve[0].src_offset = Offset(struct vertex, position); 66 ve[1].src_offset = Offset(struct vertex, color);
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H A D | tex-swizzle.c | 46 ve[0].src_offset = Offset(struct vertex, position); 48 ve[1].src_offset = Offset(struct vertex, color);
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H A D | tri-large.c | 50 ve[0].src_offset = Offset(struct vertex, position); 52 ve[1].src_offset = Offset(struct vertex, color);
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H A D | tri.c | 47 ve[0].src_offset = Offset(struct vertex, position); 49 ve[1].src_offset = Offset(struct vertex, color);
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/external/mesa3d/src/intel/vulkan/ |
H A D | anv_genX.h | 66 struct anv_bo *src, uint32_t src_offset,
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/external/tensorflow/tensorflow/contrib/lite/toco/graph_transformations/ |
H A D | lstm_utils.cc | 30 int src_offset = src_start_idx1 * src_stride + src_start_idx2; local 34 int idx_src = src_offset + i * src_stride + j;
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/external/mesa3d/src/gallium/auxiliary/draw/ |
H A D | draw_pt_emit.c | 86 unsigned src_offset = vinfo->attrib[i].src_index * 4 * sizeof(float); local 96 src_offset = 0; 101 src_offset = 0; 107 hw_key.element[i].input_offset = src_offset;
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H A D | draw_pipe_vbuf.c | 231 unsigned src_offset = (vinfo->attrib[i].src_index * 4 * sizeof(float) ); local 241 src_offset = 0; 246 src_offset = 0; 252 hw_key.element[i].input_offset = src_offset;
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H A D | draw_pt_fetch.c | 99 key.element[nr].input_offset = draw->pt.vertex_element[ei].src_offset; 110 key.element[nr].input_offset = draw->pt.vertex_element[ei].src_offset; 121 key.element[nr].input_offset = draw->pt.vertex_element[ei].src_offset;
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/external/mesa3d/src/mesa/drivers/dri/i965/ |
H A D | intel_blit.c | 260 uint32_t src_offset, src_tile_x, src_tile_y; local 263 &src_offset, &src_tile_x, &src_tile_y); 273 src_mt->bo, src_mt->offset + src_offset, 479 uintptr_t src_offset, int32_t src_pitch, 510 if ((dst_offset | src_offset) & 63) 576 GLuint src_offset, 623 src_buffer, src_pitch, src_offset, src_x, src_y, 639 src_offset, src_pitch, 697 if (!alignment_valid(brw, src_offset, src_tiling)) 703 if (src_pitch % 4 != 0 || src_offset 476 can_fast_copy_blit(struct brw_context *brw, drm_intel_bo *src_buffer, int16_t src_x, int16_t src_y, uintptr_t src_offset, int32_t src_pitch, uint32_t src_tiling, uint32_t src_tr_mode, drm_intel_bo *dst_buffer, int16_t dst_x, int16_t dst_y, uintptr_t dst_offset, int32_t dst_pitch, uint32_t dst_tiling, uint32_t dst_tr_mode, int16_t w, int16_t h, uint32_t cpp, GLenum logic_op) argument 572 intelEmitCopyBlit(struct brw_context *brw, GLuint cpp, int32_t src_pitch, drm_intel_bo *src_buffer, GLuint src_offset, uint32_t src_tiling, uint32_t src_tr_mode, int32_t dst_pitch, drm_intel_bo *dst_buffer, GLuint dst_offset, uint32_t dst_tiling, uint32_t dst_tr_mode, GLshort src_x, GLshort src_y, GLshort dst_x, GLshort dst_y, GLshort w, GLshort h, GLenum logic_op) argument 852 intel_emit_linear_blit(struct brw_context *brw, drm_intel_bo *dst_bo, unsigned int dst_offset, drm_intel_bo *src_bo, unsigned int src_offset, unsigned int size) argument [all...] |
/external/mesa3d/src/gallium/drivers/r600/ |
H A D | r600_hw_context.c | 442 struct pipe_resource *src, uint64_t src_offset, 457 src_offset += r600_resource(src)->gpu_address; 491 radeon_emit(cs, src_offset); /* SRC_ADDR_LO [31:0] */ 492 radeon_emit(cs, sync | ((src_offset >> 32) & 0xff)); /* CP_SYNC [31] | SRC_ADDR_HI [7:0] */ 503 src_offset += byte_count; 524 uint64_t src_offset, 551 radeon_emit(cs, src_offset & 0xfffffffc); 553 radeon_emit(cs, (src_offset >> 32UL) & 0xff); 555 src_offset += csize << 2; 440 r600_cp_dma_copy_buffer(struct r600_context *rctx, struct pipe_resource *dst, uint64_t dst_offset, struct pipe_resource *src, uint64_t src_offset, unsigned size) argument 520 r600_dma_copy_buffer(struct r600_context *rctx, struct pipe_resource *dst, struct pipe_resource *src, uint64_t dst_offset, uint64_t src_offset, uint64_t size) argument
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/external/mesa3d/src/mesa/drivers/dri/i915/ |
H A D | intel_blit.c | 221 GLuint src_offset, 245 if (src_offset & 4095) 270 src_buffer, src_pitch, src_offset, src_x, src_y, 276 if (src_pitch % 4 != 0 || src_offset % cpp != 0 || 332 src_offset); 597 unsigned int src_offset, 611 pitch, src_bo, src_offset, I915_TILING_NONE, 620 src_offset += pitch * height; 627 pitch, src_bo, src_offset, I915_TILING_NONE, 217 intelEmitCopyBlit(struct intel_context *intel, GLuint cpp, GLshort src_pitch, drm_intel_bo *src_buffer, GLuint src_offset, uint32_t src_tiling, GLshort dst_pitch, drm_intel_bo *dst_buffer, GLuint dst_offset, uint32_t dst_tiling, GLshort src_x, GLshort src_y, GLshort dst_x, GLshort dst_y, GLshort w, GLshort h, GLenum logic_op) argument 593 intel_emit_linear_blit(struct intel_context *intel, drm_intel_bo *dst_bo, unsigned int dst_offset, drm_intel_bo *src_bo, unsigned int src_offset, unsigned int size) argument
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H A D | intel_tex_image.c | 115 GLuint src_offset; local 150 src_buffer = intel_bufferobj_source(intel, pbo, 64, &src_offset); 152 src_offset += (GLuint) (unsigned long) pixels; 161 src_offset,
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/external/pdfium/core/fpdfapi/page/ |
H A D | cpdf_image.cpp | 302 int32_t src_offset = 0; local 305 src_offset = row * src_pitch; 308 pDest[dest_offset] = (uint8_t)(src_buf[src_offset + 2] * alpha); 309 pDest[dest_offset + 1] = (uint8_t)(src_buf[src_offset + 1] * alpha); 310 pDest[dest_offset + 2] = (uint8_t)(src_buf[src_offset] * alpha); 312 src_offset += bpp == 24 ? 3 : 4;
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/external/mesa3d/src/amd/vulkan/ |
H A D | radv_meta_buffer.c | 356 uint64_t src_offset, uint64_t dst_offset, 378 .offset = src_offset, 452 uint64_t src_offset, uint64_t dst_offset, 455 if (size >= 4096 && !(size & 3) && !(src_offset & 3) && !(dst_offset & 3)) 457 src_offset, dst_offset, size); 461 src_va += src_offset; 500 uint64_t src_offset = src_buffer->offset + pRegions[r].srcOffset; local 505 src_offset, dest_offset, copy_size); 353 copy_buffer_shader(struct radv_cmd_buffer *cmd_buffer, struct radeon_winsys_bo *src_bo, struct radeon_winsys_bo *dst_bo, uint64_t src_offset, uint64_t dst_offset, uint64_t size) argument 449 radv_copy_buffer(struct radv_cmd_buffer *cmd_buffer, struct radeon_winsys_bo *src_bo, struct radeon_winsys_bo *dst_bo, uint64_t src_offset, uint64_t dst_offset, uint64_t size) argument
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/external/kernel-headers/original/uapi/drm/ |
H A D | qxl_drm.h | 68 * src_offset) 74 __u64 src_offset; /* offset into src_handle or src buffer */ member in struct:drm_qxl_reloc
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/external/libdrm/include/drm/ |
H A D | qxl_drm.h | 65 * src_offset) 71 uint64_t src_offset; /* offset into src_handle or src buffer */ member in struct:drm_qxl_reloc
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/external/mesa3d/src/gallium/drivers/vc4/ |
H A D | vc4_tiling.c | 87 for (uint32_t src_offset = 0; src_offset < 64; src_offset += src_stride) { 88 memcpy(dst, src + src_offset, src_stride);
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/external/mesa3d/src/mesa/drivers/dri/radeon/ |
H A D | radeon_blit.c | 314 * @param[in] src_offset offset of the source image in the @a src_bo 335 intptr_t src_offset, 380 if (src_offset % 32 || dst_offset % 32) { 387 src_width, src_height, src_pitch, src_offset, 408 emit_tx_setup(r100, src_mesaformat, src_bo, src_offset, src_width, src_height, src_pitch); 333 r100_blit(struct gl_context *ctx, struct radeon_bo *src_bo, intptr_t src_offset, mesa_format src_mesaformat, unsigned src_pitch, unsigned src_width, unsigned src_height, unsigned src_x_offset, unsigned src_y_offset, struct radeon_bo *dst_bo, intptr_t dst_offset, mesa_format dst_mesaformat, unsigned dst_pitch, unsigned dst_width, unsigned dst_height, unsigned dst_x_offset, unsigned dst_y_offset, unsigned reg_width, unsigned reg_height, unsigned flip_y) argument
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