Searched refs:src1 (Results 201 - 225 of 339) sorted by relevance

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/external/mesa3d/src/mesa/program/
H A Dprogram_parse.y85 const struct asm_src_register *src1, const struct asm_src_register *src2);
89 const struct asm_src_register *src1, const struct asm_src_register *src2);
93 const struct asm_src_register *src0, const struct asm_src_register *src1,
2064 const struct asm_src_register *src1,
2083 if (src1 != NULL) {
2084 inst->Base.SrcReg[1] = src1->Base;
2085 inst->SrcReg[1] = *src1;
2103 const struct asm_src_register *src1,
2112 asm_instruction_set_operands(inst, dst, src0, src1, src2);
2123 const struct asm_src_register *src1,
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/external/libvpx/libvpx/vpx_dsp/x86/
H A Dinv_wht_sse2.asm71 %macro ADD_STORE_4P_2X 5 ; src1, src2, tmp1, tmp2, zero
H A Dvariance_avx2.c54 const __m256i src1 = _mm256_cvtepu8_epi16( local
61 const __m256i diff1 = _mm256_sub_epi16(src1, ref1);
109 const __m256i src1 = local
118 const __m256i src_ref2 = _mm256_unpacklo_epi8(src1, ref1);
119 const __m256i src_ref3 = _mm256_unpackhi_epi8(src1, ref1);
/external/llvm/lib/Target/AMDGPU/
H A DR600ExpandSpecialInstrs.cpp109 AMDGPU::ZERO); // src1
226 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1))
280 int Src1Idx = TII->getOperandIdx(MI, AMDGPU::OpName::src1);
H A DSIShrinkInstructions.cpp106 const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1);
382 TII->getNamedOperand(MI, AMDGPU::OpName::src1);
/external/mesa3d/src/amd/common/
H A Dac_nir_to_llvm.c722 LLVMValueRef src1)
724 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
732 LLVMValueRef src1)
736 src1 = to_float(ctx, src1);
737 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
755 LLVMValueRef src0, LLVMValueRef src1)
759 to_float(ctx, src1),
766 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
770 to_float(ctx, src1),
720 emit_int_cmp(struct nir_to_llvm_context *ctx, LLVMIntPredicate pred, LLVMValueRef src0, LLVMValueRef src1) argument
730 emit_float_cmp(struct nir_to_llvm_context *ctx, LLVMRealPredicate pred, LLVMValueRef src0, LLVMValueRef src1) argument
753 emit_intrin_2f_param(struct nir_to_llvm_context *ctx, const char *intrin, LLVMValueRef src0, LLVMValueRef src1) argument
764 emit_intrin_3f_param(struct nir_to_llvm_context *ctx, const char *intrin, LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2) argument
776 emit_bcsel(struct nir_to_llvm_context *ctx, LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2) argument
846 emit_minmax_int(struct nir_to_llvm_context *ctx, LLVMIntPredicate pred, LLVMValueRef src0, LLVMValueRef src1) argument
901 emit_uint_carry(struct nir_to_llvm_context *ctx, const char *intrin, LLVMValueRef src0, LLVMValueRef src1) argument
926 emit_umul_high(struct nir_to_llvm_context *ctx, LLVMValueRef src0, LLVMValueRef src1) argument
939 emit_imul_high(struct nir_to_llvm_context *ctx, LLVMValueRef src0, LLVMValueRef src1) argument
964 emit_bitfield_insert(struct nir_to_llvm_context *ctx, LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2, LLVMValueRef src3) argument
2656 LLVMValueRef src1 = get_src(ctx, instr->src[1]); local
3969 emit_pack_int16(struct nir_to_llvm_context *ctx, LLVMValueRef src0, LLVMValueRef src1) argument
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/external/mesa3d/src/compiler/nir/
H A Dnir_lower_wpos_ytransform.c72 nir_cmp(nir_builder *b, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2) argument
74 return nir_bcsel(b, nir_flt(b, src0, nir_imm_float(b, 0.0)), src1, src2);
/external/mesa3d/src/mesa/drivers/dri/i965/
H A Dbrw_ir_fs.h332 const fs_reg &src0, const fs_reg &src1);
334 const fs_reg &src0, const fs_reg &src1, const fs_reg &src2);
H A Dbrw_fs_generator.cpp548 * | src1+0 | src1+1 | src1+2 | src1+3 |
556 * | src1+0 | src1+1 | src1+2 | src1+3 |
1008 struct brw_reg src1 = brw_reg(src.file, src.nr, 0, local
1015 brw_ADD(p, dst, src0, negate(src1));
1035 struct brw_reg src1 = brw_reg(src.file, src.nr, 0, local
1055 struct brw_reg src1 = brw_reg(src.file, src.nr, 2, local
1390 generate_set_sample_id(fs_inst *inst, struct brw_reg dst, struct brw_reg src0, struct brw_reg src1) argument
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/external/webrtc/webrtc/modules/video_processing/util/
H A Ddenoiser_filter_sse2.cc34 const __m128i src1 = _mm_unpacklo_epi8( local
38 const __m128i diff1 = _mm_sub_epi16(src1, ref1);
/external/mesa3d/src/intel/blorp/
H A Dblorp_blit.c1325 GLfloat src0, GLfloat src1,
1329 double scale = (double)(src1 - src0) / (double)(dst1 - dst0);
1536 double src0, src1, dst0, dst1; member in struct:blt_axis
1655 coords->x.src0, coords->x.src1,
1659 coords->y.src0, coords->y.src1,
1850 * src0 uses delta0, and src1 uses delta1. When scale is less than 0, the
1852 * delta1, and src1 is adjusted by delta0.
1857 split_coords->src1 = orig->src1 + (scale >= 0.0 ? delta1 : delta0);
1924 shrink_surface_params(dev, &params->src, &coords->x.src0, &coords->x.src1,
1324 brw_blorp_setup_coord_transform(struct brw_blorp_coord_transform *xform, GLfloat src0, GLfloat src1, GLfloat dst0, GLfloat dst1, bool mirror) argument
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/external/v8/src/mips64/
H A Dmacro-assembler-mips64.cc94 Register src1, const Operand& src2) {
95 Branch(2, NegateCondition(cond), src1, src2);
110 Register src1, const Operand& src2) {
112 Branch(2, NegateCondition(cond), src1, src2);
4603 void MacroAssembler::MovToFloatParameters(DoubleRegister src1,
4608 DCHECK(!src1.is(fparg2));
4610 Move(f12, src1);
4612 Move(f12, src1);
4617 Move(a0, a1, src1);
4620 Move(a1, a0, src1);
91 LoadRoot(Register destination, Heap::RootListIndex index, Condition cond, Register src1, const Operand& src2) argument
107 StoreRoot(Register source, Heap::RootListIndex index, Condition cond, Register src1, const Operand& src2) argument
6183 Float32Max(FPURegister dst, FPURegister src1, FPURegister src2, Label* out_of_line) argument
6222 Float32MaxOutOfLine(FPURegister dst, FPURegister src1, FPURegister src2) argument
6227 Float32Min(FPURegister dst, FPURegister src1, FPURegister src2, Label* out_of_line) argument
6266 Float32MinOutOfLine(FPURegister dst, FPURegister src1, FPURegister src2) argument
6271 Float64Max(FPURegister dst, FPURegister src1, FPURegister src2, Label* out_of_line) argument
6309 Float64MaxOutOfLine(FPURegister dst, FPURegister src1, FPURegister src2) argument
6314 Float64Min(FPURegister dst, FPURegister src1, FPURegister src2, Label* out_of_line) argument
6352 Float64MinOutOfLine(FPURegister dst, FPURegister src1, FPURegister src2) argument
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/external/mesa3d/src/gallium/drivers/r300/compiler/
H A Dradeon_program_alu.c279 struct rc_src_register src1 = inst->U.I.SrcReg[1]; local
283 src1.Negate &= ~(RC_MASK_Z | RC_MASK_W);
284 src1.Swizzle &= ~(63 << (3 * 2));
285 src1.Swizzle |= (RC_SWIZZLE_ZERO << (3 * 2)) | (RC_SWIZZLE_ZERO << (3 * 3));
286 emit2(c, inst->Prev, RC_OPCODE_DP3, &inst->U.I, inst->U.I.DstReg, src0, src1);
302 * [1, src0.y*src1.y, src0.z, src1.w]
708 * CMP is defined as dst = src0 < 0.0 ? src1 : src2
714 * LRP dst, tmp0, src1, src2
724 /* LRP dst, tmp0, src1, src
745 struct rc_src_register src1 = inst->U.I.SrcReg[1]; local
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/external/opencv/cv/src/
H A Dcvsmooth.cpp826 const uchar* src1 = src0 + src_step;
827 const uchar* src2 = src1 + src_step;
829 src0 = src1;
831 src2 = src1;
840 int p3 = src1[x0], p4 = src1[x1], p5 = src1[x2];
859 int p3 = src1[x-cn], p4 = src1[x], p5 = src1[
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H A D_cvipp.h111 ( const arrtype* src1, int srcstep1, const arrtype* src2, int srcstep2, \
128 ( const arrtype* src1, int srcstep1, const arrtype* src2, int srcstep2, \
145 ( const arrtype* src1, int srcstep1, const arrtype* src2, int srcstep2, \
619 ( const uchar* src1, int srcstep1, uchar scalar,
623 ( const uchar* src1, int srcstep1, uchar scalar,
/external/vixl/src/aarch64/
H A Dmacro-assembler-aarch64.cc1951 const CPURegister& src1,
1955 VIXL_ASSERT(AreSameSizeAndType(src0, src1, src2, src3));
1958 int count = 1 + src1.IsValid() + src2.IsValid() + src3.IsValid();
1962 PushHelper(count, size, src0, src1, src2, src3);
2006 const CPURegister& src1 = registers.PopLowestIndex(); local
2007 if (src1.IsValid()) {
2008 Stp(src0, src1, MemOperand(StackPointer(), offset));
2078 const CPURegister& src1,
2087 VIXL_ASSERT(AreSameSizeAndType(src0, src1, src2, src3));
2094 VIXL_ASSERT(src1
1950 Push(const CPURegister& src0, const CPURegister& src1, const CPURegister& src2, const CPURegister& src3) argument
2075 PushHelper(int count, int size, const CPURegister& src0, const CPURegister& src1, const CPURegister& src2, const CPURegister& src3) argument
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/external/mesa3d/src/gallium/drivers/ilo/shader/
H A Dilo_shader_fs.c756 * src1 := ddx
763 * src1 := (v or bias or lod, ...)
769 * src1 := sampler
774 * src1 := sampler
783 * src1 := sampler
923 struct toy_src src1[4]; local
924 tsrc_transpose(inst->src[1], src1);
925 ref_or_si = src1[ref_pos - 4];
949 struct toy_src src1[4]; local
950 tsrc_transpose(inst->src[1], src1);
968 struct toy_src src1[4]; local
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/external/mesa3d/src/gallium/drivers/swr/rasterizer/memory/
H A DStoreTile.h661 simd16scalari src1 = _simd16_cvtps_epi32(comp1); // padded byte gggggggggggggggg local
666 src1 = _simd16_slli_epi32(src1, 8);
670 simd16scalari final = _simd16_or_si(_simd16_or_si(src0, src1), _simd16_or_si(src2, src3)); // 0 1 2 3 4 5 6 7 8 9 A B C D E F
731 __m256i src1 = _simd_cvtps_epi32(vComp1); // padded byte gggggggg local
740 __m128i srcLo1 = _mm256_castsi256_si128(src1); // 000g000g000g000g
745 __m128i srcHi1 = _mm256_extractf128_si256(src1, 1); // 000g000g000g000g
775 src1 = _mm256_slli_si256(src1, 1);
779 src0 = _mm256_or_si256(src0, src1);
835 simd16scalari src1 = _simd16_cvtps_epi32(comp1); // padded byte gggggggggggggggg local
897 __m256i src1 = _simd_cvtps_epi32(vComp1); // padded byte gggggggg local
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/external/capstone/arch/AArch64/
H A DAArch64GenAsmWriter.inc7104 // (ADDSWrs WZR, GPR32:$src1, GPR32:$src2, 0)
7114 // (ADDSWrs WZR, GPR32:$src1, GPR32:$src2, arith_shift32:$sh)
7127 // (ADDSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0)
7141 // (ADDSWrx WZR, GPR32sponly:$src1, GPR32:$src2, 16)
7151 // (ADDSWrx WZR, GPR32sp:$src1, GPR32:$src2, arith_extend:$sh)
7164 // (ADDSWrx GPR32:$dst, GPR32sponly:$src1, GPR32:$src2, 16)
7188 // (ADDSXrs XZR, GPR64:$src1, GPR64:$src2, 0)
7198 // (ADDSXrs XZR, GPR64:$src1, GPR64:$src2, arith_shift64:$sh)
7211 // (ADDSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0)
7223 // (ADDSXrx XZR, GPR64sp:$src1, GPR3
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/external/mesa3d/src/compiler/glsl/
H A Dir_expression_operation.py398 src1 = "op[1]->value.{0}[{1}]".format(types[1].union_field, indices[1]) if len(types) >= 2 else "ERROR"
405 src1=src1,
546 operation("add", 2, printable_name="+", source_types=numeric_types, c_expression="{src0} + {src1}", flags=vector_scalar_operation),
547 operation("sub", 2, printable_name="-", source_types=numeric_types, c_expression="{src0} - {src1}", flags=vector_scalar_operation),
549 operation("mul", 2, printable_name="*", source_types=numeric_types, c_expression="{src0} * {src1}"),
551 operation("div", 2, printable_name="/", source_types=numeric_types, c_expression={'u': "{src1} == 0 ? 0 : {src0} / {src1}", 'i': "{src1} == 0 ? 0 : {src0} / {src1}", 'defaul
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/external/mesa3d/src/gallium/drivers/vc4/
H A Dvc4_qir.h561 struct qreg src0, struct qreg src1);
748 qir_SEL(struct vc4_compile *c, uint8_t cond, struct qreg src0, struct qreg src1) argument
751 qir_MOV_dest(c, t, src1);
/external/opencv/cv/include/
H A Dcvcompat.h363 #define cvmAdd( src1, src2, dst ) cvAdd( src1, src2, dst, 0 )
364 #define cvmSub( src1, src2, dst ) cvSub( src1, src2, dst, 0 )
366 #define cvmMul( src1, src2, dst ) cvMatMulAdd( src1, src2, 0, dst )
/external/v8/src/x64/
H A Dassembler-x64.cc3957 void Assembler::vfmasd(byte op, XMMRegister dst, XMMRegister src1, argument
3961 emit_vex_prefix(dst, src1, src2, kLIG, k66, k0F38, kW1);
3967 void Assembler::vfmasd(byte op, XMMRegister dst, XMMRegister src1, argument
3971 emit_vex_prefix(dst, src1, src2, kLIG, k66, k0F38, kW1);
3977 void Assembler::vfmass(byte op, XMMRegister dst, XMMRegister src1, argument
3981 emit_vex_prefix(dst, src1, src2, kLIG, k66, k0F38, kW0);
3987 void Assembler::vfmass(byte op, XMMRegister dst, XMMRegister src1, argument
3991 emit_vex_prefix(dst, src1, src2, kLIG, k66, k0F38, kW0);
4054 void Assembler::vinstr(byte op, XMMRegister dst, XMMRegister src1, argument
4059 emit_vex_prefix(dst, src1, src
4064 vinstr(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2, SIMDPrefix pp, LeadingOpcode m, VexW w) argument
4075 vps(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2) argument
4085 vps(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2) argument
4095 vpd(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2) argument
4105 vpd(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2) argument
4133 vss(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2) argument
4143 vss(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2) argument
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/external/v8/src/crankshaft/x87/
H A Dlithium-gap-resolver-x87.cc342 Operand src1 = cgen_->HighOperand(source); local
347 __ mov(tmp, src1);
/external/v8/src/arm64/
H A Dmacro-assembler-arm64.cc868 void MacroAssembler::Push(const CPURegister& src0, const CPURegister& src1, argument
870 DCHECK(AreSameSizeAndType(src0, src1, src2, src3));
872 int count = 1 + src1.IsValid() + src2.IsValid() + src3.IsValid();
876 PushHelper(count, size, src0, src1, src2, src3);
880 void MacroAssembler::Push(const CPURegister& src0, const CPURegister& src1, argument
884 DCHECK(AreSameSizeAndType(src0, src1, src2, src3, src4, src5, src6, src7));
890 PushHelper(4, size, src0, src1, src2, src3);
930 void MacroAssembler::Push(const Register& src0, const FPRegister& src1) { argument
931 int size = src0.SizeInBytes() + src1.SizeInBytes();
934 // Reserve room for src0 and push src1
1003 const CPURegister& src1 = registers.PopHighestIndex(); local
1115 PushHelper(int count, int size, const CPURegister& src0, const CPURegister& src1, const CPURegister& src2, const CPURegister& src3) argument
1260 PokePair(const CPURegister& src1, const CPURegister& src2, int offset) argument
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